2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
44 #include <linux/workqueue.h>
45 #include <linux/interrupt.h>
47 #include <linux/mlx5/device.h>
48 #include <linux/mlx5/doorbell.h>
51 MLX5_RQ_BITMASK_VSD
= 1 << 1,
55 MLX5_BOARD_ID_LEN
= 64,
56 MLX5_MAX_NAME_LEN
= 16,
60 /* one minute for the sake of bringup. Generally, commands must always
61 * complete and we may need to increase this timeout value
63 MLX5_CMD_TIMEOUT_MSEC
= 60 * 1000,
64 MLX5_CMD_WQ_MAX_NAME
= 32,
70 CMD_STATUS_SUCCESS
= 0,
76 MLX5_SQP_IEEE_1588
= 2,
78 MLX5_SQP_SYNC_UMR
= 4,
86 MLX5_EQ_VEC_PAGES
= 0,
88 MLX5_EQ_VEC_ASYNC
= 2,
89 MLX5_EQ_VEC_COMP_BASE
,
93 MLX5_MAX_IRQ_NAME
= 32
97 MLX5_ATOMIC_MODE_IB_COMP
= 1 << 16,
98 MLX5_ATOMIC_MODE_CX
= 2 << 16,
99 MLX5_ATOMIC_MODE_8B
= 3 << 16,
100 MLX5_ATOMIC_MODE_16B
= 4 << 16,
101 MLX5_ATOMIC_MODE_32B
= 5 << 16,
102 MLX5_ATOMIC_MODE_64B
= 6 << 16,
103 MLX5_ATOMIC_MODE_128B
= 7 << 16,
104 MLX5_ATOMIC_MODE_256B
= 8 << 16,
108 MLX5_REG_QETCR
= 0x4005,
109 MLX5_REG_QTCT
= 0x400a,
110 MLX5_REG_PCAP
= 0x5001,
111 MLX5_REG_PMTU
= 0x5003,
112 MLX5_REG_PTYS
= 0x5004,
113 MLX5_REG_PAOS
= 0x5006,
114 MLX5_REG_PFCC
= 0x5007,
115 MLX5_REG_PPCNT
= 0x5008,
116 MLX5_REG_PMAOS
= 0x5012,
117 MLX5_REG_PUDE
= 0x5009,
118 MLX5_REG_PMPE
= 0x5010,
119 MLX5_REG_PELC
= 0x500e,
120 MLX5_REG_PVLC
= 0x500f,
121 MLX5_REG_PCMR
= 0x5041,
122 MLX5_REG_PMLP
= 0x5002,
123 MLX5_REG_NODE_DESC
= 0x6001,
124 MLX5_REG_HOST_ENDIANNESS
= 0x7004,
125 MLX5_REG_MCIA
= 0x9014,
126 MLX5_REG_MLCR
= 0x902b,
130 MLX5_ATOMIC_OPS_CMP_SWAP
= 1 << 0,
131 MLX5_ATOMIC_OPS_FETCH_ADD
= 1 << 1,
134 enum mlx5_page_fault_resume_flags
{
135 MLX5_PAGE_FAULT_RESUME_REQUESTOR
= 1 << 0,
136 MLX5_PAGE_FAULT_RESUME_WRITE
= 1 << 1,
137 MLX5_PAGE_FAULT_RESUME_RDMA
= 1 << 2,
138 MLX5_PAGE_FAULT_RESUME_ERROR
= 1 << 7,
147 struct mlx5_field_desc
{
152 struct mlx5_rsc_debug
{
153 struct mlx5_core_dev
*dev
;
155 enum dbg_rsc_type type
;
157 struct mlx5_field_desc fields
[0];
160 enum mlx5_dev_event
{
161 MLX5_DEV_EVENT_SYS_ERROR
,
162 MLX5_DEV_EVENT_PORT_UP
,
163 MLX5_DEV_EVENT_PORT_DOWN
,
164 MLX5_DEV_EVENT_PORT_INITIALIZED
,
165 MLX5_DEV_EVENT_LID_CHANGE
,
166 MLX5_DEV_EVENT_PKEY_CHANGE
,
167 MLX5_DEV_EVENT_GUID_CHANGE
,
168 MLX5_DEV_EVENT_CLIENT_REREG
,
171 enum mlx5_port_status
{
176 struct mlx5_uuar_info
{
177 struct mlx5_uar
*uars
;
179 int num_low_latency_uuars
;
180 unsigned long *bitmap
;
185 * protect uuar allocation data structs
193 void __iomem
*regreg
;
195 struct mlx5_uar
*uar
;
196 unsigned long offset
;
198 /* protect blue flame buffer selection when needed
202 /* serialize 64 bit writes when done as two 32 bit accesses
208 struct mlx5_cmd_first
{
212 struct mlx5_cmd_msg
{
213 struct list_head list
;
214 struct cache_ent
*cache
;
216 struct mlx5_cmd_first first
;
217 struct mlx5_cmd_mailbox
*next
;
220 struct mlx5_cmd_debug
{
221 struct dentry
*dbg_root
;
222 struct dentry
*dbg_in
;
223 struct dentry
*dbg_out
;
224 struct dentry
*dbg_outlen
;
225 struct dentry
*dbg_status
;
226 struct dentry
*dbg_run
;
235 /* protect block chain allocations
238 struct list_head head
;
241 struct cmd_msg_cache
{
242 struct cache_ent large
;
243 struct cache_ent med
;
247 struct mlx5_cmd_stats
{
252 struct dentry
*count
;
253 /* protect command average calculations */
259 dma_addr_t alloc_dma
;
270 /* protect command queue allocations
272 spinlock_t alloc_lock
;
274 /* protect token allocations
276 spinlock_t token_lock
;
278 unsigned long bitmask
;
279 char wq_name
[MLX5_CMD_WQ_MAX_NAME
];
280 struct workqueue_struct
*wq
;
281 struct semaphore sem
;
282 struct semaphore pages_sem
;
284 struct mlx5_cmd_work_ent
*ent_arr
[MLX5_MAX_COMMANDS
];
285 struct pci_pool
*pool
;
286 struct mlx5_cmd_debug dbg
;
287 struct cmd_msg_cache cache
;
288 int checksum_disabled
;
289 struct mlx5_cmd_stats stats
[MLX5_CMD_OP_MAX
];
292 struct mlx5_port_caps
{
298 struct mlx5_cmd_mailbox
{
301 struct mlx5_cmd_mailbox
*next
;
304 struct mlx5_buf_list
{
310 struct mlx5_buf_list direct
;
316 struct mlx5_eq_tasklet
{
317 struct list_head list
;
318 struct list_head process_list
;
319 struct tasklet_struct task
;
320 /* lock on completion tasklet list */
325 struct mlx5_core_dev
*dev
;
326 __be32 __iomem
*doorbell
;
334 struct list_head list
;
336 struct mlx5_rsc_debug
*dbg
;
337 struct mlx5_eq_tasklet tasklet_ctx
;
340 struct mlx5_core_psv
{
352 struct mlx5_core_sig_ctx
{
353 struct mlx5_core_psv psv_memory
;
354 struct mlx5_core_psv psv_wire
;
355 struct ib_sig_err err_item
;
356 bool sig_status_checked
;
361 struct mlx5_core_mkey
{
369 MLX5_RES_QP
= MLX5_EVENT_QUEUE_TYPE_QP
,
370 MLX5_RES_RQ
= MLX5_EVENT_QUEUE_TYPE_RQ
,
371 MLX5_RES_SQ
= MLX5_EVENT_QUEUE_TYPE_SQ
,
376 struct mlx5_core_rsc_common
{
377 enum mlx5_res_type res
;
379 struct completion free
;
382 struct mlx5_core_srq
{
383 struct mlx5_core_rsc_common common
; /* must be first */
387 int max_avail_gather
;
389 void (*event
) (struct mlx5_core_srq
*, enum mlx5_event
);
392 struct completion free
;
395 struct mlx5_eq_table
{
396 void __iomem
*update_ci
;
397 void __iomem
*update_arm_ci
;
398 struct list_head comp_eqs_list
;
399 struct mlx5_eq pages_eq
;
400 struct mlx5_eq async_eq
;
401 struct mlx5_eq cmd_eq
;
402 int num_comp_vectors
;
410 struct list_head bf_list
;
411 unsigned free_bf_bmap
;
412 void __iomem
*bf_map
;
417 struct mlx5_core_health
{
418 struct health_buffer __iomem
*health
;
419 __be32 __iomem
*health_counter
;
420 struct timer_list timer
;
424 struct workqueue_struct
*wq
;
425 struct work_struct work
;
428 struct mlx5_cq_table
{
429 /* protect radix tree
432 struct radix_tree_root tree
;
435 struct mlx5_qp_table
{
436 /* protect radix tree
439 struct radix_tree_root tree
;
442 struct mlx5_srq_table
{
443 /* protect radix tree
446 struct radix_tree_root tree
;
449 struct mlx5_mkey_table
{
450 /* protect radix tree
453 struct radix_tree_root tree
;
456 struct mlx5_vf_context
{
460 struct mlx5_core_sriov
{
461 struct mlx5_vf_context
*vfs_ctx
;
466 struct mlx5_irq_info
{
468 char name
[MLX5_MAX_IRQ_NAME
];
471 struct mlx5_fc_stats
{
472 struct list_head list
;
473 struct list_head addlist
;
474 /* protect addlist add/splice operations */
475 spinlock_t addlist_lock
;
477 struct workqueue_struct
*wq
;
478 struct delayed_work work
;
479 unsigned long next_query
;
485 char name
[MLX5_MAX_NAME_LEN
];
486 struct mlx5_eq_table eq_table
;
487 struct msix_entry
*msix_arr
;
488 struct mlx5_irq_info
*irq_info
;
489 struct mlx5_uuar_info uuari
;
490 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock
);
493 struct workqueue_struct
*pg_wq
;
494 struct rb_root page_root
;
497 struct list_head free_list
;
500 struct mlx5_core_health health
;
502 struct mlx5_srq_table srq_table
;
504 /* start: qp staff */
505 struct mlx5_qp_table qp_table
;
506 struct dentry
*qp_debugfs
;
507 struct dentry
*eq_debugfs
;
508 struct dentry
*cq_debugfs
;
509 struct dentry
*cmdif_debugfs
;
512 /* start: cq staff */
513 struct mlx5_cq_table cq_table
;
516 /* start: mkey staff */
517 struct mlx5_mkey_table mkey_table
;
518 /* end: mkey staff */
520 /* start: alloc staff */
521 /* protect buffer alocation according to numa node */
522 struct mutex alloc_mutex
;
525 struct mutex pgdir_mutex
;
526 struct list_head pgdir_list
;
527 /* end: alloc staff */
528 struct dentry
*dbg_root
;
530 /* protect mkey key part */
531 spinlock_t mkey_lock
;
534 struct list_head dev_list
;
535 struct list_head ctx_list
;
538 struct mlx5_eswitch
*eswitch
;
539 struct mlx5_core_sriov sriov
;
540 unsigned long pci_dev_data
;
541 struct mlx5_flow_root_namespace
*root_ns
;
542 struct mlx5_flow_root_namespace
*fdb_root_ns
;
543 struct mlx5_flow_root_namespace
*esw_egress_root_ns
;
544 struct mlx5_flow_root_namespace
*esw_ingress_root_ns
;
546 struct mlx5_fc_stats fc_stats
;
549 enum mlx5_device_state
{
550 MLX5_DEVICE_STATE_UP
,
551 MLX5_DEVICE_STATE_INTERNAL_ERROR
,
554 enum mlx5_interface_state
{
555 MLX5_INTERFACE_STATE_DOWN
= BIT(0),
556 MLX5_INTERFACE_STATE_UP
= BIT(1),
557 MLX5_INTERFACE_STATE_SHUTDOWN
= BIT(2),
560 enum mlx5_pci_status
{
561 MLX5_PCI_STATUS_DISABLED
,
562 MLX5_PCI_STATUS_ENABLED
,
565 struct mlx5_core_dev
{
566 struct pci_dev
*pdev
;
568 struct mutex pci_status_mutex
;
569 enum mlx5_pci_status pci_status
;
571 char board_id
[MLX5_BOARD_ID_LEN
];
573 struct mlx5_port_caps port_caps
[MLX5_MAX_PORTS
];
574 u32 hca_caps_cur
[MLX5_CAP_NUM
][MLX5_UN_SZ_DW(hca_cap_union
)];
575 u32 hca_caps_max
[MLX5_CAP_NUM
][MLX5_UN_SZ_DW(hca_cap_union
)];
576 phys_addr_t iseg_base
;
577 struct mlx5_init_seg __iomem
*iseg
;
578 enum mlx5_device_state state
;
579 /* sync interface state */
580 struct mutex intf_state_mutex
;
581 unsigned long intf_state
;
582 void (*event
) (struct mlx5_core_dev
*dev
,
583 enum mlx5_dev_event event
,
584 unsigned long param
);
585 struct mlx5_priv priv
;
586 struct mlx5_profile
*profile
;
589 #ifdef CONFIG_RFS_ACCEL
590 struct cpu_rmap
*rmap
;
597 struct mlx5_db_pgdir
*pgdir
;
598 struct mlx5_ib_user_db_page
*user_page
;
605 MLX5_DB_PER_PAGE
= PAGE_SIZE
/ L1_CACHE_BYTES
,
609 MLX5_COMP_EQ_SIZE
= 1024,
613 MLX5_PTYS_IB
= 1 << 0,
614 MLX5_PTYS_EN
= 1 << 2,
617 struct mlx5_db_pgdir
{
618 struct list_head list
;
619 DECLARE_BITMAP(bitmap
, MLX5_DB_PER_PAGE
);
624 typedef void (*mlx5_cmd_cbk_t
)(int status
, void *context
);
626 struct mlx5_cmd_work_ent
{
627 struct mlx5_cmd_msg
*in
;
628 struct mlx5_cmd_msg
*out
;
631 mlx5_cmd_cbk_t callback
;
632 struct delayed_work cb_timeout_work
;
635 struct completion done
;
636 struct mlx5_cmd
*cmd
;
637 struct work_struct work
;
638 struct mlx5_cmd_layout
*lay
;
653 enum port_state_policy
{
654 MLX5_POLICY_DOWN
= 0,
656 MLX5_POLICY_FOLLOW
= 2,
657 MLX5_POLICY_INVALID
= 0xffffffff
660 enum phy_port_state
{
664 struct mlx5_hca_vport_context
{
669 enum port_state_policy policy
;
670 enum phy_port_state phys_state
;
671 enum ib_port_state vport_state
;
672 u8 port_physical_state
;
681 u8 init_type_reply
; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
686 u16 qkey_violation_counter
;
687 u16 pkey_violation_counter
;
691 static inline void *mlx5_buf_offset(struct mlx5_buf
*buf
, int offset
)
693 return buf
->direct
.buf
+ offset
;
696 extern struct workqueue_struct
*mlx5_core_wq
;
698 #define STRUCT_FIELD(header, field) \
699 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
700 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
702 static inline struct mlx5_core_dev
*pci2mlx5_core_dev(struct pci_dev
*pdev
)
704 return pci_get_drvdata(pdev
);
707 extern struct dentry
*mlx5_debugfs_root
;
709 static inline u16
fw_rev_maj(struct mlx5_core_dev
*dev
)
711 return ioread32be(&dev
->iseg
->fw_rev
) & 0xffff;
714 static inline u16
fw_rev_min(struct mlx5_core_dev
*dev
)
716 return ioread32be(&dev
->iseg
->fw_rev
) >> 16;
719 static inline u16
fw_rev_sub(struct mlx5_core_dev
*dev
)
721 return ioread32be(&dev
->iseg
->cmdif_rev_fw_sub
) & 0xffff;
724 static inline u16
cmdif_rev(struct mlx5_core_dev
*dev
)
726 return ioread32be(&dev
->iseg
->cmdif_rev_fw_sub
) >> 16;
729 static inline void *mlx5_vzalloc(unsigned long size
)
733 rtn
= kzalloc(size
, GFP_KERNEL
| __GFP_NOWARN
);
739 static inline u32
mlx5_base_mkey(const u32 key
)
741 return key
& 0xffffff00u
;
744 int mlx5_cmd_init(struct mlx5_core_dev
*dev
);
745 void mlx5_cmd_cleanup(struct mlx5_core_dev
*dev
);
746 void mlx5_cmd_use_events(struct mlx5_core_dev
*dev
);
747 void mlx5_cmd_use_polling(struct mlx5_core_dev
*dev
);
748 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr
*hdr
);
749 int mlx5_cmd_status_to_err_v2(void *ptr
);
750 int mlx5_core_get_caps(struct mlx5_core_dev
*dev
, enum mlx5_cap_type cap_type
);
751 int mlx5_cmd_exec(struct mlx5_core_dev
*dev
, void *in
, int in_size
, void *out
,
753 int mlx5_cmd_exec_cb(struct mlx5_core_dev
*dev
, void *in
, int in_size
,
754 void *out
, int out_size
, mlx5_cmd_cbk_t callback
,
756 int mlx5_cmd_alloc_uar(struct mlx5_core_dev
*dev
, u32
*uarn
);
757 int mlx5_cmd_free_uar(struct mlx5_core_dev
*dev
, u32 uarn
);
758 int mlx5_alloc_uuars(struct mlx5_core_dev
*dev
, struct mlx5_uuar_info
*uuari
);
759 int mlx5_free_uuars(struct mlx5_core_dev
*dev
, struct mlx5_uuar_info
*uuari
);
760 int mlx5_alloc_map_uar(struct mlx5_core_dev
*mdev
, struct mlx5_uar
*uar
,
762 void mlx5_unmap_free_uar(struct mlx5_core_dev
*mdev
, struct mlx5_uar
*uar
);
763 void mlx5_health_cleanup(struct mlx5_core_dev
*dev
);
764 int mlx5_health_init(struct mlx5_core_dev
*dev
);
765 void mlx5_start_health_poll(struct mlx5_core_dev
*dev
);
766 void mlx5_stop_health_poll(struct mlx5_core_dev
*dev
);
767 int mlx5_buf_alloc_node(struct mlx5_core_dev
*dev
, int size
,
768 struct mlx5_buf
*buf
, int node
);
769 int mlx5_buf_alloc(struct mlx5_core_dev
*dev
, int size
, struct mlx5_buf
*buf
);
770 void mlx5_buf_free(struct mlx5_core_dev
*dev
, struct mlx5_buf
*buf
);
771 struct mlx5_cmd_mailbox
*mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev
*dev
,
772 gfp_t flags
, int npages
);
773 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev
*dev
,
774 struct mlx5_cmd_mailbox
*head
);
775 int mlx5_core_create_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
776 struct mlx5_create_srq_mbox_in
*in
, int inlen
,
778 int mlx5_core_destroy_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
);
779 int mlx5_core_query_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
780 struct mlx5_query_srq_mbox_out
*out
);
781 int mlx5_core_arm_srq(struct mlx5_core_dev
*dev
, struct mlx5_core_srq
*srq
,
782 u16 lwm
, int is_srq
);
783 void mlx5_init_mkey_table(struct mlx5_core_dev
*dev
);
784 void mlx5_cleanup_mkey_table(struct mlx5_core_dev
*dev
);
785 int mlx5_core_create_mkey(struct mlx5_core_dev
*dev
,
786 struct mlx5_core_mkey
*mkey
,
787 struct mlx5_create_mkey_mbox_in
*in
, int inlen
,
788 mlx5_cmd_cbk_t callback
, void *context
,
789 struct mlx5_create_mkey_mbox_out
*out
);
790 int mlx5_core_destroy_mkey(struct mlx5_core_dev
*dev
,
791 struct mlx5_core_mkey
*mkey
);
792 int mlx5_core_query_mkey(struct mlx5_core_dev
*dev
, struct mlx5_core_mkey
*mkey
,
793 struct mlx5_query_mkey_mbox_out
*out
, int outlen
);
794 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev
*dev
, struct mlx5_core_mkey
*_mkey
,
796 int mlx5_core_alloc_pd(struct mlx5_core_dev
*dev
, u32
*pdn
);
797 int mlx5_core_dealloc_pd(struct mlx5_core_dev
*dev
, u32 pdn
);
798 int mlx5_core_mad_ifc(struct mlx5_core_dev
*dev
, const void *inb
, void *outb
,
800 void mlx5_pagealloc_init(struct mlx5_core_dev
*dev
);
801 void mlx5_pagealloc_cleanup(struct mlx5_core_dev
*dev
);
802 int mlx5_pagealloc_start(struct mlx5_core_dev
*dev
);
803 void mlx5_pagealloc_stop(struct mlx5_core_dev
*dev
);
804 int mlx5_sriov_init(struct mlx5_core_dev
*dev
);
805 int mlx5_sriov_cleanup(struct mlx5_core_dev
*dev
);
806 void mlx5_core_req_pages_handler(struct mlx5_core_dev
*dev
, u16 func_id
,
808 int mlx5_satisfy_startup_pages(struct mlx5_core_dev
*dev
, int boot
);
809 int mlx5_reclaim_startup_pages(struct mlx5_core_dev
*dev
);
810 void mlx5_register_debugfs(void);
811 void mlx5_unregister_debugfs(void);
812 int mlx5_eq_init(struct mlx5_core_dev
*dev
);
813 void mlx5_eq_cleanup(struct mlx5_core_dev
*dev
);
814 void mlx5_fill_page_array(struct mlx5_buf
*buf
, __be64
*pas
);
815 void mlx5_cq_completion(struct mlx5_core_dev
*dev
, u32 cqn
);
816 void mlx5_rsc_event(struct mlx5_core_dev
*dev
, u32 rsn
, int event_type
);
817 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
818 void mlx5_eq_pagefault(struct mlx5_core_dev
*dev
, struct mlx5_eqe
*eqe
);
820 void mlx5_srq_event(struct mlx5_core_dev
*dev
, u32 srqn
, int event_type
);
821 struct mlx5_core_srq
*mlx5_core_get_srq(struct mlx5_core_dev
*dev
, u32 srqn
);
822 void mlx5_cmd_comp_handler(struct mlx5_core_dev
*dev
, u64 vec
);
823 void mlx5_cq_event(struct mlx5_core_dev
*dev
, u32 cqn
, int event_type
);
824 int mlx5_create_map_eq(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
, u8 vecidx
,
825 int nent
, u64 mask
, const char *name
, struct mlx5_uar
*uar
);
826 int mlx5_destroy_unmap_eq(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
);
827 int mlx5_start_eqs(struct mlx5_core_dev
*dev
);
828 int mlx5_stop_eqs(struct mlx5_core_dev
*dev
);
829 int mlx5_vector2eqn(struct mlx5_core_dev
*dev
, int vector
, int *eqn
,
831 int mlx5_core_attach_mcg(struct mlx5_core_dev
*dev
, union ib_gid
*mgid
, u32 qpn
);
832 int mlx5_core_detach_mcg(struct mlx5_core_dev
*dev
, union ib_gid
*mgid
, u32 qpn
);
834 int mlx5_qp_debugfs_init(struct mlx5_core_dev
*dev
);
835 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev
*dev
);
836 int mlx5_core_access_reg(struct mlx5_core_dev
*dev
, void *data_in
,
837 int size_in
, void *data_out
, int size_out
,
838 u16 reg_num
, int arg
, int write
);
840 int mlx5_debug_eq_add(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
);
841 void mlx5_debug_eq_remove(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
);
842 int mlx5_core_eq_query(struct mlx5_core_dev
*dev
, struct mlx5_eq
*eq
,
843 struct mlx5_query_eq_mbox_out
*out
, int outlen
);
844 int mlx5_eq_debugfs_init(struct mlx5_core_dev
*dev
);
845 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev
*dev
);
846 int mlx5_cq_debugfs_init(struct mlx5_core_dev
*dev
);
847 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev
*dev
);
848 int mlx5_db_alloc(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
);
849 int mlx5_db_alloc_node(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
,
851 void mlx5_db_free(struct mlx5_core_dev
*dev
, struct mlx5_db
*db
);
853 const char *mlx5_command_str(int command
);
854 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev
*dev
);
855 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev
*dev
);
856 int mlx5_core_create_psv(struct mlx5_core_dev
*dev
, u32 pdn
,
857 int npsvs
, u32
*sig_index
);
858 int mlx5_core_destroy_psv(struct mlx5_core_dev
*dev
, int psv_num
);
859 void mlx5_core_put_rsc(struct mlx5_core_rsc_common
*common
);
860 int mlx5_query_odp_caps(struct mlx5_core_dev
*dev
,
861 struct mlx5_odp_caps
*odp_caps
);
862 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev
*dev
,
863 u8 port_num
, void *out
, size_t sz
);
865 static inline int fw_initializing(struct mlx5_core_dev
*dev
)
867 return ioread32be(&dev
->iseg
->initializing
) >> 31;
870 static inline u32
mlx5_mkey_to_idx(u32 mkey
)
875 static inline u32
mlx5_idx_to_mkey(u32 mkey_idx
)
877 return mkey_idx
<< 8;
880 static inline u8
mlx5_mkey_variant(u32 mkey
)
886 MLX5_PROF_MASK_QP_SIZE
= (u64
)1 << 0,
887 MLX5_PROF_MASK_MR_CACHE
= (u64
)1 << 1,
891 MAX_MR_CACHE_ENTRIES
= 16,
895 MLX5_INTERFACE_PROTOCOL_IB
= 0,
896 MLX5_INTERFACE_PROTOCOL_ETH
= 1,
899 struct mlx5_interface
{
900 void * (*add
)(struct mlx5_core_dev
*dev
);
901 void (*remove
)(struct mlx5_core_dev
*dev
, void *context
);
902 void (*event
)(struct mlx5_core_dev
*dev
, void *context
,
903 enum mlx5_dev_event event
, unsigned long param
);
904 void * (*get_dev
)(void *context
);
906 struct list_head list
;
909 void *mlx5_get_protocol_dev(struct mlx5_core_dev
*mdev
, int protocol
);
910 int mlx5_register_interface(struct mlx5_interface
*intf
);
911 void mlx5_unregister_interface(struct mlx5_interface
*intf
);
912 int mlx5_core_query_vendor_id(struct mlx5_core_dev
*mdev
, u32
*vendor_id
);
914 struct mlx5_profile
{
920 } mr_cache
[MAX_MR_CACHE_ENTRIES
];
924 MLX5_PCI_DEV_IS_VF
= 1 << 0,
927 static inline int mlx5_core_is_pf(struct mlx5_core_dev
*dev
)
929 return !(dev
->priv
.pci_dev_data
& MLX5_PCI_DEV_IS_VF
);
932 static inline int mlx5_get_gid_table_len(u16 param
)
935 pr_warn("gid table length is zero\n");
939 return 8 * (1 << param
);
943 MLX5_TRIGGERED_CMD_COMP
= (u64
)1 << 32,
946 #endif /* MLX5_DRIVER_H */