include/linux/mlx5/driver.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DRIVER_H
  34 #define MLX5_DRIVER_H
  35
  36 #include <linux/kernel.h>
  37 #include <linux/completion.h>
  38 #include <linux/pci.h>
  39 #include <linux/spinlock_types.h>
  40 #include <linux/semaphore.h>
  41 #include <linux/slab.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/radix-tree.h>
  44 #include <linux/workqueue.h>
  45 #include <linux/mempool.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/idr.h>
  48
  49 #include <linux/mlx5/device.h>
  50 #include <linux/mlx5/doorbell.h>
  51 #include <linux/mlx5/srq.h>
  52 #include <linux/timecounter.h>
  53 #include <linux/ptp_clock_kernel.h>
  54
  55 enum {
  56         MLX5_BOARD_ID_LEN = 64,
  57         MLX5_MAX_NAME_LEN = 16,
  58 };
  59
  60 enum {
  61         /* one minute for the sake of bringup. Generally, commands must always
  62          * complete and we may need to increase this timeout value
  63          */
  64         MLX5_CMD_TIMEOUT_MSEC   = 60 * 1000,
  65         MLX5_CMD_WQ_MAX_NAME    = 32,
  66 };
  67
  68 enum {
  69         CMD_OWNER_SW            = 0x0,
  70         CMD_OWNER_HW            = 0x1,
  71         CMD_STATUS_SUCCESS      = 0,
  72 };
  73
  74 enum mlx5_sqp_t {
  75         MLX5_SQP_SMI            = 0,
  76         MLX5_SQP_GSI            = 1,
  77         MLX5_SQP_IEEE_1588      = 2,
  78         MLX5_SQP_SNIFFER        = 3,
  79         MLX5_SQP_SYNC_UMR       = 4,
  80 };
  81
  82 enum {
  83         MLX5_MAX_PORTS  = 2,
  84 };
  85
  86 enum {
  87         MLX5_EQ_VEC_PAGES        = 0,
  88         MLX5_EQ_VEC_CMD          = 1,
  89         MLX5_EQ_VEC_ASYNC        = 2,
  90         MLX5_EQ_VEC_PFAULT       = 3,
  91         MLX5_EQ_VEC_COMP_BASE,
  92 };
  93
  94 enum {
  95         MLX5_MAX_IRQ_NAME       = 32
  96 };
  97
  98 enum {
  99         MLX5_ATOMIC_MODE_IB_COMP        = 1 << 16,
 100         MLX5_ATOMIC_MODE_CX             = 2 << 16,
 101         MLX5_ATOMIC_MODE_8B             = 3 << 16,
 102         MLX5_ATOMIC_MODE_16B            = 4 << 16,
 103         MLX5_ATOMIC_MODE_32B            = 5 << 16,
 104         MLX5_ATOMIC_MODE_64B            = 6 << 16,
 105         MLX5_ATOMIC_MODE_128B           = 7 << 16,
 106         MLX5_ATOMIC_MODE_256B           = 8 << 16,
 107 };
 108
 109 enum {
 110         MLX5_REG_QPTS            = 0x4002,
 111         MLX5_REG_QETCR           = 0x4005,
 112         MLX5_REG_QTCT            = 0x400a,
 113         MLX5_REG_QPDPM           = 0x4013,
 114         MLX5_REG_QCAM            = 0x4019,
 115         MLX5_REG_DCBX_PARAM      = 0x4020,
 116         MLX5_REG_DCBX_APP        = 0x4021,
 117         MLX5_REG_FPGA_CAP        = 0x4022,
 118         MLX5_REG_FPGA_CTRL       = 0x4023,
 119         MLX5_REG_FPGA_ACCESS_REG = 0x4024,
 120         MLX5_REG_PCAP            = 0x5001,
 121         MLX5_REG_PMTU            = 0x5003,
 122         MLX5_REG_PTYS            = 0x5004,
 123         MLX5_REG_PAOS            = 0x5006,
 124         MLX5_REG_PFCC            = 0x5007,
 125         MLX5_REG_PPCNT           = 0x5008,
 126         MLX5_REG_PMAOS           = 0x5012,
 127         MLX5_REG_PUDE            = 0x5009,
 128         MLX5_REG_PMPE            = 0x5010,
 129         MLX5_REG_PELC            = 0x500e,
 130         MLX5_REG_PVLC            = 0x500f,
 131         MLX5_REG_PCMR            = 0x5041,
 132         MLX5_REG_PMLP            = 0x5002,
 133         MLX5_REG_PCAM            = 0x507f,
 134         MLX5_REG_NODE_DESC       = 0x6001,
 135         MLX5_REG_HOST_ENDIANNESS = 0x7004,
 136         MLX5_REG_MCIA            = 0x9014,
 137         MLX5_REG_MLCR            = 0x902b,
 138         MLX5_REG_MPCNT           = 0x9051,
 139         MLX5_REG_MTPPS           = 0x9053,
 140         MLX5_REG_MTPPSE          = 0x9054,
 141         MLX5_REG_MCQI            = 0x9061,
 142         MLX5_REG_MCC             = 0x9062,
 143         MLX5_REG_MCDA            = 0x9063,
 144         MLX5_REG_MCAM            = 0x907f,
 145 };
 146
 147 enum mlx5_qpts_trust_state {
 148         MLX5_QPTS_TRUST_PCP  = 1,
 149         MLX5_QPTS_TRUST_DSCP = 2,
 150 };
 151
 152 enum mlx5_dcbx_oper_mode {
 153         MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
 154         MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
 155 };
 156
 157 enum {
 158         MLX5_ATOMIC_OPS_CMP_SWAP        = 1 << 0,
 159         MLX5_ATOMIC_OPS_FETCH_ADD       = 1 << 1,
 160 };
 161
 162 enum mlx5_page_fault_resume_flags {
 163         MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
 164         MLX5_PAGE_FAULT_RESUME_WRITE     = 1 << 1,
 165         MLX5_PAGE_FAULT_RESUME_RDMA      = 1 << 2,
 166         MLX5_PAGE_FAULT_RESUME_ERROR     = 1 << 7,
 167 };
 168
 169 enum dbg_rsc_type {
 170         MLX5_DBG_RSC_QP,
 171         MLX5_DBG_RSC_EQ,
 172         MLX5_DBG_RSC_CQ,
 173 };
 174
 175 enum port_state_policy {
 176         MLX5_POLICY_DOWN        = 0,
 177         MLX5_POLICY_UP          = 1,
 178         MLX5_POLICY_FOLLOW      = 2,
 179         MLX5_POLICY_INVALID     = 0xffffffff
 180 };
 181
 182 struct mlx5_field_desc {
 183         struct dentry          *dent;
 184         int                     i;
 185 };
 186
 187 struct mlx5_rsc_debug {
 188         struct mlx5_core_dev   *dev;
 189         void                   *object;
 190         enum dbg_rsc_type       type;
 191         struct dentry          *root;
 192         struct mlx5_field_desc  fields[0];
 193 };
 194
 195 enum mlx5_dev_event {
 196         MLX5_DEV_EVENT_SYS_ERROR,
 197         MLX5_DEV_EVENT_PORT_UP,
 198         MLX5_DEV_EVENT_PORT_DOWN,
 199         MLX5_DEV_EVENT_PORT_INITIALIZED,
 200         MLX5_DEV_EVENT_LID_CHANGE,
 201         MLX5_DEV_EVENT_PKEY_CHANGE,
 202         MLX5_DEV_EVENT_GUID_CHANGE,
 203         MLX5_DEV_EVENT_CLIENT_REREG,
 204         MLX5_DEV_EVENT_PPS,
 205         MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
 206 };
 207
 208 enum mlx5_port_status {
 209         MLX5_PORT_UP        = 1,
 210         MLX5_PORT_DOWN      = 2,
 211 };
 212
 213 enum mlx5_eq_type {
 214         MLX5_EQ_TYPE_COMP,
 215         MLX5_EQ_TYPE_ASYNC,
 216 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 217         MLX5_EQ_TYPE_PF,
 218 #endif
 219 };
 220
 221 struct mlx5_bfreg_info {
 222         u32                    *sys_pages;
 223         int                     num_low_latency_bfregs;
 224         unsigned int           *count;
 225
 226         /*
 227          * protect bfreg allocation data structs
 228          */
 229         struct mutex            lock;
 230         u32                     ver;
 231         bool                    lib_uar_4k;
 232         u32                     num_sys_pages;
 233 };
 234
 235 struct mlx5_cmd_first {
 236         __be32          data[4];
 237 };
 238
 239 struct mlx5_cmd_msg {
 240         struct list_head                list;
 241         struct cmd_msg_cache           *parent;
 242         u32                             len;
 243         struct mlx5_cmd_first           first;
 244         struct mlx5_cmd_mailbox        *next;
 245 };
 246
 247 struct mlx5_cmd_debug {
 248         struct dentry          *dbg_root;
 249         struct dentry          *dbg_in;
 250         struct dentry          *dbg_out;
 251         struct dentry          *dbg_outlen;
 252         struct dentry          *dbg_status;
 253         struct dentry          *dbg_run;
 254         void                   *in_msg;
 255         void                   *out_msg;
 256         u8                      status;
 257         u16                     inlen;
 258         u16                     outlen;
 259 };
 260
 261 struct cmd_msg_cache {
 262         /* protect block chain allocations
 263          */
 264         spinlock_t              lock;
 265         struct list_head        head;
 266         unsigned int            max_inbox_size;
 267         unsigned int            num_ent;
 268 };
 269
 270 enum {
 271         MLX5_NUM_COMMAND_CACHES = 5,
 272 };
 273
 274 struct mlx5_cmd_stats {
 275         u64             sum;
 276         u64             n;
 277         struct dentry  *root;
 278         struct dentry  *avg;
 279         struct dentry  *count;
 280         /* protect command average calculations */
 281         spinlock_t      lock;
 282 };
 283
 284 struct mlx5_cmd {
 285         void           *cmd_alloc_buf;
 286         dma_addr_t      alloc_dma;
 287         int             alloc_size;
 288         void           *cmd_buf;
 289         dma_addr_t      dma;
 290         u16             cmdif_rev;
 291         u8              log_sz;
 292         u8              log_stride;
 293         int             max_reg_cmds;
 294         int             events;
 295         u32 __iomem    *vector;
 296
 297         /* protect command queue allocations
 298          */
 299         spinlock_t      alloc_lock;
 300
 301         /* protect token allocations
 302          */
 303         spinlock_t      token_lock;
 304         u8              token;
 305         unsigned long   bitmask;
 306         char            wq_name[MLX5_CMD_WQ_MAX_NAME];
 307         struct workqueue_struct *wq;
 308         struct semaphore sem;
 309         struct semaphore pages_sem;
 310         int     mode;
 311         struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
 312         struct dma_pool *pool;
 313         struct mlx5_cmd_debug dbg;
 314         struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
 315         int checksum_disabled;
 316         struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
 317 };
 318
 319 struct mlx5_port_caps {
 320         int     gid_table_len;
 321         int     pkey_table_len;
 322         u8      ext_port_cap;
 323         bool    has_smi;
 324 };
 325
 326 struct mlx5_cmd_mailbox {
 327         void           *buf;
 328         dma_addr_t      dma;
 329         struct mlx5_cmd_mailbox *next;
 330 };
 331
 332 struct mlx5_buf_list {
 333         void                   *buf;
 334         dma_addr_t              map;
 335 };
 336
 337 struct mlx5_buf {
 338         struct mlx5_buf_list    direct;
 339         int                     npages;
 340         int                     size;
 341         u8                      page_shift;
 342 };
 343
 344 struct mlx5_frag_buf {
 345         struct mlx5_buf_list    *frags;
 346         int                     npages;
 347         int                     size;
 348         u8                      page_shift;
 349 };
 350
 351 struct mlx5_eq_tasklet {
 352         struct list_head list;
 353         struct list_head process_list;
 354         struct tasklet_struct task;
 355         /* lock on completion tasklet list */
 356         spinlock_t lock;
 357 };
 358
 359 struct mlx5_eq_pagefault {
 360         struct work_struct       work;
 361         /* Pagefaults lock */
 362         spinlock_t               lock;
 363         struct workqueue_struct *wq;
 364         mempool_t               *pool;
 365 };
 366
 367 struct mlx5_eq {
 368         struct mlx5_core_dev   *dev;
 369         __be32 __iomem         *doorbell;
 370         u32                     cons_index;
 371         struct mlx5_buf         buf;
 372         int                     size;
 373         unsigned int            irqn;
 374         u8                      eqn;
 375         int                     nent;
 376         u64                     mask;
 377         struct list_head        list;
 378         int                     index;
 379         struct mlx5_rsc_debug   *dbg;
 380         enum mlx5_eq_type       type;
 381         union {
 382                 struct mlx5_eq_tasklet   tasklet_ctx;
 383 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 384                 struct mlx5_eq_pagefault pf_ctx;
 385 #endif
 386         };
 387 };
 388
 389 struct mlx5_core_psv {
 390         u32     psv_idx;
 391         struct psv_layout {
 392                 u32     pd;
 393                 u16     syndrome;
 394                 u16     reserved;
 395                 u16     bg;
 396                 u16     app_tag;
 397                 u32     ref_tag;
 398         } psv;
 399 };
 400
 401 struct mlx5_core_sig_ctx {
 402         struct mlx5_core_psv    psv_memory;
 403         struct mlx5_core_psv    psv_wire;
 404         struct ib_sig_err       err_item;
 405         bool                    sig_status_checked;
 406         bool                    sig_err_exists;
 407         u32                     sigerr_count;
 408 };
 409
 410 enum {
 411         MLX5_MKEY_MR = 1,
 412         MLX5_MKEY_MW,
 413 };
 414
 415 struct mlx5_core_mkey {
 416         u64                     iova;
 417         u64                     size;
 418         u32                     key;
 419         u32                     pd;
 420         u32                     type;
 421 };
 422
 423 #define MLX5_24BIT_MASK         ((1 << 24) - 1)
 424
 425 enum mlx5_res_type {
 426         MLX5_RES_QP     = MLX5_EVENT_QUEUE_TYPE_QP,
 427         MLX5_RES_RQ     = MLX5_EVENT_QUEUE_TYPE_RQ,
 428         MLX5_RES_SQ     = MLX5_EVENT_QUEUE_TYPE_SQ,
 429         MLX5_RES_SRQ    = 3,
 430         MLX5_RES_XSRQ   = 4,
 431         MLX5_RES_XRQ    = 5,
 432 };
 433
 434 struct mlx5_core_rsc_common {
 435         enum mlx5_res_type      res;
 436         atomic_t                refcount;
 437         struct completion       free;
 438 };
 439
 440 struct mlx5_core_srq {
 441         struct mlx5_core_rsc_common     common; /* must be first */
 442         u32             srqn;
 443         int             max;
 444         int             max_gs;
 445         int             max_avail_gather;
 446         int             wqe_shift;
 447         void (*event)   (struct mlx5_core_srq *, enum mlx5_event);
 448
 449         atomic_t                refcount;
 450         struct completion       free;
 451 };
 452
 453 struct mlx5_eq_table {
 454         void __iomem           *update_ci;
 455         void __iomem           *update_arm_ci;
 456         struct list_head        comp_eqs_list;
 457         struct mlx5_eq          pages_eq;
 458         struct mlx5_eq          async_eq;
 459         struct mlx5_eq          cmd_eq;
 460 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 461         struct mlx5_eq          pfault_eq;
 462 #endif
 463         int                     num_comp_vectors;
 464         /* protect EQs list
 465          */
 466         spinlock_t              lock;
 467 };
 468
 469 struct mlx5_uars_page {
 470         void __iomem           *map;
 471         bool                    wc;
 472         u32                     index;
 473         struct list_head        list;
 474         unsigned int            bfregs;
 475         unsigned long          *reg_bitmap; /* for non fast path bf regs */
 476         unsigned long          *fp_bitmap;
 477         unsigned int            reg_avail;
 478         unsigned int            fp_avail;
 479         struct kref             ref_count;
 480         struct mlx5_core_dev   *mdev;
 481 };
 482
 483 struct mlx5_bfreg_head {
 484         /* protect blue flame registers allocations */
 485         struct mutex            lock;
 486         struct list_head        list;
 487 };
 488
 489 struct mlx5_bfreg_data {
 490         struct mlx5_bfreg_head  reg_head;
 491         struct mlx5_bfreg_head  wc_head;
 492 };
 493
 494 struct mlx5_sq_bfreg {
 495         void __iomem           *map;
 496         struct mlx5_uars_page  *up;
 497         bool                    wc;
 498         u32                     index;
 499         unsigned int            offset;
 500 };
 501
 502 struct mlx5_core_health {
 503         struct health_buffer __iomem   *health;
 504         __be32 __iomem                 *health_counter;
 505         struct timer_list               timer;
 506         u32                             prev;
 507         int                             miss_counter;
 508         bool                            sick;
 509         /* wq spinlock to synchronize draining */
 510         spinlock_t                      wq_lock;
 511         struct workqueue_struct        *wq;
 512         unsigned long                   flags;
 513         struct work_struct              work;
 514         struct delayed_work             recover_work;
 515 };
 516
 517 struct mlx5_cq_table {
 518         /* protect radix tree
 519          */
 520         spinlock_t              lock;
 521         struct radix_tree_root  tree;
 522 };
 523
 524 struct mlx5_qp_table {
 525         /* protect radix tree
 526          */
 527         spinlock_t              lock;
 528         struct radix_tree_root  tree;
 529 };
 530
 531 struct mlx5_srq_table {
 532         /* protect radix tree
 533          */
 534         spinlock_t              lock;
 535         struct radix_tree_root  tree;
 536 };
 537
 538 struct mlx5_mkey_table {
 539         /* protect radix tree
 540          */
 541         rwlock_t                lock;
 542         struct radix_tree_root  tree;
 543 };
 544
 545 struct mlx5_vf_context {
 546         int     enabled;
 547         u64     port_guid;
 548         u64     node_guid;
 549         enum port_state_policy  policy;
 550 };
 551
 552 struct mlx5_core_sriov {
 553         struct mlx5_vf_context  *vfs_ctx;
 554         int                     num_vfs;
 555         int                     enabled_vfs;
 556 };
 557
 558 struct mlx5_irq_info {
 559         char name[MLX5_MAX_IRQ_NAME];
 560 };
 561
 562 struct mlx5_fc_stats {
 563         struct rb_root counters;
 564         struct list_head addlist;
 565         /* protect addlist add/splice operations */
 566         spinlock_t addlist_lock;
 567
 568         struct workqueue_struct *wq;
 569         struct delayed_work work;
 570         unsigned long next_query;
 571         unsigned long sampling_interval; /* jiffies */
 572 };
 573
 574 struct mlx5_mpfs;
 575 struct mlx5_eswitch;
 576 struct mlx5_lag;
 577 struct mlx5_pagefault;
 578
 579 struct mlx5_rl_entry {
 580         u32                     rate;
 581         u16                     index;
 582         u16                     refcount;
 583 };
 584
 585 struct mlx5_rl_table {
 586         /* protect rate limit table */
 587         struct mutex            rl_lock;
 588         u16                     max_size;
 589         u32                     max_rate;
 590         u32                     min_rate;
 591         struct mlx5_rl_entry   *rl_entry;
 592 };
 593
 594 enum port_module_event_status_type {
 595         MLX5_MODULE_STATUS_PLUGGED   = 0x1,
 596         MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
 597         MLX5_MODULE_STATUS_ERROR     = 0x3,
 598         MLX5_MODULE_STATUS_NUM       = 0x3,
 599 };
 600
 601 enum  port_module_event_error_type {
 602         MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
 603         MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
 604         MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
 605         MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
 606         MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
 607         MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
 608         MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
 609         MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
 610         MLX5_MODULE_EVENT_ERROR_UNKNOWN,
 611         MLX5_MODULE_EVENT_ERROR_NUM,
 612 };
 613
 614 struct mlx5_port_module_event_stats {
 615         u64 status_counters[MLX5_MODULE_STATUS_NUM];
 616         u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
 617 };
 618
 619 struct mlx5_priv {
 620         char                    name[MLX5_MAX_NAME_LEN];
 621         struct mlx5_eq_table    eq_table;
 622         struct mlx5_irq_info    *irq_info;
 623
 624         /* pages stuff */
 625         struct workqueue_struct *pg_wq;
 626         struct rb_root          page_root;
 627         int                     fw_pages;
 628         atomic_t                reg_pages;
 629         struct list_head        free_list;
 630         int                     vfs_pages;
 631
 632         struct mlx5_core_health health;
 633
 634         struct mlx5_srq_table   srq_table;
 635
 636         /* start: qp staff */
 637         struct mlx5_qp_table    qp_table;
 638         struct dentry          *qp_debugfs;
 639         struct dentry          *eq_debugfs;
 640         struct dentry          *cq_debugfs;
 641         struct dentry          *cmdif_debugfs;
 642         /* end: qp staff */
 643
 644         /* start: cq staff */
 645         struct mlx5_cq_table    cq_table;
 646         /* end: cq staff */
 647
 648         /* start: mkey staff */
 649         struct mlx5_mkey_table  mkey_table;
 650         /* end: mkey staff */
 651
 652         /* start: alloc staff */
 653         /* protect buffer alocation according to numa node */
 654         struct mutex            alloc_mutex;
 655         int                     numa_node;
 656
 657         struct mutex            pgdir_mutex;
 658         struct list_head        pgdir_list;
 659         /* end: alloc staff */
 660         struct dentry          *dbg_root;
 661
 662         /* protect mkey key part */
 663         spinlock_t              mkey_lock;
 664         u8                      mkey_key;
 665
 666         struct list_head        dev_list;
 667         struct list_head        ctx_list;
 668         spinlock_t              ctx_lock;
 669
 670         struct list_head        waiting_events_list;
 671         bool                    is_accum_events;
 672
 673         struct mlx5_flow_steering *steering;
 674         struct mlx5_mpfs        *mpfs;
 675         struct mlx5_eswitch     *eswitch;
 676         struct mlx5_core_sriov  sriov;
 677         struct mlx5_lag         *lag;
 678         unsigned long           pci_dev_data;
 679         struct mlx5_fc_stats            fc_stats;
 680         struct mlx5_rl_table            rl_table;
 681
 682         struct mlx5_port_module_event_stats  pme_stats;
 683
 684 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 685         void                  (*pfault)(struct mlx5_core_dev *dev,
 686                                         void *context,
 687                                         struct mlx5_pagefault *pfault);
 688         void                   *pfault_ctx;
 689         struct srcu_struct      pfault_srcu;
 690 #endif
 691         struct mlx5_bfreg_data          bfregs;
 692         struct mlx5_uars_page          *uar;
 693 };
 694
 695 enum mlx5_device_state {
 696         MLX5_DEVICE_STATE_UP,
 697         MLX5_DEVICE_STATE_INTERNAL_ERROR,
 698 };
 699
 700 enum mlx5_interface_state {
 701         MLX5_INTERFACE_STATE_UP = BIT(0),
 702 };
 703
 704 enum mlx5_pci_status {
 705         MLX5_PCI_STATUS_DISABLED,
 706         MLX5_PCI_STATUS_ENABLED,
 707 };
 708
 709 enum mlx5_pagefault_type_flags {
 710         MLX5_PFAULT_REQUESTOR = 1 << 0,
 711         MLX5_PFAULT_WRITE     = 1 << 1,
 712         MLX5_PFAULT_RDMA      = 1 << 2,
 713 };
 714
 715 /* Contains the details of a pagefault. */
 716 struct mlx5_pagefault {
 717         u32                     bytes_committed;
 718         u32                     token;
 719         u8                      event_subtype;
 720         u8                      type;
 721         union {
 722                 /* Initiator or send message responder pagefault details. */
 723                 struct {
 724                         /* Received packet size, only valid for responders. */
 725                         u32     packet_size;
 726                         /*
 727                          * Number of resource holding WQE, depends on type.
 728                          */
 729                         u32     wq_num;
 730                         /*
 731                          * WQE index. Refers to either the send queue or
 732                          * receive queue, according to event_subtype.
 733                          */
 734                         u16     wqe_index;
 735                 } wqe;
 736                 /* RDMA responder pagefault details */
 737                 struct {
 738                         u32     r_key;
 739                         /*
 740                          * Received packet size, minimal size page fault
 741                          * resolution required for forward progress.
 742                          */
 743                         u32     packet_size;
 744                         u32     rdma_op_len;
 745                         u64     rdma_va;
 746                 } rdma;
 747         };
 748
 749         struct mlx5_eq         *eq;
 750         struct work_struct      work;
 751 };
 752
 753 struct mlx5_td {
 754         struct list_head tirs_list;
 755         u32              tdn;
 756 };
 757
 758 struct mlx5e_resources {
 759         u32                        pdn;
 760         struct mlx5_td             td;
 761         struct mlx5_core_mkey      mkey;
 762         struct mlx5_sq_bfreg       bfreg;
 763 };
 764
 765 #define MLX5_MAX_RESERVED_GIDS 8
 766
 767 struct mlx5_rsvd_gids {
 768         unsigned int start;
 769         unsigned int count;
 770         struct ida ida;
 771 };
 772
 773 #define MAX_PIN_NUM     8
 774 struct mlx5_pps {
 775         u8                         pin_caps[MAX_PIN_NUM];
 776         struct work_struct         out_work;
 777         u64                        start[MAX_PIN_NUM];
 778         u8                         enabled;
 779 };
 780
 781 struct mlx5_clock {
 782         rwlock_t                   lock;
 783         struct cyclecounter        cycles;
 784         struct timecounter         tc;
 785         struct hwtstamp_config     hwtstamp_config;
 786         u32                        nominal_c_mult;
 787         unsigned long              overflow_period;
 788         struct delayed_work        overflow_work;
 789         struct ptp_clock          *ptp;
 790         struct ptp_clock_info      ptp_info;
 791         struct mlx5_pps            pps_info;
 792 };
 793
 794 struct mlx5_core_dev {
 795         struct pci_dev         *pdev;
 796         /* sync pci state */
 797         struct mutex            pci_status_mutex;
 798         enum mlx5_pci_status    pci_status;
 799         u8                      rev_id;
 800         char                    board_id[MLX5_BOARD_ID_LEN];
 801         struct mlx5_cmd         cmd;
 802         struct mlx5_port_caps   port_caps[MLX5_MAX_PORTS];
 803         struct {
 804                 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 805                 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 806                 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
 807                 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
 808                 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
 809                 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
 810         } caps;
 811         phys_addr_t             iseg_base;
 812         struct mlx5_init_seg __iomem *iseg;
 813         enum mlx5_device_state  state;
 814         /* sync interface state */
 815         struct mutex            intf_state_mutex;
 816         unsigned long           intf_state;
 817         void                    (*event) (struct mlx5_core_dev *dev,
 818                                           enum mlx5_dev_event event,
 819                                           unsigned long param);
 820         struct mlx5_priv        priv;
 821         struct mlx5_profile     *profile;
 822         atomic_t                num_qps;
 823         u32                     issi;
 824         struct mlx5e_resources  mlx5e_res;
 825         struct {
 826                 struct mlx5_rsvd_gids   reserved_gids;
 827                 atomic_t                roce_en;
 828         } roce;
 829 #ifdef CONFIG_MLX5_FPGA
 830         struct mlx5_fpga_device *fpga;
 831 #endif
 832 #ifdef CONFIG_RFS_ACCEL
 833         struct cpu_rmap         *rmap;
 834 #endif
 835         struct mlx5_clock        clock;
 836 };
 837
 838 struct mlx5_db {
 839         __be32                  *db;
 840         union {
 841                 struct mlx5_db_pgdir            *pgdir;
 842                 struct mlx5_ib_user_db_page     *user_page;
 843         }                       u;
 844         dma_addr_t              dma;
 845         int                     index;
 846 };
 847
 848 enum {
 849         MLX5_COMP_EQ_SIZE = 1024,
 850 };
 851
 852 enum {
 853         MLX5_PTYS_IB = 1 << 0,
 854         MLX5_PTYS_EN = 1 << 2,
 855 };
 856
 857 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
 858
 859 enum {
 860         MLX5_CMD_ENT_STATE_PENDING_COMP,
 861 };
 862
 863 struct mlx5_cmd_work_ent {
 864         unsigned long           state;
 865         struct mlx5_cmd_msg    *in;
 866         struct mlx5_cmd_msg    *out;
 867         void                   *uout;
 868         int                     uout_size;
 869         mlx5_cmd_cbk_t          callback;
 870         struct delayed_work     cb_timeout_work;
 871         void                   *context;
 872         int                     idx;
 873         struct completion       done;
 874         struct mlx5_cmd        *cmd;
 875         struct work_struct      work;
 876         struct mlx5_cmd_layout *lay;
 877         int                     ret;
 878         int                     page_queue;
 879         u8                      status;
 880         u8                      token;
 881         u64                     ts1;
 882         u64                     ts2;
 883         u16                     op;
 884         bool                    polling;
 885 };
 886
 887 struct mlx5_pas {
 888         u64     pa;
 889         u8      log_sz;
 890 };
 891
 892 enum phy_port_state {
 893         MLX5_AAA_111
 894 };
 895
 896 struct mlx5_hca_vport_context {
 897         u32                     field_select;
 898         bool                    sm_virt_aware;
 899         bool                    has_smi;
 900         bool                    has_raw;
 901         enum port_state_policy  policy;
 902         enum phy_port_state     phys_state;
 903         enum ib_port_state      vport_state;
 904         u8                      port_physical_state;
 905         u64                     sys_image_guid;
 906         u64                     port_guid;
 907         u64                     node_guid;
 908         u32                     cap_mask1;
 909         u32                     cap_mask1_perm;
 910         u32                     cap_mask2;
 911         u32                     cap_mask2_perm;
 912         u16                     lid;
 913         u8                      init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
 914         u8                      lmc;
 915         u8                      subnet_timeout;
 916         u16                     sm_lid;
 917         u8                      sm_sl;
 918         u16                     qkey_violation_counter;
 919         u16                     pkey_violation_counter;
 920         bool                    grh_required;
 921 };
 922
 923 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
 924 {
 925                 return buf->direct.buf + offset;
 926 }
 927
 928 #define STRUCT_FIELD(header, field) \
 929         .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
 930         .struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
 931
 932 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
 933 {
 934         return pci_get_drvdata(pdev);
 935 }
 936
 937 extern struct dentry *mlx5_debugfs_root;
 938
 939 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
 940 {
 941         return ioread32be(&dev->iseg->fw_rev) & 0xffff;
 942 }
 943
 944 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
 945 {
 946         return ioread32be(&dev->iseg->fw_rev) >> 16;
 947 }
 948
 949 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
 950 {
 951         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
 952 }
 953
 954 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
 955 {
 956         return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
 957 }
 958
 959 static inline u32 mlx5_base_mkey(const u32 key)
 960 {
 961         return key & 0xffffff00u;
 962 }
 963
 964 int mlx5_cmd_init(struct mlx5_core_dev *dev);
 965 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
 966 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
 967 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
 968
 969 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
 970                   int out_size);
 971 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
 972                      void *out, int out_size, mlx5_cmd_cbk_t callback,
 973                      void *context);
 974 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
 975                           void *out, int out_size);
 976 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
 977
 978 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
 979 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
 980 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
 981 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
 982 int mlx5_health_init(struct mlx5_core_dev *dev);
 983 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
 984 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
 985 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
 986 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
 987 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
 988 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
 989                         struct mlx5_buf *buf, int node);
 990 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
 991 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
 992 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
 993                              struct mlx5_frag_buf *buf, int node);
 994 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
 995 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
 996                                                       gfp_t flags, int npages);
 997 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
 998                                  struct mlx5_cmd_mailbox *head);
 999 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1000                          struct mlx5_srq_attr *in);
1001 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
1002 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1003                         struct mlx5_srq_attr *out);
1004 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1005                       u16 lwm, int is_srq);
1006 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
1007 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
1008 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1009                              struct mlx5_core_mkey *mkey,
1010                              u32 *in, int inlen,
1011                              u32 *out, int outlen,
1012                              mlx5_cmd_cbk_t callback, void *context);
1013 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1014                           struct mlx5_core_mkey *mkey,
1015                           u32 *in, int inlen);
1016 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
1017                            struct mlx5_core_mkey *mkey);
1018 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1019                          u32 *out, int outlen);
1020 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
1021                              u32 *mkey);
1022 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1023 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1024 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1025                       u16 opmod, u8 port);
1026 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1027 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1028 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1029 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1030 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1031                                  s32 npages);
1032 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1033 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1034 void mlx5_register_debugfs(void);
1035 void mlx5_unregister_debugfs(void);
1036 int mlx5_eq_init(struct mlx5_core_dev *dev);
1037 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1038 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1039 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1040 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1041 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1042 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1043 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1044 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
1045 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1046 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1047                        int nent, u64 mask, const char *name,
1048                        enum mlx5_eq_type type);
1049 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1050 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1051 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1052 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1053                     unsigned int *irqn);
1054 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1055 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1056
1057 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1058 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1059 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1060                          int size_in, void *data_out, int size_out,
1061                          u16 reg_num, int arg, int write);
1062
1063 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1064 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1065 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1066                        u32 *out, int outlen);
1067 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1068 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1069 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1070 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1071 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1072 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1073                        int node);
1074 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1075
1076 const char *mlx5_command_str(int command);
1077 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1078 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1079 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1080                          int npsvs, u32 *sig_index);
1081 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1082 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1083 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1084                         struct mlx5_odp_caps *odp_caps);
1085 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1086                              u8 port_num, void *out, size_t sz);
1087 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1088 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1089                                 u32 wq_num, u8 type, int error);
1090 #endif
1091
1092 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1093 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1094 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1095 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1096 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1097 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1098                      bool map_wc, bool fast_path);
1099 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1100
1101 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1102 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1103                            u8 roce_version, u8 roce_l3_type, const u8 *gid,
1104                            const u8 *mac, bool vlan, u16 vlan_id);
1105
1106 static inline int fw_initializing(struct mlx5_core_dev *dev)
1107 {
1108         return ioread32be(&dev->iseg->initializing) >> 31;
1109 }
1110
1111 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1112 {
1113         return mkey >> 8;
1114 }
1115
1116 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1117 {
1118         return mkey_idx << 8;
1119 }
1120
1121 static inline u8 mlx5_mkey_variant(u32 mkey)
1122 {
1123         return mkey & 0xff;
1124 }
1125
1126 enum {
1127         MLX5_PROF_MASK_QP_SIZE          = (u64)1 << 0,
1128         MLX5_PROF_MASK_MR_CACHE         = (u64)1 << 1,
1129 };
1130
1131 enum {
1132         MR_CACHE_LAST_STD_ENTRY = 20,
1133         MLX5_IMR_MTT_CACHE_ENTRY,
1134         MLX5_IMR_KSM_CACHE_ENTRY,
1135         MAX_MR_CACHE_ENTRIES
1136 };
1137
1138 enum {
1139         MLX5_INTERFACE_PROTOCOL_IB  = 0,
1140         MLX5_INTERFACE_PROTOCOL_ETH = 1,
1141 };
1142
1143 struct mlx5_interface {
1144         void *                  (*add)(struct mlx5_core_dev *dev);
1145         void                    (*remove)(struct mlx5_core_dev *dev, void *context);
1146         int                     (*attach)(struct mlx5_core_dev *dev, void *context);
1147         void                    (*detach)(struct mlx5_core_dev *dev, void *context);
1148         void                    (*event)(struct mlx5_core_dev *dev, void *context,
1149                                          enum mlx5_dev_event event, unsigned long param);
1150         void                    (*pfault)(struct mlx5_core_dev *dev,
1151                                           void *context,
1152                                           struct mlx5_pagefault *pfault);
1153         void *                  (*get_dev)(void *context);
1154         int                     protocol;
1155         struct list_head        list;
1156 };
1157
1158 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1159 int mlx5_register_interface(struct mlx5_interface *intf);
1160 void mlx5_unregister_interface(struct mlx5_interface *intf);
1161 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1162
1163 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1164 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1165 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1166 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1167 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1168 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1169
1170 #ifndef CONFIG_MLX5_CORE_IPOIB
1171 static inline
1172 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1173                                           struct ib_device *ibdev,
1174                                           const char *name,
1175                                           void (*setup)(struct net_device *))
1176 {
1177         return ERR_PTR(-EOPNOTSUPP);
1178 }
1179
1180 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1181 #else
1182 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1183                                           struct ib_device *ibdev,
1184                                           const char *name,
1185                                           void (*setup)(struct net_device *));
1186 void mlx5_rdma_netdev_free(struct net_device *netdev);
1187 #endif /* CONFIG_MLX5_CORE_IPOIB */
1188
1189 struct mlx5_profile {
1190         u64     mask;
1191         u8      log_max_qp;
1192         struct {
1193                 int     size;
1194                 int     limit;
1195         } mr_cache[MAX_MR_CACHE_ENTRIES];
1196 };
1197
1198 enum {
1199         MLX5_PCI_DEV_IS_VF              = 1 << 0,
1200 };
1201
1202 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1203 {
1204         return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1205 }
1206
1207 static inline int mlx5_get_gid_table_len(u16 param)
1208 {
1209         if (param > 4) {
1210                 pr_warn("gid table length is zero\n");
1211                 return 0;
1212         }
1213
1214         return 8 * (1 << param);
1215 }
1216
1217 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1218 {
1219         return !!(dev->priv.rl_table.max_size);
1220 }
1221
1222 enum {
1223         MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1224 };
1225
1226 static inline const struct cpumask *
1227 mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector)
1228 {
1229         return pci_irq_get_affinity(dev->pdev, MLX5_EQ_VEC_COMP_BASE + vector);
1230 }
1231
1232 #endif /* MLX5_DRIVER_H */