include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 150         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 170         MLX5_CMD_OP_NOP                           = 0x80d,
 171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 203         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 204         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 205         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 206         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 207         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 208         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 209         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 210         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 211         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 212         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 213         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 214         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 215         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 216         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 217         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 218         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 219         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 220         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 221         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 222         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 223         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 224         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 225         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 226         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 227         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 228         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 229         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 230         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 231         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 232         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 233         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 234         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 235         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 236         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 237         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 238         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 239         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 240         MLX5_CMD_OP_MAX
 241 };
 242
 243 struct mlx5_ifc_flow_table_fields_supported_bits {
 244         u8         outer_dmac[0x1];
 245         u8         outer_smac[0x1];
 246         u8         outer_ether_type[0x1];
 247         u8         outer_ip_version[0x1];
 248         u8         outer_first_prio[0x1];
 249         u8         outer_first_cfi[0x1];
 250         u8         outer_first_vid[0x1];
 251         u8         outer_ipv4_ttl[0x1];
 252         u8         outer_second_prio[0x1];
 253         u8         outer_second_cfi[0x1];
 254         u8         outer_second_vid[0x1];
 255         u8         reserved_at_b[0x1];
 256         u8         outer_sip[0x1];
 257         u8         outer_dip[0x1];
 258         u8         outer_frag[0x1];
 259         u8         outer_ip_protocol[0x1];
 260         u8         outer_ip_ecn[0x1];
 261         u8         outer_ip_dscp[0x1];
 262         u8         outer_udp_sport[0x1];
 263         u8         outer_udp_dport[0x1];
 264         u8         outer_tcp_sport[0x1];
 265         u8         outer_tcp_dport[0x1];
 266         u8         outer_tcp_flags[0x1];
 267         u8         outer_gre_protocol[0x1];
 268         u8         outer_gre_key[0x1];
 269         u8         outer_vxlan_vni[0x1];
 270         u8         reserved_at_1a[0x5];
 271         u8         source_eswitch_port[0x1];
 272
 273         u8         inner_dmac[0x1];
 274         u8         inner_smac[0x1];
 275         u8         inner_ether_type[0x1];
 276         u8         inner_ip_version[0x1];
 277         u8         inner_first_prio[0x1];
 278         u8         inner_first_cfi[0x1];
 279         u8         inner_first_vid[0x1];
 280         u8         reserved_at_27[0x1];
 281         u8         inner_second_prio[0x1];
 282         u8         inner_second_cfi[0x1];
 283         u8         inner_second_vid[0x1];
 284         u8         reserved_at_2b[0x1];
 285         u8         inner_sip[0x1];
 286         u8         inner_dip[0x1];
 287         u8         inner_frag[0x1];
 288         u8         inner_ip_protocol[0x1];
 289         u8         inner_ip_ecn[0x1];
 290         u8         inner_ip_dscp[0x1];
 291         u8         inner_udp_sport[0x1];
 292         u8         inner_udp_dport[0x1];
 293         u8         inner_tcp_sport[0x1];
 294         u8         inner_tcp_dport[0x1];
 295         u8         inner_tcp_flags[0x1];
 296         u8         reserved_at_37[0x9];
 297
 298         u8         reserved_at_40[0x40];
 299 };
 300
 301 struct mlx5_ifc_flow_table_prop_layout_bits {
 302         u8         ft_support[0x1];
 303         u8         reserved_at_1[0x1];
 304         u8         flow_counter[0x1];
 305         u8         flow_modify_en[0x1];
 306         u8         modify_root[0x1];
 307         u8         identified_miss_table_mode[0x1];
 308         u8         flow_table_modify[0x1];
 309         u8         encap[0x1];
 310         u8         decap[0x1];
 311         u8         reserved_at_9[0x17];
 312
 313         u8         reserved_at_20[0x2];
 314         u8         log_max_ft_size[0x6];
 315         u8         log_max_modify_header_context[0x8];
 316         u8         max_modify_header_actions[0x8];
 317         u8         max_ft_level[0x8];
 318
 319         u8         reserved_at_40[0x20];
 320
 321         u8         reserved_at_60[0x18];
 322         u8         log_max_ft_num[0x8];
 323
 324         u8         reserved_at_80[0x18];
 325         u8         log_max_destination[0x8];
 326
 327         u8         reserved_at_a0[0x18];
 328         u8         log_max_flow[0x8];
 329
 330         u8         reserved_at_c0[0x40];
 331
 332         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 333
 334         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 335 };
 336
 337 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 338         u8         send[0x1];
 339         u8         receive[0x1];
 340         u8         write[0x1];
 341         u8         read[0x1];
 342         u8         atomic[0x1];
 343         u8         srq_receive[0x1];
 344         u8         reserved_at_6[0x1a];
 345 };
 346
 347 struct mlx5_ifc_ipv4_layout_bits {
 348         u8         reserved_at_0[0x60];
 349
 350         u8         ipv4[0x20];
 351 };
 352
 353 struct mlx5_ifc_ipv6_layout_bits {
 354         u8         ipv6[16][0x8];
 355 };
 356
 357 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 358         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 359         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 360         u8         reserved_at_0[0x80];
 361 };
 362
 363 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 364         u8         smac_47_16[0x20];
 365
 366         u8         smac_15_0[0x10];
 367         u8         ethertype[0x10];
 368
 369         u8         dmac_47_16[0x20];
 370
 371         u8         dmac_15_0[0x10];
 372         u8         first_prio[0x3];
 373         u8         first_cfi[0x1];
 374         u8         first_vid[0xc];
 375
 376         u8         ip_protocol[0x8];
 377         u8         ip_dscp[0x6];
 378         u8         ip_ecn[0x2];
 379         u8         cvlan_tag[0x1];
 380         u8         svlan_tag[0x1];
 381         u8         frag[0x1];
 382         u8         ip_version[0x4];
 383         u8         tcp_flags[0x9];
 384
 385         u8         tcp_sport[0x10];
 386         u8         tcp_dport[0x10];
 387
 388         u8         reserved_at_c0[0x18];
 389         u8         ttl_hoplimit[0x8];
 390
 391         u8         udp_sport[0x10];
 392         u8         udp_dport[0x10];
 393
 394         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 395
 396         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 397 };
 398
 399 struct mlx5_ifc_fte_match_set_misc_bits {
 400         u8         reserved_at_0[0x8];
 401         u8         source_sqn[0x18];
 402
 403         u8         reserved_at_20[0x10];
 404         u8         source_port[0x10];
 405
 406         u8         outer_second_prio[0x3];
 407         u8         outer_second_cfi[0x1];
 408         u8         outer_second_vid[0xc];
 409         u8         inner_second_prio[0x3];
 410         u8         inner_second_cfi[0x1];
 411         u8         inner_second_vid[0xc];
 412
 413         u8         outer_second_cvlan_tag[0x1];
 414         u8         inner_second_cvlan_tag[0x1];
 415         u8         outer_second_svlan_tag[0x1];
 416         u8         inner_second_svlan_tag[0x1];
 417         u8         reserved_at_64[0xc];
 418         u8         gre_protocol[0x10];
 419
 420         u8         gre_key_h[0x18];
 421         u8         gre_key_l[0x8];
 422
 423         u8         vxlan_vni[0x18];
 424         u8         reserved_at_b8[0x8];
 425
 426         u8         reserved_at_c0[0x20];
 427
 428         u8         reserved_at_e0[0xc];
 429         u8         outer_ipv6_flow_label[0x14];
 430
 431         u8         reserved_at_100[0xc];
 432         u8         inner_ipv6_flow_label[0x14];
 433
 434         u8         reserved_at_120[0xe0];
 435 };
 436
 437 struct mlx5_ifc_cmd_pas_bits {
 438         u8         pa_h[0x20];
 439
 440         u8         pa_l[0x14];
 441         u8         reserved_at_34[0xc];
 442 };
 443
 444 struct mlx5_ifc_uint64_bits {
 445         u8         hi[0x20];
 446
 447         u8         lo[0x20];
 448 };
 449
 450 enum {
 451         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 452         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 453         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 454         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 455         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 456         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 457         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 458         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 459         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 460         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 461 };
 462
 463 struct mlx5_ifc_ads_bits {
 464         u8         fl[0x1];
 465         u8         free_ar[0x1];
 466         u8         reserved_at_2[0xe];
 467         u8         pkey_index[0x10];
 468
 469         u8         reserved_at_20[0x8];
 470         u8         grh[0x1];
 471         u8         mlid[0x7];
 472         u8         rlid[0x10];
 473
 474         u8         ack_timeout[0x5];
 475         u8         reserved_at_45[0x3];
 476         u8         src_addr_index[0x8];
 477         u8         reserved_at_50[0x4];
 478         u8         stat_rate[0x4];
 479         u8         hop_limit[0x8];
 480
 481         u8         reserved_at_60[0x4];
 482         u8         tclass[0x8];
 483         u8         flow_label[0x14];
 484
 485         u8         rgid_rip[16][0x8];
 486
 487         u8         reserved_at_100[0x4];
 488         u8         f_dscp[0x1];
 489         u8         f_ecn[0x1];
 490         u8         reserved_at_106[0x1];
 491         u8         f_eth_prio[0x1];
 492         u8         ecn[0x2];
 493         u8         dscp[0x6];
 494         u8         udp_sport[0x10];
 495
 496         u8         dei_cfi[0x1];
 497         u8         eth_prio[0x3];
 498         u8         sl[0x4];
 499         u8         port[0x8];
 500         u8         rmac_47_32[0x10];
 501
 502         u8         rmac_31_0[0x20];
 503 };
 504
 505 struct mlx5_ifc_flow_table_nic_cap_bits {
 506         u8         nic_rx_multi_path_tirs[0x1];
 507         u8         nic_rx_multi_path_tirs_fts[0x1];
 508         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 509         u8         reserved_at_3[0x1fd];
 510
 511         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 512
 513         u8         reserved_at_400[0x200];
 514
 515         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 518
 519         u8         reserved_at_a00[0x200];
 520
 521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 522
 523         u8         reserved_at_e00[0x7200];
 524 };
 525
 526 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 527         u8     reserved_at_0[0x200];
 528
 529         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 530
 531         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 532
 533         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 534
 535         u8      reserved_at_800[0x7800];
 536 };
 537
 538 struct mlx5_ifc_e_switch_cap_bits {
 539         u8         vport_svlan_strip[0x1];
 540         u8         vport_cvlan_strip[0x1];
 541         u8         vport_svlan_insert[0x1];
 542         u8         vport_cvlan_insert_if_not_exist[0x1];
 543         u8         vport_cvlan_insert_overwrite[0x1];
 544         u8         reserved_at_5[0x19];
 545         u8         nic_vport_node_guid_modify[0x1];
 546         u8         nic_vport_port_guid_modify[0x1];
 547
 548         u8         vxlan_encap_decap[0x1];
 549         u8         nvgre_encap_decap[0x1];
 550         u8         reserved_at_22[0x9];
 551         u8         log_max_encap_headers[0x5];
 552         u8         reserved_2b[0x6];
 553         u8         max_encap_header_size[0xa];
 554
 555         u8         reserved_40[0x7c0];
 556
 557 };
 558
 559 struct mlx5_ifc_qos_cap_bits {
 560         u8         packet_pacing[0x1];
 561         u8         esw_scheduling[0x1];
 562         u8         esw_bw_share[0x1];
 563         u8         esw_rate_limit[0x1];
 564         u8         reserved_at_4[0x1c];
 565
 566         u8         reserved_at_20[0x20];
 567
 568         u8         packet_pacing_max_rate[0x20];
 569
 570         u8         packet_pacing_min_rate[0x20];
 571
 572         u8         reserved_at_80[0x10];
 573         u8         packet_pacing_rate_table_size[0x10];
 574
 575         u8         esw_element_type[0x10];
 576         u8         esw_tsar_type[0x10];
 577
 578         u8         reserved_at_c0[0x10];
 579         u8         max_qos_para_vport[0x10];
 580
 581         u8         max_tsar_bw_share[0x20];
 582
 583         u8         reserved_at_100[0x700];
 584 };
 585
 586 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 587         u8         csum_cap[0x1];
 588         u8         vlan_cap[0x1];
 589         u8         lro_cap[0x1];
 590         u8         lro_psh_flag[0x1];
 591         u8         lro_time_stamp[0x1];
 592         u8         reserved_at_5[0x2];
 593         u8         wqe_vlan_insert[0x1];
 594         u8         self_lb_en_modifiable[0x1];
 595         u8         reserved_at_9[0x2];
 596         u8         max_lso_cap[0x5];
 597         u8         multi_pkt_send_wqe[0x2];
 598         u8         wqe_inline_mode[0x2];
 599         u8         rss_ind_tbl_cap[0x4];
 600         u8         reg_umr_sq[0x1];
 601         u8         scatter_fcs[0x1];
 602         u8         reserved_at_1a[0x1];
 603         u8         tunnel_lso_const_out_ip_id[0x1];
 604         u8         reserved_at_1c[0x2];
 605         u8         tunnel_statless_gre[0x1];
 606         u8         tunnel_stateless_vxlan[0x1];
 607
 608         u8         swp[0x1];
 609         u8         swp_csum[0x1];
 610         u8         swp_lso[0x1];
 611         u8         reserved_at_23[0x1d];
 612
 613         u8         reserved_at_40[0x10];
 614         u8         lro_min_mss_size[0x10];
 615
 616         u8         reserved_at_60[0x120];
 617
 618         u8         lro_timer_supported_periods[4][0x20];
 619
 620         u8         reserved_at_200[0x600];
 621 };
 622
 623 struct mlx5_ifc_roce_cap_bits {
 624         u8         roce_apm[0x1];
 625         u8         reserved_at_1[0x1f];
 626
 627         u8         reserved_at_20[0x60];
 628
 629         u8         reserved_at_80[0xc];
 630         u8         l3_type[0x4];
 631         u8         reserved_at_90[0x8];
 632         u8         roce_version[0x8];
 633
 634         u8         reserved_at_a0[0x10];
 635         u8         r_roce_dest_udp_port[0x10];
 636
 637         u8         r_roce_max_src_udp_port[0x10];
 638         u8         r_roce_min_src_udp_port[0x10];
 639
 640         u8         reserved_at_e0[0x10];
 641         u8         roce_address_table_size[0x10];
 642
 643         u8         reserved_at_100[0x700];
 644 };
 645
 646 enum {
 647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 648         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 649         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 650         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 651         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 652         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 653         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 654         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 656 };
 657
 658 enum {
 659         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 660         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 661         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 662         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 663         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 664         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 665         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 666         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 667         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 668 };
 669
 670 struct mlx5_ifc_atomic_caps_bits {
 671         u8         reserved_at_0[0x40];
 672
 673         u8         atomic_req_8B_endianness_mode[0x2];
 674         u8         reserved_at_42[0x4];
 675         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 676
 677         u8         reserved_at_47[0x19];
 678
 679         u8         reserved_at_60[0x20];
 680
 681         u8         reserved_at_80[0x10];
 682         u8         atomic_operations[0x10];
 683
 684         u8         reserved_at_a0[0x10];
 685         u8         atomic_size_qp[0x10];
 686
 687         u8         reserved_at_c0[0x10];
 688         u8         atomic_size_dc[0x10];
 689
 690         u8         reserved_at_e0[0x720];
 691 };
 692
 693 struct mlx5_ifc_odp_cap_bits {
 694         u8         reserved_at_0[0x40];
 695
 696         u8         sig[0x1];
 697         u8         reserved_at_41[0x1f];
 698
 699         u8         reserved_at_60[0x20];
 700
 701         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 702
 703         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 704
 705         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 706
 707         u8         reserved_at_e0[0x720];
 708 };
 709
 710 struct mlx5_ifc_calc_op {
 711         u8        reserved_at_0[0x10];
 712         u8        reserved_at_10[0x9];
 713         u8        op_swap_endianness[0x1];
 714         u8        op_min[0x1];
 715         u8        op_xor[0x1];
 716         u8        op_or[0x1];
 717         u8        op_and[0x1];
 718         u8        op_max[0x1];
 719         u8        op_add[0x1];
 720 };
 721
 722 struct mlx5_ifc_vector_calc_cap_bits {
 723         u8         calc_matrix[0x1];
 724         u8         reserved_at_1[0x1f];
 725         u8         reserved_at_20[0x8];
 726         u8         max_vec_count[0x8];
 727         u8         reserved_at_30[0xd];
 728         u8         max_chunk_size[0x3];
 729         struct mlx5_ifc_calc_op calc0;
 730         struct mlx5_ifc_calc_op calc1;
 731         struct mlx5_ifc_calc_op calc2;
 732         struct mlx5_ifc_calc_op calc3;
 733
 734         u8         reserved_at_e0[0x720];
 735 };
 736
 737 enum {
 738         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 739         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 740         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 741 };
 742
 743 enum {
 744         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 745         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 746 };
 747
 748 enum {
 749         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 750         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 751         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 752         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 753         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 754 };
 755
 756 enum {
 757         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 758         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 759         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 760         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 761         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 762         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 763 };
 764
 765 enum {
 766         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 767         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 768 };
 769
 770 enum {
 771         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 772         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 773         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 774 };
 775
 776 enum {
 777         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 778         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 779 };
 780
 781 enum {
 782         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 783         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 784         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 785 };
 786
 787 struct mlx5_ifc_cmd_hca_cap_bits {
 788         u8         reserved_at_0[0x80];
 789
 790         u8         log_max_srq_sz[0x8];
 791         u8         log_max_qp_sz[0x8];
 792         u8         reserved_at_90[0xb];
 793         u8         log_max_qp[0x5];
 794
 795         u8         reserved_at_a0[0xb];
 796         u8         log_max_srq[0x5];
 797         u8         reserved_at_b0[0x10];
 798
 799         u8         reserved_at_c0[0x8];
 800         u8         log_max_cq_sz[0x8];
 801         u8         reserved_at_d0[0xb];
 802         u8         log_max_cq[0x5];
 803
 804         u8         log_max_eq_sz[0x8];
 805         u8         reserved_at_e8[0x2];
 806         u8         log_max_mkey[0x6];
 807         u8         reserved_at_f0[0xc];
 808         u8         log_max_eq[0x4];
 809
 810         u8         max_indirection[0x8];
 811         u8         fixed_buffer_size[0x1];
 812         u8         log_max_mrw_sz[0x7];
 813         u8         force_teardown[0x1];
 814         u8         reserved_at_111[0x1];
 815         u8         log_max_bsf_list_size[0x6];
 816         u8         umr_extended_translation_offset[0x1];
 817         u8         null_mkey[0x1];
 818         u8         log_max_klm_list_size[0x6];
 819
 820         u8         reserved_at_120[0xa];
 821         u8         log_max_ra_req_dc[0x6];
 822         u8         reserved_at_130[0xa];
 823         u8         log_max_ra_res_dc[0x6];
 824
 825         u8         reserved_at_140[0xa];
 826         u8         log_max_ra_req_qp[0x6];
 827         u8         reserved_at_150[0xa];
 828         u8         log_max_ra_res_qp[0x6];
 829
 830         u8         end_pad[0x1];
 831         u8         cc_query_allowed[0x1];
 832         u8         cc_modify_allowed[0x1];
 833         u8         start_pad[0x1];
 834         u8         cache_line_128byte[0x1];
 835         u8         reserved_at_165[0xb];
 836         u8         gid_table_size[0x10];
 837
 838         u8         out_of_seq_cnt[0x1];
 839         u8         vport_counters[0x1];
 840         u8         retransmission_q_counters[0x1];
 841         u8         reserved_at_183[0x1];
 842         u8         modify_rq_counter_set_id[0x1];
 843         u8         reserved_at_185[0x1];
 844         u8         max_qp_cnt[0xa];
 845         u8         pkey_table_size[0x10];
 846
 847         u8         vport_group_manager[0x1];
 848         u8         vhca_group_manager[0x1];
 849         u8         ib_virt[0x1];
 850         u8         eth_virt[0x1];
 851         u8         reserved_at_1a4[0x1];
 852         u8         ets[0x1];
 853         u8         nic_flow_table[0x1];
 854         u8         eswitch_flow_table[0x1];
 855         u8         early_vf_enable[0x1];
 856         u8         mcam_reg[0x1];
 857         u8         pcam_reg[0x1];
 858         u8         local_ca_ack_delay[0x5];
 859         u8         port_module_event[0x1];
 860         u8         reserved_at_1b1[0x1];
 861         u8         ports_check[0x1];
 862         u8         reserved_at_1b3[0x1];
 863         u8         disable_link_up[0x1];
 864         u8         beacon_led[0x1];
 865         u8         port_type[0x2];
 866         u8         num_ports[0x8];
 867
 868         u8         reserved_at_1c0[0x1];
 869         u8         pps[0x1];
 870         u8         pps_modify[0x1];
 871         u8         log_max_msg[0x5];
 872         u8         reserved_at_1c8[0x4];
 873         u8         max_tc[0x4];
 874         u8         reserved_at_1d0[0x1];
 875         u8         dcbx[0x1];
 876         u8         reserved_at_1d2[0x3];
 877         u8         fpga[0x1];
 878         u8         rol_s[0x1];
 879         u8         rol_g[0x1];
 880         u8         reserved_at_1d8[0x1];
 881         u8         wol_s[0x1];
 882         u8         wol_g[0x1];
 883         u8         wol_a[0x1];
 884         u8         wol_b[0x1];
 885         u8         wol_m[0x1];
 886         u8         wol_u[0x1];
 887         u8         wol_p[0x1];
 888
 889         u8         stat_rate_support[0x10];
 890         u8         reserved_at_1f0[0xc];
 891         u8         cqe_version[0x4];
 892
 893         u8         compact_address_vector[0x1];
 894         u8         striding_rq[0x1];
 895         u8         reserved_at_202[0x1];
 896         u8         ipoib_enhanced_offloads[0x1];
 897         u8         ipoib_basic_offloads[0x1];
 898         u8         reserved_at_205[0x5];
 899         u8         umr_fence[0x2];
 900         u8         reserved_at_20c[0x3];
 901         u8         drain_sigerr[0x1];
 902         u8         cmdif_checksum[0x2];
 903         u8         sigerr_cqe[0x1];
 904         u8         reserved_at_213[0x1];
 905         u8         wq_signature[0x1];
 906         u8         sctr_data_cqe[0x1];
 907         u8         reserved_at_216[0x1];
 908         u8         sho[0x1];
 909         u8         tph[0x1];
 910         u8         rf[0x1];
 911         u8         dct[0x1];
 912         u8         qos[0x1];
 913         u8         eth_net_offloads[0x1];
 914         u8         roce[0x1];
 915         u8         atomic[0x1];
 916         u8         reserved_at_21f[0x1];
 917
 918         u8         cq_oi[0x1];
 919         u8         cq_resize[0x1];
 920         u8         cq_moderation[0x1];
 921         u8         reserved_at_223[0x3];
 922         u8         cq_eq_remap[0x1];
 923         u8         pg[0x1];
 924         u8         block_lb_mc[0x1];
 925         u8         reserved_at_229[0x1];
 926         u8         scqe_break_moderation[0x1];
 927         u8         cq_period_start_from_cqe[0x1];
 928         u8         cd[0x1];
 929         u8         reserved_at_22d[0x1];
 930         u8         apm[0x1];
 931         u8         vector_calc[0x1];
 932         u8         umr_ptr_rlky[0x1];
 933         u8         imaicl[0x1];
 934         u8         reserved_at_232[0x4];
 935         u8         qkv[0x1];
 936         u8         pkv[0x1];
 937         u8         set_deth_sqpn[0x1];
 938         u8         reserved_at_239[0x3];
 939         u8         xrc[0x1];
 940         u8         ud[0x1];
 941         u8         uc[0x1];
 942         u8         rc[0x1];
 943
 944         u8         uar_4k[0x1];
 945         u8         reserved_at_241[0x9];
 946         u8         uar_sz[0x6];
 947         u8         reserved_at_250[0x8];
 948         u8         log_pg_sz[0x8];
 949
 950         u8         bf[0x1];
 951         u8         driver_version[0x1];
 952         u8         pad_tx_eth_packet[0x1];
 953         u8         reserved_at_263[0x8];
 954         u8         log_bf_reg_size[0x5];
 955
 956         u8         reserved_at_270[0xb];
 957         u8         lag_master[0x1];
 958         u8         num_lag_ports[0x4];
 959
 960         u8         reserved_at_280[0x10];
 961         u8         max_wqe_sz_sq[0x10];
 962
 963         u8         reserved_at_2a0[0x10];
 964         u8         max_wqe_sz_rq[0x10];
 965
 966         u8         reserved_at_2c0[0x10];
 967         u8         max_wqe_sz_sq_dc[0x10];
 968
 969         u8         reserved_at_2e0[0x7];
 970         u8         max_qp_mcg[0x19];
 971
 972         u8         reserved_at_300[0x18];
 973         u8         log_max_mcg[0x8];
 974
 975         u8         reserved_at_320[0x3];
 976         u8         log_max_transport_domain[0x5];
 977         u8         reserved_at_328[0x3];
 978         u8         log_max_pd[0x5];
 979         u8         reserved_at_330[0xb];
 980         u8         log_max_xrcd[0x5];
 981
 982         u8         reserved_at_340[0x8];
 983         u8         log_max_flow_counter_bulk[0x8];
 984         u8         max_flow_counter[0x10];
 985
 986
 987         u8         reserved_at_360[0x3];
 988         u8         log_max_rq[0x5];
 989         u8         reserved_at_368[0x3];
 990         u8         log_max_sq[0x5];
 991         u8         reserved_at_370[0x3];
 992         u8         log_max_tir[0x5];
 993         u8         reserved_at_378[0x3];
 994         u8         log_max_tis[0x5];
 995
 996         u8         basic_cyclic_rcv_wqe[0x1];
 997         u8         reserved_at_381[0x2];
 998         u8         log_max_rmp[0x5];
 999         u8         reserved_at_388[0x3];
1000         u8         log_max_rqt[0x5];
1001         u8         reserved_at_390[0x3];
1002         u8         log_max_rqt_size[0x5];
1003         u8         reserved_at_398[0x3];
1004         u8         log_max_tis_per_sq[0x5];
1005
1006         u8         reserved_at_3a0[0x3];
1007         u8         log_max_stride_sz_rq[0x5];
1008         u8         reserved_at_3a8[0x3];
1009         u8         log_min_stride_sz_rq[0x5];
1010         u8         reserved_at_3b0[0x3];
1011         u8         log_max_stride_sz_sq[0x5];
1012         u8         reserved_at_3b8[0x3];
1013         u8         log_min_stride_sz_sq[0x5];
1014
1015         u8         reserved_at_3c0[0x1b];
1016         u8         log_max_wq_sz[0x5];
1017
1018         u8         nic_vport_change_event[0x1];
1019         u8         reserved_at_3e1[0xa];
1020         u8         log_max_vlan_list[0x5];
1021         u8         reserved_at_3f0[0x3];
1022         u8         log_max_current_mc_list[0x5];
1023         u8         reserved_at_3f8[0x3];
1024         u8         log_max_current_uc_list[0x5];
1025
1026         u8         reserved_at_400[0x80];
1027
1028         u8         reserved_at_480[0x3];
1029         u8         log_max_l2_table[0x5];
1030         u8         reserved_at_488[0x8];
1031         u8         log_uar_page_sz[0x10];
1032
1033         u8         reserved_at_4a0[0x20];
1034         u8         device_frequency_mhz[0x20];
1035         u8         device_frequency_khz[0x20];
1036
1037         u8         reserved_at_500[0x20];
1038         u8         num_of_uars_per_page[0x20];
1039         u8         reserved_at_540[0x40];
1040
1041         u8         reserved_at_580[0x3f];
1042         u8         cqe_compression[0x1];
1043
1044         u8         cqe_compression_timeout[0x10];
1045         u8         cqe_compression_max_num[0x10];
1046
1047         u8         reserved_at_5e0[0x10];
1048         u8         tag_matching[0x1];
1049         u8         rndv_offload_rc[0x1];
1050         u8         rndv_offload_dc[0x1];
1051         u8         log_tag_matching_list_sz[0x5];
1052         u8         reserved_at_5f8[0x3];
1053         u8         log_max_xrq[0x5];
1054
1055         u8         reserved_at_600[0x200];
1056 };
1057
1058 enum mlx5_flow_destination_type {
1059         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1060         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1061         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1062
1063         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1064 };
1065
1066 struct mlx5_ifc_dest_format_struct_bits {
1067         u8         destination_type[0x8];
1068         u8         destination_id[0x18];
1069
1070         u8         reserved_at_20[0x20];
1071 };
1072
1073 struct mlx5_ifc_flow_counter_list_bits {
1074         u8         clear[0x1];
1075         u8         num_of_counters[0xf];
1076         u8         flow_counter_id[0x10];
1077
1078         u8         reserved_at_20[0x20];
1079 };
1080
1081 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1082         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1083         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1084         u8         reserved_at_0[0x40];
1085 };
1086
1087 struct mlx5_ifc_fte_match_param_bits {
1088         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1089
1090         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1091
1092         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1093
1094         u8         reserved_at_600[0xa00];
1095 };
1096
1097 enum {
1098         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1099         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1100         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1101         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1102         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1103 };
1104
1105 struct mlx5_ifc_rx_hash_field_select_bits {
1106         u8         l3_prot_type[0x1];
1107         u8         l4_prot_type[0x1];
1108         u8         selected_fields[0x1e];
1109 };
1110
1111 enum {
1112         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1113         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1114 };
1115
1116 enum {
1117         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1118         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1119 };
1120
1121 struct mlx5_ifc_wq_bits {
1122         u8         wq_type[0x4];
1123         u8         wq_signature[0x1];
1124         u8         end_padding_mode[0x2];
1125         u8         cd_slave[0x1];
1126         u8         reserved_at_8[0x18];
1127
1128         u8         hds_skip_first_sge[0x1];
1129         u8         log2_hds_buf_size[0x3];
1130         u8         reserved_at_24[0x7];
1131         u8         page_offset[0x5];
1132         u8         lwm[0x10];
1133
1134         u8         reserved_at_40[0x8];
1135         u8         pd[0x18];
1136
1137         u8         reserved_at_60[0x8];
1138         u8         uar_page[0x18];
1139
1140         u8         dbr_addr[0x40];
1141
1142         u8         hw_counter[0x20];
1143
1144         u8         sw_counter[0x20];
1145
1146         u8         reserved_at_100[0xc];
1147         u8         log_wq_stride[0x4];
1148         u8         reserved_at_110[0x3];
1149         u8         log_wq_pg_sz[0x5];
1150         u8         reserved_at_118[0x3];
1151         u8         log_wq_sz[0x5];
1152
1153         u8         reserved_at_120[0x15];
1154         u8         log_wqe_num_of_strides[0x3];
1155         u8         two_byte_shift_en[0x1];
1156         u8         reserved_at_139[0x4];
1157         u8         log_wqe_stride_size[0x3];
1158
1159         u8         reserved_at_140[0x4c0];
1160
1161         struct mlx5_ifc_cmd_pas_bits pas[0];
1162 };
1163
1164 struct mlx5_ifc_rq_num_bits {
1165         u8         reserved_at_0[0x8];
1166         u8         rq_num[0x18];
1167 };
1168
1169 struct mlx5_ifc_mac_address_layout_bits {
1170         u8         reserved_at_0[0x10];
1171         u8         mac_addr_47_32[0x10];
1172
1173         u8         mac_addr_31_0[0x20];
1174 };
1175
1176 struct mlx5_ifc_vlan_layout_bits {
1177         u8         reserved_at_0[0x14];
1178         u8         vlan[0x0c];
1179
1180         u8         reserved_at_20[0x20];
1181 };
1182
1183 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1184         u8         reserved_at_0[0xa0];
1185
1186         u8         min_time_between_cnps[0x20];
1187
1188         u8         reserved_at_c0[0x12];
1189         u8         cnp_dscp[0x6];
1190         u8         reserved_at_d8[0x5];
1191         u8         cnp_802p_prio[0x3];
1192
1193         u8         reserved_at_e0[0x720];
1194 };
1195
1196 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1197         u8         reserved_at_0[0x60];
1198
1199         u8         reserved_at_60[0x4];
1200         u8         clamp_tgt_rate[0x1];
1201         u8         reserved_at_65[0x3];
1202         u8         clamp_tgt_rate_after_time_inc[0x1];
1203         u8         reserved_at_69[0x17];
1204
1205         u8         reserved_at_80[0x20];
1206
1207         u8         rpg_time_reset[0x20];
1208
1209         u8         rpg_byte_reset[0x20];
1210
1211         u8         rpg_threshold[0x20];
1212
1213         u8         rpg_max_rate[0x20];
1214
1215         u8         rpg_ai_rate[0x20];
1216
1217         u8         rpg_hai_rate[0x20];
1218
1219         u8         rpg_gd[0x20];
1220
1221         u8         rpg_min_dec_fac[0x20];
1222
1223         u8         rpg_min_rate[0x20];
1224
1225         u8         reserved_at_1c0[0xe0];
1226
1227         u8         rate_to_set_on_first_cnp[0x20];
1228
1229         u8         dce_tcp_g[0x20];
1230
1231         u8         dce_tcp_rtt[0x20];
1232
1233         u8         rate_reduce_monitor_period[0x20];
1234
1235         u8         reserved_at_320[0x20];
1236
1237         u8         initial_alpha_value[0x20];
1238
1239         u8         reserved_at_360[0x4a0];
1240 };
1241
1242 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1243         u8         reserved_at_0[0x80];
1244
1245         u8         rppp_max_rps[0x20];
1246
1247         u8         rpg_time_reset[0x20];
1248
1249         u8         rpg_byte_reset[0x20];
1250
1251         u8         rpg_threshold[0x20];
1252
1253         u8         rpg_max_rate[0x20];
1254
1255         u8         rpg_ai_rate[0x20];
1256
1257         u8         rpg_hai_rate[0x20];
1258
1259         u8         rpg_gd[0x20];
1260
1261         u8         rpg_min_dec_fac[0x20];
1262
1263         u8         rpg_min_rate[0x20];
1264
1265         u8         reserved_at_1c0[0x640];
1266 };
1267
1268 enum {
1269         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1270         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1271         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1272 };
1273
1274 struct mlx5_ifc_resize_field_select_bits {
1275         u8         resize_field_select[0x20];
1276 };
1277
1278 enum {
1279         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1280         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1281         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1282         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1283 };
1284
1285 struct mlx5_ifc_modify_field_select_bits {
1286         u8         modify_field_select[0x20];
1287 };
1288
1289 struct mlx5_ifc_field_select_r_roce_np_bits {
1290         u8         field_select_r_roce_np[0x20];
1291 };
1292
1293 struct mlx5_ifc_field_select_r_roce_rp_bits {
1294         u8         field_select_r_roce_rp[0x20];
1295 };
1296
1297 enum {
1298         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1299         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1300         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1301         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1302         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1303         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1304         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1305         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1306         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1307         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1308 };
1309
1310 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1311         u8         field_select_8021qaurp[0x20];
1312 };
1313
1314 struct mlx5_ifc_phys_layer_cntrs_bits {
1315         u8         time_since_last_clear_high[0x20];
1316
1317         u8         time_since_last_clear_low[0x20];
1318
1319         u8         symbol_errors_high[0x20];
1320
1321         u8         symbol_errors_low[0x20];
1322
1323         u8         sync_headers_errors_high[0x20];
1324
1325         u8         sync_headers_errors_low[0x20];
1326
1327         u8         edpl_bip_errors_lane0_high[0x20];
1328
1329         u8         edpl_bip_errors_lane0_low[0x20];
1330
1331         u8         edpl_bip_errors_lane1_high[0x20];
1332
1333         u8         edpl_bip_errors_lane1_low[0x20];
1334
1335         u8         edpl_bip_errors_lane2_high[0x20];
1336
1337         u8         edpl_bip_errors_lane2_low[0x20];
1338
1339         u8         edpl_bip_errors_lane3_high[0x20];
1340
1341         u8         edpl_bip_errors_lane3_low[0x20];
1342
1343         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1344
1345         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1346
1347         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1348
1349         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1350
1351         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1352
1353         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1354
1355         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1356
1357         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1358
1359         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1360
1361         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1362
1363         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1364
1365         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1366
1367         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1368
1369         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1370
1371         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1372
1373         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1374
1375         u8         rs_fec_corrected_blocks_high[0x20];
1376
1377         u8         rs_fec_corrected_blocks_low[0x20];
1378
1379         u8         rs_fec_uncorrectable_blocks_high[0x20];
1380
1381         u8         rs_fec_uncorrectable_blocks_low[0x20];
1382
1383         u8         rs_fec_no_errors_blocks_high[0x20];
1384
1385         u8         rs_fec_no_errors_blocks_low[0x20];
1386
1387         u8         rs_fec_single_error_blocks_high[0x20];
1388
1389         u8         rs_fec_single_error_blocks_low[0x20];
1390
1391         u8         rs_fec_corrected_symbols_total_high[0x20];
1392
1393         u8         rs_fec_corrected_symbols_total_low[0x20];
1394
1395         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1396
1397         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1398
1399         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1400
1401         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1402
1403         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1404
1405         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1406
1407         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1408
1409         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1410
1411         u8         link_down_events[0x20];
1412
1413         u8         successful_recovery_events[0x20];
1414
1415         u8         reserved_at_640[0x180];
1416 };
1417
1418 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1419         u8         time_since_last_clear_high[0x20];
1420
1421         u8         time_since_last_clear_low[0x20];
1422
1423         u8         phy_received_bits_high[0x20];
1424
1425         u8         phy_received_bits_low[0x20];
1426
1427         u8         phy_symbol_errors_high[0x20];
1428
1429         u8         phy_symbol_errors_low[0x20];
1430
1431         u8         phy_corrected_bits_high[0x20];
1432
1433         u8         phy_corrected_bits_low[0x20];
1434
1435         u8         phy_corrected_bits_lane0_high[0x20];
1436
1437         u8         phy_corrected_bits_lane0_low[0x20];
1438
1439         u8         phy_corrected_bits_lane1_high[0x20];
1440
1441         u8         phy_corrected_bits_lane1_low[0x20];
1442
1443         u8         phy_corrected_bits_lane2_high[0x20];
1444
1445         u8         phy_corrected_bits_lane2_low[0x20];
1446
1447         u8         phy_corrected_bits_lane3_high[0x20];
1448
1449         u8         phy_corrected_bits_lane3_low[0x20];
1450
1451         u8         reserved_at_200[0x5c0];
1452 };
1453
1454 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1455         u8         symbol_error_counter[0x10];
1456
1457         u8         link_error_recovery_counter[0x8];
1458
1459         u8         link_downed_counter[0x8];
1460
1461         u8         port_rcv_errors[0x10];
1462
1463         u8         port_rcv_remote_physical_errors[0x10];
1464
1465         u8         port_rcv_switch_relay_errors[0x10];
1466
1467         u8         port_xmit_discards[0x10];
1468
1469         u8         port_xmit_constraint_errors[0x8];
1470
1471         u8         port_rcv_constraint_errors[0x8];
1472
1473         u8         reserved_at_70[0x8];
1474
1475         u8         link_overrun_errors[0x8];
1476
1477         u8         reserved_at_80[0x10];
1478
1479         u8         vl_15_dropped[0x10];
1480
1481         u8         reserved_at_a0[0x80];
1482
1483         u8         port_xmit_wait[0x20];
1484 };
1485
1486 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1487         u8         transmit_queue_high[0x20];
1488
1489         u8         transmit_queue_low[0x20];
1490
1491         u8         reserved_at_40[0x780];
1492 };
1493
1494 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1495         u8         rx_octets_high[0x20];
1496
1497         u8         rx_octets_low[0x20];
1498
1499         u8         reserved_at_40[0xc0];
1500
1501         u8         rx_frames_high[0x20];
1502
1503         u8         rx_frames_low[0x20];
1504
1505         u8         tx_octets_high[0x20];
1506
1507         u8         tx_octets_low[0x20];
1508
1509         u8         reserved_at_180[0xc0];
1510
1511         u8         tx_frames_high[0x20];
1512
1513         u8         tx_frames_low[0x20];
1514
1515         u8         rx_pause_high[0x20];
1516
1517         u8         rx_pause_low[0x20];
1518
1519         u8         rx_pause_duration_high[0x20];
1520
1521         u8         rx_pause_duration_low[0x20];
1522
1523         u8         tx_pause_high[0x20];
1524
1525         u8         tx_pause_low[0x20];
1526
1527         u8         tx_pause_duration_high[0x20];
1528
1529         u8         tx_pause_duration_low[0x20];
1530
1531         u8         rx_pause_transition_high[0x20];
1532
1533         u8         rx_pause_transition_low[0x20];
1534
1535         u8         reserved_at_3c0[0x400];
1536 };
1537
1538 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1539         u8         port_transmit_wait_high[0x20];
1540
1541         u8         port_transmit_wait_low[0x20];
1542
1543         u8         reserved_at_40[0x780];
1544 };
1545
1546 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1547         u8         dot3stats_alignment_errors_high[0x20];
1548
1549         u8         dot3stats_alignment_errors_low[0x20];
1550
1551         u8         dot3stats_fcs_errors_high[0x20];
1552
1553         u8         dot3stats_fcs_errors_low[0x20];
1554
1555         u8         dot3stats_single_collision_frames_high[0x20];
1556
1557         u8         dot3stats_single_collision_frames_low[0x20];
1558
1559         u8         dot3stats_multiple_collision_frames_high[0x20];
1560
1561         u8         dot3stats_multiple_collision_frames_low[0x20];
1562
1563         u8         dot3stats_sqe_test_errors_high[0x20];
1564
1565         u8         dot3stats_sqe_test_errors_low[0x20];
1566
1567         u8         dot3stats_deferred_transmissions_high[0x20];
1568
1569         u8         dot3stats_deferred_transmissions_low[0x20];
1570
1571         u8         dot3stats_late_collisions_high[0x20];
1572
1573         u8         dot3stats_late_collisions_low[0x20];
1574
1575         u8         dot3stats_excessive_collisions_high[0x20];
1576
1577         u8         dot3stats_excessive_collisions_low[0x20];
1578
1579         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1580
1581         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1582
1583         u8         dot3stats_carrier_sense_errors_high[0x20];
1584
1585         u8         dot3stats_carrier_sense_errors_low[0x20];
1586
1587         u8         dot3stats_frame_too_longs_high[0x20];
1588
1589         u8         dot3stats_frame_too_longs_low[0x20];
1590
1591         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1592
1593         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1594
1595         u8         dot3stats_symbol_errors_high[0x20];
1596
1597         u8         dot3stats_symbol_errors_low[0x20];
1598
1599         u8         dot3control_in_unknown_opcodes_high[0x20];
1600
1601         u8         dot3control_in_unknown_opcodes_low[0x20];
1602
1603         u8         dot3in_pause_frames_high[0x20];
1604
1605         u8         dot3in_pause_frames_low[0x20];
1606
1607         u8         dot3out_pause_frames_high[0x20];
1608
1609         u8         dot3out_pause_frames_low[0x20];
1610
1611         u8         reserved_at_400[0x3c0];
1612 };
1613
1614 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1615         u8         ether_stats_drop_events_high[0x20];
1616
1617         u8         ether_stats_drop_events_low[0x20];
1618
1619         u8         ether_stats_octets_high[0x20];
1620
1621         u8         ether_stats_octets_low[0x20];
1622
1623         u8         ether_stats_pkts_high[0x20];
1624
1625         u8         ether_stats_pkts_low[0x20];
1626
1627         u8         ether_stats_broadcast_pkts_high[0x20];
1628
1629         u8         ether_stats_broadcast_pkts_low[0x20];
1630
1631         u8         ether_stats_multicast_pkts_high[0x20];
1632
1633         u8         ether_stats_multicast_pkts_low[0x20];
1634
1635         u8         ether_stats_crc_align_errors_high[0x20];
1636
1637         u8         ether_stats_crc_align_errors_low[0x20];
1638
1639         u8         ether_stats_undersize_pkts_high[0x20];
1640
1641         u8         ether_stats_undersize_pkts_low[0x20];
1642
1643         u8         ether_stats_oversize_pkts_high[0x20];
1644
1645         u8         ether_stats_oversize_pkts_low[0x20];
1646
1647         u8         ether_stats_fragments_high[0x20];
1648
1649         u8         ether_stats_fragments_low[0x20];
1650
1651         u8         ether_stats_jabbers_high[0x20];
1652
1653         u8         ether_stats_jabbers_low[0x20];
1654
1655         u8         ether_stats_collisions_high[0x20];
1656
1657         u8         ether_stats_collisions_low[0x20];
1658
1659         u8         ether_stats_pkts64octets_high[0x20];
1660
1661         u8         ether_stats_pkts64octets_low[0x20];
1662
1663         u8         ether_stats_pkts65to127octets_high[0x20];
1664
1665         u8         ether_stats_pkts65to127octets_low[0x20];
1666
1667         u8         ether_stats_pkts128to255octets_high[0x20];
1668
1669         u8         ether_stats_pkts128to255octets_low[0x20];
1670
1671         u8         ether_stats_pkts256to511octets_high[0x20];
1672
1673         u8         ether_stats_pkts256to511octets_low[0x20];
1674
1675         u8         ether_stats_pkts512to1023octets_high[0x20];
1676
1677         u8         ether_stats_pkts512to1023octets_low[0x20];
1678
1679         u8         ether_stats_pkts1024to1518octets_high[0x20];
1680
1681         u8         ether_stats_pkts1024to1518octets_low[0x20];
1682
1683         u8         ether_stats_pkts1519to2047octets_high[0x20];
1684
1685         u8         ether_stats_pkts1519to2047octets_low[0x20];
1686
1687         u8         ether_stats_pkts2048to4095octets_high[0x20];
1688
1689         u8         ether_stats_pkts2048to4095octets_low[0x20];
1690
1691         u8         ether_stats_pkts4096to8191octets_high[0x20];
1692
1693         u8         ether_stats_pkts4096to8191octets_low[0x20];
1694
1695         u8         ether_stats_pkts8192to10239octets_high[0x20];
1696
1697         u8         ether_stats_pkts8192to10239octets_low[0x20];
1698
1699         u8         reserved_at_540[0x280];
1700 };
1701
1702 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1703         u8         if_in_octets_high[0x20];
1704
1705         u8         if_in_octets_low[0x20];
1706
1707         u8         if_in_ucast_pkts_high[0x20];
1708
1709         u8         if_in_ucast_pkts_low[0x20];
1710
1711         u8         if_in_discards_high[0x20];
1712
1713         u8         if_in_discards_low[0x20];
1714
1715         u8         if_in_errors_high[0x20];
1716
1717         u8         if_in_errors_low[0x20];
1718
1719         u8         if_in_unknown_protos_high[0x20];
1720
1721         u8         if_in_unknown_protos_low[0x20];
1722
1723         u8         if_out_octets_high[0x20];
1724
1725         u8         if_out_octets_low[0x20];
1726
1727         u8         if_out_ucast_pkts_high[0x20];
1728
1729         u8         if_out_ucast_pkts_low[0x20];
1730
1731         u8         if_out_discards_high[0x20];
1732
1733         u8         if_out_discards_low[0x20];
1734
1735         u8         if_out_errors_high[0x20];
1736
1737         u8         if_out_errors_low[0x20];
1738
1739         u8         if_in_multicast_pkts_high[0x20];
1740
1741         u8         if_in_multicast_pkts_low[0x20];
1742
1743         u8         if_in_broadcast_pkts_high[0x20];
1744
1745         u8         if_in_broadcast_pkts_low[0x20];
1746
1747         u8         if_out_multicast_pkts_high[0x20];
1748
1749         u8         if_out_multicast_pkts_low[0x20];
1750
1751         u8         if_out_broadcast_pkts_high[0x20];
1752
1753         u8         if_out_broadcast_pkts_low[0x20];
1754
1755         u8         reserved_at_340[0x480];
1756 };
1757
1758 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1759         u8         a_frames_transmitted_ok_high[0x20];
1760
1761         u8         a_frames_transmitted_ok_low[0x20];
1762
1763         u8         a_frames_received_ok_high[0x20];
1764
1765         u8         a_frames_received_ok_low[0x20];
1766
1767         u8         a_frame_check_sequence_errors_high[0x20];
1768
1769         u8         a_frame_check_sequence_errors_low[0x20];
1770
1771         u8         a_alignment_errors_high[0x20];
1772
1773         u8         a_alignment_errors_low[0x20];
1774
1775         u8         a_octets_transmitted_ok_high[0x20];
1776
1777         u8         a_octets_transmitted_ok_low[0x20];
1778
1779         u8         a_octets_received_ok_high[0x20];
1780
1781         u8         a_octets_received_ok_low[0x20];
1782
1783         u8         a_multicast_frames_xmitted_ok_high[0x20];
1784
1785         u8         a_multicast_frames_xmitted_ok_low[0x20];
1786
1787         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1788
1789         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1790
1791         u8         a_multicast_frames_received_ok_high[0x20];
1792
1793         u8         a_multicast_frames_received_ok_low[0x20];
1794
1795         u8         a_broadcast_frames_received_ok_high[0x20];
1796
1797         u8         a_broadcast_frames_received_ok_low[0x20];
1798
1799         u8         a_in_range_length_errors_high[0x20];
1800
1801         u8         a_in_range_length_errors_low[0x20];
1802
1803         u8         a_out_of_range_length_field_high[0x20];
1804
1805         u8         a_out_of_range_length_field_low[0x20];
1806
1807         u8         a_frame_too_long_errors_high[0x20];
1808
1809         u8         a_frame_too_long_errors_low[0x20];
1810
1811         u8         a_symbol_error_during_carrier_high[0x20];
1812
1813         u8         a_symbol_error_during_carrier_low[0x20];
1814
1815         u8         a_mac_control_frames_transmitted_high[0x20];
1816
1817         u8         a_mac_control_frames_transmitted_low[0x20];
1818
1819         u8         a_mac_control_frames_received_high[0x20];
1820
1821         u8         a_mac_control_frames_received_low[0x20];
1822
1823         u8         a_unsupported_opcodes_received_high[0x20];
1824
1825         u8         a_unsupported_opcodes_received_low[0x20];
1826
1827         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1828
1829         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1830
1831         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1832
1833         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1834
1835         u8         reserved_at_4c0[0x300];
1836 };
1837
1838 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1839         u8         life_time_counter_high[0x20];
1840
1841         u8         life_time_counter_low[0x20];
1842
1843         u8         rx_errors[0x20];
1844
1845         u8         tx_errors[0x20];
1846
1847         u8         l0_to_recovery_eieos[0x20];
1848
1849         u8         l0_to_recovery_ts[0x20];
1850
1851         u8         l0_to_recovery_framing[0x20];
1852
1853         u8         l0_to_recovery_retrain[0x20];
1854
1855         u8         crc_error_dllp[0x20];
1856
1857         u8         crc_error_tlp[0x20];
1858
1859         u8         reserved_at_140[0x680];
1860 };
1861
1862 struct mlx5_ifc_cmd_inter_comp_event_bits {
1863         u8         command_completion_vector[0x20];
1864
1865         u8         reserved_at_20[0xc0];
1866 };
1867
1868 struct mlx5_ifc_stall_vl_event_bits {
1869         u8         reserved_at_0[0x18];
1870         u8         port_num[0x1];
1871         u8         reserved_at_19[0x3];
1872         u8         vl[0x4];
1873
1874         u8         reserved_at_20[0xa0];
1875 };
1876
1877 struct mlx5_ifc_db_bf_congestion_event_bits {
1878         u8         event_subtype[0x8];
1879         u8         reserved_at_8[0x8];
1880         u8         congestion_level[0x8];
1881         u8         reserved_at_18[0x8];
1882
1883         u8         reserved_at_20[0xa0];
1884 };
1885
1886 struct mlx5_ifc_gpio_event_bits {
1887         u8         reserved_at_0[0x60];
1888
1889         u8         gpio_event_hi[0x20];
1890
1891         u8         gpio_event_lo[0x20];
1892
1893         u8         reserved_at_a0[0x40];
1894 };
1895
1896 struct mlx5_ifc_port_state_change_event_bits {
1897         u8         reserved_at_0[0x40];
1898
1899         u8         port_num[0x4];
1900         u8         reserved_at_44[0x1c];
1901
1902         u8         reserved_at_60[0x80];
1903 };
1904
1905 struct mlx5_ifc_dropped_packet_logged_bits {
1906         u8         reserved_at_0[0xe0];
1907 };
1908
1909 enum {
1910         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1911         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1912 };
1913
1914 struct mlx5_ifc_cq_error_bits {
1915         u8         reserved_at_0[0x8];
1916         u8         cqn[0x18];
1917
1918         u8         reserved_at_20[0x20];
1919
1920         u8         reserved_at_40[0x18];
1921         u8         syndrome[0x8];
1922
1923         u8         reserved_at_60[0x80];
1924 };
1925
1926 struct mlx5_ifc_rdma_page_fault_event_bits {
1927         u8         bytes_committed[0x20];
1928
1929         u8         r_key[0x20];
1930
1931         u8         reserved_at_40[0x10];
1932         u8         packet_len[0x10];
1933
1934         u8         rdma_op_len[0x20];
1935
1936         u8         rdma_va[0x40];
1937
1938         u8         reserved_at_c0[0x5];
1939         u8         rdma[0x1];
1940         u8         write[0x1];
1941         u8         requestor[0x1];
1942         u8         qp_number[0x18];
1943 };
1944
1945 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1946         u8         bytes_committed[0x20];
1947
1948         u8         reserved_at_20[0x10];
1949         u8         wqe_index[0x10];
1950
1951         u8         reserved_at_40[0x10];
1952         u8         len[0x10];
1953
1954         u8         reserved_at_60[0x60];
1955
1956         u8         reserved_at_c0[0x5];
1957         u8         rdma[0x1];
1958         u8         write_read[0x1];
1959         u8         requestor[0x1];
1960         u8         qpn[0x18];
1961 };
1962
1963 struct mlx5_ifc_qp_events_bits {
1964         u8         reserved_at_0[0xa0];
1965
1966         u8         type[0x8];
1967         u8         reserved_at_a8[0x18];
1968
1969         u8         reserved_at_c0[0x8];
1970         u8         qpn_rqn_sqn[0x18];
1971 };
1972
1973 struct mlx5_ifc_dct_events_bits {
1974         u8         reserved_at_0[0xc0];
1975
1976         u8         reserved_at_c0[0x8];
1977         u8         dct_number[0x18];
1978 };
1979
1980 struct mlx5_ifc_comp_event_bits {
1981         u8         reserved_at_0[0xc0];
1982
1983         u8         reserved_at_c0[0x8];
1984         u8         cq_number[0x18];
1985 };
1986
1987 enum {
1988         MLX5_QPC_STATE_RST        = 0x0,
1989         MLX5_QPC_STATE_INIT       = 0x1,
1990         MLX5_QPC_STATE_RTR        = 0x2,
1991         MLX5_QPC_STATE_RTS        = 0x3,
1992         MLX5_QPC_STATE_SQER       = 0x4,
1993         MLX5_QPC_STATE_ERR        = 0x6,
1994         MLX5_QPC_STATE_SQD        = 0x7,
1995         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1996 };
1997
1998 enum {
1999         MLX5_QPC_ST_RC            = 0x0,
2000         MLX5_QPC_ST_UC            = 0x1,
2001         MLX5_QPC_ST_UD            = 0x2,
2002         MLX5_QPC_ST_XRC           = 0x3,
2003         MLX5_QPC_ST_DCI           = 0x5,
2004         MLX5_QPC_ST_QP0           = 0x7,
2005         MLX5_QPC_ST_QP1           = 0x8,
2006         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2007         MLX5_QPC_ST_REG_UMR       = 0xc,
2008 };
2009
2010 enum {
2011         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2012         MLX5_QPC_PM_STATE_REARM     = 0x1,
2013         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2014         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2015 };
2016
2017 enum {
2018         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2019         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2020 };
2021
2022 enum {
2023         MLX5_QPC_MTU_256_BYTES        = 0x1,
2024         MLX5_QPC_MTU_512_BYTES        = 0x2,
2025         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2026         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2027         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2028         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2029 };
2030
2031 enum {
2032         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2033         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2034         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2035         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2036         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2037         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2038         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2039         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2040 };
2041
2042 enum {
2043         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2044         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2045         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2046 };
2047
2048 enum {
2049         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2050         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2051         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2052 };
2053
2054 struct mlx5_ifc_qpc_bits {
2055         u8         state[0x4];
2056         u8         lag_tx_port_affinity[0x4];
2057         u8         st[0x8];
2058         u8         reserved_at_10[0x3];
2059         u8         pm_state[0x2];
2060         u8         reserved_at_15[0x7];
2061         u8         end_padding_mode[0x2];
2062         u8         reserved_at_1e[0x2];
2063
2064         u8         wq_signature[0x1];
2065         u8         block_lb_mc[0x1];
2066         u8         atomic_like_write_en[0x1];
2067         u8         latency_sensitive[0x1];
2068         u8         reserved_at_24[0x1];
2069         u8         drain_sigerr[0x1];
2070         u8         reserved_at_26[0x2];
2071         u8         pd[0x18];
2072
2073         u8         mtu[0x3];
2074         u8         log_msg_max[0x5];
2075         u8         reserved_at_48[0x1];
2076         u8         log_rq_size[0x4];
2077         u8         log_rq_stride[0x3];
2078         u8         no_sq[0x1];
2079         u8         log_sq_size[0x4];
2080         u8         reserved_at_55[0x6];
2081         u8         rlky[0x1];
2082         u8         ulp_stateless_offload_mode[0x4];
2083
2084         u8         counter_set_id[0x8];
2085         u8         uar_page[0x18];
2086
2087         u8         reserved_at_80[0x8];
2088         u8         user_index[0x18];
2089
2090         u8         reserved_at_a0[0x3];
2091         u8         log_page_size[0x5];
2092         u8         remote_qpn[0x18];
2093
2094         struct mlx5_ifc_ads_bits primary_address_path;
2095
2096         struct mlx5_ifc_ads_bits secondary_address_path;
2097
2098         u8         log_ack_req_freq[0x4];
2099         u8         reserved_at_384[0x4];
2100         u8         log_sra_max[0x3];
2101         u8         reserved_at_38b[0x2];
2102         u8         retry_count[0x3];
2103         u8         rnr_retry[0x3];
2104         u8         reserved_at_393[0x1];
2105         u8         fre[0x1];
2106         u8         cur_rnr_retry[0x3];
2107         u8         cur_retry_count[0x3];
2108         u8         reserved_at_39b[0x5];
2109
2110         u8         reserved_at_3a0[0x20];
2111
2112         u8         reserved_at_3c0[0x8];
2113         u8         next_send_psn[0x18];
2114
2115         u8         reserved_at_3e0[0x8];
2116         u8         cqn_snd[0x18];
2117
2118         u8         reserved_at_400[0x8];
2119         u8         deth_sqpn[0x18];
2120
2121         u8         reserved_at_420[0x20];
2122
2123         u8         reserved_at_440[0x8];
2124         u8         last_acked_psn[0x18];
2125
2126         u8         reserved_at_460[0x8];
2127         u8         ssn[0x18];
2128
2129         u8         reserved_at_480[0x8];
2130         u8         log_rra_max[0x3];
2131         u8         reserved_at_48b[0x1];
2132         u8         atomic_mode[0x4];
2133         u8         rre[0x1];
2134         u8         rwe[0x1];
2135         u8         rae[0x1];
2136         u8         reserved_at_493[0x1];
2137         u8         page_offset[0x6];
2138         u8         reserved_at_49a[0x3];
2139         u8         cd_slave_receive[0x1];
2140         u8         cd_slave_send[0x1];
2141         u8         cd_master[0x1];
2142
2143         u8         reserved_at_4a0[0x3];
2144         u8         min_rnr_nak[0x5];
2145         u8         next_rcv_psn[0x18];
2146
2147         u8         reserved_at_4c0[0x8];
2148         u8         xrcd[0x18];
2149
2150         u8         reserved_at_4e0[0x8];
2151         u8         cqn_rcv[0x18];
2152
2153         u8         dbr_addr[0x40];
2154
2155         u8         q_key[0x20];
2156
2157         u8         reserved_at_560[0x5];
2158         u8         rq_type[0x3];
2159         u8         srqn_rmpn_xrqn[0x18];
2160
2161         u8         reserved_at_580[0x8];
2162         u8         rmsn[0x18];
2163
2164         u8         hw_sq_wqebb_counter[0x10];
2165         u8         sw_sq_wqebb_counter[0x10];
2166
2167         u8         hw_rq_counter[0x20];
2168
2169         u8         sw_rq_counter[0x20];
2170
2171         u8         reserved_at_600[0x20];
2172
2173         u8         reserved_at_620[0xf];
2174         u8         cgs[0x1];
2175         u8         cs_req[0x8];
2176         u8         cs_res[0x8];
2177
2178         u8         dc_access_key[0x40];
2179
2180         u8         reserved_at_680[0xc0];
2181 };
2182
2183 struct mlx5_ifc_roce_addr_layout_bits {
2184         u8         source_l3_address[16][0x8];
2185
2186         u8         reserved_at_80[0x3];
2187         u8         vlan_valid[0x1];
2188         u8         vlan_id[0xc];
2189         u8         source_mac_47_32[0x10];
2190
2191         u8         source_mac_31_0[0x20];
2192
2193         u8         reserved_at_c0[0x14];
2194         u8         roce_l3_type[0x4];
2195         u8         roce_version[0x8];
2196
2197         u8         reserved_at_e0[0x20];
2198 };
2199
2200 union mlx5_ifc_hca_cap_union_bits {
2201         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2202         struct mlx5_ifc_odp_cap_bits odp_cap;
2203         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2204         struct mlx5_ifc_roce_cap_bits roce_cap;
2205         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2206         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2207         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2208         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2209         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2210         struct mlx5_ifc_qos_cap_bits qos_cap;
2211         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2212         u8         reserved_at_0[0x8000];
2213 };
2214
2215 enum {
2216         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2217         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2218         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2219         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2220         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2221         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2222         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2223 };
2224
2225 struct mlx5_ifc_flow_context_bits {
2226         u8         reserved_at_0[0x20];
2227
2228         u8         group_id[0x20];
2229
2230         u8         reserved_at_40[0x8];
2231         u8         flow_tag[0x18];
2232
2233         u8         reserved_at_60[0x10];
2234         u8         action[0x10];
2235
2236         u8         reserved_at_80[0x8];
2237         u8         destination_list_size[0x18];
2238
2239         u8         reserved_at_a0[0x8];
2240         u8         flow_counter_list_size[0x18];
2241
2242         u8         encap_id[0x20];
2243
2244         u8         modify_header_id[0x20];
2245
2246         u8         reserved_at_100[0x100];
2247
2248         struct mlx5_ifc_fte_match_param_bits match_value;
2249
2250         u8         reserved_at_1200[0x600];
2251
2252         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2253 };
2254
2255 enum {
2256         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2257         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2258 };
2259
2260 struct mlx5_ifc_xrc_srqc_bits {
2261         u8         state[0x4];
2262         u8         log_xrc_srq_size[0x4];
2263         u8         reserved_at_8[0x18];
2264
2265         u8         wq_signature[0x1];
2266         u8         cont_srq[0x1];
2267         u8         reserved_at_22[0x1];
2268         u8         rlky[0x1];
2269         u8         basic_cyclic_rcv_wqe[0x1];
2270         u8         log_rq_stride[0x3];
2271         u8         xrcd[0x18];
2272
2273         u8         page_offset[0x6];
2274         u8         reserved_at_46[0x2];
2275         u8         cqn[0x18];
2276
2277         u8         reserved_at_60[0x20];
2278
2279         u8         user_index_equal_xrc_srqn[0x1];
2280         u8         reserved_at_81[0x1];
2281         u8         log_page_size[0x6];
2282         u8         user_index[0x18];
2283
2284         u8         reserved_at_a0[0x20];
2285
2286         u8         reserved_at_c0[0x8];
2287         u8         pd[0x18];
2288
2289         u8         lwm[0x10];
2290         u8         wqe_cnt[0x10];
2291
2292         u8         reserved_at_100[0x40];
2293
2294         u8         db_record_addr_h[0x20];
2295
2296         u8         db_record_addr_l[0x1e];
2297         u8         reserved_at_17e[0x2];
2298
2299         u8         reserved_at_180[0x80];
2300 };
2301
2302 struct mlx5_ifc_traffic_counter_bits {
2303         u8         packets[0x40];
2304
2305         u8         octets[0x40];
2306 };
2307
2308 struct mlx5_ifc_tisc_bits {
2309         u8         strict_lag_tx_port_affinity[0x1];
2310         u8         reserved_at_1[0x3];
2311         u8         lag_tx_port_affinity[0x04];
2312
2313         u8         reserved_at_8[0x4];
2314         u8         prio[0x4];
2315         u8         reserved_at_10[0x10];
2316
2317         u8         reserved_at_20[0x100];
2318
2319         u8         reserved_at_120[0x8];
2320         u8         transport_domain[0x18];
2321
2322         u8         reserved_at_140[0x8];
2323         u8         underlay_qpn[0x18];
2324         u8         reserved_at_160[0x3a0];
2325 };
2326
2327 enum {
2328         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2329         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2330 };
2331
2332 enum {
2333         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2334         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2335 };
2336
2337 enum {
2338         MLX5_RX_HASH_FN_NONE           = 0x0,
2339         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2340         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2341 };
2342
2343 enum {
2344         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2345         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2346 };
2347
2348 struct mlx5_ifc_tirc_bits {
2349         u8         reserved_at_0[0x20];
2350
2351         u8         disp_type[0x4];
2352         u8         reserved_at_24[0x1c];
2353
2354         u8         reserved_at_40[0x40];
2355
2356         u8         reserved_at_80[0x4];
2357         u8         lro_timeout_period_usecs[0x10];
2358         u8         lro_enable_mask[0x4];
2359         u8         lro_max_ip_payload_size[0x8];
2360
2361         u8         reserved_at_a0[0x40];
2362
2363         u8         reserved_at_e0[0x8];
2364         u8         inline_rqn[0x18];
2365
2366         u8         rx_hash_symmetric[0x1];
2367         u8         reserved_at_101[0x1];
2368         u8         tunneled_offload_en[0x1];
2369         u8         reserved_at_103[0x5];
2370         u8         indirect_table[0x18];
2371
2372         u8         rx_hash_fn[0x4];
2373         u8         reserved_at_124[0x2];
2374         u8         self_lb_block[0x2];
2375         u8         transport_domain[0x18];
2376
2377         u8         rx_hash_toeplitz_key[10][0x20];
2378
2379         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2380
2381         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2382
2383         u8         reserved_at_2c0[0x4c0];
2384 };
2385
2386 enum {
2387         MLX5_SRQC_STATE_GOOD   = 0x0,
2388         MLX5_SRQC_STATE_ERROR  = 0x1,
2389 };
2390
2391 struct mlx5_ifc_srqc_bits {
2392         u8         state[0x4];
2393         u8         log_srq_size[0x4];
2394         u8         reserved_at_8[0x18];
2395
2396         u8         wq_signature[0x1];
2397         u8         cont_srq[0x1];
2398         u8         reserved_at_22[0x1];
2399         u8         rlky[0x1];
2400         u8         reserved_at_24[0x1];
2401         u8         log_rq_stride[0x3];
2402         u8         xrcd[0x18];
2403
2404         u8         page_offset[0x6];
2405         u8         reserved_at_46[0x2];
2406         u8         cqn[0x18];
2407
2408         u8         reserved_at_60[0x20];
2409
2410         u8         reserved_at_80[0x2];
2411         u8         log_page_size[0x6];
2412         u8         reserved_at_88[0x18];
2413
2414         u8         reserved_at_a0[0x20];
2415
2416         u8         reserved_at_c0[0x8];
2417         u8         pd[0x18];
2418
2419         u8         lwm[0x10];
2420         u8         wqe_cnt[0x10];
2421
2422         u8         reserved_at_100[0x40];
2423
2424         u8         dbr_addr[0x40];
2425
2426         u8         reserved_at_180[0x80];
2427 };
2428
2429 enum {
2430         MLX5_SQC_STATE_RST  = 0x0,
2431         MLX5_SQC_STATE_RDY  = 0x1,
2432         MLX5_SQC_STATE_ERR  = 0x3,
2433 };
2434
2435 struct mlx5_ifc_sqc_bits {
2436         u8         rlky[0x1];
2437         u8         cd_master[0x1];
2438         u8         fre[0x1];
2439         u8         flush_in_error_en[0x1];
2440         u8         reserved_at_4[0x1];
2441         u8         min_wqe_inline_mode[0x3];
2442         u8         state[0x4];
2443         u8         reg_umr[0x1];
2444         u8         allow_swp[0x1];
2445         u8         reserved_at_e[0x12];
2446
2447         u8         reserved_at_20[0x8];
2448         u8         user_index[0x18];
2449
2450         u8         reserved_at_40[0x8];
2451         u8         cqn[0x18];
2452
2453         u8         reserved_at_60[0x90];
2454
2455         u8         packet_pacing_rate_limit_index[0x10];
2456         u8         tis_lst_sz[0x10];
2457         u8         reserved_at_110[0x10];
2458
2459         u8         reserved_at_120[0x40];
2460
2461         u8         reserved_at_160[0x8];
2462         u8         tis_num_0[0x18];
2463
2464         struct mlx5_ifc_wq_bits wq;
2465 };
2466
2467 enum {
2468         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2469         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2470         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2471         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2472 };
2473
2474 struct mlx5_ifc_scheduling_context_bits {
2475         u8         element_type[0x8];
2476         u8         reserved_at_8[0x18];
2477
2478         u8         element_attributes[0x20];
2479
2480         u8         parent_element_id[0x20];
2481
2482         u8         reserved_at_60[0x40];
2483
2484         u8         bw_share[0x20];
2485
2486         u8         max_average_bw[0x20];
2487
2488         u8         reserved_at_e0[0x120];
2489 };
2490
2491 struct mlx5_ifc_rqtc_bits {
2492         u8         reserved_at_0[0xa0];
2493
2494         u8         reserved_at_a0[0x10];
2495         u8         rqt_max_size[0x10];
2496
2497         u8         reserved_at_c0[0x10];
2498         u8         rqt_actual_size[0x10];
2499
2500         u8         reserved_at_e0[0x6a0];
2501
2502         struct mlx5_ifc_rq_num_bits rq_num[0];
2503 };
2504
2505 enum {
2506         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2507         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2508 };
2509
2510 enum {
2511         MLX5_RQC_STATE_RST  = 0x0,
2512         MLX5_RQC_STATE_RDY  = 0x1,
2513         MLX5_RQC_STATE_ERR  = 0x3,
2514 };
2515
2516 struct mlx5_ifc_rqc_bits {
2517         u8         rlky[0x1];
2518         u8         reserved_at_1[0x1];
2519         u8         scatter_fcs[0x1];
2520         u8         vsd[0x1];
2521         u8         mem_rq_type[0x4];
2522         u8         state[0x4];
2523         u8         reserved_at_c[0x1];
2524         u8         flush_in_error_en[0x1];
2525         u8         reserved_at_e[0x12];
2526
2527         u8         reserved_at_20[0x8];
2528         u8         user_index[0x18];
2529
2530         u8         reserved_at_40[0x8];
2531         u8         cqn[0x18];
2532
2533         u8         counter_set_id[0x8];
2534         u8         reserved_at_68[0x18];
2535
2536         u8         reserved_at_80[0x8];
2537         u8         rmpn[0x18];
2538
2539         u8         reserved_at_a0[0xe0];
2540
2541         struct mlx5_ifc_wq_bits wq;
2542 };
2543
2544 enum {
2545         MLX5_RMPC_STATE_RDY  = 0x1,
2546         MLX5_RMPC_STATE_ERR  = 0x3,
2547 };
2548
2549 struct mlx5_ifc_rmpc_bits {
2550         u8         reserved_at_0[0x8];
2551         u8         state[0x4];
2552         u8         reserved_at_c[0x14];
2553
2554         u8         basic_cyclic_rcv_wqe[0x1];
2555         u8         reserved_at_21[0x1f];
2556
2557         u8         reserved_at_40[0x140];
2558
2559         struct mlx5_ifc_wq_bits wq;
2560 };
2561
2562 struct mlx5_ifc_nic_vport_context_bits {
2563         u8         reserved_at_0[0x5];
2564         u8         min_wqe_inline_mode[0x3];
2565         u8         reserved_at_8[0x17];
2566         u8         roce_en[0x1];
2567
2568         u8         arm_change_event[0x1];
2569         u8         reserved_at_21[0x1a];
2570         u8         event_on_mtu[0x1];
2571         u8         event_on_promisc_change[0x1];
2572         u8         event_on_vlan_change[0x1];
2573         u8         event_on_mc_address_change[0x1];
2574         u8         event_on_uc_address_change[0x1];
2575
2576         u8         reserved_at_40[0xf0];
2577
2578         u8         mtu[0x10];
2579
2580         u8         system_image_guid[0x40];
2581         u8         port_guid[0x40];
2582         u8         node_guid[0x40];
2583
2584         u8         reserved_at_200[0x140];
2585         u8         qkey_violation_counter[0x10];
2586         u8         reserved_at_350[0x430];
2587
2588         u8         promisc_uc[0x1];
2589         u8         promisc_mc[0x1];
2590         u8         promisc_all[0x1];
2591         u8         reserved_at_783[0x2];
2592         u8         allowed_list_type[0x3];
2593         u8         reserved_at_788[0xc];
2594         u8         allowed_list_size[0xc];
2595
2596         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2597
2598         u8         reserved_at_7e0[0x20];
2599
2600         u8         current_uc_mac_address[0][0x40];
2601 };
2602
2603 enum {
2604         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2605         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2606         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2607         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2608 };
2609
2610 struct mlx5_ifc_mkc_bits {
2611         u8         reserved_at_0[0x1];
2612         u8         free[0x1];
2613         u8         reserved_at_2[0xd];
2614         u8         small_fence_on_rdma_read_response[0x1];
2615         u8         umr_en[0x1];
2616         u8         a[0x1];
2617         u8         rw[0x1];
2618         u8         rr[0x1];
2619         u8         lw[0x1];
2620         u8         lr[0x1];
2621         u8         access_mode[0x2];
2622         u8         reserved_at_18[0x8];
2623
2624         u8         qpn[0x18];
2625         u8         mkey_7_0[0x8];
2626
2627         u8         reserved_at_40[0x20];
2628
2629         u8         length64[0x1];
2630         u8         bsf_en[0x1];
2631         u8         sync_umr[0x1];
2632         u8         reserved_at_63[0x2];
2633         u8         expected_sigerr_count[0x1];
2634         u8         reserved_at_66[0x1];
2635         u8         en_rinval[0x1];
2636         u8         pd[0x18];
2637
2638         u8         start_addr[0x40];
2639
2640         u8         len[0x40];
2641
2642         u8         bsf_octword_size[0x20];
2643
2644         u8         reserved_at_120[0x80];
2645
2646         u8         translations_octword_size[0x20];
2647
2648         u8         reserved_at_1c0[0x1b];
2649         u8         log_page_size[0x5];
2650
2651         u8         reserved_at_1e0[0x20];
2652 };
2653
2654 struct mlx5_ifc_pkey_bits {
2655         u8         reserved_at_0[0x10];
2656         u8         pkey[0x10];
2657 };
2658
2659 struct mlx5_ifc_array128_auto_bits {
2660         u8         array128_auto[16][0x8];
2661 };
2662
2663 struct mlx5_ifc_hca_vport_context_bits {
2664         u8         field_select[0x20];
2665
2666         u8         reserved_at_20[0xe0];
2667
2668         u8         sm_virt_aware[0x1];
2669         u8         has_smi[0x1];
2670         u8         has_raw[0x1];
2671         u8         grh_required[0x1];
2672         u8         reserved_at_104[0xc];
2673         u8         port_physical_state[0x4];
2674         u8         vport_state_policy[0x4];
2675         u8         port_state[0x4];
2676         u8         vport_state[0x4];
2677
2678         u8         reserved_at_120[0x20];
2679
2680         u8         system_image_guid[0x40];
2681
2682         u8         port_guid[0x40];
2683
2684         u8         node_guid[0x40];
2685
2686         u8         cap_mask1[0x20];
2687
2688         u8         cap_mask1_field_select[0x20];
2689
2690         u8         cap_mask2[0x20];
2691
2692         u8         cap_mask2_field_select[0x20];
2693
2694         u8         reserved_at_280[0x80];
2695
2696         u8         lid[0x10];
2697         u8         reserved_at_310[0x4];
2698         u8         init_type_reply[0x4];
2699         u8         lmc[0x3];
2700         u8         subnet_timeout[0x5];
2701
2702         u8         sm_lid[0x10];
2703         u8         sm_sl[0x4];
2704         u8         reserved_at_334[0xc];
2705
2706         u8         qkey_violation_counter[0x10];
2707         u8         pkey_violation_counter[0x10];
2708
2709         u8         reserved_at_360[0xca0];
2710 };
2711
2712 struct mlx5_ifc_esw_vport_context_bits {
2713         u8         reserved_at_0[0x3];
2714         u8         vport_svlan_strip[0x1];
2715         u8         vport_cvlan_strip[0x1];
2716         u8         vport_svlan_insert[0x1];
2717         u8         vport_cvlan_insert[0x2];
2718         u8         reserved_at_8[0x18];
2719
2720         u8         reserved_at_20[0x20];
2721
2722         u8         svlan_cfi[0x1];
2723         u8         svlan_pcp[0x3];
2724         u8         svlan_id[0xc];
2725         u8         cvlan_cfi[0x1];
2726         u8         cvlan_pcp[0x3];
2727         u8         cvlan_id[0xc];
2728
2729         u8         reserved_at_60[0x7a0];
2730 };
2731
2732 enum {
2733         MLX5_EQC_STATUS_OK                = 0x0,
2734         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2735 };
2736
2737 enum {
2738         MLX5_EQC_ST_ARMED  = 0x9,
2739         MLX5_EQC_ST_FIRED  = 0xa,
2740 };
2741
2742 struct mlx5_ifc_eqc_bits {
2743         u8         status[0x4];
2744         u8         reserved_at_4[0x9];
2745         u8         ec[0x1];
2746         u8         oi[0x1];
2747         u8         reserved_at_f[0x5];
2748         u8         st[0x4];
2749         u8         reserved_at_18[0x8];
2750
2751         u8         reserved_at_20[0x20];
2752
2753         u8         reserved_at_40[0x14];
2754         u8         page_offset[0x6];
2755         u8         reserved_at_5a[0x6];
2756
2757         u8         reserved_at_60[0x3];
2758         u8         log_eq_size[0x5];
2759         u8         uar_page[0x18];
2760
2761         u8         reserved_at_80[0x20];
2762
2763         u8         reserved_at_a0[0x18];
2764         u8         intr[0x8];
2765
2766         u8         reserved_at_c0[0x3];
2767         u8         log_page_size[0x5];
2768         u8         reserved_at_c8[0x18];
2769
2770         u8         reserved_at_e0[0x60];
2771
2772         u8         reserved_at_140[0x8];
2773         u8         consumer_counter[0x18];
2774
2775         u8         reserved_at_160[0x8];
2776         u8         producer_counter[0x18];
2777
2778         u8         reserved_at_180[0x80];
2779 };
2780
2781 enum {
2782         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2783         MLX5_DCTC_STATE_DRAINING  = 0x1,
2784         MLX5_DCTC_STATE_DRAINED   = 0x2,
2785 };
2786
2787 enum {
2788         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2789         MLX5_DCTC_CS_RES_NA         = 0x1,
2790         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2791 };
2792
2793 enum {
2794         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2795         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2796         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2797         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2798         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2799 };
2800
2801 struct mlx5_ifc_dctc_bits {
2802         u8         reserved_at_0[0x4];
2803         u8         state[0x4];
2804         u8         reserved_at_8[0x18];
2805
2806         u8         reserved_at_20[0x8];
2807         u8         user_index[0x18];
2808
2809         u8         reserved_at_40[0x8];
2810         u8         cqn[0x18];
2811
2812         u8         counter_set_id[0x8];
2813         u8         atomic_mode[0x4];
2814         u8         rre[0x1];
2815         u8         rwe[0x1];
2816         u8         rae[0x1];
2817         u8         atomic_like_write_en[0x1];
2818         u8         latency_sensitive[0x1];
2819         u8         rlky[0x1];
2820         u8         free_ar[0x1];
2821         u8         reserved_at_73[0xd];
2822
2823         u8         reserved_at_80[0x8];
2824         u8         cs_res[0x8];
2825         u8         reserved_at_90[0x3];
2826         u8         min_rnr_nak[0x5];
2827         u8         reserved_at_98[0x8];
2828
2829         u8         reserved_at_a0[0x8];
2830         u8         srqn_xrqn[0x18];
2831
2832         u8         reserved_at_c0[0x8];
2833         u8         pd[0x18];
2834
2835         u8         tclass[0x8];
2836         u8         reserved_at_e8[0x4];
2837         u8         flow_label[0x14];
2838
2839         u8         dc_access_key[0x40];
2840
2841         u8         reserved_at_140[0x5];
2842         u8         mtu[0x3];
2843         u8         port[0x8];
2844         u8         pkey_index[0x10];
2845
2846         u8         reserved_at_160[0x8];
2847         u8         my_addr_index[0x8];
2848         u8         reserved_at_170[0x8];
2849         u8         hop_limit[0x8];
2850
2851         u8         dc_access_key_violation_count[0x20];
2852
2853         u8         reserved_at_1a0[0x14];
2854         u8         dei_cfi[0x1];
2855         u8         eth_prio[0x3];
2856         u8         ecn[0x2];
2857         u8         dscp[0x6];
2858
2859         u8         reserved_at_1c0[0x40];
2860 };
2861
2862 enum {
2863         MLX5_CQC_STATUS_OK             = 0x0,
2864         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2865         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2866 };
2867
2868 enum {
2869         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2870         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2871 };
2872
2873 enum {
2874         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2875         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2876         MLX5_CQC_ST_FIRED                                 = 0xa,
2877 };
2878
2879 enum {
2880         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2881         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2882         MLX5_CQ_PERIOD_NUM_MODES
2883 };
2884
2885 struct mlx5_ifc_cqc_bits {
2886         u8         status[0x4];
2887         u8         reserved_at_4[0x4];
2888         u8         cqe_sz[0x3];
2889         u8         cc[0x1];
2890         u8         reserved_at_c[0x1];
2891         u8         scqe_break_moderation_en[0x1];
2892         u8         oi[0x1];
2893         u8         cq_period_mode[0x2];
2894         u8         cqe_comp_en[0x1];
2895         u8         mini_cqe_res_format[0x2];
2896         u8         st[0x4];
2897         u8         reserved_at_18[0x8];
2898
2899         u8         reserved_at_20[0x20];
2900
2901         u8         reserved_at_40[0x14];
2902         u8         page_offset[0x6];
2903         u8         reserved_at_5a[0x6];
2904
2905         u8         reserved_at_60[0x3];
2906         u8         log_cq_size[0x5];
2907         u8         uar_page[0x18];
2908
2909         u8         reserved_at_80[0x4];
2910         u8         cq_period[0xc];
2911         u8         cq_max_count[0x10];
2912
2913         u8         reserved_at_a0[0x18];
2914         u8         c_eqn[0x8];
2915
2916         u8         reserved_at_c0[0x3];
2917         u8         log_page_size[0x5];
2918         u8         reserved_at_c8[0x18];
2919
2920         u8         reserved_at_e0[0x20];
2921
2922         u8         reserved_at_100[0x8];
2923         u8         last_notified_index[0x18];
2924
2925         u8         reserved_at_120[0x8];
2926         u8         last_solicit_index[0x18];
2927
2928         u8         reserved_at_140[0x8];
2929         u8         consumer_counter[0x18];
2930
2931         u8         reserved_at_160[0x8];
2932         u8         producer_counter[0x18];
2933
2934         u8         reserved_at_180[0x40];
2935
2936         u8         dbr_addr[0x40];
2937 };
2938
2939 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2940         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2941         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2942         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2943         u8         reserved_at_0[0x800];
2944 };
2945
2946 struct mlx5_ifc_query_adapter_param_block_bits {
2947         u8         reserved_at_0[0xc0];
2948
2949         u8         reserved_at_c0[0x8];
2950         u8         ieee_vendor_id[0x18];
2951
2952         u8         reserved_at_e0[0x10];
2953         u8         vsd_vendor_id[0x10];
2954
2955         u8         vsd[208][0x8];
2956
2957         u8         vsd_contd_psid[16][0x8];
2958 };
2959
2960 enum {
2961         MLX5_XRQC_STATE_GOOD   = 0x0,
2962         MLX5_XRQC_STATE_ERROR  = 0x1,
2963 };
2964
2965 enum {
2966         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2967         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2968 };
2969
2970 enum {
2971         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2972 };
2973
2974 struct mlx5_ifc_tag_matching_topology_context_bits {
2975         u8         log_matching_list_sz[0x4];
2976         u8         reserved_at_4[0xc];
2977         u8         append_next_index[0x10];
2978
2979         u8         sw_phase_cnt[0x10];
2980         u8         hw_phase_cnt[0x10];
2981
2982         u8         reserved_at_40[0x40];
2983 };
2984
2985 struct mlx5_ifc_xrqc_bits {
2986         u8         state[0x4];
2987         u8         rlkey[0x1];
2988         u8         reserved_at_5[0xf];
2989         u8         topology[0x4];
2990         u8         reserved_at_18[0x4];
2991         u8         offload[0x4];
2992
2993         u8         reserved_at_20[0x8];
2994         u8         user_index[0x18];
2995
2996         u8         reserved_at_40[0x8];
2997         u8         cqn[0x18];
2998
2999         u8         reserved_at_60[0xa0];
3000
3001         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3002
3003         u8         reserved_at_180[0x880];
3004
3005         struct mlx5_ifc_wq_bits wq;
3006 };
3007
3008 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3009         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3010         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3011         u8         reserved_at_0[0x20];
3012 };
3013
3014 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3015         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3016         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3017         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3018         u8         reserved_at_0[0x20];
3019 };
3020
3021 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3022         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3023         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3024         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3025         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3026         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3027         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3028         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3029         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3030         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3031         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3032         u8         reserved_at_0[0x7c0];
3033 };
3034
3035 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3036         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3037         u8         reserved_at_0[0x7c0];
3038 };
3039
3040 union mlx5_ifc_event_auto_bits {
3041         struct mlx5_ifc_comp_event_bits comp_event;
3042         struct mlx5_ifc_dct_events_bits dct_events;
3043         struct mlx5_ifc_qp_events_bits qp_events;
3044         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3045         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3046         struct mlx5_ifc_cq_error_bits cq_error;
3047         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3048         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3049         struct mlx5_ifc_gpio_event_bits gpio_event;
3050         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3051         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3052         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3053         u8         reserved_at_0[0xe0];
3054 };
3055
3056 struct mlx5_ifc_health_buffer_bits {
3057         u8         reserved_at_0[0x100];
3058
3059         u8         assert_existptr[0x20];
3060
3061         u8         assert_callra[0x20];
3062
3063         u8         reserved_at_140[0x40];
3064
3065         u8         fw_version[0x20];
3066
3067         u8         hw_id[0x20];
3068
3069         u8         reserved_at_1c0[0x20];
3070
3071         u8         irisc_index[0x8];
3072         u8         synd[0x8];
3073         u8         ext_synd[0x10];
3074 };
3075
3076 struct mlx5_ifc_register_loopback_control_bits {
3077         u8         no_lb[0x1];
3078         u8         reserved_at_1[0x7];
3079         u8         port[0x8];
3080         u8         reserved_at_10[0x10];
3081
3082         u8         reserved_at_20[0x60];
3083 };
3084
3085 struct mlx5_ifc_vport_tc_element_bits {
3086         u8         traffic_class[0x4];
3087         u8         reserved_at_4[0xc];
3088         u8         vport_number[0x10];
3089 };
3090
3091 struct mlx5_ifc_vport_element_bits {
3092         u8         reserved_at_0[0x10];
3093         u8         vport_number[0x10];
3094 };
3095
3096 enum {
3097         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3098         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3099         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3100 };
3101
3102 struct mlx5_ifc_tsar_element_bits {
3103         u8         reserved_at_0[0x8];
3104         u8         tsar_type[0x8];
3105         u8         reserved_at_10[0x10];
3106 };
3107
3108 enum {
3109         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3110         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3111 };
3112
3113 struct mlx5_ifc_teardown_hca_out_bits {
3114         u8         status[0x8];
3115         u8         reserved_at_8[0x18];
3116
3117         u8         syndrome[0x20];
3118
3119         u8         reserved_at_40[0x3f];
3120
3121         u8         force_state[0x1];
3122 };
3123
3124 enum {
3125         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3126         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3127 };
3128
3129 struct mlx5_ifc_teardown_hca_in_bits {
3130         u8         opcode[0x10];
3131         u8         reserved_at_10[0x10];
3132
3133         u8         reserved_at_20[0x10];
3134         u8         op_mod[0x10];
3135
3136         u8         reserved_at_40[0x10];
3137         u8         profile[0x10];
3138
3139         u8         reserved_at_60[0x20];
3140 };
3141
3142 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3143         u8         status[0x8];
3144         u8         reserved_at_8[0x18];
3145
3146         u8         syndrome[0x20];
3147
3148         u8         reserved_at_40[0x40];
3149 };
3150
3151 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3152         u8         opcode[0x10];
3153         u8         reserved_at_10[0x10];
3154
3155         u8         reserved_at_20[0x10];
3156         u8         op_mod[0x10];
3157
3158         u8         reserved_at_40[0x8];
3159         u8         qpn[0x18];
3160
3161         u8         reserved_at_60[0x20];
3162
3163         u8         opt_param_mask[0x20];
3164
3165         u8         reserved_at_a0[0x20];
3166
3167         struct mlx5_ifc_qpc_bits qpc;
3168
3169         u8         reserved_at_800[0x80];
3170 };
3171
3172 struct mlx5_ifc_sqd2rts_qp_out_bits {
3173         u8         status[0x8];
3174         u8         reserved_at_8[0x18];
3175
3176         u8         syndrome[0x20];
3177
3178         u8         reserved_at_40[0x40];
3179 };
3180
3181 struct mlx5_ifc_sqd2rts_qp_in_bits {
3182         u8         opcode[0x10];
3183         u8         reserved_at_10[0x10];
3184
3185         u8         reserved_at_20[0x10];
3186         u8         op_mod[0x10];
3187
3188         u8         reserved_at_40[0x8];
3189         u8         qpn[0x18];
3190
3191         u8         reserved_at_60[0x20];
3192
3193         u8         opt_param_mask[0x20];
3194
3195         u8         reserved_at_a0[0x20];
3196
3197         struct mlx5_ifc_qpc_bits qpc;
3198
3199         u8         reserved_at_800[0x80];
3200 };
3201
3202 struct mlx5_ifc_set_roce_address_out_bits {
3203         u8         status[0x8];
3204         u8         reserved_at_8[0x18];
3205
3206         u8         syndrome[0x20];
3207
3208         u8         reserved_at_40[0x40];
3209 };
3210
3211 struct mlx5_ifc_set_roce_address_in_bits {
3212         u8         opcode[0x10];
3213         u8         reserved_at_10[0x10];
3214
3215         u8         reserved_at_20[0x10];
3216         u8         op_mod[0x10];
3217
3218         u8         roce_address_index[0x10];
3219         u8         reserved_at_50[0x10];
3220
3221         u8         reserved_at_60[0x20];
3222
3223         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3224 };
3225
3226 struct mlx5_ifc_set_mad_demux_out_bits {
3227         u8         status[0x8];
3228         u8         reserved_at_8[0x18];
3229
3230         u8         syndrome[0x20];
3231
3232         u8         reserved_at_40[0x40];
3233 };
3234
3235 enum {
3236         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3237         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3238 };
3239
3240 struct mlx5_ifc_set_mad_demux_in_bits {
3241         u8         opcode[0x10];
3242         u8         reserved_at_10[0x10];
3243
3244         u8         reserved_at_20[0x10];
3245         u8         op_mod[0x10];
3246
3247         u8         reserved_at_40[0x20];
3248
3249         u8         reserved_at_60[0x6];
3250         u8         demux_mode[0x2];
3251         u8         reserved_at_68[0x18];
3252 };
3253
3254 struct mlx5_ifc_set_l2_table_entry_out_bits {
3255         u8         status[0x8];
3256         u8         reserved_at_8[0x18];
3257
3258         u8         syndrome[0x20];
3259
3260         u8         reserved_at_40[0x40];
3261 };
3262
3263 struct mlx5_ifc_set_l2_table_entry_in_bits {
3264         u8         opcode[0x10];
3265         u8         reserved_at_10[0x10];
3266
3267         u8         reserved_at_20[0x10];
3268         u8         op_mod[0x10];
3269
3270         u8         reserved_at_40[0x60];
3271
3272         u8         reserved_at_a0[0x8];
3273         u8         table_index[0x18];
3274
3275         u8         reserved_at_c0[0x20];
3276
3277         u8         reserved_at_e0[0x13];
3278         u8         vlan_valid[0x1];
3279         u8         vlan[0xc];
3280
3281         struct mlx5_ifc_mac_address_layout_bits mac_address;
3282
3283         u8         reserved_at_140[0xc0];
3284 };
3285
3286 struct mlx5_ifc_set_issi_out_bits {
3287         u8         status[0x8];
3288         u8         reserved_at_8[0x18];
3289
3290         u8         syndrome[0x20];
3291
3292         u8         reserved_at_40[0x40];
3293 };
3294
3295 struct mlx5_ifc_set_issi_in_bits {
3296         u8         opcode[0x10];
3297         u8         reserved_at_10[0x10];
3298
3299         u8         reserved_at_20[0x10];
3300         u8         op_mod[0x10];
3301
3302         u8         reserved_at_40[0x10];
3303         u8         current_issi[0x10];
3304
3305         u8         reserved_at_60[0x20];
3306 };
3307
3308 struct mlx5_ifc_set_hca_cap_out_bits {
3309         u8         status[0x8];
3310         u8         reserved_at_8[0x18];
3311
3312         u8         syndrome[0x20];
3313
3314         u8         reserved_at_40[0x40];
3315 };
3316
3317 struct mlx5_ifc_set_hca_cap_in_bits {
3318         u8         opcode[0x10];
3319         u8         reserved_at_10[0x10];
3320
3321         u8         reserved_at_20[0x10];
3322         u8         op_mod[0x10];
3323
3324         u8         reserved_at_40[0x40];
3325
3326         union mlx5_ifc_hca_cap_union_bits capability;
3327 };
3328
3329 enum {
3330         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3331         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3332         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3333         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3334 };
3335
3336 struct mlx5_ifc_set_fte_out_bits {
3337         u8         status[0x8];
3338         u8         reserved_at_8[0x18];
3339
3340         u8         syndrome[0x20];
3341
3342         u8         reserved_at_40[0x40];
3343 };
3344
3345 struct mlx5_ifc_set_fte_in_bits {
3346         u8         opcode[0x10];
3347         u8         reserved_at_10[0x10];
3348
3349         u8         reserved_at_20[0x10];
3350         u8         op_mod[0x10];
3351
3352         u8         other_vport[0x1];
3353         u8         reserved_at_41[0xf];
3354         u8         vport_number[0x10];
3355
3356         u8         reserved_at_60[0x20];
3357
3358         u8         table_type[0x8];
3359         u8         reserved_at_88[0x18];
3360
3361         u8         reserved_at_a0[0x8];
3362         u8         table_id[0x18];
3363
3364         u8         reserved_at_c0[0x18];
3365         u8         modify_enable_mask[0x8];
3366
3367         u8         reserved_at_e0[0x20];
3368
3369         u8         flow_index[0x20];
3370
3371         u8         reserved_at_120[0xe0];
3372
3373         struct mlx5_ifc_flow_context_bits flow_context;
3374 };
3375
3376 struct mlx5_ifc_rts2rts_qp_out_bits {
3377         u8         status[0x8];
3378         u8         reserved_at_8[0x18];
3379
3380         u8         syndrome[0x20];
3381
3382         u8         reserved_at_40[0x40];
3383 };
3384
3385 struct mlx5_ifc_rts2rts_qp_in_bits {
3386         u8         opcode[0x10];
3387         u8         reserved_at_10[0x10];
3388
3389         u8         reserved_at_20[0x10];
3390         u8         op_mod[0x10];
3391
3392         u8         reserved_at_40[0x8];
3393         u8         qpn[0x18];
3394
3395         u8         reserved_at_60[0x20];
3396
3397         u8         opt_param_mask[0x20];
3398
3399         u8         reserved_at_a0[0x20];
3400
3401         struct mlx5_ifc_qpc_bits qpc;
3402
3403         u8         reserved_at_800[0x80];
3404 };
3405
3406 struct mlx5_ifc_rtr2rts_qp_out_bits {
3407         u8         status[0x8];
3408         u8         reserved_at_8[0x18];
3409
3410         u8         syndrome[0x20];
3411
3412         u8         reserved_at_40[0x40];
3413 };
3414
3415 struct mlx5_ifc_rtr2rts_qp_in_bits {
3416         u8         opcode[0x10];
3417         u8         reserved_at_10[0x10];
3418
3419         u8         reserved_at_20[0x10];
3420         u8         op_mod[0x10];
3421
3422         u8         reserved_at_40[0x8];
3423         u8         qpn[0x18];
3424
3425         u8         reserved_at_60[0x20];
3426
3427         u8         opt_param_mask[0x20];
3428
3429         u8         reserved_at_a0[0x20];
3430
3431         struct mlx5_ifc_qpc_bits qpc;
3432
3433         u8         reserved_at_800[0x80];
3434 };
3435
3436 struct mlx5_ifc_rst2init_qp_out_bits {
3437         u8         status[0x8];
3438         u8         reserved_at_8[0x18];
3439
3440         u8         syndrome[0x20];
3441
3442         u8         reserved_at_40[0x40];
3443 };
3444
3445 struct mlx5_ifc_rst2init_qp_in_bits {
3446         u8         opcode[0x10];
3447         u8         reserved_at_10[0x10];
3448
3449         u8         reserved_at_20[0x10];
3450         u8         op_mod[0x10];
3451
3452         u8         reserved_at_40[0x8];
3453         u8         qpn[0x18];
3454
3455         u8         reserved_at_60[0x20];
3456
3457         u8         opt_param_mask[0x20];
3458
3459         u8         reserved_at_a0[0x20];
3460
3461         struct mlx5_ifc_qpc_bits qpc;
3462
3463         u8         reserved_at_800[0x80];
3464 };
3465
3466 struct mlx5_ifc_query_xrq_out_bits {
3467         u8         status[0x8];
3468         u8         reserved_at_8[0x18];
3469
3470         u8         syndrome[0x20];
3471
3472         u8         reserved_at_40[0x40];
3473
3474         struct mlx5_ifc_xrqc_bits xrq_context;
3475 };
3476
3477 struct mlx5_ifc_query_xrq_in_bits {
3478         u8         opcode[0x10];
3479         u8         reserved_at_10[0x10];
3480
3481         u8         reserved_at_20[0x10];
3482         u8         op_mod[0x10];
3483
3484         u8         reserved_at_40[0x8];
3485         u8         xrqn[0x18];
3486
3487         u8         reserved_at_60[0x20];
3488 };
3489
3490 struct mlx5_ifc_query_xrc_srq_out_bits {
3491         u8         status[0x8];
3492         u8         reserved_at_8[0x18];
3493
3494         u8         syndrome[0x20];
3495
3496         u8         reserved_at_40[0x40];
3497
3498         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3499
3500         u8         reserved_at_280[0x600];
3501
3502         u8         pas[0][0x40];
3503 };
3504
3505 struct mlx5_ifc_query_xrc_srq_in_bits {
3506         u8         opcode[0x10];
3507         u8         reserved_at_10[0x10];
3508
3509         u8         reserved_at_20[0x10];
3510         u8         op_mod[0x10];
3511
3512         u8         reserved_at_40[0x8];
3513         u8         xrc_srqn[0x18];
3514
3515         u8         reserved_at_60[0x20];
3516 };
3517
3518 enum {
3519         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3520         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3521 };
3522
3523 struct mlx5_ifc_query_vport_state_out_bits {
3524         u8         status[0x8];
3525         u8         reserved_at_8[0x18];
3526
3527         u8         syndrome[0x20];
3528
3529         u8         reserved_at_40[0x20];
3530
3531         u8         reserved_at_60[0x18];
3532         u8         admin_state[0x4];
3533         u8         state[0x4];
3534 };
3535
3536 enum {
3537         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3538         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3539 };
3540
3541 struct mlx5_ifc_query_vport_state_in_bits {
3542         u8         opcode[0x10];
3543         u8         reserved_at_10[0x10];
3544
3545         u8         reserved_at_20[0x10];
3546         u8         op_mod[0x10];
3547
3548         u8         other_vport[0x1];
3549         u8         reserved_at_41[0xf];
3550         u8         vport_number[0x10];
3551
3552         u8         reserved_at_60[0x20];
3553 };
3554
3555 struct mlx5_ifc_query_vport_counter_out_bits {
3556         u8         status[0x8];
3557         u8         reserved_at_8[0x18];
3558
3559         u8         syndrome[0x20];
3560
3561         u8         reserved_at_40[0x40];
3562
3563         struct mlx5_ifc_traffic_counter_bits received_errors;
3564
3565         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3566
3567         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3568
3569         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3570
3571         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3572
3573         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3574
3575         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3576
3577         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3578
3579         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3580
3581         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3582
3583         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3584
3585         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3586
3587         u8         reserved_at_680[0xa00];
3588 };
3589
3590 enum {
3591         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3592 };
3593
3594 struct mlx5_ifc_query_vport_counter_in_bits {
3595         u8         opcode[0x10];
3596         u8         reserved_at_10[0x10];
3597
3598         u8         reserved_at_20[0x10];
3599         u8         op_mod[0x10];
3600
3601         u8         other_vport[0x1];
3602         u8         reserved_at_41[0xb];
3603         u8         port_num[0x4];
3604         u8         vport_number[0x10];
3605
3606         u8         reserved_at_60[0x60];
3607
3608         u8         clear[0x1];
3609         u8         reserved_at_c1[0x1f];
3610
3611         u8         reserved_at_e0[0x20];
3612 };
3613
3614 struct mlx5_ifc_query_tis_out_bits {
3615         u8         status[0x8];
3616         u8         reserved_at_8[0x18];
3617
3618         u8         syndrome[0x20];
3619
3620         u8         reserved_at_40[0x40];
3621
3622         struct mlx5_ifc_tisc_bits tis_context;
3623 };
3624
3625 struct mlx5_ifc_query_tis_in_bits {
3626         u8         opcode[0x10];
3627         u8         reserved_at_10[0x10];
3628
3629         u8         reserved_at_20[0x10];
3630         u8         op_mod[0x10];
3631
3632         u8         reserved_at_40[0x8];
3633         u8         tisn[0x18];
3634
3635         u8         reserved_at_60[0x20];
3636 };
3637
3638 struct mlx5_ifc_query_tir_out_bits {
3639         u8         status[0x8];
3640         u8         reserved_at_8[0x18];
3641
3642         u8         syndrome[0x20];
3643
3644         u8         reserved_at_40[0xc0];
3645
3646         struct mlx5_ifc_tirc_bits tir_context;
3647 };
3648
3649 struct mlx5_ifc_query_tir_in_bits {
3650         u8         opcode[0x10];
3651         u8         reserved_at_10[0x10];
3652
3653         u8         reserved_at_20[0x10];
3654         u8         op_mod[0x10];
3655
3656         u8         reserved_at_40[0x8];
3657         u8         tirn[0x18];
3658
3659         u8         reserved_at_60[0x20];
3660 };
3661
3662 struct mlx5_ifc_query_srq_out_bits {
3663         u8         status[0x8];
3664         u8         reserved_at_8[0x18];
3665
3666         u8         syndrome[0x20];
3667
3668         u8         reserved_at_40[0x40];
3669
3670         struct mlx5_ifc_srqc_bits srq_context_entry;
3671
3672         u8         reserved_at_280[0x600];
3673
3674         u8         pas[0][0x40];
3675 };
3676
3677 struct mlx5_ifc_query_srq_in_bits {
3678         u8         opcode[0x10];
3679         u8         reserved_at_10[0x10];
3680
3681         u8         reserved_at_20[0x10];
3682         u8         op_mod[0x10];
3683
3684         u8         reserved_at_40[0x8];
3685         u8         srqn[0x18];
3686
3687         u8         reserved_at_60[0x20];
3688 };
3689
3690 struct mlx5_ifc_query_sq_out_bits {
3691         u8         status[0x8];
3692         u8         reserved_at_8[0x18];
3693
3694         u8         syndrome[0x20];
3695
3696         u8         reserved_at_40[0xc0];
3697
3698         struct mlx5_ifc_sqc_bits sq_context;
3699 };
3700
3701 struct mlx5_ifc_query_sq_in_bits {
3702         u8         opcode[0x10];
3703         u8         reserved_at_10[0x10];
3704
3705         u8         reserved_at_20[0x10];
3706         u8         op_mod[0x10];
3707
3708         u8         reserved_at_40[0x8];
3709         u8         sqn[0x18];
3710
3711         u8         reserved_at_60[0x20];
3712 };
3713
3714 struct mlx5_ifc_query_special_contexts_out_bits {
3715         u8         status[0x8];
3716         u8         reserved_at_8[0x18];
3717
3718         u8         syndrome[0x20];
3719
3720         u8         dump_fill_mkey[0x20];
3721
3722         u8         resd_lkey[0x20];
3723
3724         u8         null_mkey[0x20];
3725
3726         u8         reserved_at_a0[0x60];
3727 };
3728
3729 struct mlx5_ifc_query_special_contexts_in_bits {
3730         u8         opcode[0x10];
3731         u8         reserved_at_10[0x10];
3732
3733         u8         reserved_at_20[0x10];
3734         u8         op_mod[0x10];
3735
3736         u8         reserved_at_40[0x40];
3737 };
3738
3739 struct mlx5_ifc_query_scheduling_element_out_bits {
3740         u8         opcode[0x10];
3741         u8         reserved_at_10[0x10];
3742
3743         u8         reserved_at_20[0x10];
3744         u8         op_mod[0x10];
3745
3746         u8         reserved_at_40[0xc0];
3747
3748         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3749
3750         u8         reserved_at_300[0x100];
3751 };
3752
3753 enum {
3754         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3755 };
3756
3757 struct mlx5_ifc_query_scheduling_element_in_bits {
3758         u8         opcode[0x10];
3759         u8         reserved_at_10[0x10];
3760
3761         u8         reserved_at_20[0x10];
3762         u8         op_mod[0x10];
3763
3764         u8         scheduling_hierarchy[0x8];
3765         u8         reserved_at_48[0x18];
3766
3767         u8         scheduling_element_id[0x20];
3768
3769         u8         reserved_at_80[0x180];
3770 };
3771
3772 struct mlx5_ifc_query_rqt_out_bits {
3773         u8         status[0x8];
3774         u8         reserved_at_8[0x18];
3775
3776         u8         syndrome[0x20];
3777
3778         u8         reserved_at_40[0xc0];
3779
3780         struct mlx5_ifc_rqtc_bits rqt_context;
3781 };
3782
3783 struct mlx5_ifc_query_rqt_in_bits {
3784         u8         opcode[0x10];
3785         u8         reserved_at_10[0x10];
3786
3787         u8         reserved_at_20[0x10];
3788         u8         op_mod[0x10];
3789
3790         u8         reserved_at_40[0x8];
3791         u8         rqtn[0x18];
3792
3793         u8         reserved_at_60[0x20];
3794 };
3795
3796 struct mlx5_ifc_query_rq_out_bits {
3797         u8         status[0x8];
3798         u8         reserved_at_8[0x18];
3799
3800         u8         syndrome[0x20];
3801
3802         u8         reserved_at_40[0xc0];
3803
3804         struct mlx5_ifc_rqc_bits rq_context;
3805 };
3806
3807 struct mlx5_ifc_query_rq_in_bits {
3808         u8         opcode[0x10];
3809         u8         reserved_at_10[0x10];
3810
3811         u8         reserved_at_20[0x10];
3812         u8         op_mod[0x10];
3813
3814         u8         reserved_at_40[0x8];
3815         u8         rqn[0x18];
3816
3817         u8         reserved_at_60[0x20];
3818 };
3819
3820 struct mlx5_ifc_query_roce_address_out_bits {
3821         u8         status[0x8];
3822         u8         reserved_at_8[0x18];
3823
3824         u8         syndrome[0x20];
3825
3826         u8         reserved_at_40[0x40];
3827
3828         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3829 };
3830
3831 struct mlx5_ifc_query_roce_address_in_bits {
3832         u8         opcode[0x10];
3833         u8         reserved_at_10[0x10];
3834
3835         u8         reserved_at_20[0x10];
3836         u8         op_mod[0x10];
3837
3838         u8         roce_address_index[0x10];
3839         u8         reserved_at_50[0x10];
3840
3841         u8         reserved_at_60[0x20];
3842 };
3843
3844 struct mlx5_ifc_query_rmp_out_bits {
3845         u8         status[0x8];
3846         u8         reserved_at_8[0x18];
3847
3848         u8         syndrome[0x20];
3849
3850         u8         reserved_at_40[0xc0];
3851
3852         struct mlx5_ifc_rmpc_bits rmp_context;
3853 };
3854
3855 struct mlx5_ifc_query_rmp_in_bits {
3856         u8         opcode[0x10];
3857         u8         reserved_at_10[0x10];
3858
3859         u8         reserved_at_20[0x10];
3860         u8         op_mod[0x10];
3861
3862         u8         reserved_at_40[0x8];
3863         u8         rmpn[0x18];
3864
3865         u8         reserved_at_60[0x20];
3866 };
3867
3868 struct mlx5_ifc_query_qp_out_bits {
3869         u8         status[0x8];
3870         u8         reserved_at_8[0x18];
3871
3872         u8         syndrome[0x20];
3873
3874         u8         reserved_at_40[0x40];
3875
3876         u8         opt_param_mask[0x20];
3877
3878         u8         reserved_at_a0[0x20];
3879
3880         struct mlx5_ifc_qpc_bits qpc;
3881
3882         u8         reserved_at_800[0x80];
3883
3884         u8         pas[0][0x40];
3885 };
3886
3887 struct mlx5_ifc_query_qp_in_bits {
3888         u8         opcode[0x10];
3889         u8         reserved_at_10[0x10];
3890
3891         u8         reserved_at_20[0x10];
3892         u8         op_mod[0x10];
3893
3894         u8         reserved_at_40[0x8];
3895         u8         qpn[0x18];
3896
3897         u8         reserved_at_60[0x20];
3898 };
3899
3900 struct mlx5_ifc_query_q_counter_out_bits {
3901         u8         status[0x8];
3902         u8         reserved_at_8[0x18];
3903
3904         u8         syndrome[0x20];
3905
3906         u8         reserved_at_40[0x40];
3907
3908         u8         rx_write_requests[0x20];
3909
3910         u8         reserved_at_a0[0x20];
3911
3912         u8         rx_read_requests[0x20];
3913
3914         u8         reserved_at_e0[0x20];
3915
3916         u8         rx_atomic_requests[0x20];
3917
3918         u8         reserved_at_120[0x20];
3919
3920         u8         rx_dct_connect[0x20];
3921
3922         u8         reserved_at_160[0x20];
3923
3924         u8         out_of_buffer[0x20];
3925
3926         u8         reserved_at_1a0[0x20];
3927
3928         u8         out_of_sequence[0x20];
3929
3930         u8         reserved_at_1e0[0x20];
3931
3932         u8         duplicate_request[0x20];
3933
3934         u8         reserved_at_220[0x20];
3935
3936         u8         rnr_nak_retry_err[0x20];
3937
3938         u8         reserved_at_260[0x20];
3939
3940         u8         packet_seq_err[0x20];
3941
3942         u8         reserved_at_2a0[0x20];
3943
3944         u8         implied_nak_seq_err[0x20];
3945
3946         u8         reserved_at_2e0[0x20];
3947
3948         u8         local_ack_timeout_err[0x20];
3949
3950         u8         reserved_at_320[0x4e0];
3951 };
3952
3953 struct mlx5_ifc_query_q_counter_in_bits {
3954         u8         opcode[0x10];
3955         u8         reserved_at_10[0x10];
3956
3957         u8         reserved_at_20[0x10];
3958         u8         op_mod[0x10];
3959
3960         u8         reserved_at_40[0x80];
3961
3962         u8         clear[0x1];
3963         u8         reserved_at_c1[0x1f];
3964
3965         u8         reserved_at_e0[0x18];
3966         u8         counter_set_id[0x8];
3967 };
3968
3969 struct mlx5_ifc_query_pages_out_bits {
3970         u8         status[0x8];
3971         u8         reserved_at_8[0x18];
3972
3973         u8         syndrome[0x20];
3974
3975         u8         reserved_at_40[0x10];
3976         u8         function_id[0x10];
3977
3978         u8         num_pages[0x20];
3979 };
3980
3981 enum {
3982         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3983         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3984         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3985 };
3986
3987 struct mlx5_ifc_query_pages_in_bits {
3988         u8         opcode[0x10];
3989         u8         reserved_at_10[0x10];
3990
3991         u8         reserved_at_20[0x10];
3992         u8         op_mod[0x10];
3993
3994         u8         reserved_at_40[0x10];
3995         u8         function_id[0x10];
3996
3997         u8         reserved_at_60[0x20];
3998 };
3999
4000 struct mlx5_ifc_query_nic_vport_context_out_bits {
4001         u8         status[0x8];
4002         u8         reserved_at_8[0x18];
4003
4004         u8         syndrome[0x20];
4005
4006         u8         reserved_at_40[0x40];
4007
4008         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4009 };
4010
4011 struct mlx5_ifc_query_nic_vport_context_in_bits {
4012         u8         opcode[0x10];
4013         u8         reserved_at_10[0x10];
4014
4015         u8         reserved_at_20[0x10];
4016         u8         op_mod[0x10];
4017
4018         u8         other_vport[0x1];
4019         u8         reserved_at_41[0xf];
4020         u8         vport_number[0x10];
4021
4022         u8         reserved_at_60[0x5];
4023         u8         allowed_list_type[0x3];
4024         u8         reserved_at_68[0x18];
4025 };
4026
4027 struct mlx5_ifc_query_mkey_out_bits {
4028         u8         status[0x8];
4029         u8         reserved_at_8[0x18];
4030
4031         u8         syndrome[0x20];
4032
4033         u8         reserved_at_40[0x40];
4034
4035         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4036
4037         u8         reserved_at_280[0x600];
4038
4039         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4040
4041         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4042 };
4043
4044 struct mlx5_ifc_query_mkey_in_bits {
4045         u8         opcode[0x10];
4046         u8         reserved_at_10[0x10];
4047
4048         u8         reserved_at_20[0x10];
4049         u8         op_mod[0x10];
4050
4051         u8         reserved_at_40[0x8];
4052         u8         mkey_index[0x18];
4053
4054         u8         pg_access[0x1];
4055         u8         reserved_at_61[0x1f];
4056 };
4057
4058 struct mlx5_ifc_query_mad_demux_out_bits {
4059         u8         status[0x8];
4060         u8         reserved_at_8[0x18];
4061
4062         u8         syndrome[0x20];
4063
4064         u8         reserved_at_40[0x40];
4065
4066         u8         mad_dumux_parameters_block[0x20];
4067 };
4068
4069 struct mlx5_ifc_query_mad_demux_in_bits {
4070         u8         opcode[0x10];
4071         u8         reserved_at_10[0x10];
4072
4073         u8         reserved_at_20[0x10];
4074         u8         op_mod[0x10];
4075
4076         u8         reserved_at_40[0x40];
4077 };
4078
4079 struct mlx5_ifc_query_l2_table_entry_out_bits {
4080         u8         status[0x8];
4081         u8         reserved_at_8[0x18];
4082
4083         u8         syndrome[0x20];
4084
4085         u8         reserved_at_40[0xa0];
4086
4087         u8         reserved_at_e0[0x13];
4088         u8         vlan_valid[0x1];
4089         u8         vlan[0xc];
4090
4091         struct mlx5_ifc_mac_address_layout_bits mac_address;
4092
4093         u8         reserved_at_140[0xc0];
4094 };
4095
4096 struct mlx5_ifc_query_l2_table_entry_in_bits {
4097         u8         opcode[0x10];
4098         u8         reserved_at_10[0x10];
4099
4100         u8         reserved_at_20[0x10];
4101         u8         op_mod[0x10];
4102
4103         u8         reserved_at_40[0x60];
4104
4105         u8         reserved_at_a0[0x8];
4106         u8         table_index[0x18];
4107
4108         u8         reserved_at_c0[0x140];
4109 };
4110
4111 struct mlx5_ifc_query_issi_out_bits {
4112         u8         status[0x8];
4113         u8         reserved_at_8[0x18];
4114
4115         u8         syndrome[0x20];
4116
4117         u8         reserved_at_40[0x10];
4118         u8         current_issi[0x10];
4119
4120         u8         reserved_at_60[0xa0];
4121
4122         u8         reserved_at_100[76][0x8];
4123         u8         supported_issi_dw0[0x20];
4124 };
4125
4126 struct mlx5_ifc_query_issi_in_bits {
4127         u8         opcode[0x10];
4128         u8         reserved_at_10[0x10];
4129
4130         u8         reserved_at_20[0x10];
4131         u8         op_mod[0x10];
4132
4133         u8         reserved_at_40[0x40];
4134 };
4135
4136 struct mlx5_ifc_set_driver_version_out_bits {
4137         u8         status[0x8];
4138         u8         reserved_0[0x18];
4139
4140         u8         syndrome[0x20];
4141         u8         reserved_1[0x40];
4142 };
4143
4144 struct mlx5_ifc_set_driver_version_in_bits {
4145         u8         opcode[0x10];
4146         u8         reserved_0[0x10];
4147
4148         u8         reserved_1[0x10];
4149         u8         op_mod[0x10];
4150
4151         u8         reserved_2[0x40];
4152         u8         driver_version[64][0x8];
4153 };
4154
4155 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4156         u8         status[0x8];
4157         u8         reserved_at_8[0x18];
4158
4159         u8         syndrome[0x20];
4160
4161         u8         reserved_at_40[0x40];
4162
4163         struct mlx5_ifc_pkey_bits pkey[0];
4164 };
4165
4166 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4167         u8         opcode[0x10];
4168         u8         reserved_at_10[0x10];
4169
4170         u8         reserved_at_20[0x10];
4171         u8         op_mod[0x10];
4172
4173         u8         other_vport[0x1];
4174         u8         reserved_at_41[0xb];
4175         u8         port_num[0x4];
4176         u8         vport_number[0x10];
4177
4178         u8         reserved_at_60[0x10];
4179         u8         pkey_index[0x10];
4180 };
4181
4182 enum {
4183         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4184         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4185         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4186 };
4187
4188 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4189         u8         status[0x8];
4190         u8         reserved_at_8[0x18];
4191
4192         u8         syndrome[0x20];
4193
4194         u8         reserved_at_40[0x20];
4195
4196         u8         gids_num[0x10];
4197         u8         reserved_at_70[0x10];
4198
4199         struct mlx5_ifc_array128_auto_bits gid[0];
4200 };
4201
4202 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4203         u8         opcode[0x10];
4204         u8         reserved_at_10[0x10];
4205
4206         u8         reserved_at_20[0x10];
4207         u8         op_mod[0x10];
4208
4209         u8         other_vport[0x1];
4210         u8         reserved_at_41[0xb];
4211         u8         port_num[0x4];
4212         u8         vport_number[0x10];
4213
4214         u8         reserved_at_60[0x10];
4215         u8         gid_index[0x10];
4216 };
4217
4218 struct mlx5_ifc_query_hca_vport_context_out_bits {
4219         u8         status[0x8];
4220         u8         reserved_at_8[0x18];
4221
4222         u8         syndrome[0x20];
4223
4224         u8         reserved_at_40[0x40];
4225
4226         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4227 };
4228
4229 struct mlx5_ifc_query_hca_vport_context_in_bits {
4230         u8         opcode[0x10];
4231         u8         reserved_at_10[0x10];
4232
4233         u8         reserved_at_20[0x10];
4234         u8         op_mod[0x10];
4235
4236         u8         other_vport[0x1];
4237         u8         reserved_at_41[0xb];
4238         u8         port_num[0x4];
4239         u8         vport_number[0x10];
4240
4241         u8         reserved_at_60[0x20];
4242 };
4243
4244 struct mlx5_ifc_query_hca_cap_out_bits {
4245         u8         status[0x8];
4246         u8         reserved_at_8[0x18];
4247
4248         u8         syndrome[0x20];
4249
4250         u8         reserved_at_40[0x40];
4251
4252         union mlx5_ifc_hca_cap_union_bits capability;
4253 };
4254
4255 struct mlx5_ifc_query_hca_cap_in_bits {
4256         u8         opcode[0x10];
4257         u8         reserved_at_10[0x10];
4258
4259         u8         reserved_at_20[0x10];
4260         u8         op_mod[0x10];
4261
4262         u8         reserved_at_40[0x40];
4263 };
4264
4265 struct mlx5_ifc_query_flow_table_out_bits {
4266         u8         status[0x8];
4267         u8         reserved_at_8[0x18];
4268
4269         u8         syndrome[0x20];
4270
4271         u8         reserved_at_40[0x80];
4272
4273         u8         reserved_at_c0[0x8];
4274         u8         level[0x8];
4275         u8         reserved_at_d0[0x8];
4276         u8         log_size[0x8];
4277
4278         u8         reserved_at_e0[0x120];
4279 };
4280
4281 struct mlx5_ifc_query_flow_table_in_bits {
4282         u8         opcode[0x10];
4283         u8         reserved_at_10[0x10];
4284
4285         u8         reserved_at_20[0x10];
4286         u8         op_mod[0x10];
4287
4288         u8         reserved_at_40[0x40];
4289
4290         u8         table_type[0x8];
4291         u8         reserved_at_88[0x18];
4292
4293         u8         reserved_at_a0[0x8];
4294         u8         table_id[0x18];
4295
4296         u8         reserved_at_c0[0x140];
4297 };
4298
4299 struct mlx5_ifc_query_fte_out_bits {
4300         u8         status[0x8];
4301         u8         reserved_at_8[0x18];
4302
4303         u8         syndrome[0x20];
4304
4305         u8         reserved_at_40[0x1c0];
4306
4307         struct mlx5_ifc_flow_context_bits flow_context;
4308 };
4309
4310 struct mlx5_ifc_query_fte_in_bits {
4311         u8         opcode[0x10];
4312         u8         reserved_at_10[0x10];
4313
4314         u8         reserved_at_20[0x10];
4315         u8         op_mod[0x10];
4316
4317         u8         reserved_at_40[0x40];
4318
4319         u8         table_type[0x8];
4320         u8         reserved_at_88[0x18];
4321
4322         u8         reserved_at_a0[0x8];
4323         u8         table_id[0x18];
4324
4325         u8         reserved_at_c0[0x40];
4326
4327         u8         flow_index[0x20];
4328
4329         u8         reserved_at_120[0xe0];
4330 };
4331
4332 enum {
4333         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4334         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4335         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4336 };
4337
4338 struct mlx5_ifc_query_flow_group_out_bits {
4339         u8         status[0x8];
4340         u8         reserved_at_8[0x18];
4341
4342         u8         syndrome[0x20];
4343
4344         u8         reserved_at_40[0xa0];
4345
4346         u8         start_flow_index[0x20];
4347
4348         u8         reserved_at_100[0x20];
4349
4350         u8         end_flow_index[0x20];
4351
4352         u8         reserved_at_140[0xa0];
4353
4354         u8         reserved_at_1e0[0x18];
4355         u8         match_criteria_enable[0x8];
4356
4357         struct mlx5_ifc_fte_match_param_bits match_criteria;
4358
4359         u8         reserved_at_1200[0xe00];
4360 };
4361
4362 struct mlx5_ifc_query_flow_group_in_bits {
4363         u8         opcode[0x10];
4364         u8         reserved_at_10[0x10];
4365
4366         u8         reserved_at_20[0x10];
4367         u8         op_mod[0x10];
4368
4369         u8         reserved_at_40[0x40];
4370
4371         u8         table_type[0x8];
4372         u8         reserved_at_88[0x18];
4373
4374         u8         reserved_at_a0[0x8];
4375         u8         table_id[0x18];
4376
4377         u8         group_id[0x20];
4378
4379         u8         reserved_at_e0[0x120];
4380 };
4381
4382 struct mlx5_ifc_query_flow_counter_out_bits {
4383         u8         status[0x8];
4384         u8         reserved_at_8[0x18];
4385
4386         u8         syndrome[0x20];
4387
4388         u8         reserved_at_40[0x40];
4389
4390         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4391 };
4392
4393 struct mlx5_ifc_query_flow_counter_in_bits {
4394         u8         opcode[0x10];
4395         u8         reserved_at_10[0x10];
4396
4397         u8         reserved_at_20[0x10];
4398         u8         op_mod[0x10];
4399
4400         u8         reserved_at_40[0x80];
4401
4402         u8         clear[0x1];
4403         u8         reserved_at_c1[0xf];
4404         u8         num_of_counters[0x10];
4405
4406         u8         reserved_at_e0[0x10];
4407         u8         flow_counter_id[0x10];
4408 };
4409
4410 struct mlx5_ifc_query_esw_vport_context_out_bits {
4411         u8         status[0x8];
4412         u8         reserved_at_8[0x18];
4413
4414         u8         syndrome[0x20];
4415
4416         u8         reserved_at_40[0x40];
4417
4418         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4419 };
4420
4421 struct mlx5_ifc_query_esw_vport_context_in_bits {
4422         u8         opcode[0x10];
4423         u8         reserved_at_10[0x10];
4424
4425         u8         reserved_at_20[0x10];
4426         u8         op_mod[0x10];
4427
4428         u8         other_vport[0x1];
4429         u8         reserved_at_41[0xf];
4430         u8         vport_number[0x10];
4431
4432         u8         reserved_at_60[0x20];
4433 };
4434
4435 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4436         u8         status[0x8];
4437         u8         reserved_at_8[0x18];
4438
4439         u8         syndrome[0x20];
4440
4441         u8         reserved_at_40[0x40];
4442 };
4443
4444 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4445         u8         reserved_at_0[0x1c];
4446         u8         vport_cvlan_insert[0x1];
4447         u8         vport_svlan_insert[0x1];
4448         u8         vport_cvlan_strip[0x1];
4449         u8         vport_svlan_strip[0x1];
4450 };
4451
4452 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4453         u8         opcode[0x10];
4454         u8         reserved_at_10[0x10];
4455
4456         u8         reserved_at_20[0x10];
4457         u8         op_mod[0x10];
4458
4459         u8         other_vport[0x1];
4460         u8         reserved_at_41[0xf];
4461         u8         vport_number[0x10];
4462
4463         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4464
4465         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4466 };
4467
4468 struct mlx5_ifc_query_eq_out_bits {
4469         u8         status[0x8];
4470         u8         reserved_at_8[0x18];
4471
4472         u8         syndrome[0x20];
4473
4474         u8         reserved_at_40[0x40];
4475
4476         struct mlx5_ifc_eqc_bits eq_context_entry;
4477
4478         u8         reserved_at_280[0x40];
4479
4480         u8         event_bitmask[0x40];
4481
4482         u8         reserved_at_300[0x580];
4483
4484         u8         pas[0][0x40];
4485 };
4486
4487 struct mlx5_ifc_query_eq_in_bits {
4488         u8         opcode[0x10];
4489         u8         reserved_at_10[0x10];
4490
4491         u8         reserved_at_20[0x10];
4492         u8         op_mod[0x10];
4493
4494         u8         reserved_at_40[0x18];
4495         u8         eq_number[0x8];
4496
4497         u8         reserved_at_60[0x20];
4498 };
4499
4500 struct mlx5_ifc_encap_header_in_bits {
4501         u8         reserved_at_0[0x5];
4502         u8         header_type[0x3];
4503         u8         reserved_at_8[0xe];
4504         u8         encap_header_size[0xa];
4505
4506         u8         reserved_at_20[0x10];
4507         u8         encap_header[2][0x8];
4508
4509         u8         more_encap_header[0][0x8];
4510 };
4511
4512 struct mlx5_ifc_query_encap_header_out_bits {
4513         u8         status[0x8];
4514         u8         reserved_at_8[0x18];
4515
4516         u8         syndrome[0x20];
4517
4518         u8         reserved_at_40[0xa0];
4519
4520         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4521 };
4522
4523 struct mlx5_ifc_query_encap_header_in_bits {
4524         u8         opcode[0x10];
4525         u8         reserved_at_10[0x10];
4526
4527         u8         reserved_at_20[0x10];
4528         u8         op_mod[0x10];
4529
4530         u8         encap_id[0x20];
4531
4532         u8         reserved_at_60[0xa0];
4533 };
4534
4535 struct mlx5_ifc_alloc_encap_header_out_bits {
4536         u8         status[0x8];
4537         u8         reserved_at_8[0x18];
4538
4539         u8         syndrome[0x20];
4540
4541         u8         encap_id[0x20];
4542
4543         u8         reserved_at_60[0x20];
4544 };
4545
4546 struct mlx5_ifc_alloc_encap_header_in_bits {
4547         u8         opcode[0x10];
4548         u8         reserved_at_10[0x10];
4549
4550         u8         reserved_at_20[0x10];
4551         u8         op_mod[0x10];
4552
4553         u8         reserved_at_40[0xa0];
4554
4555         struct mlx5_ifc_encap_header_in_bits encap_header;
4556 };
4557
4558 struct mlx5_ifc_dealloc_encap_header_out_bits {
4559         u8         status[0x8];
4560         u8         reserved_at_8[0x18];
4561
4562         u8         syndrome[0x20];
4563
4564         u8         reserved_at_40[0x40];
4565 };
4566
4567 struct mlx5_ifc_dealloc_encap_header_in_bits {
4568         u8         opcode[0x10];
4569         u8         reserved_at_10[0x10];
4570
4571         u8         reserved_20[0x10];
4572         u8         op_mod[0x10];
4573
4574         u8         encap_id[0x20];
4575
4576         u8         reserved_60[0x20];
4577 };
4578
4579 struct mlx5_ifc_set_action_in_bits {
4580         u8         action_type[0x4];
4581         u8         field[0xc];
4582         u8         reserved_at_10[0x3];
4583         u8         offset[0x5];
4584         u8         reserved_at_18[0x3];
4585         u8         length[0x5];
4586
4587         u8         data[0x20];
4588 };
4589
4590 struct mlx5_ifc_add_action_in_bits {
4591         u8         action_type[0x4];
4592         u8         field[0xc];
4593         u8         reserved_at_10[0x10];
4594
4595         u8         data[0x20];
4596 };
4597
4598 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4599         struct mlx5_ifc_set_action_in_bits set_action_in;
4600         struct mlx5_ifc_add_action_in_bits add_action_in;
4601         u8         reserved_at_0[0x40];
4602 };
4603
4604 enum {
4605         MLX5_ACTION_TYPE_SET   = 0x1,
4606         MLX5_ACTION_TYPE_ADD   = 0x2,
4607 };
4608
4609 enum {
4610         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4611         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4612         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4613         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4614         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4615         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4616         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4617         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4618         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4619         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4620         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4621         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4622         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4623         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4624         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4625         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4626         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4627         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4628         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4629         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4630         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4631         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4632         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4633 };
4634
4635 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4636         u8         status[0x8];
4637         u8         reserved_at_8[0x18];
4638
4639         u8         syndrome[0x20];
4640
4641         u8         modify_header_id[0x20];
4642
4643         u8         reserved_at_60[0x20];
4644 };
4645
4646 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4647         u8         opcode[0x10];
4648         u8         reserved_at_10[0x10];
4649
4650         u8         reserved_at_20[0x10];
4651         u8         op_mod[0x10];
4652
4653         u8         reserved_at_40[0x20];
4654
4655         u8         table_type[0x8];
4656         u8         reserved_at_68[0x10];
4657         u8         num_of_actions[0x8];
4658
4659         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4660 };
4661
4662 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4663         u8         status[0x8];
4664         u8         reserved_at_8[0x18];
4665
4666         u8         syndrome[0x20];
4667
4668         u8         reserved_at_40[0x40];
4669 };
4670
4671 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4672         u8         opcode[0x10];
4673         u8         reserved_at_10[0x10];
4674
4675         u8         reserved_at_20[0x10];
4676         u8         op_mod[0x10];
4677
4678         u8         modify_header_id[0x20];
4679
4680         u8         reserved_at_60[0x20];
4681 };
4682
4683 struct mlx5_ifc_query_dct_out_bits {
4684         u8         status[0x8];
4685         u8         reserved_at_8[0x18];
4686
4687         u8         syndrome[0x20];
4688
4689         u8         reserved_at_40[0x40];
4690
4691         struct mlx5_ifc_dctc_bits dct_context_entry;
4692
4693         u8         reserved_at_280[0x180];
4694 };
4695
4696 struct mlx5_ifc_query_dct_in_bits {
4697         u8         opcode[0x10];
4698         u8         reserved_at_10[0x10];
4699
4700         u8         reserved_at_20[0x10];
4701         u8         op_mod[0x10];
4702
4703         u8         reserved_at_40[0x8];
4704         u8         dctn[0x18];
4705
4706         u8         reserved_at_60[0x20];
4707 };
4708
4709 struct mlx5_ifc_query_cq_out_bits {
4710         u8         status[0x8];
4711         u8         reserved_at_8[0x18];
4712
4713         u8         syndrome[0x20];
4714
4715         u8         reserved_at_40[0x40];
4716
4717         struct mlx5_ifc_cqc_bits cq_context;
4718
4719         u8         reserved_at_280[0x600];
4720
4721         u8         pas[0][0x40];
4722 };
4723
4724 struct mlx5_ifc_query_cq_in_bits {
4725         u8         opcode[0x10];
4726         u8         reserved_at_10[0x10];
4727
4728         u8         reserved_at_20[0x10];
4729         u8         op_mod[0x10];
4730
4731         u8         reserved_at_40[0x8];
4732         u8         cqn[0x18];
4733
4734         u8         reserved_at_60[0x20];
4735 };
4736
4737 struct mlx5_ifc_query_cong_status_out_bits {
4738         u8         status[0x8];
4739         u8         reserved_at_8[0x18];
4740
4741         u8         syndrome[0x20];
4742
4743         u8         reserved_at_40[0x20];
4744
4745         u8         enable[0x1];
4746         u8         tag_enable[0x1];
4747         u8         reserved_at_62[0x1e];
4748 };
4749
4750 struct mlx5_ifc_query_cong_status_in_bits {
4751         u8         opcode[0x10];
4752         u8         reserved_at_10[0x10];
4753
4754         u8         reserved_at_20[0x10];
4755         u8         op_mod[0x10];
4756
4757         u8         reserved_at_40[0x18];
4758         u8         priority[0x4];
4759         u8         cong_protocol[0x4];
4760
4761         u8         reserved_at_60[0x20];
4762 };
4763
4764 struct mlx5_ifc_query_cong_statistics_out_bits {
4765         u8         status[0x8];
4766         u8         reserved_at_8[0x18];
4767
4768         u8         syndrome[0x20];
4769
4770         u8         reserved_at_40[0x40];
4771
4772         u8         rp_cur_flows[0x20];
4773
4774         u8         sum_flows[0x20];
4775
4776         u8         rp_cnp_ignored_high[0x20];
4777
4778         u8         rp_cnp_ignored_low[0x20];
4779
4780         u8         rp_cnp_handled_high[0x20];
4781
4782         u8         rp_cnp_handled_low[0x20];
4783
4784         u8         reserved_at_140[0x100];
4785
4786         u8         time_stamp_high[0x20];
4787
4788         u8         time_stamp_low[0x20];
4789
4790         u8         accumulators_period[0x20];
4791
4792         u8         np_ecn_marked_roce_packets_high[0x20];
4793
4794         u8         np_ecn_marked_roce_packets_low[0x20];
4795
4796         u8         np_cnp_sent_high[0x20];
4797
4798         u8         np_cnp_sent_low[0x20];
4799
4800         u8         reserved_at_320[0x560];
4801 };
4802
4803 struct mlx5_ifc_query_cong_statistics_in_bits {
4804         u8         opcode[0x10];
4805         u8         reserved_at_10[0x10];
4806
4807         u8         reserved_at_20[0x10];
4808         u8         op_mod[0x10];
4809
4810         u8         clear[0x1];
4811         u8         reserved_at_41[0x1f];
4812
4813         u8         reserved_at_60[0x20];
4814 };
4815
4816 struct mlx5_ifc_query_cong_params_out_bits {
4817         u8         status[0x8];
4818         u8         reserved_at_8[0x18];
4819
4820         u8         syndrome[0x20];
4821
4822         u8         reserved_at_40[0x40];
4823
4824         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4825 };
4826
4827 struct mlx5_ifc_query_cong_params_in_bits {
4828         u8         opcode[0x10];
4829         u8         reserved_at_10[0x10];
4830
4831         u8         reserved_at_20[0x10];
4832         u8         op_mod[0x10];
4833
4834         u8         reserved_at_40[0x1c];
4835         u8         cong_protocol[0x4];
4836
4837         u8         reserved_at_60[0x20];
4838 };
4839
4840 struct mlx5_ifc_query_adapter_out_bits {
4841         u8         status[0x8];
4842         u8         reserved_at_8[0x18];
4843
4844         u8         syndrome[0x20];
4845
4846         u8         reserved_at_40[0x40];
4847
4848         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4849 };
4850
4851 struct mlx5_ifc_query_adapter_in_bits {
4852         u8         opcode[0x10];
4853         u8         reserved_at_10[0x10];
4854
4855         u8         reserved_at_20[0x10];
4856         u8         op_mod[0x10];
4857
4858         u8         reserved_at_40[0x40];
4859 };
4860
4861 struct mlx5_ifc_qp_2rst_out_bits {
4862         u8         status[0x8];
4863         u8         reserved_at_8[0x18];
4864
4865         u8         syndrome[0x20];
4866
4867         u8         reserved_at_40[0x40];
4868 };
4869
4870 struct mlx5_ifc_qp_2rst_in_bits {
4871         u8         opcode[0x10];
4872         u8         reserved_at_10[0x10];
4873
4874         u8         reserved_at_20[0x10];
4875         u8         op_mod[0x10];
4876
4877         u8         reserved_at_40[0x8];
4878         u8         qpn[0x18];
4879
4880         u8         reserved_at_60[0x20];
4881 };
4882
4883 struct mlx5_ifc_qp_2err_out_bits {
4884         u8         status[0x8];
4885         u8         reserved_at_8[0x18];
4886
4887         u8         syndrome[0x20];
4888
4889         u8         reserved_at_40[0x40];
4890 };
4891
4892 struct mlx5_ifc_qp_2err_in_bits {
4893         u8         opcode[0x10];
4894         u8         reserved_at_10[0x10];
4895
4896         u8         reserved_at_20[0x10];
4897         u8         op_mod[0x10];
4898
4899         u8         reserved_at_40[0x8];
4900         u8         qpn[0x18];
4901
4902         u8         reserved_at_60[0x20];
4903 };
4904
4905 struct mlx5_ifc_page_fault_resume_out_bits {
4906         u8         status[0x8];
4907         u8         reserved_at_8[0x18];
4908
4909         u8         syndrome[0x20];
4910
4911         u8         reserved_at_40[0x40];
4912 };
4913
4914 struct mlx5_ifc_page_fault_resume_in_bits {
4915         u8         opcode[0x10];
4916         u8         reserved_at_10[0x10];
4917
4918         u8         reserved_at_20[0x10];
4919         u8         op_mod[0x10];
4920
4921         u8         error[0x1];
4922         u8         reserved_at_41[0x4];
4923         u8         page_fault_type[0x3];
4924         u8         wq_number[0x18];
4925
4926         u8         reserved_at_60[0x8];
4927         u8         token[0x18];
4928 };
4929
4930 struct mlx5_ifc_nop_out_bits {
4931         u8         status[0x8];
4932         u8         reserved_at_8[0x18];
4933
4934         u8         syndrome[0x20];
4935
4936         u8         reserved_at_40[0x40];
4937 };
4938
4939 struct mlx5_ifc_nop_in_bits {
4940         u8         opcode[0x10];
4941         u8         reserved_at_10[0x10];
4942
4943         u8         reserved_at_20[0x10];
4944         u8         op_mod[0x10];
4945
4946         u8         reserved_at_40[0x40];
4947 };
4948
4949 struct mlx5_ifc_modify_vport_state_out_bits {
4950         u8         status[0x8];
4951         u8         reserved_at_8[0x18];
4952
4953         u8         syndrome[0x20];
4954
4955         u8         reserved_at_40[0x40];
4956 };
4957
4958 struct mlx5_ifc_modify_vport_state_in_bits {
4959         u8         opcode[0x10];
4960         u8         reserved_at_10[0x10];
4961
4962         u8         reserved_at_20[0x10];
4963         u8         op_mod[0x10];
4964
4965         u8         other_vport[0x1];
4966         u8         reserved_at_41[0xf];
4967         u8         vport_number[0x10];
4968
4969         u8         reserved_at_60[0x18];
4970         u8         admin_state[0x4];
4971         u8         reserved_at_7c[0x4];
4972 };
4973
4974 struct mlx5_ifc_modify_tis_out_bits {
4975         u8         status[0x8];
4976         u8         reserved_at_8[0x18];
4977
4978         u8         syndrome[0x20];
4979
4980         u8         reserved_at_40[0x40];
4981 };
4982
4983 struct mlx5_ifc_modify_tis_bitmask_bits {
4984         u8         reserved_at_0[0x20];
4985
4986         u8         reserved_at_20[0x1d];
4987         u8         lag_tx_port_affinity[0x1];
4988         u8         strict_lag_tx_port_affinity[0x1];
4989         u8         prio[0x1];
4990 };
4991
4992 struct mlx5_ifc_modify_tis_in_bits {
4993         u8         opcode[0x10];
4994         u8         reserved_at_10[0x10];
4995
4996         u8         reserved_at_20[0x10];
4997         u8         op_mod[0x10];
4998
4999         u8         reserved_at_40[0x8];
5000         u8         tisn[0x18];
5001
5002         u8         reserved_at_60[0x20];
5003
5004         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5005
5006         u8         reserved_at_c0[0x40];
5007
5008         struct mlx5_ifc_tisc_bits ctx;
5009 };
5010
5011 struct mlx5_ifc_modify_tir_bitmask_bits {
5012         u8         reserved_at_0[0x20];
5013
5014         u8         reserved_at_20[0x1b];
5015         u8         self_lb_en[0x1];
5016         u8         reserved_at_3c[0x1];
5017         u8         hash[0x1];
5018         u8         reserved_at_3e[0x1];
5019         u8         lro[0x1];
5020 };
5021
5022 struct mlx5_ifc_modify_tir_out_bits {
5023         u8         status[0x8];
5024         u8         reserved_at_8[0x18];
5025
5026         u8         syndrome[0x20];
5027
5028         u8         reserved_at_40[0x40];
5029 };
5030
5031 struct mlx5_ifc_modify_tir_in_bits {
5032         u8         opcode[0x10];
5033         u8         reserved_at_10[0x10];
5034
5035         u8         reserved_at_20[0x10];
5036         u8         op_mod[0x10];
5037
5038         u8         reserved_at_40[0x8];
5039         u8         tirn[0x18];
5040
5041         u8         reserved_at_60[0x20];
5042
5043         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5044
5045         u8         reserved_at_c0[0x40];
5046
5047         struct mlx5_ifc_tirc_bits ctx;
5048 };
5049
5050 struct mlx5_ifc_modify_sq_out_bits {
5051         u8         status[0x8];
5052         u8         reserved_at_8[0x18];
5053
5054         u8         syndrome[0x20];
5055
5056         u8         reserved_at_40[0x40];
5057 };
5058
5059 struct mlx5_ifc_modify_sq_in_bits {
5060         u8         opcode[0x10];
5061         u8         reserved_at_10[0x10];
5062
5063         u8         reserved_at_20[0x10];
5064         u8         op_mod[0x10];
5065
5066         u8         sq_state[0x4];
5067         u8         reserved_at_44[0x4];
5068         u8         sqn[0x18];
5069
5070         u8         reserved_at_60[0x20];
5071
5072         u8         modify_bitmask[0x40];
5073
5074         u8         reserved_at_c0[0x40];
5075
5076         struct mlx5_ifc_sqc_bits ctx;
5077 };
5078
5079 struct mlx5_ifc_modify_scheduling_element_out_bits {
5080         u8         status[0x8];
5081         u8         reserved_at_8[0x18];
5082
5083         u8         syndrome[0x20];
5084
5085         u8         reserved_at_40[0x1c0];
5086 };
5087
5088 enum {
5089         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5090         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5091 };
5092
5093 struct mlx5_ifc_modify_scheduling_element_in_bits {
5094         u8         opcode[0x10];
5095         u8         reserved_at_10[0x10];
5096
5097         u8         reserved_at_20[0x10];
5098         u8         op_mod[0x10];
5099
5100         u8         scheduling_hierarchy[0x8];
5101         u8         reserved_at_48[0x18];
5102
5103         u8         scheduling_element_id[0x20];
5104
5105         u8         reserved_at_80[0x20];
5106
5107         u8         modify_bitmask[0x20];
5108
5109         u8         reserved_at_c0[0x40];
5110
5111         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5112
5113         u8         reserved_at_300[0x100];
5114 };
5115
5116 struct mlx5_ifc_modify_rqt_out_bits {
5117         u8         status[0x8];
5118         u8         reserved_at_8[0x18];
5119
5120         u8         syndrome[0x20];
5121
5122         u8         reserved_at_40[0x40];
5123 };
5124
5125 struct mlx5_ifc_rqt_bitmask_bits {
5126         u8         reserved_at_0[0x20];
5127
5128         u8         reserved_at_20[0x1f];
5129         u8         rqn_list[0x1];
5130 };
5131
5132 struct mlx5_ifc_modify_rqt_in_bits {
5133         u8         opcode[0x10];
5134         u8         reserved_at_10[0x10];
5135
5136         u8         reserved_at_20[0x10];
5137         u8         op_mod[0x10];
5138
5139         u8         reserved_at_40[0x8];
5140         u8         rqtn[0x18];
5141
5142         u8         reserved_at_60[0x20];
5143
5144         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5145
5146         u8         reserved_at_c0[0x40];
5147
5148         struct mlx5_ifc_rqtc_bits ctx;
5149 };
5150
5151 struct mlx5_ifc_modify_rq_out_bits {
5152         u8         status[0x8];
5153         u8         reserved_at_8[0x18];
5154
5155         u8         syndrome[0x20];
5156
5157         u8         reserved_at_40[0x40];
5158 };
5159
5160 enum {
5161         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5162         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5163         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5164 };
5165
5166 struct mlx5_ifc_modify_rq_in_bits {
5167         u8         opcode[0x10];
5168         u8         reserved_at_10[0x10];
5169
5170         u8         reserved_at_20[0x10];
5171         u8         op_mod[0x10];
5172
5173         u8         rq_state[0x4];
5174         u8         reserved_at_44[0x4];
5175         u8         rqn[0x18];
5176
5177         u8         reserved_at_60[0x20];
5178
5179         u8         modify_bitmask[0x40];
5180
5181         u8         reserved_at_c0[0x40];
5182
5183         struct mlx5_ifc_rqc_bits ctx;
5184 };
5185
5186 struct mlx5_ifc_modify_rmp_out_bits {
5187         u8         status[0x8];
5188         u8         reserved_at_8[0x18];
5189
5190         u8         syndrome[0x20];
5191
5192         u8         reserved_at_40[0x40];
5193 };
5194
5195 struct mlx5_ifc_rmp_bitmask_bits {
5196         u8         reserved_at_0[0x20];
5197
5198         u8         reserved_at_20[0x1f];
5199         u8         lwm[0x1];
5200 };
5201
5202 struct mlx5_ifc_modify_rmp_in_bits {
5203         u8         opcode[0x10];
5204         u8         reserved_at_10[0x10];
5205
5206         u8         reserved_at_20[0x10];
5207         u8         op_mod[0x10];
5208
5209         u8         rmp_state[0x4];
5210         u8         reserved_at_44[0x4];
5211         u8         rmpn[0x18];
5212
5213         u8         reserved_at_60[0x20];
5214
5215         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5216
5217         u8         reserved_at_c0[0x40];
5218
5219         struct mlx5_ifc_rmpc_bits ctx;
5220 };
5221
5222 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5223         u8         status[0x8];
5224         u8         reserved_at_8[0x18];
5225
5226         u8         syndrome[0x20];
5227
5228         u8         reserved_at_40[0x40];
5229 };
5230
5231 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5232         u8         reserved_at_0[0x16];
5233         u8         node_guid[0x1];
5234         u8         port_guid[0x1];
5235         u8         min_inline[0x1];
5236         u8         mtu[0x1];
5237         u8         change_event[0x1];
5238         u8         promisc[0x1];
5239         u8         permanent_address[0x1];
5240         u8         addresses_list[0x1];
5241         u8         roce_en[0x1];
5242         u8         reserved_at_1f[0x1];
5243 };
5244
5245 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5246         u8         opcode[0x10];
5247         u8         reserved_at_10[0x10];
5248
5249         u8         reserved_at_20[0x10];
5250         u8         op_mod[0x10];
5251
5252         u8         other_vport[0x1];
5253         u8         reserved_at_41[0xf];
5254         u8         vport_number[0x10];
5255
5256         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5257
5258         u8         reserved_at_80[0x780];
5259
5260         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5261 };
5262
5263 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5264         u8         status[0x8];
5265         u8         reserved_at_8[0x18];
5266
5267         u8         syndrome[0x20];
5268
5269         u8         reserved_at_40[0x40];
5270 };
5271
5272 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5273         u8         opcode[0x10];
5274         u8         reserved_at_10[0x10];
5275
5276         u8         reserved_at_20[0x10];
5277         u8         op_mod[0x10];
5278
5279         u8         other_vport[0x1];
5280         u8         reserved_at_41[0xb];
5281         u8         port_num[0x4];
5282         u8         vport_number[0x10];
5283
5284         u8         reserved_at_60[0x20];
5285
5286         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5287 };
5288
5289 struct mlx5_ifc_modify_cq_out_bits {
5290         u8         status[0x8];
5291         u8         reserved_at_8[0x18];
5292
5293         u8         syndrome[0x20];
5294
5295         u8         reserved_at_40[0x40];
5296 };
5297
5298 enum {
5299         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5300         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5301 };
5302
5303 struct mlx5_ifc_modify_cq_in_bits {
5304         u8         opcode[0x10];
5305         u8         reserved_at_10[0x10];
5306
5307         u8         reserved_at_20[0x10];
5308         u8         op_mod[0x10];
5309
5310         u8         reserved_at_40[0x8];
5311         u8         cqn[0x18];
5312
5313         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5314
5315         struct mlx5_ifc_cqc_bits cq_context;
5316
5317         u8         reserved_at_280[0x600];
5318
5319         u8         pas[0][0x40];
5320 };
5321
5322 struct mlx5_ifc_modify_cong_status_out_bits {
5323         u8         status[0x8];
5324         u8         reserved_at_8[0x18];
5325
5326         u8         syndrome[0x20];
5327
5328         u8         reserved_at_40[0x40];
5329 };
5330
5331 struct mlx5_ifc_modify_cong_status_in_bits {
5332         u8         opcode[0x10];
5333         u8         reserved_at_10[0x10];
5334
5335         u8         reserved_at_20[0x10];
5336         u8         op_mod[0x10];
5337
5338         u8         reserved_at_40[0x18];
5339         u8         priority[0x4];
5340         u8         cong_protocol[0x4];
5341
5342         u8         enable[0x1];
5343         u8         tag_enable[0x1];
5344         u8         reserved_at_62[0x1e];
5345 };
5346
5347 struct mlx5_ifc_modify_cong_params_out_bits {
5348         u8         status[0x8];
5349         u8         reserved_at_8[0x18];
5350
5351         u8         syndrome[0x20];
5352
5353         u8         reserved_at_40[0x40];
5354 };
5355
5356 struct mlx5_ifc_modify_cong_params_in_bits {
5357         u8         opcode[0x10];
5358         u8         reserved_at_10[0x10];
5359
5360         u8         reserved_at_20[0x10];
5361         u8         op_mod[0x10];
5362
5363         u8         reserved_at_40[0x1c];
5364         u8         cong_protocol[0x4];
5365
5366         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5367
5368         u8         reserved_at_80[0x80];
5369
5370         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5371 };
5372
5373 struct mlx5_ifc_manage_pages_out_bits {
5374         u8         status[0x8];
5375         u8         reserved_at_8[0x18];
5376
5377         u8         syndrome[0x20];
5378
5379         u8         output_num_entries[0x20];
5380
5381         u8         reserved_at_60[0x20];
5382
5383         u8         pas[0][0x40];
5384 };
5385
5386 enum {
5387         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5388         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5389         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5390 };
5391
5392 struct mlx5_ifc_manage_pages_in_bits {
5393         u8         opcode[0x10];
5394         u8         reserved_at_10[0x10];
5395
5396         u8         reserved_at_20[0x10];
5397         u8         op_mod[0x10];
5398
5399         u8         reserved_at_40[0x10];
5400         u8         function_id[0x10];
5401
5402         u8         input_num_entries[0x20];
5403
5404         u8         pas[0][0x40];
5405 };
5406
5407 struct mlx5_ifc_mad_ifc_out_bits {
5408         u8         status[0x8];
5409         u8         reserved_at_8[0x18];
5410
5411         u8         syndrome[0x20];
5412
5413         u8         reserved_at_40[0x40];
5414
5415         u8         response_mad_packet[256][0x8];
5416 };
5417
5418 struct mlx5_ifc_mad_ifc_in_bits {
5419         u8         opcode[0x10];
5420         u8         reserved_at_10[0x10];
5421
5422         u8         reserved_at_20[0x10];
5423         u8         op_mod[0x10];
5424
5425         u8         remote_lid[0x10];
5426         u8         reserved_at_50[0x8];
5427         u8         port[0x8];
5428
5429         u8         reserved_at_60[0x20];
5430
5431         u8         mad[256][0x8];
5432 };
5433
5434 struct mlx5_ifc_init_hca_out_bits {
5435         u8         status[0x8];
5436         u8         reserved_at_8[0x18];
5437
5438         u8         syndrome[0x20];
5439
5440         u8         reserved_at_40[0x40];
5441 };
5442
5443 struct mlx5_ifc_init_hca_in_bits {
5444         u8         opcode[0x10];
5445         u8         reserved_at_10[0x10];
5446
5447         u8         reserved_at_20[0x10];
5448         u8         op_mod[0x10];
5449
5450         u8         reserved_at_40[0x40];
5451 };
5452
5453 struct mlx5_ifc_init2rtr_qp_out_bits {
5454         u8         status[0x8];
5455         u8         reserved_at_8[0x18];
5456
5457         u8         syndrome[0x20];
5458
5459         u8         reserved_at_40[0x40];
5460 };
5461
5462 struct mlx5_ifc_init2rtr_qp_in_bits {
5463         u8         opcode[0x10];
5464         u8         reserved_at_10[0x10];
5465
5466         u8         reserved_at_20[0x10];
5467         u8         op_mod[0x10];
5468
5469         u8         reserved_at_40[0x8];
5470         u8         qpn[0x18];
5471
5472         u8         reserved_at_60[0x20];
5473
5474         u8         opt_param_mask[0x20];
5475
5476         u8         reserved_at_a0[0x20];
5477
5478         struct mlx5_ifc_qpc_bits qpc;
5479
5480         u8         reserved_at_800[0x80];
5481 };
5482
5483 struct mlx5_ifc_init2init_qp_out_bits {
5484         u8         status[0x8];
5485         u8         reserved_at_8[0x18];
5486
5487         u8         syndrome[0x20];
5488
5489         u8         reserved_at_40[0x40];
5490 };
5491
5492 struct mlx5_ifc_init2init_qp_in_bits {
5493         u8         opcode[0x10];
5494         u8         reserved_at_10[0x10];
5495
5496         u8         reserved_at_20[0x10];
5497         u8         op_mod[0x10];
5498
5499         u8         reserved_at_40[0x8];
5500         u8         qpn[0x18];
5501
5502         u8         reserved_at_60[0x20];
5503
5504         u8         opt_param_mask[0x20];
5505
5506         u8         reserved_at_a0[0x20];
5507
5508         struct mlx5_ifc_qpc_bits qpc;
5509
5510         u8         reserved_at_800[0x80];
5511 };
5512
5513 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5514         u8         status[0x8];
5515         u8         reserved_at_8[0x18];
5516
5517         u8         syndrome[0x20];
5518
5519         u8         reserved_at_40[0x40];
5520
5521         u8         packet_headers_log[128][0x8];
5522
5523         u8         packet_syndrome[64][0x8];
5524 };
5525
5526 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5527         u8         opcode[0x10];
5528         u8         reserved_at_10[0x10];
5529
5530         u8         reserved_at_20[0x10];
5531         u8         op_mod[0x10];
5532
5533         u8         reserved_at_40[0x40];
5534 };
5535
5536 struct mlx5_ifc_gen_eqe_in_bits {
5537         u8         opcode[0x10];
5538         u8         reserved_at_10[0x10];
5539
5540         u8         reserved_at_20[0x10];
5541         u8         op_mod[0x10];
5542
5543         u8         reserved_at_40[0x18];
5544         u8         eq_number[0x8];
5545
5546         u8         reserved_at_60[0x20];
5547
5548         u8         eqe[64][0x8];
5549 };
5550
5551 struct mlx5_ifc_gen_eq_out_bits {
5552         u8         status[0x8];
5553         u8         reserved_at_8[0x18];
5554
5555         u8         syndrome[0x20];
5556
5557         u8         reserved_at_40[0x40];
5558 };
5559
5560 struct mlx5_ifc_enable_hca_out_bits {
5561         u8         status[0x8];
5562         u8         reserved_at_8[0x18];
5563
5564         u8         syndrome[0x20];
5565
5566         u8         reserved_at_40[0x20];
5567 };
5568
5569 struct mlx5_ifc_enable_hca_in_bits {
5570         u8         opcode[0x10];
5571         u8         reserved_at_10[0x10];
5572
5573         u8         reserved_at_20[0x10];
5574         u8         op_mod[0x10];
5575
5576         u8         reserved_at_40[0x10];
5577         u8         function_id[0x10];
5578
5579         u8         reserved_at_60[0x20];
5580 };
5581
5582 struct mlx5_ifc_drain_dct_out_bits {
5583         u8         status[0x8];
5584         u8         reserved_at_8[0x18];
5585
5586         u8         syndrome[0x20];
5587
5588         u8         reserved_at_40[0x40];
5589 };
5590
5591 struct mlx5_ifc_drain_dct_in_bits {
5592         u8         opcode[0x10];
5593         u8         reserved_at_10[0x10];
5594
5595         u8         reserved_at_20[0x10];
5596         u8         op_mod[0x10];
5597
5598         u8         reserved_at_40[0x8];
5599         u8         dctn[0x18];
5600
5601         u8         reserved_at_60[0x20];
5602 };
5603
5604 struct mlx5_ifc_disable_hca_out_bits {
5605         u8         status[0x8];
5606         u8         reserved_at_8[0x18];
5607
5608         u8         syndrome[0x20];
5609
5610         u8         reserved_at_40[0x20];
5611 };
5612
5613 struct mlx5_ifc_disable_hca_in_bits {
5614         u8         opcode[0x10];
5615         u8         reserved_at_10[0x10];
5616
5617         u8         reserved_at_20[0x10];
5618         u8         op_mod[0x10];
5619
5620         u8         reserved_at_40[0x10];
5621         u8         function_id[0x10];
5622
5623         u8         reserved_at_60[0x20];
5624 };
5625
5626 struct mlx5_ifc_detach_from_mcg_out_bits {
5627         u8         status[0x8];
5628         u8         reserved_at_8[0x18];
5629
5630         u8         syndrome[0x20];
5631
5632         u8         reserved_at_40[0x40];
5633 };
5634
5635 struct mlx5_ifc_detach_from_mcg_in_bits {
5636         u8         opcode[0x10];
5637         u8         reserved_at_10[0x10];
5638
5639         u8         reserved_at_20[0x10];
5640         u8         op_mod[0x10];
5641
5642         u8         reserved_at_40[0x8];
5643         u8         qpn[0x18];
5644
5645         u8         reserved_at_60[0x20];
5646
5647         u8         multicast_gid[16][0x8];
5648 };
5649
5650 struct mlx5_ifc_destroy_xrq_out_bits {
5651         u8         status[0x8];
5652         u8         reserved_at_8[0x18];
5653
5654         u8         syndrome[0x20];
5655
5656         u8         reserved_at_40[0x40];
5657 };
5658
5659 struct mlx5_ifc_destroy_xrq_in_bits {
5660         u8         opcode[0x10];
5661         u8         reserved_at_10[0x10];
5662
5663         u8         reserved_at_20[0x10];
5664         u8         op_mod[0x10];
5665
5666         u8         reserved_at_40[0x8];
5667         u8         xrqn[0x18];
5668
5669         u8         reserved_at_60[0x20];
5670 };
5671
5672 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5673         u8         status[0x8];
5674         u8         reserved_at_8[0x18];
5675
5676         u8         syndrome[0x20];
5677
5678         u8         reserved_at_40[0x40];
5679 };
5680
5681 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5682         u8         opcode[0x10];
5683         u8         reserved_at_10[0x10];
5684
5685         u8         reserved_at_20[0x10];
5686         u8         op_mod[0x10];
5687
5688         u8         reserved_at_40[0x8];
5689         u8         xrc_srqn[0x18];
5690
5691         u8         reserved_at_60[0x20];
5692 };
5693
5694 struct mlx5_ifc_destroy_tis_out_bits {
5695         u8         status[0x8];
5696         u8         reserved_at_8[0x18];
5697
5698         u8         syndrome[0x20];
5699
5700         u8         reserved_at_40[0x40];
5701 };
5702
5703 struct mlx5_ifc_destroy_tis_in_bits {
5704         u8         opcode[0x10];
5705         u8         reserved_at_10[0x10];
5706
5707         u8         reserved_at_20[0x10];
5708         u8         op_mod[0x10];
5709
5710         u8         reserved_at_40[0x8];
5711         u8         tisn[0x18];
5712
5713         u8         reserved_at_60[0x20];
5714 };
5715
5716 struct mlx5_ifc_destroy_tir_out_bits {
5717         u8         status[0x8];
5718         u8         reserved_at_8[0x18];
5719
5720         u8         syndrome[0x20];
5721
5722         u8         reserved_at_40[0x40];
5723 };
5724
5725 struct mlx5_ifc_destroy_tir_in_bits {
5726         u8         opcode[0x10];
5727         u8         reserved_at_10[0x10];
5728
5729         u8         reserved_at_20[0x10];
5730         u8         op_mod[0x10];
5731
5732         u8         reserved_at_40[0x8];
5733         u8         tirn[0x18];
5734
5735         u8         reserved_at_60[0x20];
5736 };
5737
5738 struct mlx5_ifc_destroy_srq_out_bits {
5739         u8         status[0x8];
5740         u8         reserved_at_8[0x18];
5741
5742         u8         syndrome[0x20];
5743
5744         u8         reserved_at_40[0x40];
5745 };
5746
5747 struct mlx5_ifc_destroy_srq_in_bits {
5748         u8         opcode[0x10];
5749         u8         reserved_at_10[0x10];
5750
5751         u8         reserved_at_20[0x10];
5752         u8         op_mod[0x10];
5753
5754         u8         reserved_at_40[0x8];
5755         u8         srqn[0x18];
5756
5757         u8         reserved_at_60[0x20];
5758 };
5759
5760 struct mlx5_ifc_destroy_sq_out_bits {
5761         u8         status[0x8];
5762         u8         reserved_at_8[0x18];
5763
5764         u8         syndrome[0x20];
5765
5766         u8         reserved_at_40[0x40];
5767 };
5768
5769 struct mlx5_ifc_destroy_sq_in_bits {
5770         u8         opcode[0x10];
5771         u8         reserved_at_10[0x10];
5772
5773         u8         reserved_at_20[0x10];
5774         u8         op_mod[0x10];
5775
5776         u8         reserved_at_40[0x8];
5777         u8         sqn[0x18];
5778
5779         u8         reserved_at_60[0x20];
5780 };
5781
5782 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5783         u8         status[0x8];
5784         u8         reserved_at_8[0x18];
5785
5786         u8         syndrome[0x20];
5787
5788         u8         reserved_at_40[0x1c0];
5789 };
5790
5791 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5792         u8         opcode[0x10];
5793         u8         reserved_at_10[0x10];
5794
5795         u8         reserved_at_20[0x10];
5796         u8         op_mod[0x10];
5797
5798         u8         scheduling_hierarchy[0x8];
5799         u8         reserved_at_48[0x18];
5800
5801         u8         scheduling_element_id[0x20];
5802
5803         u8         reserved_at_80[0x180];
5804 };
5805
5806 struct mlx5_ifc_destroy_rqt_out_bits {
5807         u8         status[0x8];
5808         u8         reserved_at_8[0x18];
5809
5810         u8         syndrome[0x20];
5811
5812         u8         reserved_at_40[0x40];
5813 };
5814
5815 struct mlx5_ifc_destroy_rqt_in_bits {
5816         u8         opcode[0x10];
5817         u8         reserved_at_10[0x10];
5818
5819         u8         reserved_at_20[0x10];
5820         u8         op_mod[0x10];
5821
5822         u8         reserved_at_40[0x8];
5823         u8         rqtn[0x18];
5824
5825         u8         reserved_at_60[0x20];
5826 };
5827
5828 struct mlx5_ifc_destroy_rq_out_bits {
5829         u8         status[0x8];
5830         u8         reserved_at_8[0x18];
5831
5832         u8         syndrome[0x20];
5833
5834         u8         reserved_at_40[0x40];
5835 };
5836
5837 struct mlx5_ifc_destroy_rq_in_bits {
5838         u8         opcode[0x10];
5839         u8         reserved_at_10[0x10];
5840
5841         u8         reserved_at_20[0x10];
5842         u8         op_mod[0x10];
5843
5844         u8         reserved_at_40[0x8];
5845         u8         rqn[0x18];
5846
5847         u8         reserved_at_60[0x20];
5848 };
5849
5850 struct mlx5_ifc_destroy_rmp_out_bits {
5851         u8         status[0x8];
5852         u8         reserved_at_8[0x18];
5853
5854         u8         syndrome[0x20];
5855
5856         u8         reserved_at_40[0x40];
5857 };
5858
5859 struct mlx5_ifc_destroy_rmp_in_bits {
5860         u8         opcode[0x10];
5861         u8         reserved_at_10[0x10];
5862
5863         u8         reserved_at_20[0x10];
5864         u8         op_mod[0x10];
5865
5866         u8         reserved_at_40[0x8];
5867         u8         rmpn[0x18];
5868
5869         u8         reserved_at_60[0x20];
5870 };
5871
5872 struct mlx5_ifc_destroy_qp_out_bits {
5873         u8         status[0x8];
5874         u8         reserved_at_8[0x18];
5875
5876         u8         syndrome[0x20];
5877
5878         u8         reserved_at_40[0x40];
5879 };
5880
5881 struct mlx5_ifc_destroy_qp_in_bits {
5882         u8         opcode[0x10];
5883         u8         reserved_at_10[0x10];
5884
5885         u8         reserved_at_20[0x10];
5886         u8         op_mod[0x10];
5887
5888         u8         reserved_at_40[0x8];
5889         u8         qpn[0x18];
5890
5891         u8         reserved_at_60[0x20];
5892 };
5893
5894 struct mlx5_ifc_destroy_psv_out_bits {
5895         u8         status[0x8];
5896         u8         reserved_at_8[0x18];
5897
5898         u8         syndrome[0x20];
5899
5900         u8         reserved_at_40[0x40];
5901 };
5902
5903 struct mlx5_ifc_destroy_psv_in_bits {
5904         u8         opcode[0x10];
5905         u8         reserved_at_10[0x10];
5906
5907         u8         reserved_at_20[0x10];
5908         u8         op_mod[0x10];
5909
5910         u8         reserved_at_40[0x8];
5911         u8         psvn[0x18];
5912
5913         u8         reserved_at_60[0x20];
5914 };
5915
5916 struct mlx5_ifc_destroy_mkey_out_bits {
5917         u8         status[0x8];
5918         u8         reserved_at_8[0x18];
5919
5920         u8         syndrome[0x20];
5921
5922         u8         reserved_at_40[0x40];
5923 };
5924
5925 struct mlx5_ifc_destroy_mkey_in_bits {
5926         u8         opcode[0x10];
5927         u8         reserved_at_10[0x10];
5928
5929         u8         reserved_at_20[0x10];
5930         u8         op_mod[0x10];
5931
5932         u8         reserved_at_40[0x8];
5933         u8         mkey_index[0x18];
5934
5935         u8         reserved_at_60[0x20];
5936 };
5937
5938 struct mlx5_ifc_destroy_flow_table_out_bits {
5939         u8         status[0x8];
5940         u8         reserved_at_8[0x18];
5941
5942         u8         syndrome[0x20];
5943
5944         u8         reserved_at_40[0x40];
5945 };
5946
5947 struct mlx5_ifc_destroy_flow_table_in_bits {
5948         u8         opcode[0x10];
5949         u8         reserved_at_10[0x10];
5950
5951         u8         reserved_at_20[0x10];
5952         u8         op_mod[0x10];
5953
5954         u8         other_vport[0x1];
5955         u8         reserved_at_41[0xf];
5956         u8         vport_number[0x10];
5957
5958         u8         reserved_at_60[0x20];
5959
5960         u8         table_type[0x8];
5961         u8         reserved_at_88[0x18];
5962
5963         u8         reserved_at_a0[0x8];
5964         u8         table_id[0x18];
5965
5966         u8         reserved_at_c0[0x140];
5967 };
5968
5969 struct mlx5_ifc_destroy_flow_group_out_bits {
5970         u8         status[0x8];
5971         u8         reserved_at_8[0x18];
5972
5973         u8         syndrome[0x20];
5974
5975         u8         reserved_at_40[0x40];
5976 };
5977
5978 struct mlx5_ifc_destroy_flow_group_in_bits {
5979         u8         opcode[0x10];
5980         u8         reserved_at_10[0x10];
5981
5982         u8         reserved_at_20[0x10];
5983         u8         op_mod[0x10];
5984
5985         u8         other_vport[0x1];
5986         u8         reserved_at_41[0xf];
5987         u8         vport_number[0x10];
5988
5989         u8         reserved_at_60[0x20];
5990
5991         u8         table_type[0x8];
5992         u8         reserved_at_88[0x18];
5993
5994         u8         reserved_at_a0[0x8];
5995         u8         table_id[0x18];
5996
5997         u8         group_id[0x20];
5998
5999         u8         reserved_at_e0[0x120];
6000 };
6001
6002 struct mlx5_ifc_destroy_eq_out_bits {
6003         u8         status[0x8];
6004         u8         reserved_at_8[0x18];
6005
6006         u8         syndrome[0x20];
6007
6008         u8         reserved_at_40[0x40];
6009 };
6010
6011 struct mlx5_ifc_destroy_eq_in_bits {
6012         u8         opcode[0x10];
6013         u8         reserved_at_10[0x10];
6014
6015         u8         reserved_at_20[0x10];
6016         u8         op_mod[0x10];
6017
6018         u8         reserved_at_40[0x18];
6019         u8         eq_number[0x8];
6020
6021         u8         reserved_at_60[0x20];
6022 };
6023
6024 struct mlx5_ifc_destroy_dct_out_bits {
6025         u8         status[0x8];
6026         u8         reserved_at_8[0x18];
6027
6028         u8         syndrome[0x20];
6029
6030         u8         reserved_at_40[0x40];
6031 };
6032
6033 struct mlx5_ifc_destroy_dct_in_bits {
6034         u8         opcode[0x10];
6035         u8         reserved_at_10[0x10];
6036
6037         u8         reserved_at_20[0x10];
6038         u8         op_mod[0x10];
6039
6040         u8         reserved_at_40[0x8];
6041         u8         dctn[0x18];
6042
6043         u8         reserved_at_60[0x20];
6044 };
6045
6046 struct mlx5_ifc_destroy_cq_out_bits {
6047         u8         status[0x8];
6048         u8         reserved_at_8[0x18];
6049
6050         u8         syndrome[0x20];
6051
6052         u8         reserved_at_40[0x40];
6053 };
6054
6055 struct mlx5_ifc_destroy_cq_in_bits {
6056         u8         opcode[0x10];
6057         u8         reserved_at_10[0x10];
6058
6059         u8         reserved_at_20[0x10];
6060         u8         op_mod[0x10];
6061
6062         u8         reserved_at_40[0x8];
6063         u8         cqn[0x18];
6064
6065         u8         reserved_at_60[0x20];
6066 };
6067
6068 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6069         u8         status[0x8];
6070         u8         reserved_at_8[0x18];
6071
6072         u8         syndrome[0x20];
6073
6074         u8         reserved_at_40[0x40];
6075 };
6076
6077 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6078         u8         opcode[0x10];
6079         u8         reserved_at_10[0x10];
6080
6081         u8         reserved_at_20[0x10];
6082         u8         op_mod[0x10];
6083
6084         u8         reserved_at_40[0x20];
6085
6086         u8         reserved_at_60[0x10];
6087         u8         vxlan_udp_port[0x10];
6088 };
6089
6090 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6091         u8         status[0x8];
6092         u8         reserved_at_8[0x18];
6093
6094         u8         syndrome[0x20];
6095
6096         u8         reserved_at_40[0x40];
6097 };
6098
6099 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6100         u8         opcode[0x10];
6101         u8         reserved_at_10[0x10];
6102
6103         u8         reserved_at_20[0x10];
6104         u8         op_mod[0x10];
6105
6106         u8         reserved_at_40[0x60];
6107
6108         u8         reserved_at_a0[0x8];
6109         u8         table_index[0x18];
6110
6111         u8         reserved_at_c0[0x140];
6112 };
6113
6114 struct mlx5_ifc_delete_fte_out_bits {
6115         u8         status[0x8];
6116         u8         reserved_at_8[0x18];
6117
6118         u8         syndrome[0x20];
6119
6120         u8         reserved_at_40[0x40];
6121 };
6122
6123 struct mlx5_ifc_delete_fte_in_bits {
6124         u8         opcode[0x10];
6125         u8         reserved_at_10[0x10];
6126
6127         u8         reserved_at_20[0x10];
6128         u8         op_mod[0x10];
6129
6130         u8         other_vport[0x1];
6131         u8         reserved_at_41[0xf];
6132         u8         vport_number[0x10];
6133
6134         u8         reserved_at_60[0x20];
6135
6136         u8         table_type[0x8];
6137         u8         reserved_at_88[0x18];
6138
6139         u8         reserved_at_a0[0x8];
6140         u8         table_id[0x18];
6141
6142         u8         reserved_at_c0[0x40];
6143
6144         u8         flow_index[0x20];
6145
6146         u8         reserved_at_120[0xe0];
6147 };
6148
6149 struct mlx5_ifc_dealloc_xrcd_out_bits {
6150         u8         status[0x8];
6151         u8         reserved_at_8[0x18];
6152
6153         u8         syndrome[0x20];
6154
6155         u8         reserved_at_40[0x40];
6156 };
6157
6158 struct mlx5_ifc_dealloc_xrcd_in_bits {
6159         u8         opcode[0x10];
6160         u8         reserved_at_10[0x10];
6161
6162         u8         reserved_at_20[0x10];
6163         u8         op_mod[0x10];
6164
6165         u8         reserved_at_40[0x8];
6166         u8         xrcd[0x18];
6167
6168         u8         reserved_at_60[0x20];
6169 };
6170
6171 struct mlx5_ifc_dealloc_uar_out_bits {
6172         u8         status[0x8];
6173         u8         reserved_at_8[0x18];
6174
6175         u8         syndrome[0x20];
6176
6177         u8         reserved_at_40[0x40];
6178 };
6179
6180 struct mlx5_ifc_dealloc_uar_in_bits {
6181         u8         opcode[0x10];
6182         u8         reserved_at_10[0x10];
6183
6184         u8         reserved_at_20[0x10];
6185         u8         op_mod[0x10];
6186
6187         u8         reserved_at_40[0x8];
6188         u8         uar[0x18];
6189
6190         u8         reserved_at_60[0x20];
6191 };
6192
6193 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6194         u8         status[0x8];
6195         u8         reserved_at_8[0x18];
6196
6197         u8         syndrome[0x20];
6198
6199         u8         reserved_at_40[0x40];
6200 };
6201
6202 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6203         u8         opcode[0x10];
6204         u8         reserved_at_10[0x10];
6205
6206         u8         reserved_at_20[0x10];
6207         u8         op_mod[0x10];
6208
6209         u8         reserved_at_40[0x8];
6210         u8         transport_domain[0x18];
6211
6212         u8         reserved_at_60[0x20];
6213 };
6214
6215 struct mlx5_ifc_dealloc_q_counter_out_bits {
6216         u8         status[0x8];
6217         u8         reserved_at_8[0x18];
6218
6219         u8         syndrome[0x20];
6220
6221         u8         reserved_at_40[0x40];
6222 };
6223
6224 struct mlx5_ifc_dealloc_q_counter_in_bits {
6225         u8         opcode[0x10];
6226         u8         reserved_at_10[0x10];
6227
6228         u8         reserved_at_20[0x10];
6229         u8         op_mod[0x10];
6230
6231         u8         reserved_at_40[0x18];
6232         u8         counter_set_id[0x8];
6233
6234         u8         reserved_at_60[0x20];
6235 };
6236
6237 struct mlx5_ifc_dealloc_pd_out_bits {
6238         u8         status[0x8];
6239         u8         reserved_at_8[0x18];
6240
6241         u8         syndrome[0x20];
6242
6243         u8         reserved_at_40[0x40];
6244 };
6245
6246 struct mlx5_ifc_dealloc_pd_in_bits {
6247         u8         opcode[0x10];
6248         u8         reserved_at_10[0x10];
6249
6250         u8         reserved_at_20[0x10];
6251         u8         op_mod[0x10];
6252
6253         u8         reserved_at_40[0x8];
6254         u8         pd[0x18];
6255
6256         u8         reserved_at_60[0x20];
6257 };
6258
6259 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6260         u8         status[0x8];
6261         u8         reserved_at_8[0x18];
6262
6263         u8         syndrome[0x20];
6264
6265         u8         reserved_at_40[0x40];
6266 };
6267
6268 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6269         u8         opcode[0x10];
6270         u8         reserved_at_10[0x10];
6271
6272         u8         reserved_at_20[0x10];
6273         u8         op_mod[0x10];
6274
6275         u8         reserved_at_40[0x10];
6276         u8         flow_counter_id[0x10];
6277
6278         u8         reserved_at_60[0x20];
6279 };
6280
6281 struct mlx5_ifc_create_xrq_out_bits {
6282         u8         status[0x8];
6283         u8         reserved_at_8[0x18];
6284
6285         u8         syndrome[0x20];
6286
6287         u8         reserved_at_40[0x8];
6288         u8         xrqn[0x18];
6289
6290         u8         reserved_at_60[0x20];
6291 };
6292
6293 struct mlx5_ifc_create_xrq_in_bits {
6294         u8         opcode[0x10];
6295         u8         reserved_at_10[0x10];
6296
6297         u8         reserved_at_20[0x10];
6298         u8         op_mod[0x10];
6299
6300         u8         reserved_at_40[0x40];
6301
6302         struct mlx5_ifc_xrqc_bits xrq_context;
6303 };
6304
6305 struct mlx5_ifc_create_xrc_srq_out_bits {
6306         u8         status[0x8];
6307         u8         reserved_at_8[0x18];
6308
6309         u8         syndrome[0x20];
6310
6311         u8         reserved_at_40[0x8];
6312         u8         xrc_srqn[0x18];
6313
6314         u8         reserved_at_60[0x20];
6315 };
6316
6317 struct mlx5_ifc_create_xrc_srq_in_bits {
6318         u8         opcode[0x10];
6319         u8         reserved_at_10[0x10];
6320
6321         u8         reserved_at_20[0x10];
6322         u8         op_mod[0x10];
6323
6324         u8         reserved_at_40[0x40];
6325
6326         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6327
6328         u8         reserved_at_280[0x600];
6329
6330         u8         pas[0][0x40];
6331 };
6332
6333 struct mlx5_ifc_create_tis_out_bits {
6334         u8         status[0x8];
6335         u8         reserved_at_8[0x18];
6336
6337         u8         syndrome[0x20];
6338
6339         u8         reserved_at_40[0x8];
6340         u8         tisn[0x18];
6341
6342         u8         reserved_at_60[0x20];
6343 };
6344
6345 struct mlx5_ifc_create_tis_in_bits {
6346         u8         opcode[0x10];
6347         u8         reserved_at_10[0x10];
6348
6349         u8         reserved_at_20[0x10];
6350         u8         op_mod[0x10];
6351
6352         u8         reserved_at_40[0xc0];
6353
6354         struct mlx5_ifc_tisc_bits ctx;
6355 };
6356
6357 struct mlx5_ifc_create_tir_out_bits {
6358         u8         status[0x8];
6359         u8         reserved_at_8[0x18];
6360
6361         u8         syndrome[0x20];
6362
6363         u8         reserved_at_40[0x8];
6364         u8         tirn[0x18];
6365
6366         u8         reserved_at_60[0x20];
6367 };
6368
6369 struct mlx5_ifc_create_tir_in_bits {
6370         u8         opcode[0x10];
6371         u8         reserved_at_10[0x10];
6372
6373         u8         reserved_at_20[0x10];
6374         u8         op_mod[0x10];
6375
6376         u8         reserved_at_40[0xc0];
6377
6378         struct mlx5_ifc_tirc_bits ctx;
6379 };
6380
6381 struct mlx5_ifc_create_srq_out_bits {
6382         u8         status[0x8];
6383         u8         reserved_at_8[0x18];
6384
6385         u8         syndrome[0x20];
6386
6387         u8         reserved_at_40[0x8];
6388         u8         srqn[0x18];
6389
6390         u8         reserved_at_60[0x20];
6391 };
6392
6393 struct mlx5_ifc_create_srq_in_bits {
6394         u8         opcode[0x10];
6395         u8         reserved_at_10[0x10];
6396
6397         u8         reserved_at_20[0x10];
6398         u8         op_mod[0x10];
6399
6400         u8         reserved_at_40[0x40];
6401
6402         struct mlx5_ifc_srqc_bits srq_context_entry;
6403
6404         u8         reserved_at_280[0x600];
6405
6406         u8         pas[0][0x40];
6407 };
6408
6409 struct mlx5_ifc_create_sq_out_bits {
6410         u8         status[0x8];
6411         u8         reserved_at_8[0x18];
6412
6413         u8         syndrome[0x20];
6414
6415         u8         reserved_at_40[0x8];
6416         u8         sqn[0x18];
6417
6418         u8         reserved_at_60[0x20];
6419 };
6420
6421 struct mlx5_ifc_create_sq_in_bits {
6422         u8         opcode[0x10];
6423         u8         reserved_at_10[0x10];
6424
6425         u8         reserved_at_20[0x10];
6426         u8         op_mod[0x10];
6427
6428         u8         reserved_at_40[0xc0];
6429
6430         struct mlx5_ifc_sqc_bits ctx;
6431 };
6432
6433 struct mlx5_ifc_create_scheduling_element_out_bits {
6434         u8         status[0x8];
6435         u8         reserved_at_8[0x18];
6436
6437         u8         syndrome[0x20];
6438
6439         u8         reserved_at_40[0x40];
6440
6441         u8         scheduling_element_id[0x20];
6442
6443         u8         reserved_at_a0[0x160];
6444 };
6445
6446 struct mlx5_ifc_create_scheduling_element_in_bits {
6447         u8         opcode[0x10];
6448         u8         reserved_at_10[0x10];
6449
6450         u8         reserved_at_20[0x10];
6451         u8         op_mod[0x10];
6452
6453         u8         scheduling_hierarchy[0x8];
6454         u8         reserved_at_48[0x18];
6455
6456         u8         reserved_at_60[0xa0];
6457
6458         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6459
6460         u8         reserved_at_300[0x100];
6461 };
6462
6463 struct mlx5_ifc_create_rqt_out_bits {
6464         u8         status[0x8];
6465         u8         reserved_at_8[0x18];
6466
6467         u8         syndrome[0x20];
6468
6469         u8         reserved_at_40[0x8];
6470         u8         rqtn[0x18];
6471
6472         u8         reserved_at_60[0x20];
6473 };
6474
6475 struct mlx5_ifc_create_rqt_in_bits {
6476         u8         opcode[0x10];
6477         u8         reserved_at_10[0x10];
6478
6479         u8         reserved_at_20[0x10];
6480         u8         op_mod[0x10];
6481
6482         u8         reserved_at_40[0xc0];
6483
6484         struct mlx5_ifc_rqtc_bits rqt_context;
6485 };
6486
6487 struct mlx5_ifc_create_rq_out_bits {
6488         u8         status[0x8];
6489         u8         reserved_at_8[0x18];
6490
6491         u8         syndrome[0x20];
6492
6493         u8         reserved_at_40[0x8];
6494         u8         rqn[0x18];
6495
6496         u8         reserved_at_60[0x20];
6497 };
6498
6499 struct mlx5_ifc_create_rq_in_bits {
6500         u8         opcode[0x10];
6501         u8         reserved_at_10[0x10];
6502
6503         u8         reserved_at_20[0x10];
6504         u8         op_mod[0x10];
6505
6506         u8         reserved_at_40[0xc0];
6507
6508         struct mlx5_ifc_rqc_bits ctx;
6509 };
6510
6511 struct mlx5_ifc_create_rmp_out_bits {
6512         u8         status[0x8];
6513         u8         reserved_at_8[0x18];
6514
6515         u8         syndrome[0x20];
6516
6517         u8         reserved_at_40[0x8];
6518         u8         rmpn[0x18];
6519
6520         u8         reserved_at_60[0x20];
6521 };
6522
6523 struct mlx5_ifc_create_rmp_in_bits {
6524         u8         opcode[0x10];
6525         u8         reserved_at_10[0x10];
6526
6527         u8         reserved_at_20[0x10];
6528         u8         op_mod[0x10];
6529
6530         u8         reserved_at_40[0xc0];
6531
6532         struct mlx5_ifc_rmpc_bits ctx;
6533 };
6534
6535 struct mlx5_ifc_create_qp_out_bits {
6536         u8         status[0x8];
6537         u8         reserved_at_8[0x18];
6538
6539         u8         syndrome[0x20];
6540
6541         u8         reserved_at_40[0x8];
6542         u8         qpn[0x18];
6543
6544         u8         reserved_at_60[0x20];
6545 };
6546
6547 struct mlx5_ifc_create_qp_in_bits {
6548         u8         opcode[0x10];
6549         u8         reserved_at_10[0x10];
6550
6551         u8         reserved_at_20[0x10];
6552         u8         op_mod[0x10];
6553
6554         u8         reserved_at_40[0x40];
6555
6556         u8         opt_param_mask[0x20];
6557
6558         u8         reserved_at_a0[0x20];
6559
6560         struct mlx5_ifc_qpc_bits qpc;
6561
6562         u8         reserved_at_800[0x80];
6563
6564         u8         pas[0][0x40];
6565 };
6566
6567 struct mlx5_ifc_create_psv_out_bits {
6568         u8         status[0x8];
6569         u8         reserved_at_8[0x18];
6570
6571         u8         syndrome[0x20];
6572
6573         u8         reserved_at_40[0x40];
6574
6575         u8         reserved_at_80[0x8];
6576         u8         psv0_index[0x18];
6577
6578         u8         reserved_at_a0[0x8];
6579         u8         psv1_index[0x18];
6580
6581         u8         reserved_at_c0[0x8];
6582         u8         psv2_index[0x18];
6583
6584         u8         reserved_at_e0[0x8];
6585         u8         psv3_index[0x18];
6586 };
6587
6588 struct mlx5_ifc_create_psv_in_bits {
6589         u8         opcode[0x10];
6590         u8         reserved_at_10[0x10];
6591
6592         u8         reserved_at_20[0x10];
6593         u8         op_mod[0x10];
6594
6595         u8         num_psv[0x4];
6596         u8         reserved_at_44[0x4];
6597         u8         pd[0x18];
6598
6599         u8         reserved_at_60[0x20];
6600 };
6601
6602 struct mlx5_ifc_create_mkey_out_bits {
6603         u8         status[0x8];
6604         u8         reserved_at_8[0x18];
6605
6606         u8         syndrome[0x20];
6607
6608         u8         reserved_at_40[0x8];
6609         u8         mkey_index[0x18];
6610
6611         u8         reserved_at_60[0x20];
6612 };
6613
6614 struct mlx5_ifc_create_mkey_in_bits {
6615         u8         opcode[0x10];
6616         u8         reserved_at_10[0x10];
6617
6618         u8         reserved_at_20[0x10];
6619         u8         op_mod[0x10];
6620
6621         u8         reserved_at_40[0x20];
6622
6623         u8         pg_access[0x1];
6624         u8         reserved_at_61[0x1f];
6625
6626         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6627
6628         u8         reserved_at_280[0x80];
6629
6630         u8         translations_octword_actual_size[0x20];
6631
6632         u8         reserved_at_320[0x560];
6633
6634         u8         klm_pas_mtt[0][0x20];
6635 };
6636
6637 struct mlx5_ifc_create_flow_table_out_bits {
6638         u8         status[0x8];
6639         u8         reserved_at_8[0x18];
6640
6641         u8         syndrome[0x20];
6642
6643         u8         reserved_at_40[0x8];
6644         u8         table_id[0x18];
6645
6646         u8         reserved_at_60[0x20];
6647 };
6648
6649 struct mlx5_ifc_flow_table_context_bits {
6650         u8         encap_en[0x1];
6651         u8         decap_en[0x1];
6652         u8         reserved_at_2[0x2];
6653         u8         table_miss_action[0x4];
6654         u8         level[0x8];
6655         u8         reserved_at_10[0x8];
6656         u8         log_size[0x8];
6657
6658         u8         reserved_at_20[0x8];
6659         u8         table_miss_id[0x18];
6660
6661         u8         reserved_at_40[0x8];
6662         u8         lag_master_next_table_id[0x18];
6663
6664         u8         reserved_at_60[0xe0];
6665 };
6666
6667 struct mlx5_ifc_create_flow_table_in_bits {
6668         u8         opcode[0x10];
6669         u8         reserved_at_10[0x10];
6670
6671         u8         reserved_at_20[0x10];
6672         u8         op_mod[0x10];
6673
6674         u8         other_vport[0x1];
6675         u8         reserved_at_41[0xf];
6676         u8         vport_number[0x10];
6677
6678         u8         reserved_at_60[0x20];
6679
6680         u8         table_type[0x8];
6681         u8         reserved_at_88[0x18];
6682
6683         u8         reserved_at_a0[0x20];
6684
6685         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6686 };
6687
6688 struct mlx5_ifc_create_flow_group_out_bits {
6689         u8         status[0x8];
6690         u8         reserved_at_8[0x18];
6691
6692         u8         syndrome[0x20];
6693
6694         u8         reserved_at_40[0x8];
6695         u8         group_id[0x18];
6696
6697         u8         reserved_at_60[0x20];
6698 };
6699
6700 enum {
6701         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6702         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6703         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6704 };
6705
6706 struct mlx5_ifc_create_flow_group_in_bits {
6707         u8         opcode[0x10];
6708         u8         reserved_at_10[0x10];
6709
6710         u8         reserved_at_20[0x10];
6711         u8         op_mod[0x10];
6712
6713         u8         other_vport[0x1];
6714         u8         reserved_at_41[0xf];
6715         u8         vport_number[0x10];
6716
6717         u8         reserved_at_60[0x20];
6718
6719         u8         table_type[0x8];
6720         u8         reserved_at_88[0x18];
6721
6722         u8         reserved_at_a0[0x8];
6723         u8         table_id[0x18];
6724
6725         u8         reserved_at_c0[0x20];
6726
6727         u8         start_flow_index[0x20];
6728
6729         u8         reserved_at_100[0x20];
6730
6731         u8         end_flow_index[0x20];
6732
6733         u8         reserved_at_140[0xa0];
6734
6735         u8         reserved_at_1e0[0x18];
6736         u8         match_criteria_enable[0x8];
6737
6738         struct mlx5_ifc_fte_match_param_bits match_criteria;
6739
6740         u8         reserved_at_1200[0xe00];
6741 };
6742
6743 struct mlx5_ifc_create_eq_out_bits {
6744         u8         status[0x8];
6745         u8         reserved_at_8[0x18];
6746
6747         u8         syndrome[0x20];
6748
6749         u8         reserved_at_40[0x18];
6750         u8         eq_number[0x8];
6751
6752         u8         reserved_at_60[0x20];
6753 };
6754
6755 struct mlx5_ifc_create_eq_in_bits {
6756         u8         opcode[0x10];
6757         u8         reserved_at_10[0x10];
6758
6759         u8         reserved_at_20[0x10];
6760         u8         op_mod[0x10];
6761
6762         u8         reserved_at_40[0x40];
6763
6764         struct mlx5_ifc_eqc_bits eq_context_entry;
6765
6766         u8         reserved_at_280[0x40];
6767
6768         u8         event_bitmask[0x40];
6769
6770         u8         reserved_at_300[0x580];
6771
6772         u8         pas[0][0x40];
6773 };
6774
6775 struct mlx5_ifc_create_dct_out_bits {
6776         u8         status[0x8];
6777         u8         reserved_at_8[0x18];
6778
6779         u8         syndrome[0x20];
6780
6781         u8         reserved_at_40[0x8];
6782         u8         dctn[0x18];
6783
6784         u8         reserved_at_60[0x20];
6785 };
6786
6787 struct mlx5_ifc_create_dct_in_bits {
6788         u8         opcode[0x10];
6789         u8         reserved_at_10[0x10];
6790
6791         u8         reserved_at_20[0x10];
6792         u8         op_mod[0x10];
6793
6794         u8         reserved_at_40[0x40];
6795
6796         struct mlx5_ifc_dctc_bits dct_context_entry;
6797
6798         u8         reserved_at_280[0x180];
6799 };
6800
6801 struct mlx5_ifc_create_cq_out_bits {
6802         u8         status[0x8];
6803         u8         reserved_at_8[0x18];
6804
6805         u8         syndrome[0x20];
6806
6807         u8         reserved_at_40[0x8];
6808         u8         cqn[0x18];
6809
6810         u8         reserved_at_60[0x20];
6811 };
6812
6813 struct mlx5_ifc_create_cq_in_bits {
6814         u8         opcode[0x10];
6815         u8         reserved_at_10[0x10];
6816
6817         u8         reserved_at_20[0x10];
6818         u8         op_mod[0x10];
6819
6820         u8         reserved_at_40[0x40];
6821
6822         struct mlx5_ifc_cqc_bits cq_context;
6823
6824         u8         reserved_at_280[0x600];
6825
6826         u8         pas[0][0x40];
6827 };
6828
6829 struct mlx5_ifc_config_int_moderation_out_bits {
6830         u8         status[0x8];
6831         u8         reserved_at_8[0x18];
6832
6833         u8         syndrome[0x20];
6834
6835         u8         reserved_at_40[0x4];
6836         u8         min_delay[0xc];
6837         u8         int_vector[0x10];
6838
6839         u8         reserved_at_60[0x20];
6840 };
6841
6842 enum {
6843         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6844         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6845 };
6846
6847 struct mlx5_ifc_config_int_moderation_in_bits {
6848         u8         opcode[0x10];
6849         u8         reserved_at_10[0x10];
6850
6851         u8         reserved_at_20[0x10];
6852         u8         op_mod[0x10];
6853
6854         u8         reserved_at_40[0x4];
6855         u8         min_delay[0xc];
6856         u8         int_vector[0x10];
6857
6858         u8         reserved_at_60[0x20];
6859 };
6860
6861 struct mlx5_ifc_attach_to_mcg_out_bits {
6862         u8         status[0x8];
6863         u8         reserved_at_8[0x18];
6864
6865         u8         syndrome[0x20];
6866
6867         u8         reserved_at_40[0x40];
6868 };
6869
6870 struct mlx5_ifc_attach_to_mcg_in_bits {
6871         u8         opcode[0x10];
6872         u8         reserved_at_10[0x10];
6873
6874         u8         reserved_at_20[0x10];
6875         u8         op_mod[0x10];
6876
6877         u8         reserved_at_40[0x8];
6878         u8         qpn[0x18];
6879
6880         u8         reserved_at_60[0x20];
6881
6882         u8         multicast_gid[16][0x8];
6883 };
6884
6885 struct mlx5_ifc_arm_xrq_out_bits {
6886         u8         status[0x8];
6887         u8         reserved_at_8[0x18];
6888
6889         u8         syndrome[0x20];
6890
6891         u8         reserved_at_40[0x40];
6892 };
6893
6894 struct mlx5_ifc_arm_xrq_in_bits {
6895         u8         opcode[0x10];
6896         u8         reserved_at_10[0x10];
6897
6898         u8         reserved_at_20[0x10];
6899         u8         op_mod[0x10];
6900
6901         u8         reserved_at_40[0x8];
6902         u8         xrqn[0x18];
6903
6904         u8         reserved_at_60[0x10];
6905         u8         lwm[0x10];
6906 };
6907
6908 struct mlx5_ifc_arm_xrc_srq_out_bits {
6909         u8         status[0x8];
6910         u8         reserved_at_8[0x18];
6911
6912         u8         syndrome[0x20];
6913
6914         u8         reserved_at_40[0x40];
6915 };
6916
6917 enum {
6918         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6919 };
6920
6921 struct mlx5_ifc_arm_xrc_srq_in_bits {
6922         u8         opcode[0x10];
6923         u8         reserved_at_10[0x10];
6924
6925         u8         reserved_at_20[0x10];
6926         u8         op_mod[0x10];
6927
6928         u8         reserved_at_40[0x8];
6929         u8         xrc_srqn[0x18];
6930
6931         u8         reserved_at_60[0x10];
6932         u8         lwm[0x10];
6933 };
6934
6935 struct mlx5_ifc_arm_rq_out_bits {
6936         u8         status[0x8];
6937         u8         reserved_at_8[0x18];
6938
6939         u8         syndrome[0x20];
6940
6941         u8         reserved_at_40[0x40];
6942 };
6943
6944 enum {
6945         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6946         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6947 };
6948
6949 struct mlx5_ifc_arm_rq_in_bits {
6950         u8         opcode[0x10];
6951         u8         reserved_at_10[0x10];
6952
6953         u8         reserved_at_20[0x10];
6954         u8         op_mod[0x10];
6955
6956         u8         reserved_at_40[0x8];
6957         u8         srq_number[0x18];
6958
6959         u8         reserved_at_60[0x10];
6960         u8         lwm[0x10];
6961 };
6962
6963 struct mlx5_ifc_arm_dct_out_bits {
6964         u8         status[0x8];
6965         u8         reserved_at_8[0x18];
6966
6967         u8         syndrome[0x20];
6968
6969         u8         reserved_at_40[0x40];
6970 };
6971
6972 struct mlx5_ifc_arm_dct_in_bits {
6973         u8         opcode[0x10];
6974         u8         reserved_at_10[0x10];
6975
6976         u8         reserved_at_20[0x10];
6977         u8         op_mod[0x10];
6978
6979         u8         reserved_at_40[0x8];
6980         u8         dct_number[0x18];
6981
6982         u8         reserved_at_60[0x20];
6983 };
6984
6985 struct mlx5_ifc_alloc_xrcd_out_bits {
6986         u8         status[0x8];
6987         u8         reserved_at_8[0x18];
6988
6989         u8         syndrome[0x20];
6990
6991         u8         reserved_at_40[0x8];
6992         u8         xrcd[0x18];
6993
6994         u8         reserved_at_60[0x20];
6995 };
6996
6997 struct mlx5_ifc_alloc_xrcd_in_bits {
6998         u8         opcode[0x10];
6999         u8         reserved_at_10[0x10];
7000
7001         u8         reserved_at_20[0x10];
7002         u8         op_mod[0x10];
7003
7004         u8         reserved_at_40[0x40];
7005 };
7006
7007 struct mlx5_ifc_alloc_uar_out_bits {
7008         u8         status[0x8];
7009         u8         reserved_at_8[0x18];
7010
7011         u8         syndrome[0x20];
7012
7013         u8         reserved_at_40[0x8];
7014         u8         uar[0x18];
7015
7016         u8         reserved_at_60[0x20];
7017 };
7018
7019 struct mlx5_ifc_alloc_uar_in_bits {
7020         u8         opcode[0x10];
7021         u8         reserved_at_10[0x10];
7022
7023         u8         reserved_at_20[0x10];
7024         u8         op_mod[0x10];
7025
7026         u8         reserved_at_40[0x40];
7027 };
7028
7029 struct mlx5_ifc_alloc_transport_domain_out_bits {
7030         u8         status[0x8];
7031         u8         reserved_at_8[0x18];
7032
7033         u8         syndrome[0x20];
7034
7035         u8         reserved_at_40[0x8];
7036         u8         transport_domain[0x18];
7037
7038         u8         reserved_at_60[0x20];
7039 };
7040
7041 struct mlx5_ifc_alloc_transport_domain_in_bits {
7042         u8         opcode[0x10];
7043         u8         reserved_at_10[0x10];
7044
7045         u8         reserved_at_20[0x10];
7046         u8         op_mod[0x10];
7047
7048         u8         reserved_at_40[0x40];
7049 };
7050
7051 struct mlx5_ifc_alloc_q_counter_out_bits {
7052         u8         status[0x8];
7053         u8         reserved_at_8[0x18];
7054
7055         u8         syndrome[0x20];
7056
7057         u8         reserved_at_40[0x18];
7058         u8         counter_set_id[0x8];
7059
7060         u8         reserved_at_60[0x20];
7061 };
7062
7063 struct mlx5_ifc_alloc_q_counter_in_bits {
7064         u8         opcode[0x10];
7065         u8         reserved_at_10[0x10];
7066
7067         u8         reserved_at_20[0x10];
7068         u8         op_mod[0x10];
7069
7070         u8         reserved_at_40[0x40];
7071 };
7072
7073 struct mlx5_ifc_alloc_pd_out_bits {
7074         u8         status[0x8];
7075         u8         reserved_at_8[0x18];
7076
7077         u8         syndrome[0x20];
7078
7079         u8         reserved_at_40[0x8];
7080         u8         pd[0x18];
7081
7082         u8         reserved_at_60[0x20];
7083 };
7084
7085 struct mlx5_ifc_alloc_pd_in_bits {
7086         u8         opcode[0x10];
7087         u8         reserved_at_10[0x10];
7088
7089         u8         reserved_at_20[0x10];
7090         u8         op_mod[0x10];
7091
7092         u8         reserved_at_40[0x40];
7093 };
7094
7095 struct mlx5_ifc_alloc_flow_counter_out_bits {
7096         u8         status[0x8];
7097         u8         reserved_at_8[0x18];
7098
7099         u8         syndrome[0x20];
7100
7101         u8         reserved_at_40[0x10];
7102         u8         flow_counter_id[0x10];
7103
7104         u8         reserved_at_60[0x20];
7105 };
7106
7107 struct mlx5_ifc_alloc_flow_counter_in_bits {
7108         u8         opcode[0x10];
7109         u8         reserved_at_10[0x10];
7110
7111         u8         reserved_at_20[0x10];
7112         u8         op_mod[0x10];
7113
7114         u8         reserved_at_40[0x40];
7115 };
7116
7117 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7118         u8         status[0x8];
7119         u8         reserved_at_8[0x18];
7120
7121         u8         syndrome[0x20];
7122
7123         u8         reserved_at_40[0x40];
7124 };
7125
7126 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7127         u8         opcode[0x10];
7128         u8         reserved_at_10[0x10];
7129
7130         u8         reserved_at_20[0x10];
7131         u8         op_mod[0x10];
7132
7133         u8         reserved_at_40[0x20];
7134
7135         u8         reserved_at_60[0x10];
7136         u8         vxlan_udp_port[0x10];
7137 };
7138
7139 struct mlx5_ifc_set_rate_limit_out_bits {
7140         u8         status[0x8];
7141         u8         reserved_at_8[0x18];
7142
7143         u8         syndrome[0x20];
7144
7145         u8         reserved_at_40[0x40];
7146 };
7147
7148 struct mlx5_ifc_set_rate_limit_in_bits {
7149         u8         opcode[0x10];
7150         u8         reserved_at_10[0x10];
7151
7152         u8         reserved_at_20[0x10];
7153         u8         op_mod[0x10];
7154
7155         u8         reserved_at_40[0x10];
7156         u8         rate_limit_index[0x10];
7157
7158         u8         reserved_at_60[0x20];
7159
7160         u8         rate_limit[0x20];
7161 };
7162
7163 struct mlx5_ifc_access_register_out_bits {
7164         u8         status[0x8];
7165         u8         reserved_at_8[0x18];
7166
7167         u8         syndrome[0x20];
7168
7169         u8         reserved_at_40[0x40];
7170
7171         u8         register_data[0][0x20];
7172 };
7173
7174 enum {
7175         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7176         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7177 };
7178
7179 struct mlx5_ifc_access_register_in_bits {
7180         u8         opcode[0x10];
7181         u8         reserved_at_10[0x10];
7182
7183         u8         reserved_at_20[0x10];
7184         u8         op_mod[0x10];
7185
7186         u8         reserved_at_40[0x10];
7187         u8         register_id[0x10];
7188
7189         u8         argument[0x20];
7190
7191         u8         register_data[0][0x20];
7192 };
7193
7194 struct mlx5_ifc_sltp_reg_bits {
7195         u8         status[0x4];
7196         u8         version[0x4];
7197         u8         local_port[0x8];
7198         u8         pnat[0x2];
7199         u8         reserved_at_12[0x2];
7200         u8         lane[0x4];
7201         u8         reserved_at_18[0x8];
7202
7203         u8         reserved_at_20[0x20];
7204
7205         u8         reserved_at_40[0x7];
7206         u8         polarity[0x1];
7207         u8         ob_tap0[0x8];
7208         u8         ob_tap1[0x8];
7209         u8         ob_tap2[0x8];
7210
7211         u8         reserved_at_60[0xc];
7212         u8         ob_preemp_mode[0x4];
7213         u8         ob_reg[0x8];
7214         u8         ob_bias[0x8];
7215
7216         u8         reserved_at_80[0x20];
7217 };
7218
7219 struct mlx5_ifc_slrg_reg_bits {
7220         u8         status[0x4];
7221         u8         version[0x4];
7222         u8         local_port[0x8];
7223         u8         pnat[0x2];
7224         u8         reserved_at_12[0x2];
7225         u8         lane[0x4];
7226         u8         reserved_at_18[0x8];
7227
7228         u8         time_to_link_up[0x10];
7229         u8         reserved_at_30[0xc];
7230         u8         grade_lane_speed[0x4];
7231
7232         u8         grade_version[0x8];
7233         u8         grade[0x18];
7234
7235         u8         reserved_at_60[0x4];
7236         u8         height_grade_type[0x4];
7237         u8         height_grade[0x18];
7238
7239         u8         height_dz[0x10];
7240         u8         height_dv[0x10];
7241
7242         u8         reserved_at_a0[0x10];
7243         u8         height_sigma[0x10];
7244
7245         u8         reserved_at_c0[0x20];
7246
7247         u8         reserved_at_e0[0x4];
7248         u8         phase_grade_type[0x4];
7249         u8         phase_grade[0x18];
7250
7251         u8         reserved_at_100[0x8];
7252         u8         phase_eo_pos[0x8];
7253         u8         reserved_at_110[0x8];
7254         u8         phase_eo_neg[0x8];
7255
7256         u8         ffe_set_tested[0x10];
7257         u8         test_errors_per_lane[0x10];
7258 };
7259
7260 struct mlx5_ifc_pvlc_reg_bits {
7261         u8         reserved_at_0[0x8];
7262         u8         local_port[0x8];
7263         u8         reserved_at_10[0x10];
7264
7265         u8         reserved_at_20[0x1c];
7266         u8         vl_hw_cap[0x4];
7267
7268         u8         reserved_at_40[0x1c];
7269         u8         vl_admin[0x4];
7270
7271         u8         reserved_at_60[0x1c];
7272         u8         vl_operational[0x4];
7273 };
7274
7275 struct mlx5_ifc_pude_reg_bits {
7276         u8         swid[0x8];
7277         u8         local_port[0x8];
7278         u8         reserved_at_10[0x4];
7279         u8         admin_status[0x4];
7280         u8         reserved_at_18[0x4];
7281         u8         oper_status[0x4];
7282
7283         u8         reserved_at_20[0x60];
7284 };
7285
7286 struct mlx5_ifc_ptys_reg_bits {
7287         u8         reserved_at_0[0x1];
7288         u8         an_disable_admin[0x1];
7289         u8         an_disable_cap[0x1];
7290         u8         reserved_at_3[0x5];
7291         u8         local_port[0x8];
7292         u8         reserved_at_10[0xd];
7293         u8         proto_mask[0x3];
7294
7295         u8         an_status[0x4];
7296         u8         reserved_at_24[0x3c];
7297
7298         u8         eth_proto_capability[0x20];
7299
7300         u8         ib_link_width_capability[0x10];
7301         u8         ib_proto_capability[0x10];
7302
7303         u8         reserved_at_a0[0x20];
7304
7305         u8         eth_proto_admin[0x20];
7306
7307         u8         ib_link_width_admin[0x10];
7308         u8         ib_proto_admin[0x10];
7309
7310         u8         reserved_at_100[0x20];
7311
7312         u8         eth_proto_oper[0x20];
7313
7314         u8         ib_link_width_oper[0x10];
7315         u8         ib_proto_oper[0x10];
7316
7317         u8         reserved_at_160[0x1c];
7318         u8         connector_type[0x4];
7319
7320         u8         eth_proto_lp_advertise[0x20];
7321
7322         u8         reserved_at_1a0[0x60];
7323 };
7324
7325 struct mlx5_ifc_mlcr_reg_bits {
7326         u8         reserved_at_0[0x8];
7327         u8         local_port[0x8];
7328         u8         reserved_at_10[0x20];
7329
7330         u8         beacon_duration[0x10];
7331         u8         reserved_at_40[0x10];
7332
7333         u8         beacon_remain[0x10];
7334 };
7335
7336 struct mlx5_ifc_ptas_reg_bits {
7337         u8         reserved_at_0[0x20];
7338
7339         u8         algorithm_options[0x10];
7340         u8         reserved_at_30[0x4];
7341         u8         repetitions_mode[0x4];
7342         u8         num_of_repetitions[0x8];
7343
7344         u8         grade_version[0x8];
7345         u8         height_grade_type[0x4];
7346         u8         phase_grade_type[0x4];
7347         u8         height_grade_weight[0x8];
7348         u8         phase_grade_weight[0x8];
7349
7350         u8         gisim_measure_bits[0x10];
7351         u8         adaptive_tap_measure_bits[0x10];
7352
7353         u8         ber_bath_high_error_threshold[0x10];
7354         u8         ber_bath_mid_error_threshold[0x10];
7355
7356         u8         ber_bath_low_error_threshold[0x10];
7357         u8         one_ratio_high_threshold[0x10];
7358
7359         u8         one_ratio_high_mid_threshold[0x10];
7360         u8         one_ratio_low_mid_threshold[0x10];
7361
7362         u8         one_ratio_low_threshold[0x10];
7363         u8         ndeo_error_threshold[0x10];
7364
7365         u8         mixer_offset_step_size[0x10];
7366         u8         reserved_at_110[0x8];
7367         u8         mix90_phase_for_voltage_bath[0x8];
7368
7369         u8         mixer_offset_start[0x10];
7370         u8         mixer_offset_end[0x10];
7371
7372         u8         reserved_at_140[0x15];
7373         u8         ber_test_time[0xb];
7374 };
7375
7376 struct mlx5_ifc_pspa_reg_bits {
7377         u8         swid[0x8];
7378         u8         local_port[0x8];
7379         u8         sub_port[0x8];
7380         u8         reserved_at_18[0x8];
7381
7382         u8         reserved_at_20[0x20];
7383 };
7384
7385 struct mlx5_ifc_pqdr_reg_bits {
7386         u8         reserved_at_0[0x8];
7387         u8         local_port[0x8];
7388         u8         reserved_at_10[0x5];
7389         u8         prio[0x3];
7390         u8         reserved_at_18[0x6];
7391         u8         mode[0x2];
7392
7393         u8         reserved_at_20[0x20];
7394
7395         u8         reserved_at_40[0x10];
7396         u8         min_threshold[0x10];
7397
7398         u8         reserved_at_60[0x10];
7399         u8         max_threshold[0x10];
7400
7401         u8         reserved_at_80[0x10];
7402         u8         mark_probability_denominator[0x10];
7403
7404         u8         reserved_at_a0[0x60];
7405 };
7406
7407 struct mlx5_ifc_ppsc_reg_bits {
7408         u8         reserved_at_0[0x8];
7409         u8         local_port[0x8];
7410         u8         reserved_at_10[0x10];
7411
7412         u8         reserved_at_20[0x60];
7413
7414         u8         reserved_at_80[0x1c];
7415         u8         wrps_admin[0x4];
7416
7417         u8         reserved_at_a0[0x1c];
7418         u8         wrps_status[0x4];
7419
7420         u8         reserved_at_c0[0x8];
7421         u8         up_threshold[0x8];
7422         u8         reserved_at_d0[0x8];
7423         u8         down_threshold[0x8];
7424
7425         u8         reserved_at_e0[0x20];
7426
7427         u8         reserved_at_100[0x1c];
7428         u8         srps_admin[0x4];
7429
7430         u8         reserved_at_120[0x1c];
7431         u8         srps_status[0x4];
7432
7433         u8         reserved_at_140[0x40];
7434 };
7435
7436 struct mlx5_ifc_pplr_reg_bits {
7437         u8         reserved_at_0[0x8];
7438         u8         local_port[0x8];
7439         u8         reserved_at_10[0x10];
7440
7441         u8         reserved_at_20[0x8];
7442         u8         lb_cap[0x8];
7443         u8         reserved_at_30[0x8];
7444         u8         lb_en[0x8];
7445 };
7446
7447 struct mlx5_ifc_pplm_reg_bits {
7448         u8         reserved_at_0[0x8];
7449         u8         local_port[0x8];
7450         u8         reserved_at_10[0x10];
7451
7452         u8         reserved_at_20[0x20];
7453
7454         u8         port_profile_mode[0x8];
7455         u8         static_port_profile[0x8];
7456         u8         active_port_profile[0x8];
7457         u8         reserved_at_58[0x8];
7458
7459         u8         retransmission_active[0x8];
7460         u8         fec_mode_active[0x18];
7461
7462         u8         reserved_at_80[0x20];
7463 };
7464
7465 struct mlx5_ifc_ppcnt_reg_bits {
7466         u8         swid[0x8];
7467         u8         local_port[0x8];
7468         u8         pnat[0x2];
7469         u8         reserved_at_12[0x8];
7470         u8         grp[0x6];
7471
7472         u8         clr[0x1];
7473         u8         reserved_at_21[0x1c];
7474         u8         prio_tc[0x3];
7475
7476         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7477 };
7478
7479 struct mlx5_ifc_mpcnt_reg_bits {
7480         u8         reserved_at_0[0x8];
7481         u8         pcie_index[0x8];
7482         u8         reserved_at_10[0xa];
7483         u8         grp[0x6];
7484
7485         u8         clr[0x1];
7486         u8         reserved_at_21[0x1f];
7487
7488         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7489 };
7490
7491 struct mlx5_ifc_ppad_reg_bits {
7492         u8         reserved_at_0[0x3];
7493         u8         single_mac[0x1];
7494         u8         reserved_at_4[0x4];
7495         u8         local_port[0x8];
7496         u8         mac_47_32[0x10];
7497
7498         u8         mac_31_0[0x20];
7499
7500         u8         reserved_at_40[0x40];
7501 };
7502
7503 struct mlx5_ifc_pmtu_reg_bits {
7504         u8         reserved_at_0[0x8];
7505         u8         local_port[0x8];
7506         u8         reserved_at_10[0x10];
7507
7508         u8         max_mtu[0x10];
7509         u8         reserved_at_30[0x10];
7510
7511         u8         admin_mtu[0x10];
7512         u8         reserved_at_50[0x10];
7513
7514         u8         oper_mtu[0x10];
7515         u8         reserved_at_70[0x10];
7516 };
7517
7518 struct mlx5_ifc_pmpr_reg_bits {
7519         u8         reserved_at_0[0x8];
7520         u8         module[0x8];
7521         u8         reserved_at_10[0x10];
7522
7523         u8         reserved_at_20[0x18];
7524         u8         attenuation_5g[0x8];
7525
7526         u8         reserved_at_40[0x18];
7527         u8         attenuation_7g[0x8];
7528
7529         u8         reserved_at_60[0x18];
7530         u8         attenuation_12g[0x8];
7531 };
7532
7533 struct mlx5_ifc_pmpe_reg_bits {
7534         u8         reserved_at_0[0x8];
7535         u8         module[0x8];
7536         u8         reserved_at_10[0xc];
7537         u8         module_status[0x4];
7538
7539         u8         reserved_at_20[0x60];
7540 };
7541
7542 struct mlx5_ifc_pmpc_reg_bits {
7543         u8         module_state_updated[32][0x8];
7544 };
7545
7546 struct mlx5_ifc_pmlpn_reg_bits {
7547         u8         reserved_at_0[0x4];
7548         u8         mlpn_status[0x4];
7549         u8         local_port[0x8];
7550         u8         reserved_at_10[0x10];
7551
7552         u8         e[0x1];
7553         u8         reserved_at_21[0x1f];
7554 };
7555
7556 struct mlx5_ifc_pmlp_reg_bits {
7557         u8         rxtx[0x1];
7558         u8         reserved_at_1[0x7];
7559         u8         local_port[0x8];
7560         u8         reserved_at_10[0x8];
7561         u8         width[0x8];
7562
7563         u8         lane0_module_mapping[0x20];
7564
7565         u8         lane1_module_mapping[0x20];
7566
7567         u8         lane2_module_mapping[0x20];
7568
7569         u8         lane3_module_mapping[0x20];
7570
7571         u8         reserved_at_a0[0x160];
7572 };
7573
7574 struct mlx5_ifc_pmaos_reg_bits {
7575         u8         reserved_at_0[0x8];
7576         u8         module[0x8];
7577         u8         reserved_at_10[0x4];
7578         u8         admin_status[0x4];
7579         u8         reserved_at_18[0x4];
7580         u8         oper_status[0x4];
7581
7582         u8         ase[0x1];
7583         u8         ee[0x1];
7584         u8         reserved_at_22[0x1c];
7585         u8         e[0x2];
7586
7587         u8         reserved_at_40[0x40];
7588 };
7589
7590 struct mlx5_ifc_plpc_reg_bits {
7591         u8         reserved_at_0[0x4];
7592         u8         profile_id[0xc];
7593         u8         reserved_at_10[0x4];
7594         u8         proto_mask[0x4];
7595         u8         reserved_at_18[0x8];
7596
7597         u8         reserved_at_20[0x10];
7598         u8         lane_speed[0x10];
7599
7600         u8         reserved_at_40[0x17];
7601         u8         lpbf[0x1];
7602         u8         fec_mode_policy[0x8];
7603
7604         u8         retransmission_capability[0x8];
7605         u8         fec_mode_capability[0x18];
7606
7607         u8         retransmission_support_admin[0x8];
7608         u8         fec_mode_support_admin[0x18];
7609
7610         u8         retransmission_request_admin[0x8];
7611         u8         fec_mode_request_admin[0x18];
7612
7613         u8         reserved_at_c0[0x80];
7614 };
7615
7616 struct mlx5_ifc_plib_reg_bits {
7617         u8         reserved_at_0[0x8];
7618         u8         local_port[0x8];
7619         u8         reserved_at_10[0x8];
7620         u8         ib_port[0x8];
7621
7622         u8         reserved_at_20[0x60];
7623 };
7624
7625 struct mlx5_ifc_plbf_reg_bits {
7626         u8         reserved_at_0[0x8];
7627         u8         local_port[0x8];
7628         u8         reserved_at_10[0xd];
7629         u8         lbf_mode[0x3];
7630
7631         u8         reserved_at_20[0x20];
7632 };
7633
7634 struct mlx5_ifc_pipg_reg_bits {
7635         u8         reserved_at_0[0x8];
7636         u8         local_port[0x8];
7637         u8         reserved_at_10[0x10];
7638
7639         u8         dic[0x1];
7640         u8         reserved_at_21[0x19];
7641         u8         ipg[0x4];
7642         u8         reserved_at_3e[0x2];
7643 };
7644
7645 struct mlx5_ifc_pifr_reg_bits {
7646         u8         reserved_at_0[0x8];
7647         u8         local_port[0x8];
7648         u8         reserved_at_10[0x10];
7649
7650         u8         reserved_at_20[0xe0];
7651
7652         u8         port_filter[8][0x20];
7653
7654         u8         port_filter_update_en[8][0x20];
7655 };
7656
7657 struct mlx5_ifc_pfcc_reg_bits {
7658         u8         reserved_at_0[0x8];
7659         u8         local_port[0x8];
7660         u8         reserved_at_10[0x10];
7661
7662         u8         ppan[0x4];
7663         u8         reserved_at_24[0x4];
7664         u8         prio_mask_tx[0x8];
7665         u8         reserved_at_30[0x8];
7666         u8         prio_mask_rx[0x8];
7667
7668         u8         pptx[0x1];
7669         u8         aptx[0x1];
7670         u8         reserved_at_42[0x6];
7671         u8         pfctx[0x8];
7672         u8         reserved_at_50[0x10];
7673
7674         u8         pprx[0x1];
7675         u8         aprx[0x1];
7676         u8         reserved_at_62[0x6];
7677         u8         pfcrx[0x8];
7678         u8         reserved_at_70[0x10];
7679
7680         u8         reserved_at_80[0x80];
7681 };
7682
7683 struct mlx5_ifc_pelc_reg_bits {
7684         u8         op[0x4];
7685         u8         reserved_at_4[0x4];
7686         u8         local_port[0x8];
7687         u8         reserved_at_10[0x10];
7688
7689         u8         op_admin[0x8];
7690         u8         op_capability[0x8];
7691         u8         op_request[0x8];
7692         u8         op_active[0x8];
7693
7694         u8         admin[0x40];
7695
7696         u8         capability[0x40];
7697
7698         u8         request[0x40];
7699
7700         u8         active[0x40];
7701
7702         u8         reserved_at_140[0x80];
7703 };
7704
7705 struct mlx5_ifc_peir_reg_bits {
7706         u8         reserved_at_0[0x8];
7707         u8         local_port[0x8];
7708         u8         reserved_at_10[0x10];
7709
7710         u8         reserved_at_20[0xc];
7711         u8         error_count[0x4];
7712         u8         reserved_at_30[0x10];
7713
7714         u8         reserved_at_40[0xc];
7715         u8         lane[0x4];
7716         u8         reserved_at_50[0x8];
7717         u8         error_type[0x8];
7718 };
7719
7720 struct mlx5_ifc_pcam_enhanced_features_bits {
7721         u8         reserved_at_0[0x7c];
7722
7723         u8         ptys_connector_type[0x1];
7724         u8         reserved_at_7d[0x1];
7725         u8         ppcnt_discard_group[0x1];
7726         u8         ppcnt_statistical_group[0x1];
7727 };
7728
7729 struct mlx5_ifc_pcam_reg_bits {
7730         u8         reserved_at_0[0x8];
7731         u8         feature_group[0x8];
7732         u8         reserved_at_10[0x8];
7733         u8         access_reg_group[0x8];
7734
7735         u8         reserved_at_20[0x20];
7736
7737         union {
7738                 u8         reserved_at_0[0x80];
7739         } port_access_reg_cap_mask;
7740
7741         u8         reserved_at_c0[0x80];
7742
7743         union {
7744                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7745                 u8         reserved_at_0[0x80];
7746         } feature_cap_mask;
7747
7748         u8         reserved_at_1c0[0xc0];
7749 };
7750
7751 struct mlx5_ifc_mcam_enhanced_features_bits {
7752         u8         reserved_at_0[0x7d];
7753
7754         u8         mtpps_enh_out_per_adj[0x1];
7755         u8         mtpps_fs[0x1];
7756         u8         pcie_performance_group[0x1];
7757 };
7758
7759 struct mlx5_ifc_mcam_access_reg_bits {
7760         u8         reserved_at_0[0x1c];
7761         u8         mcda[0x1];
7762         u8         mcc[0x1];
7763         u8         mcqi[0x1];
7764         u8         reserved_at_1f[0x1];
7765
7766         u8         regs_95_to_64[0x20];
7767         u8         regs_63_to_32[0x20];
7768         u8         regs_31_to_0[0x20];
7769 };
7770
7771 struct mlx5_ifc_mcam_reg_bits {
7772         u8         reserved_at_0[0x8];
7773         u8         feature_group[0x8];
7774         u8         reserved_at_10[0x8];
7775         u8         access_reg_group[0x8];
7776
7777         u8         reserved_at_20[0x20];
7778
7779         union {
7780                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7781                 u8         reserved_at_0[0x80];
7782         } mng_access_reg_cap_mask;
7783
7784         u8         reserved_at_c0[0x80];
7785
7786         union {
7787                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7788                 u8         reserved_at_0[0x80];
7789         } mng_feature_cap_mask;
7790
7791         u8         reserved_at_1c0[0x80];
7792 };
7793
7794 struct mlx5_ifc_pcap_reg_bits {
7795         u8         reserved_at_0[0x8];
7796         u8         local_port[0x8];
7797         u8         reserved_at_10[0x10];
7798
7799         u8         port_capability_mask[4][0x20];
7800 };
7801
7802 struct mlx5_ifc_paos_reg_bits {
7803         u8         swid[0x8];
7804         u8         local_port[0x8];
7805         u8         reserved_at_10[0x4];
7806         u8         admin_status[0x4];
7807         u8         reserved_at_18[0x4];
7808         u8         oper_status[0x4];
7809
7810         u8         ase[0x1];
7811         u8         ee[0x1];
7812         u8         reserved_at_22[0x1c];
7813         u8         e[0x2];
7814
7815         u8         reserved_at_40[0x40];
7816 };
7817
7818 struct mlx5_ifc_pamp_reg_bits {
7819         u8         reserved_at_0[0x8];
7820         u8         opamp_group[0x8];
7821         u8         reserved_at_10[0xc];
7822         u8         opamp_group_type[0x4];
7823
7824         u8         start_index[0x10];
7825         u8         reserved_at_30[0x4];
7826         u8         num_of_indices[0xc];
7827
7828         u8         index_data[18][0x10];
7829 };
7830
7831 struct mlx5_ifc_pcmr_reg_bits {
7832         u8         reserved_at_0[0x8];
7833         u8         local_port[0x8];
7834         u8         reserved_at_10[0x2e];
7835         u8         fcs_cap[0x1];
7836         u8         reserved_at_3f[0x1f];
7837         u8         fcs_chk[0x1];
7838         u8         reserved_at_5f[0x1];
7839 };
7840
7841 struct mlx5_ifc_lane_2_module_mapping_bits {
7842         u8         reserved_at_0[0x6];
7843         u8         rx_lane[0x2];
7844         u8         reserved_at_8[0x6];
7845         u8         tx_lane[0x2];
7846         u8         reserved_at_10[0x8];
7847         u8         module[0x8];
7848 };
7849
7850 struct mlx5_ifc_bufferx_reg_bits {
7851         u8         reserved_at_0[0x6];
7852         u8         lossy[0x1];
7853         u8         epsb[0x1];
7854         u8         reserved_at_8[0xc];
7855         u8         size[0xc];
7856
7857         u8         xoff_threshold[0x10];
7858         u8         xon_threshold[0x10];
7859 };
7860
7861 struct mlx5_ifc_set_node_in_bits {
7862         u8         node_description[64][0x8];
7863 };
7864
7865 struct mlx5_ifc_register_power_settings_bits {
7866         u8         reserved_at_0[0x18];
7867         u8         power_settings_level[0x8];
7868
7869         u8         reserved_at_20[0x60];
7870 };
7871
7872 struct mlx5_ifc_register_host_endianness_bits {
7873         u8         he[0x1];
7874         u8         reserved_at_1[0x1f];
7875
7876         u8         reserved_at_20[0x60];
7877 };
7878
7879 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7880         u8         reserved_at_0[0x20];
7881
7882         u8         mkey[0x20];
7883
7884         u8         addressh_63_32[0x20];
7885
7886         u8         addressl_31_0[0x20];
7887 };
7888
7889 struct mlx5_ifc_ud_adrs_vector_bits {
7890         u8         dc_key[0x40];
7891
7892         u8         ext[0x1];
7893         u8         reserved_at_41[0x7];
7894         u8         destination_qp_dct[0x18];
7895
7896         u8         static_rate[0x4];
7897         u8         sl_eth_prio[0x4];
7898         u8         fl[0x1];
7899         u8         mlid[0x7];
7900         u8         rlid_udp_sport[0x10];
7901
7902         u8         reserved_at_80[0x20];
7903
7904         u8         rmac_47_16[0x20];
7905
7906         u8         rmac_15_0[0x10];
7907         u8         tclass[0x8];
7908         u8         hop_limit[0x8];
7909
7910         u8         reserved_at_e0[0x1];
7911         u8         grh[0x1];
7912         u8         reserved_at_e2[0x2];
7913         u8         src_addr_index[0x8];
7914         u8         flow_label[0x14];
7915
7916         u8         rgid_rip[16][0x8];
7917 };
7918
7919 struct mlx5_ifc_pages_req_event_bits {
7920         u8         reserved_at_0[0x10];
7921         u8         function_id[0x10];
7922
7923         u8         num_pages[0x20];
7924
7925         u8         reserved_at_40[0xa0];
7926 };
7927
7928 struct mlx5_ifc_eqe_bits {
7929         u8         reserved_at_0[0x8];
7930         u8         event_type[0x8];
7931         u8         reserved_at_10[0x8];
7932         u8         event_sub_type[0x8];
7933
7934         u8         reserved_at_20[0xe0];
7935
7936         union mlx5_ifc_event_auto_bits event_data;
7937
7938         u8         reserved_at_1e0[0x10];
7939         u8         signature[0x8];
7940         u8         reserved_at_1f8[0x7];
7941         u8         owner[0x1];
7942 };
7943
7944 enum {
7945         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7946 };
7947
7948 struct mlx5_ifc_cmd_queue_entry_bits {
7949         u8         type[0x8];
7950         u8         reserved_at_8[0x18];
7951
7952         u8         input_length[0x20];
7953
7954         u8         input_mailbox_pointer_63_32[0x20];
7955
7956         u8         input_mailbox_pointer_31_9[0x17];
7957         u8         reserved_at_77[0x9];
7958
7959         u8         command_input_inline_data[16][0x8];
7960
7961         u8         command_output_inline_data[16][0x8];
7962
7963         u8         output_mailbox_pointer_63_32[0x20];
7964
7965         u8         output_mailbox_pointer_31_9[0x17];
7966         u8         reserved_at_1b7[0x9];
7967
7968         u8         output_length[0x20];
7969
7970         u8         token[0x8];
7971         u8         signature[0x8];
7972         u8         reserved_at_1f0[0x8];
7973         u8         status[0x7];
7974         u8         ownership[0x1];
7975 };
7976
7977 struct mlx5_ifc_cmd_out_bits {
7978         u8         status[0x8];
7979         u8         reserved_at_8[0x18];
7980
7981         u8         syndrome[0x20];
7982
7983         u8         command_output[0x20];
7984 };
7985
7986 struct mlx5_ifc_cmd_in_bits {
7987         u8         opcode[0x10];
7988         u8         reserved_at_10[0x10];
7989
7990         u8         reserved_at_20[0x10];
7991         u8         op_mod[0x10];
7992
7993         u8         command[0][0x20];
7994 };
7995
7996 struct mlx5_ifc_cmd_if_box_bits {
7997         u8         mailbox_data[512][0x8];
7998
7999         u8         reserved_at_1000[0x180];
8000
8001         u8         next_pointer_63_32[0x20];
8002
8003         u8         next_pointer_31_10[0x16];
8004         u8         reserved_at_11b6[0xa];
8005
8006         u8         block_number[0x20];
8007
8008         u8         reserved_at_11e0[0x8];
8009         u8         token[0x8];
8010         u8         ctrl_signature[0x8];
8011         u8         signature[0x8];
8012 };
8013
8014 struct mlx5_ifc_mtt_bits {
8015         u8         ptag_63_32[0x20];
8016
8017         u8         ptag_31_8[0x18];
8018         u8         reserved_at_38[0x6];
8019         u8         wr_en[0x1];
8020         u8         rd_en[0x1];
8021 };
8022
8023 struct mlx5_ifc_query_wol_rol_out_bits {
8024         u8         status[0x8];
8025         u8         reserved_at_8[0x18];
8026
8027         u8         syndrome[0x20];
8028
8029         u8         reserved_at_40[0x10];
8030         u8         rol_mode[0x8];
8031         u8         wol_mode[0x8];
8032
8033         u8         reserved_at_60[0x20];
8034 };
8035
8036 struct mlx5_ifc_query_wol_rol_in_bits {
8037         u8         opcode[0x10];
8038         u8         reserved_at_10[0x10];
8039
8040         u8         reserved_at_20[0x10];
8041         u8         op_mod[0x10];
8042
8043         u8         reserved_at_40[0x40];
8044 };
8045
8046 struct mlx5_ifc_set_wol_rol_out_bits {
8047         u8         status[0x8];
8048         u8         reserved_at_8[0x18];
8049
8050         u8         syndrome[0x20];
8051
8052         u8         reserved_at_40[0x40];
8053 };
8054
8055 struct mlx5_ifc_set_wol_rol_in_bits {
8056         u8         opcode[0x10];
8057         u8         reserved_at_10[0x10];
8058
8059         u8         reserved_at_20[0x10];
8060         u8         op_mod[0x10];
8061
8062         u8         rol_mode_valid[0x1];
8063         u8         wol_mode_valid[0x1];
8064         u8         reserved_at_42[0xe];
8065         u8         rol_mode[0x8];
8066         u8         wol_mode[0x8];
8067
8068         u8         reserved_at_60[0x20];
8069 };
8070
8071 enum {
8072         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8073         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8074         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8075 };
8076
8077 enum {
8078         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8079         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8080         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8081 };
8082
8083 enum {
8084         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8085         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8086         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8087         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8088         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8089         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8090         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8091         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8092         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8093         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8094         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8095 };
8096
8097 struct mlx5_ifc_initial_seg_bits {
8098         u8         fw_rev_minor[0x10];
8099         u8         fw_rev_major[0x10];
8100
8101         u8         cmd_interface_rev[0x10];
8102         u8         fw_rev_subminor[0x10];
8103
8104         u8         reserved_at_40[0x40];
8105
8106         u8         cmdq_phy_addr_63_32[0x20];
8107
8108         u8         cmdq_phy_addr_31_12[0x14];
8109         u8         reserved_at_b4[0x2];
8110         u8         nic_interface[0x2];
8111         u8         log_cmdq_size[0x4];
8112         u8         log_cmdq_stride[0x4];
8113
8114         u8         command_doorbell_vector[0x20];
8115
8116         u8         reserved_at_e0[0xf00];
8117
8118         u8         initializing[0x1];
8119         u8         reserved_at_fe1[0x4];
8120         u8         nic_interface_supported[0x3];
8121         u8         reserved_at_fe8[0x18];
8122
8123         struct mlx5_ifc_health_buffer_bits health_buffer;
8124
8125         u8         no_dram_nic_offset[0x20];
8126
8127         u8         reserved_at_1220[0x6e40];
8128
8129         u8         reserved_at_8060[0x1f];
8130         u8         clear_int[0x1];
8131
8132         u8         health_syndrome[0x8];
8133         u8         health_counter[0x18];
8134
8135         u8         reserved_at_80a0[0x17fc0];
8136 };
8137
8138 struct mlx5_ifc_mtpps_reg_bits {
8139         u8         reserved_at_0[0xc];
8140         u8         cap_number_of_pps_pins[0x4];
8141         u8         reserved_at_10[0x4];
8142         u8         cap_max_num_of_pps_in_pins[0x4];
8143         u8         reserved_at_18[0x4];
8144         u8         cap_max_num_of_pps_out_pins[0x4];
8145
8146         u8         reserved_at_20[0x24];
8147         u8         cap_pin_3_mode[0x4];
8148         u8         reserved_at_48[0x4];
8149         u8         cap_pin_2_mode[0x4];
8150         u8         reserved_at_50[0x4];
8151         u8         cap_pin_1_mode[0x4];
8152         u8         reserved_at_58[0x4];
8153         u8         cap_pin_0_mode[0x4];
8154
8155         u8         reserved_at_60[0x4];
8156         u8         cap_pin_7_mode[0x4];
8157         u8         reserved_at_68[0x4];
8158         u8         cap_pin_6_mode[0x4];
8159         u8         reserved_at_70[0x4];
8160         u8         cap_pin_5_mode[0x4];
8161         u8         reserved_at_78[0x4];
8162         u8         cap_pin_4_mode[0x4];
8163
8164         u8         field_select[0x20];
8165         u8         reserved_at_a0[0x60];
8166
8167         u8         enable[0x1];
8168         u8         reserved_at_101[0xb];
8169         u8         pattern[0x4];
8170         u8         reserved_at_110[0x4];
8171         u8         pin_mode[0x4];
8172         u8         pin[0x8];
8173
8174         u8         reserved_at_120[0x20];
8175
8176         u8         time_stamp[0x40];
8177
8178         u8         out_pulse_duration[0x10];
8179         u8         out_periodic_adjustment[0x10];
8180         u8         enhanced_out_periodic_adjustment[0x20];
8181
8182         u8         reserved_at_1c0[0x20];
8183 };
8184
8185 struct mlx5_ifc_mtppse_reg_bits {
8186         u8         reserved_at_0[0x18];
8187         u8         pin[0x8];
8188         u8         event_arm[0x1];
8189         u8         reserved_at_21[0x1b];
8190         u8         event_generation_mode[0x4];
8191         u8         reserved_at_40[0x40];
8192 };
8193
8194 struct mlx5_ifc_mcqi_cap_bits {
8195         u8         supported_info_bitmask[0x20];
8196
8197         u8         component_size[0x20];
8198
8199         u8         max_component_size[0x20];
8200
8201         u8         log_mcda_word_size[0x4];
8202         u8         reserved_at_64[0xc];
8203         u8         mcda_max_write_size[0x10];
8204
8205         u8         rd_en[0x1];
8206         u8         reserved_at_81[0x1];
8207         u8         match_chip_id[0x1];
8208         u8         match_psid[0x1];
8209         u8         check_user_timestamp[0x1];
8210         u8         match_base_guid_mac[0x1];
8211         u8         reserved_at_86[0x1a];
8212 };
8213
8214 struct mlx5_ifc_mcqi_reg_bits {
8215         u8         read_pending_component[0x1];
8216         u8         reserved_at_1[0xf];
8217         u8         component_index[0x10];
8218
8219         u8         reserved_at_20[0x20];
8220
8221         u8         reserved_at_40[0x1b];
8222         u8         info_type[0x5];
8223
8224         u8         info_size[0x20];
8225
8226         u8         offset[0x20];
8227
8228         u8         reserved_at_a0[0x10];
8229         u8         data_size[0x10];
8230
8231         u8         data[0][0x20];
8232 };
8233
8234 struct mlx5_ifc_mcc_reg_bits {
8235         u8         reserved_at_0[0x4];
8236         u8         time_elapsed_since_last_cmd[0xc];
8237         u8         reserved_at_10[0x8];
8238         u8         instruction[0x8];
8239
8240         u8         reserved_at_20[0x10];
8241         u8         component_index[0x10];
8242
8243         u8         reserved_at_40[0x8];
8244         u8         update_handle[0x18];
8245
8246         u8         handle_owner_type[0x4];
8247         u8         handle_owner_host_id[0x4];
8248         u8         reserved_at_68[0x1];
8249         u8         control_progress[0x7];
8250         u8         error_code[0x8];
8251         u8         reserved_at_78[0x4];
8252         u8         control_state[0x4];
8253
8254         u8         component_size[0x20];
8255
8256         u8         reserved_at_a0[0x60];
8257 };
8258
8259 struct mlx5_ifc_mcda_reg_bits {
8260         u8         reserved_at_0[0x8];
8261         u8         update_handle[0x18];
8262
8263         u8         offset[0x20];
8264
8265         u8         reserved_at_40[0x10];
8266         u8         size[0x10];
8267
8268         u8         reserved_at_60[0x20];
8269
8270         u8         data[0][0x20];
8271 };
8272
8273 union mlx5_ifc_ports_control_registers_document_bits {
8274         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8275         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8276         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8277         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8278         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8279         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8280         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8281         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8282         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8283         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8284         struct mlx5_ifc_paos_reg_bits paos_reg;
8285         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8286         struct mlx5_ifc_peir_reg_bits peir_reg;
8287         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8288         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8289         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8290         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8291         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8292         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8293         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8294         struct mlx5_ifc_plib_reg_bits plib_reg;
8295         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8296         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8297         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8298         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8299         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8300         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8301         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8302         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8303         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8304         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8305         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8306         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8307         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8308         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8309         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8310         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8311         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8312         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8313         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8314         struct mlx5_ifc_pude_reg_bits pude_reg;
8315         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8316         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8317         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8318         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8319         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8320         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8321         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8322         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8323         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8324         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8325         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8326         u8         reserved_at_0[0x60e0];
8327 };
8328
8329 union mlx5_ifc_debug_enhancements_document_bits {
8330         struct mlx5_ifc_health_buffer_bits health_buffer;
8331         u8         reserved_at_0[0x200];
8332 };
8333
8334 union mlx5_ifc_uplink_pci_interface_document_bits {
8335         struct mlx5_ifc_initial_seg_bits initial_seg;
8336         u8         reserved_at_0[0x20060];
8337 };
8338
8339 struct mlx5_ifc_set_flow_table_root_out_bits {
8340         u8         status[0x8];
8341         u8         reserved_at_8[0x18];
8342
8343         u8         syndrome[0x20];
8344
8345         u8         reserved_at_40[0x40];
8346 };
8347
8348 struct mlx5_ifc_set_flow_table_root_in_bits {
8349         u8         opcode[0x10];
8350         u8         reserved_at_10[0x10];
8351
8352         u8         reserved_at_20[0x10];
8353         u8         op_mod[0x10];
8354
8355         u8         other_vport[0x1];
8356         u8         reserved_at_41[0xf];
8357         u8         vport_number[0x10];
8358
8359         u8         reserved_at_60[0x20];
8360
8361         u8         table_type[0x8];
8362         u8         reserved_at_88[0x18];
8363
8364         u8         reserved_at_a0[0x8];
8365         u8         table_id[0x18];
8366
8367         u8         reserved_at_c0[0x8];
8368         u8         underlay_qpn[0x18];
8369         u8         reserved_at_e0[0x120];
8370 };
8371
8372 enum {
8373         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8374         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8375 };
8376
8377 struct mlx5_ifc_modify_flow_table_out_bits {
8378         u8         status[0x8];
8379         u8         reserved_at_8[0x18];
8380
8381         u8         syndrome[0x20];
8382
8383         u8         reserved_at_40[0x40];
8384 };
8385
8386 struct mlx5_ifc_modify_flow_table_in_bits {
8387         u8         opcode[0x10];
8388         u8         reserved_at_10[0x10];
8389
8390         u8         reserved_at_20[0x10];
8391         u8         op_mod[0x10];
8392
8393         u8         other_vport[0x1];
8394         u8         reserved_at_41[0xf];
8395         u8         vport_number[0x10];
8396
8397         u8         reserved_at_60[0x10];
8398         u8         modify_field_select[0x10];
8399
8400         u8         table_type[0x8];
8401         u8         reserved_at_88[0x18];
8402
8403         u8         reserved_at_a0[0x8];
8404         u8         table_id[0x18];
8405
8406         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8407 };
8408
8409 struct mlx5_ifc_ets_tcn_config_reg_bits {
8410         u8         g[0x1];
8411         u8         b[0x1];
8412         u8         r[0x1];
8413         u8         reserved_at_3[0x9];
8414         u8         group[0x4];
8415         u8         reserved_at_10[0x9];
8416         u8         bw_allocation[0x7];
8417
8418         u8         reserved_at_20[0xc];
8419         u8         max_bw_units[0x4];
8420         u8         reserved_at_30[0x8];
8421         u8         max_bw_value[0x8];
8422 };
8423
8424 struct mlx5_ifc_ets_global_config_reg_bits {
8425         u8         reserved_at_0[0x2];
8426         u8         r[0x1];
8427         u8         reserved_at_3[0x1d];
8428
8429         u8         reserved_at_20[0xc];
8430         u8         max_bw_units[0x4];
8431         u8         reserved_at_30[0x8];
8432         u8         max_bw_value[0x8];
8433 };
8434
8435 struct mlx5_ifc_qetc_reg_bits {
8436         u8                                         reserved_at_0[0x8];
8437         u8                                         port_number[0x8];
8438         u8                                         reserved_at_10[0x30];
8439
8440         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8441         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8442 };
8443
8444 struct mlx5_ifc_qtct_reg_bits {
8445         u8         reserved_at_0[0x8];
8446         u8         port_number[0x8];
8447         u8         reserved_at_10[0xd];
8448         u8         prio[0x3];
8449
8450         u8         reserved_at_20[0x1d];
8451         u8         tclass[0x3];
8452 };
8453
8454 struct mlx5_ifc_mcia_reg_bits {
8455         u8         l[0x1];
8456         u8         reserved_at_1[0x7];
8457         u8         module[0x8];
8458         u8         reserved_at_10[0x8];
8459         u8         status[0x8];
8460
8461         u8         i2c_device_address[0x8];
8462         u8         page_number[0x8];
8463         u8         device_address[0x10];
8464
8465         u8         reserved_at_40[0x10];
8466         u8         size[0x10];
8467
8468         u8         reserved_at_60[0x20];
8469
8470         u8         dword_0[0x20];
8471         u8         dword_1[0x20];
8472         u8         dword_2[0x20];
8473         u8         dword_3[0x20];
8474         u8         dword_4[0x20];
8475         u8         dword_5[0x20];
8476         u8         dword_6[0x20];
8477         u8         dword_7[0x20];
8478         u8         dword_8[0x20];
8479         u8         dword_9[0x20];
8480         u8         dword_10[0x20];
8481         u8         dword_11[0x20];
8482 };
8483
8484 struct mlx5_ifc_dcbx_param_bits {
8485         u8         dcbx_cee_cap[0x1];
8486         u8         dcbx_ieee_cap[0x1];
8487         u8         dcbx_standby_cap[0x1];
8488         u8         reserved_at_0[0x5];
8489         u8         port_number[0x8];
8490         u8         reserved_at_10[0xa];
8491         u8         max_application_table_size[6];
8492         u8         reserved_at_20[0x15];
8493         u8         version_oper[0x3];
8494         u8         reserved_at_38[5];
8495         u8         version_admin[0x3];
8496         u8         willing_admin[0x1];
8497         u8         reserved_at_41[0x3];
8498         u8         pfc_cap_oper[0x4];
8499         u8         reserved_at_48[0x4];
8500         u8         pfc_cap_admin[0x4];
8501         u8         reserved_at_50[0x4];
8502         u8         num_of_tc_oper[0x4];
8503         u8         reserved_at_58[0x4];
8504         u8         num_of_tc_admin[0x4];
8505         u8         remote_willing[0x1];
8506         u8         reserved_at_61[3];
8507         u8         remote_pfc_cap[4];
8508         u8         reserved_at_68[0x14];
8509         u8         remote_num_of_tc[0x4];
8510         u8         reserved_at_80[0x18];
8511         u8         error[0x8];
8512         u8         reserved_at_a0[0x160];
8513 };
8514
8515 struct mlx5_ifc_lagc_bits {
8516         u8         reserved_at_0[0x1d];
8517         u8         lag_state[0x3];
8518
8519         u8         reserved_at_20[0x14];
8520         u8         tx_remap_affinity_2[0x4];
8521         u8         reserved_at_38[0x4];
8522         u8         tx_remap_affinity_1[0x4];
8523 };
8524
8525 struct mlx5_ifc_create_lag_out_bits {
8526         u8         status[0x8];
8527         u8         reserved_at_8[0x18];
8528
8529         u8         syndrome[0x20];
8530
8531         u8         reserved_at_40[0x40];
8532 };
8533
8534 struct mlx5_ifc_create_lag_in_bits {
8535         u8         opcode[0x10];
8536         u8         reserved_at_10[0x10];
8537
8538         u8         reserved_at_20[0x10];
8539         u8         op_mod[0x10];
8540
8541         struct mlx5_ifc_lagc_bits ctx;
8542 };
8543
8544 struct mlx5_ifc_modify_lag_out_bits {
8545         u8         status[0x8];
8546         u8         reserved_at_8[0x18];
8547
8548         u8         syndrome[0x20];
8549
8550         u8         reserved_at_40[0x40];
8551 };
8552
8553 struct mlx5_ifc_modify_lag_in_bits {
8554         u8         opcode[0x10];
8555         u8         reserved_at_10[0x10];
8556
8557         u8         reserved_at_20[0x10];
8558         u8         op_mod[0x10];
8559
8560         u8         reserved_at_40[0x20];
8561         u8         field_select[0x20];
8562
8563         struct mlx5_ifc_lagc_bits ctx;
8564 };
8565
8566 struct mlx5_ifc_query_lag_out_bits {
8567         u8         status[0x8];
8568         u8         reserved_at_8[0x18];
8569
8570         u8         syndrome[0x20];
8571
8572         u8         reserved_at_40[0x40];
8573
8574         struct mlx5_ifc_lagc_bits ctx;
8575 };
8576
8577 struct mlx5_ifc_query_lag_in_bits {
8578         u8         opcode[0x10];
8579         u8         reserved_at_10[0x10];
8580
8581         u8         reserved_at_20[0x10];
8582         u8         op_mod[0x10];
8583
8584         u8         reserved_at_40[0x40];
8585 };
8586
8587 struct mlx5_ifc_destroy_lag_out_bits {
8588         u8         status[0x8];
8589         u8         reserved_at_8[0x18];
8590
8591         u8         syndrome[0x20];
8592
8593         u8         reserved_at_40[0x40];
8594 };
8595
8596 struct mlx5_ifc_destroy_lag_in_bits {
8597         u8         opcode[0x10];
8598         u8         reserved_at_10[0x10];
8599
8600         u8         reserved_at_20[0x10];
8601         u8         op_mod[0x10];
8602
8603         u8         reserved_at_40[0x40];
8604 };
8605
8606 struct mlx5_ifc_create_vport_lag_out_bits {
8607         u8         status[0x8];
8608         u8         reserved_at_8[0x18];
8609
8610         u8         syndrome[0x20];
8611
8612         u8         reserved_at_40[0x40];
8613 };
8614
8615 struct mlx5_ifc_create_vport_lag_in_bits {
8616         u8         opcode[0x10];
8617         u8         reserved_at_10[0x10];
8618
8619         u8         reserved_at_20[0x10];
8620         u8         op_mod[0x10];
8621
8622         u8         reserved_at_40[0x40];
8623 };
8624
8625 struct mlx5_ifc_destroy_vport_lag_out_bits {
8626         u8         status[0x8];
8627         u8         reserved_at_8[0x18];
8628
8629         u8         syndrome[0x20];
8630
8631         u8         reserved_at_40[0x40];
8632 };
8633
8634 struct mlx5_ifc_destroy_vport_lag_in_bits {
8635         u8         opcode[0x10];
8636         u8         reserved_at_10[0x10];
8637
8638         u8         reserved_at_20[0x10];
8639         u8         op_mod[0x10];
8640
8641         u8         reserved_at_40[0x40];
8642 };
8643
8644 #endif /* MLX5_IFC_H */