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[mirror_ubuntu-hirsute-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
64 };
65
66 enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71 };
72
73 enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77 };
78
79 enum {
80 MLX5_SHARED_RESOURCE_UID = 0xffff,
81 };
82
83 enum {
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
85 };
86
87 enum {
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
91 };
92
93 enum {
94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
95 MLX5_OBJ_TYPE_MKEY = 0xff01,
96 MLX5_OBJ_TYPE_QP = 0xff02,
97 MLX5_OBJ_TYPE_PSV = 0xff03,
98 MLX5_OBJ_TYPE_RMP = 0xff04,
99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
100 MLX5_OBJ_TYPE_RQ = 0xff06,
101 MLX5_OBJ_TYPE_SQ = 0xff07,
102 MLX5_OBJ_TYPE_TIR = 0xff08,
103 MLX5_OBJ_TYPE_TIS = 0xff09,
104 MLX5_OBJ_TYPE_DCT = 0xff0a,
105 MLX5_OBJ_TYPE_XRQ = 0xff0b,
106 MLX5_OBJ_TYPE_RQT = 0xff0e,
107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
108 MLX5_OBJ_TYPE_CQ = 0xff10,
109 };
110
111 enum {
112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
114 MLX5_CMD_OP_INIT_HCA = 0x102,
115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
116 MLX5_CMD_OP_ENABLE_HCA = 0x104,
117 MLX5_CMD_OP_DISABLE_HCA = 0x105,
118 MLX5_CMD_OP_QUERY_PAGES = 0x107,
119 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
120 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
121 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
122 MLX5_CMD_OP_SET_ISSI = 0x10b,
123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
125 MLX5_CMD_OP_ALLOC_SF = 0x113,
126 MLX5_CMD_OP_DEALLOC_SF = 0x114,
127 MLX5_CMD_OP_CREATE_MKEY = 0x200,
128 MLX5_CMD_OP_QUERY_MKEY = 0x201,
129 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
130 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
131 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
132 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
133 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
134 MLX5_CMD_OP_CREATE_EQ = 0x301,
135 MLX5_CMD_OP_DESTROY_EQ = 0x302,
136 MLX5_CMD_OP_QUERY_EQ = 0x303,
137 MLX5_CMD_OP_GEN_EQE = 0x304,
138 MLX5_CMD_OP_CREATE_CQ = 0x400,
139 MLX5_CMD_OP_DESTROY_CQ = 0x401,
140 MLX5_CMD_OP_QUERY_CQ = 0x402,
141 MLX5_CMD_OP_MODIFY_CQ = 0x403,
142 MLX5_CMD_OP_CREATE_QP = 0x500,
143 MLX5_CMD_OP_DESTROY_QP = 0x501,
144 MLX5_CMD_OP_RST2INIT_QP = 0x502,
145 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
146 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
147 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
148 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
149 MLX5_CMD_OP_2ERR_QP = 0x507,
150 MLX5_CMD_OP_2RST_QP = 0x50a,
151 MLX5_CMD_OP_QUERY_QP = 0x50b,
152 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
153 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
154 MLX5_CMD_OP_CREATE_PSV = 0x600,
155 MLX5_CMD_OP_DESTROY_PSV = 0x601,
156 MLX5_CMD_OP_CREATE_SRQ = 0x700,
157 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
158 MLX5_CMD_OP_QUERY_SRQ = 0x702,
159 MLX5_CMD_OP_ARM_RQ = 0x703,
160 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
161 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
162 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
163 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
164 MLX5_CMD_OP_CREATE_DCT = 0x710,
165 MLX5_CMD_OP_DESTROY_DCT = 0x711,
166 MLX5_CMD_OP_DRAIN_DCT = 0x712,
167 MLX5_CMD_OP_QUERY_DCT = 0x713,
168 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
169 MLX5_CMD_OP_CREATE_XRQ = 0x717,
170 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
171 MLX5_CMD_OP_QUERY_XRQ = 0x719,
172 MLX5_CMD_OP_ARM_XRQ = 0x71a,
173 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
174 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
175 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
176 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
177 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
178 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
179 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
180 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
181 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
182 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
183 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
184 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
185 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
186 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
187 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
188 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
190 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
191 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
192 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
193 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
194 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
195 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
196 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
197 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
198 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
199 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
200 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
201 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
202 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
203 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
204 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
205 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
206 MLX5_CMD_OP_ALLOC_PD = 0x800,
207 MLX5_CMD_OP_DEALLOC_PD = 0x801,
208 MLX5_CMD_OP_ALLOC_UAR = 0x802,
209 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
210 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
211 MLX5_CMD_OP_ACCESS_REG = 0x805,
212 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
213 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
214 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
215 MLX5_CMD_OP_MAD_IFC = 0x50d,
216 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
217 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
218 MLX5_CMD_OP_NOP = 0x80d,
219 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
220 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
221 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
222 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
223 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
224 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
225 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
226 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
227 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
228 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
229 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
230 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
231 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
232 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
233 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
234 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
235 MLX5_CMD_OP_CREATE_LAG = 0x840,
236 MLX5_CMD_OP_MODIFY_LAG = 0x841,
237 MLX5_CMD_OP_QUERY_LAG = 0x842,
238 MLX5_CMD_OP_DESTROY_LAG = 0x843,
239 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
240 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
241 MLX5_CMD_OP_CREATE_TIR = 0x900,
242 MLX5_CMD_OP_MODIFY_TIR = 0x901,
243 MLX5_CMD_OP_DESTROY_TIR = 0x902,
244 MLX5_CMD_OP_QUERY_TIR = 0x903,
245 MLX5_CMD_OP_CREATE_SQ = 0x904,
246 MLX5_CMD_OP_MODIFY_SQ = 0x905,
247 MLX5_CMD_OP_DESTROY_SQ = 0x906,
248 MLX5_CMD_OP_QUERY_SQ = 0x907,
249 MLX5_CMD_OP_CREATE_RQ = 0x908,
250 MLX5_CMD_OP_MODIFY_RQ = 0x909,
251 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
252 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
253 MLX5_CMD_OP_QUERY_RQ = 0x90b,
254 MLX5_CMD_OP_CREATE_RMP = 0x90c,
255 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
256 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
257 MLX5_CMD_OP_QUERY_RMP = 0x90f,
258 MLX5_CMD_OP_CREATE_TIS = 0x912,
259 MLX5_CMD_OP_MODIFY_TIS = 0x913,
260 MLX5_CMD_OP_DESTROY_TIS = 0x914,
261 MLX5_CMD_OP_QUERY_TIS = 0x915,
262 MLX5_CMD_OP_CREATE_RQT = 0x916,
263 MLX5_CMD_OP_MODIFY_RQT = 0x917,
264 MLX5_CMD_OP_DESTROY_RQT = 0x918,
265 MLX5_CMD_OP_QUERY_RQT = 0x919,
266 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
267 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
268 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
269 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
270 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
271 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
272 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
273 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
274 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
275 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
276 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
277 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
278 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
279 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
280 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
281 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
282 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
283 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
284 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
285 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
286 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
287 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
288 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
289 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
290 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
291 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
292 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
293 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
294 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
295 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
296 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
297 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
298 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
299 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
300 MLX5_CMD_OP_MAX
301 };
302
303 /* Valid range for general commands that don't work over an object */
304 enum {
305 MLX5_CMD_OP_GENERAL_START = 0xb00,
306 MLX5_CMD_OP_GENERAL_END = 0xd00,
307 };
308
309 struct mlx5_ifc_flow_table_fields_supported_bits {
310 u8 outer_dmac[0x1];
311 u8 outer_smac[0x1];
312 u8 outer_ether_type[0x1];
313 u8 outer_ip_version[0x1];
314 u8 outer_first_prio[0x1];
315 u8 outer_first_cfi[0x1];
316 u8 outer_first_vid[0x1];
317 u8 outer_ipv4_ttl[0x1];
318 u8 outer_second_prio[0x1];
319 u8 outer_second_cfi[0x1];
320 u8 outer_second_vid[0x1];
321 u8 reserved_at_b[0x1];
322 u8 outer_sip[0x1];
323 u8 outer_dip[0x1];
324 u8 outer_frag[0x1];
325 u8 outer_ip_protocol[0x1];
326 u8 outer_ip_ecn[0x1];
327 u8 outer_ip_dscp[0x1];
328 u8 outer_udp_sport[0x1];
329 u8 outer_udp_dport[0x1];
330 u8 outer_tcp_sport[0x1];
331 u8 outer_tcp_dport[0x1];
332 u8 outer_tcp_flags[0x1];
333 u8 outer_gre_protocol[0x1];
334 u8 outer_gre_key[0x1];
335 u8 outer_vxlan_vni[0x1];
336 u8 outer_geneve_vni[0x1];
337 u8 outer_geneve_oam[0x1];
338 u8 outer_geneve_protocol_type[0x1];
339 u8 outer_geneve_opt_len[0x1];
340 u8 reserved_at_1e[0x1];
341 u8 source_eswitch_port[0x1];
342
343 u8 inner_dmac[0x1];
344 u8 inner_smac[0x1];
345 u8 inner_ether_type[0x1];
346 u8 inner_ip_version[0x1];
347 u8 inner_first_prio[0x1];
348 u8 inner_first_cfi[0x1];
349 u8 inner_first_vid[0x1];
350 u8 reserved_at_27[0x1];
351 u8 inner_second_prio[0x1];
352 u8 inner_second_cfi[0x1];
353 u8 inner_second_vid[0x1];
354 u8 reserved_at_2b[0x1];
355 u8 inner_sip[0x1];
356 u8 inner_dip[0x1];
357 u8 inner_frag[0x1];
358 u8 inner_ip_protocol[0x1];
359 u8 inner_ip_ecn[0x1];
360 u8 inner_ip_dscp[0x1];
361 u8 inner_udp_sport[0x1];
362 u8 inner_udp_dport[0x1];
363 u8 inner_tcp_sport[0x1];
364 u8 inner_tcp_dport[0x1];
365 u8 inner_tcp_flags[0x1];
366 u8 reserved_at_37[0x9];
367
368 u8 geneve_tlv_option_0_data[0x1];
369 u8 reserved_at_41[0x4];
370 u8 outer_first_mpls_over_udp[0x4];
371 u8 outer_first_mpls_over_gre[0x4];
372 u8 inner_first_mpls[0x4];
373 u8 outer_first_mpls[0x4];
374 u8 reserved_at_55[0x2];
375 u8 outer_esp_spi[0x1];
376 u8 reserved_at_58[0x2];
377 u8 bth_dst_qp[0x1];
378
379 u8 reserved_at_5b[0x25];
380 };
381
382 struct mlx5_ifc_flow_table_prop_layout_bits {
383 u8 ft_support[0x1];
384 u8 reserved_at_1[0x1];
385 u8 flow_counter[0x1];
386 u8 flow_modify_en[0x1];
387 u8 modify_root[0x1];
388 u8 identified_miss_table_mode[0x1];
389 u8 flow_table_modify[0x1];
390 u8 reformat[0x1];
391 u8 decap[0x1];
392 u8 reserved_at_9[0x1];
393 u8 pop_vlan[0x1];
394 u8 push_vlan[0x1];
395 u8 reserved_at_c[0x1];
396 u8 pop_vlan_2[0x1];
397 u8 push_vlan_2[0x1];
398 u8 reformat_and_vlan_action[0x1];
399 u8 reserved_at_10[0x1];
400 u8 sw_owner[0x1];
401 u8 reformat_l3_tunnel_to_l2[0x1];
402 u8 reformat_l2_to_l3_tunnel[0x1];
403 u8 reformat_and_modify_action[0x1];
404 u8 reserved_at_15[0x2];
405 u8 table_miss_action_domain[0x1];
406 u8 termination_table[0x1];
407 u8 reserved_at_19[0x7];
408 u8 reserved_at_20[0x2];
409 u8 log_max_ft_size[0x6];
410 u8 log_max_modify_header_context[0x8];
411 u8 max_modify_header_actions[0x8];
412 u8 max_ft_level[0x8];
413
414 u8 reserved_at_40[0x20];
415
416 u8 reserved_at_60[0x18];
417 u8 log_max_ft_num[0x8];
418
419 u8 reserved_at_80[0x18];
420 u8 log_max_destination[0x8];
421
422 u8 log_max_flow_counter[0x8];
423 u8 reserved_at_a8[0x10];
424 u8 log_max_flow[0x8];
425
426 u8 reserved_at_c0[0x40];
427
428 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
429
430 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
431 };
432
433 struct mlx5_ifc_odp_per_transport_service_cap_bits {
434 u8 send[0x1];
435 u8 receive[0x1];
436 u8 write[0x1];
437 u8 read[0x1];
438 u8 atomic[0x1];
439 u8 srq_receive[0x1];
440 u8 reserved_at_6[0x1a];
441 };
442
443 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
444 u8 smac_47_16[0x20];
445
446 u8 smac_15_0[0x10];
447 u8 ethertype[0x10];
448
449 u8 dmac_47_16[0x20];
450
451 u8 dmac_15_0[0x10];
452 u8 first_prio[0x3];
453 u8 first_cfi[0x1];
454 u8 first_vid[0xc];
455
456 u8 ip_protocol[0x8];
457 u8 ip_dscp[0x6];
458 u8 ip_ecn[0x2];
459 u8 cvlan_tag[0x1];
460 u8 svlan_tag[0x1];
461 u8 frag[0x1];
462 u8 ip_version[0x4];
463 u8 tcp_flags[0x9];
464
465 u8 tcp_sport[0x10];
466 u8 tcp_dport[0x10];
467
468 u8 reserved_at_c0[0x18];
469 u8 ttl_hoplimit[0x8];
470
471 u8 udp_sport[0x10];
472 u8 udp_dport[0x10];
473
474 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
475
476 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
477 };
478
479 struct mlx5_ifc_nvgre_key_bits {
480 u8 hi[0x18];
481 u8 lo[0x8];
482 };
483
484 union mlx5_ifc_gre_key_bits {
485 struct mlx5_ifc_nvgre_key_bits nvgre;
486 u8 key[0x20];
487 };
488
489 struct mlx5_ifc_fte_match_set_misc_bits {
490 u8 gre_c_present[0x1];
491 u8 reserved_at_1[0x1];
492 u8 gre_k_present[0x1];
493 u8 gre_s_present[0x1];
494 u8 source_vhca_port[0x4];
495 u8 source_sqn[0x18];
496
497 u8 source_eswitch_owner_vhca_id[0x10];
498 u8 source_port[0x10];
499
500 u8 outer_second_prio[0x3];
501 u8 outer_second_cfi[0x1];
502 u8 outer_second_vid[0xc];
503 u8 inner_second_prio[0x3];
504 u8 inner_second_cfi[0x1];
505 u8 inner_second_vid[0xc];
506
507 u8 outer_second_cvlan_tag[0x1];
508 u8 inner_second_cvlan_tag[0x1];
509 u8 outer_second_svlan_tag[0x1];
510 u8 inner_second_svlan_tag[0x1];
511 u8 reserved_at_64[0xc];
512 u8 gre_protocol[0x10];
513
514 union mlx5_ifc_gre_key_bits gre_key;
515
516 u8 vxlan_vni[0x18];
517 u8 reserved_at_b8[0x8];
518
519 u8 geneve_vni[0x18];
520 u8 reserved_at_d8[0x7];
521 u8 geneve_oam[0x1];
522
523 u8 reserved_at_e0[0xc];
524 u8 outer_ipv6_flow_label[0x14];
525
526 u8 reserved_at_100[0xc];
527 u8 inner_ipv6_flow_label[0x14];
528
529 u8 reserved_at_120[0xa];
530 u8 geneve_opt_len[0x6];
531 u8 geneve_protocol_type[0x10];
532
533 u8 reserved_at_140[0x8];
534 u8 bth_dst_qp[0x18];
535 u8 reserved_at_160[0x20];
536 u8 outer_esp_spi[0x20];
537 u8 reserved_at_1a0[0x60];
538 };
539
540 struct mlx5_ifc_fte_match_mpls_bits {
541 u8 mpls_label[0x14];
542 u8 mpls_exp[0x3];
543 u8 mpls_s_bos[0x1];
544 u8 mpls_ttl[0x8];
545 };
546
547 struct mlx5_ifc_fte_match_set_misc2_bits {
548 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
549
550 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
551
552 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
553
554 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
555
556 u8 metadata_reg_c_7[0x20];
557
558 u8 metadata_reg_c_6[0x20];
559
560 u8 metadata_reg_c_5[0x20];
561
562 u8 metadata_reg_c_4[0x20];
563
564 u8 metadata_reg_c_3[0x20];
565
566 u8 metadata_reg_c_2[0x20];
567
568 u8 metadata_reg_c_1[0x20];
569
570 u8 metadata_reg_c_0[0x20];
571
572 u8 metadata_reg_a[0x20];
573
574 u8 metadata_reg_b[0x20];
575
576 u8 reserved_at_1c0[0x40];
577 };
578
579 struct mlx5_ifc_fte_match_set_misc3_bits {
580 u8 inner_tcp_seq_num[0x20];
581
582 u8 outer_tcp_seq_num[0x20];
583
584 u8 inner_tcp_ack_num[0x20];
585
586 u8 outer_tcp_ack_num[0x20];
587
588 u8 reserved_at_80[0x8];
589 u8 outer_vxlan_gpe_vni[0x18];
590
591 u8 outer_vxlan_gpe_next_protocol[0x8];
592 u8 outer_vxlan_gpe_flags[0x8];
593 u8 reserved_at_b0[0x10];
594
595 u8 icmp_header_data[0x20];
596
597 u8 icmpv6_header_data[0x20];
598
599 u8 icmp_type[0x8];
600 u8 icmp_code[0x8];
601 u8 icmpv6_type[0x8];
602 u8 icmpv6_code[0x8];
603
604 u8 geneve_tlv_option_0_data[0x20];
605
606 u8 reserved_at_140[0xc0];
607 };
608
609 struct mlx5_ifc_cmd_pas_bits {
610 u8 pa_h[0x20];
611
612 u8 pa_l[0x14];
613 u8 reserved_at_34[0xc];
614 };
615
616 struct mlx5_ifc_uint64_bits {
617 u8 hi[0x20];
618
619 u8 lo[0x20];
620 };
621
622 enum {
623 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
624 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
625 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
626 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
627 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
628 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
629 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
630 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
631 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
632 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
633 };
634
635 struct mlx5_ifc_ads_bits {
636 u8 fl[0x1];
637 u8 free_ar[0x1];
638 u8 reserved_at_2[0xe];
639 u8 pkey_index[0x10];
640
641 u8 reserved_at_20[0x8];
642 u8 grh[0x1];
643 u8 mlid[0x7];
644 u8 rlid[0x10];
645
646 u8 ack_timeout[0x5];
647 u8 reserved_at_45[0x3];
648 u8 src_addr_index[0x8];
649 u8 reserved_at_50[0x4];
650 u8 stat_rate[0x4];
651 u8 hop_limit[0x8];
652
653 u8 reserved_at_60[0x4];
654 u8 tclass[0x8];
655 u8 flow_label[0x14];
656
657 u8 rgid_rip[16][0x8];
658
659 u8 reserved_at_100[0x4];
660 u8 f_dscp[0x1];
661 u8 f_ecn[0x1];
662 u8 reserved_at_106[0x1];
663 u8 f_eth_prio[0x1];
664 u8 ecn[0x2];
665 u8 dscp[0x6];
666 u8 udp_sport[0x10];
667
668 u8 dei_cfi[0x1];
669 u8 eth_prio[0x3];
670 u8 sl[0x4];
671 u8 vhca_port_num[0x8];
672 u8 rmac_47_32[0x10];
673
674 u8 rmac_31_0[0x20];
675 };
676
677 struct mlx5_ifc_flow_table_nic_cap_bits {
678 u8 nic_rx_multi_path_tirs[0x1];
679 u8 nic_rx_multi_path_tirs_fts[0x1];
680 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
681 u8 reserved_at_3[0x1d];
682 u8 encap_general_header[0x1];
683 u8 reserved_at_21[0xa];
684 u8 log_max_packet_reformat_context[0x5];
685 u8 reserved_at_30[0x6];
686 u8 max_encap_header_size[0xa];
687 u8 reserved_at_40[0x1c0];
688
689 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
690
691 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
692
693 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
694
695 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
696
697 u8 reserved_at_a00[0x200];
698
699 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
700
701 u8 reserved_at_e00[0x1200];
702
703 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
704
705 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
706
707 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
708
709 u8 reserved_at_20c0[0x5f40];
710 };
711
712 enum {
713 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
714 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
715 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
716 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
717 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
718 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
719 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
720 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
721 };
722
723 struct mlx5_ifc_flow_table_eswitch_cap_bits {
724 u8 fdb_to_vport_reg_c_id[0x8];
725 u8 reserved_at_8[0xf];
726 u8 flow_source[0x1];
727 u8 reserved_at_18[0x2];
728 u8 multi_fdb_encap[0x1];
729 u8 reserved_at_1b[0x1];
730 u8 fdb_multi_path_to_table[0x1];
731 u8 reserved_at_1d[0x3];
732
733 u8 reserved_at_20[0x1e0];
734
735 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
736
737 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
738
739 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
740
741 u8 reserved_at_800[0x1000];
742
743 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
744
745 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
746
747 u8 sw_steering_uplink_icm_address_rx[0x40];
748
749 u8 sw_steering_uplink_icm_address_tx[0x40];
750
751 u8 reserved_at_1900[0x6700];
752 };
753
754 enum {
755 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
756 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
757 };
758
759 struct mlx5_ifc_e_switch_cap_bits {
760 u8 vport_svlan_strip[0x1];
761 u8 vport_cvlan_strip[0x1];
762 u8 vport_svlan_insert[0x1];
763 u8 vport_cvlan_insert_if_not_exist[0x1];
764 u8 vport_cvlan_insert_overwrite[0x1];
765 u8 reserved_at_5[0x3];
766 u8 esw_uplink_ingress_acl[0x1];
767 u8 reserved_at_9[0x10];
768 u8 esw_functions_changed[0x1];
769 u8 reserved_at_1a[0x1];
770 u8 ecpf_vport_exists[0x1];
771 u8 counter_eswitch_affinity[0x1];
772 u8 merged_eswitch[0x1];
773 u8 nic_vport_node_guid_modify[0x1];
774 u8 nic_vport_port_guid_modify[0x1];
775
776 u8 vxlan_encap_decap[0x1];
777 u8 nvgre_encap_decap[0x1];
778 u8 reserved_at_22[0x1];
779 u8 log_max_fdb_encap_uplink[0x5];
780 u8 reserved_at_21[0x3];
781 u8 log_max_packet_reformat_context[0x5];
782 u8 reserved_2b[0x6];
783 u8 max_encap_header_size[0xa];
784
785 u8 reserved_at_40[0xb];
786 u8 log_max_esw_sf[0x5];
787 u8 esw_sf_base_id[0x10];
788
789 u8 reserved_at_60[0x7a0];
790
791 };
792
793 struct mlx5_ifc_qos_cap_bits {
794 u8 packet_pacing[0x1];
795 u8 esw_scheduling[0x1];
796 u8 esw_bw_share[0x1];
797 u8 esw_rate_limit[0x1];
798 u8 reserved_at_4[0x1];
799 u8 packet_pacing_burst_bound[0x1];
800 u8 packet_pacing_typical_size[0x1];
801 u8 reserved_at_7[0x19];
802
803 u8 reserved_at_20[0x20];
804
805 u8 packet_pacing_max_rate[0x20];
806
807 u8 packet_pacing_min_rate[0x20];
808
809 u8 reserved_at_80[0x10];
810 u8 packet_pacing_rate_table_size[0x10];
811
812 u8 esw_element_type[0x10];
813 u8 esw_tsar_type[0x10];
814
815 u8 reserved_at_c0[0x10];
816 u8 max_qos_para_vport[0x10];
817
818 u8 max_tsar_bw_share[0x20];
819
820 u8 reserved_at_100[0x700];
821 };
822
823 struct mlx5_ifc_debug_cap_bits {
824 u8 core_dump_general[0x1];
825 u8 core_dump_qp[0x1];
826 u8 reserved_at_2[0x1e];
827
828 u8 reserved_at_20[0x2];
829 u8 stall_detect[0x1];
830 u8 reserved_at_23[0x1d];
831
832 u8 reserved_at_40[0x7c0];
833 };
834
835 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
836 u8 csum_cap[0x1];
837 u8 vlan_cap[0x1];
838 u8 lro_cap[0x1];
839 u8 lro_psh_flag[0x1];
840 u8 lro_time_stamp[0x1];
841 u8 reserved_at_5[0x2];
842 u8 wqe_vlan_insert[0x1];
843 u8 self_lb_en_modifiable[0x1];
844 u8 reserved_at_9[0x2];
845 u8 max_lso_cap[0x5];
846 u8 multi_pkt_send_wqe[0x2];
847 u8 wqe_inline_mode[0x2];
848 u8 rss_ind_tbl_cap[0x4];
849 u8 reg_umr_sq[0x1];
850 u8 scatter_fcs[0x1];
851 u8 enhanced_multi_pkt_send_wqe[0x1];
852 u8 tunnel_lso_const_out_ip_id[0x1];
853 u8 reserved_at_1c[0x2];
854 u8 tunnel_stateless_gre[0x1];
855 u8 tunnel_stateless_vxlan[0x1];
856
857 u8 swp[0x1];
858 u8 swp_csum[0x1];
859 u8 swp_lso[0x1];
860 u8 cqe_checksum_full[0x1];
861 u8 reserved_at_24[0x5];
862 u8 tunnel_stateless_ip_over_ip[0x1];
863 u8 reserved_at_2a[0x6];
864 u8 max_vxlan_udp_ports[0x8];
865 u8 reserved_at_38[0x6];
866 u8 max_geneve_opt_len[0x1];
867 u8 tunnel_stateless_geneve_rx[0x1];
868
869 u8 reserved_at_40[0x10];
870 u8 lro_min_mss_size[0x10];
871
872 u8 reserved_at_60[0x120];
873
874 u8 lro_timer_supported_periods[4][0x20];
875
876 u8 reserved_at_200[0x600];
877 };
878
879 struct mlx5_ifc_roce_cap_bits {
880 u8 roce_apm[0x1];
881 u8 reserved_at_1[0x1f];
882
883 u8 reserved_at_20[0x60];
884
885 u8 reserved_at_80[0xc];
886 u8 l3_type[0x4];
887 u8 reserved_at_90[0x8];
888 u8 roce_version[0x8];
889
890 u8 reserved_at_a0[0x10];
891 u8 r_roce_dest_udp_port[0x10];
892
893 u8 r_roce_max_src_udp_port[0x10];
894 u8 r_roce_min_src_udp_port[0x10];
895
896 u8 reserved_at_e0[0x10];
897 u8 roce_address_table_size[0x10];
898
899 u8 reserved_at_100[0x700];
900 };
901
902 struct mlx5_ifc_sync_steering_in_bits {
903 u8 opcode[0x10];
904 u8 uid[0x10];
905
906 u8 reserved_at_20[0x10];
907 u8 op_mod[0x10];
908
909 u8 reserved_at_40[0xc0];
910 };
911
912 struct mlx5_ifc_sync_steering_out_bits {
913 u8 status[0x8];
914 u8 reserved_at_8[0x18];
915
916 u8 syndrome[0x20];
917
918 u8 reserved_at_40[0x40];
919 };
920
921 struct mlx5_ifc_device_mem_cap_bits {
922 u8 memic[0x1];
923 u8 reserved_at_1[0x1f];
924
925 u8 reserved_at_20[0xb];
926 u8 log_min_memic_alloc_size[0x5];
927 u8 reserved_at_30[0x8];
928 u8 log_max_memic_addr_alignment[0x8];
929
930 u8 memic_bar_start_addr[0x40];
931
932 u8 memic_bar_size[0x20];
933
934 u8 max_memic_size[0x20];
935
936 u8 steering_sw_icm_start_address[0x40];
937
938 u8 reserved_at_100[0x8];
939 u8 log_header_modify_sw_icm_size[0x8];
940 u8 reserved_at_110[0x2];
941 u8 log_sw_icm_alloc_granularity[0x6];
942 u8 log_steering_sw_icm_size[0x8];
943
944 u8 reserved_at_120[0x20];
945
946 u8 header_modify_sw_icm_start_address[0x40];
947
948 u8 reserved_at_180[0x680];
949 };
950
951 struct mlx5_ifc_device_event_cap_bits {
952 u8 user_affiliated_events[4][0x40];
953
954 u8 user_unaffiliated_events[4][0x40];
955 };
956
957 struct mlx5_ifc_device_virtio_emulation_cap_bits {
958 u8 reserved_at_0[0x20];
959
960 u8 reserved_at_20[0x13];
961 u8 log_doorbell_stride[0x5];
962 u8 reserved_at_38[0x3];
963 u8 log_doorbell_bar_size[0x5];
964
965 u8 doorbell_bar_offset[0x40];
966
967 u8 reserved_at_80[0x780];
968 };
969
970 enum {
971 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
972 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
973 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
974 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
975 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
976 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
977 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
978 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
979 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
980 };
981
982 enum {
983 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
984 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
985 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
986 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
987 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
988 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
989 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
990 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
991 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
992 };
993
994 struct mlx5_ifc_atomic_caps_bits {
995 u8 reserved_at_0[0x40];
996
997 u8 atomic_req_8B_endianness_mode[0x2];
998 u8 reserved_at_42[0x4];
999 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1000
1001 u8 reserved_at_47[0x19];
1002
1003 u8 reserved_at_60[0x20];
1004
1005 u8 reserved_at_80[0x10];
1006 u8 atomic_operations[0x10];
1007
1008 u8 reserved_at_a0[0x10];
1009 u8 atomic_size_qp[0x10];
1010
1011 u8 reserved_at_c0[0x10];
1012 u8 atomic_size_dc[0x10];
1013
1014 u8 reserved_at_e0[0x720];
1015 };
1016
1017 struct mlx5_ifc_odp_cap_bits {
1018 u8 reserved_at_0[0x40];
1019
1020 u8 sig[0x1];
1021 u8 reserved_at_41[0x1f];
1022
1023 u8 reserved_at_60[0x20];
1024
1025 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1026
1027 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1028
1029 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1030
1031 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1032
1033 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1034
1035 u8 reserved_at_120[0x6E0];
1036 };
1037
1038 struct mlx5_ifc_calc_op {
1039 u8 reserved_at_0[0x10];
1040 u8 reserved_at_10[0x9];
1041 u8 op_swap_endianness[0x1];
1042 u8 op_min[0x1];
1043 u8 op_xor[0x1];
1044 u8 op_or[0x1];
1045 u8 op_and[0x1];
1046 u8 op_max[0x1];
1047 u8 op_add[0x1];
1048 };
1049
1050 struct mlx5_ifc_vector_calc_cap_bits {
1051 u8 calc_matrix[0x1];
1052 u8 reserved_at_1[0x1f];
1053 u8 reserved_at_20[0x8];
1054 u8 max_vec_count[0x8];
1055 u8 reserved_at_30[0xd];
1056 u8 max_chunk_size[0x3];
1057 struct mlx5_ifc_calc_op calc0;
1058 struct mlx5_ifc_calc_op calc1;
1059 struct mlx5_ifc_calc_op calc2;
1060 struct mlx5_ifc_calc_op calc3;
1061
1062 u8 reserved_at_c0[0x720];
1063 };
1064
1065 struct mlx5_ifc_tls_cap_bits {
1066 u8 tls_1_2_aes_gcm_128[0x1];
1067 u8 tls_1_3_aes_gcm_128[0x1];
1068 u8 tls_1_2_aes_gcm_256[0x1];
1069 u8 tls_1_3_aes_gcm_256[0x1];
1070 u8 reserved_at_4[0x1c];
1071
1072 u8 reserved_at_20[0x7e0];
1073 };
1074
1075 enum {
1076 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1077 MLX5_WQ_TYPE_CYCLIC = 0x1,
1078 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1079 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1080 };
1081
1082 enum {
1083 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1084 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1085 };
1086
1087 enum {
1088 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1089 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1090 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1091 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1092 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1093 };
1094
1095 enum {
1096 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1097 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1098 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1099 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1100 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1101 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1102 };
1103
1104 enum {
1105 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1106 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1107 };
1108
1109 enum {
1110 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1111 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1112 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1113 };
1114
1115 enum {
1116 MLX5_CAP_PORT_TYPE_IB = 0x0,
1117 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1118 };
1119
1120 enum {
1121 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1122 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1123 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1124 };
1125
1126 enum {
1127 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1128 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1129 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1130 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1131 };
1132
1133 enum {
1134 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1135 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1136 };
1137
1138 #define MLX5_FC_BULK_SIZE_FACTOR 128
1139
1140 enum mlx5_fc_bulk_alloc_bitmask {
1141 MLX5_FC_BULK_128 = (1 << 0),
1142 MLX5_FC_BULK_256 = (1 << 1),
1143 MLX5_FC_BULK_512 = (1 << 2),
1144 MLX5_FC_BULK_1024 = (1 << 3),
1145 MLX5_FC_BULK_2048 = (1 << 4),
1146 MLX5_FC_BULK_4096 = (1 << 5),
1147 MLX5_FC_BULK_8192 = (1 << 6),
1148 MLX5_FC_BULK_16384 = (1 << 7),
1149 };
1150
1151 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1152
1153 struct mlx5_ifc_cmd_hca_cap_bits {
1154 u8 reserved_at_0[0x30];
1155 u8 vhca_id[0x10];
1156
1157 u8 reserved_at_40[0x40];
1158
1159 u8 log_max_srq_sz[0x8];
1160 u8 log_max_qp_sz[0x8];
1161 u8 event_cap[0x1];
1162 u8 reserved_at_91[0x7];
1163 u8 prio_tag_required[0x1];
1164 u8 reserved_at_99[0x2];
1165 u8 log_max_qp[0x5];
1166
1167 u8 reserved_at_a0[0xb];
1168 u8 log_max_srq[0x5];
1169 u8 reserved_at_b0[0x10];
1170
1171 u8 max_sgl_for_optimized_performance[0x8];
1172 u8 log_max_cq_sz[0x8];
1173 u8 reserved_at_d0[0xb];
1174 u8 log_max_cq[0x5];
1175
1176 u8 log_max_eq_sz[0x8];
1177 u8 reserved_at_e8[0x2];
1178 u8 log_max_mkey[0x6];
1179 u8 reserved_at_f0[0x8];
1180 u8 dump_fill_mkey[0x1];
1181 u8 reserved_at_f9[0x2];
1182 u8 fast_teardown[0x1];
1183 u8 log_max_eq[0x4];
1184
1185 u8 max_indirection[0x8];
1186 u8 fixed_buffer_size[0x1];
1187 u8 log_max_mrw_sz[0x7];
1188 u8 force_teardown[0x1];
1189 u8 reserved_at_111[0x1];
1190 u8 log_max_bsf_list_size[0x6];
1191 u8 umr_extended_translation_offset[0x1];
1192 u8 null_mkey[0x1];
1193 u8 log_max_klm_list_size[0x6];
1194
1195 u8 reserved_at_120[0xa];
1196 u8 log_max_ra_req_dc[0x6];
1197 u8 reserved_at_130[0xa];
1198 u8 log_max_ra_res_dc[0x6];
1199
1200 u8 reserved_at_140[0xa];
1201 u8 log_max_ra_req_qp[0x6];
1202 u8 reserved_at_150[0xa];
1203 u8 log_max_ra_res_qp[0x6];
1204
1205 u8 end_pad[0x1];
1206 u8 cc_query_allowed[0x1];
1207 u8 cc_modify_allowed[0x1];
1208 u8 start_pad[0x1];
1209 u8 cache_line_128byte[0x1];
1210 u8 reserved_at_165[0x4];
1211 u8 rts2rts_qp_counters_set_id[0x1];
1212 u8 reserved_at_16a[0x2];
1213 u8 vnic_env_int_rq_oob[0x1];
1214 u8 sbcam_reg[0x1];
1215 u8 reserved_at_16e[0x1];
1216 u8 qcam_reg[0x1];
1217 u8 gid_table_size[0x10];
1218
1219 u8 out_of_seq_cnt[0x1];
1220 u8 vport_counters[0x1];
1221 u8 retransmission_q_counters[0x1];
1222 u8 debug[0x1];
1223 u8 modify_rq_counter_set_id[0x1];
1224 u8 rq_delay_drop[0x1];
1225 u8 max_qp_cnt[0xa];
1226 u8 pkey_table_size[0x10];
1227
1228 u8 vport_group_manager[0x1];
1229 u8 vhca_group_manager[0x1];
1230 u8 ib_virt[0x1];
1231 u8 eth_virt[0x1];
1232 u8 vnic_env_queue_counters[0x1];
1233 u8 ets[0x1];
1234 u8 nic_flow_table[0x1];
1235 u8 eswitch_manager[0x1];
1236 u8 device_memory[0x1];
1237 u8 mcam_reg[0x1];
1238 u8 pcam_reg[0x1];
1239 u8 local_ca_ack_delay[0x5];
1240 u8 port_module_event[0x1];
1241 u8 enhanced_error_q_counters[0x1];
1242 u8 ports_check[0x1];
1243 u8 reserved_at_1b3[0x1];
1244 u8 disable_link_up[0x1];
1245 u8 beacon_led[0x1];
1246 u8 port_type[0x2];
1247 u8 num_ports[0x8];
1248
1249 u8 reserved_at_1c0[0x1];
1250 u8 pps[0x1];
1251 u8 pps_modify[0x1];
1252 u8 log_max_msg[0x5];
1253 u8 reserved_at_1c8[0x4];
1254 u8 max_tc[0x4];
1255 u8 temp_warn_event[0x1];
1256 u8 dcbx[0x1];
1257 u8 general_notification_event[0x1];
1258 u8 reserved_at_1d3[0x2];
1259 u8 fpga[0x1];
1260 u8 rol_s[0x1];
1261 u8 rol_g[0x1];
1262 u8 reserved_at_1d8[0x1];
1263 u8 wol_s[0x1];
1264 u8 wol_g[0x1];
1265 u8 wol_a[0x1];
1266 u8 wol_b[0x1];
1267 u8 wol_m[0x1];
1268 u8 wol_u[0x1];
1269 u8 wol_p[0x1];
1270
1271 u8 stat_rate_support[0x10];
1272 u8 reserved_at_1f0[0xc];
1273 u8 cqe_version[0x4];
1274
1275 u8 compact_address_vector[0x1];
1276 u8 striding_rq[0x1];
1277 u8 reserved_at_202[0x1];
1278 u8 ipoib_enhanced_offloads[0x1];
1279 u8 ipoib_basic_offloads[0x1];
1280 u8 reserved_at_205[0x1];
1281 u8 repeated_block_disabled[0x1];
1282 u8 umr_modify_entity_size_disabled[0x1];
1283 u8 umr_modify_atomic_disabled[0x1];
1284 u8 umr_indirect_mkey_disabled[0x1];
1285 u8 umr_fence[0x2];
1286 u8 dc_req_scat_data_cqe[0x1];
1287 u8 reserved_at_20d[0x2];
1288 u8 drain_sigerr[0x1];
1289 u8 cmdif_checksum[0x2];
1290 u8 sigerr_cqe[0x1];
1291 u8 reserved_at_213[0x1];
1292 u8 wq_signature[0x1];
1293 u8 sctr_data_cqe[0x1];
1294 u8 reserved_at_216[0x1];
1295 u8 sho[0x1];
1296 u8 tph[0x1];
1297 u8 rf[0x1];
1298 u8 dct[0x1];
1299 u8 qos[0x1];
1300 u8 eth_net_offloads[0x1];
1301 u8 roce[0x1];
1302 u8 atomic[0x1];
1303 u8 reserved_at_21f[0x1];
1304
1305 u8 cq_oi[0x1];
1306 u8 cq_resize[0x1];
1307 u8 cq_moderation[0x1];
1308 u8 reserved_at_223[0x3];
1309 u8 cq_eq_remap[0x1];
1310 u8 pg[0x1];
1311 u8 block_lb_mc[0x1];
1312 u8 reserved_at_229[0x1];
1313 u8 scqe_break_moderation[0x1];
1314 u8 cq_period_start_from_cqe[0x1];
1315 u8 cd[0x1];
1316 u8 reserved_at_22d[0x1];
1317 u8 apm[0x1];
1318 u8 vector_calc[0x1];
1319 u8 umr_ptr_rlky[0x1];
1320 u8 imaicl[0x1];
1321 u8 qp_packet_based[0x1];
1322 u8 reserved_at_233[0x3];
1323 u8 qkv[0x1];
1324 u8 pkv[0x1];
1325 u8 set_deth_sqpn[0x1];
1326 u8 reserved_at_239[0x3];
1327 u8 xrc[0x1];
1328 u8 ud[0x1];
1329 u8 uc[0x1];
1330 u8 rc[0x1];
1331
1332 u8 uar_4k[0x1];
1333 u8 reserved_at_241[0x9];
1334 u8 uar_sz[0x6];
1335 u8 reserved_at_250[0x8];
1336 u8 log_pg_sz[0x8];
1337
1338 u8 bf[0x1];
1339 u8 driver_version[0x1];
1340 u8 pad_tx_eth_packet[0x1];
1341 u8 reserved_at_263[0x8];
1342 u8 log_bf_reg_size[0x5];
1343
1344 u8 reserved_at_270[0x8];
1345 u8 lag_tx_port_affinity[0x1];
1346 u8 reserved_at_279[0x2];
1347 u8 lag_master[0x1];
1348 u8 num_lag_ports[0x4];
1349
1350 u8 reserved_at_280[0x10];
1351 u8 max_wqe_sz_sq[0x10];
1352
1353 u8 reserved_at_2a0[0x10];
1354 u8 max_wqe_sz_rq[0x10];
1355
1356 u8 max_flow_counter_31_16[0x10];
1357 u8 max_wqe_sz_sq_dc[0x10];
1358
1359 u8 reserved_at_2e0[0x7];
1360 u8 max_qp_mcg[0x19];
1361
1362 u8 reserved_at_300[0x10];
1363 u8 flow_counter_bulk_alloc[0x8];
1364 u8 log_max_mcg[0x8];
1365
1366 u8 reserved_at_320[0x3];
1367 u8 log_max_transport_domain[0x5];
1368 u8 reserved_at_328[0x3];
1369 u8 log_max_pd[0x5];
1370 u8 reserved_at_330[0xb];
1371 u8 log_max_xrcd[0x5];
1372
1373 u8 nic_receive_steering_discard[0x1];
1374 u8 receive_discard_vport_down[0x1];
1375 u8 transmit_discard_vport_down[0x1];
1376 u8 reserved_at_343[0x5];
1377 u8 log_max_flow_counter_bulk[0x8];
1378 u8 max_flow_counter_15_0[0x10];
1379
1380
1381 u8 reserved_at_360[0x3];
1382 u8 log_max_rq[0x5];
1383 u8 reserved_at_368[0x3];
1384 u8 log_max_sq[0x5];
1385 u8 reserved_at_370[0x3];
1386 u8 log_max_tir[0x5];
1387 u8 reserved_at_378[0x3];
1388 u8 log_max_tis[0x5];
1389
1390 u8 basic_cyclic_rcv_wqe[0x1];
1391 u8 reserved_at_381[0x2];
1392 u8 log_max_rmp[0x5];
1393 u8 reserved_at_388[0x3];
1394 u8 log_max_rqt[0x5];
1395 u8 reserved_at_390[0x3];
1396 u8 log_max_rqt_size[0x5];
1397 u8 reserved_at_398[0x3];
1398 u8 log_max_tis_per_sq[0x5];
1399
1400 u8 ext_stride_num_range[0x1];
1401 u8 reserved_at_3a1[0x2];
1402 u8 log_max_stride_sz_rq[0x5];
1403 u8 reserved_at_3a8[0x3];
1404 u8 log_min_stride_sz_rq[0x5];
1405 u8 reserved_at_3b0[0x3];
1406 u8 log_max_stride_sz_sq[0x5];
1407 u8 reserved_at_3b8[0x3];
1408 u8 log_min_stride_sz_sq[0x5];
1409
1410 u8 hairpin[0x1];
1411 u8 reserved_at_3c1[0x2];
1412 u8 log_max_hairpin_queues[0x5];
1413 u8 reserved_at_3c8[0x3];
1414 u8 log_max_hairpin_wq_data_sz[0x5];
1415 u8 reserved_at_3d0[0x3];
1416 u8 log_max_hairpin_num_packets[0x5];
1417 u8 reserved_at_3d8[0x3];
1418 u8 log_max_wq_sz[0x5];
1419
1420 u8 nic_vport_change_event[0x1];
1421 u8 disable_local_lb_uc[0x1];
1422 u8 disable_local_lb_mc[0x1];
1423 u8 log_min_hairpin_wq_data_sz[0x5];
1424 u8 reserved_at_3e8[0x3];
1425 u8 log_max_vlan_list[0x5];
1426 u8 reserved_at_3f0[0x3];
1427 u8 log_max_current_mc_list[0x5];
1428 u8 reserved_at_3f8[0x3];
1429 u8 log_max_current_uc_list[0x5];
1430
1431 u8 general_obj_types[0x40];
1432
1433 u8 reserved_at_440[0x20];
1434
1435 u8 tls[0x1];
1436 u8 reserved_at_461[0x2];
1437 u8 log_max_uctx[0x5];
1438 u8 reserved_at_468[0x3];
1439 u8 log_max_umem[0x5];
1440 u8 max_num_eqs[0x10];
1441
1442 u8 reserved_at_480[0x3];
1443 u8 log_max_l2_table[0x5];
1444 u8 reserved_at_488[0x8];
1445 u8 log_uar_page_sz[0x10];
1446
1447 u8 reserved_at_4a0[0x20];
1448 u8 device_frequency_mhz[0x20];
1449 u8 device_frequency_khz[0x20];
1450
1451 u8 reserved_at_500[0x20];
1452 u8 num_of_uars_per_page[0x20];
1453
1454 u8 flex_parser_protocols[0x20];
1455
1456 u8 max_geneve_tlv_options[0x8];
1457 u8 reserved_at_568[0x3];
1458 u8 max_geneve_tlv_option_data_len[0x5];
1459 u8 reserved_at_570[0x10];
1460
1461 u8 reserved_at_580[0x33];
1462 u8 log_max_dek[0x5];
1463 u8 reserved_at_5b8[0x4];
1464 u8 mini_cqe_resp_stride_index[0x1];
1465 u8 cqe_128_always[0x1];
1466 u8 cqe_compression_128[0x1];
1467 u8 cqe_compression[0x1];
1468
1469 u8 cqe_compression_timeout[0x10];
1470 u8 cqe_compression_max_num[0x10];
1471
1472 u8 reserved_at_5e0[0x10];
1473 u8 tag_matching[0x1];
1474 u8 rndv_offload_rc[0x1];
1475 u8 rndv_offload_dc[0x1];
1476 u8 log_tag_matching_list_sz[0x5];
1477 u8 reserved_at_5f8[0x3];
1478 u8 log_max_xrq[0x5];
1479
1480 u8 affiliate_nic_vport_criteria[0x8];
1481 u8 native_port_num[0x8];
1482 u8 num_vhca_ports[0x8];
1483 u8 reserved_at_618[0x6];
1484 u8 sw_owner_id[0x1];
1485 u8 reserved_at_61f[0x1];
1486
1487 u8 max_num_of_monitor_counters[0x10];
1488 u8 num_ppcnt_monitor_counters[0x10];
1489
1490 u8 reserved_at_640[0x10];
1491 u8 num_q_monitor_counters[0x10];
1492
1493 u8 reserved_at_660[0x20];
1494
1495 u8 sf[0x1];
1496 u8 sf_set_partition[0x1];
1497 u8 reserved_at_682[0x1];
1498 u8 log_max_sf[0x5];
1499 u8 reserved_at_688[0x8];
1500 u8 log_min_sf_size[0x8];
1501 u8 max_num_sf_partitions[0x8];
1502
1503 u8 uctx_cap[0x20];
1504
1505 u8 reserved_at_6c0[0x4];
1506 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1507 u8 flex_parser_id_icmp_dw1[0x4];
1508 u8 flex_parser_id_icmp_dw0[0x4];
1509 u8 flex_parser_id_icmpv6_dw1[0x4];
1510 u8 flex_parser_id_icmpv6_dw0[0x4];
1511 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1512 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1513
1514 u8 reserved_at_6e0[0x10];
1515 u8 sf_base_id[0x10];
1516
1517 u8 reserved_at_700[0x80];
1518 u8 vhca_tunnel_commands[0x40];
1519 u8 reserved_at_7c0[0x40];
1520 };
1521
1522 enum mlx5_flow_destination_type {
1523 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1524 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1525 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1526
1527 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1528 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1529 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1530 };
1531
1532 enum mlx5_flow_table_miss_action {
1533 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1534 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1535 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1536 };
1537
1538 struct mlx5_ifc_dest_format_struct_bits {
1539 u8 destination_type[0x8];
1540 u8 destination_id[0x18];
1541
1542 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1543 u8 packet_reformat[0x1];
1544 u8 reserved_at_22[0xe];
1545 u8 destination_eswitch_owner_vhca_id[0x10];
1546 };
1547
1548 struct mlx5_ifc_flow_counter_list_bits {
1549 u8 flow_counter_id[0x20];
1550
1551 u8 reserved_at_20[0x20];
1552 };
1553
1554 struct mlx5_ifc_extended_dest_format_bits {
1555 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1556
1557 u8 packet_reformat_id[0x20];
1558
1559 u8 reserved_at_60[0x20];
1560 };
1561
1562 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1563 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1564 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1565 };
1566
1567 struct mlx5_ifc_fte_match_param_bits {
1568 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1569
1570 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1571
1572 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1573
1574 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1575
1576 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1577
1578 u8 reserved_at_a00[0x600];
1579 };
1580
1581 enum {
1582 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1583 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1584 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1585 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1586 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1587 };
1588
1589 struct mlx5_ifc_rx_hash_field_select_bits {
1590 u8 l3_prot_type[0x1];
1591 u8 l4_prot_type[0x1];
1592 u8 selected_fields[0x1e];
1593 };
1594
1595 enum {
1596 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1597 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1598 };
1599
1600 enum {
1601 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1602 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1603 };
1604
1605 struct mlx5_ifc_wq_bits {
1606 u8 wq_type[0x4];
1607 u8 wq_signature[0x1];
1608 u8 end_padding_mode[0x2];
1609 u8 cd_slave[0x1];
1610 u8 reserved_at_8[0x18];
1611
1612 u8 hds_skip_first_sge[0x1];
1613 u8 log2_hds_buf_size[0x3];
1614 u8 reserved_at_24[0x7];
1615 u8 page_offset[0x5];
1616 u8 lwm[0x10];
1617
1618 u8 reserved_at_40[0x8];
1619 u8 pd[0x18];
1620
1621 u8 reserved_at_60[0x8];
1622 u8 uar_page[0x18];
1623
1624 u8 dbr_addr[0x40];
1625
1626 u8 hw_counter[0x20];
1627
1628 u8 sw_counter[0x20];
1629
1630 u8 reserved_at_100[0xc];
1631 u8 log_wq_stride[0x4];
1632 u8 reserved_at_110[0x3];
1633 u8 log_wq_pg_sz[0x5];
1634 u8 reserved_at_118[0x3];
1635 u8 log_wq_sz[0x5];
1636
1637 u8 dbr_umem_valid[0x1];
1638 u8 wq_umem_valid[0x1];
1639 u8 reserved_at_122[0x1];
1640 u8 log_hairpin_num_packets[0x5];
1641 u8 reserved_at_128[0x3];
1642 u8 log_hairpin_data_sz[0x5];
1643
1644 u8 reserved_at_130[0x4];
1645 u8 log_wqe_num_of_strides[0x4];
1646 u8 two_byte_shift_en[0x1];
1647 u8 reserved_at_139[0x4];
1648 u8 log_wqe_stride_size[0x3];
1649
1650 u8 reserved_at_140[0x4c0];
1651
1652 struct mlx5_ifc_cmd_pas_bits pas[0];
1653 };
1654
1655 struct mlx5_ifc_rq_num_bits {
1656 u8 reserved_at_0[0x8];
1657 u8 rq_num[0x18];
1658 };
1659
1660 struct mlx5_ifc_mac_address_layout_bits {
1661 u8 reserved_at_0[0x10];
1662 u8 mac_addr_47_32[0x10];
1663
1664 u8 mac_addr_31_0[0x20];
1665 };
1666
1667 struct mlx5_ifc_vlan_layout_bits {
1668 u8 reserved_at_0[0x14];
1669 u8 vlan[0x0c];
1670
1671 u8 reserved_at_20[0x20];
1672 };
1673
1674 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1675 u8 reserved_at_0[0xa0];
1676
1677 u8 min_time_between_cnps[0x20];
1678
1679 u8 reserved_at_c0[0x12];
1680 u8 cnp_dscp[0x6];
1681 u8 reserved_at_d8[0x4];
1682 u8 cnp_prio_mode[0x1];
1683 u8 cnp_802p_prio[0x3];
1684
1685 u8 reserved_at_e0[0x720];
1686 };
1687
1688 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1689 u8 reserved_at_0[0x60];
1690
1691 u8 reserved_at_60[0x4];
1692 u8 clamp_tgt_rate[0x1];
1693 u8 reserved_at_65[0x3];
1694 u8 clamp_tgt_rate_after_time_inc[0x1];
1695 u8 reserved_at_69[0x17];
1696
1697 u8 reserved_at_80[0x20];
1698
1699 u8 rpg_time_reset[0x20];
1700
1701 u8 rpg_byte_reset[0x20];
1702
1703 u8 rpg_threshold[0x20];
1704
1705 u8 rpg_max_rate[0x20];
1706
1707 u8 rpg_ai_rate[0x20];
1708
1709 u8 rpg_hai_rate[0x20];
1710
1711 u8 rpg_gd[0x20];
1712
1713 u8 rpg_min_dec_fac[0x20];
1714
1715 u8 rpg_min_rate[0x20];
1716
1717 u8 reserved_at_1c0[0xe0];
1718
1719 u8 rate_to_set_on_first_cnp[0x20];
1720
1721 u8 dce_tcp_g[0x20];
1722
1723 u8 dce_tcp_rtt[0x20];
1724
1725 u8 rate_reduce_monitor_period[0x20];
1726
1727 u8 reserved_at_320[0x20];
1728
1729 u8 initial_alpha_value[0x20];
1730
1731 u8 reserved_at_360[0x4a0];
1732 };
1733
1734 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1735 u8 reserved_at_0[0x80];
1736
1737 u8 rppp_max_rps[0x20];
1738
1739 u8 rpg_time_reset[0x20];
1740
1741 u8 rpg_byte_reset[0x20];
1742
1743 u8 rpg_threshold[0x20];
1744
1745 u8 rpg_max_rate[0x20];
1746
1747 u8 rpg_ai_rate[0x20];
1748
1749 u8 rpg_hai_rate[0x20];
1750
1751 u8 rpg_gd[0x20];
1752
1753 u8 rpg_min_dec_fac[0x20];
1754
1755 u8 rpg_min_rate[0x20];
1756
1757 u8 reserved_at_1c0[0x640];
1758 };
1759
1760 enum {
1761 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1762 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1763 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1764 };
1765
1766 struct mlx5_ifc_resize_field_select_bits {
1767 u8 resize_field_select[0x20];
1768 };
1769
1770 enum {
1771 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1772 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1773 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1774 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1775 };
1776
1777 struct mlx5_ifc_modify_field_select_bits {
1778 u8 modify_field_select[0x20];
1779 };
1780
1781 struct mlx5_ifc_field_select_r_roce_np_bits {
1782 u8 field_select_r_roce_np[0x20];
1783 };
1784
1785 struct mlx5_ifc_field_select_r_roce_rp_bits {
1786 u8 field_select_r_roce_rp[0x20];
1787 };
1788
1789 enum {
1790 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1791 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1792 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1793 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1794 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1795 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1796 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1797 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1798 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1799 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1800 };
1801
1802 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1803 u8 field_select_8021qaurp[0x20];
1804 };
1805
1806 struct mlx5_ifc_phys_layer_cntrs_bits {
1807 u8 time_since_last_clear_high[0x20];
1808
1809 u8 time_since_last_clear_low[0x20];
1810
1811 u8 symbol_errors_high[0x20];
1812
1813 u8 symbol_errors_low[0x20];
1814
1815 u8 sync_headers_errors_high[0x20];
1816
1817 u8 sync_headers_errors_low[0x20];
1818
1819 u8 edpl_bip_errors_lane0_high[0x20];
1820
1821 u8 edpl_bip_errors_lane0_low[0x20];
1822
1823 u8 edpl_bip_errors_lane1_high[0x20];
1824
1825 u8 edpl_bip_errors_lane1_low[0x20];
1826
1827 u8 edpl_bip_errors_lane2_high[0x20];
1828
1829 u8 edpl_bip_errors_lane2_low[0x20];
1830
1831 u8 edpl_bip_errors_lane3_high[0x20];
1832
1833 u8 edpl_bip_errors_lane3_low[0x20];
1834
1835 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1836
1837 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1838
1839 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1840
1841 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1842
1843 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1844
1845 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1846
1847 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1848
1849 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1850
1851 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1852
1853 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1854
1855 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1856
1857 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1858
1859 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1860
1861 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1862
1863 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1864
1865 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1866
1867 u8 rs_fec_corrected_blocks_high[0x20];
1868
1869 u8 rs_fec_corrected_blocks_low[0x20];
1870
1871 u8 rs_fec_uncorrectable_blocks_high[0x20];
1872
1873 u8 rs_fec_uncorrectable_blocks_low[0x20];
1874
1875 u8 rs_fec_no_errors_blocks_high[0x20];
1876
1877 u8 rs_fec_no_errors_blocks_low[0x20];
1878
1879 u8 rs_fec_single_error_blocks_high[0x20];
1880
1881 u8 rs_fec_single_error_blocks_low[0x20];
1882
1883 u8 rs_fec_corrected_symbols_total_high[0x20];
1884
1885 u8 rs_fec_corrected_symbols_total_low[0x20];
1886
1887 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1888
1889 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1890
1891 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1892
1893 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1894
1895 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1896
1897 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1898
1899 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1900
1901 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1902
1903 u8 link_down_events[0x20];
1904
1905 u8 successful_recovery_events[0x20];
1906
1907 u8 reserved_at_640[0x180];
1908 };
1909
1910 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1911 u8 time_since_last_clear_high[0x20];
1912
1913 u8 time_since_last_clear_low[0x20];
1914
1915 u8 phy_received_bits_high[0x20];
1916
1917 u8 phy_received_bits_low[0x20];
1918
1919 u8 phy_symbol_errors_high[0x20];
1920
1921 u8 phy_symbol_errors_low[0x20];
1922
1923 u8 phy_corrected_bits_high[0x20];
1924
1925 u8 phy_corrected_bits_low[0x20];
1926
1927 u8 phy_corrected_bits_lane0_high[0x20];
1928
1929 u8 phy_corrected_bits_lane0_low[0x20];
1930
1931 u8 phy_corrected_bits_lane1_high[0x20];
1932
1933 u8 phy_corrected_bits_lane1_low[0x20];
1934
1935 u8 phy_corrected_bits_lane2_high[0x20];
1936
1937 u8 phy_corrected_bits_lane2_low[0x20];
1938
1939 u8 phy_corrected_bits_lane3_high[0x20];
1940
1941 u8 phy_corrected_bits_lane3_low[0x20];
1942
1943 u8 reserved_at_200[0x5c0];
1944 };
1945
1946 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1947 u8 symbol_error_counter[0x10];
1948
1949 u8 link_error_recovery_counter[0x8];
1950
1951 u8 link_downed_counter[0x8];
1952
1953 u8 port_rcv_errors[0x10];
1954
1955 u8 port_rcv_remote_physical_errors[0x10];
1956
1957 u8 port_rcv_switch_relay_errors[0x10];
1958
1959 u8 port_xmit_discards[0x10];
1960
1961 u8 port_xmit_constraint_errors[0x8];
1962
1963 u8 port_rcv_constraint_errors[0x8];
1964
1965 u8 reserved_at_70[0x8];
1966
1967 u8 link_overrun_errors[0x8];
1968
1969 u8 reserved_at_80[0x10];
1970
1971 u8 vl_15_dropped[0x10];
1972
1973 u8 reserved_at_a0[0x80];
1974
1975 u8 port_xmit_wait[0x20];
1976 };
1977
1978 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
1979 u8 transmit_queue_high[0x20];
1980
1981 u8 transmit_queue_low[0x20];
1982
1983 u8 no_buffer_discard_uc_high[0x20];
1984
1985 u8 no_buffer_discard_uc_low[0x20];
1986
1987 u8 reserved_at_80[0x740];
1988 };
1989
1990 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
1991 u8 wred_discard_high[0x20];
1992
1993 u8 wred_discard_low[0x20];
1994
1995 u8 ecn_marked_tc_high[0x20];
1996
1997 u8 ecn_marked_tc_low[0x20];
1998
1999 u8 reserved_at_80[0x740];
2000 };
2001
2002 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2003 u8 rx_octets_high[0x20];
2004
2005 u8 rx_octets_low[0x20];
2006
2007 u8 reserved_at_40[0xc0];
2008
2009 u8 rx_frames_high[0x20];
2010
2011 u8 rx_frames_low[0x20];
2012
2013 u8 tx_octets_high[0x20];
2014
2015 u8 tx_octets_low[0x20];
2016
2017 u8 reserved_at_180[0xc0];
2018
2019 u8 tx_frames_high[0x20];
2020
2021 u8 tx_frames_low[0x20];
2022
2023 u8 rx_pause_high[0x20];
2024
2025 u8 rx_pause_low[0x20];
2026
2027 u8 rx_pause_duration_high[0x20];
2028
2029 u8 rx_pause_duration_low[0x20];
2030
2031 u8 tx_pause_high[0x20];
2032
2033 u8 tx_pause_low[0x20];
2034
2035 u8 tx_pause_duration_high[0x20];
2036
2037 u8 tx_pause_duration_low[0x20];
2038
2039 u8 rx_pause_transition_high[0x20];
2040
2041 u8 rx_pause_transition_low[0x20];
2042
2043 u8 reserved_at_3c0[0x40];
2044
2045 u8 device_stall_minor_watermark_cnt_high[0x20];
2046
2047 u8 device_stall_minor_watermark_cnt_low[0x20];
2048
2049 u8 device_stall_critical_watermark_cnt_high[0x20];
2050
2051 u8 device_stall_critical_watermark_cnt_low[0x20];
2052
2053 u8 reserved_at_480[0x340];
2054 };
2055
2056 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2057 u8 port_transmit_wait_high[0x20];
2058
2059 u8 port_transmit_wait_low[0x20];
2060
2061 u8 reserved_at_40[0x100];
2062
2063 u8 rx_buffer_almost_full_high[0x20];
2064
2065 u8 rx_buffer_almost_full_low[0x20];
2066
2067 u8 rx_buffer_full_high[0x20];
2068
2069 u8 rx_buffer_full_low[0x20];
2070
2071 u8 rx_icrc_encapsulated_high[0x20];
2072
2073 u8 rx_icrc_encapsulated_low[0x20];
2074
2075 u8 reserved_at_200[0x5c0];
2076 };
2077
2078 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2079 u8 dot3stats_alignment_errors_high[0x20];
2080
2081 u8 dot3stats_alignment_errors_low[0x20];
2082
2083 u8 dot3stats_fcs_errors_high[0x20];
2084
2085 u8 dot3stats_fcs_errors_low[0x20];
2086
2087 u8 dot3stats_single_collision_frames_high[0x20];
2088
2089 u8 dot3stats_single_collision_frames_low[0x20];
2090
2091 u8 dot3stats_multiple_collision_frames_high[0x20];
2092
2093 u8 dot3stats_multiple_collision_frames_low[0x20];
2094
2095 u8 dot3stats_sqe_test_errors_high[0x20];
2096
2097 u8 dot3stats_sqe_test_errors_low[0x20];
2098
2099 u8 dot3stats_deferred_transmissions_high[0x20];
2100
2101 u8 dot3stats_deferred_transmissions_low[0x20];
2102
2103 u8 dot3stats_late_collisions_high[0x20];
2104
2105 u8 dot3stats_late_collisions_low[0x20];
2106
2107 u8 dot3stats_excessive_collisions_high[0x20];
2108
2109 u8 dot3stats_excessive_collisions_low[0x20];
2110
2111 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2112
2113 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2114
2115 u8 dot3stats_carrier_sense_errors_high[0x20];
2116
2117 u8 dot3stats_carrier_sense_errors_low[0x20];
2118
2119 u8 dot3stats_frame_too_longs_high[0x20];
2120
2121 u8 dot3stats_frame_too_longs_low[0x20];
2122
2123 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2124
2125 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2126
2127 u8 dot3stats_symbol_errors_high[0x20];
2128
2129 u8 dot3stats_symbol_errors_low[0x20];
2130
2131 u8 dot3control_in_unknown_opcodes_high[0x20];
2132
2133 u8 dot3control_in_unknown_opcodes_low[0x20];
2134
2135 u8 dot3in_pause_frames_high[0x20];
2136
2137 u8 dot3in_pause_frames_low[0x20];
2138
2139 u8 dot3out_pause_frames_high[0x20];
2140
2141 u8 dot3out_pause_frames_low[0x20];
2142
2143 u8 reserved_at_400[0x3c0];
2144 };
2145
2146 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2147 u8 ether_stats_drop_events_high[0x20];
2148
2149 u8 ether_stats_drop_events_low[0x20];
2150
2151 u8 ether_stats_octets_high[0x20];
2152
2153 u8 ether_stats_octets_low[0x20];
2154
2155 u8 ether_stats_pkts_high[0x20];
2156
2157 u8 ether_stats_pkts_low[0x20];
2158
2159 u8 ether_stats_broadcast_pkts_high[0x20];
2160
2161 u8 ether_stats_broadcast_pkts_low[0x20];
2162
2163 u8 ether_stats_multicast_pkts_high[0x20];
2164
2165 u8 ether_stats_multicast_pkts_low[0x20];
2166
2167 u8 ether_stats_crc_align_errors_high[0x20];
2168
2169 u8 ether_stats_crc_align_errors_low[0x20];
2170
2171 u8 ether_stats_undersize_pkts_high[0x20];
2172
2173 u8 ether_stats_undersize_pkts_low[0x20];
2174
2175 u8 ether_stats_oversize_pkts_high[0x20];
2176
2177 u8 ether_stats_oversize_pkts_low[0x20];
2178
2179 u8 ether_stats_fragments_high[0x20];
2180
2181 u8 ether_stats_fragments_low[0x20];
2182
2183 u8 ether_stats_jabbers_high[0x20];
2184
2185 u8 ether_stats_jabbers_low[0x20];
2186
2187 u8 ether_stats_collisions_high[0x20];
2188
2189 u8 ether_stats_collisions_low[0x20];
2190
2191 u8 ether_stats_pkts64octets_high[0x20];
2192
2193 u8 ether_stats_pkts64octets_low[0x20];
2194
2195 u8 ether_stats_pkts65to127octets_high[0x20];
2196
2197 u8 ether_stats_pkts65to127octets_low[0x20];
2198
2199 u8 ether_stats_pkts128to255octets_high[0x20];
2200
2201 u8 ether_stats_pkts128to255octets_low[0x20];
2202
2203 u8 ether_stats_pkts256to511octets_high[0x20];
2204
2205 u8 ether_stats_pkts256to511octets_low[0x20];
2206
2207 u8 ether_stats_pkts512to1023octets_high[0x20];
2208
2209 u8 ether_stats_pkts512to1023octets_low[0x20];
2210
2211 u8 ether_stats_pkts1024to1518octets_high[0x20];
2212
2213 u8 ether_stats_pkts1024to1518octets_low[0x20];
2214
2215 u8 ether_stats_pkts1519to2047octets_high[0x20];
2216
2217 u8 ether_stats_pkts1519to2047octets_low[0x20];
2218
2219 u8 ether_stats_pkts2048to4095octets_high[0x20];
2220
2221 u8 ether_stats_pkts2048to4095octets_low[0x20];
2222
2223 u8 ether_stats_pkts4096to8191octets_high[0x20];
2224
2225 u8 ether_stats_pkts4096to8191octets_low[0x20];
2226
2227 u8 ether_stats_pkts8192to10239octets_high[0x20];
2228
2229 u8 ether_stats_pkts8192to10239octets_low[0x20];
2230
2231 u8 reserved_at_540[0x280];
2232 };
2233
2234 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2235 u8 if_in_octets_high[0x20];
2236
2237 u8 if_in_octets_low[0x20];
2238
2239 u8 if_in_ucast_pkts_high[0x20];
2240
2241 u8 if_in_ucast_pkts_low[0x20];
2242
2243 u8 if_in_discards_high[0x20];
2244
2245 u8 if_in_discards_low[0x20];
2246
2247 u8 if_in_errors_high[0x20];
2248
2249 u8 if_in_errors_low[0x20];
2250
2251 u8 if_in_unknown_protos_high[0x20];
2252
2253 u8 if_in_unknown_protos_low[0x20];
2254
2255 u8 if_out_octets_high[0x20];
2256
2257 u8 if_out_octets_low[0x20];
2258
2259 u8 if_out_ucast_pkts_high[0x20];
2260
2261 u8 if_out_ucast_pkts_low[0x20];
2262
2263 u8 if_out_discards_high[0x20];
2264
2265 u8 if_out_discards_low[0x20];
2266
2267 u8 if_out_errors_high[0x20];
2268
2269 u8 if_out_errors_low[0x20];
2270
2271 u8 if_in_multicast_pkts_high[0x20];
2272
2273 u8 if_in_multicast_pkts_low[0x20];
2274
2275 u8 if_in_broadcast_pkts_high[0x20];
2276
2277 u8 if_in_broadcast_pkts_low[0x20];
2278
2279 u8 if_out_multicast_pkts_high[0x20];
2280
2281 u8 if_out_multicast_pkts_low[0x20];
2282
2283 u8 if_out_broadcast_pkts_high[0x20];
2284
2285 u8 if_out_broadcast_pkts_low[0x20];
2286
2287 u8 reserved_at_340[0x480];
2288 };
2289
2290 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2291 u8 a_frames_transmitted_ok_high[0x20];
2292
2293 u8 a_frames_transmitted_ok_low[0x20];
2294
2295 u8 a_frames_received_ok_high[0x20];
2296
2297 u8 a_frames_received_ok_low[0x20];
2298
2299 u8 a_frame_check_sequence_errors_high[0x20];
2300
2301 u8 a_frame_check_sequence_errors_low[0x20];
2302
2303 u8 a_alignment_errors_high[0x20];
2304
2305 u8 a_alignment_errors_low[0x20];
2306
2307 u8 a_octets_transmitted_ok_high[0x20];
2308
2309 u8 a_octets_transmitted_ok_low[0x20];
2310
2311 u8 a_octets_received_ok_high[0x20];
2312
2313 u8 a_octets_received_ok_low[0x20];
2314
2315 u8 a_multicast_frames_xmitted_ok_high[0x20];
2316
2317 u8 a_multicast_frames_xmitted_ok_low[0x20];
2318
2319 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2320
2321 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2322
2323 u8 a_multicast_frames_received_ok_high[0x20];
2324
2325 u8 a_multicast_frames_received_ok_low[0x20];
2326
2327 u8 a_broadcast_frames_received_ok_high[0x20];
2328
2329 u8 a_broadcast_frames_received_ok_low[0x20];
2330
2331 u8 a_in_range_length_errors_high[0x20];
2332
2333 u8 a_in_range_length_errors_low[0x20];
2334
2335 u8 a_out_of_range_length_field_high[0x20];
2336
2337 u8 a_out_of_range_length_field_low[0x20];
2338
2339 u8 a_frame_too_long_errors_high[0x20];
2340
2341 u8 a_frame_too_long_errors_low[0x20];
2342
2343 u8 a_symbol_error_during_carrier_high[0x20];
2344
2345 u8 a_symbol_error_during_carrier_low[0x20];
2346
2347 u8 a_mac_control_frames_transmitted_high[0x20];
2348
2349 u8 a_mac_control_frames_transmitted_low[0x20];
2350
2351 u8 a_mac_control_frames_received_high[0x20];
2352
2353 u8 a_mac_control_frames_received_low[0x20];
2354
2355 u8 a_unsupported_opcodes_received_high[0x20];
2356
2357 u8 a_unsupported_opcodes_received_low[0x20];
2358
2359 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2360
2361 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2362
2363 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2364
2365 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2366
2367 u8 reserved_at_4c0[0x300];
2368 };
2369
2370 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2371 u8 life_time_counter_high[0x20];
2372
2373 u8 life_time_counter_low[0x20];
2374
2375 u8 rx_errors[0x20];
2376
2377 u8 tx_errors[0x20];
2378
2379 u8 l0_to_recovery_eieos[0x20];
2380
2381 u8 l0_to_recovery_ts[0x20];
2382
2383 u8 l0_to_recovery_framing[0x20];
2384
2385 u8 l0_to_recovery_retrain[0x20];
2386
2387 u8 crc_error_dllp[0x20];
2388
2389 u8 crc_error_tlp[0x20];
2390
2391 u8 tx_overflow_buffer_pkt_high[0x20];
2392
2393 u8 tx_overflow_buffer_pkt_low[0x20];
2394
2395 u8 outbound_stalled_reads[0x20];
2396
2397 u8 outbound_stalled_writes[0x20];
2398
2399 u8 outbound_stalled_reads_events[0x20];
2400
2401 u8 outbound_stalled_writes_events[0x20];
2402
2403 u8 reserved_at_200[0x5c0];
2404 };
2405
2406 struct mlx5_ifc_cmd_inter_comp_event_bits {
2407 u8 command_completion_vector[0x20];
2408
2409 u8 reserved_at_20[0xc0];
2410 };
2411
2412 struct mlx5_ifc_stall_vl_event_bits {
2413 u8 reserved_at_0[0x18];
2414 u8 port_num[0x1];
2415 u8 reserved_at_19[0x3];
2416 u8 vl[0x4];
2417
2418 u8 reserved_at_20[0xa0];
2419 };
2420
2421 struct mlx5_ifc_db_bf_congestion_event_bits {
2422 u8 event_subtype[0x8];
2423 u8 reserved_at_8[0x8];
2424 u8 congestion_level[0x8];
2425 u8 reserved_at_18[0x8];
2426
2427 u8 reserved_at_20[0xa0];
2428 };
2429
2430 struct mlx5_ifc_gpio_event_bits {
2431 u8 reserved_at_0[0x60];
2432
2433 u8 gpio_event_hi[0x20];
2434
2435 u8 gpio_event_lo[0x20];
2436
2437 u8 reserved_at_a0[0x40];
2438 };
2439
2440 struct mlx5_ifc_port_state_change_event_bits {
2441 u8 reserved_at_0[0x40];
2442
2443 u8 port_num[0x4];
2444 u8 reserved_at_44[0x1c];
2445
2446 u8 reserved_at_60[0x80];
2447 };
2448
2449 struct mlx5_ifc_dropped_packet_logged_bits {
2450 u8 reserved_at_0[0xe0];
2451 };
2452
2453 enum {
2454 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2455 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2456 };
2457
2458 struct mlx5_ifc_cq_error_bits {
2459 u8 reserved_at_0[0x8];
2460 u8 cqn[0x18];
2461
2462 u8 reserved_at_20[0x20];
2463
2464 u8 reserved_at_40[0x18];
2465 u8 syndrome[0x8];
2466
2467 u8 reserved_at_60[0x80];
2468 };
2469
2470 struct mlx5_ifc_rdma_page_fault_event_bits {
2471 u8 bytes_committed[0x20];
2472
2473 u8 r_key[0x20];
2474
2475 u8 reserved_at_40[0x10];
2476 u8 packet_len[0x10];
2477
2478 u8 rdma_op_len[0x20];
2479
2480 u8 rdma_va[0x40];
2481
2482 u8 reserved_at_c0[0x5];
2483 u8 rdma[0x1];
2484 u8 write[0x1];
2485 u8 requestor[0x1];
2486 u8 qp_number[0x18];
2487 };
2488
2489 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2490 u8 bytes_committed[0x20];
2491
2492 u8 reserved_at_20[0x10];
2493 u8 wqe_index[0x10];
2494
2495 u8 reserved_at_40[0x10];
2496 u8 len[0x10];
2497
2498 u8 reserved_at_60[0x60];
2499
2500 u8 reserved_at_c0[0x5];
2501 u8 rdma[0x1];
2502 u8 write_read[0x1];
2503 u8 requestor[0x1];
2504 u8 qpn[0x18];
2505 };
2506
2507 struct mlx5_ifc_qp_events_bits {
2508 u8 reserved_at_0[0xa0];
2509
2510 u8 type[0x8];
2511 u8 reserved_at_a8[0x18];
2512
2513 u8 reserved_at_c0[0x8];
2514 u8 qpn_rqn_sqn[0x18];
2515 };
2516
2517 struct mlx5_ifc_dct_events_bits {
2518 u8 reserved_at_0[0xc0];
2519
2520 u8 reserved_at_c0[0x8];
2521 u8 dct_number[0x18];
2522 };
2523
2524 struct mlx5_ifc_comp_event_bits {
2525 u8 reserved_at_0[0xc0];
2526
2527 u8 reserved_at_c0[0x8];
2528 u8 cq_number[0x18];
2529 };
2530
2531 enum {
2532 MLX5_QPC_STATE_RST = 0x0,
2533 MLX5_QPC_STATE_INIT = 0x1,
2534 MLX5_QPC_STATE_RTR = 0x2,
2535 MLX5_QPC_STATE_RTS = 0x3,
2536 MLX5_QPC_STATE_SQER = 0x4,
2537 MLX5_QPC_STATE_ERR = 0x6,
2538 MLX5_QPC_STATE_SQD = 0x7,
2539 MLX5_QPC_STATE_SUSPENDED = 0x9,
2540 };
2541
2542 enum {
2543 MLX5_QPC_ST_RC = 0x0,
2544 MLX5_QPC_ST_UC = 0x1,
2545 MLX5_QPC_ST_UD = 0x2,
2546 MLX5_QPC_ST_XRC = 0x3,
2547 MLX5_QPC_ST_DCI = 0x5,
2548 MLX5_QPC_ST_QP0 = 0x7,
2549 MLX5_QPC_ST_QP1 = 0x8,
2550 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2551 MLX5_QPC_ST_REG_UMR = 0xc,
2552 };
2553
2554 enum {
2555 MLX5_QPC_PM_STATE_ARMED = 0x0,
2556 MLX5_QPC_PM_STATE_REARM = 0x1,
2557 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2558 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2559 };
2560
2561 enum {
2562 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2563 };
2564
2565 enum {
2566 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2567 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2568 };
2569
2570 enum {
2571 MLX5_QPC_MTU_256_BYTES = 0x1,
2572 MLX5_QPC_MTU_512_BYTES = 0x2,
2573 MLX5_QPC_MTU_1K_BYTES = 0x3,
2574 MLX5_QPC_MTU_2K_BYTES = 0x4,
2575 MLX5_QPC_MTU_4K_BYTES = 0x5,
2576 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2577 };
2578
2579 enum {
2580 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2581 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2582 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2583 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2584 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2585 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2586 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2587 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2588 };
2589
2590 enum {
2591 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2592 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2593 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2594 };
2595
2596 enum {
2597 MLX5_QPC_CS_RES_DISABLE = 0x0,
2598 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2599 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2600 };
2601
2602 struct mlx5_ifc_qpc_bits {
2603 u8 state[0x4];
2604 u8 lag_tx_port_affinity[0x4];
2605 u8 st[0x8];
2606 u8 reserved_at_10[0x3];
2607 u8 pm_state[0x2];
2608 u8 reserved_at_15[0x1];
2609 u8 req_e2e_credit_mode[0x2];
2610 u8 offload_type[0x4];
2611 u8 end_padding_mode[0x2];
2612 u8 reserved_at_1e[0x2];
2613
2614 u8 wq_signature[0x1];
2615 u8 block_lb_mc[0x1];
2616 u8 atomic_like_write_en[0x1];
2617 u8 latency_sensitive[0x1];
2618 u8 reserved_at_24[0x1];
2619 u8 drain_sigerr[0x1];
2620 u8 reserved_at_26[0x2];
2621 u8 pd[0x18];
2622
2623 u8 mtu[0x3];
2624 u8 log_msg_max[0x5];
2625 u8 reserved_at_48[0x1];
2626 u8 log_rq_size[0x4];
2627 u8 log_rq_stride[0x3];
2628 u8 no_sq[0x1];
2629 u8 log_sq_size[0x4];
2630 u8 reserved_at_55[0x6];
2631 u8 rlky[0x1];
2632 u8 ulp_stateless_offload_mode[0x4];
2633
2634 u8 counter_set_id[0x8];
2635 u8 uar_page[0x18];
2636
2637 u8 reserved_at_80[0x8];
2638 u8 user_index[0x18];
2639
2640 u8 reserved_at_a0[0x3];
2641 u8 log_page_size[0x5];
2642 u8 remote_qpn[0x18];
2643
2644 struct mlx5_ifc_ads_bits primary_address_path;
2645
2646 struct mlx5_ifc_ads_bits secondary_address_path;
2647
2648 u8 log_ack_req_freq[0x4];
2649 u8 reserved_at_384[0x4];
2650 u8 log_sra_max[0x3];
2651 u8 reserved_at_38b[0x2];
2652 u8 retry_count[0x3];
2653 u8 rnr_retry[0x3];
2654 u8 reserved_at_393[0x1];
2655 u8 fre[0x1];
2656 u8 cur_rnr_retry[0x3];
2657 u8 cur_retry_count[0x3];
2658 u8 reserved_at_39b[0x5];
2659
2660 u8 reserved_at_3a0[0x20];
2661
2662 u8 reserved_at_3c0[0x8];
2663 u8 next_send_psn[0x18];
2664
2665 u8 reserved_at_3e0[0x8];
2666 u8 cqn_snd[0x18];
2667
2668 u8 reserved_at_400[0x8];
2669 u8 deth_sqpn[0x18];
2670
2671 u8 reserved_at_420[0x20];
2672
2673 u8 reserved_at_440[0x8];
2674 u8 last_acked_psn[0x18];
2675
2676 u8 reserved_at_460[0x8];
2677 u8 ssn[0x18];
2678
2679 u8 reserved_at_480[0x8];
2680 u8 log_rra_max[0x3];
2681 u8 reserved_at_48b[0x1];
2682 u8 atomic_mode[0x4];
2683 u8 rre[0x1];
2684 u8 rwe[0x1];
2685 u8 rae[0x1];
2686 u8 reserved_at_493[0x1];
2687 u8 page_offset[0x6];
2688 u8 reserved_at_49a[0x3];
2689 u8 cd_slave_receive[0x1];
2690 u8 cd_slave_send[0x1];
2691 u8 cd_master[0x1];
2692
2693 u8 reserved_at_4a0[0x3];
2694 u8 min_rnr_nak[0x5];
2695 u8 next_rcv_psn[0x18];
2696
2697 u8 reserved_at_4c0[0x8];
2698 u8 xrcd[0x18];
2699
2700 u8 reserved_at_4e0[0x8];
2701 u8 cqn_rcv[0x18];
2702
2703 u8 dbr_addr[0x40];
2704
2705 u8 q_key[0x20];
2706
2707 u8 reserved_at_560[0x5];
2708 u8 rq_type[0x3];
2709 u8 srqn_rmpn_xrqn[0x18];
2710
2711 u8 reserved_at_580[0x8];
2712 u8 rmsn[0x18];
2713
2714 u8 hw_sq_wqebb_counter[0x10];
2715 u8 sw_sq_wqebb_counter[0x10];
2716
2717 u8 hw_rq_counter[0x20];
2718
2719 u8 sw_rq_counter[0x20];
2720
2721 u8 reserved_at_600[0x20];
2722
2723 u8 reserved_at_620[0xf];
2724 u8 cgs[0x1];
2725 u8 cs_req[0x8];
2726 u8 cs_res[0x8];
2727
2728 u8 dc_access_key[0x40];
2729
2730 u8 reserved_at_680[0x3];
2731 u8 dbr_umem_valid[0x1];
2732
2733 u8 reserved_at_684[0xbc];
2734 };
2735
2736 struct mlx5_ifc_roce_addr_layout_bits {
2737 u8 source_l3_address[16][0x8];
2738
2739 u8 reserved_at_80[0x3];
2740 u8 vlan_valid[0x1];
2741 u8 vlan_id[0xc];
2742 u8 source_mac_47_32[0x10];
2743
2744 u8 source_mac_31_0[0x20];
2745
2746 u8 reserved_at_c0[0x14];
2747 u8 roce_l3_type[0x4];
2748 u8 roce_version[0x8];
2749
2750 u8 reserved_at_e0[0x20];
2751 };
2752
2753 union mlx5_ifc_hca_cap_union_bits {
2754 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2755 struct mlx5_ifc_odp_cap_bits odp_cap;
2756 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2757 struct mlx5_ifc_roce_cap_bits roce_cap;
2758 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2759 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2760 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2761 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2762 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2763 struct mlx5_ifc_qos_cap_bits qos_cap;
2764 struct mlx5_ifc_debug_cap_bits debug_cap;
2765 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2766 struct mlx5_ifc_tls_cap_bits tls_cap;
2767 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2768 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
2769 u8 reserved_at_0[0x8000];
2770 };
2771
2772 enum {
2773 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2774 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2775 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2776 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2777 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2778 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2779 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2780 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2781 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2782 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2783 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2784 };
2785
2786 enum {
2787 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
2788 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
2789 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
2790 };
2791
2792 struct mlx5_ifc_vlan_bits {
2793 u8 ethtype[0x10];
2794 u8 prio[0x3];
2795 u8 cfi[0x1];
2796 u8 vid[0xc];
2797 };
2798
2799 struct mlx5_ifc_flow_context_bits {
2800 struct mlx5_ifc_vlan_bits push_vlan;
2801
2802 u8 group_id[0x20];
2803
2804 u8 reserved_at_40[0x8];
2805 u8 flow_tag[0x18];
2806
2807 u8 reserved_at_60[0x10];
2808 u8 action[0x10];
2809
2810 u8 extended_destination[0x1];
2811 u8 reserved_at_81[0x1];
2812 u8 flow_source[0x2];
2813 u8 reserved_at_84[0x4];
2814 u8 destination_list_size[0x18];
2815
2816 u8 reserved_at_a0[0x8];
2817 u8 flow_counter_list_size[0x18];
2818
2819 u8 packet_reformat_id[0x20];
2820
2821 u8 modify_header_id[0x20];
2822
2823 struct mlx5_ifc_vlan_bits push_vlan_2;
2824
2825 u8 reserved_at_120[0xe0];
2826
2827 struct mlx5_ifc_fte_match_param_bits match_value;
2828
2829 u8 reserved_at_1200[0x600];
2830
2831 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2832 };
2833
2834 enum {
2835 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2836 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2837 };
2838
2839 struct mlx5_ifc_xrc_srqc_bits {
2840 u8 state[0x4];
2841 u8 log_xrc_srq_size[0x4];
2842 u8 reserved_at_8[0x18];
2843
2844 u8 wq_signature[0x1];
2845 u8 cont_srq[0x1];
2846 u8 reserved_at_22[0x1];
2847 u8 rlky[0x1];
2848 u8 basic_cyclic_rcv_wqe[0x1];
2849 u8 log_rq_stride[0x3];
2850 u8 xrcd[0x18];
2851
2852 u8 page_offset[0x6];
2853 u8 reserved_at_46[0x1];
2854 u8 dbr_umem_valid[0x1];
2855 u8 cqn[0x18];
2856
2857 u8 reserved_at_60[0x20];
2858
2859 u8 user_index_equal_xrc_srqn[0x1];
2860 u8 reserved_at_81[0x1];
2861 u8 log_page_size[0x6];
2862 u8 user_index[0x18];
2863
2864 u8 reserved_at_a0[0x20];
2865
2866 u8 reserved_at_c0[0x8];
2867 u8 pd[0x18];
2868
2869 u8 lwm[0x10];
2870 u8 wqe_cnt[0x10];
2871
2872 u8 reserved_at_100[0x40];
2873
2874 u8 db_record_addr_h[0x20];
2875
2876 u8 db_record_addr_l[0x1e];
2877 u8 reserved_at_17e[0x2];
2878
2879 u8 reserved_at_180[0x80];
2880 };
2881
2882 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2883 u8 counter_error_queues[0x20];
2884
2885 u8 total_error_queues[0x20];
2886
2887 u8 send_queue_priority_update_flow[0x20];
2888
2889 u8 reserved_at_60[0x20];
2890
2891 u8 nic_receive_steering_discard[0x40];
2892
2893 u8 receive_discard_vport_down[0x40];
2894
2895 u8 transmit_discard_vport_down[0x40];
2896
2897 u8 reserved_at_140[0xa0];
2898
2899 u8 internal_rq_out_of_buffer[0x20];
2900
2901 u8 reserved_at_200[0xe00];
2902 };
2903
2904 struct mlx5_ifc_traffic_counter_bits {
2905 u8 packets[0x40];
2906
2907 u8 octets[0x40];
2908 };
2909
2910 struct mlx5_ifc_tisc_bits {
2911 u8 strict_lag_tx_port_affinity[0x1];
2912 u8 tls_en[0x1];
2913 u8 reserved_at_2[0x2];
2914 u8 lag_tx_port_affinity[0x04];
2915
2916 u8 reserved_at_8[0x4];
2917 u8 prio[0x4];
2918 u8 reserved_at_10[0x10];
2919
2920 u8 reserved_at_20[0x100];
2921
2922 u8 reserved_at_120[0x8];
2923 u8 transport_domain[0x18];
2924
2925 u8 reserved_at_140[0x8];
2926 u8 underlay_qpn[0x18];
2927
2928 u8 reserved_at_160[0x8];
2929 u8 pd[0x18];
2930
2931 u8 reserved_at_180[0x380];
2932 };
2933
2934 enum {
2935 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2936 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2937 };
2938
2939 enum {
2940 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2941 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2942 };
2943
2944 enum {
2945 MLX5_RX_HASH_FN_NONE = 0x0,
2946 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2947 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2948 };
2949
2950 enum {
2951 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2952 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2953 };
2954
2955 struct mlx5_ifc_tirc_bits {
2956 u8 reserved_at_0[0x20];
2957
2958 u8 disp_type[0x4];
2959 u8 reserved_at_24[0x1c];
2960
2961 u8 reserved_at_40[0x40];
2962
2963 u8 reserved_at_80[0x4];
2964 u8 lro_timeout_period_usecs[0x10];
2965 u8 lro_enable_mask[0x4];
2966 u8 lro_max_ip_payload_size[0x8];
2967
2968 u8 reserved_at_a0[0x40];
2969
2970 u8 reserved_at_e0[0x8];
2971 u8 inline_rqn[0x18];
2972
2973 u8 rx_hash_symmetric[0x1];
2974 u8 reserved_at_101[0x1];
2975 u8 tunneled_offload_en[0x1];
2976 u8 reserved_at_103[0x5];
2977 u8 indirect_table[0x18];
2978
2979 u8 rx_hash_fn[0x4];
2980 u8 reserved_at_124[0x2];
2981 u8 self_lb_block[0x2];
2982 u8 transport_domain[0x18];
2983
2984 u8 rx_hash_toeplitz_key[10][0x20];
2985
2986 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2987
2988 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2989
2990 u8 reserved_at_2c0[0x4c0];
2991 };
2992
2993 enum {
2994 MLX5_SRQC_STATE_GOOD = 0x0,
2995 MLX5_SRQC_STATE_ERROR = 0x1,
2996 };
2997
2998 struct mlx5_ifc_srqc_bits {
2999 u8 state[0x4];
3000 u8 log_srq_size[0x4];
3001 u8 reserved_at_8[0x18];
3002
3003 u8 wq_signature[0x1];
3004 u8 cont_srq[0x1];
3005 u8 reserved_at_22[0x1];
3006 u8 rlky[0x1];
3007 u8 reserved_at_24[0x1];
3008 u8 log_rq_stride[0x3];
3009 u8 xrcd[0x18];
3010
3011 u8 page_offset[0x6];
3012 u8 reserved_at_46[0x2];
3013 u8 cqn[0x18];
3014
3015 u8 reserved_at_60[0x20];
3016
3017 u8 reserved_at_80[0x2];
3018 u8 log_page_size[0x6];
3019 u8 reserved_at_88[0x18];
3020
3021 u8 reserved_at_a0[0x20];
3022
3023 u8 reserved_at_c0[0x8];
3024 u8 pd[0x18];
3025
3026 u8 lwm[0x10];
3027 u8 wqe_cnt[0x10];
3028
3029 u8 reserved_at_100[0x40];
3030
3031 u8 dbr_addr[0x40];
3032
3033 u8 reserved_at_180[0x80];
3034 };
3035
3036 enum {
3037 MLX5_SQC_STATE_RST = 0x0,
3038 MLX5_SQC_STATE_RDY = 0x1,
3039 MLX5_SQC_STATE_ERR = 0x3,
3040 };
3041
3042 struct mlx5_ifc_sqc_bits {
3043 u8 rlky[0x1];
3044 u8 cd_master[0x1];
3045 u8 fre[0x1];
3046 u8 flush_in_error_en[0x1];
3047 u8 allow_multi_pkt_send_wqe[0x1];
3048 u8 min_wqe_inline_mode[0x3];
3049 u8 state[0x4];
3050 u8 reg_umr[0x1];
3051 u8 allow_swp[0x1];
3052 u8 hairpin[0x1];
3053 u8 reserved_at_f[0x11];
3054
3055 u8 reserved_at_20[0x8];
3056 u8 user_index[0x18];
3057
3058 u8 reserved_at_40[0x8];
3059 u8 cqn[0x18];
3060
3061 u8 reserved_at_60[0x8];
3062 u8 hairpin_peer_rq[0x18];
3063
3064 u8 reserved_at_80[0x10];
3065 u8 hairpin_peer_vhca[0x10];
3066
3067 u8 reserved_at_a0[0x50];
3068
3069 u8 packet_pacing_rate_limit_index[0x10];
3070 u8 tis_lst_sz[0x10];
3071 u8 reserved_at_110[0x10];
3072
3073 u8 reserved_at_120[0x40];
3074
3075 u8 reserved_at_160[0x8];
3076 u8 tis_num_0[0x18];
3077
3078 struct mlx5_ifc_wq_bits wq;
3079 };
3080
3081 enum {
3082 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3083 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3084 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3085 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3086 };
3087
3088 enum {
3089 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3090 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3091 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3092 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3093 };
3094
3095 struct mlx5_ifc_scheduling_context_bits {
3096 u8 element_type[0x8];
3097 u8 reserved_at_8[0x18];
3098
3099 u8 element_attributes[0x20];
3100
3101 u8 parent_element_id[0x20];
3102
3103 u8 reserved_at_60[0x40];
3104
3105 u8 bw_share[0x20];
3106
3107 u8 max_average_bw[0x20];
3108
3109 u8 reserved_at_e0[0x120];
3110 };
3111
3112 struct mlx5_ifc_rqtc_bits {
3113 u8 reserved_at_0[0xa0];
3114
3115 u8 reserved_at_a0[0x10];
3116 u8 rqt_max_size[0x10];
3117
3118 u8 reserved_at_c0[0x10];
3119 u8 rqt_actual_size[0x10];
3120
3121 u8 reserved_at_e0[0x6a0];
3122
3123 struct mlx5_ifc_rq_num_bits rq_num[0];
3124 };
3125
3126 enum {
3127 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3128 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3129 };
3130
3131 enum {
3132 MLX5_RQC_STATE_RST = 0x0,
3133 MLX5_RQC_STATE_RDY = 0x1,
3134 MLX5_RQC_STATE_ERR = 0x3,
3135 };
3136
3137 struct mlx5_ifc_rqc_bits {
3138 u8 rlky[0x1];
3139 u8 delay_drop_en[0x1];
3140 u8 scatter_fcs[0x1];
3141 u8 vsd[0x1];
3142 u8 mem_rq_type[0x4];
3143 u8 state[0x4];
3144 u8 reserved_at_c[0x1];
3145 u8 flush_in_error_en[0x1];
3146 u8 hairpin[0x1];
3147 u8 reserved_at_f[0x11];
3148
3149 u8 reserved_at_20[0x8];
3150 u8 user_index[0x18];
3151
3152 u8 reserved_at_40[0x8];
3153 u8 cqn[0x18];
3154
3155 u8 counter_set_id[0x8];
3156 u8 reserved_at_68[0x18];
3157
3158 u8 reserved_at_80[0x8];
3159 u8 rmpn[0x18];
3160
3161 u8 reserved_at_a0[0x8];
3162 u8 hairpin_peer_sq[0x18];
3163
3164 u8 reserved_at_c0[0x10];
3165 u8 hairpin_peer_vhca[0x10];
3166
3167 u8 reserved_at_e0[0xa0];
3168
3169 struct mlx5_ifc_wq_bits wq;
3170 };
3171
3172 enum {
3173 MLX5_RMPC_STATE_RDY = 0x1,
3174 MLX5_RMPC_STATE_ERR = 0x3,
3175 };
3176
3177 struct mlx5_ifc_rmpc_bits {
3178 u8 reserved_at_0[0x8];
3179 u8 state[0x4];
3180 u8 reserved_at_c[0x14];
3181
3182 u8 basic_cyclic_rcv_wqe[0x1];
3183 u8 reserved_at_21[0x1f];
3184
3185 u8 reserved_at_40[0x140];
3186
3187 struct mlx5_ifc_wq_bits wq;
3188 };
3189
3190 struct mlx5_ifc_nic_vport_context_bits {
3191 u8 reserved_at_0[0x5];
3192 u8 min_wqe_inline_mode[0x3];
3193 u8 reserved_at_8[0x15];
3194 u8 disable_mc_local_lb[0x1];
3195 u8 disable_uc_local_lb[0x1];
3196 u8 roce_en[0x1];
3197
3198 u8 arm_change_event[0x1];
3199 u8 reserved_at_21[0x1a];
3200 u8 event_on_mtu[0x1];
3201 u8 event_on_promisc_change[0x1];
3202 u8 event_on_vlan_change[0x1];
3203 u8 event_on_mc_address_change[0x1];
3204 u8 event_on_uc_address_change[0x1];
3205
3206 u8 reserved_at_40[0xc];
3207
3208 u8 affiliation_criteria[0x4];
3209 u8 affiliated_vhca_id[0x10];
3210
3211 u8 reserved_at_60[0xd0];
3212
3213 u8 mtu[0x10];
3214
3215 u8 system_image_guid[0x40];
3216 u8 port_guid[0x40];
3217 u8 node_guid[0x40];
3218
3219 u8 reserved_at_200[0x140];
3220 u8 qkey_violation_counter[0x10];
3221 u8 reserved_at_350[0x430];
3222
3223 u8 promisc_uc[0x1];
3224 u8 promisc_mc[0x1];
3225 u8 promisc_all[0x1];
3226 u8 reserved_at_783[0x2];
3227 u8 allowed_list_type[0x3];
3228 u8 reserved_at_788[0xc];
3229 u8 allowed_list_size[0xc];
3230
3231 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3232
3233 u8 reserved_at_7e0[0x20];
3234
3235 u8 current_uc_mac_address[0][0x40];
3236 };
3237
3238 enum {
3239 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3240 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3241 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3242 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3243 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3244 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3245 };
3246
3247 struct mlx5_ifc_mkc_bits {
3248 u8 reserved_at_0[0x1];
3249 u8 free[0x1];
3250 u8 reserved_at_2[0x1];
3251 u8 access_mode_4_2[0x3];
3252 u8 reserved_at_6[0x7];
3253 u8 relaxed_ordering_write[0x1];
3254 u8 reserved_at_e[0x1];
3255 u8 small_fence_on_rdma_read_response[0x1];
3256 u8 umr_en[0x1];
3257 u8 a[0x1];
3258 u8 rw[0x1];
3259 u8 rr[0x1];
3260 u8 lw[0x1];
3261 u8 lr[0x1];
3262 u8 access_mode_1_0[0x2];
3263 u8 reserved_at_18[0x8];
3264
3265 u8 qpn[0x18];
3266 u8 mkey_7_0[0x8];
3267
3268 u8 reserved_at_40[0x20];
3269
3270 u8 length64[0x1];
3271 u8 bsf_en[0x1];
3272 u8 sync_umr[0x1];
3273 u8 reserved_at_63[0x2];
3274 u8 expected_sigerr_count[0x1];
3275 u8 reserved_at_66[0x1];
3276 u8 en_rinval[0x1];
3277 u8 pd[0x18];
3278
3279 u8 start_addr[0x40];
3280
3281 u8 len[0x40];
3282
3283 u8 bsf_octword_size[0x20];
3284
3285 u8 reserved_at_120[0x80];
3286
3287 u8 translations_octword_size[0x20];
3288
3289 u8 reserved_at_1c0[0x1b];
3290 u8 log_page_size[0x5];
3291
3292 u8 reserved_at_1e0[0x20];
3293 };
3294
3295 struct mlx5_ifc_pkey_bits {
3296 u8 reserved_at_0[0x10];
3297 u8 pkey[0x10];
3298 };
3299
3300 struct mlx5_ifc_array128_auto_bits {
3301 u8 array128_auto[16][0x8];
3302 };
3303
3304 struct mlx5_ifc_hca_vport_context_bits {
3305 u8 field_select[0x20];
3306
3307 u8 reserved_at_20[0xe0];
3308
3309 u8 sm_virt_aware[0x1];
3310 u8 has_smi[0x1];
3311 u8 has_raw[0x1];
3312 u8 grh_required[0x1];
3313 u8 reserved_at_104[0xc];
3314 u8 port_physical_state[0x4];
3315 u8 vport_state_policy[0x4];
3316 u8 port_state[0x4];
3317 u8 vport_state[0x4];
3318
3319 u8 reserved_at_120[0x20];
3320
3321 u8 system_image_guid[0x40];
3322
3323 u8 port_guid[0x40];
3324
3325 u8 node_guid[0x40];
3326
3327 u8 cap_mask1[0x20];
3328
3329 u8 cap_mask1_field_select[0x20];
3330
3331 u8 cap_mask2[0x20];
3332
3333 u8 cap_mask2_field_select[0x20];
3334
3335 u8 reserved_at_280[0x80];
3336
3337 u8 lid[0x10];
3338 u8 reserved_at_310[0x4];
3339 u8 init_type_reply[0x4];
3340 u8 lmc[0x3];
3341 u8 subnet_timeout[0x5];
3342
3343 u8 sm_lid[0x10];
3344 u8 sm_sl[0x4];
3345 u8 reserved_at_334[0xc];
3346
3347 u8 qkey_violation_counter[0x10];
3348 u8 pkey_violation_counter[0x10];
3349
3350 u8 reserved_at_360[0xca0];
3351 };
3352
3353 struct mlx5_ifc_esw_vport_context_bits {
3354 u8 fdb_to_vport_reg_c[0x1];
3355 u8 reserved_at_1[0x2];
3356 u8 vport_svlan_strip[0x1];
3357 u8 vport_cvlan_strip[0x1];
3358 u8 vport_svlan_insert[0x1];
3359 u8 vport_cvlan_insert[0x2];
3360 u8 fdb_to_vport_reg_c_id[0x8];
3361 u8 reserved_at_10[0x10];
3362
3363 u8 reserved_at_20[0x20];
3364
3365 u8 svlan_cfi[0x1];
3366 u8 svlan_pcp[0x3];
3367 u8 svlan_id[0xc];
3368 u8 cvlan_cfi[0x1];
3369 u8 cvlan_pcp[0x3];
3370 u8 cvlan_id[0xc];
3371
3372 u8 reserved_at_60[0x720];
3373
3374 u8 sw_steering_vport_icm_address_rx[0x40];
3375
3376 u8 sw_steering_vport_icm_address_tx[0x40];
3377 };
3378
3379 enum {
3380 MLX5_EQC_STATUS_OK = 0x0,
3381 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3382 };
3383
3384 enum {
3385 MLX5_EQC_ST_ARMED = 0x9,
3386 MLX5_EQC_ST_FIRED = 0xa,
3387 };
3388
3389 struct mlx5_ifc_eqc_bits {
3390 u8 status[0x4];
3391 u8 reserved_at_4[0x9];
3392 u8 ec[0x1];
3393 u8 oi[0x1];
3394 u8 reserved_at_f[0x5];
3395 u8 st[0x4];
3396 u8 reserved_at_18[0x8];
3397
3398 u8 reserved_at_20[0x20];
3399
3400 u8 reserved_at_40[0x14];
3401 u8 page_offset[0x6];
3402 u8 reserved_at_5a[0x6];
3403
3404 u8 reserved_at_60[0x3];
3405 u8 log_eq_size[0x5];
3406 u8 uar_page[0x18];
3407
3408 u8 reserved_at_80[0x20];
3409
3410 u8 reserved_at_a0[0x18];
3411 u8 intr[0x8];
3412
3413 u8 reserved_at_c0[0x3];
3414 u8 log_page_size[0x5];
3415 u8 reserved_at_c8[0x18];
3416
3417 u8 reserved_at_e0[0x60];
3418
3419 u8 reserved_at_140[0x8];
3420 u8 consumer_counter[0x18];
3421
3422 u8 reserved_at_160[0x8];
3423 u8 producer_counter[0x18];
3424
3425 u8 reserved_at_180[0x80];
3426 };
3427
3428 enum {
3429 MLX5_DCTC_STATE_ACTIVE = 0x0,
3430 MLX5_DCTC_STATE_DRAINING = 0x1,
3431 MLX5_DCTC_STATE_DRAINED = 0x2,
3432 };
3433
3434 enum {
3435 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3436 MLX5_DCTC_CS_RES_NA = 0x1,
3437 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3438 };
3439
3440 enum {
3441 MLX5_DCTC_MTU_256_BYTES = 0x1,
3442 MLX5_DCTC_MTU_512_BYTES = 0x2,
3443 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3444 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3445 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3446 };
3447
3448 struct mlx5_ifc_dctc_bits {
3449 u8 reserved_at_0[0x4];
3450 u8 state[0x4];
3451 u8 reserved_at_8[0x18];
3452
3453 u8 reserved_at_20[0x8];
3454 u8 user_index[0x18];
3455
3456 u8 reserved_at_40[0x8];
3457 u8 cqn[0x18];
3458
3459 u8 counter_set_id[0x8];
3460 u8 atomic_mode[0x4];
3461 u8 rre[0x1];
3462 u8 rwe[0x1];
3463 u8 rae[0x1];
3464 u8 atomic_like_write_en[0x1];
3465 u8 latency_sensitive[0x1];
3466 u8 rlky[0x1];
3467 u8 free_ar[0x1];
3468 u8 reserved_at_73[0xd];
3469
3470 u8 reserved_at_80[0x8];
3471 u8 cs_res[0x8];
3472 u8 reserved_at_90[0x3];
3473 u8 min_rnr_nak[0x5];
3474 u8 reserved_at_98[0x8];
3475
3476 u8 reserved_at_a0[0x8];
3477 u8 srqn_xrqn[0x18];
3478
3479 u8 reserved_at_c0[0x8];
3480 u8 pd[0x18];
3481
3482 u8 tclass[0x8];
3483 u8 reserved_at_e8[0x4];
3484 u8 flow_label[0x14];
3485
3486 u8 dc_access_key[0x40];
3487
3488 u8 reserved_at_140[0x5];
3489 u8 mtu[0x3];
3490 u8 port[0x8];
3491 u8 pkey_index[0x10];
3492
3493 u8 reserved_at_160[0x8];
3494 u8 my_addr_index[0x8];
3495 u8 reserved_at_170[0x8];
3496 u8 hop_limit[0x8];
3497
3498 u8 dc_access_key_violation_count[0x20];
3499
3500 u8 reserved_at_1a0[0x14];
3501 u8 dei_cfi[0x1];
3502 u8 eth_prio[0x3];
3503 u8 ecn[0x2];
3504 u8 dscp[0x6];
3505
3506 u8 reserved_at_1c0[0x40];
3507 };
3508
3509 enum {
3510 MLX5_CQC_STATUS_OK = 0x0,
3511 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3512 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3513 };
3514
3515 enum {
3516 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3517 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3518 };
3519
3520 enum {
3521 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3522 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3523 MLX5_CQC_ST_FIRED = 0xa,
3524 };
3525
3526 enum {
3527 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3528 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3529 MLX5_CQ_PERIOD_NUM_MODES
3530 };
3531
3532 struct mlx5_ifc_cqc_bits {
3533 u8 status[0x4];
3534 u8 reserved_at_4[0x2];
3535 u8 dbr_umem_valid[0x1];
3536 u8 reserved_at_7[0x1];
3537 u8 cqe_sz[0x3];
3538 u8 cc[0x1];
3539 u8 reserved_at_c[0x1];
3540 u8 scqe_break_moderation_en[0x1];
3541 u8 oi[0x1];
3542 u8 cq_period_mode[0x2];
3543 u8 cqe_comp_en[0x1];
3544 u8 mini_cqe_res_format[0x2];
3545 u8 st[0x4];
3546 u8 reserved_at_18[0x8];
3547
3548 u8 reserved_at_20[0x20];
3549
3550 u8 reserved_at_40[0x14];
3551 u8 page_offset[0x6];
3552 u8 reserved_at_5a[0x6];
3553
3554 u8 reserved_at_60[0x3];
3555 u8 log_cq_size[0x5];
3556 u8 uar_page[0x18];
3557
3558 u8 reserved_at_80[0x4];
3559 u8 cq_period[0xc];
3560 u8 cq_max_count[0x10];
3561
3562 u8 reserved_at_a0[0x18];
3563 u8 c_eqn[0x8];
3564
3565 u8 reserved_at_c0[0x3];
3566 u8 log_page_size[0x5];
3567 u8 reserved_at_c8[0x18];
3568
3569 u8 reserved_at_e0[0x20];
3570
3571 u8 reserved_at_100[0x8];
3572 u8 last_notified_index[0x18];
3573
3574 u8 reserved_at_120[0x8];
3575 u8 last_solicit_index[0x18];
3576
3577 u8 reserved_at_140[0x8];
3578 u8 consumer_counter[0x18];
3579
3580 u8 reserved_at_160[0x8];
3581 u8 producer_counter[0x18];
3582
3583 u8 reserved_at_180[0x40];
3584
3585 u8 dbr_addr[0x40];
3586 };
3587
3588 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3589 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3590 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3591 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3592 u8 reserved_at_0[0x800];
3593 };
3594
3595 struct mlx5_ifc_query_adapter_param_block_bits {
3596 u8 reserved_at_0[0xc0];
3597
3598 u8 reserved_at_c0[0x8];
3599 u8 ieee_vendor_id[0x18];
3600
3601 u8 reserved_at_e0[0x10];
3602 u8 vsd_vendor_id[0x10];
3603
3604 u8 vsd[208][0x8];
3605
3606 u8 vsd_contd_psid[16][0x8];
3607 };
3608
3609 enum {
3610 MLX5_XRQC_STATE_GOOD = 0x0,
3611 MLX5_XRQC_STATE_ERROR = 0x1,
3612 };
3613
3614 enum {
3615 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3616 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3617 };
3618
3619 enum {
3620 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3621 };
3622
3623 struct mlx5_ifc_tag_matching_topology_context_bits {
3624 u8 log_matching_list_sz[0x4];
3625 u8 reserved_at_4[0xc];
3626 u8 append_next_index[0x10];
3627
3628 u8 sw_phase_cnt[0x10];
3629 u8 hw_phase_cnt[0x10];
3630
3631 u8 reserved_at_40[0x40];
3632 };
3633
3634 struct mlx5_ifc_xrqc_bits {
3635 u8 state[0x4];
3636 u8 rlkey[0x1];
3637 u8 reserved_at_5[0xf];
3638 u8 topology[0x4];
3639 u8 reserved_at_18[0x4];
3640 u8 offload[0x4];
3641
3642 u8 reserved_at_20[0x8];
3643 u8 user_index[0x18];
3644
3645 u8 reserved_at_40[0x8];
3646 u8 cqn[0x18];
3647
3648 u8 reserved_at_60[0xa0];
3649
3650 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3651
3652 u8 reserved_at_180[0x280];
3653
3654 struct mlx5_ifc_wq_bits wq;
3655 };
3656
3657 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3658 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3659 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3660 u8 reserved_at_0[0x20];
3661 };
3662
3663 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3664 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3665 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3666 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3667 u8 reserved_at_0[0x20];
3668 };
3669
3670 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3671 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3672 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3673 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3674 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3675 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3676 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3677 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3678 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3679 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3680 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3681 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3682 u8 reserved_at_0[0x7c0];
3683 };
3684
3685 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3686 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3687 u8 reserved_at_0[0x7c0];
3688 };
3689
3690 union mlx5_ifc_event_auto_bits {
3691 struct mlx5_ifc_comp_event_bits comp_event;
3692 struct mlx5_ifc_dct_events_bits dct_events;
3693 struct mlx5_ifc_qp_events_bits qp_events;
3694 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3695 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3696 struct mlx5_ifc_cq_error_bits cq_error;
3697 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3698 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3699 struct mlx5_ifc_gpio_event_bits gpio_event;
3700 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3701 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3702 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3703 u8 reserved_at_0[0xe0];
3704 };
3705
3706 struct mlx5_ifc_health_buffer_bits {
3707 u8 reserved_at_0[0x100];
3708
3709 u8 assert_existptr[0x20];
3710
3711 u8 assert_callra[0x20];
3712
3713 u8 reserved_at_140[0x40];
3714
3715 u8 fw_version[0x20];
3716
3717 u8 hw_id[0x20];
3718
3719 u8 reserved_at_1c0[0x20];
3720
3721 u8 irisc_index[0x8];
3722 u8 synd[0x8];
3723 u8 ext_synd[0x10];
3724 };
3725
3726 struct mlx5_ifc_register_loopback_control_bits {
3727 u8 no_lb[0x1];
3728 u8 reserved_at_1[0x7];
3729 u8 port[0x8];
3730 u8 reserved_at_10[0x10];
3731
3732 u8 reserved_at_20[0x60];
3733 };
3734
3735 struct mlx5_ifc_vport_tc_element_bits {
3736 u8 traffic_class[0x4];
3737 u8 reserved_at_4[0xc];
3738 u8 vport_number[0x10];
3739 };
3740
3741 struct mlx5_ifc_vport_element_bits {
3742 u8 reserved_at_0[0x10];
3743 u8 vport_number[0x10];
3744 };
3745
3746 enum {
3747 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3748 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3749 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3750 };
3751
3752 struct mlx5_ifc_tsar_element_bits {
3753 u8 reserved_at_0[0x8];
3754 u8 tsar_type[0x8];
3755 u8 reserved_at_10[0x10];
3756 };
3757
3758 enum {
3759 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3760 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3761 };
3762
3763 struct mlx5_ifc_teardown_hca_out_bits {
3764 u8 status[0x8];
3765 u8 reserved_at_8[0x18];
3766
3767 u8 syndrome[0x20];
3768
3769 u8 reserved_at_40[0x3f];
3770
3771 u8 state[0x1];
3772 };
3773
3774 enum {
3775 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3776 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3777 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3778 };
3779
3780 struct mlx5_ifc_teardown_hca_in_bits {
3781 u8 opcode[0x10];
3782 u8 reserved_at_10[0x10];
3783
3784 u8 reserved_at_20[0x10];
3785 u8 op_mod[0x10];
3786
3787 u8 reserved_at_40[0x10];
3788 u8 profile[0x10];
3789
3790 u8 reserved_at_60[0x20];
3791 };
3792
3793 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3794 u8 status[0x8];
3795 u8 reserved_at_8[0x18];
3796
3797 u8 syndrome[0x20];
3798
3799 u8 reserved_at_40[0x40];
3800 };
3801
3802 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3803 u8 opcode[0x10];
3804 u8 uid[0x10];
3805
3806 u8 reserved_at_20[0x10];
3807 u8 op_mod[0x10];
3808
3809 u8 reserved_at_40[0x8];
3810 u8 qpn[0x18];
3811
3812 u8 reserved_at_60[0x20];
3813
3814 u8 opt_param_mask[0x20];
3815
3816 u8 reserved_at_a0[0x20];
3817
3818 struct mlx5_ifc_qpc_bits qpc;
3819
3820 u8 reserved_at_800[0x80];
3821 };
3822
3823 struct mlx5_ifc_sqd2rts_qp_out_bits {
3824 u8 status[0x8];
3825 u8 reserved_at_8[0x18];
3826
3827 u8 syndrome[0x20];
3828
3829 u8 reserved_at_40[0x40];
3830 };
3831
3832 struct mlx5_ifc_sqd2rts_qp_in_bits {
3833 u8 opcode[0x10];
3834 u8 uid[0x10];
3835
3836 u8 reserved_at_20[0x10];
3837 u8 op_mod[0x10];
3838
3839 u8 reserved_at_40[0x8];
3840 u8 qpn[0x18];
3841
3842 u8 reserved_at_60[0x20];
3843
3844 u8 opt_param_mask[0x20];
3845
3846 u8 reserved_at_a0[0x20];
3847
3848 struct mlx5_ifc_qpc_bits qpc;
3849
3850 u8 reserved_at_800[0x80];
3851 };
3852
3853 struct mlx5_ifc_set_roce_address_out_bits {
3854 u8 status[0x8];
3855 u8 reserved_at_8[0x18];
3856
3857 u8 syndrome[0x20];
3858
3859 u8 reserved_at_40[0x40];
3860 };
3861
3862 struct mlx5_ifc_set_roce_address_in_bits {
3863 u8 opcode[0x10];
3864 u8 reserved_at_10[0x10];
3865
3866 u8 reserved_at_20[0x10];
3867 u8 op_mod[0x10];
3868
3869 u8 roce_address_index[0x10];
3870 u8 reserved_at_50[0xc];
3871 u8 vhca_port_num[0x4];
3872
3873 u8 reserved_at_60[0x20];
3874
3875 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3876 };
3877
3878 struct mlx5_ifc_set_mad_demux_out_bits {
3879 u8 status[0x8];
3880 u8 reserved_at_8[0x18];
3881
3882 u8 syndrome[0x20];
3883
3884 u8 reserved_at_40[0x40];
3885 };
3886
3887 enum {
3888 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3889 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3890 };
3891
3892 struct mlx5_ifc_set_mad_demux_in_bits {
3893 u8 opcode[0x10];
3894 u8 reserved_at_10[0x10];
3895
3896 u8 reserved_at_20[0x10];
3897 u8 op_mod[0x10];
3898
3899 u8 reserved_at_40[0x20];
3900
3901 u8 reserved_at_60[0x6];
3902 u8 demux_mode[0x2];
3903 u8 reserved_at_68[0x18];
3904 };
3905
3906 struct mlx5_ifc_set_l2_table_entry_out_bits {
3907 u8 status[0x8];
3908 u8 reserved_at_8[0x18];
3909
3910 u8 syndrome[0x20];
3911
3912 u8 reserved_at_40[0x40];
3913 };
3914
3915 struct mlx5_ifc_set_l2_table_entry_in_bits {
3916 u8 opcode[0x10];
3917 u8 reserved_at_10[0x10];
3918
3919 u8 reserved_at_20[0x10];
3920 u8 op_mod[0x10];
3921
3922 u8 reserved_at_40[0x60];
3923
3924 u8 reserved_at_a0[0x8];
3925 u8 table_index[0x18];
3926
3927 u8 reserved_at_c0[0x20];
3928
3929 u8 reserved_at_e0[0x13];
3930 u8 vlan_valid[0x1];
3931 u8 vlan[0xc];
3932
3933 struct mlx5_ifc_mac_address_layout_bits mac_address;
3934
3935 u8 reserved_at_140[0xc0];
3936 };
3937
3938 struct mlx5_ifc_set_issi_out_bits {
3939 u8 status[0x8];
3940 u8 reserved_at_8[0x18];
3941
3942 u8 syndrome[0x20];
3943
3944 u8 reserved_at_40[0x40];
3945 };
3946
3947 struct mlx5_ifc_set_issi_in_bits {
3948 u8 opcode[0x10];
3949 u8 reserved_at_10[0x10];
3950
3951 u8 reserved_at_20[0x10];
3952 u8 op_mod[0x10];
3953
3954 u8 reserved_at_40[0x10];
3955 u8 current_issi[0x10];
3956
3957 u8 reserved_at_60[0x20];
3958 };
3959
3960 struct mlx5_ifc_set_hca_cap_out_bits {
3961 u8 status[0x8];
3962 u8 reserved_at_8[0x18];
3963
3964 u8 syndrome[0x20];
3965
3966 u8 reserved_at_40[0x40];
3967 };
3968
3969 struct mlx5_ifc_set_hca_cap_in_bits {
3970 u8 opcode[0x10];
3971 u8 reserved_at_10[0x10];
3972
3973 u8 reserved_at_20[0x10];
3974 u8 op_mod[0x10];
3975
3976 u8 reserved_at_40[0x40];
3977
3978 union mlx5_ifc_hca_cap_union_bits capability;
3979 };
3980
3981 enum {
3982 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3983 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3984 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3985 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3986 };
3987
3988 struct mlx5_ifc_set_fte_out_bits {
3989 u8 status[0x8];
3990 u8 reserved_at_8[0x18];
3991
3992 u8 syndrome[0x20];
3993
3994 u8 reserved_at_40[0x40];
3995 };
3996
3997 struct mlx5_ifc_set_fte_in_bits {
3998 u8 opcode[0x10];
3999 u8 reserved_at_10[0x10];
4000
4001 u8 reserved_at_20[0x10];
4002 u8 op_mod[0x10];
4003
4004 u8 other_vport[0x1];
4005 u8 reserved_at_41[0xf];
4006 u8 vport_number[0x10];
4007
4008 u8 reserved_at_60[0x20];
4009
4010 u8 table_type[0x8];
4011 u8 reserved_at_88[0x18];
4012
4013 u8 reserved_at_a0[0x8];
4014 u8 table_id[0x18];
4015
4016 u8 reserved_at_c0[0x18];
4017 u8 modify_enable_mask[0x8];
4018
4019 u8 reserved_at_e0[0x20];
4020
4021 u8 flow_index[0x20];
4022
4023 u8 reserved_at_120[0xe0];
4024
4025 struct mlx5_ifc_flow_context_bits flow_context;
4026 };
4027
4028 struct mlx5_ifc_rts2rts_qp_out_bits {
4029 u8 status[0x8];
4030 u8 reserved_at_8[0x18];
4031
4032 u8 syndrome[0x20];
4033
4034 u8 reserved_at_40[0x40];
4035 };
4036
4037 struct mlx5_ifc_rts2rts_qp_in_bits {
4038 u8 opcode[0x10];
4039 u8 uid[0x10];
4040
4041 u8 reserved_at_20[0x10];
4042 u8 op_mod[0x10];
4043
4044 u8 reserved_at_40[0x8];
4045 u8 qpn[0x18];
4046
4047 u8 reserved_at_60[0x20];
4048
4049 u8 opt_param_mask[0x20];
4050
4051 u8 reserved_at_a0[0x20];
4052
4053 struct mlx5_ifc_qpc_bits qpc;
4054
4055 u8 reserved_at_800[0x80];
4056 };
4057
4058 struct mlx5_ifc_rtr2rts_qp_out_bits {
4059 u8 status[0x8];
4060 u8 reserved_at_8[0x18];
4061
4062 u8 syndrome[0x20];
4063
4064 u8 reserved_at_40[0x40];
4065 };
4066
4067 struct mlx5_ifc_rtr2rts_qp_in_bits {
4068 u8 opcode[0x10];
4069 u8 uid[0x10];
4070
4071 u8 reserved_at_20[0x10];
4072 u8 op_mod[0x10];
4073
4074 u8 reserved_at_40[0x8];
4075 u8 qpn[0x18];
4076
4077 u8 reserved_at_60[0x20];
4078
4079 u8 opt_param_mask[0x20];
4080
4081 u8 reserved_at_a0[0x20];
4082
4083 struct mlx5_ifc_qpc_bits qpc;
4084
4085 u8 reserved_at_800[0x80];
4086 };
4087
4088 struct mlx5_ifc_rst2init_qp_out_bits {
4089 u8 status[0x8];
4090 u8 reserved_at_8[0x18];
4091
4092 u8 syndrome[0x20];
4093
4094 u8 reserved_at_40[0x40];
4095 };
4096
4097 struct mlx5_ifc_rst2init_qp_in_bits {
4098 u8 opcode[0x10];
4099 u8 uid[0x10];
4100
4101 u8 reserved_at_20[0x10];
4102 u8 op_mod[0x10];
4103
4104 u8 reserved_at_40[0x8];
4105 u8 qpn[0x18];
4106
4107 u8 reserved_at_60[0x20];
4108
4109 u8 opt_param_mask[0x20];
4110
4111 u8 reserved_at_a0[0x20];
4112
4113 struct mlx5_ifc_qpc_bits qpc;
4114
4115 u8 reserved_at_800[0x80];
4116 };
4117
4118 struct mlx5_ifc_query_xrq_out_bits {
4119 u8 status[0x8];
4120 u8 reserved_at_8[0x18];
4121
4122 u8 syndrome[0x20];
4123
4124 u8 reserved_at_40[0x40];
4125
4126 struct mlx5_ifc_xrqc_bits xrq_context;
4127 };
4128
4129 struct mlx5_ifc_query_xrq_in_bits {
4130 u8 opcode[0x10];
4131 u8 reserved_at_10[0x10];
4132
4133 u8 reserved_at_20[0x10];
4134 u8 op_mod[0x10];
4135
4136 u8 reserved_at_40[0x8];
4137 u8 xrqn[0x18];
4138
4139 u8 reserved_at_60[0x20];
4140 };
4141
4142 struct mlx5_ifc_query_xrc_srq_out_bits {
4143 u8 status[0x8];
4144 u8 reserved_at_8[0x18];
4145
4146 u8 syndrome[0x20];
4147
4148 u8 reserved_at_40[0x40];
4149
4150 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4151
4152 u8 reserved_at_280[0x600];
4153
4154 u8 pas[0][0x40];
4155 };
4156
4157 struct mlx5_ifc_query_xrc_srq_in_bits {
4158 u8 opcode[0x10];
4159 u8 reserved_at_10[0x10];
4160
4161 u8 reserved_at_20[0x10];
4162 u8 op_mod[0x10];
4163
4164 u8 reserved_at_40[0x8];
4165 u8 xrc_srqn[0x18];
4166
4167 u8 reserved_at_60[0x20];
4168 };
4169
4170 enum {
4171 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4172 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4173 };
4174
4175 struct mlx5_ifc_query_vport_state_out_bits {
4176 u8 status[0x8];
4177 u8 reserved_at_8[0x18];
4178
4179 u8 syndrome[0x20];
4180
4181 u8 reserved_at_40[0x20];
4182
4183 u8 reserved_at_60[0x18];
4184 u8 admin_state[0x4];
4185 u8 state[0x4];
4186 };
4187
4188 enum {
4189 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4190 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4191 };
4192
4193 struct mlx5_ifc_arm_monitor_counter_in_bits {
4194 u8 opcode[0x10];
4195 u8 uid[0x10];
4196
4197 u8 reserved_at_20[0x10];
4198 u8 op_mod[0x10];
4199
4200 u8 reserved_at_40[0x20];
4201
4202 u8 reserved_at_60[0x20];
4203 };
4204
4205 struct mlx5_ifc_arm_monitor_counter_out_bits {
4206 u8 status[0x8];
4207 u8 reserved_at_8[0x18];
4208
4209 u8 syndrome[0x20];
4210
4211 u8 reserved_at_40[0x40];
4212 };
4213
4214 enum {
4215 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4216 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4217 };
4218
4219 enum mlx5_monitor_counter_ppcnt {
4220 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4221 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4222 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4223 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4224 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4225 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4226 };
4227
4228 enum {
4229 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4230 };
4231
4232 struct mlx5_ifc_monitor_counter_output_bits {
4233 u8 reserved_at_0[0x4];
4234 u8 type[0x4];
4235 u8 reserved_at_8[0x8];
4236 u8 counter[0x10];
4237
4238 u8 counter_group_id[0x20];
4239 };
4240
4241 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4242 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4243 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4244 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4245
4246 struct mlx5_ifc_set_monitor_counter_in_bits {
4247 u8 opcode[0x10];
4248 u8 uid[0x10];
4249
4250 u8 reserved_at_20[0x10];
4251 u8 op_mod[0x10];
4252
4253 u8 reserved_at_40[0x10];
4254 u8 num_of_counters[0x10];
4255
4256 u8 reserved_at_60[0x20];
4257
4258 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4259 };
4260
4261 struct mlx5_ifc_set_monitor_counter_out_bits {
4262 u8 status[0x8];
4263 u8 reserved_at_8[0x18];
4264
4265 u8 syndrome[0x20];
4266
4267 u8 reserved_at_40[0x40];
4268 };
4269
4270 struct mlx5_ifc_query_vport_state_in_bits {
4271 u8 opcode[0x10];
4272 u8 reserved_at_10[0x10];
4273
4274 u8 reserved_at_20[0x10];
4275 u8 op_mod[0x10];
4276
4277 u8 other_vport[0x1];
4278 u8 reserved_at_41[0xf];
4279 u8 vport_number[0x10];
4280
4281 u8 reserved_at_60[0x20];
4282 };
4283
4284 struct mlx5_ifc_query_vnic_env_out_bits {
4285 u8 status[0x8];
4286 u8 reserved_at_8[0x18];
4287
4288 u8 syndrome[0x20];
4289
4290 u8 reserved_at_40[0x40];
4291
4292 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4293 };
4294
4295 enum {
4296 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4297 };
4298
4299 struct mlx5_ifc_query_vnic_env_in_bits {
4300 u8 opcode[0x10];
4301 u8 reserved_at_10[0x10];
4302
4303 u8 reserved_at_20[0x10];
4304 u8 op_mod[0x10];
4305
4306 u8 other_vport[0x1];
4307 u8 reserved_at_41[0xf];
4308 u8 vport_number[0x10];
4309
4310 u8 reserved_at_60[0x20];
4311 };
4312
4313 struct mlx5_ifc_query_vport_counter_out_bits {
4314 u8 status[0x8];
4315 u8 reserved_at_8[0x18];
4316
4317 u8 syndrome[0x20];
4318
4319 u8 reserved_at_40[0x40];
4320
4321 struct mlx5_ifc_traffic_counter_bits received_errors;
4322
4323 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4324
4325 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4326
4327 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4328
4329 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4330
4331 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4332
4333 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4334
4335 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4336
4337 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4338
4339 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4340
4341 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4342
4343 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4344
4345 u8 reserved_at_680[0xa00];
4346 };
4347
4348 enum {
4349 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4350 };
4351
4352 struct mlx5_ifc_query_vport_counter_in_bits {
4353 u8 opcode[0x10];
4354 u8 reserved_at_10[0x10];
4355
4356 u8 reserved_at_20[0x10];
4357 u8 op_mod[0x10];
4358
4359 u8 other_vport[0x1];
4360 u8 reserved_at_41[0xb];
4361 u8 port_num[0x4];
4362 u8 vport_number[0x10];
4363
4364 u8 reserved_at_60[0x60];
4365
4366 u8 clear[0x1];
4367 u8 reserved_at_c1[0x1f];
4368
4369 u8 reserved_at_e0[0x20];
4370 };
4371
4372 struct mlx5_ifc_query_tis_out_bits {
4373 u8 status[0x8];
4374 u8 reserved_at_8[0x18];
4375
4376 u8 syndrome[0x20];
4377
4378 u8 reserved_at_40[0x40];
4379
4380 struct mlx5_ifc_tisc_bits tis_context;
4381 };
4382
4383 struct mlx5_ifc_query_tis_in_bits {
4384 u8 opcode[0x10];
4385 u8 reserved_at_10[0x10];
4386
4387 u8 reserved_at_20[0x10];
4388 u8 op_mod[0x10];
4389
4390 u8 reserved_at_40[0x8];
4391 u8 tisn[0x18];
4392
4393 u8 reserved_at_60[0x20];
4394 };
4395
4396 struct mlx5_ifc_query_tir_out_bits {
4397 u8 status[0x8];
4398 u8 reserved_at_8[0x18];
4399
4400 u8 syndrome[0x20];
4401
4402 u8 reserved_at_40[0xc0];
4403
4404 struct mlx5_ifc_tirc_bits tir_context;
4405 };
4406
4407 struct mlx5_ifc_query_tir_in_bits {
4408 u8 opcode[0x10];
4409 u8 reserved_at_10[0x10];
4410
4411 u8 reserved_at_20[0x10];
4412 u8 op_mod[0x10];
4413
4414 u8 reserved_at_40[0x8];
4415 u8 tirn[0x18];
4416
4417 u8 reserved_at_60[0x20];
4418 };
4419
4420 struct mlx5_ifc_query_srq_out_bits {
4421 u8 status[0x8];
4422 u8 reserved_at_8[0x18];
4423
4424 u8 syndrome[0x20];
4425
4426 u8 reserved_at_40[0x40];
4427
4428 struct mlx5_ifc_srqc_bits srq_context_entry;
4429
4430 u8 reserved_at_280[0x600];
4431
4432 u8 pas[0][0x40];
4433 };
4434
4435 struct mlx5_ifc_query_srq_in_bits {
4436 u8 opcode[0x10];
4437 u8 reserved_at_10[0x10];
4438
4439 u8 reserved_at_20[0x10];
4440 u8 op_mod[0x10];
4441
4442 u8 reserved_at_40[0x8];
4443 u8 srqn[0x18];
4444
4445 u8 reserved_at_60[0x20];
4446 };
4447
4448 struct mlx5_ifc_query_sq_out_bits {
4449 u8 status[0x8];
4450 u8 reserved_at_8[0x18];
4451
4452 u8 syndrome[0x20];
4453
4454 u8 reserved_at_40[0xc0];
4455
4456 struct mlx5_ifc_sqc_bits sq_context;
4457 };
4458
4459 struct mlx5_ifc_query_sq_in_bits {
4460 u8 opcode[0x10];
4461 u8 reserved_at_10[0x10];
4462
4463 u8 reserved_at_20[0x10];
4464 u8 op_mod[0x10];
4465
4466 u8 reserved_at_40[0x8];
4467 u8 sqn[0x18];
4468
4469 u8 reserved_at_60[0x20];
4470 };
4471
4472 struct mlx5_ifc_query_special_contexts_out_bits {
4473 u8 status[0x8];
4474 u8 reserved_at_8[0x18];
4475
4476 u8 syndrome[0x20];
4477
4478 u8 dump_fill_mkey[0x20];
4479
4480 u8 resd_lkey[0x20];
4481
4482 u8 null_mkey[0x20];
4483
4484 u8 reserved_at_a0[0x60];
4485 };
4486
4487 struct mlx5_ifc_query_special_contexts_in_bits {
4488 u8 opcode[0x10];
4489 u8 reserved_at_10[0x10];
4490
4491 u8 reserved_at_20[0x10];
4492 u8 op_mod[0x10];
4493
4494 u8 reserved_at_40[0x40];
4495 };
4496
4497 struct mlx5_ifc_query_scheduling_element_out_bits {
4498 u8 opcode[0x10];
4499 u8 reserved_at_10[0x10];
4500
4501 u8 reserved_at_20[0x10];
4502 u8 op_mod[0x10];
4503
4504 u8 reserved_at_40[0xc0];
4505
4506 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4507
4508 u8 reserved_at_300[0x100];
4509 };
4510
4511 enum {
4512 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4513 };
4514
4515 struct mlx5_ifc_query_scheduling_element_in_bits {
4516 u8 opcode[0x10];
4517 u8 reserved_at_10[0x10];
4518
4519 u8 reserved_at_20[0x10];
4520 u8 op_mod[0x10];
4521
4522 u8 scheduling_hierarchy[0x8];
4523 u8 reserved_at_48[0x18];
4524
4525 u8 scheduling_element_id[0x20];
4526
4527 u8 reserved_at_80[0x180];
4528 };
4529
4530 struct mlx5_ifc_query_rqt_out_bits {
4531 u8 status[0x8];
4532 u8 reserved_at_8[0x18];
4533
4534 u8 syndrome[0x20];
4535
4536 u8 reserved_at_40[0xc0];
4537
4538 struct mlx5_ifc_rqtc_bits rqt_context;
4539 };
4540
4541 struct mlx5_ifc_query_rqt_in_bits {
4542 u8 opcode[0x10];
4543 u8 reserved_at_10[0x10];
4544
4545 u8 reserved_at_20[0x10];
4546 u8 op_mod[0x10];
4547
4548 u8 reserved_at_40[0x8];
4549 u8 rqtn[0x18];
4550
4551 u8 reserved_at_60[0x20];
4552 };
4553
4554 struct mlx5_ifc_query_rq_out_bits {
4555 u8 status[0x8];
4556 u8 reserved_at_8[0x18];
4557
4558 u8 syndrome[0x20];
4559
4560 u8 reserved_at_40[0xc0];
4561
4562 struct mlx5_ifc_rqc_bits rq_context;
4563 };
4564
4565 struct mlx5_ifc_query_rq_in_bits {
4566 u8 opcode[0x10];
4567 u8 reserved_at_10[0x10];
4568
4569 u8 reserved_at_20[0x10];
4570 u8 op_mod[0x10];
4571
4572 u8 reserved_at_40[0x8];
4573 u8 rqn[0x18];
4574
4575 u8 reserved_at_60[0x20];
4576 };
4577
4578 struct mlx5_ifc_query_roce_address_out_bits {
4579 u8 status[0x8];
4580 u8 reserved_at_8[0x18];
4581
4582 u8 syndrome[0x20];
4583
4584 u8 reserved_at_40[0x40];
4585
4586 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4587 };
4588
4589 struct mlx5_ifc_query_roce_address_in_bits {
4590 u8 opcode[0x10];
4591 u8 reserved_at_10[0x10];
4592
4593 u8 reserved_at_20[0x10];
4594 u8 op_mod[0x10];
4595
4596 u8 roce_address_index[0x10];
4597 u8 reserved_at_50[0xc];
4598 u8 vhca_port_num[0x4];
4599
4600 u8 reserved_at_60[0x20];
4601 };
4602
4603 struct mlx5_ifc_query_rmp_out_bits {
4604 u8 status[0x8];
4605 u8 reserved_at_8[0x18];
4606
4607 u8 syndrome[0x20];
4608
4609 u8 reserved_at_40[0xc0];
4610
4611 struct mlx5_ifc_rmpc_bits rmp_context;
4612 };
4613
4614 struct mlx5_ifc_query_rmp_in_bits {
4615 u8 opcode[0x10];
4616 u8 reserved_at_10[0x10];
4617
4618 u8 reserved_at_20[0x10];
4619 u8 op_mod[0x10];
4620
4621 u8 reserved_at_40[0x8];
4622 u8 rmpn[0x18];
4623
4624 u8 reserved_at_60[0x20];
4625 };
4626
4627 struct mlx5_ifc_query_qp_out_bits {
4628 u8 status[0x8];
4629 u8 reserved_at_8[0x18];
4630
4631 u8 syndrome[0x20];
4632
4633 u8 reserved_at_40[0x40];
4634
4635 u8 opt_param_mask[0x20];
4636
4637 u8 reserved_at_a0[0x20];
4638
4639 struct mlx5_ifc_qpc_bits qpc;
4640
4641 u8 reserved_at_800[0x80];
4642
4643 u8 pas[0][0x40];
4644 };
4645
4646 struct mlx5_ifc_query_qp_in_bits {
4647 u8 opcode[0x10];
4648 u8 reserved_at_10[0x10];
4649
4650 u8 reserved_at_20[0x10];
4651 u8 op_mod[0x10];
4652
4653 u8 reserved_at_40[0x8];
4654 u8 qpn[0x18];
4655
4656 u8 reserved_at_60[0x20];
4657 };
4658
4659 struct mlx5_ifc_query_q_counter_out_bits {
4660 u8 status[0x8];
4661 u8 reserved_at_8[0x18];
4662
4663 u8 syndrome[0x20];
4664
4665 u8 reserved_at_40[0x40];
4666
4667 u8 rx_write_requests[0x20];
4668
4669 u8 reserved_at_a0[0x20];
4670
4671 u8 rx_read_requests[0x20];
4672
4673 u8 reserved_at_e0[0x20];
4674
4675 u8 rx_atomic_requests[0x20];
4676
4677 u8 reserved_at_120[0x20];
4678
4679 u8 rx_dct_connect[0x20];
4680
4681 u8 reserved_at_160[0x20];
4682
4683 u8 out_of_buffer[0x20];
4684
4685 u8 reserved_at_1a0[0x20];
4686
4687 u8 out_of_sequence[0x20];
4688
4689 u8 reserved_at_1e0[0x20];
4690
4691 u8 duplicate_request[0x20];
4692
4693 u8 reserved_at_220[0x20];
4694
4695 u8 rnr_nak_retry_err[0x20];
4696
4697 u8 reserved_at_260[0x20];
4698
4699 u8 packet_seq_err[0x20];
4700
4701 u8 reserved_at_2a0[0x20];
4702
4703 u8 implied_nak_seq_err[0x20];
4704
4705 u8 reserved_at_2e0[0x20];
4706
4707 u8 local_ack_timeout_err[0x20];
4708
4709 u8 reserved_at_320[0xa0];
4710
4711 u8 resp_local_length_error[0x20];
4712
4713 u8 req_local_length_error[0x20];
4714
4715 u8 resp_local_qp_error[0x20];
4716
4717 u8 local_operation_error[0x20];
4718
4719 u8 resp_local_protection[0x20];
4720
4721 u8 req_local_protection[0x20];
4722
4723 u8 resp_cqe_error[0x20];
4724
4725 u8 req_cqe_error[0x20];
4726
4727 u8 req_mw_binding[0x20];
4728
4729 u8 req_bad_response[0x20];
4730
4731 u8 req_remote_invalid_request[0x20];
4732
4733 u8 resp_remote_invalid_request[0x20];
4734
4735 u8 req_remote_access_errors[0x20];
4736
4737 u8 resp_remote_access_errors[0x20];
4738
4739 u8 req_remote_operation_errors[0x20];
4740
4741 u8 req_transport_retries_exceeded[0x20];
4742
4743 u8 cq_overflow[0x20];
4744
4745 u8 resp_cqe_flush_error[0x20];
4746
4747 u8 req_cqe_flush_error[0x20];
4748
4749 u8 reserved_at_620[0x1e0];
4750 };
4751
4752 struct mlx5_ifc_query_q_counter_in_bits {
4753 u8 opcode[0x10];
4754 u8 reserved_at_10[0x10];
4755
4756 u8 reserved_at_20[0x10];
4757 u8 op_mod[0x10];
4758
4759 u8 reserved_at_40[0x80];
4760
4761 u8 clear[0x1];
4762 u8 reserved_at_c1[0x1f];
4763
4764 u8 reserved_at_e0[0x18];
4765 u8 counter_set_id[0x8];
4766 };
4767
4768 struct mlx5_ifc_query_pages_out_bits {
4769 u8 status[0x8];
4770 u8 reserved_at_8[0x18];
4771
4772 u8 syndrome[0x20];
4773
4774 u8 embedded_cpu_function[0x1];
4775 u8 reserved_at_41[0xf];
4776 u8 function_id[0x10];
4777
4778 u8 num_pages[0x20];
4779 };
4780
4781 enum {
4782 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4783 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4784 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4785 };
4786
4787 struct mlx5_ifc_query_pages_in_bits {
4788 u8 opcode[0x10];
4789 u8 reserved_at_10[0x10];
4790
4791 u8 reserved_at_20[0x10];
4792 u8 op_mod[0x10];
4793
4794 u8 embedded_cpu_function[0x1];
4795 u8 reserved_at_41[0xf];
4796 u8 function_id[0x10];
4797
4798 u8 reserved_at_60[0x20];
4799 };
4800
4801 struct mlx5_ifc_query_nic_vport_context_out_bits {
4802 u8 status[0x8];
4803 u8 reserved_at_8[0x18];
4804
4805 u8 syndrome[0x20];
4806
4807 u8 reserved_at_40[0x40];
4808
4809 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4810 };
4811
4812 struct mlx5_ifc_query_nic_vport_context_in_bits {
4813 u8 opcode[0x10];
4814 u8 reserved_at_10[0x10];
4815
4816 u8 reserved_at_20[0x10];
4817 u8 op_mod[0x10];
4818
4819 u8 other_vport[0x1];
4820 u8 reserved_at_41[0xf];
4821 u8 vport_number[0x10];
4822
4823 u8 reserved_at_60[0x5];
4824 u8 allowed_list_type[0x3];
4825 u8 reserved_at_68[0x18];
4826 };
4827
4828 struct mlx5_ifc_query_mkey_out_bits {
4829 u8 status[0x8];
4830 u8 reserved_at_8[0x18];
4831
4832 u8 syndrome[0x20];
4833
4834 u8 reserved_at_40[0x40];
4835
4836 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4837
4838 u8 reserved_at_280[0x600];
4839
4840 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4841
4842 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4843 };
4844
4845 struct mlx5_ifc_query_mkey_in_bits {
4846 u8 opcode[0x10];
4847 u8 reserved_at_10[0x10];
4848
4849 u8 reserved_at_20[0x10];
4850 u8 op_mod[0x10];
4851
4852 u8 reserved_at_40[0x8];
4853 u8 mkey_index[0x18];
4854
4855 u8 pg_access[0x1];
4856 u8 reserved_at_61[0x1f];
4857 };
4858
4859 struct mlx5_ifc_query_mad_demux_out_bits {
4860 u8 status[0x8];
4861 u8 reserved_at_8[0x18];
4862
4863 u8 syndrome[0x20];
4864
4865 u8 reserved_at_40[0x40];
4866
4867 u8 mad_dumux_parameters_block[0x20];
4868 };
4869
4870 struct mlx5_ifc_query_mad_demux_in_bits {
4871 u8 opcode[0x10];
4872 u8 reserved_at_10[0x10];
4873
4874 u8 reserved_at_20[0x10];
4875 u8 op_mod[0x10];
4876
4877 u8 reserved_at_40[0x40];
4878 };
4879
4880 struct mlx5_ifc_query_l2_table_entry_out_bits {
4881 u8 status[0x8];
4882 u8 reserved_at_8[0x18];
4883
4884 u8 syndrome[0x20];
4885
4886 u8 reserved_at_40[0xa0];
4887
4888 u8 reserved_at_e0[0x13];
4889 u8 vlan_valid[0x1];
4890 u8 vlan[0xc];
4891
4892 struct mlx5_ifc_mac_address_layout_bits mac_address;
4893
4894 u8 reserved_at_140[0xc0];
4895 };
4896
4897 struct mlx5_ifc_query_l2_table_entry_in_bits {
4898 u8 opcode[0x10];
4899 u8 reserved_at_10[0x10];
4900
4901 u8 reserved_at_20[0x10];
4902 u8 op_mod[0x10];
4903
4904 u8 reserved_at_40[0x60];
4905
4906 u8 reserved_at_a0[0x8];
4907 u8 table_index[0x18];
4908
4909 u8 reserved_at_c0[0x140];
4910 };
4911
4912 struct mlx5_ifc_query_issi_out_bits {
4913 u8 status[0x8];
4914 u8 reserved_at_8[0x18];
4915
4916 u8 syndrome[0x20];
4917
4918 u8 reserved_at_40[0x10];
4919 u8 current_issi[0x10];
4920
4921 u8 reserved_at_60[0xa0];
4922
4923 u8 reserved_at_100[76][0x8];
4924 u8 supported_issi_dw0[0x20];
4925 };
4926
4927 struct mlx5_ifc_query_issi_in_bits {
4928 u8 opcode[0x10];
4929 u8 reserved_at_10[0x10];
4930
4931 u8 reserved_at_20[0x10];
4932 u8 op_mod[0x10];
4933
4934 u8 reserved_at_40[0x40];
4935 };
4936
4937 struct mlx5_ifc_set_driver_version_out_bits {
4938 u8 status[0x8];
4939 u8 reserved_0[0x18];
4940
4941 u8 syndrome[0x20];
4942 u8 reserved_1[0x40];
4943 };
4944
4945 struct mlx5_ifc_set_driver_version_in_bits {
4946 u8 opcode[0x10];
4947 u8 reserved_0[0x10];
4948
4949 u8 reserved_1[0x10];
4950 u8 op_mod[0x10];
4951
4952 u8 reserved_2[0x40];
4953 u8 driver_version[64][0x8];
4954 };
4955
4956 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4957 u8 status[0x8];
4958 u8 reserved_at_8[0x18];
4959
4960 u8 syndrome[0x20];
4961
4962 u8 reserved_at_40[0x40];
4963
4964 struct mlx5_ifc_pkey_bits pkey[0];
4965 };
4966
4967 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4968 u8 opcode[0x10];
4969 u8 reserved_at_10[0x10];
4970
4971 u8 reserved_at_20[0x10];
4972 u8 op_mod[0x10];
4973
4974 u8 other_vport[0x1];
4975 u8 reserved_at_41[0xb];
4976 u8 port_num[0x4];
4977 u8 vport_number[0x10];
4978
4979 u8 reserved_at_60[0x10];
4980 u8 pkey_index[0x10];
4981 };
4982
4983 enum {
4984 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4985 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4986 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4987 };
4988
4989 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4990 u8 status[0x8];
4991 u8 reserved_at_8[0x18];
4992
4993 u8 syndrome[0x20];
4994
4995 u8 reserved_at_40[0x20];
4996
4997 u8 gids_num[0x10];
4998 u8 reserved_at_70[0x10];
4999
5000 struct mlx5_ifc_array128_auto_bits gid[0];
5001 };
5002
5003 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5004 u8 opcode[0x10];
5005 u8 reserved_at_10[0x10];
5006
5007 u8 reserved_at_20[0x10];
5008 u8 op_mod[0x10];
5009
5010 u8 other_vport[0x1];
5011 u8 reserved_at_41[0xb];
5012 u8 port_num[0x4];
5013 u8 vport_number[0x10];
5014
5015 u8 reserved_at_60[0x10];
5016 u8 gid_index[0x10];
5017 };
5018
5019 struct mlx5_ifc_query_hca_vport_context_out_bits {
5020 u8 status[0x8];
5021 u8 reserved_at_8[0x18];
5022
5023 u8 syndrome[0x20];
5024
5025 u8 reserved_at_40[0x40];
5026
5027 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5028 };
5029
5030 struct mlx5_ifc_query_hca_vport_context_in_bits {
5031 u8 opcode[0x10];
5032 u8 reserved_at_10[0x10];
5033
5034 u8 reserved_at_20[0x10];
5035 u8 op_mod[0x10];
5036
5037 u8 other_vport[0x1];
5038 u8 reserved_at_41[0xb];
5039 u8 port_num[0x4];
5040 u8 vport_number[0x10];
5041
5042 u8 reserved_at_60[0x20];
5043 };
5044
5045 struct mlx5_ifc_query_hca_cap_out_bits {
5046 u8 status[0x8];
5047 u8 reserved_at_8[0x18];
5048
5049 u8 syndrome[0x20];
5050
5051 u8 reserved_at_40[0x40];
5052
5053 union mlx5_ifc_hca_cap_union_bits capability;
5054 };
5055
5056 struct mlx5_ifc_query_hca_cap_in_bits {
5057 u8 opcode[0x10];
5058 u8 reserved_at_10[0x10];
5059
5060 u8 reserved_at_20[0x10];
5061 u8 op_mod[0x10];
5062
5063 u8 other_function[0x1];
5064 u8 reserved_at_41[0xf];
5065 u8 function_id[0x10];
5066
5067 u8 reserved_at_60[0x20];
5068 };
5069
5070 struct mlx5_ifc_other_hca_cap_bits {
5071 u8 roce[0x1];
5072 u8 reserved_at_1[0x27f];
5073 };
5074
5075 struct mlx5_ifc_query_other_hca_cap_out_bits {
5076 u8 status[0x8];
5077 u8 reserved_at_8[0x18];
5078
5079 u8 syndrome[0x20];
5080
5081 u8 reserved_at_40[0x40];
5082
5083 struct mlx5_ifc_other_hca_cap_bits other_capability;
5084 };
5085
5086 struct mlx5_ifc_query_other_hca_cap_in_bits {
5087 u8 opcode[0x10];
5088 u8 reserved_at_10[0x10];
5089
5090 u8 reserved_at_20[0x10];
5091 u8 op_mod[0x10];
5092
5093 u8 reserved_at_40[0x10];
5094 u8 function_id[0x10];
5095
5096 u8 reserved_at_60[0x20];
5097 };
5098
5099 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5100 u8 status[0x8];
5101 u8 reserved_at_8[0x18];
5102
5103 u8 syndrome[0x20];
5104
5105 u8 reserved_at_40[0x40];
5106 };
5107
5108 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5109 u8 opcode[0x10];
5110 u8 reserved_at_10[0x10];
5111
5112 u8 reserved_at_20[0x10];
5113 u8 op_mod[0x10];
5114
5115 u8 reserved_at_40[0x10];
5116 u8 function_id[0x10];
5117 u8 field_select[0x20];
5118
5119 struct mlx5_ifc_other_hca_cap_bits other_capability;
5120 };
5121
5122 struct mlx5_ifc_flow_table_context_bits {
5123 u8 reformat_en[0x1];
5124 u8 decap_en[0x1];
5125 u8 sw_owner[0x1];
5126 u8 termination_table[0x1];
5127 u8 table_miss_action[0x4];
5128 u8 level[0x8];
5129 u8 reserved_at_10[0x8];
5130 u8 log_size[0x8];
5131
5132 u8 reserved_at_20[0x8];
5133 u8 table_miss_id[0x18];
5134
5135 u8 reserved_at_40[0x8];
5136 u8 lag_master_next_table_id[0x18];
5137
5138 u8 reserved_at_60[0x60];
5139
5140 u8 sw_owner_icm_root_1[0x40];
5141
5142 u8 sw_owner_icm_root_0[0x40];
5143
5144 };
5145
5146 struct mlx5_ifc_query_flow_table_out_bits {
5147 u8 status[0x8];
5148 u8 reserved_at_8[0x18];
5149
5150 u8 syndrome[0x20];
5151
5152 u8 reserved_at_40[0x80];
5153
5154 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5155 };
5156
5157 struct mlx5_ifc_query_flow_table_in_bits {
5158 u8 opcode[0x10];
5159 u8 reserved_at_10[0x10];
5160
5161 u8 reserved_at_20[0x10];
5162 u8 op_mod[0x10];
5163
5164 u8 reserved_at_40[0x40];
5165
5166 u8 table_type[0x8];
5167 u8 reserved_at_88[0x18];
5168
5169 u8 reserved_at_a0[0x8];
5170 u8 table_id[0x18];
5171
5172 u8 reserved_at_c0[0x140];
5173 };
5174
5175 struct mlx5_ifc_query_fte_out_bits {
5176 u8 status[0x8];
5177 u8 reserved_at_8[0x18];
5178
5179 u8 syndrome[0x20];
5180
5181 u8 reserved_at_40[0x1c0];
5182
5183 struct mlx5_ifc_flow_context_bits flow_context;
5184 };
5185
5186 struct mlx5_ifc_query_fte_in_bits {
5187 u8 opcode[0x10];
5188 u8 reserved_at_10[0x10];
5189
5190 u8 reserved_at_20[0x10];
5191 u8 op_mod[0x10];
5192
5193 u8 reserved_at_40[0x40];
5194
5195 u8 table_type[0x8];
5196 u8 reserved_at_88[0x18];
5197
5198 u8 reserved_at_a0[0x8];
5199 u8 table_id[0x18];
5200
5201 u8 reserved_at_c0[0x40];
5202
5203 u8 flow_index[0x20];
5204
5205 u8 reserved_at_120[0xe0];
5206 };
5207
5208 enum {
5209 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5210 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5211 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5212 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5213 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5214 };
5215
5216 struct mlx5_ifc_query_flow_group_out_bits {
5217 u8 status[0x8];
5218 u8 reserved_at_8[0x18];
5219
5220 u8 syndrome[0x20];
5221
5222 u8 reserved_at_40[0xa0];
5223
5224 u8 start_flow_index[0x20];
5225
5226 u8 reserved_at_100[0x20];
5227
5228 u8 end_flow_index[0x20];
5229
5230 u8 reserved_at_140[0xa0];
5231
5232 u8 reserved_at_1e0[0x18];
5233 u8 match_criteria_enable[0x8];
5234
5235 struct mlx5_ifc_fte_match_param_bits match_criteria;
5236
5237 u8 reserved_at_1200[0xe00];
5238 };
5239
5240 struct mlx5_ifc_query_flow_group_in_bits {
5241 u8 opcode[0x10];
5242 u8 reserved_at_10[0x10];
5243
5244 u8 reserved_at_20[0x10];
5245 u8 op_mod[0x10];
5246
5247 u8 reserved_at_40[0x40];
5248
5249 u8 table_type[0x8];
5250 u8 reserved_at_88[0x18];
5251
5252 u8 reserved_at_a0[0x8];
5253 u8 table_id[0x18];
5254
5255 u8 group_id[0x20];
5256
5257 u8 reserved_at_e0[0x120];
5258 };
5259
5260 struct mlx5_ifc_query_flow_counter_out_bits {
5261 u8 status[0x8];
5262 u8 reserved_at_8[0x18];
5263
5264 u8 syndrome[0x20];
5265
5266 u8 reserved_at_40[0x40];
5267
5268 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5269 };
5270
5271 struct mlx5_ifc_query_flow_counter_in_bits {
5272 u8 opcode[0x10];
5273 u8 reserved_at_10[0x10];
5274
5275 u8 reserved_at_20[0x10];
5276 u8 op_mod[0x10];
5277
5278 u8 reserved_at_40[0x80];
5279
5280 u8 clear[0x1];
5281 u8 reserved_at_c1[0xf];
5282 u8 num_of_counters[0x10];
5283
5284 u8 flow_counter_id[0x20];
5285 };
5286
5287 struct mlx5_ifc_query_esw_vport_context_out_bits {
5288 u8 status[0x8];
5289 u8 reserved_at_8[0x18];
5290
5291 u8 syndrome[0x20];
5292
5293 u8 reserved_at_40[0x40];
5294
5295 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5296 };
5297
5298 struct mlx5_ifc_query_esw_vport_context_in_bits {
5299 u8 opcode[0x10];
5300 u8 reserved_at_10[0x10];
5301
5302 u8 reserved_at_20[0x10];
5303 u8 op_mod[0x10];
5304
5305 u8 other_vport[0x1];
5306 u8 reserved_at_41[0xf];
5307 u8 vport_number[0x10];
5308
5309 u8 reserved_at_60[0x20];
5310 };
5311
5312 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5313 u8 status[0x8];
5314 u8 reserved_at_8[0x18];
5315
5316 u8 syndrome[0x20];
5317
5318 u8 reserved_at_40[0x40];
5319 };
5320
5321 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5322 u8 reserved_at_0[0x1b];
5323 u8 fdb_to_vport_reg_c_id[0x1];
5324 u8 vport_cvlan_insert[0x1];
5325 u8 vport_svlan_insert[0x1];
5326 u8 vport_cvlan_strip[0x1];
5327 u8 vport_svlan_strip[0x1];
5328 };
5329
5330 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5331 u8 opcode[0x10];
5332 u8 reserved_at_10[0x10];
5333
5334 u8 reserved_at_20[0x10];
5335 u8 op_mod[0x10];
5336
5337 u8 other_vport[0x1];
5338 u8 reserved_at_41[0xf];
5339 u8 vport_number[0x10];
5340
5341 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5342
5343 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5344 };
5345
5346 struct mlx5_ifc_query_eq_out_bits {
5347 u8 status[0x8];
5348 u8 reserved_at_8[0x18];
5349
5350 u8 syndrome[0x20];
5351
5352 u8 reserved_at_40[0x40];
5353
5354 struct mlx5_ifc_eqc_bits eq_context_entry;
5355
5356 u8 reserved_at_280[0x40];
5357
5358 u8 event_bitmask[0x40];
5359
5360 u8 reserved_at_300[0x580];
5361
5362 u8 pas[0][0x40];
5363 };
5364
5365 struct mlx5_ifc_query_eq_in_bits {
5366 u8 opcode[0x10];
5367 u8 reserved_at_10[0x10];
5368
5369 u8 reserved_at_20[0x10];
5370 u8 op_mod[0x10];
5371
5372 u8 reserved_at_40[0x18];
5373 u8 eq_number[0x8];
5374
5375 u8 reserved_at_60[0x20];
5376 };
5377
5378 struct mlx5_ifc_packet_reformat_context_in_bits {
5379 u8 reserved_at_0[0x5];
5380 u8 reformat_type[0x3];
5381 u8 reserved_at_8[0xe];
5382 u8 reformat_data_size[0xa];
5383
5384 u8 reserved_at_20[0x10];
5385 u8 reformat_data[2][0x8];
5386
5387 u8 more_reformat_data[0][0x8];
5388 };
5389
5390 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5391 u8 status[0x8];
5392 u8 reserved_at_8[0x18];
5393
5394 u8 syndrome[0x20];
5395
5396 u8 reserved_at_40[0xa0];
5397
5398 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5399 };
5400
5401 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5402 u8 opcode[0x10];
5403 u8 reserved_at_10[0x10];
5404
5405 u8 reserved_at_20[0x10];
5406 u8 op_mod[0x10];
5407
5408 u8 packet_reformat_id[0x20];
5409
5410 u8 reserved_at_60[0xa0];
5411 };
5412
5413 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5414 u8 status[0x8];
5415 u8 reserved_at_8[0x18];
5416
5417 u8 syndrome[0x20];
5418
5419 u8 packet_reformat_id[0x20];
5420
5421 u8 reserved_at_60[0x20];
5422 };
5423
5424 enum mlx5_reformat_ctx_type {
5425 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5426 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5427 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5428 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5429 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5430 };
5431
5432 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5433 u8 opcode[0x10];
5434 u8 reserved_at_10[0x10];
5435
5436 u8 reserved_at_20[0x10];
5437 u8 op_mod[0x10];
5438
5439 u8 reserved_at_40[0xa0];
5440
5441 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5442 };
5443
5444 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5445 u8 status[0x8];
5446 u8 reserved_at_8[0x18];
5447
5448 u8 syndrome[0x20];
5449
5450 u8 reserved_at_40[0x40];
5451 };
5452
5453 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5454 u8 opcode[0x10];
5455 u8 reserved_at_10[0x10];
5456
5457 u8 reserved_20[0x10];
5458 u8 op_mod[0x10];
5459
5460 u8 packet_reformat_id[0x20];
5461
5462 u8 reserved_60[0x20];
5463 };
5464
5465 struct mlx5_ifc_set_action_in_bits {
5466 u8 action_type[0x4];
5467 u8 field[0xc];
5468 u8 reserved_at_10[0x3];
5469 u8 offset[0x5];
5470 u8 reserved_at_18[0x3];
5471 u8 length[0x5];
5472
5473 u8 data[0x20];
5474 };
5475
5476 struct mlx5_ifc_add_action_in_bits {
5477 u8 action_type[0x4];
5478 u8 field[0xc];
5479 u8 reserved_at_10[0x10];
5480
5481 u8 data[0x20];
5482 };
5483
5484 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5485 struct mlx5_ifc_set_action_in_bits set_action_in;
5486 struct mlx5_ifc_add_action_in_bits add_action_in;
5487 u8 reserved_at_0[0x40];
5488 };
5489
5490 enum {
5491 MLX5_ACTION_TYPE_SET = 0x1,
5492 MLX5_ACTION_TYPE_ADD = 0x2,
5493 };
5494
5495 enum {
5496 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5497 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5498 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5499 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5500 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5501 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5502 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5503 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5504 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5505 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5506 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5507 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5508 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5509 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5510 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5511 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5512 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5513 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5514 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5515 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5516 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5517 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5518 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5519 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5520 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5521 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5522 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5523 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5524 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5525 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5526 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5527 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5528 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5529 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5530 };
5531
5532 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5533 u8 status[0x8];
5534 u8 reserved_at_8[0x18];
5535
5536 u8 syndrome[0x20];
5537
5538 u8 modify_header_id[0x20];
5539
5540 u8 reserved_at_60[0x20];
5541 };
5542
5543 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5544 u8 opcode[0x10];
5545 u8 reserved_at_10[0x10];
5546
5547 u8 reserved_at_20[0x10];
5548 u8 op_mod[0x10];
5549
5550 u8 reserved_at_40[0x20];
5551
5552 u8 table_type[0x8];
5553 u8 reserved_at_68[0x10];
5554 u8 num_of_actions[0x8];
5555
5556 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5557 };
5558
5559 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5560 u8 status[0x8];
5561 u8 reserved_at_8[0x18];
5562
5563 u8 syndrome[0x20];
5564
5565 u8 reserved_at_40[0x40];
5566 };
5567
5568 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5569 u8 opcode[0x10];
5570 u8 reserved_at_10[0x10];
5571
5572 u8 reserved_at_20[0x10];
5573 u8 op_mod[0x10];
5574
5575 u8 modify_header_id[0x20];
5576
5577 u8 reserved_at_60[0x20];
5578 };
5579
5580 struct mlx5_ifc_query_dct_out_bits {
5581 u8 status[0x8];
5582 u8 reserved_at_8[0x18];
5583
5584 u8 syndrome[0x20];
5585
5586 u8 reserved_at_40[0x40];
5587
5588 struct mlx5_ifc_dctc_bits dct_context_entry;
5589
5590 u8 reserved_at_280[0x180];
5591 };
5592
5593 struct mlx5_ifc_query_dct_in_bits {
5594 u8 opcode[0x10];
5595 u8 reserved_at_10[0x10];
5596
5597 u8 reserved_at_20[0x10];
5598 u8 op_mod[0x10];
5599
5600 u8 reserved_at_40[0x8];
5601 u8 dctn[0x18];
5602
5603 u8 reserved_at_60[0x20];
5604 };
5605
5606 struct mlx5_ifc_query_cq_out_bits {
5607 u8 status[0x8];
5608 u8 reserved_at_8[0x18];
5609
5610 u8 syndrome[0x20];
5611
5612 u8 reserved_at_40[0x40];
5613
5614 struct mlx5_ifc_cqc_bits cq_context;
5615
5616 u8 reserved_at_280[0x600];
5617
5618 u8 pas[0][0x40];
5619 };
5620
5621 struct mlx5_ifc_query_cq_in_bits {
5622 u8 opcode[0x10];
5623 u8 reserved_at_10[0x10];
5624
5625 u8 reserved_at_20[0x10];
5626 u8 op_mod[0x10];
5627
5628 u8 reserved_at_40[0x8];
5629 u8 cqn[0x18];
5630
5631 u8 reserved_at_60[0x20];
5632 };
5633
5634 struct mlx5_ifc_query_cong_status_out_bits {
5635 u8 status[0x8];
5636 u8 reserved_at_8[0x18];
5637
5638 u8 syndrome[0x20];
5639
5640 u8 reserved_at_40[0x20];
5641
5642 u8 enable[0x1];
5643 u8 tag_enable[0x1];
5644 u8 reserved_at_62[0x1e];
5645 };
5646
5647 struct mlx5_ifc_query_cong_status_in_bits {
5648 u8 opcode[0x10];
5649 u8 reserved_at_10[0x10];
5650
5651 u8 reserved_at_20[0x10];
5652 u8 op_mod[0x10];
5653
5654 u8 reserved_at_40[0x18];
5655 u8 priority[0x4];
5656 u8 cong_protocol[0x4];
5657
5658 u8 reserved_at_60[0x20];
5659 };
5660
5661 struct mlx5_ifc_query_cong_statistics_out_bits {
5662 u8 status[0x8];
5663 u8 reserved_at_8[0x18];
5664
5665 u8 syndrome[0x20];
5666
5667 u8 reserved_at_40[0x40];
5668
5669 u8 rp_cur_flows[0x20];
5670
5671 u8 sum_flows[0x20];
5672
5673 u8 rp_cnp_ignored_high[0x20];
5674
5675 u8 rp_cnp_ignored_low[0x20];
5676
5677 u8 rp_cnp_handled_high[0x20];
5678
5679 u8 rp_cnp_handled_low[0x20];
5680
5681 u8 reserved_at_140[0x100];
5682
5683 u8 time_stamp_high[0x20];
5684
5685 u8 time_stamp_low[0x20];
5686
5687 u8 accumulators_period[0x20];
5688
5689 u8 np_ecn_marked_roce_packets_high[0x20];
5690
5691 u8 np_ecn_marked_roce_packets_low[0x20];
5692
5693 u8 np_cnp_sent_high[0x20];
5694
5695 u8 np_cnp_sent_low[0x20];
5696
5697 u8 reserved_at_320[0x560];
5698 };
5699
5700 struct mlx5_ifc_query_cong_statistics_in_bits {
5701 u8 opcode[0x10];
5702 u8 reserved_at_10[0x10];
5703
5704 u8 reserved_at_20[0x10];
5705 u8 op_mod[0x10];
5706
5707 u8 clear[0x1];
5708 u8 reserved_at_41[0x1f];
5709
5710 u8 reserved_at_60[0x20];
5711 };
5712
5713 struct mlx5_ifc_query_cong_params_out_bits {
5714 u8 status[0x8];
5715 u8 reserved_at_8[0x18];
5716
5717 u8 syndrome[0x20];
5718
5719 u8 reserved_at_40[0x40];
5720
5721 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5722 };
5723
5724 struct mlx5_ifc_query_cong_params_in_bits {
5725 u8 opcode[0x10];
5726 u8 reserved_at_10[0x10];
5727
5728 u8 reserved_at_20[0x10];
5729 u8 op_mod[0x10];
5730
5731 u8 reserved_at_40[0x1c];
5732 u8 cong_protocol[0x4];
5733
5734 u8 reserved_at_60[0x20];
5735 };
5736
5737 struct mlx5_ifc_query_adapter_out_bits {
5738 u8 status[0x8];
5739 u8 reserved_at_8[0x18];
5740
5741 u8 syndrome[0x20];
5742
5743 u8 reserved_at_40[0x40];
5744
5745 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5746 };
5747
5748 struct mlx5_ifc_query_adapter_in_bits {
5749 u8 opcode[0x10];
5750 u8 reserved_at_10[0x10];
5751
5752 u8 reserved_at_20[0x10];
5753 u8 op_mod[0x10];
5754
5755 u8 reserved_at_40[0x40];
5756 };
5757
5758 struct mlx5_ifc_qp_2rst_out_bits {
5759 u8 status[0x8];
5760 u8 reserved_at_8[0x18];
5761
5762 u8 syndrome[0x20];
5763
5764 u8 reserved_at_40[0x40];
5765 };
5766
5767 struct mlx5_ifc_qp_2rst_in_bits {
5768 u8 opcode[0x10];
5769 u8 uid[0x10];
5770
5771 u8 reserved_at_20[0x10];
5772 u8 op_mod[0x10];
5773
5774 u8 reserved_at_40[0x8];
5775 u8 qpn[0x18];
5776
5777 u8 reserved_at_60[0x20];
5778 };
5779
5780 struct mlx5_ifc_qp_2err_out_bits {
5781 u8 status[0x8];
5782 u8 reserved_at_8[0x18];
5783
5784 u8 syndrome[0x20];
5785
5786 u8 reserved_at_40[0x40];
5787 };
5788
5789 struct mlx5_ifc_qp_2err_in_bits {
5790 u8 opcode[0x10];
5791 u8 uid[0x10];
5792
5793 u8 reserved_at_20[0x10];
5794 u8 op_mod[0x10];
5795
5796 u8 reserved_at_40[0x8];
5797 u8 qpn[0x18];
5798
5799 u8 reserved_at_60[0x20];
5800 };
5801
5802 struct mlx5_ifc_page_fault_resume_out_bits {
5803 u8 status[0x8];
5804 u8 reserved_at_8[0x18];
5805
5806 u8 syndrome[0x20];
5807
5808 u8 reserved_at_40[0x40];
5809 };
5810
5811 struct mlx5_ifc_page_fault_resume_in_bits {
5812 u8 opcode[0x10];
5813 u8 reserved_at_10[0x10];
5814
5815 u8 reserved_at_20[0x10];
5816 u8 op_mod[0x10];
5817
5818 u8 error[0x1];
5819 u8 reserved_at_41[0x4];
5820 u8 page_fault_type[0x3];
5821 u8 wq_number[0x18];
5822
5823 u8 reserved_at_60[0x8];
5824 u8 token[0x18];
5825 };
5826
5827 struct mlx5_ifc_nop_out_bits {
5828 u8 status[0x8];
5829 u8 reserved_at_8[0x18];
5830
5831 u8 syndrome[0x20];
5832
5833 u8 reserved_at_40[0x40];
5834 };
5835
5836 struct mlx5_ifc_nop_in_bits {
5837 u8 opcode[0x10];
5838 u8 reserved_at_10[0x10];
5839
5840 u8 reserved_at_20[0x10];
5841 u8 op_mod[0x10];
5842
5843 u8 reserved_at_40[0x40];
5844 };
5845
5846 struct mlx5_ifc_modify_vport_state_out_bits {
5847 u8 status[0x8];
5848 u8 reserved_at_8[0x18];
5849
5850 u8 syndrome[0x20];
5851
5852 u8 reserved_at_40[0x40];
5853 };
5854
5855 struct mlx5_ifc_modify_vport_state_in_bits {
5856 u8 opcode[0x10];
5857 u8 reserved_at_10[0x10];
5858
5859 u8 reserved_at_20[0x10];
5860 u8 op_mod[0x10];
5861
5862 u8 other_vport[0x1];
5863 u8 reserved_at_41[0xf];
5864 u8 vport_number[0x10];
5865
5866 u8 reserved_at_60[0x18];
5867 u8 admin_state[0x4];
5868 u8 reserved_at_7c[0x4];
5869 };
5870
5871 struct mlx5_ifc_modify_tis_out_bits {
5872 u8 status[0x8];
5873 u8 reserved_at_8[0x18];
5874
5875 u8 syndrome[0x20];
5876
5877 u8 reserved_at_40[0x40];
5878 };
5879
5880 struct mlx5_ifc_modify_tis_bitmask_bits {
5881 u8 reserved_at_0[0x20];
5882
5883 u8 reserved_at_20[0x1d];
5884 u8 lag_tx_port_affinity[0x1];
5885 u8 strict_lag_tx_port_affinity[0x1];
5886 u8 prio[0x1];
5887 };
5888
5889 struct mlx5_ifc_modify_tis_in_bits {
5890 u8 opcode[0x10];
5891 u8 uid[0x10];
5892
5893 u8 reserved_at_20[0x10];
5894 u8 op_mod[0x10];
5895
5896 u8 reserved_at_40[0x8];
5897 u8 tisn[0x18];
5898
5899 u8 reserved_at_60[0x20];
5900
5901 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5902
5903 u8 reserved_at_c0[0x40];
5904
5905 struct mlx5_ifc_tisc_bits ctx;
5906 };
5907
5908 struct mlx5_ifc_modify_tir_bitmask_bits {
5909 u8 reserved_at_0[0x20];
5910
5911 u8 reserved_at_20[0x1b];
5912 u8 self_lb_en[0x1];
5913 u8 reserved_at_3c[0x1];
5914 u8 hash[0x1];
5915 u8 reserved_at_3e[0x1];
5916 u8 lro[0x1];
5917 };
5918
5919 struct mlx5_ifc_modify_tir_out_bits {
5920 u8 status[0x8];
5921 u8 reserved_at_8[0x18];
5922
5923 u8 syndrome[0x20];
5924
5925 u8 reserved_at_40[0x40];
5926 };
5927
5928 struct mlx5_ifc_modify_tir_in_bits {
5929 u8 opcode[0x10];
5930 u8 uid[0x10];
5931
5932 u8 reserved_at_20[0x10];
5933 u8 op_mod[0x10];
5934
5935 u8 reserved_at_40[0x8];
5936 u8 tirn[0x18];
5937
5938 u8 reserved_at_60[0x20];
5939
5940 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5941
5942 u8 reserved_at_c0[0x40];
5943
5944 struct mlx5_ifc_tirc_bits ctx;
5945 };
5946
5947 struct mlx5_ifc_modify_sq_out_bits {
5948 u8 status[0x8];
5949 u8 reserved_at_8[0x18];
5950
5951 u8 syndrome[0x20];
5952
5953 u8 reserved_at_40[0x40];
5954 };
5955
5956 struct mlx5_ifc_modify_sq_in_bits {
5957 u8 opcode[0x10];
5958 u8 uid[0x10];
5959
5960 u8 reserved_at_20[0x10];
5961 u8 op_mod[0x10];
5962
5963 u8 sq_state[0x4];
5964 u8 reserved_at_44[0x4];
5965 u8 sqn[0x18];
5966
5967 u8 reserved_at_60[0x20];
5968
5969 u8 modify_bitmask[0x40];
5970
5971 u8 reserved_at_c0[0x40];
5972
5973 struct mlx5_ifc_sqc_bits ctx;
5974 };
5975
5976 struct mlx5_ifc_modify_scheduling_element_out_bits {
5977 u8 status[0x8];
5978 u8 reserved_at_8[0x18];
5979
5980 u8 syndrome[0x20];
5981
5982 u8 reserved_at_40[0x1c0];
5983 };
5984
5985 enum {
5986 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5987 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5988 };
5989
5990 struct mlx5_ifc_modify_scheduling_element_in_bits {
5991 u8 opcode[0x10];
5992 u8 reserved_at_10[0x10];
5993
5994 u8 reserved_at_20[0x10];
5995 u8 op_mod[0x10];
5996
5997 u8 scheduling_hierarchy[0x8];
5998 u8 reserved_at_48[0x18];
5999
6000 u8 scheduling_element_id[0x20];
6001
6002 u8 reserved_at_80[0x20];
6003
6004 u8 modify_bitmask[0x20];
6005
6006 u8 reserved_at_c0[0x40];
6007
6008 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6009
6010 u8 reserved_at_300[0x100];
6011 };
6012
6013 struct mlx5_ifc_modify_rqt_out_bits {
6014 u8 status[0x8];
6015 u8 reserved_at_8[0x18];
6016
6017 u8 syndrome[0x20];
6018
6019 u8 reserved_at_40[0x40];
6020 };
6021
6022 struct mlx5_ifc_rqt_bitmask_bits {
6023 u8 reserved_at_0[0x20];
6024
6025 u8 reserved_at_20[0x1f];
6026 u8 rqn_list[0x1];
6027 };
6028
6029 struct mlx5_ifc_modify_rqt_in_bits {
6030 u8 opcode[0x10];
6031 u8 uid[0x10];
6032
6033 u8 reserved_at_20[0x10];
6034 u8 op_mod[0x10];
6035
6036 u8 reserved_at_40[0x8];
6037 u8 rqtn[0x18];
6038
6039 u8 reserved_at_60[0x20];
6040
6041 struct mlx5_ifc_rqt_bitmask_bits bitmask;
6042
6043 u8 reserved_at_c0[0x40];
6044
6045 struct mlx5_ifc_rqtc_bits ctx;
6046 };
6047
6048 struct mlx5_ifc_modify_rq_out_bits {
6049 u8 status[0x8];
6050 u8 reserved_at_8[0x18];
6051
6052 u8 syndrome[0x20];
6053
6054 u8 reserved_at_40[0x40];
6055 };
6056
6057 enum {
6058 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6059 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6060 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6061 };
6062
6063 struct mlx5_ifc_modify_rq_in_bits {
6064 u8 opcode[0x10];
6065 u8 uid[0x10];
6066
6067 u8 reserved_at_20[0x10];
6068 u8 op_mod[0x10];
6069
6070 u8 rq_state[0x4];
6071 u8 reserved_at_44[0x4];
6072 u8 rqn[0x18];
6073
6074 u8 reserved_at_60[0x20];
6075
6076 u8 modify_bitmask[0x40];
6077
6078 u8 reserved_at_c0[0x40];
6079
6080 struct mlx5_ifc_rqc_bits ctx;
6081 };
6082
6083 struct mlx5_ifc_modify_rmp_out_bits {
6084 u8 status[0x8];
6085 u8 reserved_at_8[0x18];
6086
6087 u8 syndrome[0x20];
6088
6089 u8 reserved_at_40[0x40];
6090 };
6091
6092 struct mlx5_ifc_rmp_bitmask_bits {
6093 u8 reserved_at_0[0x20];
6094
6095 u8 reserved_at_20[0x1f];
6096 u8 lwm[0x1];
6097 };
6098
6099 struct mlx5_ifc_modify_rmp_in_bits {
6100 u8 opcode[0x10];
6101 u8 uid[0x10];
6102
6103 u8 reserved_at_20[0x10];
6104 u8 op_mod[0x10];
6105
6106 u8 rmp_state[0x4];
6107 u8 reserved_at_44[0x4];
6108 u8 rmpn[0x18];
6109
6110 u8 reserved_at_60[0x20];
6111
6112 struct mlx5_ifc_rmp_bitmask_bits bitmask;
6113
6114 u8 reserved_at_c0[0x40];
6115
6116 struct mlx5_ifc_rmpc_bits ctx;
6117 };
6118
6119 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6120 u8 status[0x8];
6121 u8 reserved_at_8[0x18];
6122
6123 u8 syndrome[0x20];
6124
6125 u8 reserved_at_40[0x40];
6126 };
6127
6128 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6129 u8 reserved_at_0[0x12];
6130 u8 affiliation[0x1];
6131 u8 reserved_at_13[0x1];
6132 u8 disable_uc_local_lb[0x1];
6133 u8 disable_mc_local_lb[0x1];
6134 u8 node_guid[0x1];
6135 u8 port_guid[0x1];
6136 u8 min_inline[0x1];
6137 u8 mtu[0x1];
6138 u8 change_event[0x1];
6139 u8 promisc[0x1];
6140 u8 permanent_address[0x1];
6141 u8 addresses_list[0x1];
6142 u8 roce_en[0x1];
6143 u8 reserved_at_1f[0x1];
6144 };
6145
6146 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6147 u8 opcode[0x10];
6148 u8 reserved_at_10[0x10];
6149
6150 u8 reserved_at_20[0x10];
6151 u8 op_mod[0x10];
6152
6153 u8 other_vport[0x1];
6154 u8 reserved_at_41[0xf];
6155 u8 vport_number[0x10];
6156
6157 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6158
6159 u8 reserved_at_80[0x780];
6160
6161 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6162 };
6163
6164 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6165 u8 status[0x8];
6166 u8 reserved_at_8[0x18];
6167
6168 u8 syndrome[0x20];
6169
6170 u8 reserved_at_40[0x40];
6171 };
6172
6173 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6174 u8 opcode[0x10];
6175 u8 reserved_at_10[0x10];
6176
6177 u8 reserved_at_20[0x10];
6178 u8 op_mod[0x10];
6179
6180 u8 other_vport[0x1];
6181 u8 reserved_at_41[0xb];
6182 u8 port_num[0x4];
6183 u8 vport_number[0x10];
6184
6185 u8 reserved_at_60[0x20];
6186
6187 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6188 };
6189
6190 struct mlx5_ifc_modify_cq_out_bits {
6191 u8 status[0x8];
6192 u8 reserved_at_8[0x18];
6193
6194 u8 syndrome[0x20];
6195
6196 u8 reserved_at_40[0x40];
6197 };
6198
6199 enum {
6200 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6201 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6202 };
6203
6204 struct mlx5_ifc_modify_cq_in_bits {
6205 u8 opcode[0x10];
6206 u8 uid[0x10];
6207
6208 u8 reserved_at_20[0x10];
6209 u8 op_mod[0x10];
6210
6211 u8 reserved_at_40[0x8];
6212 u8 cqn[0x18];
6213
6214 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6215
6216 struct mlx5_ifc_cqc_bits cq_context;
6217
6218 u8 reserved_at_280[0x60];
6219
6220 u8 cq_umem_valid[0x1];
6221 u8 reserved_at_2e1[0x1f];
6222
6223 u8 reserved_at_300[0x580];
6224
6225 u8 pas[0][0x40];
6226 };
6227
6228 struct mlx5_ifc_modify_cong_status_out_bits {
6229 u8 status[0x8];
6230 u8 reserved_at_8[0x18];
6231
6232 u8 syndrome[0x20];
6233
6234 u8 reserved_at_40[0x40];
6235 };
6236
6237 struct mlx5_ifc_modify_cong_status_in_bits {
6238 u8 opcode[0x10];
6239 u8 reserved_at_10[0x10];
6240
6241 u8 reserved_at_20[0x10];
6242 u8 op_mod[0x10];
6243
6244 u8 reserved_at_40[0x18];
6245 u8 priority[0x4];
6246 u8 cong_protocol[0x4];
6247
6248 u8 enable[0x1];
6249 u8 tag_enable[0x1];
6250 u8 reserved_at_62[0x1e];
6251 };
6252
6253 struct mlx5_ifc_modify_cong_params_out_bits {
6254 u8 status[0x8];
6255 u8 reserved_at_8[0x18];
6256
6257 u8 syndrome[0x20];
6258
6259 u8 reserved_at_40[0x40];
6260 };
6261
6262 struct mlx5_ifc_modify_cong_params_in_bits {
6263 u8 opcode[0x10];
6264 u8 reserved_at_10[0x10];
6265
6266 u8 reserved_at_20[0x10];
6267 u8 op_mod[0x10];
6268
6269 u8 reserved_at_40[0x1c];
6270 u8 cong_protocol[0x4];
6271
6272 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6273
6274 u8 reserved_at_80[0x80];
6275
6276 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6277 };
6278
6279 struct mlx5_ifc_manage_pages_out_bits {
6280 u8 status[0x8];
6281 u8 reserved_at_8[0x18];
6282
6283 u8 syndrome[0x20];
6284
6285 u8 output_num_entries[0x20];
6286
6287 u8 reserved_at_60[0x20];
6288
6289 u8 pas[0][0x40];
6290 };
6291
6292 enum {
6293 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6294 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6295 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6296 };
6297
6298 struct mlx5_ifc_manage_pages_in_bits {
6299 u8 opcode[0x10];
6300 u8 reserved_at_10[0x10];
6301
6302 u8 reserved_at_20[0x10];
6303 u8 op_mod[0x10];
6304
6305 u8 embedded_cpu_function[0x1];
6306 u8 reserved_at_41[0xf];
6307 u8 function_id[0x10];
6308
6309 u8 input_num_entries[0x20];
6310
6311 u8 pas[0][0x40];
6312 };
6313
6314 struct mlx5_ifc_mad_ifc_out_bits {
6315 u8 status[0x8];
6316 u8 reserved_at_8[0x18];
6317
6318 u8 syndrome[0x20];
6319
6320 u8 reserved_at_40[0x40];
6321
6322 u8 response_mad_packet[256][0x8];
6323 };
6324
6325 struct mlx5_ifc_mad_ifc_in_bits {
6326 u8 opcode[0x10];
6327 u8 reserved_at_10[0x10];
6328
6329 u8 reserved_at_20[0x10];
6330 u8 op_mod[0x10];
6331
6332 u8 remote_lid[0x10];
6333 u8 reserved_at_50[0x8];
6334 u8 port[0x8];
6335
6336 u8 reserved_at_60[0x20];
6337
6338 u8 mad[256][0x8];
6339 };
6340
6341 struct mlx5_ifc_init_hca_out_bits {
6342 u8 status[0x8];
6343 u8 reserved_at_8[0x18];
6344
6345 u8 syndrome[0x20];
6346
6347 u8 reserved_at_40[0x40];
6348 };
6349
6350 struct mlx5_ifc_init_hca_in_bits {
6351 u8 opcode[0x10];
6352 u8 reserved_at_10[0x10];
6353
6354 u8 reserved_at_20[0x10];
6355 u8 op_mod[0x10];
6356
6357 u8 reserved_at_40[0x40];
6358 u8 sw_owner_id[4][0x20];
6359 };
6360
6361 struct mlx5_ifc_init2rtr_qp_out_bits {
6362 u8 status[0x8];
6363 u8 reserved_at_8[0x18];
6364
6365 u8 syndrome[0x20];
6366
6367 u8 reserved_at_40[0x40];
6368 };
6369
6370 struct mlx5_ifc_init2rtr_qp_in_bits {
6371 u8 opcode[0x10];
6372 u8 uid[0x10];
6373
6374 u8 reserved_at_20[0x10];
6375 u8 op_mod[0x10];
6376
6377 u8 reserved_at_40[0x8];
6378 u8 qpn[0x18];
6379
6380 u8 reserved_at_60[0x20];
6381
6382 u8 opt_param_mask[0x20];
6383
6384 u8 reserved_at_a0[0x20];
6385
6386 struct mlx5_ifc_qpc_bits qpc;
6387
6388 u8 reserved_at_800[0x80];
6389 };
6390
6391 struct mlx5_ifc_init2init_qp_out_bits {
6392 u8 status[0x8];
6393 u8 reserved_at_8[0x18];
6394
6395 u8 syndrome[0x20];
6396
6397 u8 reserved_at_40[0x40];
6398 };
6399
6400 struct mlx5_ifc_init2init_qp_in_bits {
6401 u8 opcode[0x10];
6402 u8 uid[0x10];
6403
6404 u8 reserved_at_20[0x10];
6405 u8 op_mod[0x10];
6406
6407 u8 reserved_at_40[0x8];
6408 u8 qpn[0x18];
6409
6410 u8 reserved_at_60[0x20];
6411
6412 u8 opt_param_mask[0x20];
6413
6414 u8 reserved_at_a0[0x20];
6415
6416 struct mlx5_ifc_qpc_bits qpc;
6417
6418 u8 reserved_at_800[0x80];
6419 };
6420
6421 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6422 u8 status[0x8];
6423 u8 reserved_at_8[0x18];
6424
6425 u8 syndrome[0x20];
6426
6427 u8 reserved_at_40[0x40];
6428
6429 u8 packet_headers_log[128][0x8];
6430
6431 u8 packet_syndrome[64][0x8];
6432 };
6433
6434 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6435 u8 opcode[0x10];
6436 u8 reserved_at_10[0x10];
6437
6438 u8 reserved_at_20[0x10];
6439 u8 op_mod[0x10];
6440
6441 u8 reserved_at_40[0x40];
6442 };
6443
6444 struct mlx5_ifc_gen_eqe_in_bits {
6445 u8 opcode[0x10];
6446 u8 reserved_at_10[0x10];
6447
6448 u8 reserved_at_20[0x10];
6449 u8 op_mod[0x10];
6450
6451 u8 reserved_at_40[0x18];
6452 u8 eq_number[0x8];
6453
6454 u8 reserved_at_60[0x20];
6455
6456 u8 eqe[64][0x8];
6457 };
6458
6459 struct mlx5_ifc_gen_eq_out_bits {
6460 u8 status[0x8];
6461 u8 reserved_at_8[0x18];
6462
6463 u8 syndrome[0x20];
6464
6465 u8 reserved_at_40[0x40];
6466 };
6467
6468 struct mlx5_ifc_enable_hca_out_bits {
6469 u8 status[0x8];
6470 u8 reserved_at_8[0x18];
6471
6472 u8 syndrome[0x20];
6473
6474 u8 reserved_at_40[0x20];
6475 };
6476
6477 struct mlx5_ifc_enable_hca_in_bits {
6478 u8 opcode[0x10];
6479 u8 reserved_at_10[0x10];
6480
6481 u8 reserved_at_20[0x10];
6482 u8 op_mod[0x10];
6483
6484 u8 embedded_cpu_function[0x1];
6485 u8 reserved_at_41[0xf];
6486 u8 function_id[0x10];
6487
6488 u8 reserved_at_60[0x20];
6489 };
6490
6491 struct mlx5_ifc_drain_dct_out_bits {
6492 u8 status[0x8];
6493 u8 reserved_at_8[0x18];
6494
6495 u8 syndrome[0x20];
6496
6497 u8 reserved_at_40[0x40];
6498 };
6499
6500 struct mlx5_ifc_drain_dct_in_bits {
6501 u8 opcode[0x10];
6502 u8 uid[0x10];
6503
6504 u8 reserved_at_20[0x10];
6505 u8 op_mod[0x10];
6506
6507 u8 reserved_at_40[0x8];
6508 u8 dctn[0x18];
6509
6510 u8 reserved_at_60[0x20];
6511 };
6512
6513 struct mlx5_ifc_disable_hca_out_bits {
6514 u8 status[0x8];
6515 u8 reserved_at_8[0x18];
6516
6517 u8 syndrome[0x20];
6518
6519 u8 reserved_at_40[0x20];
6520 };
6521
6522 struct mlx5_ifc_disable_hca_in_bits {
6523 u8 opcode[0x10];
6524 u8 reserved_at_10[0x10];
6525
6526 u8 reserved_at_20[0x10];
6527 u8 op_mod[0x10];
6528
6529 u8 embedded_cpu_function[0x1];
6530 u8 reserved_at_41[0xf];
6531 u8 function_id[0x10];
6532
6533 u8 reserved_at_60[0x20];
6534 };
6535
6536 struct mlx5_ifc_detach_from_mcg_out_bits {
6537 u8 status[0x8];
6538 u8 reserved_at_8[0x18];
6539
6540 u8 syndrome[0x20];
6541
6542 u8 reserved_at_40[0x40];
6543 };
6544
6545 struct mlx5_ifc_detach_from_mcg_in_bits {
6546 u8 opcode[0x10];
6547 u8 uid[0x10];
6548
6549 u8 reserved_at_20[0x10];
6550 u8 op_mod[0x10];
6551
6552 u8 reserved_at_40[0x8];
6553 u8 qpn[0x18];
6554
6555 u8 reserved_at_60[0x20];
6556
6557 u8 multicast_gid[16][0x8];
6558 };
6559
6560 struct mlx5_ifc_destroy_xrq_out_bits {
6561 u8 status[0x8];
6562 u8 reserved_at_8[0x18];
6563
6564 u8 syndrome[0x20];
6565
6566 u8 reserved_at_40[0x40];
6567 };
6568
6569 struct mlx5_ifc_destroy_xrq_in_bits {
6570 u8 opcode[0x10];
6571 u8 uid[0x10];
6572
6573 u8 reserved_at_20[0x10];
6574 u8 op_mod[0x10];
6575
6576 u8 reserved_at_40[0x8];
6577 u8 xrqn[0x18];
6578
6579 u8 reserved_at_60[0x20];
6580 };
6581
6582 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6583 u8 status[0x8];
6584 u8 reserved_at_8[0x18];
6585
6586 u8 syndrome[0x20];
6587
6588 u8 reserved_at_40[0x40];
6589 };
6590
6591 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6592 u8 opcode[0x10];
6593 u8 uid[0x10];
6594
6595 u8 reserved_at_20[0x10];
6596 u8 op_mod[0x10];
6597
6598 u8 reserved_at_40[0x8];
6599 u8 xrc_srqn[0x18];
6600
6601 u8 reserved_at_60[0x20];
6602 };
6603
6604 struct mlx5_ifc_destroy_tis_out_bits {
6605 u8 status[0x8];
6606 u8 reserved_at_8[0x18];
6607
6608 u8 syndrome[0x20];
6609
6610 u8 reserved_at_40[0x40];
6611 };
6612
6613 struct mlx5_ifc_destroy_tis_in_bits {
6614 u8 opcode[0x10];
6615 u8 uid[0x10];
6616
6617 u8 reserved_at_20[0x10];
6618 u8 op_mod[0x10];
6619
6620 u8 reserved_at_40[0x8];
6621 u8 tisn[0x18];
6622
6623 u8 reserved_at_60[0x20];
6624 };
6625
6626 struct mlx5_ifc_destroy_tir_out_bits {
6627 u8 status[0x8];
6628 u8 reserved_at_8[0x18];
6629
6630 u8 syndrome[0x20];
6631
6632 u8 reserved_at_40[0x40];
6633 };
6634
6635 struct mlx5_ifc_destroy_tir_in_bits {
6636 u8 opcode[0x10];
6637 u8 uid[0x10];
6638
6639 u8 reserved_at_20[0x10];
6640 u8 op_mod[0x10];
6641
6642 u8 reserved_at_40[0x8];
6643 u8 tirn[0x18];
6644
6645 u8 reserved_at_60[0x20];
6646 };
6647
6648 struct mlx5_ifc_destroy_srq_out_bits {
6649 u8 status[0x8];
6650 u8 reserved_at_8[0x18];
6651
6652 u8 syndrome[0x20];
6653
6654 u8 reserved_at_40[0x40];
6655 };
6656
6657 struct mlx5_ifc_destroy_srq_in_bits {
6658 u8 opcode[0x10];
6659 u8 uid[0x10];
6660
6661 u8 reserved_at_20[0x10];
6662 u8 op_mod[0x10];
6663
6664 u8 reserved_at_40[0x8];
6665 u8 srqn[0x18];
6666
6667 u8 reserved_at_60[0x20];
6668 };
6669
6670 struct mlx5_ifc_destroy_sq_out_bits {
6671 u8 status[0x8];
6672 u8 reserved_at_8[0x18];
6673
6674 u8 syndrome[0x20];
6675
6676 u8 reserved_at_40[0x40];
6677 };
6678
6679 struct mlx5_ifc_destroy_sq_in_bits {
6680 u8 opcode[0x10];
6681 u8 uid[0x10];
6682
6683 u8 reserved_at_20[0x10];
6684 u8 op_mod[0x10];
6685
6686 u8 reserved_at_40[0x8];
6687 u8 sqn[0x18];
6688
6689 u8 reserved_at_60[0x20];
6690 };
6691
6692 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6693 u8 status[0x8];
6694 u8 reserved_at_8[0x18];
6695
6696 u8 syndrome[0x20];
6697
6698 u8 reserved_at_40[0x1c0];
6699 };
6700
6701 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6702 u8 opcode[0x10];
6703 u8 reserved_at_10[0x10];
6704
6705 u8 reserved_at_20[0x10];
6706 u8 op_mod[0x10];
6707
6708 u8 scheduling_hierarchy[0x8];
6709 u8 reserved_at_48[0x18];
6710
6711 u8 scheduling_element_id[0x20];
6712
6713 u8 reserved_at_80[0x180];
6714 };
6715
6716 struct mlx5_ifc_destroy_rqt_out_bits {
6717 u8 status[0x8];
6718 u8 reserved_at_8[0x18];
6719
6720 u8 syndrome[0x20];
6721
6722 u8 reserved_at_40[0x40];
6723 };
6724
6725 struct mlx5_ifc_destroy_rqt_in_bits {
6726 u8 opcode[0x10];
6727 u8 uid[0x10];
6728
6729 u8 reserved_at_20[0x10];
6730 u8 op_mod[0x10];
6731
6732 u8 reserved_at_40[0x8];
6733 u8 rqtn[0x18];
6734
6735 u8 reserved_at_60[0x20];
6736 };
6737
6738 struct mlx5_ifc_destroy_rq_out_bits {
6739 u8 status[0x8];
6740 u8 reserved_at_8[0x18];
6741
6742 u8 syndrome[0x20];
6743
6744 u8 reserved_at_40[0x40];
6745 };
6746
6747 struct mlx5_ifc_destroy_rq_in_bits {
6748 u8 opcode[0x10];
6749 u8 uid[0x10];
6750
6751 u8 reserved_at_20[0x10];
6752 u8 op_mod[0x10];
6753
6754 u8 reserved_at_40[0x8];
6755 u8 rqn[0x18];
6756
6757 u8 reserved_at_60[0x20];
6758 };
6759
6760 struct mlx5_ifc_set_delay_drop_params_in_bits {
6761 u8 opcode[0x10];
6762 u8 reserved_at_10[0x10];
6763
6764 u8 reserved_at_20[0x10];
6765 u8 op_mod[0x10];
6766
6767 u8 reserved_at_40[0x20];
6768
6769 u8 reserved_at_60[0x10];
6770 u8 delay_drop_timeout[0x10];
6771 };
6772
6773 struct mlx5_ifc_set_delay_drop_params_out_bits {
6774 u8 status[0x8];
6775 u8 reserved_at_8[0x18];
6776
6777 u8 syndrome[0x20];
6778
6779 u8 reserved_at_40[0x40];
6780 };
6781
6782 struct mlx5_ifc_destroy_rmp_out_bits {
6783 u8 status[0x8];
6784 u8 reserved_at_8[0x18];
6785
6786 u8 syndrome[0x20];
6787
6788 u8 reserved_at_40[0x40];
6789 };
6790
6791 struct mlx5_ifc_destroy_rmp_in_bits {
6792 u8 opcode[0x10];
6793 u8 uid[0x10];
6794
6795 u8 reserved_at_20[0x10];
6796 u8 op_mod[0x10];
6797
6798 u8 reserved_at_40[0x8];
6799 u8 rmpn[0x18];
6800
6801 u8 reserved_at_60[0x20];
6802 };
6803
6804 struct mlx5_ifc_destroy_qp_out_bits {
6805 u8 status[0x8];
6806 u8 reserved_at_8[0x18];
6807
6808 u8 syndrome[0x20];
6809
6810 u8 reserved_at_40[0x40];
6811 };
6812
6813 struct mlx5_ifc_destroy_qp_in_bits {
6814 u8 opcode[0x10];
6815 u8 uid[0x10];
6816
6817 u8 reserved_at_20[0x10];
6818 u8 op_mod[0x10];
6819
6820 u8 reserved_at_40[0x8];
6821 u8 qpn[0x18];
6822
6823 u8 reserved_at_60[0x20];
6824 };
6825
6826 struct mlx5_ifc_destroy_psv_out_bits {
6827 u8 status[0x8];
6828 u8 reserved_at_8[0x18];
6829
6830 u8 syndrome[0x20];
6831
6832 u8 reserved_at_40[0x40];
6833 };
6834
6835 struct mlx5_ifc_destroy_psv_in_bits {
6836 u8 opcode[0x10];
6837 u8 reserved_at_10[0x10];
6838
6839 u8 reserved_at_20[0x10];
6840 u8 op_mod[0x10];
6841
6842 u8 reserved_at_40[0x8];
6843 u8 psvn[0x18];
6844
6845 u8 reserved_at_60[0x20];
6846 };
6847
6848 struct mlx5_ifc_destroy_mkey_out_bits {
6849 u8 status[0x8];
6850 u8 reserved_at_8[0x18];
6851
6852 u8 syndrome[0x20];
6853
6854 u8 reserved_at_40[0x40];
6855 };
6856
6857 struct mlx5_ifc_destroy_mkey_in_bits {
6858 u8 opcode[0x10];
6859 u8 reserved_at_10[0x10];
6860
6861 u8 reserved_at_20[0x10];
6862 u8 op_mod[0x10];
6863
6864 u8 reserved_at_40[0x8];
6865 u8 mkey_index[0x18];
6866
6867 u8 reserved_at_60[0x20];
6868 };
6869
6870 struct mlx5_ifc_destroy_flow_table_out_bits {
6871 u8 status[0x8];
6872 u8 reserved_at_8[0x18];
6873
6874 u8 syndrome[0x20];
6875
6876 u8 reserved_at_40[0x40];
6877 };
6878
6879 struct mlx5_ifc_destroy_flow_table_in_bits {
6880 u8 opcode[0x10];
6881 u8 reserved_at_10[0x10];
6882
6883 u8 reserved_at_20[0x10];
6884 u8 op_mod[0x10];
6885
6886 u8 other_vport[0x1];
6887 u8 reserved_at_41[0xf];
6888 u8 vport_number[0x10];
6889
6890 u8 reserved_at_60[0x20];
6891
6892 u8 table_type[0x8];
6893 u8 reserved_at_88[0x18];
6894
6895 u8 reserved_at_a0[0x8];
6896 u8 table_id[0x18];
6897
6898 u8 reserved_at_c0[0x140];
6899 };
6900
6901 struct mlx5_ifc_destroy_flow_group_out_bits {
6902 u8 status[0x8];
6903 u8 reserved_at_8[0x18];
6904
6905 u8 syndrome[0x20];
6906
6907 u8 reserved_at_40[0x40];
6908 };
6909
6910 struct mlx5_ifc_destroy_flow_group_in_bits {
6911 u8 opcode[0x10];
6912 u8 reserved_at_10[0x10];
6913
6914 u8 reserved_at_20[0x10];
6915 u8 op_mod[0x10];
6916
6917 u8 other_vport[0x1];
6918 u8 reserved_at_41[0xf];
6919 u8 vport_number[0x10];
6920
6921 u8 reserved_at_60[0x20];
6922
6923 u8 table_type[0x8];
6924 u8 reserved_at_88[0x18];
6925
6926 u8 reserved_at_a0[0x8];
6927 u8 table_id[0x18];
6928
6929 u8 group_id[0x20];
6930
6931 u8 reserved_at_e0[0x120];
6932 };
6933
6934 struct mlx5_ifc_destroy_eq_out_bits {
6935 u8 status[0x8];
6936 u8 reserved_at_8[0x18];
6937
6938 u8 syndrome[0x20];
6939
6940 u8 reserved_at_40[0x40];
6941 };
6942
6943 struct mlx5_ifc_destroy_eq_in_bits {
6944 u8 opcode[0x10];
6945 u8 reserved_at_10[0x10];
6946
6947 u8 reserved_at_20[0x10];
6948 u8 op_mod[0x10];
6949
6950 u8 reserved_at_40[0x18];
6951 u8 eq_number[0x8];
6952
6953 u8 reserved_at_60[0x20];
6954 };
6955
6956 struct mlx5_ifc_destroy_dct_out_bits {
6957 u8 status[0x8];
6958 u8 reserved_at_8[0x18];
6959
6960 u8 syndrome[0x20];
6961
6962 u8 reserved_at_40[0x40];
6963 };
6964
6965 struct mlx5_ifc_destroy_dct_in_bits {
6966 u8 opcode[0x10];
6967 u8 uid[0x10];
6968
6969 u8 reserved_at_20[0x10];
6970 u8 op_mod[0x10];
6971
6972 u8 reserved_at_40[0x8];
6973 u8 dctn[0x18];
6974
6975 u8 reserved_at_60[0x20];
6976 };
6977
6978 struct mlx5_ifc_destroy_cq_out_bits {
6979 u8 status[0x8];
6980 u8 reserved_at_8[0x18];
6981
6982 u8 syndrome[0x20];
6983
6984 u8 reserved_at_40[0x40];
6985 };
6986
6987 struct mlx5_ifc_destroy_cq_in_bits {
6988 u8 opcode[0x10];
6989 u8 uid[0x10];
6990
6991 u8 reserved_at_20[0x10];
6992 u8 op_mod[0x10];
6993
6994 u8 reserved_at_40[0x8];
6995 u8 cqn[0x18];
6996
6997 u8 reserved_at_60[0x20];
6998 };
6999
7000 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7001 u8 status[0x8];
7002 u8 reserved_at_8[0x18];
7003
7004 u8 syndrome[0x20];
7005
7006 u8 reserved_at_40[0x40];
7007 };
7008
7009 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7010 u8 opcode[0x10];
7011 u8 reserved_at_10[0x10];
7012
7013 u8 reserved_at_20[0x10];
7014 u8 op_mod[0x10];
7015
7016 u8 reserved_at_40[0x20];
7017
7018 u8 reserved_at_60[0x10];
7019 u8 vxlan_udp_port[0x10];
7020 };
7021
7022 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7023 u8 status[0x8];
7024 u8 reserved_at_8[0x18];
7025
7026 u8 syndrome[0x20];
7027
7028 u8 reserved_at_40[0x40];
7029 };
7030
7031 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7032 u8 opcode[0x10];
7033 u8 reserved_at_10[0x10];
7034
7035 u8 reserved_at_20[0x10];
7036 u8 op_mod[0x10];
7037
7038 u8 reserved_at_40[0x60];
7039
7040 u8 reserved_at_a0[0x8];
7041 u8 table_index[0x18];
7042
7043 u8 reserved_at_c0[0x140];
7044 };
7045
7046 struct mlx5_ifc_delete_fte_out_bits {
7047 u8 status[0x8];
7048 u8 reserved_at_8[0x18];
7049
7050 u8 syndrome[0x20];
7051
7052 u8 reserved_at_40[0x40];
7053 };
7054
7055 struct mlx5_ifc_delete_fte_in_bits {
7056 u8 opcode[0x10];
7057 u8 reserved_at_10[0x10];
7058
7059 u8 reserved_at_20[0x10];
7060 u8 op_mod[0x10];
7061
7062 u8 other_vport[0x1];
7063 u8 reserved_at_41[0xf];
7064 u8 vport_number[0x10];
7065
7066 u8 reserved_at_60[0x20];
7067
7068 u8 table_type[0x8];
7069 u8 reserved_at_88[0x18];
7070
7071 u8 reserved_at_a0[0x8];
7072 u8 table_id[0x18];
7073
7074 u8 reserved_at_c0[0x40];
7075
7076 u8 flow_index[0x20];
7077
7078 u8 reserved_at_120[0xe0];
7079 };
7080
7081 struct mlx5_ifc_dealloc_xrcd_out_bits {
7082 u8 status[0x8];
7083 u8 reserved_at_8[0x18];
7084
7085 u8 syndrome[0x20];
7086
7087 u8 reserved_at_40[0x40];
7088 };
7089
7090 struct mlx5_ifc_dealloc_xrcd_in_bits {
7091 u8 opcode[0x10];
7092 u8 uid[0x10];
7093
7094 u8 reserved_at_20[0x10];
7095 u8 op_mod[0x10];
7096
7097 u8 reserved_at_40[0x8];
7098 u8 xrcd[0x18];
7099
7100 u8 reserved_at_60[0x20];
7101 };
7102
7103 struct mlx5_ifc_dealloc_uar_out_bits {
7104 u8 status[0x8];
7105 u8 reserved_at_8[0x18];
7106
7107 u8 syndrome[0x20];
7108
7109 u8 reserved_at_40[0x40];
7110 };
7111
7112 struct mlx5_ifc_dealloc_uar_in_bits {
7113 u8 opcode[0x10];
7114 u8 reserved_at_10[0x10];
7115
7116 u8 reserved_at_20[0x10];
7117 u8 op_mod[0x10];
7118
7119 u8 reserved_at_40[0x8];
7120 u8 uar[0x18];
7121
7122 u8 reserved_at_60[0x20];
7123 };
7124
7125 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7126 u8 status[0x8];
7127 u8 reserved_at_8[0x18];
7128
7129 u8 syndrome[0x20];
7130
7131 u8 reserved_at_40[0x40];
7132 };
7133
7134 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7135 u8 opcode[0x10];
7136 u8 uid[0x10];
7137
7138 u8 reserved_at_20[0x10];
7139 u8 op_mod[0x10];
7140
7141 u8 reserved_at_40[0x8];
7142 u8 transport_domain[0x18];
7143
7144 u8 reserved_at_60[0x20];
7145 };
7146
7147 struct mlx5_ifc_dealloc_q_counter_out_bits {
7148 u8 status[0x8];
7149 u8 reserved_at_8[0x18];
7150
7151 u8 syndrome[0x20];
7152
7153 u8 reserved_at_40[0x40];
7154 };
7155
7156 struct mlx5_ifc_dealloc_q_counter_in_bits {
7157 u8 opcode[0x10];
7158 u8 reserved_at_10[0x10];
7159
7160 u8 reserved_at_20[0x10];
7161 u8 op_mod[0x10];
7162
7163 u8 reserved_at_40[0x18];
7164 u8 counter_set_id[0x8];
7165
7166 u8 reserved_at_60[0x20];
7167 };
7168
7169 struct mlx5_ifc_dealloc_pd_out_bits {
7170 u8 status[0x8];
7171 u8 reserved_at_8[0x18];
7172
7173 u8 syndrome[0x20];
7174
7175 u8 reserved_at_40[0x40];
7176 };
7177
7178 struct mlx5_ifc_dealloc_pd_in_bits {
7179 u8 opcode[0x10];
7180 u8 uid[0x10];
7181
7182 u8 reserved_at_20[0x10];
7183 u8 op_mod[0x10];
7184
7185 u8 reserved_at_40[0x8];
7186 u8 pd[0x18];
7187
7188 u8 reserved_at_60[0x20];
7189 };
7190
7191 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7192 u8 status[0x8];
7193 u8 reserved_at_8[0x18];
7194
7195 u8 syndrome[0x20];
7196
7197 u8 reserved_at_40[0x40];
7198 };
7199
7200 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7201 u8 opcode[0x10];
7202 u8 reserved_at_10[0x10];
7203
7204 u8 reserved_at_20[0x10];
7205 u8 op_mod[0x10];
7206
7207 u8 flow_counter_id[0x20];
7208
7209 u8 reserved_at_60[0x20];
7210 };
7211
7212 struct mlx5_ifc_create_xrq_out_bits {
7213 u8 status[0x8];
7214 u8 reserved_at_8[0x18];
7215
7216 u8 syndrome[0x20];
7217
7218 u8 reserved_at_40[0x8];
7219 u8 xrqn[0x18];
7220
7221 u8 reserved_at_60[0x20];
7222 };
7223
7224 struct mlx5_ifc_create_xrq_in_bits {
7225 u8 opcode[0x10];
7226 u8 uid[0x10];
7227
7228 u8 reserved_at_20[0x10];
7229 u8 op_mod[0x10];
7230
7231 u8 reserved_at_40[0x40];
7232
7233 struct mlx5_ifc_xrqc_bits xrq_context;
7234 };
7235
7236 struct mlx5_ifc_create_xrc_srq_out_bits {
7237 u8 status[0x8];
7238 u8 reserved_at_8[0x18];
7239
7240 u8 syndrome[0x20];
7241
7242 u8 reserved_at_40[0x8];
7243 u8 xrc_srqn[0x18];
7244
7245 u8 reserved_at_60[0x20];
7246 };
7247
7248 struct mlx5_ifc_create_xrc_srq_in_bits {
7249 u8 opcode[0x10];
7250 u8 uid[0x10];
7251
7252 u8 reserved_at_20[0x10];
7253 u8 op_mod[0x10];
7254
7255 u8 reserved_at_40[0x40];
7256
7257 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7258
7259 u8 reserved_at_280[0x60];
7260
7261 u8 xrc_srq_umem_valid[0x1];
7262 u8 reserved_at_2e1[0x1f];
7263
7264 u8 reserved_at_300[0x580];
7265
7266 u8 pas[0][0x40];
7267 };
7268
7269 struct mlx5_ifc_create_tis_out_bits {
7270 u8 status[0x8];
7271 u8 reserved_at_8[0x18];
7272
7273 u8 syndrome[0x20];
7274
7275 u8 reserved_at_40[0x8];
7276 u8 tisn[0x18];
7277
7278 u8 reserved_at_60[0x20];
7279 };
7280
7281 struct mlx5_ifc_create_tis_in_bits {
7282 u8 opcode[0x10];
7283 u8 uid[0x10];
7284
7285 u8 reserved_at_20[0x10];
7286 u8 op_mod[0x10];
7287
7288 u8 reserved_at_40[0xc0];
7289
7290 struct mlx5_ifc_tisc_bits ctx;
7291 };
7292
7293 struct mlx5_ifc_create_tir_out_bits {
7294 u8 status[0x8];
7295 u8 icm_address_63_40[0x18];
7296
7297 u8 syndrome[0x20];
7298
7299 u8 icm_address_39_32[0x8];
7300 u8 tirn[0x18];
7301
7302 u8 icm_address_31_0[0x20];
7303 };
7304
7305 struct mlx5_ifc_create_tir_in_bits {
7306 u8 opcode[0x10];
7307 u8 uid[0x10];
7308
7309 u8 reserved_at_20[0x10];
7310 u8 op_mod[0x10];
7311
7312 u8 reserved_at_40[0xc0];
7313
7314 struct mlx5_ifc_tirc_bits ctx;
7315 };
7316
7317 struct mlx5_ifc_create_srq_out_bits {
7318 u8 status[0x8];
7319 u8 reserved_at_8[0x18];
7320
7321 u8 syndrome[0x20];
7322
7323 u8 reserved_at_40[0x8];
7324 u8 srqn[0x18];
7325
7326 u8 reserved_at_60[0x20];
7327 };
7328
7329 struct mlx5_ifc_create_srq_in_bits {
7330 u8 opcode[0x10];
7331 u8 uid[0x10];
7332
7333 u8 reserved_at_20[0x10];
7334 u8 op_mod[0x10];
7335
7336 u8 reserved_at_40[0x40];
7337
7338 struct mlx5_ifc_srqc_bits srq_context_entry;
7339
7340 u8 reserved_at_280[0x600];
7341
7342 u8 pas[0][0x40];
7343 };
7344
7345 struct mlx5_ifc_create_sq_out_bits {
7346 u8 status[0x8];
7347 u8 reserved_at_8[0x18];
7348
7349 u8 syndrome[0x20];
7350
7351 u8 reserved_at_40[0x8];
7352 u8 sqn[0x18];
7353
7354 u8 reserved_at_60[0x20];
7355 };
7356
7357 struct mlx5_ifc_create_sq_in_bits {
7358 u8 opcode[0x10];
7359 u8 uid[0x10];
7360
7361 u8 reserved_at_20[0x10];
7362 u8 op_mod[0x10];
7363
7364 u8 reserved_at_40[0xc0];
7365
7366 struct mlx5_ifc_sqc_bits ctx;
7367 };
7368
7369 struct mlx5_ifc_create_scheduling_element_out_bits {
7370 u8 status[0x8];
7371 u8 reserved_at_8[0x18];
7372
7373 u8 syndrome[0x20];
7374
7375 u8 reserved_at_40[0x40];
7376
7377 u8 scheduling_element_id[0x20];
7378
7379 u8 reserved_at_a0[0x160];
7380 };
7381
7382 struct mlx5_ifc_create_scheduling_element_in_bits {
7383 u8 opcode[0x10];
7384 u8 reserved_at_10[0x10];
7385
7386 u8 reserved_at_20[0x10];
7387 u8 op_mod[0x10];
7388
7389 u8 scheduling_hierarchy[0x8];
7390 u8 reserved_at_48[0x18];
7391
7392 u8 reserved_at_60[0xa0];
7393
7394 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7395
7396 u8 reserved_at_300[0x100];
7397 };
7398
7399 struct mlx5_ifc_create_rqt_out_bits {
7400 u8 status[0x8];
7401 u8 reserved_at_8[0x18];
7402
7403 u8 syndrome[0x20];
7404
7405 u8 reserved_at_40[0x8];
7406 u8 rqtn[0x18];
7407
7408 u8 reserved_at_60[0x20];
7409 };
7410
7411 struct mlx5_ifc_create_rqt_in_bits {
7412 u8 opcode[0x10];
7413 u8 uid[0x10];
7414
7415 u8 reserved_at_20[0x10];
7416 u8 op_mod[0x10];
7417
7418 u8 reserved_at_40[0xc0];
7419
7420 struct mlx5_ifc_rqtc_bits rqt_context;
7421 };
7422
7423 struct mlx5_ifc_create_rq_out_bits {
7424 u8 status[0x8];
7425 u8 reserved_at_8[0x18];
7426
7427 u8 syndrome[0x20];
7428
7429 u8 reserved_at_40[0x8];
7430 u8 rqn[0x18];
7431
7432 u8 reserved_at_60[0x20];
7433 };
7434
7435 struct mlx5_ifc_create_rq_in_bits {
7436 u8 opcode[0x10];
7437 u8 uid[0x10];
7438
7439 u8 reserved_at_20[0x10];
7440 u8 op_mod[0x10];
7441
7442 u8 reserved_at_40[0xc0];
7443
7444 struct mlx5_ifc_rqc_bits ctx;
7445 };
7446
7447 struct mlx5_ifc_create_rmp_out_bits {
7448 u8 status[0x8];
7449 u8 reserved_at_8[0x18];
7450
7451 u8 syndrome[0x20];
7452
7453 u8 reserved_at_40[0x8];
7454 u8 rmpn[0x18];
7455
7456 u8 reserved_at_60[0x20];
7457 };
7458
7459 struct mlx5_ifc_create_rmp_in_bits {
7460 u8 opcode[0x10];
7461 u8 uid[0x10];
7462
7463 u8 reserved_at_20[0x10];
7464 u8 op_mod[0x10];
7465
7466 u8 reserved_at_40[0xc0];
7467
7468 struct mlx5_ifc_rmpc_bits ctx;
7469 };
7470
7471 struct mlx5_ifc_create_qp_out_bits {
7472 u8 status[0x8];
7473 u8 reserved_at_8[0x18];
7474
7475 u8 syndrome[0x20];
7476
7477 u8 reserved_at_40[0x8];
7478 u8 qpn[0x18];
7479
7480 u8 reserved_at_60[0x20];
7481 };
7482
7483 struct mlx5_ifc_create_qp_in_bits {
7484 u8 opcode[0x10];
7485 u8 uid[0x10];
7486
7487 u8 reserved_at_20[0x10];
7488 u8 op_mod[0x10];
7489
7490 u8 reserved_at_40[0x40];
7491
7492 u8 opt_param_mask[0x20];
7493
7494 u8 reserved_at_a0[0x20];
7495
7496 struct mlx5_ifc_qpc_bits qpc;
7497
7498 u8 reserved_at_800[0x60];
7499
7500 u8 wq_umem_valid[0x1];
7501 u8 reserved_at_861[0x1f];
7502
7503 u8 pas[0][0x40];
7504 };
7505
7506 struct mlx5_ifc_create_psv_out_bits {
7507 u8 status[0x8];
7508 u8 reserved_at_8[0x18];
7509
7510 u8 syndrome[0x20];
7511
7512 u8 reserved_at_40[0x40];
7513
7514 u8 reserved_at_80[0x8];
7515 u8 psv0_index[0x18];
7516
7517 u8 reserved_at_a0[0x8];
7518 u8 psv1_index[0x18];
7519
7520 u8 reserved_at_c0[0x8];
7521 u8 psv2_index[0x18];
7522
7523 u8 reserved_at_e0[0x8];
7524 u8 psv3_index[0x18];
7525 };
7526
7527 struct mlx5_ifc_create_psv_in_bits {
7528 u8 opcode[0x10];
7529 u8 reserved_at_10[0x10];
7530
7531 u8 reserved_at_20[0x10];
7532 u8 op_mod[0x10];
7533
7534 u8 num_psv[0x4];
7535 u8 reserved_at_44[0x4];
7536 u8 pd[0x18];
7537
7538 u8 reserved_at_60[0x20];
7539 };
7540
7541 struct mlx5_ifc_create_mkey_out_bits {
7542 u8 status[0x8];
7543 u8 reserved_at_8[0x18];
7544
7545 u8 syndrome[0x20];
7546
7547 u8 reserved_at_40[0x8];
7548 u8 mkey_index[0x18];
7549
7550 u8 reserved_at_60[0x20];
7551 };
7552
7553 struct mlx5_ifc_create_mkey_in_bits {
7554 u8 opcode[0x10];
7555 u8 reserved_at_10[0x10];
7556
7557 u8 reserved_at_20[0x10];
7558 u8 op_mod[0x10];
7559
7560 u8 reserved_at_40[0x20];
7561
7562 u8 pg_access[0x1];
7563 u8 mkey_umem_valid[0x1];
7564 u8 reserved_at_62[0x1e];
7565
7566 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7567
7568 u8 reserved_at_280[0x80];
7569
7570 u8 translations_octword_actual_size[0x20];
7571
7572 u8 reserved_at_320[0x560];
7573
7574 u8 klm_pas_mtt[0][0x20];
7575 };
7576
7577 enum {
7578 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7579 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7580 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7581 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7582 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7583 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7584 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7585 };
7586
7587 struct mlx5_ifc_create_flow_table_out_bits {
7588 u8 status[0x8];
7589 u8 icm_address_63_40[0x18];
7590
7591 u8 syndrome[0x20];
7592
7593 u8 icm_address_39_32[0x8];
7594 u8 table_id[0x18];
7595
7596 u8 icm_address_31_0[0x20];
7597 };
7598
7599 struct mlx5_ifc_create_flow_table_in_bits {
7600 u8 opcode[0x10];
7601 u8 reserved_at_10[0x10];
7602
7603 u8 reserved_at_20[0x10];
7604 u8 op_mod[0x10];
7605
7606 u8 other_vport[0x1];
7607 u8 reserved_at_41[0xf];
7608 u8 vport_number[0x10];
7609
7610 u8 reserved_at_60[0x20];
7611
7612 u8 table_type[0x8];
7613 u8 reserved_at_88[0x18];
7614
7615 u8 reserved_at_a0[0x20];
7616
7617 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7618 };
7619
7620 struct mlx5_ifc_create_flow_group_out_bits {
7621 u8 status[0x8];
7622 u8 reserved_at_8[0x18];
7623
7624 u8 syndrome[0x20];
7625
7626 u8 reserved_at_40[0x8];
7627 u8 group_id[0x18];
7628
7629 u8 reserved_at_60[0x20];
7630 };
7631
7632 enum {
7633 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7634 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7635 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7636 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7637 };
7638
7639 struct mlx5_ifc_create_flow_group_in_bits {
7640 u8 opcode[0x10];
7641 u8 reserved_at_10[0x10];
7642
7643 u8 reserved_at_20[0x10];
7644 u8 op_mod[0x10];
7645
7646 u8 other_vport[0x1];
7647 u8 reserved_at_41[0xf];
7648 u8 vport_number[0x10];
7649
7650 u8 reserved_at_60[0x20];
7651
7652 u8 table_type[0x8];
7653 u8 reserved_at_88[0x18];
7654
7655 u8 reserved_at_a0[0x8];
7656 u8 table_id[0x18];
7657
7658 u8 source_eswitch_owner_vhca_id_valid[0x1];
7659
7660 u8 reserved_at_c1[0x1f];
7661
7662 u8 start_flow_index[0x20];
7663
7664 u8 reserved_at_100[0x20];
7665
7666 u8 end_flow_index[0x20];
7667
7668 u8 reserved_at_140[0xa0];
7669
7670 u8 reserved_at_1e0[0x18];
7671 u8 match_criteria_enable[0x8];
7672
7673 struct mlx5_ifc_fte_match_param_bits match_criteria;
7674
7675 u8 reserved_at_1200[0xe00];
7676 };
7677
7678 struct mlx5_ifc_create_eq_out_bits {
7679 u8 status[0x8];
7680 u8 reserved_at_8[0x18];
7681
7682 u8 syndrome[0x20];
7683
7684 u8 reserved_at_40[0x18];
7685 u8 eq_number[0x8];
7686
7687 u8 reserved_at_60[0x20];
7688 };
7689
7690 struct mlx5_ifc_create_eq_in_bits {
7691 u8 opcode[0x10];
7692 u8 uid[0x10];
7693
7694 u8 reserved_at_20[0x10];
7695 u8 op_mod[0x10];
7696
7697 u8 reserved_at_40[0x40];
7698
7699 struct mlx5_ifc_eqc_bits eq_context_entry;
7700
7701 u8 reserved_at_280[0x40];
7702
7703 u8 event_bitmask[4][0x40];
7704
7705 u8 reserved_at_3c0[0x4c0];
7706
7707 u8 pas[0][0x40];
7708 };
7709
7710 struct mlx5_ifc_create_dct_out_bits {
7711 u8 status[0x8];
7712 u8 reserved_at_8[0x18];
7713
7714 u8 syndrome[0x20];
7715
7716 u8 reserved_at_40[0x8];
7717 u8 dctn[0x18];
7718
7719 u8 reserved_at_60[0x20];
7720 };
7721
7722 struct mlx5_ifc_create_dct_in_bits {
7723 u8 opcode[0x10];
7724 u8 uid[0x10];
7725
7726 u8 reserved_at_20[0x10];
7727 u8 op_mod[0x10];
7728
7729 u8 reserved_at_40[0x40];
7730
7731 struct mlx5_ifc_dctc_bits dct_context_entry;
7732
7733 u8 reserved_at_280[0x180];
7734 };
7735
7736 struct mlx5_ifc_create_cq_out_bits {
7737 u8 status[0x8];
7738 u8 reserved_at_8[0x18];
7739
7740 u8 syndrome[0x20];
7741
7742 u8 reserved_at_40[0x8];
7743 u8 cqn[0x18];
7744
7745 u8 reserved_at_60[0x20];
7746 };
7747
7748 struct mlx5_ifc_create_cq_in_bits {
7749 u8 opcode[0x10];
7750 u8 uid[0x10];
7751
7752 u8 reserved_at_20[0x10];
7753 u8 op_mod[0x10];
7754
7755 u8 reserved_at_40[0x40];
7756
7757 struct mlx5_ifc_cqc_bits cq_context;
7758
7759 u8 reserved_at_280[0x60];
7760
7761 u8 cq_umem_valid[0x1];
7762 u8 reserved_at_2e1[0x59f];
7763
7764 u8 pas[0][0x40];
7765 };
7766
7767 struct mlx5_ifc_config_int_moderation_out_bits {
7768 u8 status[0x8];
7769 u8 reserved_at_8[0x18];
7770
7771 u8 syndrome[0x20];
7772
7773 u8 reserved_at_40[0x4];
7774 u8 min_delay[0xc];
7775 u8 int_vector[0x10];
7776
7777 u8 reserved_at_60[0x20];
7778 };
7779
7780 enum {
7781 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7782 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7783 };
7784
7785 struct mlx5_ifc_config_int_moderation_in_bits {
7786 u8 opcode[0x10];
7787 u8 reserved_at_10[0x10];
7788
7789 u8 reserved_at_20[0x10];
7790 u8 op_mod[0x10];
7791
7792 u8 reserved_at_40[0x4];
7793 u8 min_delay[0xc];
7794 u8 int_vector[0x10];
7795
7796 u8 reserved_at_60[0x20];
7797 };
7798
7799 struct mlx5_ifc_attach_to_mcg_out_bits {
7800 u8 status[0x8];
7801 u8 reserved_at_8[0x18];
7802
7803 u8 syndrome[0x20];
7804
7805 u8 reserved_at_40[0x40];
7806 };
7807
7808 struct mlx5_ifc_attach_to_mcg_in_bits {
7809 u8 opcode[0x10];
7810 u8 uid[0x10];
7811
7812 u8 reserved_at_20[0x10];
7813 u8 op_mod[0x10];
7814
7815 u8 reserved_at_40[0x8];
7816 u8 qpn[0x18];
7817
7818 u8 reserved_at_60[0x20];
7819
7820 u8 multicast_gid[16][0x8];
7821 };
7822
7823 struct mlx5_ifc_arm_xrq_out_bits {
7824 u8 status[0x8];
7825 u8 reserved_at_8[0x18];
7826
7827 u8 syndrome[0x20];
7828
7829 u8 reserved_at_40[0x40];
7830 };
7831
7832 struct mlx5_ifc_arm_xrq_in_bits {
7833 u8 opcode[0x10];
7834 u8 reserved_at_10[0x10];
7835
7836 u8 reserved_at_20[0x10];
7837 u8 op_mod[0x10];
7838
7839 u8 reserved_at_40[0x8];
7840 u8 xrqn[0x18];
7841
7842 u8 reserved_at_60[0x10];
7843 u8 lwm[0x10];
7844 };
7845
7846 struct mlx5_ifc_arm_xrc_srq_out_bits {
7847 u8 status[0x8];
7848 u8 reserved_at_8[0x18];
7849
7850 u8 syndrome[0x20];
7851
7852 u8 reserved_at_40[0x40];
7853 };
7854
7855 enum {
7856 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7857 };
7858
7859 struct mlx5_ifc_arm_xrc_srq_in_bits {
7860 u8 opcode[0x10];
7861 u8 uid[0x10];
7862
7863 u8 reserved_at_20[0x10];
7864 u8 op_mod[0x10];
7865
7866 u8 reserved_at_40[0x8];
7867 u8 xrc_srqn[0x18];
7868
7869 u8 reserved_at_60[0x10];
7870 u8 lwm[0x10];
7871 };
7872
7873 struct mlx5_ifc_arm_rq_out_bits {
7874 u8 status[0x8];
7875 u8 reserved_at_8[0x18];
7876
7877 u8 syndrome[0x20];
7878
7879 u8 reserved_at_40[0x40];
7880 };
7881
7882 enum {
7883 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7884 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7885 };
7886
7887 struct mlx5_ifc_arm_rq_in_bits {
7888 u8 opcode[0x10];
7889 u8 uid[0x10];
7890
7891 u8 reserved_at_20[0x10];
7892 u8 op_mod[0x10];
7893
7894 u8 reserved_at_40[0x8];
7895 u8 srq_number[0x18];
7896
7897 u8 reserved_at_60[0x10];
7898 u8 lwm[0x10];
7899 };
7900
7901 struct mlx5_ifc_arm_dct_out_bits {
7902 u8 status[0x8];
7903 u8 reserved_at_8[0x18];
7904
7905 u8 syndrome[0x20];
7906
7907 u8 reserved_at_40[0x40];
7908 };
7909
7910 struct mlx5_ifc_arm_dct_in_bits {
7911 u8 opcode[0x10];
7912 u8 reserved_at_10[0x10];
7913
7914 u8 reserved_at_20[0x10];
7915 u8 op_mod[0x10];
7916
7917 u8 reserved_at_40[0x8];
7918 u8 dct_number[0x18];
7919
7920 u8 reserved_at_60[0x20];
7921 };
7922
7923 struct mlx5_ifc_alloc_xrcd_out_bits {
7924 u8 status[0x8];
7925 u8 reserved_at_8[0x18];
7926
7927 u8 syndrome[0x20];
7928
7929 u8 reserved_at_40[0x8];
7930 u8 xrcd[0x18];
7931
7932 u8 reserved_at_60[0x20];
7933 };
7934
7935 struct mlx5_ifc_alloc_xrcd_in_bits {
7936 u8 opcode[0x10];
7937 u8 uid[0x10];
7938
7939 u8 reserved_at_20[0x10];
7940 u8 op_mod[0x10];
7941
7942 u8 reserved_at_40[0x40];
7943 };
7944
7945 struct mlx5_ifc_alloc_uar_out_bits {
7946 u8 status[0x8];
7947 u8 reserved_at_8[0x18];
7948
7949 u8 syndrome[0x20];
7950
7951 u8 reserved_at_40[0x8];
7952 u8 uar[0x18];
7953
7954 u8 reserved_at_60[0x20];
7955 };
7956
7957 struct mlx5_ifc_alloc_uar_in_bits {
7958 u8 opcode[0x10];
7959 u8 reserved_at_10[0x10];
7960
7961 u8 reserved_at_20[0x10];
7962 u8 op_mod[0x10];
7963
7964 u8 reserved_at_40[0x40];
7965 };
7966
7967 struct mlx5_ifc_alloc_transport_domain_out_bits {
7968 u8 status[0x8];
7969 u8 reserved_at_8[0x18];
7970
7971 u8 syndrome[0x20];
7972
7973 u8 reserved_at_40[0x8];
7974 u8 transport_domain[0x18];
7975
7976 u8 reserved_at_60[0x20];
7977 };
7978
7979 struct mlx5_ifc_alloc_transport_domain_in_bits {
7980 u8 opcode[0x10];
7981 u8 uid[0x10];
7982
7983 u8 reserved_at_20[0x10];
7984 u8 op_mod[0x10];
7985
7986 u8 reserved_at_40[0x40];
7987 };
7988
7989 struct mlx5_ifc_alloc_q_counter_out_bits {
7990 u8 status[0x8];
7991 u8 reserved_at_8[0x18];
7992
7993 u8 syndrome[0x20];
7994
7995 u8 reserved_at_40[0x18];
7996 u8 counter_set_id[0x8];
7997
7998 u8 reserved_at_60[0x20];
7999 };
8000
8001 struct mlx5_ifc_alloc_q_counter_in_bits {
8002 u8 opcode[0x10];
8003 u8 uid[0x10];
8004
8005 u8 reserved_at_20[0x10];
8006 u8 op_mod[0x10];
8007
8008 u8 reserved_at_40[0x40];
8009 };
8010
8011 struct mlx5_ifc_alloc_pd_out_bits {
8012 u8 status[0x8];
8013 u8 reserved_at_8[0x18];
8014
8015 u8 syndrome[0x20];
8016
8017 u8 reserved_at_40[0x8];
8018 u8 pd[0x18];
8019
8020 u8 reserved_at_60[0x20];
8021 };
8022
8023 struct mlx5_ifc_alloc_pd_in_bits {
8024 u8 opcode[0x10];
8025 u8 uid[0x10];
8026
8027 u8 reserved_at_20[0x10];
8028 u8 op_mod[0x10];
8029
8030 u8 reserved_at_40[0x40];
8031 };
8032
8033 struct mlx5_ifc_alloc_flow_counter_out_bits {
8034 u8 status[0x8];
8035 u8 reserved_at_8[0x18];
8036
8037 u8 syndrome[0x20];
8038
8039 u8 flow_counter_id[0x20];
8040
8041 u8 reserved_at_60[0x20];
8042 };
8043
8044 struct mlx5_ifc_alloc_flow_counter_in_bits {
8045 u8 opcode[0x10];
8046 u8 reserved_at_10[0x10];
8047
8048 u8 reserved_at_20[0x10];
8049 u8 op_mod[0x10];
8050
8051 u8 reserved_at_40[0x38];
8052 u8 flow_counter_bulk[0x8];
8053 };
8054
8055 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8056 u8 status[0x8];
8057 u8 reserved_at_8[0x18];
8058
8059 u8 syndrome[0x20];
8060
8061 u8 reserved_at_40[0x40];
8062 };
8063
8064 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8065 u8 opcode[0x10];
8066 u8 reserved_at_10[0x10];
8067
8068 u8 reserved_at_20[0x10];
8069 u8 op_mod[0x10];
8070
8071 u8 reserved_at_40[0x20];
8072
8073 u8 reserved_at_60[0x10];
8074 u8 vxlan_udp_port[0x10];
8075 };
8076
8077 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8078 u8 status[0x8];
8079 u8 reserved_at_8[0x18];
8080
8081 u8 syndrome[0x20];
8082
8083 u8 reserved_at_40[0x40];
8084 };
8085
8086 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8087 u8 opcode[0x10];
8088 u8 reserved_at_10[0x10];
8089
8090 u8 reserved_at_20[0x10];
8091 u8 op_mod[0x10];
8092
8093 u8 reserved_at_40[0x10];
8094 u8 rate_limit_index[0x10];
8095
8096 u8 reserved_at_60[0x20];
8097
8098 u8 rate_limit[0x20];
8099
8100 u8 burst_upper_bound[0x20];
8101
8102 u8 reserved_at_c0[0x10];
8103 u8 typical_packet_size[0x10];
8104
8105 u8 reserved_at_e0[0x120];
8106 };
8107
8108 struct mlx5_ifc_access_register_out_bits {
8109 u8 status[0x8];
8110 u8 reserved_at_8[0x18];
8111
8112 u8 syndrome[0x20];
8113
8114 u8 reserved_at_40[0x40];
8115
8116 u8 register_data[0][0x20];
8117 };
8118
8119 enum {
8120 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8121 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8122 };
8123
8124 struct mlx5_ifc_access_register_in_bits {
8125 u8 opcode[0x10];
8126 u8 reserved_at_10[0x10];
8127
8128 u8 reserved_at_20[0x10];
8129 u8 op_mod[0x10];
8130
8131 u8 reserved_at_40[0x10];
8132 u8 register_id[0x10];
8133
8134 u8 argument[0x20];
8135
8136 u8 register_data[0][0x20];
8137 };
8138
8139 struct mlx5_ifc_sltp_reg_bits {
8140 u8 status[0x4];
8141 u8 version[0x4];
8142 u8 local_port[0x8];
8143 u8 pnat[0x2];
8144 u8 reserved_at_12[0x2];
8145 u8 lane[0x4];
8146 u8 reserved_at_18[0x8];
8147
8148 u8 reserved_at_20[0x20];
8149
8150 u8 reserved_at_40[0x7];
8151 u8 polarity[0x1];
8152 u8 ob_tap0[0x8];
8153 u8 ob_tap1[0x8];
8154 u8 ob_tap2[0x8];
8155
8156 u8 reserved_at_60[0xc];
8157 u8 ob_preemp_mode[0x4];
8158 u8 ob_reg[0x8];
8159 u8 ob_bias[0x8];
8160
8161 u8 reserved_at_80[0x20];
8162 };
8163
8164 struct mlx5_ifc_slrg_reg_bits {
8165 u8 status[0x4];
8166 u8 version[0x4];
8167 u8 local_port[0x8];
8168 u8 pnat[0x2];
8169 u8 reserved_at_12[0x2];
8170 u8 lane[0x4];
8171 u8 reserved_at_18[0x8];
8172
8173 u8 time_to_link_up[0x10];
8174 u8 reserved_at_30[0xc];
8175 u8 grade_lane_speed[0x4];
8176
8177 u8 grade_version[0x8];
8178 u8 grade[0x18];
8179
8180 u8 reserved_at_60[0x4];
8181 u8 height_grade_type[0x4];
8182 u8 height_grade[0x18];
8183
8184 u8 height_dz[0x10];
8185 u8 height_dv[0x10];
8186
8187 u8 reserved_at_a0[0x10];
8188 u8 height_sigma[0x10];
8189
8190 u8 reserved_at_c0[0x20];
8191
8192 u8 reserved_at_e0[0x4];
8193 u8 phase_grade_type[0x4];
8194 u8 phase_grade[0x18];
8195
8196 u8 reserved_at_100[0x8];
8197 u8 phase_eo_pos[0x8];
8198 u8 reserved_at_110[0x8];
8199 u8 phase_eo_neg[0x8];
8200
8201 u8 ffe_set_tested[0x10];
8202 u8 test_errors_per_lane[0x10];
8203 };
8204
8205 struct mlx5_ifc_pvlc_reg_bits {
8206 u8 reserved_at_0[0x8];
8207 u8 local_port[0x8];
8208 u8 reserved_at_10[0x10];
8209
8210 u8 reserved_at_20[0x1c];
8211 u8 vl_hw_cap[0x4];
8212
8213 u8 reserved_at_40[0x1c];
8214 u8 vl_admin[0x4];
8215
8216 u8 reserved_at_60[0x1c];
8217 u8 vl_operational[0x4];
8218 };
8219
8220 struct mlx5_ifc_pude_reg_bits {
8221 u8 swid[0x8];
8222 u8 local_port[0x8];
8223 u8 reserved_at_10[0x4];
8224 u8 admin_status[0x4];
8225 u8 reserved_at_18[0x4];
8226 u8 oper_status[0x4];
8227
8228 u8 reserved_at_20[0x60];
8229 };
8230
8231 struct mlx5_ifc_ptys_reg_bits {
8232 u8 reserved_at_0[0x1];
8233 u8 an_disable_admin[0x1];
8234 u8 an_disable_cap[0x1];
8235 u8 reserved_at_3[0x5];
8236 u8 local_port[0x8];
8237 u8 reserved_at_10[0xd];
8238 u8 proto_mask[0x3];
8239
8240 u8 an_status[0x4];
8241 u8 reserved_at_24[0x1c];
8242
8243 u8 ext_eth_proto_capability[0x20];
8244
8245 u8 eth_proto_capability[0x20];
8246
8247 u8 ib_link_width_capability[0x10];
8248 u8 ib_proto_capability[0x10];
8249
8250 u8 ext_eth_proto_admin[0x20];
8251
8252 u8 eth_proto_admin[0x20];
8253
8254 u8 ib_link_width_admin[0x10];
8255 u8 ib_proto_admin[0x10];
8256
8257 u8 ext_eth_proto_oper[0x20];
8258
8259 u8 eth_proto_oper[0x20];
8260
8261 u8 ib_link_width_oper[0x10];
8262 u8 ib_proto_oper[0x10];
8263
8264 u8 reserved_at_160[0x1c];
8265 u8 connector_type[0x4];
8266
8267 u8 eth_proto_lp_advertise[0x20];
8268
8269 u8 reserved_at_1a0[0x60];
8270 };
8271
8272 struct mlx5_ifc_mlcr_reg_bits {
8273 u8 reserved_at_0[0x8];
8274 u8 local_port[0x8];
8275 u8 reserved_at_10[0x20];
8276
8277 u8 beacon_duration[0x10];
8278 u8 reserved_at_40[0x10];
8279
8280 u8 beacon_remain[0x10];
8281 };
8282
8283 struct mlx5_ifc_ptas_reg_bits {
8284 u8 reserved_at_0[0x20];
8285
8286 u8 algorithm_options[0x10];
8287 u8 reserved_at_30[0x4];
8288 u8 repetitions_mode[0x4];
8289 u8 num_of_repetitions[0x8];
8290
8291 u8 grade_version[0x8];
8292 u8 height_grade_type[0x4];
8293 u8 phase_grade_type[0x4];
8294 u8 height_grade_weight[0x8];
8295 u8 phase_grade_weight[0x8];
8296
8297 u8 gisim_measure_bits[0x10];
8298 u8 adaptive_tap_measure_bits[0x10];
8299
8300 u8 ber_bath_high_error_threshold[0x10];
8301 u8 ber_bath_mid_error_threshold[0x10];
8302
8303 u8 ber_bath_low_error_threshold[0x10];
8304 u8 one_ratio_high_threshold[0x10];
8305
8306 u8 one_ratio_high_mid_threshold[0x10];
8307 u8 one_ratio_low_mid_threshold[0x10];
8308
8309 u8 one_ratio_low_threshold[0x10];
8310 u8 ndeo_error_threshold[0x10];
8311
8312 u8 mixer_offset_step_size[0x10];
8313 u8 reserved_at_110[0x8];
8314 u8 mix90_phase_for_voltage_bath[0x8];
8315
8316 u8 mixer_offset_start[0x10];
8317 u8 mixer_offset_end[0x10];
8318
8319 u8 reserved_at_140[0x15];
8320 u8 ber_test_time[0xb];
8321 };
8322
8323 struct mlx5_ifc_pspa_reg_bits {
8324 u8 swid[0x8];
8325 u8 local_port[0x8];
8326 u8 sub_port[0x8];
8327 u8 reserved_at_18[0x8];
8328
8329 u8 reserved_at_20[0x20];
8330 };
8331
8332 struct mlx5_ifc_pqdr_reg_bits {
8333 u8 reserved_at_0[0x8];
8334 u8 local_port[0x8];
8335 u8 reserved_at_10[0x5];
8336 u8 prio[0x3];
8337 u8 reserved_at_18[0x6];
8338 u8 mode[0x2];
8339
8340 u8 reserved_at_20[0x20];
8341
8342 u8 reserved_at_40[0x10];
8343 u8 min_threshold[0x10];
8344
8345 u8 reserved_at_60[0x10];
8346 u8 max_threshold[0x10];
8347
8348 u8 reserved_at_80[0x10];
8349 u8 mark_probability_denominator[0x10];
8350
8351 u8 reserved_at_a0[0x60];
8352 };
8353
8354 struct mlx5_ifc_ppsc_reg_bits {
8355 u8 reserved_at_0[0x8];
8356 u8 local_port[0x8];
8357 u8 reserved_at_10[0x10];
8358
8359 u8 reserved_at_20[0x60];
8360
8361 u8 reserved_at_80[0x1c];
8362 u8 wrps_admin[0x4];
8363
8364 u8 reserved_at_a0[0x1c];
8365 u8 wrps_status[0x4];
8366
8367 u8 reserved_at_c0[0x8];
8368 u8 up_threshold[0x8];
8369 u8 reserved_at_d0[0x8];
8370 u8 down_threshold[0x8];
8371
8372 u8 reserved_at_e0[0x20];
8373
8374 u8 reserved_at_100[0x1c];
8375 u8 srps_admin[0x4];
8376
8377 u8 reserved_at_120[0x1c];
8378 u8 srps_status[0x4];
8379
8380 u8 reserved_at_140[0x40];
8381 };
8382
8383 struct mlx5_ifc_pplr_reg_bits {
8384 u8 reserved_at_0[0x8];
8385 u8 local_port[0x8];
8386 u8 reserved_at_10[0x10];
8387
8388 u8 reserved_at_20[0x8];
8389 u8 lb_cap[0x8];
8390 u8 reserved_at_30[0x8];
8391 u8 lb_en[0x8];
8392 };
8393
8394 struct mlx5_ifc_pplm_reg_bits {
8395 u8 reserved_at_0[0x8];
8396 u8 local_port[0x8];
8397 u8 reserved_at_10[0x10];
8398
8399 u8 reserved_at_20[0x20];
8400
8401 u8 port_profile_mode[0x8];
8402 u8 static_port_profile[0x8];
8403 u8 active_port_profile[0x8];
8404 u8 reserved_at_58[0x8];
8405
8406 u8 retransmission_active[0x8];
8407 u8 fec_mode_active[0x18];
8408
8409 u8 rs_fec_correction_bypass_cap[0x4];
8410 u8 reserved_at_84[0x8];
8411 u8 fec_override_cap_56g[0x4];
8412 u8 fec_override_cap_100g[0x4];
8413 u8 fec_override_cap_50g[0x4];
8414 u8 fec_override_cap_25g[0x4];
8415 u8 fec_override_cap_10g_40g[0x4];
8416
8417 u8 rs_fec_correction_bypass_admin[0x4];
8418 u8 reserved_at_a4[0x8];
8419 u8 fec_override_admin_56g[0x4];
8420 u8 fec_override_admin_100g[0x4];
8421 u8 fec_override_admin_50g[0x4];
8422 u8 fec_override_admin_25g[0x4];
8423 u8 fec_override_admin_10g_40g[0x4];
8424 };
8425
8426 struct mlx5_ifc_ppcnt_reg_bits {
8427 u8 swid[0x8];
8428 u8 local_port[0x8];
8429 u8 pnat[0x2];
8430 u8 reserved_at_12[0x8];
8431 u8 grp[0x6];
8432
8433 u8 clr[0x1];
8434 u8 reserved_at_21[0x1c];
8435 u8 prio_tc[0x3];
8436
8437 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8438 };
8439
8440 struct mlx5_ifc_mpein_reg_bits {
8441 u8 reserved_at_0[0x2];
8442 u8 depth[0x6];
8443 u8 pcie_index[0x8];
8444 u8 node[0x8];
8445 u8 reserved_at_18[0x8];
8446
8447 u8 capability_mask[0x20];
8448
8449 u8 reserved_at_40[0x8];
8450 u8 link_width_enabled[0x8];
8451 u8 link_speed_enabled[0x10];
8452
8453 u8 lane0_physical_position[0x8];
8454 u8 link_width_active[0x8];
8455 u8 link_speed_active[0x10];
8456
8457 u8 num_of_pfs[0x10];
8458 u8 num_of_vfs[0x10];
8459
8460 u8 bdf0[0x10];
8461 u8 reserved_at_b0[0x10];
8462
8463 u8 max_read_request_size[0x4];
8464 u8 max_payload_size[0x4];
8465 u8 reserved_at_c8[0x5];
8466 u8 pwr_status[0x3];
8467 u8 port_type[0x4];
8468 u8 reserved_at_d4[0xb];
8469 u8 lane_reversal[0x1];
8470
8471 u8 reserved_at_e0[0x14];
8472 u8 pci_power[0xc];
8473
8474 u8 reserved_at_100[0x20];
8475
8476 u8 device_status[0x10];
8477 u8 port_state[0x8];
8478 u8 reserved_at_138[0x8];
8479
8480 u8 reserved_at_140[0x10];
8481 u8 receiver_detect_result[0x10];
8482
8483 u8 reserved_at_160[0x20];
8484 };
8485
8486 struct mlx5_ifc_mpcnt_reg_bits {
8487 u8 reserved_at_0[0x8];
8488 u8 pcie_index[0x8];
8489 u8 reserved_at_10[0xa];
8490 u8 grp[0x6];
8491
8492 u8 clr[0x1];
8493 u8 reserved_at_21[0x1f];
8494
8495 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8496 };
8497
8498 struct mlx5_ifc_ppad_reg_bits {
8499 u8 reserved_at_0[0x3];
8500 u8 single_mac[0x1];
8501 u8 reserved_at_4[0x4];
8502 u8 local_port[0x8];
8503 u8 mac_47_32[0x10];
8504
8505 u8 mac_31_0[0x20];
8506
8507 u8 reserved_at_40[0x40];
8508 };
8509
8510 struct mlx5_ifc_pmtu_reg_bits {
8511 u8 reserved_at_0[0x8];
8512 u8 local_port[0x8];
8513 u8 reserved_at_10[0x10];
8514
8515 u8 max_mtu[0x10];
8516 u8 reserved_at_30[0x10];
8517
8518 u8 admin_mtu[0x10];
8519 u8 reserved_at_50[0x10];
8520
8521 u8 oper_mtu[0x10];
8522 u8 reserved_at_70[0x10];
8523 };
8524
8525 struct mlx5_ifc_pmpr_reg_bits {
8526 u8 reserved_at_0[0x8];
8527 u8 module[0x8];
8528 u8 reserved_at_10[0x10];
8529
8530 u8 reserved_at_20[0x18];
8531 u8 attenuation_5g[0x8];
8532
8533 u8 reserved_at_40[0x18];
8534 u8 attenuation_7g[0x8];
8535
8536 u8 reserved_at_60[0x18];
8537 u8 attenuation_12g[0x8];
8538 };
8539
8540 struct mlx5_ifc_pmpe_reg_bits {
8541 u8 reserved_at_0[0x8];
8542 u8 module[0x8];
8543 u8 reserved_at_10[0xc];
8544 u8 module_status[0x4];
8545
8546 u8 reserved_at_20[0x60];
8547 };
8548
8549 struct mlx5_ifc_pmpc_reg_bits {
8550 u8 module_state_updated[32][0x8];
8551 };
8552
8553 struct mlx5_ifc_pmlpn_reg_bits {
8554 u8 reserved_at_0[0x4];
8555 u8 mlpn_status[0x4];
8556 u8 local_port[0x8];
8557 u8 reserved_at_10[0x10];
8558
8559 u8 e[0x1];
8560 u8 reserved_at_21[0x1f];
8561 };
8562
8563 struct mlx5_ifc_pmlp_reg_bits {
8564 u8 rxtx[0x1];
8565 u8 reserved_at_1[0x7];
8566 u8 local_port[0x8];
8567 u8 reserved_at_10[0x8];
8568 u8 width[0x8];
8569
8570 u8 lane0_module_mapping[0x20];
8571
8572 u8 lane1_module_mapping[0x20];
8573
8574 u8 lane2_module_mapping[0x20];
8575
8576 u8 lane3_module_mapping[0x20];
8577
8578 u8 reserved_at_a0[0x160];
8579 };
8580
8581 struct mlx5_ifc_pmaos_reg_bits {
8582 u8 reserved_at_0[0x8];
8583 u8 module[0x8];
8584 u8 reserved_at_10[0x4];
8585 u8 admin_status[0x4];
8586 u8 reserved_at_18[0x4];
8587 u8 oper_status[0x4];
8588
8589 u8 ase[0x1];
8590 u8 ee[0x1];
8591 u8 reserved_at_22[0x1c];
8592 u8 e[0x2];
8593
8594 u8 reserved_at_40[0x40];
8595 };
8596
8597 struct mlx5_ifc_plpc_reg_bits {
8598 u8 reserved_at_0[0x4];
8599 u8 profile_id[0xc];
8600 u8 reserved_at_10[0x4];
8601 u8 proto_mask[0x4];
8602 u8 reserved_at_18[0x8];
8603
8604 u8 reserved_at_20[0x10];
8605 u8 lane_speed[0x10];
8606
8607 u8 reserved_at_40[0x17];
8608 u8 lpbf[0x1];
8609 u8 fec_mode_policy[0x8];
8610
8611 u8 retransmission_capability[0x8];
8612 u8 fec_mode_capability[0x18];
8613
8614 u8 retransmission_support_admin[0x8];
8615 u8 fec_mode_support_admin[0x18];
8616
8617 u8 retransmission_request_admin[0x8];
8618 u8 fec_mode_request_admin[0x18];
8619
8620 u8 reserved_at_c0[0x80];
8621 };
8622
8623 struct mlx5_ifc_plib_reg_bits {
8624 u8 reserved_at_0[0x8];
8625 u8 local_port[0x8];
8626 u8 reserved_at_10[0x8];
8627 u8 ib_port[0x8];
8628
8629 u8 reserved_at_20[0x60];
8630 };
8631
8632 struct mlx5_ifc_plbf_reg_bits {
8633 u8 reserved_at_0[0x8];
8634 u8 local_port[0x8];
8635 u8 reserved_at_10[0xd];
8636 u8 lbf_mode[0x3];
8637
8638 u8 reserved_at_20[0x20];
8639 };
8640
8641 struct mlx5_ifc_pipg_reg_bits {
8642 u8 reserved_at_0[0x8];
8643 u8 local_port[0x8];
8644 u8 reserved_at_10[0x10];
8645
8646 u8 dic[0x1];
8647 u8 reserved_at_21[0x19];
8648 u8 ipg[0x4];
8649 u8 reserved_at_3e[0x2];
8650 };
8651
8652 struct mlx5_ifc_pifr_reg_bits {
8653 u8 reserved_at_0[0x8];
8654 u8 local_port[0x8];
8655 u8 reserved_at_10[0x10];
8656
8657 u8 reserved_at_20[0xe0];
8658
8659 u8 port_filter[8][0x20];
8660
8661 u8 port_filter_update_en[8][0x20];
8662 };
8663
8664 struct mlx5_ifc_pfcc_reg_bits {
8665 u8 reserved_at_0[0x8];
8666 u8 local_port[0x8];
8667 u8 reserved_at_10[0xb];
8668 u8 ppan_mask_n[0x1];
8669 u8 minor_stall_mask[0x1];
8670 u8 critical_stall_mask[0x1];
8671 u8 reserved_at_1e[0x2];
8672
8673 u8 ppan[0x4];
8674 u8 reserved_at_24[0x4];
8675 u8 prio_mask_tx[0x8];
8676 u8 reserved_at_30[0x8];
8677 u8 prio_mask_rx[0x8];
8678
8679 u8 pptx[0x1];
8680 u8 aptx[0x1];
8681 u8 pptx_mask_n[0x1];
8682 u8 reserved_at_43[0x5];
8683 u8 pfctx[0x8];
8684 u8 reserved_at_50[0x10];
8685
8686 u8 pprx[0x1];
8687 u8 aprx[0x1];
8688 u8 pprx_mask_n[0x1];
8689 u8 reserved_at_63[0x5];
8690 u8 pfcrx[0x8];
8691 u8 reserved_at_70[0x10];
8692
8693 u8 device_stall_minor_watermark[0x10];
8694 u8 device_stall_critical_watermark[0x10];
8695
8696 u8 reserved_at_a0[0x60];
8697 };
8698
8699 struct mlx5_ifc_pelc_reg_bits {
8700 u8 op[0x4];
8701 u8 reserved_at_4[0x4];
8702 u8 local_port[0x8];
8703 u8 reserved_at_10[0x10];
8704
8705 u8 op_admin[0x8];
8706 u8 op_capability[0x8];
8707 u8 op_request[0x8];
8708 u8 op_active[0x8];
8709
8710 u8 admin[0x40];
8711
8712 u8 capability[0x40];
8713
8714 u8 request[0x40];
8715
8716 u8 active[0x40];
8717
8718 u8 reserved_at_140[0x80];
8719 };
8720
8721 struct mlx5_ifc_peir_reg_bits {
8722 u8 reserved_at_0[0x8];
8723 u8 local_port[0x8];
8724 u8 reserved_at_10[0x10];
8725
8726 u8 reserved_at_20[0xc];
8727 u8 error_count[0x4];
8728 u8 reserved_at_30[0x10];
8729
8730 u8 reserved_at_40[0xc];
8731 u8 lane[0x4];
8732 u8 reserved_at_50[0x8];
8733 u8 error_type[0x8];
8734 };
8735
8736 struct mlx5_ifc_mpegc_reg_bits {
8737 u8 reserved_at_0[0x30];
8738 u8 field_select[0x10];
8739
8740 u8 tx_overflow_sense[0x1];
8741 u8 mark_cqe[0x1];
8742 u8 mark_cnp[0x1];
8743 u8 reserved_at_43[0x1b];
8744 u8 tx_lossy_overflow_oper[0x2];
8745
8746 u8 reserved_at_60[0x100];
8747 };
8748
8749 struct mlx5_ifc_pcam_enhanced_features_bits {
8750 u8 reserved_at_0[0x6d];
8751 u8 rx_icrc_encapsulated_counter[0x1];
8752 u8 reserved_at_6e[0x4];
8753 u8 ptys_extended_ethernet[0x1];
8754 u8 reserved_at_73[0x3];
8755 u8 pfcc_mask[0x1];
8756 u8 reserved_at_77[0x3];
8757 u8 per_lane_error_counters[0x1];
8758 u8 rx_buffer_fullness_counters[0x1];
8759 u8 ptys_connector_type[0x1];
8760 u8 reserved_at_7d[0x1];
8761 u8 ppcnt_discard_group[0x1];
8762 u8 ppcnt_statistical_group[0x1];
8763 };
8764
8765 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8766 u8 port_access_reg_cap_mask_127_to_96[0x20];
8767 u8 port_access_reg_cap_mask_95_to_64[0x20];
8768
8769 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8770 u8 pplm[0x1];
8771 u8 port_access_reg_cap_mask_34_to_32[0x3];
8772
8773 u8 port_access_reg_cap_mask_31_to_13[0x13];
8774 u8 pbmc[0x1];
8775 u8 pptb[0x1];
8776 u8 port_access_reg_cap_mask_10_to_09[0x2];
8777 u8 ppcnt[0x1];
8778 u8 port_access_reg_cap_mask_07_to_00[0x8];
8779 };
8780
8781 struct mlx5_ifc_pcam_reg_bits {
8782 u8 reserved_at_0[0x8];
8783 u8 feature_group[0x8];
8784 u8 reserved_at_10[0x8];
8785 u8 access_reg_group[0x8];
8786
8787 u8 reserved_at_20[0x20];
8788
8789 union {
8790 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8791 u8 reserved_at_0[0x80];
8792 } port_access_reg_cap_mask;
8793
8794 u8 reserved_at_c0[0x80];
8795
8796 union {
8797 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8798 u8 reserved_at_0[0x80];
8799 } feature_cap_mask;
8800
8801 u8 reserved_at_1c0[0xc0];
8802 };
8803
8804 struct mlx5_ifc_mcam_enhanced_features_bits {
8805 u8 reserved_at_0[0x6e];
8806 u8 pci_status_and_power[0x1];
8807 u8 reserved_at_6f[0x5];
8808 u8 mark_tx_action_cnp[0x1];
8809 u8 mark_tx_action_cqe[0x1];
8810 u8 dynamic_tx_overflow[0x1];
8811 u8 reserved_at_77[0x4];
8812 u8 pcie_outbound_stalled[0x1];
8813 u8 tx_overflow_buffer_pkt[0x1];
8814 u8 mtpps_enh_out_per_adj[0x1];
8815 u8 mtpps_fs[0x1];
8816 u8 pcie_performance_group[0x1];
8817 };
8818
8819 struct mlx5_ifc_mcam_access_reg_bits {
8820 u8 reserved_at_0[0x1c];
8821 u8 mcda[0x1];
8822 u8 mcc[0x1];
8823 u8 mcqi[0x1];
8824 u8 mcqs[0x1];
8825
8826 u8 regs_95_to_87[0x9];
8827 u8 mpegc[0x1];
8828 u8 regs_85_to_68[0x12];
8829 u8 tracer_registers[0x4];
8830
8831 u8 regs_63_to_32[0x20];
8832 u8 regs_31_to_0[0x20];
8833 };
8834
8835 struct mlx5_ifc_mcam_access_reg_bits1 {
8836 u8 regs_127_to_96[0x20];
8837
8838 u8 regs_95_to_64[0x20];
8839
8840 u8 regs_63_to_32[0x20];
8841
8842 u8 regs_31_to_0[0x20];
8843 };
8844
8845 struct mlx5_ifc_mcam_access_reg_bits2 {
8846 u8 regs_127_to_99[0x1d];
8847 u8 mirc[0x1];
8848 u8 regs_97_to_96[0x2];
8849
8850 u8 regs_95_to_64[0x20];
8851
8852 u8 regs_63_to_32[0x20];
8853
8854 u8 regs_31_to_0[0x20];
8855 };
8856
8857 struct mlx5_ifc_mcam_reg_bits {
8858 u8 reserved_at_0[0x8];
8859 u8 feature_group[0x8];
8860 u8 reserved_at_10[0x8];
8861 u8 access_reg_group[0x8];
8862
8863 u8 reserved_at_20[0x20];
8864
8865 union {
8866 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8867 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
8868 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
8869 u8 reserved_at_0[0x80];
8870 } mng_access_reg_cap_mask;
8871
8872 u8 reserved_at_c0[0x80];
8873
8874 union {
8875 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8876 u8 reserved_at_0[0x80];
8877 } mng_feature_cap_mask;
8878
8879 u8 reserved_at_1c0[0x80];
8880 };
8881
8882 struct mlx5_ifc_qcam_access_reg_cap_mask {
8883 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8884 u8 qpdpm[0x1];
8885 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8886 u8 qdpm[0x1];
8887 u8 qpts[0x1];
8888 u8 qcap[0x1];
8889 u8 qcam_access_reg_cap_mask_0[0x1];
8890 };
8891
8892 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8893 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8894 u8 qpts_trust_both[0x1];
8895 };
8896
8897 struct mlx5_ifc_qcam_reg_bits {
8898 u8 reserved_at_0[0x8];
8899 u8 feature_group[0x8];
8900 u8 reserved_at_10[0x8];
8901 u8 access_reg_group[0x8];
8902 u8 reserved_at_20[0x20];
8903
8904 union {
8905 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8906 u8 reserved_at_0[0x80];
8907 } qos_access_reg_cap_mask;
8908
8909 u8 reserved_at_c0[0x80];
8910
8911 union {
8912 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8913 u8 reserved_at_0[0x80];
8914 } qos_feature_cap_mask;
8915
8916 u8 reserved_at_1c0[0x80];
8917 };
8918
8919 struct mlx5_ifc_core_dump_reg_bits {
8920 u8 reserved_at_0[0x18];
8921 u8 core_dump_type[0x8];
8922
8923 u8 reserved_at_20[0x30];
8924 u8 vhca_id[0x10];
8925
8926 u8 reserved_at_60[0x8];
8927 u8 qpn[0x18];
8928 u8 reserved_at_80[0x180];
8929 };
8930
8931 struct mlx5_ifc_pcap_reg_bits {
8932 u8 reserved_at_0[0x8];
8933 u8 local_port[0x8];
8934 u8 reserved_at_10[0x10];
8935
8936 u8 port_capability_mask[4][0x20];
8937 };
8938
8939 struct mlx5_ifc_paos_reg_bits {
8940 u8 swid[0x8];
8941 u8 local_port[0x8];
8942 u8 reserved_at_10[0x4];
8943 u8 admin_status[0x4];
8944 u8 reserved_at_18[0x4];
8945 u8 oper_status[0x4];
8946
8947 u8 ase[0x1];
8948 u8 ee[0x1];
8949 u8 reserved_at_22[0x1c];
8950 u8 e[0x2];
8951
8952 u8 reserved_at_40[0x40];
8953 };
8954
8955 struct mlx5_ifc_pamp_reg_bits {
8956 u8 reserved_at_0[0x8];
8957 u8 opamp_group[0x8];
8958 u8 reserved_at_10[0xc];
8959 u8 opamp_group_type[0x4];
8960
8961 u8 start_index[0x10];
8962 u8 reserved_at_30[0x4];
8963 u8 num_of_indices[0xc];
8964
8965 u8 index_data[18][0x10];
8966 };
8967
8968 struct mlx5_ifc_pcmr_reg_bits {
8969 u8 reserved_at_0[0x8];
8970 u8 local_port[0x8];
8971 u8 reserved_at_10[0x10];
8972 u8 entropy_force_cap[0x1];
8973 u8 entropy_calc_cap[0x1];
8974 u8 entropy_gre_calc_cap[0x1];
8975 u8 reserved_at_23[0x1b];
8976 u8 fcs_cap[0x1];
8977 u8 reserved_at_3f[0x1];
8978 u8 entropy_force[0x1];
8979 u8 entropy_calc[0x1];
8980 u8 entropy_gre_calc[0x1];
8981 u8 reserved_at_43[0x1b];
8982 u8 fcs_chk[0x1];
8983 u8 reserved_at_5f[0x1];
8984 };
8985
8986 struct mlx5_ifc_lane_2_module_mapping_bits {
8987 u8 reserved_at_0[0x6];
8988 u8 rx_lane[0x2];
8989 u8 reserved_at_8[0x6];
8990 u8 tx_lane[0x2];
8991 u8 reserved_at_10[0x8];
8992 u8 module[0x8];
8993 };
8994
8995 struct mlx5_ifc_bufferx_reg_bits {
8996 u8 reserved_at_0[0x6];
8997 u8 lossy[0x1];
8998 u8 epsb[0x1];
8999 u8 reserved_at_8[0xc];
9000 u8 size[0xc];
9001
9002 u8 xoff_threshold[0x10];
9003 u8 xon_threshold[0x10];
9004 };
9005
9006 struct mlx5_ifc_set_node_in_bits {
9007 u8 node_description[64][0x8];
9008 };
9009
9010 struct mlx5_ifc_register_power_settings_bits {
9011 u8 reserved_at_0[0x18];
9012 u8 power_settings_level[0x8];
9013
9014 u8 reserved_at_20[0x60];
9015 };
9016
9017 struct mlx5_ifc_register_host_endianness_bits {
9018 u8 he[0x1];
9019 u8 reserved_at_1[0x1f];
9020
9021 u8 reserved_at_20[0x60];
9022 };
9023
9024 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9025 u8 reserved_at_0[0x20];
9026
9027 u8 mkey[0x20];
9028
9029 u8 addressh_63_32[0x20];
9030
9031 u8 addressl_31_0[0x20];
9032 };
9033
9034 struct mlx5_ifc_ud_adrs_vector_bits {
9035 u8 dc_key[0x40];
9036
9037 u8 ext[0x1];
9038 u8 reserved_at_41[0x7];
9039 u8 destination_qp_dct[0x18];
9040
9041 u8 static_rate[0x4];
9042 u8 sl_eth_prio[0x4];
9043 u8 fl[0x1];
9044 u8 mlid[0x7];
9045 u8 rlid_udp_sport[0x10];
9046
9047 u8 reserved_at_80[0x20];
9048
9049 u8 rmac_47_16[0x20];
9050
9051 u8 rmac_15_0[0x10];
9052 u8 tclass[0x8];
9053 u8 hop_limit[0x8];
9054
9055 u8 reserved_at_e0[0x1];
9056 u8 grh[0x1];
9057 u8 reserved_at_e2[0x2];
9058 u8 src_addr_index[0x8];
9059 u8 flow_label[0x14];
9060
9061 u8 rgid_rip[16][0x8];
9062 };
9063
9064 struct mlx5_ifc_pages_req_event_bits {
9065 u8 reserved_at_0[0x10];
9066 u8 function_id[0x10];
9067
9068 u8 num_pages[0x20];
9069
9070 u8 reserved_at_40[0xa0];
9071 };
9072
9073 struct mlx5_ifc_eqe_bits {
9074 u8 reserved_at_0[0x8];
9075 u8 event_type[0x8];
9076 u8 reserved_at_10[0x8];
9077 u8 event_sub_type[0x8];
9078
9079 u8 reserved_at_20[0xe0];
9080
9081 union mlx5_ifc_event_auto_bits event_data;
9082
9083 u8 reserved_at_1e0[0x10];
9084 u8 signature[0x8];
9085 u8 reserved_at_1f8[0x7];
9086 u8 owner[0x1];
9087 };
9088
9089 enum {
9090 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9091 };
9092
9093 struct mlx5_ifc_cmd_queue_entry_bits {
9094 u8 type[0x8];
9095 u8 reserved_at_8[0x18];
9096
9097 u8 input_length[0x20];
9098
9099 u8 input_mailbox_pointer_63_32[0x20];
9100
9101 u8 input_mailbox_pointer_31_9[0x17];
9102 u8 reserved_at_77[0x9];
9103
9104 u8 command_input_inline_data[16][0x8];
9105
9106 u8 command_output_inline_data[16][0x8];
9107
9108 u8 output_mailbox_pointer_63_32[0x20];
9109
9110 u8 output_mailbox_pointer_31_9[0x17];
9111 u8 reserved_at_1b7[0x9];
9112
9113 u8 output_length[0x20];
9114
9115 u8 token[0x8];
9116 u8 signature[0x8];
9117 u8 reserved_at_1f0[0x8];
9118 u8 status[0x7];
9119 u8 ownership[0x1];
9120 };
9121
9122 struct mlx5_ifc_cmd_out_bits {
9123 u8 status[0x8];
9124 u8 reserved_at_8[0x18];
9125
9126 u8 syndrome[0x20];
9127
9128 u8 command_output[0x20];
9129 };
9130
9131 struct mlx5_ifc_cmd_in_bits {
9132 u8 opcode[0x10];
9133 u8 reserved_at_10[0x10];
9134
9135 u8 reserved_at_20[0x10];
9136 u8 op_mod[0x10];
9137
9138 u8 command[0][0x20];
9139 };
9140
9141 struct mlx5_ifc_cmd_if_box_bits {
9142 u8 mailbox_data[512][0x8];
9143
9144 u8 reserved_at_1000[0x180];
9145
9146 u8 next_pointer_63_32[0x20];
9147
9148 u8 next_pointer_31_10[0x16];
9149 u8 reserved_at_11b6[0xa];
9150
9151 u8 block_number[0x20];
9152
9153 u8 reserved_at_11e0[0x8];
9154 u8 token[0x8];
9155 u8 ctrl_signature[0x8];
9156 u8 signature[0x8];
9157 };
9158
9159 struct mlx5_ifc_mtt_bits {
9160 u8 ptag_63_32[0x20];
9161
9162 u8 ptag_31_8[0x18];
9163 u8 reserved_at_38[0x6];
9164 u8 wr_en[0x1];
9165 u8 rd_en[0x1];
9166 };
9167
9168 struct mlx5_ifc_query_wol_rol_out_bits {
9169 u8 status[0x8];
9170 u8 reserved_at_8[0x18];
9171
9172 u8 syndrome[0x20];
9173
9174 u8 reserved_at_40[0x10];
9175 u8 rol_mode[0x8];
9176 u8 wol_mode[0x8];
9177
9178 u8 reserved_at_60[0x20];
9179 };
9180
9181 struct mlx5_ifc_query_wol_rol_in_bits {
9182 u8 opcode[0x10];
9183 u8 reserved_at_10[0x10];
9184
9185 u8 reserved_at_20[0x10];
9186 u8 op_mod[0x10];
9187
9188 u8 reserved_at_40[0x40];
9189 };
9190
9191 struct mlx5_ifc_set_wol_rol_out_bits {
9192 u8 status[0x8];
9193 u8 reserved_at_8[0x18];
9194
9195 u8 syndrome[0x20];
9196
9197 u8 reserved_at_40[0x40];
9198 };
9199
9200 struct mlx5_ifc_set_wol_rol_in_bits {
9201 u8 opcode[0x10];
9202 u8 reserved_at_10[0x10];
9203
9204 u8 reserved_at_20[0x10];
9205 u8 op_mod[0x10];
9206
9207 u8 rol_mode_valid[0x1];
9208 u8 wol_mode_valid[0x1];
9209 u8 reserved_at_42[0xe];
9210 u8 rol_mode[0x8];
9211 u8 wol_mode[0x8];
9212
9213 u8 reserved_at_60[0x20];
9214 };
9215
9216 enum {
9217 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9218 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9219 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9220 };
9221
9222 enum {
9223 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9224 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9225 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9226 };
9227
9228 enum {
9229 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9230 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9231 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9232 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9233 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9234 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9235 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9236 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9237 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9238 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9239 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9240 };
9241
9242 struct mlx5_ifc_initial_seg_bits {
9243 u8 fw_rev_minor[0x10];
9244 u8 fw_rev_major[0x10];
9245
9246 u8 cmd_interface_rev[0x10];
9247 u8 fw_rev_subminor[0x10];
9248
9249 u8 reserved_at_40[0x40];
9250
9251 u8 cmdq_phy_addr_63_32[0x20];
9252
9253 u8 cmdq_phy_addr_31_12[0x14];
9254 u8 reserved_at_b4[0x2];
9255 u8 nic_interface[0x2];
9256 u8 log_cmdq_size[0x4];
9257 u8 log_cmdq_stride[0x4];
9258
9259 u8 command_doorbell_vector[0x20];
9260
9261 u8 reserved_at_e0[0xf00];
9262
9263 u8 initializing[0x1];
9264 u8 reserved_at_fe1[0x4];
9265 u8 nic_interface_supported[0x3];
9266 u8 embedded_cpu[0x1];
9267 u8 reserved_at_fe9[0x17];
9268
9269 struct mlx5_ifc_health_buffer_bits health_buffer;
9270
9271 u8 no_dram_nic_offset[0x20];
9272
9273 u8 reserved_at_1220[0x6e40];
9274
9275 u8 reserved_at_8060[0x1f];
9276 u8 clear_int[0x1];
9277
9278 u8 health_syndrome[0x8];
9279 u8 health_counter[0x18];
9280
9281 u8 reserved_at_80a0[0x17fc0];
9282 };
9283
9284 struct mlx5_ifc_mtpps_reg_bits {
9285 u8 reserved_at_0[0xc];
9286 u8 cap_number_of_pps_pins[0x4];
9287 u8 reserved_at_10[0x4];
9288 u8 cap_max_num_of_pps_in_pins[0x4];
9289 u8 reserved_at_18[0x4];
9290 u8 cap_max_num_of_pps_out_pins[0x4];
9291
9292 u8 reserved_at_20[0x24];
9293 u8 cap_pin_3_mode[0x4];
9294 u8 reserved_at_48[0x4];
9295 u8 cap_pin_2_mode[0x4];
9296 u8 reserved_at_50[0x4];
9297 u8 cap_pin_1_mode[0x4];
9298 u8 reserved_at_58[0x4];
9299 u8 cap_pin_0_mode[0x4];
9300
9301 u8 reserved_at_60[0x4];
9302 u8 cap_pin_7_mode[0x4];
9303 u8 reserved_at_68[0x4];
9304 u8 cap_pin_6_mode[0x4];
9305 u8 reserved_at_70[0x4];
9306 u8 cap_pin_5_mode[0x4];
9307 u8 reserved_at_78[0x4];
9308 u8 cap_pin_4_mode[0x4];
9309
9310 u8 field_select[0x20];
9311 u8 reserved_at_a0[0x60];
9312
9313 u8 enable[0x1];
9314 u8 reserved_at_101[0xb];
9315 u8 pattern[0x4];
9316 u8 reserved_at_110[0x4];
9317 u8 pin_mode[0x4];
9318 u8 pin[0x8];
9319
9320 u8 reserved_at_120[0x20];
9321
9322 u8 time_stamp[0x40];
9323
9324 u8 out_pulse_duration[0x10];
9325 u8 out_periodic_adjustment[0x10];
9326 u8 enhanced_out_periodic_adjustment[0x20];
9327
9328 u8 reserved_at_1c0[0x20];
9329 };
9330
9331 struct mlx5_ifc_mtppse_reg_bits {
9332 u8 reserved_at_0[0x18];
9333 u8 pin[0x8];
9334 u8 event_arm[0x1];
9335 u8 reserved_at_21[0x1b];
9336 u8 event_generation_mode[0x4];
9337 u8 reserved_at_40[0x40];
9338 };
9339
9340 struct mlx5_ifc_mcqs_reg_bits {
9341 u8 last_index_flag[0x1];
9342 u8 reserved_at_1[0x7];
9343 u8 fw_device[0x8];
9344 u8 component_index[0x10];
9345
9346 u8 reserved_at_20[0x10];
9347 u8 identifier[0x10];
9348
9349 u8 reserved_at_40[0x17];
9350 u8 component_status[0x5];
9351 u8 component_update_state[0x4];
9352
9353 u8 last_update_state_changer_type[0x4];
9354 u8 last_update_state_changer_host_id[0x4];
9355 u8 reserved_at_68[0x18];
9356 };
9357
9358 struct mlx5_ifc_mcqi_cap_bits {
9359 u8 supported_info_bitmask[0x20];
9360
9361 u8 component_size[0x20];
9362
9363 u8 max_component_size[0x20];
9364
9365 u8 log_mcda_word_size[0x4];
9366 u8 reserved_at_64[0xc];
9367 u8 mcda_max_write_size[0x10];
9368
9369 u8 rd_en[0x1];
9370 u8 reserved_at_81[0x1];
9371 u8 match_chip_id[0x1];
9372 u8 match_psid[0x1];
9373 u8 check_user_timestamp[0x1];
9374 u8 match_base_guid_mac[0x1];
9375 u8 reserved_at_86[0x1a];
9376 };
9377
9378 struct mlx5_ifc_mcqi_version_bits {
9379 u8 reserved_at_0[0x2];
9380 u8 build_time_valid[0x1];
9381 u8 user_defined_time_valid[0x1];
9382 u8 reserved_at_4[0x14];
9383 u8 version_string_length[0x8];
9384
9385 u8 version[0x20];
9386
9387 u8 build_time[0x40];
9388
9389 u8 user_defined_time[0x40];
9390
9391 u8 build_tool_version[0x20];
9392
9393 u8 reserved_at_e0[0x20];
9394
9395 u8 version_string[92][0x8];
9396 };
9397
9398 struct mlx5_ifc_mcqi_activation_method_bits {
9399 u8 pending_server_ac_power_cycle[0x1];
9400 u8 pending_server_dc_power_cycle[0x1];
9401 u8 pending_server_reboot[0x1];
9402 u8 pending_fw_reset[0x1];
9403 u8 auto_activate[0x1];
9404 u8 all_hosts_sync[0x1];
9405 u8 device_hw_reset[0x1];
9406 u8 reserved_at_7[0x19];
9407 };
9408
9409 union mlx5_ifc_mcqi_reg_data_bits {
9410 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9411 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9412 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9413 };
9414
9415 struct mlx5_ifc_mcqi_reg_bits {
9416 u8 read_pending_component[0x1];
9417 u8 reserved_at_1[0xf];
9418 u8 component_index[0x10];
9419
9420 u8 reserved_at_20[0x20];
9421
9422 u8 reserved_at_40[0x1b];
9423 u8 info_type[0x5];
9424
9425 u8 info_size[0x20];
9426
9427 u8 offset[0x20];
9428
9429 u8 reserved_at_a0[0x10];
9430 u8 data_size[0x10];
9431
9432 union mlx5_ifc_mcqi_reg_data_bits data[0];
9433 };
9434
9435 struct mlx5_ifc_mcc_reg_bits {
9436 u8 reserved_at_0[0x4];
9437 u8 time_elapsed_since_last_cmd[0xc];
9438 u8 reserved_at_10[0x8];
9439 u8 instruction[0x8];
9440
9441 u8 reserved_at_20[0x10];
9442 u8 component_index[0x10];
9443
9444 u8 reserved_at_40[0x8];
9445 u8 update_handle[0x18];
9446
9447 u8 handle_owner_type[0x4];
9448 u8 handle_owner_host_id[0x4];
9449 u8 reserved_at_68[0x1];
9450 u8 control_progress[0x7];
9451 u8 error_code[0x8];
9452 u8 reserved_at_78[0x4];
9453 u8 control_state[0x4];
9454
9455 u8 component_size[0x20];
9456
9457 u8 reserved_at_a0[0x60];
9458 };
9459
9460 struct mlx5_ifc_mcda_reg_bits {
9461 u8 reserved_at_0[0x8];
9462 u8 update_handle[0x18];
9463
9464 u8 offset[0x20];
9465
9466 u8 reserved_at_40[0x10];
9467 u8 size[0x10];
9468
9469 u8 reserved_at_60[0x20];
9470
9471 u8 data[0][0x20];
9472 };
9473
9474 struct mlx5_ifc_mirc_reg_bits {
9475 u8 reserved_at_0[0x18];
9476 u8 status_code[0x8];
9477
9478 u8 reserved_at_20[0x20];
9479 };
9480
9481 union mlx5_ifc_ports_control_registers_document_bits {
9482 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9483 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9484 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9485 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9486 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9487 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9488 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9489 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9490 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9491 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9492 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9493 struct mlx5_ifc_paos_reg_bits paos_reg;
9494 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9495 struct mlx5_ifc_peir_reg_bits peir_reg;
9496 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9497 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9498 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9499 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9500 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9501 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9502 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9503 struct mlx5_ifc_plib_reg_bits plib_reg;
9504 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9505 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9506 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9507 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9508 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9509 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9510 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9511 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9512 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9513 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9514 struct mlx5_ifc_mpein_reg_bits mpein_reg;
9515 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9516 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9517 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9518 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9519 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9520 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9521 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9522 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9523 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9524 struct mlx5_ifc_pude_reg_bits pude_reg;
9525 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9526 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9527 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9528 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9529 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9530 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9531 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9532 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9533 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9534 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9535 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9536 struct mlx5_ifc_mirc_reg_bits mirc_reg;
9537 u8 reserved_at_0[0x60e0];
9538 };
9539
9540 union mlx5_ifc_debug_enhancements_document_bits {
9541 struct mlx5_ifc_health_buffer_bits health_buffer;
9542 u8 reserved_at_0[0x200];
9543 };
9544
9545 union mlx5_ifc_uplink_pci_interface_document_bits {
9546 struct mlx5_ifc_initial_seg_bits initial_seg;
9547 u8 reserved_at_0[0x20060];
9548 };
9549
9550 struct mlx5_ifc_set_flow_table_root_out_bits {
9551 u8 status[0x8];
9552 u8 reserved_at_8[0x18];
9553
9554 u8 syndrome[0x20];
9555
9556 u8 reserved_at_40[0x40];
9557 };
9558
9559 struct mlx5_ifc_set_flow_table_root_in_bits {
9560 u8 opcode[0x10];
9561 u8 reserved_at_10[0x10];
9562
9563 u8 reserved_at_20[0x10];
9564 u8 op_mod[0x10];
9565
9566 u8 other_vport[0x1];
9567 u8 reserved_at_41[0xf];
9568 u8 vport_number[0x10];
9569
9570 u8 reserved_at_60[0x20];
9571
9572 u8 table_type[0x8];
9573 u8 reserved_at_88[0x18];
9574
9575 u8 reserved_at_a0[0x8];
9576 u8 table_id[0x18];
9577
9578 u8 reserved_at_c0[0x8];
9579 u8 underlay_qpn[0x18];
9580 u8 reserved_at_e0[0x120];
9581 };
9582
9583 enum {
9584 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9585 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9586 };
9587
9588 struct mlx5_ifc_modify_flow_table_out_bits {
9589 u8 status[0x8];
9590 u8 reserved_at_8[0x18];
9591
9592 u8 syndrome[0x20];
9593
9594 u8 reserved_at_40[0x40];
9595 };
9596
9597 struct mlx5_ifc_modify_flow_table_in_bits {
9598 u8 opcode[0x10];
9599 u8 reserved_at_10[0x10];
9600
9601 u8 reserved_at_20[0x10];
9602 u8 op_mod[0x10];
9603
9604 u8 other_vport[0x1];
9605 u8 reserved_at_41[0xf];
9606 u8 vport_number[0x10];
9607
9608 u8 reserved_at_60[0x10];
9609 u8 modify_field_select[0x10];
9610
9611 u8 table_type[0x8];
9612 u8 reserved_at_88[0x18];
9613
9614 u8 reserved_at_a0[0x8];
9615 u8 table_id[0x18];
9616
9617 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9618 };
9619
9620 struct mlx5_ifc_ets_tcn_config_reg_bits {
9621 u8 g[0x1];
9622 u8 b[0x1];
9623 u8 r[0x1];
9624 u8 reserved_at_3[0x9];
9625 u8 group[0x4];
9626 u8 reserved_at_10[0x9];
9627 u8 bw_allocation[0x7];
9628
9629 u8 reserved_at_20[0xc];
9630 u8 max_bw_units[0x4];
9631 u8 reserved_at_30[0x8];
9632 u8 max_bw_value[0x8];
9633 };
9634
9635 struct mlx5_ifc_ets_global_config_reg_bits {
9636 u8 reserved_at_0[0x2];
9637 u8 r[0x1];
9638 u8 reserved_at_3[0x1d];
9639
9640 u8 reserved_at_20[0xc];
9641 u8 max_bw_units[0x4];
9642 u8 reserved_at_30[0x8];
9643 u8 max_bw_value[0x8];
9644 };
9645
9646 struct mlx5_ifc_qetc_reg_bits {
9647 u8 reserved_at_0[0x8];
9648 u8 port_number[0x8];
9649 u8 reserved_at_10[0x30];
9650
9651 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9652 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9653 };
9654
9655 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9656 u8 e[0x1];
9657 u8 reserved_at_01[0x0b];
9658 u8 prio[0x04];
9659 };
9660
9661 struct mlx5_ifc_qpdpm_reg_bits {
9662 u8 reserved_at_0[0x8];
9663 u8 local_port[0x8];
9664 u8 reserved_at_10[0x10];
9665 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9666 };
9667
9668 struct mlx5_ifc_qpts_reg_bits {
9669 u8 reserved_at_0[0x8];
9670 u8 local_port[0x8];
9671 u8 reserved_at_10[0x2d];
9672 u8 trust_state[0x3];
9673 };
9674
9675 struct mlx5_ifc_pptb_reg_bits {
9676 u8 reserved_at_0[0x2];
9677 u8 mm[0x2];
9678 u8 reserved_at_4[0x4];
9679 u8 local_port[0x8];
9680 u8 reserved_at_10[0x6];
9681 u8 cm[0x1];
9682 u8 um[0x1];
9683 u8 pm[0x8];
9684
9685 u8 prio_x_buff[0x20];
9686
9687 u8 pm_msb[0x8];
9688 u8 reserved_at_48[0x10];
9689 u8 ctrl_buff[0x4];
9690 u8 untagged_buff[0x4];
9691 };
9692
9693 struct mlx5_ifc_pbmc_reg_bits {
9694 u8 reserved_at_0[0x8];
9695 u8 local_port[0x8];
9696 u8 reserved_at_10[0x10];
9697
9698 u8 xoff_timer_value[0x10];
9699 u8 xoff_refresh[0x10];
9700
9701 u8 reserved_at_40[0x9];
9702 u8 fullness_threshold[0x7];
9703 u8 port_buffer_size[0x10];
9704
9705 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9706
9707 u8 reserved_at_2e0[0x40];
9708 };
9709
9710 struct mlx5_ifc_qtct_reg_bits {
9711 u8 reserved_at_0[0x8];
9712 u8 port_number[0x8];
9713 u8 reserved_at_10[0xd];
9714 u8 prio[0x3];
9715
9716 u8 reserved_at_20[0x1d];
9717 u8 tclass[0x3];
9718 };
9719
9720 struct mlx5_ifc_mcia_reg_bits {
9721 u8 l[0x1];
9722 u8 reserved_at_1[0x7];
9723 u8 module[0x8];
9724 u8 reserved_at_10[0x8];
9725 u8 status[0x8];
9726
9727 u8 i2c_device_address[0x8];
9728 u8 page_number[0x8];
9729 u8 device_address[0x10];
9730
9731 u8 reserved_at_40[0x10];
9732 u8 size[0x10];
9733
9734 u8 reserved_at_60[0x20];
9735
9736 u8 dword_0[0x20];
9737 u8 dword_1[0x20];
9738 u8 dword_2[0x20];
9739 u8 dword_3[0x20];
9740 u8 dword_4[0x20];
9741 u8 dword_5[0x20];
9742 u8 dword_6[0x20];
9743 u8 dword_7[0x20];
9744 u8 dword_8[0x20];
9745 u8 dword_9[0x20];
9746 u8 dword_10[0x20];
9747 u8 dword_11[0x20];
9748 };
9749
9750 struct mlx5_ifc_dcbx_param_bits {
9751 u8 dcbx_cee_cap[0x1];
9752 u8 dcbx_ieee_cap[0x1];
9753 u8 dcbx_standby_cap[0x1];
9754 u8 reserved_at_3[0x5];
9755 u8 port_number[0x8];
9756 u8 reserved_at_10[0xa];
9757 u8 max_application_table_size[6];
9758 u8 reserved_at_20[0x15];
9759 u8 version_oper[0x3];
9760 u8 reserved_at_38[5];
9761 u8 version_admin[0x3];
9762 u8 willing_admin[0x1];
9763 u8 reserved_at_41[0x3];
9764 u8 pfc_cap_oper[0x4];
9765 u8 reserved_at_48[0x4];
9766 u8 pfc_cap_admin[0x4];
9767 u8 reserved_at_50[0x4];
9768 u8 num_of_tc_oper[0x4];
9769 u8 reserved_at_58[0x4];
9770 u8 num_of_tc_admin[0x4];
9771 u8 remote_willing[0x1];
9772 u8 reserved_at_61[3];
9773 u8 remote_pfc_cap[4];
9774 u8 reserved_at_68[0x14];
9775 u8 remote_num_of_tc[0x4];
9776 u8 reserved_at_80[0x18];
9777 u8 error[0x8];
9778 u8 reserved_at_a0[0x160];
9779 };
9780
9781 struct mlx5_ifc_lagc_bits {
9782 u8 reserved_at_0[0x1d];
9783 u8 lag_state[0x3];
9784
9785 u8 reserved_at_20[0x14];
9786 u8 tx_remap_affinity_2[0x4];
9787 u8 reserved_at_38[0x4];
9788 u8 tx_remap_affinity_1[0x4];
9789 };
9790
9791 struct mlx5_ifc_create_lag_out_bits {
9792 u8 status[0x8];
9793 u8 reserved_at_8[0x18];
9794
9795 u8 syndrome[0x20];
9796
9797 u8 reserved_at_40[0x40];
9798 };
9799
9800 struct mlx5_ifc_create_lag_in_bits {
9801 u8 opcode[0x10];
9802 u8 reserved_at_10[0x10];
9803
9804 u8 reserved_at_20[0x10];
9805 u8 op_mod[0x10];
9806
9807 struct mlx5_ifc_lagc_bits ctx;
9808 };
9809
9810 struct mlx5_ifc_modify_lag_out_bits {
9811 u8 status[0x8];
9812 u8 reserved_at_8[0x18];
9813
9814 u8 syndrome[0x20];
9815
9816 u8 reserved_at_40[0x40];
9817 };
9818
9819 struct mlx5_ifc_modify_lag_in_bits {
9820 u8 opcode[0x10];
9821 u8 reserved_at_10[0x10];
9822
9823 u8 reserved_at_20[0x10];
9824 u8 op_mod[0x10];
9825
9826 u8 reserved_at_40[0x20];
9827 u8 field_select[0x20];
9828
9829 struct mlx5_ifc_lagc_bits ctx;
9830 };
9831
9832 struct mlx5_ifc_query_lag_out_bits {
9833 u8 status[0x8];
9834 u8 reserved_at_8[0x18];
9835
9836 u8 syndrome[0x20];
9837
9838 struct mlx5_ifc_lagc_bits ctx;
9839 };
9840
9841 struct mlx5_ifc_query_lag_in_bits {
9842 u8 opcode[0x10];
9843 u8 reserved_at_10[0x10];
9844
9845 u8 reserved_at_20[0x10];
9846 u8 op_mod[0x10];
9847
9848 u8 reserved_at_40[0x40];
9849 };
9850
9851 struct mlx5_ifc_destroy_lag_out_bits {
9852 u8 status[0x8];
9853 u8 reserved_at_8[0x18];
9854
9855 u8 syndrome[0x20];
9856
9857 u8 reserved_at_40[0x40];
9858 };
9859
9860 struct mlx5_ifc_destroy_lag_in_bits {
9861 u8 opcode[0x10];
9862 u8 reserved_at_10[0x10];
9863
9864 u8 reserved_at_20[0x10];
9865 u8 op_mod[0x10];
9866
9867 u8 reserved_at_40[0x40];
9868 };
9869
9870 struct mlx5_ifc_create_vport_lag_out_bits {
9871 u8 status[0x8];
9872 u8 reserved_at_8[0x18];
9873
9874 u8 syndrome[0x20];
9875
9876 u8 reserved_at_40[0x40];
9877 };
9878
9879 struct mlx5_ifc_create_vport_lag_in_bits {
9880 u8 opcode[0x10];
9881 u8 reserved_at_10[0x10];
9882
9883 u8 reserved_at_20[0x10];
9884 u8 op_mod[0x10];
9885
9886 u8 reserved_at_40[0x40];
9887 };
9888
9889 struct mlx5_ifc_destroy_vport_lag_out_bits {
9890 u8 status[0x8];
9891 u8 reserved_at_8[0x18];
9892
9893 u8 syndrome[0x20];
9894
9895 u8 reserved_at_40[0x40];
9896 };
9897
9898 struct mlx5_ifc_destroy_vport_lag_in_bits {
9899 u8 opcode[0x10];
9900 u8 reserved_at_10[0x10];
9901
9902 u8 reserved_at_20[0x10];
9903 u8 op_mod[0x10];
9904
9905 u8 reserved_at_40[0x40];
9906 };
9907
9908 struct mlx5_ifc_alloc_memic_in_bits {
9909 u8 opcode[0x10];
9910 u8 reserved_at_10[0x10];
9911
9912 u8 reserved_at_20[0x10];
9913 u8 op_mod[0x10];
9914
9915 u8 reserved_at_30[0x20];
9916
9917 u8 reserved_at_40[0x18];
9918 u8 log_memic_addr_alignment[0x8];
9919
9920 u8 range_start_addr[0x40];
9921
9922 u8 range_size[0x20];
9923
9924 u8 memic_size[0x20];
9925 };
9926
9927 struct mlx5_ifc_alloc_memic_out_bits {
9928 u8 status[0x8];
9929 u8 reserved_at_8[0x18];
9930
9931 u8 syndrome[0x20];
9932
9933 u8 memic_start_addr[0x40];
9934 };
9935
9936 struct mlx5_ifc_dealloc_memic_in_bits {
9937 u8 opcode[0x10];
9938 u8 reserved_at_10[0x10];
9939
9940 u8 reserved_at_20[0x10];
9941 u8 op_mod[0x10];
9942
9943 u8 reserved_at_40[0x40];
9944
9945 u8 memic_start_addr[0x40];
9946
9947 u8 memic_size[0x20];
9948
9949 u8 reserved_at_e0[0x20];
9950 };
9951
9952 struct mlx5_ifc_dealloc_memic_out_bits {
9953 u8 status[0x8];
9954 u8 reserved_at_8[0x18];
9955
9956 u8 syndrome[0x20];
9957
9958 u8 reserved_at_40[0x40];
9959 };
9960
9961 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9962 u8 opcode[0x10];
9963 u8 uid[0x10];
9964
9965 u8 vhca_tunnel_id[0x10];
9966 u8 obj_type[0x10];
9967
9968 u8 obj_id[0x20];
9969
9970 u8 reserved_at_60[0x20];
9971 };
9972
9973 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9974 u8 status[0x8];
9975 u8 reserved_at_8[0x18];
9976
9977 u8 syndrome[0x20];
9978
9979 u8 obj_id[0x20];
9980
9981 u8 reserved_at_60[0x20];
9982 };
9983
9984 struct mlx5_ifc_umem_bits {
9985 u8 reserved_at_0[0x80];
9986
9987 u8 reserved_at_80[0x1b];
9988 u8 log_page_size[0x5];
9989
9990 u8 page_offset[0x20];
9991
9992 u8 num_of_mtt[0x40];
9993
9994 struct mlx5_ifc_mtt_bits mtt[0];
9995 };
9996
9997 struct mlx5_ifc_uctx_bits {
9998 u8 cap[0x20];
9999
10000 u8 reserved_at_20[0x160];
10001 };
10002
10003 struct mlx5_ifc_sw_icm_bits {
10004 u8 modify_field_select[0x40];
10005
10006 u8 reserved_at_40[0x18];
10007 u8 log_sw_icm_size[0x8];
10008
10009 u8 reserved_at_60[0x20];
10010
10011 u8 sw_icm_start_addr[0x40];
10012
10013 u8 reserved_at_c0[0x140];
10014 };
10015
10016 struct mlx5_ifc_geneve_tlv_option_bits {
10017 u8 modify_field_select[0x40];
10018
10019 u8 reserved_at_40[0x18];
10020 u8 geneve_option_fte_index[0x8];
10021
10022 u8 option_class[0x10];
10023 u8 option_type[0x8];
10024 u8 reserved_at_78[0x3];
10025 u8 option_data_length[0x5];
10026
10027 u8 reserved_at_80[0x180];
10028 };
10029
10030 struct mlx5_ifc_create_umem_in_bits {
10031 u8 opcode[0x10];
10032 u8 uid[0x10];
10033
10034 u8 reserved_at_20[0x10];
10035 u8 op_mod[0x10];
10036
10037 u8 reserved_at_40[0x40];
10038
10039 struct mlx5_ifc_umem_bits umem;
10040 };
10041
10042 struct mlx5_ifc_create_uctx_in_bits {
10043 u8 opcode[0x10];
10044 u8 reserved_at_10[0x10];
10045
10046 u8 reserved_at_20[0x10];
10047 u8 op_mod[0x10];
10048
10049 u8 reserved_at_40[0x40];
10050
10051 struct mlx5_ifc_uctx_bits uctx;
10052 };
10053
10054 struct mlx5_ifc_destroy_uctx_in_bits {
10055 u8 opcode[0x10];
10056 u8 reserved_at_10[0x10];
10057
10058 u8 reserved_at_20[0x10];
10059 u8 op_mod[0x10];
10060
10061 u8 reserved_at_40[0x10];
10062 u8 uid[0x10];
10063
10064 u8 reserved_at_60[0x20];
10065 };
10066
10067 struct mlx5_ifc_create_sw_icm_in_bits {
10068 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10069 struct mlx5_ifc_sw_icm_bits sw_icm;
10070 };
10071
10072 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10073 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10074 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
10075 };
10076
10077 struct mlx5_ifc_mtrc_string_db_param_bits {
10078 u8 string_db_base_address[0x20];
10079
10080 u8 reserved_at_20[0x8];
10081 u8 string_db_size[0x18];
10082 };
10083
10084 struct mlx5_ifc_mtrc_cap_bits {
10085 u8 trace_owner[0x1];
10086 u8 trace_to_memory[0x1];
10087 u8 reserved_at_2[0x4];
10088 u8 trc_ver[0x2];
10089 u8 reserved_at_8[0x14];
10090 u8 num_string_db[0x4];
10091
10092 u8 first_string_trace[0x8];
10093 u8 num_string_trace[0x8];
10094 u8 reserved_at_30[0x28];
10095
10096 u8 log_max_trace_buffer_size[0x8];
10097
10098 u8 reserved_at_60[0x20];
10099
10100 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10101
10102 u8 reserved_at_280[0x180];
10103 };
10104
10105 struct mlx5_ifc_mtrc_conf_bits {
10106 u8 reserved_at_0[0x1c];
10107 u8 trace_mode[0x4];
10108 u8 reserved_at_20[0x18];
10109 u8 log_trace_buffer_size[0x8];
10110 u8 trace_mkey[0x20];
10111 u8 reserved_at_60[0x3a0];
10112 };
10113
10114 struct mlx5_ifc_mtrc_stdb_bits {
10115 u8 string_db_index[0x4];
10116 u8 reserved_at_4[0x4];
10117 u8 read_size[0x18];
10118 u8 start_offset[0x20];
10119 u8 string_db_data[0];
10120 };
10121
10122 struct mlx5_ifc_mtrc_ctrl_bits {
10123 u8 trace_status[0x2];
10124 u8 reserved_at_2[0x2];
10125 u8 arm_event[0x1];
10126 u8 reserved_at_5[0xb];
10127 u8 modify_field_select[0x10];
10128 u8 reserved_at_20[0x2b];
10129 u8 current_timestamp52_32[0x15];
10130 u8 current_timestamp31_0[0x20];
10131 u8 reserved_at_80[0x180];
10132 };
10133
10134 struct mlx5_ifc_host_params_context_bits {
10135 u8 host_number[0x8];
10136 u8 reserved_at_8[0x7];
10137 u8 host_pf_disabled[0x1];
10138 u8 host_num_of_vfs[0x10];
10139
10140 u8 host_total_vfs[0x10];
10141 u8 host_pci_bus[0x10];
10142
10143 u8 reserved_at_40[0x10];
10144 u8 host_pci_device[0x10];
10145
10146 u8 reserved_at_60[0x10];
10147 u8 host_pci_function[0x10];
10148
10149 u8 reserved_at_80[0x180];
10150 };
10151
10152 struct mlx5_ifc_query_esw_functions_in_bits {
10153 u8 opcode[0x10];
10154 u8 reserved_at_10[0x10];
10155
10156 u8 reserved_at_20[0x10];
10157 u8 op_mod[0x10];
10158
10159 u8 reserved_at_40[0x40];
10160 };
10161
10162 struct mlx5_ifc_query_esw_functions_out_bits {
10163 u8 status[0x8];
10164 u8 reserved_at_8[0x18];
10165
10166 u8 syndrome[0x20];
10167
10168 u8 reserved_at_40[0x40];
10169
10170 struct mlx5_ifc_host_params_context_bits host_params_context;
10171
10172 u8 reserved_at_280[0x180];
10173 u8 host_sf_enable[0][0x40];
10174 };
10175
10176 struct mlx5_ifc_sf_partition_bits {
10177 u8 reserved_at_0[0x10];
10178 u8 log_num_sf[0x8];
10179 u8 log_sf_bar_size[0x8];
10180 };
10181
10182 struct mlx5_ifc_query_sf_partitions_out_bits {
10183 u8 status[0x8];
10184 u8 reserved_at_8[0x18];
10185
10186 u8 syndrome[0x20];
10187
10188 u8 reserved_at_40[0x18];
10189 u8 num_sf_partitions[0x8];
10190
10191 u8 reserved_at_60[0x20];
10192
10193 struct mlx5_ifc_sf_partition_bits sf_partition[0];
10194 };
10195
10196 struct mlx5_ifc_query_sf_partitions_in_bits {
10197 u8 opcode[0x10];
10198 u8 reserved_at_10[0x10];
10199
10200 u8 reserved_at_20[0x10];
10201 u8 op_mod[0x10];
10202
10203 u8 reserved_at_40[0x40];
10204 };
10205
10206 struct mlx5_ifc_dealloc_sf_out_bits {
10207 u8 status[0x8];
10208 u8 reserved_at_8[0x18];
10209
10210 u8 syndrome[0x20];
10211
10212 u8 reserved_at_40[0x40];
10213 };
10214
10215 struct mlx5_ifc_dealloc_sf_in_bits {
10216 u8 opcode[0x10];
10217 u8 reserved_at_10[0x10];
10218
10219 u8 reserved_at_20[0x10];
10220 u8 op_mod[0x10];
10221
10222 u8 reserved_at_40[0x10];
10223 u8 function_id[0x10];
10224
10225 u8 reserved_at_60[0x20];
10226 };
10227
10228 struct mlx5_ifc_alloc_sf_out_bits {
10229 u8 status[0x8];
10230 u8 reserved_at_8[0x18];
10231
10232 u8 syndrome[0x20];
10233
10234 u8 reserved_at_40[0x40];
10235 };
10236
10237 struct mlx5_ifc_alloc_sf_in_bits {
10238 u8 opcode[0x10];
10239 u8 reserved_at_10[0x10];
10240
10241 u8 reserved_at_20[0x10];
10242 u8 op_mod[0x10];
10243
10244 u8 reserved_at_40[0x10];
10245 u8 function_id[0x10];
10246
10247 u8 reserved_at_60[0x20];
10248 };
10249
10250 struct mlx5_ifc_affiliated_event_header_bits {
10251 u8 reserved_at_0[0x10];
10252 u8 obj_type[0x10];
10253
10254 u8 obj_id[0x20];
10255 };
10256
10257 enum {
10258 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10259 };
10260
10261 enum {
10262 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10263 };
10264
10265 struct mlx5_ifc_encryption_key_obj_bits {
10266 u8 modify_field_select[0x40];
10267
10268 u8 reserved_at_40[0x14];
10269 u8 key_size[0x4];
10270 u8 reserved_at_58[0x4];
10271 u8 key_type[0x4];
10272
10273 u8 reserved_at_60[0x8];
10274 u8 pd[0x18];
10275
10276 u8 reserved_at_80[0x180];
10277 u8 key[8][0x20];
10278
10279 u8 reserved_at_300[0x500];
10280 };
10281
10282 struct mlx5_ifc_create_encryption_key_in_bits {
10283 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10284 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10285 };
10286
10287 enum {
10288 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10289 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10290 };
10291
10292 enum {
10293 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10294 };
10295
10296 struct mlx5_ifc_tls_static_params_bits {
10297 u8 const_2[0x2];
10298 u8 tls_version[0x4];
10299 u8 const_1[0x2];
10300 u8 reserved_at_8[0x14];
10301 u8 encryption_standard[0x4];
10302
10303 u8 reserved_at_20[0x20];
10304
10305 u8 initial_record_number[0x40];
10306
10307 u8 resync_tcp_sn[0x20];
10308
10309 u8 gcm_iv[0x20];
10310
10311 u8 implicit_iv[0x40];
10312
10313 u8 reserved_at_100[0x8];
10314 u8 dek_index[0x18];
10315
10316 u8 reserved_at_120[0xe0];
10317 };
10318
10319 struct mlx5_ifc_tls_progress_params_bits {
10320 u8 reserved_at_0[0x8];
10321 u8 tisn[0x18];
10322
10323 u8 next_record_tcp_sn[0x20];
10324
10325 u8 hw_resync_tcp_sn[0x20];
10326
10327 u8 record_tracker_state[0x2];
10328 u8 auth_state[0x2];
10329 u8 reserved_at_64[0x4];
10330 u8 hw_offset_record_number[0x18];
10331 };
10332
10333 #endif /* MLX5_IFC_H */
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