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[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60 };
61
62 enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67 };
68
69 enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72 };
73
74 enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
230 MLX5_CMD_OP_MAX
231 };
232
233 struct mlx5_ifc_flow_table_fields_supported_bits {
234 u8 outer_dmac[0x1];
235 u8 outer_smac[0x1];
236 u8 outer_ether_type[0x1];
237 u8 reserved_at_3[0x1];
238 u8 outer_first_prio[0x1];
239 u8 outer_first_cfi[0x1];
240 u8 outer_first_vid[0x1];
241 u8 reserved_at_7[0x1];
242 u8 outer_second_prio[0x1];
243 u8 outer_second_cfi[0x1];
244 u8 outer_second_vid[0x1];
245 u8 reserved_at_b[0x1];
246 u8 outer_sip[0x1];
247 u8 outer_dip[0x1];
248 u8 outer_frag[0x1];
249 u8 outer_ip_protocol[0x1];
250 u8 outer_ip_ecn[0x1];
251 u8 outer_ip_dscp[0x1];
252 u8 outer_udp_sport[0x1];
253 u8 outer_udp_dport[0x1];
254 u8 outer_tcp_sport[0x1];
255 u8 outer_tcp_dport[0x1];
256 u8 outer_tcp_flags[0x1];
257 u8 outer_gre_protocol[0x1];
258 u8 outer_gre_key[0x1];
259 u8 outer_vxlan_vni[0x1];
260 u8 reserved_at_1a[0x5];
261 u8 source_eswitch_port[0x1];
262
263 u8 inner_dmac[0x1];
264 u8 inner_smac[0x1];
265 u8 inner_ether_type[0x1];
266 u8 reserved_at_23[0x1];
267 u8 inner_first_prio[0x1];
268 u8 inner_first_cfi[0x1];
269 u8 inner_first_vid[0x1];
270 u8 reserved_at_27[0x1];
271 u8 inner_second_prio[0x1];
272 u8 inner_second_cfi[0x1];
273 u8 inner_second_vid[0x1];
274 u8 reserved_at_2b[0x1];
275 u8 inner_sip[0x1];
276 u8 inner_dip[0x1];
277 u8 inner_frag[0x1];
278 u8 inner_ip_protocol[0x1];
279 u8 inner_ip_ecn[0x1];
280 u8 inner_ip_dscp[0x1];
281 u8 inner_udp_sport[0x1];
282 u8 inner_udp_dport[0x1];
283 u8 inner_tcp_sport[0x1];
284 u8 inner_tcp_dport[0x1];
285 u8 inner_tcp_flags[0x1];
286 u8 reserved_at_37[0x9];
287
288 u8 reserved_at_40[0x40];
289 };
290
291 struct mlx5_ifc_flow_table_prop_layout_bits {
292 u8 ft_support[0x1];
293 u8 reserved_at_1[0x1];
294 u8 flow_counter[0x1];
295 u8 flow_modify_en[0x1];
296 u8 modify_root[0x1];
297 u8 identified_miss_table_mode[0x1];
298 u8 flow_table_modify[0x1];
299 u8 encap[0x1];
300 u8 decap[0x1];
301 u8 reserved_at_9[0x17];
302
303 u8 reserved_at_20[0x2];
304 u8 log_max_ft_size[0x6];
305 u8 reserved_at_28[0x10];
306 u8 max_ft_level[0x8];
307
308 u8 reserved_at_40[0x20];
309
310 u8 reserved_at_60[0x18];
311 u8 log_max_ft_num[0x8];
312
313 u8 reserved_at_80[0x18];
314 u8 log_max_destination[0x8];
315
316 u8 reserved_at_a0[0x18];
317 u8 log_max_flow[0x8];
318
319 u8 reserved_at_c0[0x40];
320
321 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
322
323 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
324 };
325
326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
327 u8 send[0x1];
328 u8 receive[0x1];
329 u8 write[0x1];
330 u8 read[0x1];
331 u8 atomic[0x1];
332 u8 srq_receive[0x1];
333 u8 reserved_at_6[0x1a];
334 };
335
336 struct mlx5_ifc_ipv4_layout_bits {
337 u8 reserved_at_0[0x60];
338
339 u8 ipv4[0x20];
340 };
341
342 struct mlx5_ifc_ipv6_layout_bits {
343 u8 ipv6[16][0x8];
344 };
345
346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
347 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
348 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
349 u8 reserved_at_0[0x80];
350 };
351
352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
353 u8 smac_47_16[0x20];
354
355 u8 smac_15_0[0x10];
356 u8 ethertype[0x10];
357
358 u8 dmac_47_16[0x20];
359
360 u8 dmac_15_0[0x10];
361 u8 first_prio[0x3];
362 u8 first_cfi[0x1];
363 u8 first_vid[0xc];
364
365 u8 ip_protocol[0x8];
366 u8 ip_dscp[0x6];
367 u8 ip_ecn[0x2];
368 u8 vlan_tag[0x1];
369 u8 reserved_at_91[0x1];
370 u8 frag[0x1];
371 u8 reserved_at_93[0x4];
372 u8 tcp_flags[0x9];
373
374 u8 tcp_sport[0x10];
375 u8 tcp_dport[0x10];
376
377 u8 reserved_at_c0[0x20];
378
379 u8 udp_sport[0x10];
380 u8 udp_dport[0x10];
381
382 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
383
384 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
385 };
386
387 struct mlx5_ifc_fte_match_set_misc_bits {
388 u8 reserved_at_0[0x8];
389 u8 source_sqn[0x18];
390
391 u8 reserved_at_20[0x10];
392 u8 source_port[0x10];
393
394 u8 outer_second_prio[0x3];
395 u8 outer_second_cfi[0x1];
396 u8 outer_second_vid[0xc];
397 u8 inner_second_prio[0x3];
398 u8 inner_second_cfi[0x1];
399 u8 inner_second_vid[0xc];
400
401 u8 outer_second_vlan_tag[0x1];
402 u8 inner_second_vlan_tag[0x1];
403 u8 reserved_at_62[0xe];
404 u8 gre_protocol[0x10];
405
406 u8 gre_key_h[0x18];
407 u8 gre_key_l[0x8];
408
409 u8 vxlan_vni[0x18];
410 u8 reserved_at_b8[0x8];
411
412 u8 reserved_at_c0[0x20];
413
414 u8 reserved_at_e0[0xc];
415 u8 outer_ipv6_flow_label[0x14];
416
417 u8 reserved_at_100[0xc];
418 u8 inner_ipv6_flow_label[0x14];
419
420 u8 reserved_at_120[0xe0];
421 };
422
423 struct mlx5_ifc_cmd_pas_bits {
424 u8 pa_h[0x20];
425
426 u8 pa_l[0x14];
427 u8 reserved_at_34[0xc];
428 };
429
430 struct mlx5_ifc_uint64_bits {
431 u8 hi[0x20];
432
433 u8 lo[0x20];
434 };
435
436 enum {
437 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
438 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
439 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
440 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
441 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
442 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
443 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
444 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
445 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
446 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
447 };
448
449 struct mlx5_ifc_ads_bits {
450 u8 fl[0x1];
451 u8 free_ar[0x1];
452 u8 reserved_at_2[0xe];
453 u8 pkey_index[0x10];
454
455 u8 reserved_at_20[0x8];
456 u8 grh[0x1];
457 u8 mlid[0x7];
458 u8 rlid[0x10];
459
460 u8 ack_timeout[0x5];
461 u8 reserved_at_45[0x3];
462 u8 src_addr_index[0x8];
463 u8 reserved_at_50[0x4];
464 u8 stat_rate[0x4];
465 u8 hop_limit[0x8];
466
467 u8 reserved_at_60[0x4];
468 u8 tclass[0x8];
469 u8 flow_label[0x14];
470
471 u8 rgid_rip[16][0x8];
472
473 u8 reserved_at_100[0x4];
474 u8 f_dscp[0x1];
475 u8 f_ecn[0x1];
476 u8 reserved_at_106[0x1];
477 u8 f_eth_prio[0x1];
478 u8 ecn[0x2];
479 u8 dscp[0x6];
480 u8 udp_sport[0x10];
481
482 u8 dei_cfi[0x1];
483 u8 eth_prio[0x3];
484 u8 sl[0x4];
485 u8 port[0x8];
486 u8 rmac_47_32[0x10];
487
488 u8 rmac_31_0[0x20];
489 };
490
491 struct mlx5_ifc_flow_table_nic_cap_bits {
492 u8 nic_rx_multi_path_tirs[0x1];
493 u8 nic_rx_multi_path_tirs_fts[0x1];
494 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
495 u8 reserved_at_3[0x1fd];
496
497 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
498
499 u8 reserved_at_400[0x200];
500
501 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
502
503 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
504
505 u8 reserved_at_a00[0x200];
506
507 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
508
509 u8 reserved_at_e00[0x7200];
510 };
511
512 struct mlx5_ifc_flow_table_eswitch_cap_bits {
513 u8 reserved_at_0[0x200];
514
515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
516
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
518
519 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
520
521 u8 reserved_at_800[0x7800];
522 };
523
524 struct mlx5_ifc_e_switch_cap_bits {
525 u8 vport_svlan_strip[0x1];
526 u8 vport_cvlan_strip[0x1];
527 u8 vport_svlan_insert[0x1];
528 u8 vport_cvlan_insert_if_not_exist[0x1];
529 u8 vport_cvlan_insert_overwrite[0x1];
530 u8 reserved_at_5[0x19];
531 u8 nic_vport_node_guid_modify[0x1];
532 u8 nic_vport_port_guid_modify[0x1];
533
534 u8 vxlan_encap_decap[0x1];
535 u8 nvgre_encap_decap[0x1];
536 u8 reserved_at_22[0x9];
537 u8 log_max_encap_headers[0x5];
538 u8 reserved_2b[0x6];
539 u8 max_encap_header_size[0xa];
540
541 u8 reserved_40[0x7c0];
542
543 };
544
545 struct mlx5_ifc_qos_cap_bits {
546 u8 packet_pacing[0x1];
547 u8 esw_scheduling[0x1];
548 u8 reserved_at_2[0x1e];
549
550 u8 reserved_at_20[0x20];
551
552 u8 packet_pacing_max_rate[0x20];
553
554 u8 packet_pacing_min_rate[0x20];
555
556 u8 reserved_at_80[0x10];
557 u8 packet_pacing_rate_table_size[0x10];
558
559 u8 esw_element_type[0x10];
560 u8 esw_tsar_type[0x10];
561
562 u8 reserved_at_c0[0x10];
563 u8 max_qos_para_vport[0x10];
564
565 u8 max_tsar_bw_share[0x20];
566
567 u8 reserved_at_100[0x700];
568 };
569
570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
571 u8 csum_cap[0x1];
572 u8 vlan_cap[0x1];
573 u8 lro_cap[0x1];
574 u8 lro_psh_flag[0x1];
575 u8 lro_time_stamp[0x1];
576 u8 reserved_at_5[0x3];
577 u8 self_lb_en_modifiable[0x1];
578 u8 reserved_at_9[0x2];
579 u8 max_lso_cap[0x5];
580 u8 multi_pkt_send_wqe[0x2];
581 u8 wqe_inline_mode[0x2];
582 u8 rss_ind_tbl_cap[0x4];
583 u8 reg_umr_sq[0x1];
584 u8 scatter_fcs[0x1];
585 u8 reserved_at_1a[0x1];
586 u8 tunnel_lso_const_out_ip_id[0x1];
587 u8 reserved_at_1c[0x2];
588 u8 tunnel_statless_gre[0x1];
589 u8 tunnel_stateless_vxlan[0x1];
590
591 u8 reserved_at_20[0x20];
592
593 u8 reserved_at_40[0x10];
594 u8 lro_min_mss_size[0x10];
595
596 u8 reserved_at_60[0x120];
597
598 u8 lro_timer_supported_periods[4][0x20];
599
600 u8 reserved_at_200[0x600];
601 };
602
603 struct mlx5_ifc_roce_cap_bits {
604 u8 roce_apm[0x1];
605 u8 reserved_at_1[0x1f];
606
607 u8 reserved_at_20[0x60];
608
609 u8 reserved_at_80[0xc];
610 u8 l3_type[0x4];
611 u8 reserved_at_90[0x8];
612 u8 roce_version[0x8];
613
614 u8 reserved_at_a0[0x10];
615 u8 r_roce_dest_udp_port[0x10];
616
617 u8 r_roce_max_src_udp_port[0x10];
618 u8 r_roce_min_src_udp_port[0x10];
619
620 u8 reserved_at_e0[0x10];
621 u8 roce_address_table_size[0x10];
622
623 u8 reserved_at_100[0x700];
624 };
625
626 enum {
627 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
628 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
629 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
630 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
631 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
636 };
637
638 enum {
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
648 };
649
650 struct mlx5_ifc_atomic_caps_bits {
651 u8 reserved_at_0[0x40];
652
653 u8 atomic_req_8B_endianess_mode[0x2];
654 u8 reserved_at_42[0x4];
655 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
656
657 u8 reserved_at_47[0x19];
658
659 u8 reserved_at_60[0x20];
660
661 u8 reserved_at_80[0x10];
662 u8 atomic_operations[0x10];
663
664 u8 reserved_at_a0[0x10];
665 u8 atomic_size_qp[0x10];
666
667 u8 reserved_at_c0[0x10];
668 u8 atomic_size_dc[0x10];
669
670 u8 reserved_at_e0[0x720];
671 };
672
673 struct mlx5_ifc_odp_cap_bits {
674 u8 reserved_at_0[0x40];
675
676 u8 sig[0x1];
677 u8 reserved_at_41[0x1f];
678
679 u8 reserved_at_60[0x20];
680
681 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
682
683 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
684
685 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
686
687 u8 reserved_at_e0[0x720];
688 };
689
690 struct mlx5_ifc_calc_op {
691 u8 reserved_at_0[0x10];
692 u8 reserved_at_10[0x9];
693 u8 op_swap_endianness[0x1];
694 u8 op_min[0x1];
695 u8 op_xor[0x1];
696 u8 op_or[0x1];
697 u8 op_and[0x1];
698 u8 op_max[0x1];
699 u8 op_add[0x1];
700 };
701
702 struct mlx5_ifc_vector_calc_cap_bits {
703 u8 calc_matrix[0x1];
704 u8 reserved_at_1[0x1f];
705 u8 reserved_at_20[0x8];
706 u8 max_vec_count[0x8];
707 u8 reserved_at_30[0xd];
708 u8 max_chunk_size[0x3];
709 struct mlx5_ifc_calc_op calc0;
710 struct mlx5_ifc_calc_op calc1;
711 struct mlx5_ifc_calc_op calc2;
712 struct mlx5_ifc_calc_op calc3;
713
714 u8 reserved_at_e0[0x720];
715 };
716
717 enum {
718 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
719 MLX5_WQ_TYPE_CYCLIC = 0x1,
720 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
721 };
722
723 enum {
724 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
725 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
726 };
727
728 enum {
729 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
730 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
731 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
732 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
733 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
734 };
735
736 enum {
737 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
738 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
739 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
740 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
741 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
742 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
743 };
744
745 enum {
746 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
747 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
748 };
749
750 enum {
751 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
752 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
753 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
754 };
755
756 enum {
757 MLX5_CAP_PORT_TYPE_IB = 0x0,
758 MLX5_CAP_PORT_TYPE_ETH = 0x1,
759 };
760
761 struct mlx5_ifc_cmd_hca_cap_bits {
762 u8 reserved_at_0[0x80];
763
764 u8 log_max_srq_sz[0x8];
765 u8 log_max_qp_sz[0x8];
766 u8 reserved_at_90[0xb];
767 u8 log_max_qp[0x5];
768
769 u8 reserved_at_a0[0xb];
770 u8 log_max_srq[0x5];
771 u8 reserved_at_b0[0x10];
772
773 u8 reserved_at_c0[0x8];
774 u8 log_max_cq_sz[0x8];
775 u8 reserved_at_d0[0xb];
776 u8 log_max_cq[0x5];
777
778 u8 log_max_eq_sz[0x8];
779 u8 reserved_at_e8[0x2];
780 u8 log_max_mkey[0x6];
781 u8 reserved_at_f0[0xc];
782 u8 log_max_eq[0x4];
783
784 u8 max_indirection[0x8];
785 u8 fixed_buffer_size[0x1];
786 u8 log_max_mrw_sz[0x7];
787 u8 reserved_at_110[0x2];
788 u8 log_max_bsf_list_size[0x6];
789 u8 umr_extended_translation_offset[0x1];
790 u8 null_mkey[0x1];
791 u8 log_max_klm_list_size[0x6];
792
793 u8 reserved_at_120[0xa];
794 u8 log_max_ra_req_dc[0x6];
795 u8 reserved_at_130[0xa];
796 u8 log_max_ra_res_dc[0x6];
797
798 u8 reserved_at_140[0xa];
799 u8 log_max_ra_req_qp[0x6];
800 u8 reserved_at_150[0xa];
801 u8 log_max_ra_res_qp[0x6];
802
803 u8 pad_cap[0x1];
804 u8 cc_query_allowed[0x1];
805 u8 cc_modify_allowed[0x1];
806 u8 reserved_at_163[0xd];
807 u8 gid_table_size[0x10];
808
809 u8 out_of_seq_cnt[0x1];
810 u8 vport_counters[0x1];
811 u8 retransmission_q_counters[0x1];
812 u8 reserved_at_183[0x1];
813 u8 modify_rq_counter_set_id[0x1];
814 u8 reserved_at_185[0x1];
815 u8 max_qp_cnt[0xa];
816 u8 pkey_table_size[0x10];
817
818 u8 vport_group_manager[0x1];
819 u8 vhca_group_manager[0x1];
820 u8 ib_virt[0x1];
821 u8 eth_virt[0x1];
822 u8 reserved_at_1a4[0x1];
823 u8 ets[0x1];
824 u8 nic_flow_table[0x1];
825 u8 eswitch_flow_table[0x1];
826 u8 early_vf_enable[0x1];
827 u8 reserved_at_1a9[0x2];
828 u8 local_ca_ack_delay[0x5];
829 u8 port_module_event[0x1];
830 u8 reserved_at_1b1[0x1];
831 u8 ports_check[0x1];
832 u8 reserved_at_1b3[0x1];
833 u8 disable_link_up[0x1];
834 u8 beacon_led[0x1];
835 u8 port_type[0x2];
836 u8 num_ports[0x8];
837
838 u8 reserved_at_1c0[0x1];
839 u8 pps[0x1];
840 u8 pps_modify[0x1];
841 u8 log_max_msg[0x5];
842 u8 reserved_at_1c8[0x4];
843 u8 max_tc[0x4];
844 u8 reserved_at_1d0[0x1];
845 u8 dcbx[0x1];
846 u8 reserved_at_1d2[0x4];
847 u8 rol_s[0x1];
848 u8 rol_g[0x1];
849 u8 reserved_at_1d8[0x1];
850 u8 wol_s[0x1];
851 u8 wol_g[0x1];
852 u8 wol_a[0x1];
853 u8 wol_b[0x1];
854 u8 wol_m[0x1];
855 u8 wol_u[0x1];
856 u8 wol_p[0x1];
857
858 u8 stat_rate_support[0x10];
859 u8 reserved_at_1f0[0xc];
860 u8 cqe_version[0x4];
861
862 u8 compact_address_vector[0x1];
863 u8 striding_rq[0x1];
864 u8 reserved_at_202[0x2];
865 u8 ipoib_basic_offloads[0x1];
866 u8 reserved_at_205[0xa];
867 u8 drain_sigerr[0x1];
868 u8 cmdif_checksum[0x2];
869 u8 sigerr_cqe[0x1];
870 u8 reserved_at_213[0x1];
871 u8 wq_signature[0x1];
872 u8 sctr_data_cqe[0x1];
873 u8 reserved_at_216[0x1];
874 u8 sho[0x1];
875 u8 tph[0x1];
876 u8 rf[0x1];
877 u8 dct[0x1];
878 u8 qos[0x1];
879 u8 eth_net_offloads[0x1];
880 u8 roce[0x1];
881 u8 atomic[0x1];
882 u8 reserved_at_21f[0x1];
883
884 u8 cq_oi[0x1];
885 u8 cq_resize[0x1];
886 u8 cq_moderation[0x1];
887 u8 reserved_at_223[0x3];
888 u8 cq_eq_remap[0x1];
889 u8 pg[0x1];
890 u8 block_lb_mc[0x1];
891 u8 reserved_at_229[0x1];
892 u8 scqe_break_moderation[0x1];
893 u8 cq_period_start_from_cqe[0x1];
894 u8 cd[0x1];
895 u8 reserved_at_22d[0x1];
896 u8 apm[0x1];
897 u8 vector_calc[0x1];
898 u8 umr_ptr_rlky[0x1];
899 u8 imaicl[0x1];
900 u8 reserved_at_232[0x4];
901 u8 qkv[0x1];
902 u8 pkv[0x1];
903 u8 set_deth_sqpn[0x1];
904 u8 reserved_at_239[0x3];
905 u8 xrc[0x1];
906 u8 ud[0x1];
907 u8 uc[0x1];
908 u8 rc[0x1];
909
910 u8 uar_4k[0x1];
911 u8 reserved_at_241[0x9];
912 u8 uar_sz[0x6];
913 u8 reserved_at_250[0x8];
914 u8 log_pg_sz[0x8];
915
916 u8 bf[0x1];
917 u8 driver_version[0x1];
918 u8 pad_tx_eth_packet[0x1];
919 u8 reserved_at_263[0x8];
920 u8 log_bf_reg_size[0x5];
921
922 u8 reserved_at_270[0xb];
923 u8 lag_master[0x1];
924 u8 num_lag_ports[0x4];
925
926 u8 reserved_at_280[0x10];
927 u8 max_wqe_sz_sq[0x10];
928
929 u8 reserved_at_2a0[0x10];
930 u8 max_wqe_sz_rq[0x10];
931
932 u8 reserved_at_2c0[0x10];
933 u8 max_wqe_sz_sq_dc[0x10];
934
935 u8 reserved_at_2e0[0x7];
936 u8 max_qp_mcg[0x19];
937
938 u8 reserved_at_300[0x18];
939 u8 log_max_mcg[0x8];
940
941 u8 reserved_at_320[0x3];
942 u8 log_max_transport_domain[0x5];
943 u8 reserved_at_328[0x3];
944 u8 log_max_pd[0x5];
945 u8 reserved_at_330[0xb];
946 u8 log_max_xrcd[0x5];
947
948 u8 reserved_at_340[0x8];
949 u8 log_max_flow_counter_bulk[0x8];
950 u8 max_flow_counter[0x10];
951
952
953 u8 reserved_at_360[0x3];
954 u8 log_max_rq[0x5];
955 u8 reserved_at_368[0x3];
956 u8 log_max_sq[0x5];
957 u8 reserved_at_370[0x3];
958 u8 log_max_tir[0x5];
959 u8 reserved_at_378[0x3];
960 u8 log_max_tis[0x5];
961
962 u8 basic_cyclic_rcv_wqe[0x1];
963 u8 reserved_at_381[0x2];
964 u8 log_max_rmp[0x5];
965 u8 reserved_at_388[0x3];
966 u8 log_max_rqt[0x5];
967 u8 reserved_at_390[0x3];
968 u8 log_max_rqt_size[0x5];
969 u8 reserved_at_398[0x3];
970 u8 log_max_tis_per_sq[0x5];
971
972 u8 reserved_at_3a0[0x3];
973 u8 log_max_stride_sz_rq[0x5];
974 u8 reserved_at_3a8[0x3];
975 u8 log_min_stride_sz_rq[0x5];
976 u8 reserved_at_3b0[0x3];
977 u8 log_max_stride_sz_sq[0x5];
978 u8 reserved_at_3b8[0x3];
979 u8 log_min_stride_sz_sq[0x5];
980
981 u8 reserved_at_3c0[0x1b];
982 u8 log_max_wq_sz[0x5];
983
984 u8 nic_vport_change_event[0x1];
985 u8 reserved_at_3e1[0xa];
986 u8 log_max_vlan_list[0x5];
987 u8 reserved_at_3f0[0x3];
988 u8 log_max_current_mc_list[0x5];
989 u8 reserved_at_3f8[0x3];
990 u8 log_max_current_uc_list[0x5];
991
992 u8 reserved_at_400[0x80];
993
994 u8 reserved_at_480[0x3];
995 u8 log_max_l2_table[0x5];
996 u8 reserved_at_488[0x8];
997 u8 log_uar_page_sz[0x10];
998
999 u8 reserved_at_4a0[0x20];
1000 u8 device_frequency_mhz[0x20];
1001 u8 device_frequency_khz[0x20];
1002
1003 u8 reserved_at_500[0x20];
1004 u8 num_of_uars_per_page[0x20];
1005 u8 reserved_at_540[0x40];
1006
1007 u8 reserved_at_580[0x3f];
1008 u8 cqe_compression[0x1];
1009
1010 u8 cqe_compression_timeout[0x10];
1011 u8 cqe_compression_max_num[0x10];
1012
1013 u8 reserved_at_5e0[0x10];
1014 u8 tag_matching[0x1];
1015 u8 rndv_offload_rc[0x1];
1016 u8 rndv_offload_dc[0x1];
1017 u8 log_tag_matching_list_sz[0x5];
1018 u8 reserved_at_5f8[0x3];
1019 u8 log_max_xrq[0x5];
1020
1021 u8 reserved_at_600[0x200];
1022 };
1023
1024 enum mlx5_flow_destination_type {
1025 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1026 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1027 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1028
1029 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1030 };
1031
1032 struct mlx5_ifc_dest_format_struct_bits {
1033 u8 destination_type[0x8];
1034 u8 destination_id[0x18];
1035
1036 u8 reserved_at_20[0x20];
1037 };
1038
1039 struct mlx5_ifc_flow_counter_list_bits {
1040 u8 clear[0x1];
1041 u8 num_of_counters[0xf];
1042 u8 flow_counter_id[0x10];
1043
1044 u8 reserved_at_20[0x20];
1045 };
1046
1047 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1048 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1049 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1050 u8 reserved_at_0[0x40];
1051 };
1052
1053 struct mlx5_ifc_fte_match_param_bits {
1054 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1055
1056 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1057
1058 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1059
1060 u8 reserved_at_600[0xa00];
1061 };
1062
1063 enum {
1064 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1065 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1066 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1067 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1068 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1069 };
1070
1071 struct mlx5_ifc_rx_hash_field_select_bits {
1072 u8 l3_prot_type[0x1];
1073 u8 l4_prot_type[0x1];
1074 u8 selected_fields[0x1e];
1075 };
1076
1077 enum {
1078 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1079 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1080 };
1081
1082 enum {
1083 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1084 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1085 };
1086
1087 struct mlx5_ifc_wq_bits {
1088 u8 wq_type[0x4];
1089 u8 wq_signature[0x1];
1090 u8 end_padding_mode[0x2];
1091 u8 cd_slave[0x1];
1092 u8 reserved_at_8[0x18];
1093
1094 u8 hds_skip_first_sge[0x1];
1095 u8 log2_hds_buf_size[0x3];
1096 u8 reserved_at_24[0x7];
1097 u8 page_offset[0x5];
1098 u8 lwm[0x10];
1099
1100 u8 reserved_at_40[0x8];
1101 u8 pd[0x18];
1102
1103 u8 reserved_at_60[0x8];
1104 u8 uar_page[0x18];
1105
1106 u8 dbr_addr[0x40];
1107
1108 u8 hw_counter[0x20];
1109
1110 u8 sw_counter[0x20];
1111
1112 u8 reserved_at_100[0xc];
1113 u8 log_wq_stride[0x4];
1114 u8 reserved_at_110[0x3];
1115 u8 log_wq_pg_sz[0x5];
1116 u8 reserved_at_118[0x3];
1117 u8 log_wq_sz[0x5];
1118
1119 u8 reserved_at_120[0x15];
1120 u8 log_wqe_num_of_strides[0x3];
1121 u8 two_byte_shift_en[0x1];
1122 u8 reserved_at_139[0x4];
1123 u8 log_wqe_stride_size[0x3];
1124
1125 u8 reserved_at_140[0x4c0];
1126
1127 struct mlx5_ifc_cmd_pas_bits pas[0];
1128 };
1129
1130 struct mlx5_ifc_rq_num_bits {
1131 u8 reserved_at_0[0x8];
1132 u8 rq_num[0x18];
1133 };
1134
1135 struct mlx5_ifc_mac_address_layout_bits {
1136 u8 reserved_at_0[0x10];
1137 u8 mac_addr_47_32[0x10];
1138
1139 u8 mac_addr_31_0[0x20];
1140 };
1141
1142 struct mlx5_ifc_vlan_layout_bits {
1143 u8 reserved_at_0[0x14];
1144 u8 vlan[0x0c];
1145
1146 u8 reserved_at_20[0x20];
1147 };
1148
1149 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1150 u8 reserved_at_0[0xa0];
1151
1152 u8 min_time_between_cnps[0x20];
1153
1154 u8 reserved_at_c0[0x12];
1155 u8 cnp_dscp[0x6];
1156 u8 reserved_at_d8[0x5];
1157 u8 cnp_802p_prio[0x3];
1158
1159 u8 reserved_at_e0[0x720];
1160 };
1161
1162 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1163 u8 reserved_at_0[0x60];
1164
1165 u8 reserved_at_60[0x4];
1166 u8 clamp_tgt_rate[0x1];
1167 u8 reserved_at_65[0x3];
1168 u8 clamp_tgt_rate_after_time_inc[0x1];
1169 u8 reserved_at_69[0x17];
1170
1171 u8 reserved_at_80[0x20];
1172
1173 u8 rpg_time_reset[0x20];
1174
1175 u8 rpg_byte_reset[0x20];
1176
1177 u8 rpg_threshold[0x20];
1178
1179 u8 rpg_max_rate[0x20];
1180
1181 u8 rpg_ai_rate[0x20];
1182
1183 u8 rpg_hai_rate[0x20];
1184
1185 u8 rpg_gd[0x20];
1186
1187 u8 rpg_min_dec_fac[0x20];
1188
1189 u8 rpg_min_rate[0x20];
1190
1191 u8 reserved_at_1c0[0xe0];
1192
1193 u8 rate_to_set_on_first_cnp[0x20];
1194
1195 u8 dce_tcp_g[0x20];
1196
1197 u8 dce_tcp_rtt[0x20];
1198
1199 u8 rate_reduce_monitor_period[0x20];
1200
1201 u8 reserved_at_320[0x20];
1202
1203 u8 initial_alpha_value[0x20];
1204
1205 u8 reserved_at_360[0x4a0];
1206 };
1207
1208 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1209 u8 reserved_at_0[0x80];
1210
1211 u8 rppp_max_rps[0x20];
1212
1213 u8 rpg_time_reset[0x20];
1214
1215 u8 rpg_byte_reset[0x20];
1216
1217 u8 rpg_threshold[0x20];
1218
1219 u8 rpg_max_rate[0x20];
1220
1221 u8 rpg_ai_rate[0x20];
1222
1223 u8 rpg_hai_rate[0x20];
1224
1225 u8 rpg_gd[0x20];
1226
1227 u8 rpg_min_dec_fac[0x20];
1228
1229 u8 rpg_min_rate[0x20];
1230
1231 u8 reserved_at_1c0[0x640];
1232 };
1233
1234 enum {
1235 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1236 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1237 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1238 };
1239
1240 struct mlx5_ifc_resize_field_select_bits {
1241 u8 resize_field_select[0x20];
1242 };
1243
1244 enum {
1245 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1246 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1247 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1248 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1249 };
1250
1251 struct mlx5_ifc_modify_field_select_bits {
1252 u8 modify_field_select[0x20];
1253 };
1254
1255 struct mlx5_ifc_field_select_r_roce_np_bits {
1256 u8 field_select_r_roce_np[0x20];
1257 };
1258
1259 struct mlx5_ifc_field_select_r_roce_rp_bits {
1260 u8 field_select_r_roce_rp[0x20];
1261 };
1262
1263 enum {
1264 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1265 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1266 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1267 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1268 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1269 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1270 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1271 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1272 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1273 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1274 };
1275
1276 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1277 u8 field_select_8021qaurp[0x20];
1278 };
1279
1280 struct mlx5_ifc_phys_layer_cntrs_bits {
1281 u8 time_since_last_clear_high[0x20];
1282
1283 u8 time_since_last_clear_low[0x20];
1284
1285 u8 symbol_errors_high[0x20];
1286
1287 u8 symbol_errors_low[0x20];
1288
1289 u8 sync_headers_errors_high[0x20];
1290
1291 u8 sync_headers_errors_low[0x20];
1292
1293 u8 edpl_bip_errors_lane0_high[0x20];
1294
1295 u8 edpl_bip_errors_lane0_low[0x20];
1296
1297 u8 edpl_bip_errors_lane1_high[0x20];
1298
1299 u8 edpl_bip_errors_lane1_low[0x20];
1300
1301 u8 edpl_bip_errors_lane2_high[0x20];
1302
1303 u8 edpl_bip_errors_lane2_low[0x20];
1304
1305 u8 edpl_bip_errors_lane3_high[0x20];
1306
1307 u8 edpl_bip_errors_lane3_low[0x20];
1308
1309 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1310
1311 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1312
1313 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1314
1315 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1316
1317 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1318
1319 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1320
1321 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1322
1323 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1324
1325 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1326
1327 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1328
1329 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1330
1331 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1332
1333 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1334
1335 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1336
1337 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1338
1339 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1340
1341 u8 rs_fec_corrected_blocks_high[0x20];
1342
1343 u8 rs_fec_corrected_blocks_low[0x20];
1344
1345 u8 rs_fec_uncorrectable_blocks_high[0x20];
1346
1347 u8 rs_fec_uncorrectable_blocks_low[0x20];
1348
1349 u8 rs_fec_no_errors_blocks_high[0x20];
1350
1351 u8 rs_fec_no_errors_blocks_low[0x20];
1352
1353 u8 rs_fec_single_error_blocks_high[0x20];
1354
1355 u8 rs_fec_single_error_blocks_low[0x20];
1356
1357 u8 rs_fec_corrected_symbols_total_high[0x20];
1358
1359 u8 rs_fec_corrected_symbols_total_low[0x20];
1360
1361 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1362
1363 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1364
1365 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1366
1367 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1368
1369 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1370
1371 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1372
1373 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1374
1375 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1376
1377 u8 link_down_events[0x20];
1378
1379 u8 successful_recovery_events[0x20];
1380
1381 u8 reserved_at_640[0x180];
1382 };
1383
1384 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1385 u8 symbol_error_counter[0x10];
1386
1387 u8 link_error_recovery_counter[0x8];
1388
1389 u8 link_downed_counter[0x8];
1390
1391 u8 port_rcv_errors[0x10];
1392
1393 u8 port_rcv_remote_physical_errors[0x10];
1394
1395 u8 port_rcv_switch_relay_errors[0x10];
1396
1397 u8 port_xmit_discards[0x10];
1398
1399 u8 port_xmit_constraint_errors[0x8];
1400
1401 u8 port_rcv_constraint_errors[0x8];
1402
1403 u8 reserved_at_70[0x8];
1404
1405 u8 link_overrun_errors[0x8];
1406
1407 u8 reserved_at_80[0x10];
1408
1409 u8 vl_15_dropped[0x10];
1410
1411 u8 reserved_at_a0[0xa0];
1412 };
1413
1414 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1415 u8 transmit_queue_high[0x20];
1416
1417 u8 transmit_queue_low[0x20];
1418
1419 u8 reserved_at_40[0x780];
1420 };
1421
1422 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1423 u8 rx_octets_high[0x20];
1424
1425 u8 rx_octets_low[0x20];
1426
1427 u8 reserved_at_40[0xc0];
1428
1429 u8 rx_frames_high[0x20];
1430
1431 u8 rx_frames_low[0x20];
1432
1433 u8 tx_octets_high[0x20];
1434
1435 u8 tx_octets_low[0x20];
1436
1437 u8 reserved_at_180[0xc0];
1438
1439 u8 tx_frames_high[0x20];
1440
1441 u8 tx_frames_low[0x20];
1442
1443 u8 rx_pause_high[0x20];
1444
1445 u8 rx_pause_low[0x20];
1446
1447 u8 rx_pause_duration_high[0x20];
1448
1449 u8 rx_pause_duration_low[0x20];
1450
1451 u8 tx_pause_high[0x20];
1452
1453 u8 tx_pause_low[0x20];
1454
1455 u8 tx_pause_duration_high[0x20];
1456
1457 u8 tx_pause_duration_low[0x20];
1458
1459 u8 rx_pause_transition_high[0x20];
1460
1461 u8 rx_pause_transition_low[0x20];
1462
1463 u8 reserved_at_3c0[0x400];
1464 };
1465
1466 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1467 u8 port_transmit_wait_high[0x20];
1468
1469 u8 port_transmit_wait_low[0x20];
1470
1471 u8 reserved_at_40[0x780];
1472 };
1473
1474 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1475 u8 dot3stats_alignment_errors_high[0x20];
1476
1477 u8 dot3stats_alignment_errors_low[0x20];
1478
1479 u8 dot3stats_fcs_errors_high[0x20];
1480
1481 u8 dot3stats_fcs_errors_low[0x20];
1482
1483 u8 dot3stats_single_collision_frames_high[0x20];
1484
1485 u8 dot3stats_single_collision_frames_low[0x20];
1486
1487 u8 dot3stats_multiple_collision_frames_high[0x20];
1488
1489 u8 dot3stats_multiple_collision_frames_low[0x20];
1490
1491 u8 dot3stats_sqe_test_errors_high[0x20];
1492
1493 u8 dot3stats_sqe_test_errors_low[0x20];
1494
1495 u8 dot3stats_deferred_transmissions_high[0x20];
1496
1497 u8 dot3stats_deferred_transmissions_low[0x20];
1498
1499 u8 dot3stats_late_collisions_high[0x20];
1500
1501 u8 dot3stats_late_collisions_low[0x20];
1502
1503 u8 dot3stats_excessive_collisions_high[0x20];
1504
1505 u8 dot3stats_excessive_collisions_low[0x20];
1506
1507 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1508
1509 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1510
1511 u8 dot3stats_carrier_sense_errors_high[0x20];
1512
1513 u8 dot3stats_carrier_sense_errors_low[0x20];
1514
1515 u8 dot3stats_frame_too_longs_high[0x20];
1516
1517 u8 dot3stats_frame_too_longs_low[0x20];
1518
1519 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1520
1521 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1522
1523 u8 dot3stats_symbol_errors_high[0x20];
1524
1525 u8 dot3stats_symbol_errors_low[0x20];
1526
1527 u8 dot3control_in_unknown_opcodes_high[0x20];
1528
1529 u8 dot3control_in_unknown_opcodes_low[0x20];
1530
1531 u8 dot3in_pause_frames_high[0x20];
1532
1533 u8 dot3in_pause_frames_low[0x20];
1534
1535 u8 dot3out_pause_frames_high[0x20];
1536
1537 u8 dot3out_pause_frames_low[0x20];
1538
1539 u8 reserved_at_400[0x3c0];
1540 };
1541
1542 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1543 u8 ether_stats_drop_events_high[0x20];
1544
1545 u8 ether_stats_drop_events_low[0x20];
1546
1547 u8 ether_stats_octets_high[0x20];
1548
1549 u8 ether_stats_octets_low[0x20];
1550
1551 u8 ether_stats_pkts_high[0x20];
1552
1553 u8 ether_stats_pkts_low[0x20];
1554
1555 u8 ether_stats_broadcast_pkts_high[0x20];
1556
1557 u8 ether_stats_broadcast_pkts_low[0x20];
1558
1559 u8 ether_stats_multicast_pkts_high[0x20];
1560
1561 u8 ether_stats_multicast_pkts_low[0x20];
1562
1563 u8 ether_stats_crc_align_errors_high[0x20];
1564
1565 u8 ether_stats_crc_align_errors_low[0x20];
1566
1567 u8 ether_stats_undersize_pkts_high[0x20];
1568
1569 u8 ether_stats_undersize_pkts_low[0x20];
1570
1571 u8 ether_stats_oversize_pkts_high[0x20];
1572
1573 u8 ether_stats_oversize_pkts_low[0x20];
1574
1575 u8 ether_stats_fragments_high[0x20];
1576
1577 u8 ether_stats_fragments_low[0x20];
1578
1579 u8 ether_stats_jabbers_high[0x20];
1580
1581 u8 ether_stats_jabbers_low[0x20];
1582
1583 u8 ether_stats_collisions_high[0x20];
1584
1585 u8 ether_stats_collisions_low[0x20];
1586
1587 u8 ether_stats_pkts64octets_high[0x20];
1588
1589 u8 ether_stats_pkts64octets_low[0x20];
1590
1591 u8 ether_stats_pkts65to127octets_high[0x20];
1592
1593 u8 ether_stats_pkts65to127octets_low[0x20];
1594
1595 u8 ether_stats_pkts128to255octets_high[0x20];
1596
1597 u8 ether_stats_pkts128to255octets_low[0x20];
1598
1599 u8 ether_stats_pkts256to511octets_high[0x20];
1600
1601 u8 ether_stats_pkts256to511octets_low[0x20];
1602
1603 u8 ether_stats_pkts512to1023octets_high[0x20];
1604
1605 u8 ether_stats_pkts512to1023octets_low[0x20];
1606
1607 u8 ether_stats_pkts1024to1518octets_high[0x20];
1608
1609 u8 ether_stats_pkts1024to1518octets_low[0x20];
1610
1611 u8 ether_stats_pkts1519to2047octets_high[0x20];
1612
1613 u8 ether_stats_pkts1519to2047octets_low[0x20];
1614
1615 u8 ether_stats_pkts2048to4095octets_high[0x20];
1616
1617 u8 ether_stats_pkts2048to4095octets_low[0x20];
1618
1619 u8 ether_stats_pkts4096to8191octets_high[0x20];
1620
1621 u8 ether_stats_pkts4096to8191octets_low[0x20];
1622
1623 u8 ether_stats_pkts8192to10239octets_high[0x20];
1624
1625 u8 ether_stats_pkts8192to10239octets_low[0x20];
1626
1627 u8 reserved_at_540[0x280];
1628 };
1629
1630 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1631 u8 if_in_octets_high[0x20];
1632
1633 u8 if_in_octets_low[0x20];
1634
1635 u8 if_in_ucast_pkts_high[0x20];
1636
1637 u8 if_in_ucast_pkts_low[0x20];
1638
1639 u8 if_in_discards_high[0x20];
1640
1641 u8 if_in_discards_low[0x20];
1642
1643 u8 if_in_errors_high[0x20];
1644
1645 u8 if_in_errors_low[0x20];
1646
1647 u8 if_in_unknown_protos_high[0x20];
1648
1649 u8 if_in_unknown_protos_low[0x20];
1650
1651 u8 if_out_octets_high[0x20];
1652
1653 u8 if_out_octets_low[0x20];
1654
1655 u8 if_out_ucast_pkts_high[0x20];
1656
1657 u8 if_out_ucast_pkts_low[0x20];
1658
1659 u8 if_out_discards_high[0x20];
1660
1661 u8 if_out_discards_low[0x20];
1662
1663 u8 if_out_errors_high[0x20];
1664
1665 u8 if_out_errors_low[0x20];
1666
1667 u8 if_in_multicast_pkts_high[0x20];
1668
1669 u8 if_in_multicast_pkts_low[0x20];
1670
1671 u8 if_in_broadcast_pkts_high[0x20];
1672
1673 u8 if_in_broadcast_pkts_low[0x20];
1674
1675 u8 if_out_multicast_pkts_high[0x20];
1676
1677 u8 if_out_multicast_pkts_low[0x20];
1678
1679 u8 if_out_broadcast_pkts_high[0x20];
1680
1681 u8 if_out_broadcast_pkts_low[0x20];
1682
1683 u8 reserved_at_340[0x480];
1684 };
1685
1686 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1687 u8 a_frames_transmitted_ok_high[0x20];
1688
1689 u8 a_frames_transmitted_ok_low[0x20];
1690
1691 u8 a_frames_received_ok_high[0x20];
1692
1693 u8 a_frames_received_ok_low[0x20];
1694
1695 u8 a_frame_check_sequence_errors_high[0x20];
1696
1697 u8 a_frame_check_sequence_errors_low[0x20];
1698
1699 u8 a_alignment_errors_high[0x20];
1700
1701 u8 a_alignment_errors_low[0x20];
1702
1703 u8 a_octets_transmitted_ok_high[0x20];
1704
1705 u8 a_octets_transmitted_ok_low[0x20];
1706
1707 u8 a_octets_received_ok_high[0x20];
1708
1709 u8 a_octets_received_ok_low[0x20];
1710
1711 u8 a_multicast_frames_xmitted_ok_high[0x20];
1712
1713 u8 a_multicast_frames_xmitted_ok_low[0x20];
1714
1715 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1716
1717 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1718
1719 u8 a_multicast_frames_received_ok_high[0x20];
1720
1721 u8 a_multicast_frames_received_ok_low[0x20];
1722
1723 u8 a_broadcast_frames_received_ok_high[0x20];
1724
1725 u8 a_broadcast_frames_received_ok_low[0x20];
1726
1727 u8 a_in_range_length_errors_high[0x20];
1728
1729 u8 a_in_range_length_errors_low[0x20];
1730
1731 u8 a_out_of_range_length_field_high[0x20];
1732
1733 u8 a_out_of_range_length_field_low[0x20];
1734
1735 u8 a_frame_too_long_errors_high[0x20];
1736
1737 u8 a_frame_too_long_errors_low[0x20];
1738
1739 u8 a_symbol_error_during_carrier_high[0x20];
1740
1741 u8 a_symbol_error_during_carrier_low[0x20];
1742
1743 u8 a_mac_control_frames_transmitted_high[0x20];
1744
1745 u8 a_mac_control_frames_transmitted_low[0x20];
1746
1747 u8 a_mac_control_frames_received_high[0x20];
1748
1749 u8 a_mac_control_frames_received_low[0x20];
1750
1751 u8 a_unsupported_opcodes_received_high[0x20];
1752
1753 u8 a_unsupported_opcodes_received_low[0x20];
1754
1755 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1756
1757 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1758
1759 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1760
1761 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1762
1763 u8 reserved_at_4c0[0x300];
1764 };
1765
1766 struct mlx5_ifc_cmd_inter_comp_event_bits {
1767 u8 command_completion_vector[0x20];
1768
1769 u8 reserved_at_20[0xc0];
1770 };
1771
1772 struct mlx5_ifc_stall_vl_event_bits {
1773 u8 reserved_at_0[0x18];
1774 u8 port_num[0x1];
1775 u8 reserved_at_19[0x3];
1776 u8 vl[0x4];
1777
1778 u8 reserved_at_20[0xa0];
1779 };
1780
1781 struct mlx5_ifc_db_bf_congestion_event_bits {
1782 u8 event_subtype[0x8];
1783 u8 reserved_at_8[0x8];
1784 u8 congestion_level[0x8];
1785 u8 reserved_at_18[0x8];
1786
1787 u8 reserved_at_20[0xa0];
1788 };
1789
1790 struct mlx5_ifc_gpio_event_bits {
1791 u8 reserved_at_0[0x60];
1792
1793 u8 gpio_event_hi[0x20];
1794
1795 u8 gpio_event_lo[0x20];
1796
1797 u8 reserved_at_a0[0x40];
1798 };
1799
1800 struct mlx5_ifc_port_state_change_event_bits {
1801 u8 reserved_at_0[0x40];
1802
1803 u8 port_num[0x4];
1804 u8 reserved_at_44[0x1c];
1805
1806 u8 reserved_at_60[0x80];
1807 };
1808
1809 struct mlx5_ifc_dropped_packet_logged_bits {
1810 u8 reserved_at_0[0xe0];
1811 };
1812
1813 enum {
1814 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1815 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1816 };
1817
1818 struct mlx5_ifc_cq_error_bits {
1819 u8 reserved_at_0[0x8];
1820 u8 cqn[0x18];
1821
1822 u8 reserved_at_20[0x20];
1823
1824 u8 reserved_at_40[0x18];
1825 u8 syndrome[0x8];
1826
1827 u8 reserved_at_60[0x80];
1828 };
1829
1830 struct mlx5_ifc_rdma_page_fault_event_bits {
1831 u8 bytes_committed[0x20];
1832
1833 u8 r_key[0x20];
1834
1835 u8 reserved_at_40[0x10];
1836 u8 packet_len[0x10];
1837
1838 u8 rdma_op_len[0x20];
1839
1840 u8 rdma_va[0x40];
1841
1842 u8 reserved_at_c0[0x5];
1843 u8 rdma[0x1];
1844 u8 write[0x1];
1845 u8 requestor[0x1];
1846 u8 qp_number[0x18];
1847 };
1848
1849 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1850 u8 bytes_committed[0x20];
1851
1852 u8 reserved_at_20[0x10];
1853 u8 wqe_index[0x10];
1854
1855 u8 reserved_at_40[0x10];
1856 u8 len[0x10];
1857
1858 u8 reserved_at_60[0x60];
1859
1860 u8 reserved_at_c0[0x5];
1861 u8 rdma[0x1];
1862 u8 write_read[0x1];
1863 u8 requestor[0x1];
1864 u8 qpn[0x18];
1865 };
1866
1867 struct mlx5_ifc_qp_events_bits {
1868 u8 reserved_at_0[0xa0];
1869
1870 u8 type[0x8];
1871 u8 reserved_at_a8[0x18];
1872
1873 u8 reserved_at_c0[0x8];
1874 u8 qpn_rqn_sqn[0x18];
1875 };
1876
1877 struct mlx5_ifc_dct_events_bits {
1878 u8 reserved_at_0[0xc0];
1879
1880 u8 reserved_at_c0[0x8];
1881 u8 dct_number[0x18];
1882 };
1883
1884 struct mlx5_ifc_comp_event_bits {
1885 u8 reserved_at_0[0xc0];
1886
1887 u8 reserved_at_c0[0x8];
1888 u8 cq_number[0x18];
1889 };
1890
1891 enum {
1892 MLX5_QPC_STATE_RST = 0x0,
1893 MLX5_QPC_STATE_INIT = 0x1,
1894 MLX5_QPC_STATE_RTR = 0x2,
1895 MLX5_QPC_STATE_RTS = 0x3,
1896 MLX5_QPC_STATE_SQER = 0x4,
1897 MLX5_QPC_STATE_ERR = 0x6,
1898 MLX5_QPC_STATE_SQD = 0x7,
1899 MLX5_QPC_STATE_SUSPENDED = 0x9,
1900 };
1901
1902 enum {
1903 MLX5_QPC_ST_RC = 0x0,
1904 MLX5_QPC_ST_UC = 0x1,
1905 MLX5_QPC_ST_UD = 0x2,
1906 MLX5_QPC_ST_XRC = 0x3,
1907 MLX5_QPC_ST_DCI = 0x5,
1908 MLX5_QPC_ST_QP0 = 0x7,
1909 MLX5_QPC_ST_QP1 = 0x8,
1910 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1911 MLX5_QPC_ST_REG_UMR = 0xc,
1912 };
1913
1914 enum {
1915 MLX5_QPC_PM_STATE_ARMED = 0x0,
1916 MLX5_QPC_PM_STATE_REARM = 0x1,
1917 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1918 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1919 };
1920
1921 enum {
1922 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1923 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1924 };
1925
1926 enum {
1927 MLX5_QPC_MTU_256_BYTES = 0x1,
1928 MLX5_QPC_MTU_512_BYTES = 0x2,
1929 MLX5_QPC_MTU_1K_BYTES = 0x3,
1930 MLX5_QPC_MTU_2K_BYTES = 0x4,
1931 MLX5_QPC_MTU_4K_BYTES = 0x5,
1932 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1933 };
1934
1935 enum {
1936 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1937 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1938 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1939 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1940 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1941 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1942 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1943 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1944 };
1945
1946 enum {
1947 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1948 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1949 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1950 };
1951
1952 enum {
1953 MLX5_QPC_CS_RES_DISABLE = 0x0,
1954 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1955 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1956 };
1957
1958 struct mlx5_ifc_qpc_bits {
1959 u8 state[0x4];
1960 u8 lag_tx_port_affinity[0x4];
1961 u8 st[0x8];
1962 u8 reserved_at_10[0x3];
1963 u8 pm_state[0x2];
1964 u8 reserved_at_15[0x7];
1965 u8 end_padding_mode[0x2];
1966 u8 reserved_at_1e[0x2];
1967
1968 u8 wq_signature[0x1];
1969 u8 block_lb_mc[0x1];
1970 u8 atomic_like_write_en[0x1];
1971 u8 latency_sensitive[0x1];
1972 u8 reserved_at_24[0x1];
1973 u8 drain_sigerr[0x1];
1974 u8 reserved_at_26[0x2];
1975 u8 pd[0x18];
1976
1977 u8 mtu[0x3];
1978 u8 log_msg_max[0x5];
1979 u8 reserved_at_48[0x1];
1980 u8 log_rq_size[0x4];
1981 u8 log_rq_stride[0x3];
1982 u8 no_sq[0x1];
1983 u8 log_sq_size[0x4];
1984 u8 reserved_at_55[0x6];
1985 u8 rlky[0x1];
1986 u8 ulp_stateless_offload_mode[0x4];
1987
1988 u8 counter_set_id[0x8];
1989 u8 uar_page[0x18];
1990
1991 u8 reserved_at_80[0x8];
1992 u8 user_index[0x18];
1993
1994 u8 reserved_at_a0[0x3];
1995 u8 log_page_size[0x5];
1996 u8 remote_qpn[0x18];
1997
1998 struct mlx5_ifc_ads_bits primary_address_path;
1999
2000 struct mlx5_ifc_ads_bits secondary_address_path;
2001
2002 u8 log_ack_req_freq[0x4];
2003 u8 reserved_at_384[0x4];
2004 u8 log_sra_max[0x3];
2005 u8 reserved_at_38b[0x2];
2006 u8 retry_count[0x3];
2007 u8 rnr_retry[0x3];
2008 u8 reserved_at_393[0x1];
2009 u8 fre[0x1];
2010 u8 cur_rnr_retry[0x3];
2011 u8 cur_retry_count[0x3];
2012 u8 reserved_at_39b[0x5];
2013
2014 u8 reserved_at_3a0[0x20];
2015
2016 u8 reserved_at_3c0[0x8];
2017 u8 next_send_psn[0x18];
2018
2019 u8 reserved_at_3e0[0x8];
2020 u8 cqn_snd[0x18];
2021
2022 u8 reserved_at_400[0x8];
2023 u8 deth_sqpn[0x18];
2024
2025 u8 reserved_at_420[0x20];
2026
2027 u8 reserved_at_440[0x8];
2028 u8 last_acked_psn[0x18];
2029
2030 u8 reserved_at_460[0x8];
2031 u8 ssn[0x18];
2032
2033 u8 reserved_at_480[0x8];
2034 u8 log_rra_max[0x3];
2035 u8 reserved_at_48b[0x1];
2036 u8 atomic_mode[0x4];
2037 u8 rre[0x1];
2038 u8 rwe[0x1];
2039 u8 rae[0x1];
2040 u8 reserved_at_493[0x1];
2041 u8 page_offset[0x6];
2042 u8 reserved_at_49a[0x3];
2043 u8 cd_slave_receive[0x1];
2044 u8 cd_slave_send[0x1];
2045 u8 cd_master[0x1];
2046
2047 u8 reserved_at_4a0[0x3];
2048 u8 min_rnr_nak[0x5];
2049 u8 next_rcv_psn[0x18];
2050
2051 u8 reserved_at_4c0[0x8];
2052 u8 xrcd[0x18];
2053
2054 u8 reserved_at_4e0[0x8];
2055 u8 cqn_rcv[0x18];
2056
2057 u8 dbr_addr[0x40];
2058
2059 u8 q_key[0x20];
2060
2061 u8 reserved_at_560[0x5];
2062 u8 rq_type[0x3];
2063 u8 srqn_rmpn_xrqn[0x18];
2064
2065 u8 reserved_at_580[0x8];
2066 u8 rmsn[0x18];
2067
2068 u8 hw_sq_wqebb_counter[0x10];
2069 u8 sw_sq_wqebb_counter[0x10];
2070
2071 u8 hw_rq_counter[0x20];
2072
2073 u8 sw_rq_counter[0x20];
2074
2075 u8 reserved_at_600[0x20];
2076
2077 u8 reserved_at_620[0xf];
2078 u8 cgs[0x1];
2079 u8 cs_req[0x8];
2080 u8 cs_res[0x8];
2081
2082 u8 dc_access_key[0x40];
2083
2084 u8 reserved_at_680[0xc0];
2085 };
2086
2087 struct mlx5_ifc_roce_addr_layout_bits {
2088 u8 source_l3_address[16][0x8];
2089
2090 u8 reserved_at_80[0x3];
2091 u8 vlan_valid[0x1];
2092 u8 vlan_id[0xc];
2093 u8 source_mac_47_32[0x10];
2094
2095 u8 source_mac_31_0[0x20];
2096
2097 u8 reserved_at_c0[0x14];
2098 u8 roce_l3_type[0x4];
2099 u8 roce_version[0x8];
2100
2101 u8 reserved_at_e0[0x20];
2102 };
2103
2104 union mlx5_ifc_hca_cap_union_bits {
2105 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2106 struct mlx5_ifc_odp_cap_bits odp_cap;
2107 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2108 struct mlx5_ifc_roce_cap_bits roce_cap;
2109 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2110 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2111 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2112 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2113 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2114 struct mlx5_ifc_qos_cap_bits qos_cap;
2115 u8 reserved_at_0[0x8000];
2116 };
2117
2118 enum {
2119 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2120 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2121 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2122 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2123 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2124 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2125 };
2126
2127 struct mlx5_ifc_flow_context_bits {
2128 u8 reserved_at_0[0x20];
2129
2130 u8 group_id[0x20];
2131
2132 u8 reserved_at_40[0x8];
2133 u8 flow_tag[0x18];
2134
2135 u8 reserved_at_60[0x10];
2136 u8 action[0x10];
2137
2138 u8 reserved_at_80[0x8];
2139 u8 destination_list_size[0x18];
2140
2141 u8 reserved_at_a0[0x8];
2142 u8 flow_counter_list_size[0x18];
2143
2144 u8 encap_id[0x20];
2145
2146 u8 reserved_at_e0[0x120];
2147
2148 struct mlx5_ifc_fte_match_param_bits match_value;
2149
2150 u8 reserved_at_1200[0x600];
2151
2152 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2153 };
2154
2155 enum {
2156 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2157 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2158 };
2159
2160 struct mlx5_ifc_xrc_srqc_bits {
2161 u8 state[0x4];
2162 u8 log_xrc_srq_size[0x4];
2163 u8 reserved_at_8[0x18];
2164
2165 u8 wq_signature[0x1];
2166 u8 cont_srq[0x1];
2167 u8 reserved_at_22[0x1];
2168 u8 rlky[0x1];
2169 u8 basic_cyclic_rcv_wqe[0x1];
2170 u8 log_rq_stride[0x3];
2171 u8 xrcd[0x18];
2172
2173 u8 page_offset[0x6];
2174 u8 reserved_at_46[0x2];
2175 u8 cqn[0x18];
2176
2177 u8 reserved_at_60[0x20];
2178
2179 u8 user_index_equal_xrc_srqn[0x1];
2180 u8 reserved_at_81[0x1];
2181 u8 log_page_size[0x6];
2182 u8 user_index[0x18];
2183
2184 u8 reserved_at_a0[0x20];
2185
2186 u8 reserved_at_c0[0x8];
2187 u8 pd[0x18];
2188
2189 u8 lwm[0x10];
2190 u8 wqe_cnt[0x10];
2191
2192 u8 reserved_at_100[0x40];
2193
2194 u8 db_record_addr_h[0x20];
2195
2196 u8 db_record_addr_l[0x1e];
2197 u8 reserved_at_17e[0x2];
2198
2199 u8 reserved_at_180[0x80];
2200 };
2201
2202 struct mlx5_ifc_traffic_counter_bits {
2203 u8 packets[0x40];
2204
2205 u8 octets[0x40];
2206 };
2207
2208 struct mlx5_ifc_tisc_bits {
2209 u8 strict_lag_tx_port_affinity[0x1];
2210 u8 reserved_at_1[0x3];
2211 u8 lag_tx_port_affinity[0x04];
2212
2213 u8 reserved_at_8[0x4];
2214 u8 prio[0x4];
2215 u8 reserved_at_10[0x10];
2216
2217 u8 reserved_at_20[0x100];
2218
2219 u8 reserved_at_120[0x8];
2220 u8 transport_domain[0x18];
2221
2222 u8 reserved_at_140[0x3c0];
2223 };
2224
2225 enum {
2226 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2227 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2228 };
2229
2230 enum {
2231 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2232 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2233 };
2234
2235 enum {
2236 MLX5_RX_HASH_FN_NONE = 0x0,
2237 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2238 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2239 };
2240
2241 enum {
2242 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2243 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2244 };
2245
2246 struct mlx5_ifc_tirc_bits {
2247 u8 reserved_at_0[0x20];
2248
2249 u8 disp_type[0x4];
2250 u8 reserved_at_24[0x1c];
2251
2252 u8 reserved_at_40[0x40];
2253
2254 u8 reserved_at_80[0x4];
2255 u8 lro_timeout_period_usecs[0x10];
2256 u8 lro_enable_mask[0x4];
2257 u8 lro_max_ip_payload_size[0x8];
2258
2259 u8 reserved_at_a0[0x40];
2260
2261 u8 reserved_at_e0[0x8];
2262 u8 inline_rqn[0x18];
2263
2264 u8 rx_hash_symmetric[0x1];
2265 u8 reserved_at_101[0x1];
2266 u8 tunneled_offload_en[0x1];
2267 u8 reserved_at_103[0x5];
2268 u8 indirect_table[0x18];
2269
2270 u8 rx_hash_fn[0x4];
2271 u8 reserved_at_124[0x2];
2272 u8 self_lb_block[0x2];
2273 u8 transport_domain[0x18];
2274
2275 u8 rx_hash_toeplitz_key[10][0x20];
2276
2277 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2278
2279 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2280
2281 u8 reserved_at_2c0[0x4c0];
2282 };
2283
2284 enum {
2285 MLX5_SRQC_STATE_GOOD = 0x0,
2286 MLX5_SRQC_STATE_ERROR = 0x1,
2287 };
2288
2289 struct mlx5_ifc_srqc_bits {
2290 u8 state[0x4];
2291 u8 log_srq_size[0x4];
2292 u8 reserved_at_8[0x18];
2293
2294 u8 wq_signature[0x1];
2295 u8 cont_srq[0x1];
2296 u8 reserved_at_22[0x1];
2297 u8 rlky[0x1];
2298 u8 reserved_at_24[0x1];
2299 u8 log_rq_stride[0x3];
2300 u8 xrcd[0x18];
2301
2302 u8 page_offset[0x6];
2303 u8 reserved_at_46[0x2];
2304 u8 cqn[0x18];
2305
2306 u8 reserved_at_60[0x20];
2307
2308 u8 reserved_at_80[0x2];
2309 u8 log_page_size[0x6];
2310 u8 reserved_at_88[0x18];
2311
2312 u8 reserved_at_a0[0x20];
2313
2314 u8 reserved_at_c0[0x8];
2315 u8 pd[0x18];
2316
2317 u8 lwm[0x10];
2318 u8 wqe_cnt[0x10];
2319
2320 u8 reserved_at_100[0x40];
2321
2322 u8 dbr_addr[0x40];
2323
2324 u8 reserved_at_180[0x80];
2325 };
2326
2327 enum {
2328 MLX5_SQC_STATE_RST = 0x0,
2329 MLX5_SQC_STATE_RDY = 0x1,
2330 MLX5_SQC_STATE_ERR = 0x3,
2331 };
2332
2333 struct mlx5_ifc_sqc_bits {
2334 u8 rlky[0x1];
2335 u8 cd_master[0x1];
2336 u8 fre[0x1];
2337 u8 flush_in_error_en[0x1];
2338 u8 reserved_at_4[0x1];
2339 u8 min_wqe_inline_mode[0x3];
2340 u8 state[0x4];
2341 u8 reg_umr[0x1];
2342 u8 reserved_at_d[0x13];
2343
2344 u8 reserved_at_20[0x8];
2345 u8 user_index[0x18];
2346
2347 u8 reserved_at_40[0x8];
2348 u8 cqn[0x18];
2349
2350 u8 reserved_at_60[0x90];
2351
2352 u8 packet_pacing_rate_limit_index[0x10];
2353 u8 tis_lst_sz[0x10];
2354 u8 reserved_at_110[0x10];
2355
2356 u8 reserved_at_120[0x40];
2357
2358 u8 reserved_at_160[0x8];
2359 u8 tis_num_0[0x18];
2360
2361 struct mlx5_ifc_wq_bits wq;
2362 };
2363
2364 enum {
2365 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2366 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2367 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2368 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2369 };
2370
2371 struct mlx5_ifc_scheduling_context_bits {
2372 u8 element_type[0x8];
2373 u8 reserved_at_8[0x18];
2374
2375 u8 element_attributes[0x20];
2376
2377 u8 parent_element_id[0x20];
2378
2379 u8 reserved_at_60[0x40];
2380
2381 u8 bw_share[0x20];
2382
2383 u8 max_average_bw[0x20];
2384
2385 u8 reserved_at_e0[0x120];
2386 };
2387
2388 struct mlx5_ifc_rqtc_bits {
2389 u8 reserved_at_0[0xa0];
2390
2391 u8 reserved_at_a0[0x10];
2392 u8 rqt_max_size[0x10];
2393
2394 u8 reserved_at_c0[0x10];
2395 u8 rqt_actual_size[0x10];
2396
2397 u8 reserved_at_e0[0x6a0];
2398
2399 struct mlx5_ifc_rq_num_bits rq_num[0];
2400 };
2401
2402 enum {
2403 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2404 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2405 };
2406
2407 enum {
2408 MLX5_RQC_STATE_RST = 0x0,
2409 MLX5_RQC_STATE_RDY = 0x1,
2410 MLX5_RQC_STATE_ERR = 0x3,
2411 };
2412
2413 struct mlx5_ifc_rqc_bits {
2414 u8 rlky[0x1];
2415 u8 reserved_at_1[0x1];
2416 u8 scatter_fcs[0x1];
2417 u8 vsd[0x1];
2418 u8 mem_rq_type[0x4];
2419 u8 state[0x4];
2420 u8 reserved_at_c[0x1];
2421 u8 flush_in_error_en[0x1];
2422 u8 reserved_at_e[0x12];
2423
2424 u8 reserved_at_20[0x8];
2425 u8 user_index[0x18];
2426
2427 u8 reserved_at_40[0x8];
2428 u8 cqn[0x18];
2429
2430 u8 counter_set_id[0x8];
2431 u8 reserved_at_68[0x18];
2432
2433 u8 reserved_at_80[0x8];
2434 u8 rmpn[0x18];
2435
2436 u8 reserved_at_a0[0xe0];
2437
2438 struct mlx5_ifc_wq_bits wq;
2439 };
2440
2441 enum {
2442 MLX5_RMPC_STATE_RDY = 0x1,
2443 MLX5_RMPC_STATE_ERR = 0x3,
2444 };
2445
2446 struct mlx5_ifc_rmpc_bits {
2447 u8 reserved_at_0[0x8];
2448 u8 state[0x4];
2449 u8 reserved_at_c[0x14];
2450
2451 u8 basic_cyclic_rcv_wqe[0x1];
2452 u8 reserved_at_21[0x1f];
2453
2454 u8 reserved_at_40[0x140];
2455
2456 struct mlx5_ifc_wq_bits wq;
2457 };
2458
2459 struct mlx5_ifc_nic_vport_context_bits {
2460 u8 reserved_at_0[0x5];
2461 u8 min_wqe_inline_mode[0x3];
2462 u8 reserved_at_8[0x17];
2463 u8 roce_en[0x1];
2464
2465 u8 arm_change_event[0x1];
2466 u8 reserved_at_21[0x1a];
2467 u8 event_on_mtu[0x1];
2468 u8 event_on_promisc_change[0x1];
2469 u8 event_on_vlan_change[0x1];
2470 u8 event_on_mc_address_change[0x1];
2471 u8 event_on_uc_address_change[0x1];
2472
2473 u8 reserved_at_40[0xf0];
2474
2475 u8 mtu[0x10];
2476
2477 u8 system_image_guid[0x40];
2478 u8 port_guid[0x40];
2479 u8 node_guid[0x40];
2480
2481 u8 reserved_at_200[0x140];
2482 u8 qkey_violation_counter[0x10];
2483 u8 reserved_at_350[0x430];
2484
2485 u8 promisc_uc[0x1];
2486 u8 promisc_mc[0x1];
2487 u8 promisc_all[0x1];
2488 u8 reserved_at_783[0x2];
2489 u8 allowed_list_type[0x3];
2490 u8 reserved_at_788[0xc];
2491 u8 allowed_list_size[0xc];
2492
2493 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2494
2495 u8 reserved_at_7e0[0x20];
2496
2497 u8 current_uc_mac_address[0][0x40];
2498 };
2499
2500 enum {
2501 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2502 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2503 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2504 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2505 };
2506
2507 struct mlx5_ifc_mkc_bits {
2508 u8 reserved_at_0[0x1];
2509 u8 free[0x1];
2510 u8 reserved_at_2[0xd];
2511 u8 small_fence_on_rdma_read_response[0x1];
2512 u8 umr_en[0x1];
2513 u8 a[0x1];
2514 u8 rw[0x1];
2515 u8 rr[0x1];
2516 u8 lw[0x1];
2517 u8 lr[0x1];
2518 u8 access_mode[0x2];
2519 u8 reserved_at_18[0x8];
2520
2521 u8 qpn[0x18];
2522 u8 mkey_7_0[0x8];
2523
2524 u8 reserved_at_40[0x20];
2525
2526 u8 length64[0x1];
2527 u8 bsf_en[0x1];
2528 u8 sync_umr[0x1];
2529 u8 reserved_at_63[0x2];
2530 u8 expected_sigerr_count[0x1];
2531 u8 reserved_at_66[0x1];
2532 u8 en_rinval[0x1];
2533 u8 pd[0x18];
2534
2535 u8 start_addr[0x40];
2536
2537 u8 len[0x40];
2538
2539 u8 bsf_octword_size[0x20];
2540
2541 u8 reserved_at_120[0x80];
2542
2543 u8 translations_octword_size[0x20];
2544
2545 u8 reserved_at_1c0[0x1b];
2546 u8 log_page_size[0x5];
2547
2548 u8 reserved_at_1e0[0x20];
2549 };
2550
2551 struct mlx5_ifc_pkey_bits {
2552 u8 reserved_at_0[0x10];
2553 u8 pkey[0x10];
2554 };
2555
2556 struct mlx5_ifc_array128_auto_bits {
2557 u8 array128_auto[16][0x8];
2558 };
2559
2560 struct mlx5_ifc_hca_vport_context_bits {
2561 u8 field_select[0x20];
2562
2563 u8 reserved_at_20[0xe0];
2564
2565 u8 sm_virt_aware[0x1];
2566 u8 has_smi[0x1];
2567 u8 has_raw[0x1];
2568 u8 grh_required[0x1];
2569 u8 reserved_at_104[0xc];
2570 u8 port_physical_state[0x4];
2571 u8 vport_state_policy[0x4];
2572 u8 port_state[0x4];
2573 u8 vport_state[0x4];
2574
2575 u8 reserved_at_120[0x20];
2576
2577 u8 system_image_guid[0x40];
2578
2579 u8 port_guid[0x40];
2580
2581 u8 node_guid[0x40];
2582
2583 u8 cap_mask1[0x20];
2584
2585 u8 cap_mask1_field_select[0x20];
2586
2587 u8 cap_mask2[0x20];
2588
2589 u8 cap_mask2_field_select[0x20];
2590
2591 u8 reserved_at_280[0x80];
2592
2593 u8 lid[0x10];
2594 u8 reserved_at_310[0x4];
2595 u8 init_type_reply[0x4];
2596 u8 lmc[0x3];
2597 u8 subnet_timeout[0x5];
2598
2599 u8 sm_lid[0x10];
2600 u8 sm_sl[0x4];
2601 u8 reserved_at_334[0xc];
2602
2603 u8 qkey_violation_counter[0x10];
2604 u8 pkey_violation_counter[0x10];
2605
2606 u8 reserved_at_360[0xca0];
2607 };
2608
2609 struct mlx5_ifc_esw_vport_context_bits {
2610 u8 reserved_at_0[0x3];
2611 u8 vport_svlan_strip[0x1];
2612 u8 vport_cvlan_strip[0x1];
2613 u8 vport_svlan_insert[0x1];
2614 u8 vport_cvlan_insert[0x2];
2615 u8 reserved_at_8[0x18];
2616
2617 u8 reserved_at_20[0x20];
2618
2619 u8 svlan_cfi[0x1];
2620 u8 svlan_pcp[0x3];
2621 u8 svlan_id[0xc];
2622 u8 cvlan_cfi[0x1];
2623 u8 cvlan_pcp[0x3];
2624 u8 cvlan_id[0xc];
2625
2626 u8 reserved_at_60[0x7a0];
2627 };
2628
2629 enum {
2630 MLX5_EQC_STATUS_OK = 0x0,
2631 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2632 };
2633
2634 enum {
2635 MLX5_EQC_ST_ARMED = 0x9,
2636 MLX5_EQC_ST_FIRED = 0xa,
2637 };
2638
2639 struct mlx5_ifc_eqc_bits {
2640 u8 status[0x4];
2641 u8 reserved_at_4[0x9];
2642 u8 ec[0x1];
2643 u8 oi[0x1];
2644 u8 reserved_at_f[0x5];
2645 u8 st[0x4];
2646 u8 reserved_at_18[0x8];
2647
2648 u8 reserved_at_20[0x20];
2649
2650 u8 reserved_at_40[0x14];
2651 u8 page_offset[0x6];
2652 u8 reserved_at_5a[0x6];
2653
2654 u8 reserved_at_60[0x3];
2655 u8 log_eq_size[0x5];
2656 u8 uar_page[0x18];
2657
2658 u8 reserved_at_80[0x20];
2659
2660 u8 reserved_at_a0[0x18];
2661 u8 intr[0x8];
2662
2663 u8 reserved_at_c0[0x3];
2664 u8 log_page_size[0x5];
2665 u8 reserved_at_c8[0x18];
2666
2667 u8 reserved_at_e0[0x60];
2668
2669 u8 reserved_at_140[0x8];
2670 u8 consumer_counter[0x18];
2671
2672 u8 reserved_at_160[0x8];
2673 u8 producer_counter[0x18];
2674
2675 u8 reserved_at_180[0x80];
2676 };
2677
2678 enum {
2679 MLX5_DCTC_STATE_ACTIVE = 0x0,
2680 MLX5_DCTC_STATE_DRAINING = 0x1,
2681 MLX5_DCTC_STATE_DRAINED = 0x2,
2682 };
2683
2684 enum {
2685 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2686 MLX5_DCTC_CS_RES_NA = 0x1,
2687 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2688 };
2689
2690 enum {
2691 MLX5_DCTC_MTU_256_BYTES = 0x1,
2692 MLX5_DCTC_MTU_512_BYTES = 0x2,
2693 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2694 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2695 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2696 };
2697
2698 struct mlx5_ifc_dctc_bits {
2699 u8 reserved_at_0[0x4];
2700 u8 state[0x4];
2701 u8 reserved_at_8[0x18];
2702
2703 u8 reserved_at_20[0x8];
2704 u8 user_index[0x18];
2705
2706 u8 reserved_at_40[0x8];
2707 u8 cqn[0x18];
2708
2709 u8 counter_set_id[0x8];
2710 u8 atomic_mode[0x4];
2711 u8 rre[0x1];
2712 u8 rwe[0x1];
2713 u8 rae[0x1];
2714 u8 atomic_like_write_en[0x1];
2715 u8 latency_sensitive[0x1];
2716 u8 rlky[0x1];
2717 u8 free_ar[0x1];
2718 u8 reserved_at_73[0xd];
2719
2720 u8 reserved_at_80[0x8];
2721 u8 cs_res[0x8];
2722 u8 reserved_at_90[0x3];
2723 u8 min_rnr_nak[0x5];
2724 u8 reserved_at_98[0x8];
2725
2726 u8 reserved_at_a0[0x8];
2727 u8 srqn_xrqn[0x18];
2728
2729 u8 reserved_at_c0[0x8];
2730 u8 pd[0x18];
2731
2732 u8 tclass[0x8];
2733 u8 reserved_at_e8[0x4];
2734 u8 flow_label[0x14];
2735
2736 u8 dc_access_key[0x40];
2737
2738 u8 reserved_at_140[0x5];
2739 u8 mtu[0x3];
2740 u8 port[0x8];
2741 u8 pkey_index[0x10];
2742
2743 u8 reserved_at_160[0x8];
2744 u8 my_addr_index[0x8];
2745 u8 reserved_at_170[0x8];
2746 u8 hop_limit[0x8];
2747
2748 u8 dc_access_key_violation_count[0x20];
2749
2750 u8 reserved_at_1a0[0x14];
2751 u8 dei_cfi[0x1];
2752 u8 eth_prio[0x3];
2753 u8 ecn[0x2];
2754 u8 dscp[0x6];
2755
2756 u8 reserved_at_1c0[0x40];
2757 };
2758
2759 enum {
2760 MLX5_CQC_STATUS_OK = 0x0,
2761 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2762 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2763 };
2764
2765 enum {
2766 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2767 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2768 };
2769
2770 enum {
2771 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2772 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2773 MLX5_CQC_ST_FIRED = 0xa,
2774 };
2775
2776 enum {
2777 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2778 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2779 MLX5_CQ_PERIOD_NUM_MODES
2780 };
2781
2782 struct mlx5_ifc_cqc_bits {
2783 u8 status[0x4];
2784 u8 reserved_at_4[0x4];
2785 u8 cqe_sz[0x3];
2786 u8 cc[0x1];
2787 u8 reserved_at_c[0x1];
2788 u8 scqe_break_moderation_en[0x1];
2789 u8 oi[0x1];
2790 u8 cq_period_mode[0x2];
2791 u8 cqe_comp_en[0x1];
2792 u8 mini_cqe_res_format[0x2];
2793 u8 st[0x4];
2794 u8 reserved_at_18[0x8];
2795
2796 u8 reserved_at_20[0x20];
2797
2798 u8 reserved_at_40[0x14];
2799 u8 page_offset[0x6];
2800 u8 reserved_at_5a[0x6];
2801
2802 u8 reserved_at_60[0x3];
2803 u8 log_cq_size[0x5];
2804 u8 uar_page[0x18];
2805
2806 u8 reserved_at_80[0x4];
2807 u8 cq_period[0xc];
2808 u8 cq_max_count[0x10];
2809
2810 u8 reserved_at_a0[0x18];
2811 u8 c_eqn[0x8];
2812
2813 u8 reserved_at_c0[0x3];
2814 u8 log_page_size[0x5];
2815 u8 reserved_at_c8[0x18];
2816
2817 u8 reserved_at_e0[0x20];
2818
2819 u8 reserved_at_100[0x8];
2820 u8 last_notified_index[0x18];
2821
2822 u8 reserved_at_120[0x8];
2823 u8 last_solicit_index[0x18];
2824
2825 u8 reserved_at_140[0x8];
2826 u8 consumer_counter[0x18];
2827
2828 u8 reserved_at_160[0x8];
2829 u8 producer_counter[0x18];
2830
2831 u8 reserved_at_180[0x40];
2832
2833 u8 dbr_addr[0x40];
2834 };
2835
2836 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2837 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2838 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2839 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2840 u8 reserved_at_0[0x800];
2841 };
2842
2843 struct mlx5_ifc_query_adapter_param_block_bits {
2844 u8 reserved_at_0[0xc0];
2845
2846 u8 reserved_at_c0[0x8];
2847 u8 ieee_vendor_id[0x18];
2848
2849 u8 reserved_at_e0[0x10];
2850 u8 vsd_vendor_id[0x10];
2851
2852 u8 vsd[208][0x8];
2853
2854 u8 vsd_contd_psid[16][0x8];
2855 };
2856
2857 enum {
2858 MLX5_XRQC_STATE_GOOD = 0x0,
2859 MLX5_XRQC_STATE_ERROR = 0x1,
2860 };
2861
2862 enum {
2863 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2864 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2865 };
2866
2867 enum {
2868 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2869 };
2870
2871 struct mlx5_ifc_tag_matching_topology_context_bits {
2872 u8 log_matching_list_sz[0x4];
2873 u8 reserved_at_4[0xc];
2874 u8 append_next_index[0x10];
2875
2876 u8 sw_phase_cnt[0x10];
2877 u8 hw_phase_cnt[0x10];
2878
2879 u8 reserved_at_40[0x40];
2880 };
2881
2882 struct mlx5_ifc_xrqc_bits {
2883 u8 state[0x4];
2884 u8 rlkey[0x1];
2885 u8 reserved_at_5[0xf];
2886 u8 topology[0x4];
2887 u8 reserved_at_18[0x4];
2888 u8 offload[0x4];
2889
2890 u8 reserved_at_20[0x8];
2891 u8 user_index[0x18];
2892
2893 u8 reserved_at_40[0x8];
2894 u8 cqn[0x18];
2895
2896 u8 reserved_at_60[0xa0];
2897
2898 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2899
2900 u8 reserved_at_180[0x880];
2901
2902 struct mlx5_ifc_wq_bits wq;
2903 };
2904
2905 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2906 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2907 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2908 u8 reserved_at_0[0x20];
2909 };
2910
2911 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2912 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2913 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2914 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2915 u8 reserved_at_0[0x20];
2916 };
2917
2918 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2919 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2920 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2921 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2922 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2923 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2924 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2925 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2926 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2927 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2928 u8 reserved_at_0[0x7c0];
2929 };
2930
2931 union mlx5_ifc_event_auto_bits {
2932 struct mlx5_ifc_comp_event_bits comp_event;
2933 struct mlx5_ifc_dct_events_bits dct_events;
2934 struct mlx5_ifc_qp_events_bits qp_events;
2935 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2936 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2937 struct mlx5_ifc_cq_error_bits cq_error;
2938 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2939 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2940 struct mlx5_ifc_gpio_event_bits gpio_event;
2941 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2942 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2943 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2944 u8 reserved_at_0[0xe0];
2945 };
2946
2947 struct mlx5_ifc_health_buffer_bits {
2948 u8 reserved_at_0[0x100];
2949
2950 u8 assert_existptr[0x20];
2951
2952 u8 assert_callra[0x20];
2953
2954 u8 reserved_at_140[0x40];
2955
2956 u8 fw_version[0x20];
2957
2958 u8 hw_id[0x20];
2959
2960 u8 reserved_at_1c0[0x20];
2961
2962 u8 irisc_index[0x8];
2963 u8 synd[0x8];
2964 u8 ext_synd[0x10];
2965 };
2966
2967 struct mlx5_ifc_register_loopback_control_bits {
2968 u8 no_lb[0x1];
2969 u8 reserved_at_1[0x7];
2970 u8 port[0x8];
2971 u8 reserved_at_10[0x10];
2972
2973 u8 reserved_at_20[0x60];
2974 };
2975
2976 struct mlx5_ifc_vport_tc_element_bits {
2977 u8 traffic_class[0x4];
2978 u8 reserved_at_4[0xc];
2979 u8 vport_number[0x10];
2980 };
2981
2982 struct mlx5_ifc_vport_element_bits {
2983 u8 reserved_at_0[0x10];
2984 u8 vport_number[0x10];
2985 };
2986
2987 enum {
2988 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
2989 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
2990 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
2991 };
2992
2993 struct mlx5_ifc_tsar_element_bits {
2994 u8 reserved_at_0[0x8];
2995 u8 tsar_type[0x8];
2996 u8 reserved_at_10[0x10];
2997 };
2998
2999 struct mlx5_ifc_teardown_hca_out_bits {
3000 u8 status[0x8];
3001 u8 reserved_at_8[0x18];
3002
3003 u8 syndrome[0x20];
3004
3005 u8 reserved_at_40[0x40];
3006 };
3007
3008 enum {
3009 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3010 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3011 };
3012
3013 struct mlx5_ifc_teardown_hca_in_bits {
3014 u8 opcode[0x10];
3015 u8 reserved_at_10[0x10];
3016
3017 u8 reserved_at_20[0x10];
3018 u8 op_mod[0x10];
3019
3020 u8 reserved_at_40[0x10];
3021 u8 profile[0x10];
3022
3023 u8 reserved_at_60[0x20];
3024 };
3025
3026 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3027 u8 status[0x8];
3028 u8 reserved_at_8[0x18];
3029
3030 u8 syndrome[0x20];
3031
3032 u8 reserved_at_40[0x40];
3033 };
3034
3035 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3036 u8 opcode[0x10];
3037 u8 reserved_at_10[0x10];
3038
3039 u8 reserved_at_20[0x10];
3040 u8 op_mod[0x10];
3041
3042 u8 reserved_at_40[0x8];
3043 u8 qpn[0x18];
3044
3045 u8 reserved_at_60[0x20];
3046
3047 u8 opt_param_mask[0x20];
3048
3049 u8 reserved_at_a0[0x20];
3050
3051 struct mlx5_ifc_qpc_bits qpc;
3052
3053 u8 reserved_at_800[0x80];
3054 };
3055
3056 struct mlx5_ifc_sqd2rts_qp_out_bits {
3057 u8 status[0x8];
3058 u8 reserved_at_8[0x18];
3059
3060 u8 syndrome[0x20];
3061
3062 u8 reserved_at_40[0x40];
3063 };
3064
3065 struct mlx5_ifc_sqd2rts_qp_in_bits {
3066 u8 opcode[0x10];
3067 u8 reserved_at_10[0x10];
3068
3069 u8 reserved_at_20[0x10];
3070 u8 op_mod[0x10];
3071
3072 u8 reserved_at_40[0x8];
3073 u8 qpn[0x18];
3074
3075 u8 reserved_at_60[0x20];
3076
3077 u8 opt_param_mask[0x20];
3078
3079 u8 reserved_at_a0[0x20];
3080
3081 struct mlx5_ifc_qpc_bits qpc;
3082
3083 u8 reserved_at_800[0x80];
3084 };
3085
3086 struct mlx5_ifc_set_roce_address_out_bits {
3087 u8 status[0x8];
3088 u8 reserved_at_8[0x18];
3089
3090 u8 syndrome[0x20];
3091
3092 u8 reserved_at_40[0x40];
3093 };
3094
3095 struct mlx5_ifc_set_roce_address_in_bits {
3096 u8 opcode[0x10];
3097 u8 reserved_at_10[0x10];
3098
3099 u8 reserved_at_20[0x10];
3100 u8 op_mod[0x10];
3101
3102 u8 roce_address_index[0x10];
3103 u8 reserved_at_50[0x10];
3104
3105 u8 reserved_at_60[0x20];
3106
3107 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3108 };
3109
3110 struct mlx5_ifc_set_mad_demux_out_bits {
3111 u8 status[0x8];
3112 u8 reserved_at_8[0x18];
3113
3114 u8 syndrome[0x20];
3115
3116 u8 reserved_at_40[0x40];
3117 };
3118
3119 enum {
3120 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3121 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3122 };
3123
3124 struct mlx5_ifc_set_mad_demux_in_bits {
3125 u8 opcode[0x10];
3126 u8 reserved_at_10[0x10];
3127
3128 u8 reserved_at_20[0x10];
3129 u8 op_mod[0x10];
3130
3131 u8 reserved_at_40[0x20];
3132
3133 u8 reserved_at_60[0x6];
3134 u8 demux_mode[0x2];
3135 u8 reserved_at_68[0x18];
3136 };
3137
3138 struct mlx5_ifc_set_l2_table_entry_out_bits {
3139 u8 status[0x8];
3140 u8 reserved_at_8[0x18];
3141
3142 u8 syndrome[0x20];
3143
3144 u8 reserved_at_40[0x40];
3145 };
3146
3147 struct mlx5_ifc_set_l2_table_entry_in_bits {
3148 u8 opcode[0x10];
3149 u8 reserved_at_10[0x10];
3150
3151 u8 reserved_at_20[0x10];
3152 u8 op_mod[0x10];
3153
3154 u8 reserved_at_40[0x60];
3155
3156 u8 reserved_at_a0[0x8];
3157 u8 table_index[0x18];
3158
3159 u8 reserved_at_c0[0x20];
3160
3161 u8 reserved_at_e0[0x13];
3162 u8 vlan_valid[0x1];
3163 u8 vlan[0xc];
3164
3165 struct mlx5_ifc_mac_address_layout_bits mac_address;
3166
3167 u8 reserved_at_140[0xc0];
3168 };
3169
3170 struct mlx5_ifc_set_issi_out_bits {
3171 u8 status[0x8];
3172 u8 reserved_at_8[0x18];
3173
3174 u8 syndrome[0x20];
3175
3176 u8 reserved_at_40[0x40];
3177 };
3178
3179 struct mlx5_ifc_set_issi_in_bits {
3180 u8 opcode[0x10];
3181 u8 reserved_at_10[0x10];
3182
3183 u8 reserved_at_20[0x10];
3184 u8 op_mod[0x10];
3185
3186 u8 reserved_at_40[0x10];
3187 u8 current_issi[0x10];
3188
3189 u8 reserved_at_60[0x20];
3190 };
3191
3192 struct mlx5_ifc_set_hca_cap_out_bits {
3193 u8 status[0x8];
3194 u8 reserved_at_8[0x18];
3195
3196 u8 syndrome[0x20];
3197
3198 u8 reserved_at_40[0x40];
3199 };
3200
3201 struct mlx5_ifc_set_hca_cap_in_bits {
3202 u8 opcode[0x10];
3203 u8 reserved_at_10[0x10];
3204
3205 u8 reserved_at_20[0x10];
3206 u8 op_mod[0x10];
3207
3208 u8 reserved_at_40[0x40];
3209
3210 union mlx5_ifc_hca_cap_union_bits capability;
3211 };
3212
3213 enum {
3214 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3215 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3216 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3217 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3218 };
3219
3220 struct mlx5_ifc_set_fte_out_bits {
3221 u8 status[0x8];
3222 u8 reserved_at_8[0x18];
3223
3224 u8 syndrome[0x20];
3225
3226 u8 reserved_at_40[0x40];
3227 };
3228
3229 struct mlx5_ifc_set_fte_in_bits {
3230 u8 opcode[0x10];
3231 u8 reserved_at_10[0x10];
3232
3233 u8 reserved_at_20[0x10];
3234 u8 op_mod[0x10];
3235
3236 u8 other_vport[0x1];
3237 u8 reserved_at_41[0xf];
3238 u8 vport_number[0x10];
3239
3240 u8 reserved_at_60[0x20];
3241
3242 u8 table_type[0x8];
3243 u8 reserved_at_88[0x18];
3244
3245 u8 reserved_at_a0[0x8];
3246 u8 table_id[0x18];
3247
3248 u8 reserved_at_c0[0x18];
3249 u8 modify_enable_mask[0x8];
3250
3251 u8 reserved_at_e0[0x20];
3252
3253 u8 flow_index[0x20];
3254
3255 u8 reserved_at_120[0xe0];
3256
3257 struct mlx5_ifc_flow_context_bits flow_context;
3258 };
3259
3260 struct mlx5_ifc_rts2rts_qp_out_bits {
3261 u8 status[0x8];
3262 u8 reserved_at_8[0x18];
3263
3264 u8 syndrome[0x20];
3265
3266 u8 reserved_at_40[0x40];
3267 };
3268
3269 struct mlx5_ifc_rts2rts_qp_in_bits {
3270 u8 opcode[0x10];
3271 u8 reserved_at_10[0x10];
3272
3273 u8 reserved_at_20[0x10];
3274 u8 op_mod[0x10];
3275
3276 u8 reserved_at_40[0x8];
3277 u8 qpn[0x18];
3278
3279 u8 reserved_at_60[0x20];
3280
3281 u8 opt_param_mask[0x20];
3282
3283 u8 reserved_at_a0[0x20];
3284
3285 struct mlx5_ifc_qpc_bits qpc;
3286
3287 u8 reserved_at_800[0x80];
3288 };
3289
3290 struct mlx5_ifc_rtr2rts_qp_out_bits {
3291 u8 status[0x8];
3292 u8 reserved_at_8[0x18];
3293
3294 u8 syndrome[0x20];
3295
3296 u8 reserved_at_40[0x40];
3297 };
3298
3299 struct mlx5_ifc_rtr2rts_qp_in_bits {
3300 u8 opcode[0x10];
3301 u8 reserved_at_10[0x10];
3302
3303 u8 reserved_at_20[0x10];
3304 u8 op_mod[0x10];
3305
3306 u8 reserved_at_40[0x8];
3307 u8 qpn[0x18];
3308
3309 u8 reserved_at_60[0x20];
3310
3311 u8 opt_param_mask[0x20];
3312
3313 u8 reserved_at_a0[0x20];
3314
3315 struct mlx5_ifc_qpc_bits qpc;
3316
3317 u8 reserved_at_800[0x80];
3318 };
3319
3320 struct mlx5_ifc_rst2init_qp_out_bits {
3321 u8 status[0x8];
3322 u8 reserved_at_8[0x18];
3323
3324 u8 syndrome[0x20];
3325
3326 u8 reserved_at_40[0x40];
3327 };
3328
3329 struct mlx5_ifc_rst2init_qp_in_bits {
3330 u8 opcode[0x10];
3331 u8 reserved_at_10[0x10];
3332
3333 u8 reserved_at_20[0x10];
3334 u8 op_mod[0x10];
3335
3336 u8 reserved_at_40[0x8];
3337 u8 qpn[0x18];
3338
3339 u8 reserved_at_60[0x20];
3340
3341 u8 opt_param_mask[0x20];
3342
3343 u8 reserved_at_a0[0x20];
3344
3345 struct mlx5_ifc_qpc_bits qpc;
3346
3347 u8 reserved_at_800[0x80];
3348 };
3349
3350 struct mlx5_ifc_query_xrq_out_bits {
3351 u8 status[0x8];
3352 u8 reserved_at_8[0x18];
3353
3354 u8 syndrome[0x20];
3355
3356 u8 reserved_at_40[0x40];
3357
3358 struct mlx5_ifc_xrqc_bits xrq_context;
3359 };
3360
3361 struct mlx5_ifc_query_xrq_in_bits {
3362 u8 opcode[0x10];
3363 u8 reserved_at_10[0x10];
3364
3365 u8 reserved_at_20[0x10];
3366 u8 op_mod[0x10];
3367
3368 u8 reserved_at_40[0x8];
3369 u8 xrqn[0x18];
3370
3371 u8 reserved_at_60[0x20];
3372 };
3373
3374 struct mlx5_ifc_query_xrc_srq_out_bits {
3375 u8 status[0x8];
3376 u8 reserved_at_8[0x18];
3377
3378 u8 syndrome[0x20];
3379
3380 u8 reserved_at_40[0x40];
3381
3382 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3383
3384 u8 reserved_at_280[0x600];
3385
3386 u8 pas[0][0x40];
3387 };
3388
3389 struct mlx5_ifc_query_xrc_srq_in_bits {
3390 u8 opcode[0x10];
3391 u8 reserved_at_10[0x10];
3392
3393 u8 reserved_at_20[0x10];
3394 u8 op_mod[0x10];
3395
3396 u8 reserved_at_40[0x8];
3397 u8 xrc_srqn[0x18];
3398
3399 u8 reserved_at_60[0x20];
3400 };
3401
3402 enum {
3403 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3404 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3405 };
3406
3407 struct mlx5_ifc_query_vport_state_out_bits {
3408 u8 status[0x8];
3409 u8 reserved_at_8[0x18];
3410
3411 u8 syndrome[0x20];
3412
3413 u8 reserved_at_40[0x20];
3414
3415 u8 reserved_at_60[0x18];
3416 u8 admin_state[0x4];
3417 u8 state[0x4];
3418 };
3419
3420 enum {
3421 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3422 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3423 };
3424
3425 struct mlx5_ifc_query_vport_state_in_bits {
3426 u8 opcode[0x10];
3427 u8 reserved_at_10[0x10];
3428
3429 u8 reserved_at_20[0x10];
3430 u8 op_mod[0x10];
3431
3432 u8 other_vport[0x1];
3433 u8 reserved_at_41[0xf];
3434 u8 vport_number[0x10];
3435
3436 u8 reserved_at_60[0x20];
3437 };
3438
3439 struct mlx5_ifc_query_vport_counter_out_bits {
3440 u8 status[0x8];
3441 u8 reserved_at_8[0x18];
3442
3443 u8 syndrome[0x20];
3444
3445 u8 reserved_at_40[0x40];
3446
3447 struct mlx5_ifc_traffic_counter_bits received_errors;
3448
3449 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3450
3451 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3452
3453 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3454
3455 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3456
3457 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3458
3459 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3460
3461 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3462
3463 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3464
3465 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3466
3467 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3468
3469 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3470
3471 u8 reserved_at_680[0xa00];
3472 };
3473
3474 enum {
3475 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3476 };
3477
3478 struct mlx5_ifc_query_vport_counter_in_bits {
3479 u8 opcode[0x10];
3480 u8 reserved_at_10[0x10];
3481
3482 u8 reserved_at_20[0x10];
3483 u8 op_mod[0x10];
3484
3485 u8 other_vport[0x1];
3486 u8 reserved_at_41[0xb];
3487 u8 port_num[0x4];
3488 u8 vport_number[0x10];
3489
3490 u8 reserved_at_60[0x60];
3491
3492 u8 clear[0x1];
3493 u8 reserved_at_c1[0x1f];
3494
3495 u8 reserved_at_e0[0x20];
3496 };
3497
3498 struct mlx5_ifc_query_tis_out_bits {
3499 u8 status[0x8];
3500 u8 reserved_at_8[0x18];
3501
3502 u8 syndrome[0x20];
3503
3504 u8 reserved_at_40[0x40];
3505
3506 struct mlx5_ifc_tisc_bits tis_context;
3507 };
3508
3509 struct mlx5_ifc_query_tis_in_bits {
3510 u8 opcode[0x10];
3511 u8 reserved_at_10[0x10];
3512
3513 u8 reserved_at_20[0x10];
3514 u8 op_mod[0x10];
3515
3516 u8 reserved_at_40[0x8];
3517 u8 tisn[0x18];
3518
3519 u8 reserved_at_60[0x20];
3520 };
3521
3522 struct mlx5_ifc_query_tir_out_bits {
3523 u8 status[0x8];
3524 u8 reserved_at_8[0x18];
3525
3526 u8 syndrome[0x20];
3527
3528 u8 reserved_at_40[0xc0];
3529
3530 struct mlx5_ifc_tirc_bits tir_context;
3531 };
3532
3533 struct mlx5_ifc_query_tir_in_bits {
3534 u8 opcode[0x10];
3535 u8 reserved_at_10[0x10];
3536
3537 u8 reserved_at_20[0x10];
3538 u8 op_mod[0x10];
3539
3540 u8 reserved_at_40[0x8];
3541 u8 tirn[0x18];
3542
3543 u8 reserved_at_60[0x20];
3544 };
3545
3546 struct mlx5_ifc_query_srq_out_bits {
3547 u8 status[0x8];
3548 u8 reserved_at_8[0x18];
3549
3550 u8 syndrome[0x20];
3551
3552 u8 reserved_at_40[0x40];
3553
3554 struct mlx5_ifc_srqc_bits srq_context_entry;
3555
3556 u8 reserved_at_280[0x600];
3557
3558 u8 pas[0][0x40];
3559 };
3560
3561 struct mlx5_ifc_query_srq_in_bits {
3562 u8 opcode[0x10];
3563 u8 reserved_at_10[0x10];
3564
3565 u8 reserved_at_20[0x10];
3566 u8 op_mod[0x10];
3567
3568 u8 reserved_at_40[0x8];
3569 u8 srqn[0x18];
3570
3571 u8 reserved_at_60[0x20];
3572 };
3573
3574 struct mlx5_ifc_query_sq_out_bits {
3575 u8 status[0x8];
3576 u8 reserved_at_8[0x18];
3577
3578 u8 syndrome[0x20];
3579
3580 u8 reserved_at_40[0xc0];
3581
3582 struct mlx5_ifc_sqc_bits sq_context;
3583 };
3584
3585 struct mlx5_ifc_query_sq_in_bits {
3586 u8 opcode[0x10];
3587 u8 reserved_at_10[0x10];
3588
3589 u8 reserved_at_20[0x10];
3590 u8 op_mod[0x10];
3591
3592 u8 reserved_at_40[0x8];
3593 u8 sqn[0x18];
3594
3595 u8 reserved_at_60[0x20];
3596 };
3597
3598 struct mlx5_ifc_query_special_contexts_out_bits {
3599 u8 status[0x8];
3600 u8 reserved_at_8[0x18];
3601
3602 u8 syndrome[0x20];
3603
3604 u8 dump_fill_mkey[0x20];
3605
3606 u8 resd_lkey[0x20];
3607
3608 u8 null_mkey[0x20];
3609
3610 u8 reserved_at_a0[0x60];
3611 };
3612
3613 struct mlx5_ifc_query_special_contexts_in_bits {
3614 u8 opcode[0x10];
3615 u8 reserved_at_10[0x10];
3616
3617 u8 reserved_at_20[0x10];
3618 u8 op_mod[0x10];
3619
3620 u8 reserved_at_40[0x40];
3621 };
3622
3623 struct mlx5_ifc_query_scheduling_element_out_bits {
3624 u8 opcode[0x10];
3625 u8 reserved_at_10[0x10];
3626
3627 u8 reserved_at_20[0x10];
3628 u8 op_mod[0x10];
3629
3630 u8 reserved_at_40[0xc0];
3631
3632 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3633
3634 u8 reserved_at_300[0x100];
3635 };
3636
3637 enum {
3638 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3639 };
3640
3641 struct mlx5_ifc_query_scheduling_element_in_bits {
3642 u8 opcode[0x10];
3643 u8 reserved_at_10[0x10];
3644
3645 u8 reserved_at_20[0x10];
3646 u8 op_mod[0x10];
3647
3648 u8 scheduling_hierarchy[0x8];
3649 u8 reserved_at_48[0x18];
3650
3651 u8 scheduling_element_id[0x20];
3652
3653 u8 reserved_at_80[0x180];
3654 };
3655
3656 struct mlx5_ifc_query_rqt_out_bits {
3657 u8 status[0x8];
3658 u8 reserved_at_8[0x18];
3659
3660 u8 syndrome[0x20];
3661
3662 u8 reserved_at_40[0xc0];
3663
3664 struct mlx5_ifc_rqtc_bits rqt_context;
3665 };
3666
3667 struct mlx5_ifc_query_rqt_in_bits {
3668 u8 opcode[0x10];
3669 u8 reserved_at_10[0x10];
3670
3671 u8 reserved_at_20[0x10];
3672 u8 op_mod[0x10];
3673
3674 u8 reserved_at_40[0x8];
3675 u8 rqtn[0x18];
3676
3677 u8 reserved_at_60[0x20];
3678 };
3679
3680 struct mlx5_ifc_query_rq_out_bits {
3681 u8 status[0x8];
3682 u8 reserved_at_8[0x18];
3683
3684 u8 syndrome[0x20];
3685
3686 u8 reserved_at_40[0xc0];
3687
3688 struct mlx5_ifc_rqc_bits rq_context;
3689 };
3690
3691 struct mlx5_ifc_query_rq_in_bits {
3692 u8 opcode[0x10];
3693 u8 reserved_at_10[0x10];
3694
3695 u8 reserved_at_20[0x10];
3696 u8 op_mod[0x10];
3697
3698 u8 reserved_at_40[0x8];
3699 u8 rqn[0x18];
3700
3701 u8 reserved_at_60[0x20];
3702 };
3703
3704 struct mlx5_ifc_query_roce_address_out_bits {
3705 u8 status[0x8];
3706 u8 reserved_at_8[0x18];
3707
3708 u8 syndrome[0x20];
3709
3710 u8 reserved_at_40[0x40];
3711
3712 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3713 };
3714
3715 struct mlx5_ifc_query_roce_address_in_bits {
3716 u8 opcode[0x10];
3717 u8 reserved_at_10[0x10];
3718
3719 u8 reserved_at_20[0x10];
3720 u8 op_mod[0x10];
3721
3722 u8 roce_address_index[0x10];
3723 u8 reserved_at_50[0x10];
3724
3725 u8 reserved_at_60[0x20];
3726 };
3727
3728 struct mlx5_ifc_query_rmp_out_bits {
3729 u8 status[0x8];
3730 u8 reserved_at_8[0x18];
3731
3732 u8 syndrome[0x20];
3733
3734 u8 reserved_at_40[0xc0];
3735
3736 struct mlx5_ifc_rmpc_bits rmp_context;
3737 };
3738
3739 struct mlx5_ifc_query_rmp_in_bits {
3740 u8 opcode[0x10];
3741 u8 reserved_at_10[0x10];
3742
3743 u8 reserved_at_20[0x10];
3744 u8 op_mod[0x10];
3745
3746 u8 reserved_at_40[0x8];
3747 u8 rmpn[0x18];
3748
3749 u8 reserved_at_60[0x20];
3750 };
3751
3752 struct mlx5_ifc_query_qp_out_bits {
3753 u8 status[0x8];
3754 u8 reserved_at_8[0x18];
3755
3756 u8 syndrome[0x20];
3757
3758 u8 reserved_at_40[0x40];
3759
3760 u8 opt_param_mask[0x20];
3761
3762 u8 reserved_at_a0[0x20];
3763
3764 struct mlx5_ifc_qpc_bits qpc;
3765
3766 u8 reserved_at_800[0x80];
3767
3768 u8 pas[0][0x40];
3769 };
3770
3771 struct mlx5_ifc_query_qp_in_bits {
3772 u8 opcode[0x10];
3773 u8 reserved_at_10[0x10];
3774
3775 u8 reserved_at_20[0x10];
3776 u8 op_mod[0x10];
3777
3778 u8 reserved_at_40[0x8];
3779 u8 qpn[0x18];
3780
3781 u8 reserved_at_60[0x20];
3782 };
3783
3784 struct mlx5_ifc_query_q_counter_out_bits {
3785 u8 status[0x8];
3786 u8 reserved_at_8[0x18];
3787
3788 u8 syndrome[0x20];
3789
3790 u8 reserved_at_40[0x40];
3791
3792 u8 rx_write_requests[0x20];
3793
3794 u8 reserved_at_a0[0x20];
3795
3796 u8 rx_read_requests[0x20];
3797
3798 u8 reserved_at_e0[0x20];
3799
3800 u8 rx_atomic_requests[0x20];
3801
3802 u8 reserved_at_120[0x20];
3803
3804 u8 rx_dct_connect[0x20];
3805
3806 u8 reserved_at_160[0x20];
3807
3808 u8 out_of_buffer[0x20];
3809
3810 u8 reserved_at_1a0[0x20];
3811
3812 u8 out_of_sequence[0x20];
3813
3814 u8 reserved_at_1e0[0x20];
3815
3816 u8 duplicate_request[0x20];
3817
3818 u8 reserved_at_220[0x20];
3819
3820 u8 rnr_nak_retry_err[0x20];
3821
3822 u8 reserved_at_260[0x20];
3823
3824 u8 packet_seq_err[0x20];
3825
3826 u8 reserved_at_2a0[0x20];
3827
3828 u8 implied_nak_seq_err[0x20];
3829
3830 u8 reserved_at_2e0[0x20];
3831
3832 u8 local_ack_timeout_err[0x20];
3833
3834 u8 reserved_at_320[0x4e0];
3835 };
3836
3837 struct mlx5_ifc_query_q_counter_in_bits {
3838 u8 opcode[0x10];
3839 u8 reserved_at_10[0x10];
3840
3841 u8 reserved_at_20[0x10];
3842 u8 op_mod[0x10];
3843
3844 u8 reserved_at_40[0x80];
3845
3846 u8 clear[0x1];
3847 u8 reserved_at_c1[0x1f];
3848
3849 u8 reserved_at_e0[0x18];
3850 u8 counter_set_id[0x8];
3851 };
3852
3853 struct mlx5_ifc_query_pages_out_bits {
3854 u8 status[0x8];
3855 u8 reserved_at_8[0x18];
3856
3857 u8 syndrome[0x20];
3858
3859 u8 reserved_at_40[0x10];
3860 u8 function_id[0x10];
3861
3862 u8 num_pages[0x20];
3863 };
3864
3865 enum {
3866 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3867 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3868 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3869 };
3870
3871 struct mlx5_ifc_query_pages_in_bits {
3872 u8 opcode[0x10];
3873 u8 reserved_at_10[0x10];
3874
3875 u8 reserved_at_20[0x10];
3876 u8 op_mod[0x10];
3877
3878 u8 reserved_at_40[0x10];
3879 u8 function_id[0x10];
3880
3881 u8 reserved_at_60[0x20];
3882 };
3883
3884 struct mlx5_ifc_query_nic_vport_context_out_bits {
3885 u8 status[0x8];
3886 u8 reserved_at_8[0x18];
3887
3888 u8 syndrome[0x20];
3889
3890 u8 reserved_at_40[0x40];
3891
3892 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3893 };
3894
3895 struct mlx5_ifc_query_nic_vport_context_in_bits {
3896 u8 opcode[0x10];
3897 u8 reserved_at_10[0x10];
3898
3899 u8 reserved_at_20[0x10];
3900 u8 op_mod[0x10];
3901
3902 u8 other_vport[0x1];
3903 u8 reserved_at_41[0xf];
3904 u8 vport_number[0x10];
3905
3906 u8 reserved_at_60[0x5];
3907 u8 allowed_list_type[0x3];
3908 u8 reserved_at_68[0x18];
3909 };
3910
3911 struct mlx5_ifc_query_mkey_out_bits {
3912 u8 status[0x8];
3913 u8 reserved_at_8[0x18];
3914
3915 u8 syndrome[0x20];
3916
3917 u8 reserved_at_40[0x40];
3918
3919 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3920
3921 u8 reserved_at_280[0x600];
3922
3923 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3924
3925 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3926 };
3927
3928 struct mlx5_ifc_query_mkey_in_bits {
3929 u8 opcode[0x10];
3930 u8 reserved_at_10[0x10];
3931
3932 u8 reserved_at_20[0x10];
3933 u8 op_mod[0x10];
3934
3935 u8 reserved_at_40[0x8];
3936 u8 mkey_index[0x18];
3937
3938 u8 pg_access[0x1];
3939 u8 reserved_at_61[0x1f];
3940 };
3941
3942 struct mlx5_ifc_query_mad_demux_out_bits {
3943 u8 status[0x8];
3944 u8 reserved_at_8[0x18];
3945
3946 u8 syndrome[0x20];
3947
3948 u8 reserved_at_40[0x40];
3949
3950 u8 mad_dumux_parameters_block[0x20];
3951 };
3952
3953 struct mlx5_ifc_query_mad_demux_in_bits {
3954 u8 opcode[0x10];
3955 u8 reserved_at_10[0x10];
3956
3957 u8 reserved_at_20[0x10];
3958 u8 op_mod[0x10];
3959
3960 u8 reserved_at_40[0x40];
3961 };
3962
3963 struct mlx5_ifc_query_l2_table_entry_out_bits {
3964 u8 status[0x8];
3965 u8 reserved_at_8[0x18];
3966
3967 u8 syndrome[0x20];
3968
3969 u8 reserved_at_40[0xa0];
3970
3971 u8 reserved_at_e0[0x13];
3972 u8 vlan_valid[0x1];
3973 u8 vlan[0xc];
3974
3975 struct mlx5_ifc_mac_address_layout_bits mac_address;
3976
3977 u8 reserved_at_140[0xc0];
3978 };
3979
3980 struct mlx5_ifc_query_l2_table_entry_in_bits {
3981 u8 opcode[0x10];
3982 u8 reserved_at_10[0x10];
3983
3984 u8 reserved_at_20[0x10];
3985 u8 op_mod[0x10];
3986
3987 u8 reserved_at_40[0x60];
3988
3989 u8 reserved_at_a0[0x8];
3990 u8 table_index[0x18];
3991
3992 u8 reserved_at_c0[0x140];
3993 };
3994
3995 struct mlx5_ifc_query_issi_out_bits {
3996 u8 status[0x8];
3997 u8 reserved_at_8[0x18];
3998
3999 u8 syndrome[0x20];
4000
4001 u8 reserved_at_40[0x10];
4002 u8 current_issi[0x10];
4003
4004 u8 reserved_at_60[0xa0];
4005
4006 u8 reserved_at_100[76][0x8];
4007 u8 supported_issi_dw0[0x20];
4008 };
4009
4010 struct mlx5_ifc_query_issi_in_bits {
4011 u8 opcode[0x10];
4012 u8 reserved_at_10[0x10];
4013
4014 u8 reserved_at_20[0x10];
4015 u8 op_mod[0x10];
4016
4017 u8 reserved_at_40[0x40];
4018 };
4019
4020 struct mlx5_ifc_set_driver_version_out_bits {
4021 u8 status[0x8];
4022 u8 reserved_0[0x18];
4023
4024 u8 syndrome[0x20];
4025 u8 reserved_1[0x40];
4026 };
4027
4028 struct mlx5_ifc_set_driver_version_in_bits {
4029 u8 opcode[0x10];
4030 u8 reserved_0[0x10];
4031
4032 u8 reserved_1[0x10];
4033 u8 op_mod[0x10];
4034
4035 u8 reserved_2[0x40];
4036 u8 driver_version[64][0x8];
4037 };
4038
4039 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4040 u8 status[0x8];
4041 u8 reserved_at_8[0x18];
4042
4043 u8 syndrome[0x20];
4044
4045 u8 reserved_at_40[0x40];
4046
4047 struct mlx5_ifc_pkey_bits pkey[0];
4048 };
4049
4050 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4051 u8 opcode[0x10];
4052 u8 reserved_at_10[0x10];
4053
4054 u8 reserved_at_20[0x10];
4055 u8 op_mod[0x10];
4056
4057 u8 other_vport[0x1];
4058 u8 reserved_at_41[0xb];
4059 u8 port_num[0x4];
4060 u8 vport_number[0x10];
4061
4062 u8 reserved_at_60[0x10];
4063 u8 pkey_index[0x10];
4064 };
4065
4066 enum {
4067 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4068 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4069 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4070 };
4071
4072 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4073 u8 status[0x8];
4074 u8 reserved_at_8[0x18];
4075
4076 u8 syndrome[0x20];
4077
4078 u8 reserved_at_40[0x20];
4079
4080 u8 gids_num[0x10];
4081 u8 reserved_at_70[0x10];
4082
4083 struct mlx5_ifc_array128_auto_bits gid[0];
4084 };
4085
4086 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4087 u8 opcode[0x10];
4088 u8 reserved_at_10[0x10];
4089
4090 u8 reserved_at_20[0x10];
4091 u8 op_mod[0x10];
4092
4093 u8 other_vport[0x1];
4094 u8 reserved_at_41[0xb];
4095 u8 port_num[0x4];
4096 u8 vport_number[0x10];
4097
4098 u8 reserved_at_60[0x10];
4099 u8 gid_index[0x10];
4100 };
4101
4102 struct mlx5_ifc_query_hca_vport_context_out_bits {
4103 u8 status[0x8];
4104 u8 reserved_at_8[0x18];
4105
4106 u8 syndrome[0x20];
4107
4108 u8 reserved_at_40[0x40];
4109
4110 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4111 };
4112
4113 struct mlx5_ifc_query_hca_vport_context_in_bits {
4114 u8 opcode[0x10];
4115 u8 reserved_at_10[0x10];
4116
4117 u8 reserved_at_20[0x10];
4118 u8 op_mod[0x10];
4119
4120 u8 other_vport[0x1];
4121 u8 reserved_at_41[0xb];
4122 u8 port_num[0x4];
4123 u8 vport_number[0x10];
4124
4125 u8 reserved_at_60[0x20];
4126 };
4127
4128 struct mlx5_ifc_query_hca_cap_out_bits {
4129 u8 status[0x8];
4130 u8 reserved_at_8[0x18];
4131
4132 u8 syndrome[0x20];
4133
4134 u8 reserved_at_40[0x40];
4135
4136 union mlx5_ifc_hca_cap_union_bits capability;
4137 };
4138
4139 struct mlx5_ifc_query_hca_cap_in_bits {
4140 u8 opcode[0x10];
4141 u8 reserved_at_10[0x10];
4142
4143 u8 reserved_at_20[0x10];
4144 u8 op_mod[0x10];
4145
4146 u8 reserved_at_40[0x40];
4147 };
4148
4149 struct mlx5_ifc_query_flow_table_out_bits {
4150 u8 status[0x8];
4151 u8 reserved_at_8[0x18];
4152
4153 u8 syndrome[0x20];
4154
4155 u8 reserved_at_40[0x80];
4156
4157 u8 reserved_at_c0[0x8];
4158 u8 level[0x8];
4159 u8 reserved_at_d0[0x8];
4160 u8 log_size[0x8];
4161
4162 u8 reserved_at_e0[0x120];
4163 };
4164
4165 struct mlx5_ifc_query_flow_table_in_bits {
4166 u8 opcode[0x10];
4167 u8 reserved_at_10[0x10];
4168
4169 u8 reserved_at_20[0x10];
4170 u8 op_mod[0x10];
4171
4172 u8 reserved_at_40[0x40];
4173
4174 u8 table_type[0x8];
4175 u8 reserved_at_88[0x18];
4176
4177 u8 reserved_at_a0[0x8];
4178 u8 table_id[0x18];
4179
4180 u8 reserved_at_c0[0x140];
4181 };
4182
4183 struct mlx5_ifc_query_fte_out_bits {
4184 u8 status[0x8];
4185 u8 reserved_at_8[0x18];
4186
4187 u8 syndrome[0x20];
4188
4189 u8 reserved_at_40[0x1c0];
4190
4191 struct mlx5_ifc_flow_context_bits flow_context;
4192 };
4193
4194 struct mlx5_ifc_query_fte_in_bits {
4195 u8 opcode[0x10];
4196 u8 reserved_at_10[0x10];
4197
4198 u8 reserved_at_20[0x10];
4199 u8 op_mod[0x10];
4200
4201 u8 reserved_at_40[0x40];
4202
4203 u8 table_type[0x8];
4204 u8 reserved_at_88[0x18];
4205
4206 u8 reserved_at_a0[0x8];
4207 u8 table_id[0x18];
4208
4209 u8 reserved_at_c0[0x40];
4210
4211 u8 flow_index[0x20];
4212
4213 u8 reserved_at_120[0xe0];
4214 };
4215
4216 enum {
4217 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4218 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4219 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4220 };
4221
4222 struct mlx5_ifc_query_flow_group_out_bits {
4223 u8 status[0x8];
4224 u8 reserved_at_8[0x18];
4225
4226 u8 syndrome[0x20];
4227
4228 u8 reserved_at_40[0xa0];
4229
4230 u8 start_flow_index[0x20];
4231
4232 u8 reserved_at_100[0x20];
4233
4234 u8 end_flow_index[0x20];
4235
4236 u8 reserved_at_140[0xa0];
4237
4238 u8 reserved_at_1e0[0x18];
4239 u8 match_criteria_enable[0x8];
4240
4241 struct mlx5_ifc_fte_match_param_bits match_criteria;
4242
4243 u8 reserved_at_1200[0xe00];
4244 };
4245
4246 struct mlx5_ifc_query_flow_group_in_bits {
4247 u8 opcode[0x10];
4248 u8 reserved_at_10[0x10];
4249
4250 u8 reserved_at_20[0x10];
4251 u8 op_mod[0x10];
4252
4253 u8 reserved_at_40[0x40];
4254
4255 u8 table_type[0x8];
4256 u8 reserved_at_88[0x18];
4257
4258 u8 reserved_at_a0[0x8];
4259 u8 table_id[0x18];
4260
4261 u8 group_id[0x20];
4262
4263 u8 reserved_at_e0[0x120];
4264 };
4265
4266 struct mlx5_ifc_query_flow_counter_out_bits {
4267 u8 status[0x8];
4268 u8 reserved_at_8[0x18];
4269
4270 u8 syndrome[0x20];
4271
4272 u8 reserved_at_40[0x40];
4273
4274 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4275 };
4276
4277 struct mlx5_ifc_query_flow_counter_in_bits {
4278 u8 opcode[0x10];
4279 u8 reserved_at_10[0x10];
4280
4281 u8 reserved_at_20[0x10];
4282 u8 op_mod[0x10];
4283
4284 u8 reserved_at_40[0x80];
4285
4286 u8 clear[0x1];
4287 u8 reserved_at_c1[0xf];
4288 u8 num_of_counters[0x10];
4289
4290 u8 reserved_at_e0[0x10];
4291 u8 flow_counter_id[0x10];
4292 };
4293
4294 struct mlx5_ifc_query_esw_vport_context_out_bits {
4295 u8 status[0x8];
4296 u8 reserved_at_8[0x18];
4297
4298 u8 syndrome[0x20];
4299
4300 u8 reserved_at_40[0x40];
4301
4302 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4303 };
4304
4305 struct mlx5_ifc_query_esw_vport_context_in_bits {
4306 u8 opcode[0x10];
4307 u8 reserved_at_10[0x10];
4308
4309 u8 reserved_at_20[0x10];
4310 u8 op_mod[0x10];
4311
4312 u8 other_vport[0x1];
4313 u8 reserved_at_41[0xf];
4314 u8 vport_number[0x10];
4315
4316 u8 reserved_at_60[0x20];
4317 };
4318
4319 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4320 u8 status[0x8];
4321 u8 reserved_at_8[0x18];
4322
4323 u8 syndrome[0x20];
4324
4325 u8 reserved_at_40[0x40];
4326 };
4327
4328 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4329 u8 reserved_at_0[0x1c];
4330 u8 vport_cvlan_insert[0x1];
4331 u8 vport_svlan_insert[0x1];
4332 u8 vport_cvlan_strip[0x1];
4333 u8 vport_svlan_strip[0x1];
4334 };
4335
4336 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4337 u8 opcode[0x10];
4338 u8 reserved_at_10[0x10];
4339
4340 u8 reserved_at_20[0x10];
4341 u8 op_mod[0x10];
4342
4343 u8 other_vport[0x1];
4344 u8 reserved_at_41[0xf];
4345 u8 vport_number[0x10];
4346
4347 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4348
4349 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4350 };
4351
4352 struct mlx5_ifc_query_eq_out_bits {
4353 u8 status[0x8];
4354 u8 reserved_at_8[0x18];
4355
4356 u8 syndrome[0x20];
4357
4358 u8 reserved_at_40[0x40];
4359
4360 struct mlx5_ifc_eqc_bits eq_context_entry;
4361
4362 u8 reserved_at_280[0x40];
4363
4364 u8 event_bitmask[0x40];
4365
4366 u8 reserved_at_300[0x580];
4367
4368 u8 pas[0][0x40];
4369 };
4370
4371 struct mlx5_ifc_query_eq_in_bits {
4372 u8 opcode[0x10];
4373 u8 reserved_at_10[0x10];
4374
4375 u8 reserved_at_20[0x10];
4376 u8 op_mod[0x10];
4377
4378 u8 reserved_at_40[0x18];
4379 u8 eq_number[0x8];
4380
4381 u8 reserved_at_60[0x20];
4382 };
4383
4384 struct mlx5_ifc_encap_header_in_bits {
4385 u8 reserved_at_0[0x5];
4386 u8 header_type[0x3];
4387 u8 reserved_at_8[0xe];
4388 u8 encap_header_size[0xa];
4389
4390 u8 reserved_at_20[0x10];
4391 u8 encap_header[2][0x8];
4392
4393 u8 more_encap_header[0][0x8];
4394 };
4395
4396 struct mlx5_ifc_query_encap_header_out_bits {
4397 u8 status[0x8];
4398 u8 reserved_at_8[0x18];
4399
4400 u8 syndrome[0x20];
4401
4402 u8 reserved_at_40[0xa0];
4403
4404 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4405 };
4406
4407 struct mlx5_ifc_query_encap_header_in_bits {
4408 u8 opcode[0x10];
4409 u8 reserved_at_10[0x10];
4410
4411 u8 reserved_at_20[0x10];
4412 u8 op_mod[0x10];
4413
4414 u8 encap_id[0x20];
4415
4416 u8 reserved_at_60[0xa0];
4417 };
4418
4419 struct mlx5_ifc_alloc_encap_header_out_bits {
4420 u8 status[0x8];
4421 u8 reserved_at_8[0x18];
4422
4423 u8 syndrome[0x20];
4424
4425 u8 encap_id[0x20];
4426
4427 u8 reserved_at_60[0x20];
4428 };
4429
4430 struct mlx5_ifc_alloc_encap_header_in_bits {
4431 u8 opcode[0x10];
4432 u8 reserved_at_10[0x10];
4433
4434 u8 reserved_at_20[0x10];
4435 u8 op_mod[0x10];
4436
4437 u8 reserved_at_40[0xa0];
4438
4439 struct mlx5_ifc_encap_header_in_bits encap_header;
4440 };
4441
4442 struct mlx5_ifc_dealloc_encap_header_out_bits {
4443 u8 status[0x8];
4444 u8 reserved_at_8[0x18];
4445
4446 u8 syndrome[0x20];
4447
4448 u8 reserved_at_40[0x40];
4449 };
4450
4451 struct mlx5_ifc_dealloc_encap_header_in_bits {
4452 u8 opcode[0x10];
4453 u8 reserved_at_10[0x10];
4454
4455 u8 reserved_20[0x10];
4456 u8 op_mod[0x10];
4457
4458 u8 encap_id[0x20];
4459
4460 u8 reserved_60[0x20];
4461 };
4462
4463 struct mlx5_ifc_query_dct_out_bits {
4464 u8 status[0x8];
4465 u8 reserved_at_8[0x18];
4466
4467 u8 syndrome[0x20];
4468
4469 u8 reserved_at_40[0x40];
4470
4471 struct mlx5_ifc_dctc_bits dct_context_entry;
4472
4473 u8 reserved_at_280[0x180];
4474 };
4475
4476 struct mlx5_ifc_query_dct_in_bits {
4477 u8 opcode[0x10];
4478 u8 reserved_at_10[0x10];
4479
4480 u8 reserved_at_20[0x10];
4481 u8 op_mod[0x10];
4482
4483 u8 reserved_at_40[0x8];
4484 u8 dctn[0x18];
4485
4486 u8 reserved_at_60[0x20];
4487 };
4488
4489 struct mlx5_ifc_query_cq_out_bits {
4490 u8 status[0x8];
4491 u8 reserved_at_8[0x18];
4492
4493 u8 syndrome[0x20];
4494
4495 u8 reserved_at_40[0x40];
4496
4497 struct mlx5_ifc_cqc_bits cq_context;
4498
4499 u8 reserved_at_280[0x600];
4500
4501 u8 pas[0][0x40];
4502 };
4503
4504 struct mlx5_ifc_query_cq_in_bits {
4505 u8 opcode[0x10];
4506 u8 reserved_at_10[0x10];
4507
4508 u8 reserved_at_20[0x10];
4509 u8 op_mod[0x10];
4510
4511 u8 reserved_at_40[0x8];
4512 u8 cqn[0x18];
4513
4514 u8 reserved_at_60[0x20];
4515 };
4516
4517 struct mlx5_ifc_query_cong_status_out_bits {
4518 u8 status[0x8];
4519 u8 reserved_at_8[0x18];
4520
4521 u8 syndrome[0x20];
4522
4523 u8 reserved_at_40[0x20];
4524
4525 u8 enable[0x1];
4526 u8 tag_enable[0x1];
4527 u8 reserved_at_62[0x1e];
4528 };
4529
4530 struct mlx5_ifc_query_cong_status_in_bits {
4531 u8 opcode[0x10];
4532 u8 reserved_at_10[0x10];
4533
4534 u8 reserved_at_20[0x10];
4535 u8 op_mod[0x10];
4536
4537 u8 reserved_at_40[0x18];
4538 u8 priority[0x4];
4539 u8 cong_protocol[0x4];
4540
4541 u8 reserved_at_60[0x20];
4542 };
4543
4544 struct mlx5_ifc_query_cong_statistics_out_bits {
4545 u8 status[0x8];
4546 u8 reserved_at_8[0x18];
4547
4548 u8 syndrome[0x20];
4549
4550 u8 reserved_at_40[0x40];
4551
4552 u8 cur_flows[0x20];
4553
4554 u8 sum_flows[0x20];
4555
4556 u8 cnp_ignored_high[0x20];
4557
4558 u8 cnp_ignored_low[0x20];
4559
4560 u8 cnp_handled_high[0x20];
4561
4562 u8 cnp_handled_low[0x20];
4563
4564 u8 reserved_at_140[0x100];
4565
4566 u8 time_stamp_high[0x20];
4567
4568 u8 time_stamp_low[0x20];
4569
4570 u8 accumulators_period[0x20];
4571
4572 u8 ecn_marked_roce_packets_high[0x20];
4573
4574 u8 ecn_marked_roce_packets_low[0x20];
4575
4576 u8 cnps_sent_high[0x20];
4577
4578 u8 cnps_sent_low[0x20];
4579
4580 u8 reserved_at_320[0x560];
4581 };
4582
4583 struct mlx5_ifc_query_cong_statistics_in_bits {
4584 u8 opcode[0x10];
4585 u8 reserved_at_10[0x10];
4586
4587 u8 reserved_at_20[0x10];
4588 u8 op_mod[0x10];
4589
4590 u8 clear[0x1];
4591 u8 reserved_at_41[0x1f];
4592
4593 u8 reserved_at_60[0x20];
4594 };
4595
4596 struct mlx5_ifc_query_cong_params_out_bits {
4597 u8 status[0x8];
4598 u8 reserved_at_8[0x18];
4599
4600 u8 syndrome[0x20];
4601
4602 u8 reserved_at_40[0x40];
4603
4604 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4605 };
4606
4607 struct mlx5_ifc_query_cong_params_in_bits {
4608 u8 opcode[0x10];
4609 u8 reserved_at_10[0x10];
4610
4611 u8 reserved_at_20[0x10];
4612 u8 op_mod[0x10];
4613
4614 u8 reserved_at_40[0x1c];
4615 u8 cong_protocol[0x4];
4616
4617 u8 reserved_at_60[0x20];
4618 };
4619
4620 struct mlx5_ifc_query_adapter_out_bits {
4621 u8 status[0x8];
4622 u8 reserved_at_8[0x18];
4623
4624 u8 syndrome[0x20];
4625
4626 u8 reserved_at_40[0x40];
4627
4628 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4629 };
4630
4631 struct mlx5_ifc_query_adapter_in_bits {
4632 u8 opcode[0x10];
4633 u8 reserved_at_10[0x10];
4634
4635 u8 reserved_at_20[0x10];
4636 u8 op_mod[0x10];
4637
4638 u8 reserved_at_40[0x40];
4639 };
4640
4641 struct mlx5_ifc_qp_2rst_out_bits {
4642 u8 status[0x8];
4643 u8 reserved_at_8[0x18];
4644
4645 u8 syndrome[0x20];
4646
4647 u8 reserved_at_40[0x40];
4648 };
4649
4650 struct mlx5_ifc_qp_2rst_in_bits {
4651 u8 opcode[0x10];
4652 u8 reserved_at_10[0x10];
4653
4654 u8 reserved_at_20[0x10];
4655 u8 op_mod[0x10];
4656
4657 u8 reserved_at_40[0x8];
4658 u8 qpn[0x18];
4659
4660 u8 reserved_at_60[0x20];
4661 };
4662
4663 struct mlx5_ifc_qp_2err_out_bits {
4664 u8 status[0x8];
4665 u8 reserved_at_8[0x18];
4666
4667 u8 syndrome[0x20];
4668
4669 u8 reserved_at_40[0x40];
4670 };
4671
4672 struct mlx5_ifc_qp_2err_in_bits {
4673 u8 opcode[0x10];
4674 u8 reserved_at_10[0x10];
4675
4676 u8 reserved_at_20[0x10];
4677 u8 op_mod[0x10];
4678
4679 u8 reserved_at_40[0x8];
4680 u8 qpn[0x18];
4681
4682 u8 reserved_at_60[0x20];
4683 };
4684
4685 struct mlx5_ifc_page_fault_resume_out_bits {
4686 u8 status[0x8];
4687 u8 reserved_at_8[0x18];
4688
4689 u8 syndrome[0x20];
4690
4691 u8 reserved_at_40[0x40];
4692 };
4693
4694 struct mlx5_ifc_page_fault_resume_in_bits {
4695 u8 opcode[0x10];
4696 u8 reserved_at_10[0x10];
4697
4698 u8 reserved_at_20[0x10];
4699 u8 op_mod[0x10];
4700
4701 u8 error[0x1];
4702 u8 reserved_at_41[0x4];
4703 u8 page_fault_type[0x3];
4704 u8 wq_number[0x18];
4705
4706 u8 reserved_at_60[0x8];
4707 u8 token[0x18];
4708 };
4709
4710 struct mlx5_ifc_nop_out_bits {
4711 u8 status[0x8];
4712 u8 reserved_at_8[0x18];
4713
4714 u8 syndrome[0x20];
4715
4716 u8 reserved_at_40[0x40];
4717 };
4718
4719 struct mlx5_ifc_nop_in_bits {
4720 u8 opcode[0x10];
4721 u8 reserved_at_10[0x10];
4722
4723 u8 reserved_at_20[0x10];
4724 u8 op_mod[0x10];
4725
4726 u8 reserved_at_40[0x40];
4727 };
4728
4729 struct mlx5_ifc_modify_vport_state_out_bits {
4730 u8 status[0x8];
4731 u8 reserved_at_8[0x18];
4732
4733 u8 syndrome[0x20];
4734
4735 u8 reserved_at_40[0x40];
4736 };
4737
4738 struct mlx5_ifc_modify_vport_state_in_bits {
4739 u8 opcode[0x10];
4740 u8 reserved_at_10[0x10];
4741
4742 u8 reserved_at_20[0x10];
4743 u8 op_mod[0x10];
4744
4745 u8 other_vport[0x1];
4746 u8 reserved_at_41[0xf];
4747 u8 vport_number[0x10];
4748
4749 u8 reserved_at_60[0x18];
4750 u8 admin_state[0x4];
4751 u8 reserved_at_7c[0x4];
4752 };
4753
4754 struct mlx5_ifc_modify_tis_out_bits {
4755 u8 status[0x8];
4756 u8 reserved_at_8[0x18];
4757
4758 u8 syndrome[0x20];
4759
4760 u8 reserved_at_40[0x40];
4761 };
4762
4763 struct mlx5_ifc_modify_tis_bitmask_bits {
4764 u8 reserved_at_0[0x20];
4765
4766 u8 reserved_at_20[0x1d];
4767 u8 lag_tx_port_affinity[0x1];
4768 u8 strict_lag_tx_port_affinity[0x1];
4769 u8 prio[0x1];
4770 };
4771
4772 struct mlx5_ifc_modify_tis_in_bits {
4773 u8 opcode[0x10];
4774 u8 reserved_at_10[0x10];
4775
4776 u8 reserved_at_20[0x10];
4777 u8 op_mod[0x10];
4778
4779 u8 reserved_at_40[0x8];
4780 u8 tisn[0x18];
4781
4782 u8 reserved_at_60[0x20];
4783
4784 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4785
4786 u8 reserved_at_c0[0x40];
4787
4788 struct mlx5_ifc_tisc_bits ctx;
4789 };
4790
4791 struct mlx5_ifc_modify_tir_bitmask_bits {
4792 u8 reserved_at_0[0x20];
4793
4794 u8 reserved_at_20[0x1b];
4795 u8 self_lb_en[0x1];
4796 u8 reserved_at_3c[0x1];
4797 u8 hash[0x1];
4798 u8 reserved_at_3e[0x1];
4799 u8 lro[0x1];
4800 };
4801
4802 struct mlx5_ifc_modify_tir_out_bits {
4803 u8 status[0x8];
4804 u8 reserved_at_8[0x18];
4805
4806 u8 syndrome[0x20];
4807
4808 u8 reserved_at_40[0x40];
4809 };
4810
4811 struct mlx5_ifc_modify_tir_in_bits {
4812 u8 opcode[0x10];
4813 u8 reserved_at_10[0x10];
4814
4815 u8 reserved_at_20[0x10];
4816 u8 op_mod[0x10];
4817
4818 u8 reserved_at_40[0x8];
4819 u8 tirn[0x18];
4820
4821 u8 reserved_at_60[0x20];
4822
4823 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4824
4825 u8 reserved_at_c0[0x40];
4826
4827 struct mlx5_ifc_tirc_bits ctx;
4828 };
4829
4830 struct mlx5_ifc_modify_sq_out_bits {
4831 u8 status[0x8];
4832 u8 reserved_at_8[0x18];
4833
4834 u8 syndrome[0x20];
4835
4836 u8 reserved_at_40[0x40];
4837 };
4838
4839 struct mlx5_ifc_modify_sq_in_bits {
4840 u8 opcode[0x10];
4841 u8 reserved_at_10[0x10];
4842
4843 u8 reserved_at_20[0x10];
4844 u8 op_mod[0x10];
4845
4846 u8 sq_state[0x4];
4847 u8 reserved_at_44[0x4];
4848 u8 sqn[0x18];
4849
4850 u8 reserved_at_60[0x20];
4851
4852 u8 modify_bitmask[0x40];
4853
4854 u8 reserved_at_c0[0x40];
4855
4856 struct mlx5_ifc_sqc_bits ctx;
4857 };
4858
4859 struct mlx5_ifc_modify_scheduling_element_out_bits {
4860 u8 status[0x8];
4861 u8 reserved_at_8[0x18];
4862
4863 u8 syndrome[0x20];
4864
4865 u8 reserved_at_40[0x1c0];
4866 };
4867
4868 enum {
4869 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4870 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4871 };
4872
4873 struct mlx5_ifc_modify_scheduling_element_in_bits {
4874 u8 opcode[0x10];
4875 u8 reserved_at_10[0x10];
4876
4877 u8 reserved_at_20[0x10];
4878 u8 op_mod[0x10];
4879
4880 u8 scheduling_hierarchy[0x8];
4881 u8 reserved_at_48[0x18];
4882
4883 u8 scheduling_element_id[0x20];
4884
4885 u8 reserved_at_80[0x20];
4886
4887 u8 modify_bitmask[0x20];
4888
4889 u8 reserved_at_c0[0x40];
4890
4891 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4892
4893 u8 reserved_at_300[0x100];
4894 };
4895
4896 struct mlx5_ifc_modify_rqt_out_bits {
4897 u8 status[0x8];
4898 u8 reserved_at_8[0x18];
4899
4900 u8 syndrome[0x20];
4901
4902 u8 reserved_at_40[0x40];
4903 };
4904
4905 struct mlx5_ifc_rqt_bitmask_bits {
4906 u8 reserved_at_0[0x20];
4907
4908 u8 reserved_at_20[0x1f];
4909 u8 rqn_list[0x1];
4910 };
4911
4912 struct mlx5_ifc_modify_rqt_in_bits {
4913 u8 opcode[0x10];
4914 u8 reserved_at_10[0x10];
4915
4916 u8 reserved_at_20[0x10];
4917 u8 op_mod[0x10];
4918
4919 u8 reserved_at_40[0x8];
4920 u8 rqtn[0x18];
4921
4922 u8 reserved_at_60[0x20];
4923
4924 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4925
4926 u8 reserved_at_c0[0x40];
4927
4928 struct mlx5_ifc_rqtc_bits ctx;
4929 };
4930
4931 struct mlx5_ifc_modify_rq_out_bits {
4932 u8 status[0x8];
4933 u8 reserved_at_8[0x18];
4934
4935 u8 syndrome[0x20];
4936
4937 u8 reserved_at_40[0x40];
4938 };
4939
4940 enum {
4941 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4942 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4943 };
4944
4945 struct mlx5_ifc_modify_rq_in_bits {
4946 u8 opcode[0x10];
4947 u8 reserved_at_10[0x10];
4948
4949 u8 reserved_at_20[0x10];
4950 u8 op_mod[0x10];
4951
4952 u8 rq_state[0x4];
4953 u8 reserved_at_44[0x4];
4954 u8 rqn[0x18];
4955
4956 u8 reserved_at_60[0x20];
4957
4958 u8 modify_bitmask[0x40];
4959
4960 u8 reserved_at_c0[0x40];
4961
4962 struct mlx5_ifc_rqc_bits ctx;
4963 };
4964
4965 struct mlx5_ifc_modify_rmp_out_bits {
4966 u8 status[0x8];
4967 u8 reserved_at_8[0x18];
4968
4969 u8 syndrome[0x20];
4970
4971 u8 reserved_at_40[0x40];
4972 };
4973
4974 struct mlx5_ifc_rmp_bitmask_bits {
4975 u8 reserved_at_0[0x20];
4976
4977 u8 reserved_at_20[0x1f];
4978 u8 lwm[0x1];
4979 };
4980
4981 struct mlx5_ifc_modify_rmp_in_bits {
4982 u8 opcode[0x10];
4983 u8 reserved_at_10[0x10];
4984
4985 u8 reserved_at_20[0x10];
4986 u8 op_mod[0x10];
4987
4988 u8 rmp_state[0x4];
4989 u8 reserved_at_44[0x4];
4990 u8 rmpn[0x18];
4991
4992 u8 reserved_at_60[0x20];
4993
4994 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4995
4996 u8 reserved_at_c0[0x40];
4997
4998 struct mlx5_ifc_rmpc_bits ctx;
4999 };
5000
5001 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5002 u8 status[0x8];
5003 u8 reserved_at_8[0x18];
5004
5005 u8 syndrome[0x20];
5006
5007 u8 reserved_at_40[0x40];
5008 };
5009
5010 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5011 u8 reserved_at_0[0x16];
5012 u8 node_guid[0x1];
5013 u8 port_guid[0x1];
5014 u8 min_inline[0x1];
5015 u8 mtu[0x1];
5016 u8 change_event[0x1];
5017 u8 promisc[0x1];
5018 u8 permanent_address[0x1];
5019 u8 addresses_list[0x1];
5020 u8 roce_en[0x1];
5021 u8 reserved_at_1f[0x1];
5022 };
5023
5024 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5025 u8 opcode[0x10];
5026 u8 reserved_at_10[0x10];
5027
5028 u8 reserved_at_20[0x10];
5029 u8 op_mod[0x10];
5030
5031 u8 other_vport[0x1];
5032 u8 reserved_at_41[0xf];
5033 u8 vport_number[0x10];
5034
5035 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5036
5037 u8 reserved_at_80[0x780];
5038
5039 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5040 };
5041
5042 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5043 u8 status[0x8];
5044 u8 reserved_at_8[0x18];
5045
5046 u8 syndrome[0x20];
5047
5048 u8 reserved_at_40[0x40];
5049 };
5050
5051 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5052 u8 opcode[0x10];
5053 u8 reserved_at_10[0x10];
5054
5055 u8 reserved_at_20[0x10];
5056 u8 op_mod[0x10];
5057
5058 u8 other_vport[0x1];
5059 u8 reserved_at_41[0xb];
5060 u8 port_num[0x4];
5061 u8 vport_number[0x10];
5062
5063 u8 reserved_at_60[0x20];
5064
5065 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5066 };
5067
5068 struct mlx5_ifc_modify_cq_out_bits {
5069 u8 status[0x8];
5070 u8 reserved_at_8[0x18];
5071
5072 u8 syndrome[0x20];
5073
5074 u8 reserved_at_40[0x40];
5075 };
5076
5077 enum {
5078 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5079 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5080 };
5081
5082 struct mlx5_ifc_modify_cq_in_bits {
5083 u8 opcode[0x10];
5084 u8 reserved_at_10[0x10];
5085
5086 u8 reserved_at_20[0x10];
5087 u8 op_mod[0x10];
5088
5089 u8 reserved_at_40[0x8];
5090 u8 cqn[0x18];
5091
5092 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5093
5094 struct mlx5_ifc_cqc_bits cq_context;
5095
5096 u8 reserved_at_280[0x600];
5097
5098 u8 pas[0][0x40];
5099 };
5100
5101 struct mlx5_ifc_modify_cong_status_out_bits {
5102 u8 status[0x8];
5103 u8 reserved_at_8[0x18];
5104
5105 u8 syndrome[0x20];
5106
5107 u8 reserved_at_40[0x40];
5108 };
5109
5110 struct mlx5_ifc_modify_cong_status_in_bits {
5111 u8 opcode[0x10];
5112 u8 reserved_at_10[0x10];
5113
5114 u8 reserved_at_20[0x10];
5115 u8 op_mod[0x10];
5116
5117 u8 reserved_at_40[0x18];
5118 u8 priority[0x4];
5119 u8 cong_protocol[0x4];
5120
5121 u8 enable[0x1];
5122 u8 tag_enable[0x1];
5123 u8 reserved_at_62[0x1e];
5124 };
5125
5126 struct mlx5_ifc_modify_cong_params_out_bits {
5127 u8 status[0x8];
5128 u8 reserved_at_8[0x18];
5129
5130 u8 syndrome[0x20];
5131
5132 u8 reserved_at_40[0x40];
5133 };
5134
5135 struct mlx5_ifc_modify_cong_params_in_bits {
5136 u8 opcode[0x10];
5137 u8 reserved_at_10[0x10];
5138
5139 u8 reserved_at_20[0x10];
5140 u8 op_mod[0x10];
5141
5142 u8 reserved_at_40[0x1c];
5143 u8 cong_protocol[0x4];
5144
5145 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5146
5147 u8 reserved_at_80[0x80];
5148
5149 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5150 };
5151
5152 struct mlx5_ifc_manage_pages_out_bits {
5153 u8 status[0x8];
5154 u8 reserved_at_8[0x18];
5155
5156 u8 syndrome[0x20];
5157
5158 u8 output_num_entries[0x20];
5159
5160 u8 reserved_at_60[0x20];
5161
5162 u8 pas[0][0x40];
5163 };
5164
5165 enum {
5166 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5167 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5168 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5169 };
5170
5171 struct mlx5_ifc_manage_pages_in_bits {
5172 u8 opcode[0x10];
5173 u8 reserved_at_10[0x10];
5174
5175 u8 reserved_at_20[0x10];
5176 u8 op_mod[0x10];
5177
5178 u8 reserved_at_40[0x10];
5179 u8 function_id[0x10];
5180
5181 u8 input_num_entries[0x20];
5182
5183 u8 pas[0][0x40];
5184 };
5185
5186 struct mlx5_ifc_mad_ifc_out_bits {
5187 u8 status[0x8];
5188 u8 reserved_at_8[0x18];
5189
5190 u8 syndrome[0x20];
5191
5192 u8 reserved_at_40[0x40];
5193
5194 u8 response_mad_packet[256][0x8];
5195 };
5196
5197 struct mlx5_ifc_mad_ifc_in_bits {
5198 u8 opcode[0x10];
5199 u8 reserved_at_10[0x10];
5200
5201 u8 reserved_at_20[0x10];
5202 u8 op_mod[0x10];
5203
5204 u8 remote_lid[0x10];
5205 u8 reserved_at_50[0x8];
5206 u8 port[0x8];
5207
5208 u8 reserved_at_60[0x20];
5209
5210 u8 mad[256][0x8];
5211 };
5212
5213 struct mlx5_ifc_init_hca_out_bits {
5214 u8 status[0x8];
5215 u8 reserved_at_8[0x18];
5216
5217 u8 syndrome[0x20];
5218
5219 u8 reserved_at_40[0x40];
5220 };
5221
5222 struct mlx5_ifc_init_hca_in_bits {
5223 u8 opcode[0x10];
5224 u8 reserved_at_10[0x10];
5225
5226 u8 reserved_at_20[0x10];
5227 u8 op_mod[0x10];
5228
5229 u8 reserved_at_40[0x40];
5230 };
5231
5232 struct mlx5_ifc_init2rtr_qp_out_bits {
5233 u8 status[0x8];
5234 u8 reserved_at_8[0x18];
5235
5236 u8 syndrome[0x20];
5237
5238 u8 reserved_at_40[0x40];
5239 };
5240
5241 struct mlx5_ifc_init2rtr_qp_in_bits {
5242 u8 opcode[0x10];
5243 u8 reserved_at_10[0x10];
5244
5245 u8 reserved_at_20[0x10];
5246 u8 op_mod[0x10];
5247
5248 u8 reserved_at_40[0x8];
5249 u8 qpn[0x18];
5250
5251 u8 reserved_at_60[0x20];
5252
5253 u8 opt_param_mask[0x20];
5254
5255 u8 reserved_at_a0[0x20];
5256
5257 struct mlx5_ifc_qpc_bits qpc;
5258
5259 u8 reserved_at_800[0x80];
5260 };
5261
5262 struct mlx5_ifc_init2init_qp_out_bits {
5263 u8 status[0x8];
5264 u8 reserved_at_8[0x18];
5265
5266 u8 syndrome[0x20];
5267
5268 u8 reserved_at_40[0x40];
5269 };
5270
5271 struct mlx5_ifc_init2init_qp_in_bits {
5272 u8 opcode[0x10];
5273 u8 reserved_at_10[0x10];
5274
5275 u8 reserved_at_20[0x10];
5276 u8 op_mod[0x10];
5277
5278 u8 reserved_at_40[0x8];
5279 u8 qpn[0x18];
5280
5281 u8 reserved_at_60[0x20];
5282
5283 u8 opt_param_mask[0x20];
5284
5285 u8 reserved_at_a0[0x20];
5286
5287 struct mlx5_ifc_qpc_bits qpc;
5288
5289 u8 reserved_at_800[0x80];
5290 };
5291
5292 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5293 u8 status[0x8];
5294 u8 reserved_at_8[0x18];
5295
5296 u8 syndrome[0x20];
5297
5298 u8 reserved_at_40[0x40];
5299
5300 u8 packet_headers_log[128][0x8];
5301
5302 u8 packet_syndrome[64][0x8];
5303 };
5304
5305 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5306 u8 opcode[0x10];
5307 u8 reserved_at_10[0x10];
5308
5309 u8 reserved_at_20[0x10];
5310 u8 op_mod[0x10];
5311
5312 u8 reserved_at_40[0x40];
5313 };
5314
5315 struct mlx5_ifc_gen_eqe_in_bits {
5316 u8 opcode[0x10];
5317 u8 reserved_at_10[0x10];
5318
5319 u8 reserved_at_20[0x10];
5320 u8 op_mod[0x10];
5321
5322 u8 reserved_at_40[0x18];
5323 u8 eq_number[0x8];
5324
5325 u8 reserved_at_60[0x20];
5326
5327 u8 eqe[64][0x8];
5328 };
5329
5330 struct mlx5_ifc_gen_eq_out_bits {
5331 u8 status[0x8];
5332 u8 reserved_at_8[0x18];
5333
5334 u8 syndrome[0x20];
5335
5336 u8 reserved_at_40[0x40];
5337 };
5338
5339 struct mlx5_ifc_enable_hca_out_bits {
5340 u8 status[0x8];
5341 u8 reserved_at_8[0x18];
5342
5343 u8 syndrome[0x20];
5344
5345 u8 reserved_at_40[0x20];
5346 };
5347
5348 struct mlx5_ifc_enable_hca_in_bits {
5349 u8 opcode[0x10];
5350 u8 reserved_at_10[0x10];
5351
5352 u8 reserved_at_20[0x10];
5353 u8 op_mod[0x10];
5354
5355 u8 reserved_at_40[0x10];
5356 u8 function_id[0x10];
5357
5358 u8 reserved_at_60[0x20];
5359 };
5360
5361 struct mlx5_ifc_drain_dct_out_bits {
5362 u8 status[0x8];
5363 u8 reserved_at_8[0x18];
5364
5365 u8 syndrome[0x20];
5366
5367 u8 reserved_at_40[0x40];
5368 };
5369
5370 struct mlx5_ifc_drain_dct_in_bits {
5371 u8 opcode[0x10];
5372 u8 reserved_at_10[0x10];
5373
5374 u8 reserved_at_20[0x10];
5375 u8 op_mod[0x10];
5376
5377 u8 reserved_at_40[0x8];
5378 u8 dctn[0x18];
5379
5380 u8 reserved_at_60[0x20];
5381 };
5382
5383 struct mlx5_ifc_disable_hca_out_bits {
5384 u8 status[0x8];
5385 u8 reserved_at_8[0x18];
5386
5387 u8 syndrome[0x20];
5388
5389 u8 reserved_at_40[0x20];
5390 };
5391
5392 struct mlx5_ifc_disable_hca_in_bits {
5393 u8 opcode[0x10];
5394 u8 reserved_at_10[0x10];
5395
5396 u8 reserved_at_20[0x10];
5397 u8 op_mod[0x10];
5398
5399 u8 reserved_at_40[0x10];
5400 u8 function_id[0x10];
5401
5402 u8 reserved_at_60[0x20];
5403 };
5404
5405 struct mlx5_ifc_detach_from_mcg_out_bits {
5406 u8 status[0x8];
5407 u8 reserved_at_8[0x18];
5408
5409 u8 syndrome[0x20];
5410
5411 u8 reserved_at_40[0x40];
5412 };
5413
5414 struct mlx5_ifc_detach_from_mcg_in_bits {
5415 u8 opcode[0x10];
5416 u8 reserved_at_10[0x10];
5417
5418 u8 reserved_at_20[0x10];
5419 u8 op_mod[0x10];
5420
5421 u8 reserved_at_40[0x8];
5422 u8 qpn[0x18];
5423
5424 u8 reserved_at_60[0x20];
5425
5426 u8 multicast_gid[16][0x8];
5427 };
5428
5429 struct mlx5_ifc_destroy_xrq_out_bits {
5430 u8 status[0x8];
5431 u8 reserved_at_8[0x18];
5432
5433 u8 syndrome[0x20];
5434
5435 u8 reserved_at_40[0x40];
5436 };
5437
5438 struct mlx5_ifc_destroy_xrq_in_bits {
5439 u8 opcode[0x10];
5440 u8 reserved_at_10[0x10];
5441
5442 u8 reserved_at_20[0x10];
5443 u8 op_mod[0x10];
5444
5445 u8 reserved_at_40[0x8];
5446 u8 xrqn[0x18];
5447
5448 u8 reserved_at_60[0x20];
5449 };
5450
5451 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5452 u8 status[0x8];
5453 u8 reserved_at_8[0x18];
5454
5455 u8 syndrome[0x20];
5456
5457 u8 reserved_at_40[0x40];
5458 };
5459
5460 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5461 u8 opcode[0x10];
5462 u8 reserved_at_10[0x10];
5463
5464 u8 reserved_at_20[0x10];
5465 u8 op_mod[0x10];
5466
5467 u8 reserved_at_40[0x8];
5468 u8 xrc_srqn[0x18];
5469
5470 u8 reserved_at_60[0x20];
5471 };
5472
5473 struct mlx5_ifc_destroy_tis_out_bits {
5474 u8 status[0x8];
5475 u8 reserved_at_8[0x18];
5476
5477 u8 syndrome[0x20];
5478
5479 u8 reserved_at_40[0x40];
5480 };
5481
5482 struct mlx5_ifc_destroy_tis_in_bits {
5483 u8 opcode[0x10];
5484 u8 reserved_at_10[0x10];
5485
5486 u8 reserved_at_20[0x10];
5487 u8 op_mod[0x10];
5488
5489 u8 reserved_at_40[0x8];
5490 u8 tisn[0x18];
5491
5492 u8 reserved_at_60[0x20];
5493 };
5494
5495 struct mlx5_ifc_destroy_tir_out_bits {
5496 u8 status[0x8];
5497 u8 reserved_at_8[0x18];
5498
5499 u8 syndrome[0x20];
5500
5501 u8 reserved_at_40[0x40];
5502 };
5503
5504 struct mlx5_ifc_destroy_tir_in_bits {
5505 u8 opcode[0x10];
5506 u8 reserved_at_10[0x10];
5507
5508 u8 reserved_at_20[0x10];
5509 u8 op_mod[0x10];
5510
5511 u8 reserved_at_40[0x8];
5512 u8 tirn[0x18];
5513
5514 u8 reserved_at_60[0x20];
5515 };
5516
5517 struct mlx5_ifc_destroy_srq_out_bits {
5518 u8 status[0x8];
5519 u8 reserved_at_8[0x18];
5520
5521 u8 syndrome[0x20];
5522
5523 u8 reserved_at_40[0x40];
5524 };
5525
5526 struct mlx5_ifc_destroy_srq_in_bits {
5527 u8 opcode[0x10];
5528 u8 reserved_at_10[0x10];
5529
5530 u8 reserved_at_20[0x10];
5531 u8 op_mod[0x10];
5532
5533 u8 reserved_at_40[0x8];
5534 u8 srqn[0x18];
5535
5536 u8 reserved_at_60[0x20];
5537 };
5538
5539 struct mlx5_ifc_destroy_sq_out_bits {
5540 u8 status[0x8];
5541 u8 reserved_at_8[0x18];
5542
5543 u8 syndrome[0x20];
5544
5545 u8 reserved_at_40[0x40];
5546 };
5547
5548 struct mlx5_ifc_destroy_sq_in_bits {
5549 u8 opcode[0x10];
5550 u8 reserved_at_10[0x10];
5551
5552 u8 reserved_at_20[0x10];
5553 u8 op_mod[0x10];
5554
5555 u8 reserved_at_40[0x8];
5556 u8 sqn[0x18];
5557
5558 u8 reserved_at_60[0x20];
5559 };
5560
5561 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5562 u8 status[0x8];
5563 u8 reserved_at_8[0x18];
5564
5565 u8 syndrome[0x20];
5566
5567 u8 reserved_at_40[0x1c0];
5568 };
5569
5570 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5571 u8 opcode[0x10];
5572 u8 reserved_at_10[0x10];
5573
5574 u8 reserved_at_20[0x10];
5575 u8 op_mod[0x10];
5576
5577 u8 scheduling_hierarchy[0x8];
5578 u8 reserved_at_48[0x18];
5579
5580 u8 scheduling_element_id[0x20];
5581
5582 u8 reserved_at_80[0x180];
5583 };
5584
5585 struct mlx5_ifc_destroy_rqt_out_bits {
5586 u8 status[0x8];
5587 u8 reserved_at_8[0x18];
5588
5589 u8 syndrome[0x20];
5590
5591 u8 reserved_at_40[0x40];
5592 };
5593
5594 struct mlx5_ifc_destroy_rqt_in_bits {
5595 u8 opcode[0x10];
5596 u8 reserved_at_10[0x10];
5597
5598 u8 reserved_at_20[0x10];
5599 u8 op_mod[0x10];
5600
5601 u8 reserved_at_40[0x8];
5602 u8 rqtn[0x18];
5603
5604 u8 reserved_at_60[0x20];
5605 };
5606
5607 struct mlx5_ifc_destroy_rq_out_bits {
5608 u8 status[0x8];
5609 u8 reserved_at_8[0x18];
5610
5611 u8 syndrome[0x20];
5612
5613 u8 reserved_at_40[0x40];
5614 };
5615
5616 struct mlx5_ifc_destroy_rq_in_bits {
5617 u8 opcode[0x10];
5618 u8 reserved_at_10[0x10];
5619
5620 u8 reserved_at_20[0x10];
5621 u8 op_mod[0x10];
5622
5623 u8 reserved_at_40[0x8];
5624 u8 rqn[0x18];
5625
5626 u8 reserved_at_60[0x20];
5627 };
5628
5629 struct mlx5_ifc_destroy_rmp_out_bits {
5630 u8 status[0x8];
5631 u8 reserved_at_8[0x18];
5632
5633 u8 syndrome[0x20];
5634
5635 u8 reserved_at_40[0x40];
5636 };
5637
5638 struct mlx5_ifc_destroy_rmp_in_bits {
5639 u8 opcode[0x10];
5640 u8 reserved_at_10[0x10];
5641
5642 u8 reserved_at_20[0x10];
5643 u8 op_mod[0x10];
5644
5645 u8 reserved_at_40[0x8];
5646 u8 rmpn[0x18];
5647
5648 u8 reserved_at_60[0x20];
5649 };
5650
5651 struct mlx5_ifc_destroy_qp_out_bits {
5652 u8 status[0x8];
5653 u8 reserved_at_8[0x18];
5654
5655 u8 syndrome[0x20];
5656
5657 u8 reserved_at_40[0x40];
5658 };
5659
5660 struct mlx5_ifc_destroy_qp_in_bits {
5661 u8 opcode[0x10];
5662 u8 reserved_at_10[0x10];
5663
5664 u8 reserved_at_20[0x10];
5665 u8 op_mod[0x10];
5666
5667 u8 reserved_at_40[0x8];
5668 u8 qpn[0x18];
5669
5670 u8 reserved_at_60[0x20];
5671 };
5672
5673 struct mlx5_ifc_destroy_psv_out_bits {
5674 u8 status[0x8];
5675 u8 reserved_at_8[0x18];
5676
5677 u8 syndrome[0x20];
5678
5679 u8 reserved_at_40[0x40];
5680 };
5681
5682 struct mlx5_ifc_destroy_psv_in_bits {
5683 u8 opcode[0x10];
5684 u8 reserved_at_10[0x10];
5685
5686 u8 reserved_at_20[0x10];
5687 u8 op_mod[0x10];
5688
5689 u8 reserved_at_40[0x8];
5690 u8 psvn[0x18];
5691
5692 u8 reserved_at_60[0x20];
5693 };
5694
5695 struct mlx5_ifc_destroy_mkey_out_bits {
5696 u8 status[0x8];
5697 u8 reserved_at_8[0x18];
5698
5699 u8 syndrome[0x20];
5700
5701 u8 reserved_at_40[0x40];
5702 };
5703
5704 struct mlx5_ifc_destroy_mkey_in_bits {
5705 u8 opcode[0x10];
5706 u8 reserved_at_10[0x10];
5707
5708 u8 reserved_at_20[0x10];
5709 u8 op_mod[0x10];
5710
5711 u8 reserved_at_40[0x8];
5712 u8 mkey_index[0x18];
5713
5714 u8 reserved_at_60[0x20];
5715 };
5716
5717 struct mlx5_ifc_destroy_flow_table_out_bits {
5718 u8 status[0x8];
5719 u8 reserved_at_8[0x18];
5720
5721 u8 syndrome[0x20];
5722
5723 u8 reserved_at_40[0x40];
5724 };
5725
5726 struct mlx5_ifc_destroy_flow_table_in_bits {
5727 u8 opcode[0x10];
5728 u8 reserved_at_10[0x10];
5729
5730 u8 reserved_at_20[0x10];
5731 u8 op_mod[0x10];
5732
5733 u8 other_vport[0x1];
5734 u8 reserved_at_41[0xf];
5735 u8 vport_number[0x10];
5736
5737 u8 reserved_at_60[0x20];
5738
5739 u8 table_type[0x8];
5740 u8 reserved_at_88[0x18];
5741
5742 u8 reserved_at_a0[0x8];
5743 u8 table_id[0x18];
5744
5745 u8 reserved_at_c0[0x140];
5746 };
5747
5748 struct mlx5_ifc_destroy_flow_group_out_bits {
5749 u8 status[0x8];
5750 u8 reserved_at_8[0x18];
5751
5752 u8 syndrome[0x20];
5753
5754 u8 reserved_at_40[0x40];
5755 };
5756
5757 struct mlx5_ifc_destroy_flow_group_in_bits {
5758 u8 opcode[0x10];
5759 u8 reserved_at_10[0x10];
5760
5761 u8 reserved_at_20[0x10];
5762 u8 op_mod[0x10];
5763
5764 u8 other_vport[0x1];
5765 u8 reserved_at_41[0xf];
5766 u8 vport_number[0x10];
5767
5768 u8 reserved_at_60[0x20];
5769
5770 u8 table_type[0x8];
5771 u8 reserved_at_88[0x18];
5772
5773 u8 reserved_at_a0[0x8];
5774 u8 table_id[0x18];
5775
5776 u8 group_id[0x20];
5777
5778 u8 reserved_at_e0[0x120];
5779 };
5780
5781 struct mlx5_ifc_destroy_eq_out_bits {
5782 u8 status[0x8];
5783 u8 reserved_at_8[0x18];
5784
5785 u8 syndrome[0x20];
5786
5787 u8 reserved_at_40[0x40];
5788 };
5789
5790 struct mlx5_ifc_destroy_eq_in_bits {
5791 u8 opcode[0x10];
5792 u8 reserved_at_10[0x10];
5793
5794 u8 reserved_at_20[0x10];
5795 u8 op_mod[0x10];
5796
5797 u8 reserved_at_40[0x18];
5798 u8 eq_number[0x8];
5799
5800 u8 reserved_at_60[0x20];
5801 };
5802
5803 struct mlx5_ifc_destroy_dct_out_bits {
5804 u8 status[0x8];
5805 u8 reserved_at_8[0x18];
5806
5807 u8 syndrome[0x20];
5808
5809 u8 reserved_at_40[0x40];
5810 };
5811
5812 struct mlx5_ifc_destroy_dct_in_bits {
5813 u8 opcode[0x10];
5814 u8 reserved_at_10[0x10];
5815
5816 u8 reserved_at_20[0x10];
5817 u8 op_mod[0x10];
5818
5819 u8 reserved_at_40[0x8];
5820 u8 dctn[0x18];
5821
5822 u8 reserved_at_60[0x20];
5823 };
5824
5825 struct mlx5_ifc_destroy_cq_out_bits {
5826 u8 status[0x8];
5827 u8 reserved_at_8[0x18];
5828
5829 u8 syndrome[0x20];
5830
5831 u8 reserved_at_40[0x40];
5832 };
5833
5834 struct mlx5_ifc_destroy_cq_in_bits {
5835 u8 opcode[0x10];
5836 u8 reserved_at_10[0x10];
5837
5838 u8 reserved_at_20[0x10];
5839 u8 op_mod[0x10];
5840
5841 u8 reserved_at_40[0x8];
5842 u8 cqn[0x18];
5843
5844 u8 reserved_at_60[0x20];
5845 };
5846
5847 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5848 u8 status[0x8];
5849 u8 reserved_at_8[0x18];
5850
5851 u8 syndrome[0x20];
5852
5853 u8 reserved_at_40[0x40];
5854 };
5855
5856 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5857 u8 opcode[0x10];
5858 u8 reserved_at_10[0x10];
5859
5860 u8 reserved_at_20[0x10];
5861 u8 op_mod[0x10];
5862
5863 u8 reserved_at_40[0x20];
5864
5865 u8 reserved_at_60[0x10];
5866 u8 vxlan_udp_port[0x10];
5867 };
5868
5869 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5870 u8 status[0x8];
5871 u8 reserved_at_8[0x18];
5872
5873 u8 syndrome[0x20];
5874
5875 u8 reserved_at_40[0x40];
5876 };
5877
5878 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5879 u8 opcode[0x10];
5880 u8 reserved_at_10[0x10];
5881
5882 u8 reserved_at_20[0x10];
5883 u8 op_mod[0x10];
5884
5885 u8 reserved_at_40[0x60];
5886
5887 u8 reserved_at_a0[0x8];
5888 u8 table_index[0x18];
5889
5890 u8 reserved_at_c0[0x140];
5891 };
5892
5893 struct mlx5_ifc_delete_fte_out_bits {
5894 u8 status[0x8];
5895 u8 reserved_at_8[0x18];
5896
5897 u8 syndrome[0x20];
5898
5899 u8 reserved_at_40[0x40];
5900 };
5901
5902 struct mlx5_ifc_delete_fte_in_bits {
5903 u8 opcode[0x10];
5904 u8 reserved_at_10[0x10];
5905
5906 u8 reserved_at_20[0x10];
5907 u8 op_mod[0x10];
5908
5909 u8 other_vport[0x1];
5910 u8 reserved_at_41[0xf];
5911 u8 vport_number[0x10];
5912
5913 u8 reserved_at_60[0x20];
5914
5915 u8 table_type[0x8];
5916 u8 reserved_at_88[0x18];
5917
5918 u8 reserved_at_a0[0x8];
5919 u8 table_id[0x18];
5920
5921 u8 reserved_at_c0[0x40];
5922
5923 u8 flow_index[0x20];
5924
5925 u8 reserved_at_120[0xe0];
5926 };
5927
5928 struct mlx5_ifc_dealloc_xrcd_out_bits {
5929 u8 status[0x8];
5930 u8 reserved_at_8[0x18];
5931
5932 u8 syndrome[0x20];
5933
5934 u8 reserved_at_40[0x40];
5935 };
5936
5937 struct mlx5_ifc_dealloc_xrcd_in_bits {
5938 u8 opcode[0x10];
5939 u8 reserved_at_10[0x10];
5940
5941 u8 reserved_at_20[0x10];
5942 u8 op_mod[0x10];
5943
5944 u8 reserved_at_40[0x8];
5945 u8 xrcd[0x18];
5946
5947 u8 reserved_at_60[0x20];
5948 };
5949
5950 struct mlx5_ifc_dealloc_uar_out_bits {
5951 u8 status[0x8];
5952 u8 reserved_at_8[0x18];
5953
5954 u8 syndrome[0x20];
5955
5956 u8 reserved_at_40[0x40];
5957 };
5958
5959 struct mlx5_ifc_dealloc_uar_in_bits {
5960 u8 opcode[0x10];
5961 u8 reserved_at_10[0x10];
5962
5963 u8 reserved_at_20[0x10];
5964 u8 op_mod[0x10];
5965
5966 u8 reserved_at_40[0x8];
5967 u8 uar[0x18];
5968
5969 u8 reserved_at_60[0x20];
5970 };
5971
5972 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5973 u8 status[0x8];
5974 u8 reserved_at_8[0x18];
5975
5976 u8 syndrome[0x20];
5977
5978 u8 reserved_at_40[0x40];
5979 };
5980
5981 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5982 u8 opcode[0x10];
5983 u8 reserved_at_10[0x10];
5984
5985 u8 reserved_at_20[0x10];
5986 u8 op_mod[0x10];
5987
5988 u8 reserved_at_40[0x8];
5989 u8 transport_domain[0x18];
5990
5991 u8 reserved_at_60[0x20];
5992 };
5993
5994 struct mlx5_ifc_dealloc_q_counter_out_bits {
5995 u8 status[0x8];
5996 u8 reserved_at_8[0x18];
5997
5998 u8 syndrome[0x20];
5999
6000 u8 reserved_at_40[0x40];
6001 };
6002
6003 struct mlx5_ifc_dealloc_q_counter_in_bits {
6004 u8 opcode[0x10];
6005 u8 reserved_at_10[0x10];
6006
6007 u8 reserved_at_20[0x10];
6008 u8 op_mod[0x10];
6009
6010 u8 reserved_at_40[0x18];
6011 u8 counter_set_id[0x8];
6012
6013 u8 reserved_at_60[0x20];
6014 };
6015
6016 struct mlx5_ifc_dealloc_pd_out_bits {
6017 u8 status[0x8];
6018 u8 reserved_at_8[0x18];
6019
6020 u8 syndrome[0x20];
6021
6022 u8 reserved_at_40[0x40];
6023 };
6024
6025 struct mlx5_ifc_dealloc_pd_in_bits {
6026 u8 opcode[0x10];
6027 u8 reserved_at_10[0x10];
6028
6029 u8 reserved_at_20[0x10];
6030 u8 op_mod[0x10];
6031
6032 u8 reserved_at_40[0x8];
6033 u8 pd[0x18];
6034
6035 u8 reserved_at_60[0x20];
6036 };
6037
6038 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6039 u8 status[0x8];
6040 u8 reserved_at_8[0x18];
6041
6042 u8 syndrome[0x20];
6043
6044 u8 reserved_at_40[0x40];
6045 };
6046
6047 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6048 u8 opcode[0x10];
6049 u8 reserved_at_10[0x10];
6050
6051 u8 reserved_at_20[0x10];
6052 u8 op_mod[0x10];
6053
6054 u8 reserved_at_40[0x10];
6055 u8 flow_counter_id[0x10];
6056
6057 u8 reserved_at_60[0x20];
6058 };
6059
6060 struct mlx5_ifc_create_xrq_out_bits {
6061 u8 status[0x8];
6062 u8 reserved_at_8[0x18];
6063
6064 u8 syndrome[0x20];
6065
6066 u8 reserved_at_40[0x8];
6067 u8 xrqn[0x18];
6068
6069 u8 reserved_at_60[0x20];
6070 };
6071
6072 struct mlx5_ifc_create_xrq_in_bits {
6073 u8 opcode[0x10];
6074 u8 reserved_at_10[0x10];
6075
6076 u8 reserved_at_20[0x10];
6077 u8 op_mod[0x10];
6078
6079 u8 reserved_at_40[0x40];
6080
6081 struct mlx5_ifc_xrqc_bits xrq_context;
6082 };
6083
6084 struct mlx5_ifc_create_xrc_srq_out_bits {
6085 u8 status[0x8];
6086 u8 reserved_at_8[0x18];
6087
6088 u8 syndrome[0x20];
6089
6090 u8 reserved_at_40[0x8];
6091 u8 xrc_srqn[0x18];
6092
6093 u8 reserved_at_60[0x20];
6094 };
6095
6096 struct mlx5_ifc_create_xrc_srq_in_bits {
6097 u8 opcode[0x10];
6098 u8 reserved_at_10[0x10];
6099
6100 u8 reserved_at_20[0x10];
6101 u8 op_mod[0x10];
6102
6103 u8 reserved_at_40[0x40];
6104
6105 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6106
6107 u8 reserved_at_280[0x600];
6108
6109 u8 pas[0][0x40];
6110 };
6111
6112 struct mlx5_ifc_create_tis_out_bits {
6113 u8 status[0x8];
6114 u8 reserved_at_8[0x18];
6115
6116 u8 syndrome[0x20];
6117
6118 u8 reserved_at_40[0x8];
6119 u8 tisn[0x18];
6120
6121 u8 reserved_at_60[0x20];
6122 };
6123
6124 struct mlx5_ifc_create_tis_in_bits {
6125 u8 opcode[0x10];
6126 u8 reserved_at_10[0x10];
6127
6128 u8 reserved_at_20[0x10];
6129 u8 op_mod[0x10];
6130
6131 u8 reserved_at_40[0xc0];
6132
6133 struct mlx5_ifc_tisc_bits ctx;
6134 };
6135
6136 struct mlx5_ifc_create_tir_out_bits {
6137 u8 status[0x8];
6138 u8 reserved_at_8[0x18];
6139
6140 u8 syndrome[0x20];
6141
6142 u8 reserved_at_40[0x8];
6143 u8 tirn[0x18];
6144
6145 u8 reserved_at_60[0x20];
6146 };
6147
6148 struct mlx5_ifc_create_tir_in_bits {
6149 u8 opcode[0x10];
6150 u8 reserved_at_10[0x10];
6151
6152 u8 reserved_at_20[0x10];
6153 u8 op_mod[0x10];
6154
6155 u8 reserved_at_40[0xc0];
6156
6157 struct mlx5_ifc_tirc_bits ctx;
6158 };
6159
6160 struct mlx5_ifc_create_srq_out_bits {
6161 u8 status[0x8];
6162 u8 reserved_at_8[0x18];
6163
6164 u8 syndrome[0x20];
6165
6166 u8 reserved_at_40[0x8];
6167 u8 srqn[0x18];
6168
6169 u8 reserved_at_60[0x20];
6170 };
6171
6172 struct mlx5_ifc_create_srq_in_bits {
6173 u8 opcode[0x10];
6174 u8 reserved_at_10[0x10];
6175
6176 u8 reserved_at_20[0x10];
6177 u8 op_mod[0x10];
6178
6179 u8 reserved_at_40[0x40];
6180
6181 struct mlx5_ifc_srqc_bits srq_context_entry;
6182
6183 u8 reserved_at_280[0x600];
6184
6185 u8 pas[0][0x40];
6186 };
6187
6188 struct mlx5_ifc_create_sq_out_bits {
6189 u8 status[0x8];
6190 u8 reserved_at_8[0x18];
6191
6192 u8 syndrome[0x20];
6193
6194 u8 reserved_at_40[0x8];
6195 u8 sqn[0x18];
6196
6197 u8 reserved_at_60[0x20];
6198 };
6199
6200 struct mlx5_ifc_create_sq_in_bits {
6201 u8 opcode[0x10];
6202 u8 reserved_at_10[0x10];
6203
6204 u8 reserved_at_20[0x10];
6205 u8 op_mod[0x10];
6206
6207 u8 reserved_at_40[0xc0];
6208
6209 struct mlx5_ifc_sqc_bits ctx;
6210 };
6211
6212 struct mlx5_ifc_create_scheduling_element_out_bits {
6213 u8 status[0x8];
6214 u8 reserved_at_8[0x18];
6215
6216 u8 syndrome[0x20];
6217
6218 u8 reserved_at_40[0x40];
6219
6220 u8 scheduling_element_id[0x20];
6221
6222 u8 reserved_at_a0[0x160];
6223 };
6224
6225 struct mlx5_ifc_create_scheduling_element_in_bits {
6226 u8 opcode[0x10];
6227 u8 reserved_at_10[0x10];
6228
6229 u8 reserved_at_20[0x10];
6230 u8 op_mod[0x10];
6231
6232 u8 scheduling_hierarchy[0x8];
6233 u8 reserved_at_48[0x18];
6234
6235 u8 reserved_at_60[0xa0];
6236
6237 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6238
6239 u8 reserved_at_300[0x100];
6240 };
6241
6242 struct mlx5_ifc_create_rqt_out_bits {
6243 u8 status[0x8];
6244 u8 reserved_at_8[0x18];
6245
6246 u8 syndrome[0x20];
6247
6248 u8 reserved_at_40[0x8];
6249 u8 rqtn[0x18];
6250
6251 u8 reserved_at_60[0x20];
6252 };
6253
6254 struct mlx5_ifc_create_rqt_in_bits {
6255 u8 opcode[0x10];
6256 u8 reserved_at_10[0x10];
6257
6258 u8 reserved_at_20[0x10];
6259 u8 op_mod[0x10];
6260
6261 u8 reserved_at_40[0xc0];
6262
6263 struct mlx5_ifc_rqtc_bits rqt_context;
6264 };
6265
6266 struct mlx5_ifc_create_rq_out_bits {
6267 u8 status[0x8];
6268 u8 reserved_at_8[0x18];
6269
6270 u8 syndrome[0x20];
6271
6272 u8 reserved_at_40[0x8];
6273 u8 rqn[0x18];
6274
6275 u8 reserved_at_60[0x20];
6276 };
6277
6278 struct mlx5_ifc_create_rq_in_bits {
6279 u8 opcode[0x10];
6280 u8 reserved_at_10[0x10];
6281
6282 u8 reserved_at_20[0x10];
6283 u8 op_mod[0x10];
6284
6285 u8 reserved_at_40[0xc0];
6286
6287 struct mlx5_ifc_rqc_bits ctx;
6288 };
6289
6290 struct mlx5_ifc_create_rmp_out_bits {
6291 u8 status[0x8];
6292 u8 reserved_at_8[0x18];
6293
6294 u8 syndrome[0x20];
6295
6296 u8 reserved_at_40[0x8];
6297 u8 rmpn[0x18];
6298
6299 u8 reserved_at_60[0x20];
6300 };
6301
6302 struct mlx5_ifc_create_rmp_in_bits {
6303 u8 opcode[0x10];
6304 u8 reserved_at_10[0x10];
6305
6306 u8 reserved_at_20[0x10];
6307 u8 op_mod[0x10];
6308
6309 u8 reserved_at_40[0xc0];
6310
6311 struct mlx5_ifc_rmpc_bits ctx;
6312 };
6313
6314 struct mlx5_ifc_create_qp_out_bits {
6315 u8 status[0x8];
6316 u8 reserved_at_8[0x18];
6317
6318 u8 syndrome[0x20];
6319
6320 u8 reserved_at_40[0x8];
6321 u8 qpn[0x18];
6322
6323 u8 reserved_at_60[0x20];
6324 };
6325
6326 struct mlx5_ifc_create_qp_in_bits {
6327 u8 opcode[0x10];
6328 u8 reserved_at_10[0x10];
6329
6330 u8 reserved_at_20[0x10];
6331 u8 op_mod[0x10];
6332
6333 u8 reserved_at_40[0x40];
6334
6335 u8 opt_param_mask[0x20];
6336
6337 u8 reserved_at_a0[0x20];
6338
6339 struct mlx5_ifc_qpc_bits qpc;
6340
6341 u8 reserved_at_800[0x80];
6342
6343 u8 pas[0][0x40];
6344 };
6345
6346 struct mlx5_ifc_create_psv_out_bits {
6347 u8 status[0x8];
6348 u8 reserved_at_8[0x18];
6349
6350 u8 syndrome[0x20];
6351
6352 u8 reserved_at_40[0x40];
6353
6354 u8 reserved_at_80[0x8];
6355 u8 psv0_index[0x18];
6356
6357 u8 reserved_at_a0[0x8];
6358 u8 psv1_index[0x18];
6359
6360 u8 reserved_at_c0[0x8];
6361 u8 psv2_index[0x18];
6362
6363 u8 reserved_at_e0[0x8];
6364 u8 psv3_index[0x18];
6365 };
6366
6367 struct mlx5_ifc_create_psv_in_bits {
6368 u8 opcode[0x10];
6369 u8 reserved_at_10[0x10];
6370
6371 u8 reserved_at_20[0x10];
6372 u8 op_mod[0x10];
6373
6374 u8 num_psv[0x4];
6375 u8 reserved_at_44[0x4];
6376 u8 pd[0x18];
6377
6378 u8 reserved_at_60[0x20];
6379 };
6380
6381 struct mlx5_ifc_create_mkey_out_bits {
6382 u8 status[0x8];
6383 u8 reserved_at_8[0x18];
6384
6385 u8 syndrome[0x20];
6386
6387 u8 reserved_at_40[0x8];
6388 u8 mkey_index[0x18];
6389
6390 u8 reserved_at_60[0x20];
6391 };
6392
6393 struct mlx5_ifc_create_mkey_in_bits {
6394 u8 opcode[0x10];
6395 u8 reserved_at_10[0x10];
6396
6397 u8 reserved_at_20[0x10];
6398 u8 op_mod[0x10];
6399
6400 u8 reserved_at_40[0x20];
6401
6402 u8 pg_access[0x1];
6403 u8 reserved_at_61[0x1f];
6404
6405 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6406
6407 u8 reserved_at_280[0x80];
6408
6409 u8 translations_octword_actual_size[0x20];
6410
6411 u8 reserved_at_320[0x560];
6412
6413 u8 klm_pas_mtt[0][0x20];
6414 };
6415
6416 struct mlx5_ifc_create_flow_table_out_bits {
6417 u8 status[0x8];
6418 u8 reserved_at_8[0x18];
6419
6420 u8 syndrome[0x20];
6421
6422 u8 reserved_at_40[0x8];
6423 u8 table_id[0x18];
6424
6425 u8 reserved_at_60[0x20];
6426 };
6427
6428 struct mlx5_ifc_create_flow_table_in_bits {
6429 u8 opcode[0x10];
6430 u8 reserved_at_10[0x10];
6431
6432 u8 reserved_at_20[0x10];
6433 u8 op_mod[0x10];
6434
6435 u8 other_vport[0x1];
6436 u8 reserved_at_41[0xf];
6437 u8 vport_number[0x10];
6438
6439 u8 reserved_at_60[0x20];
6440
6441 u8 table_type[0x8];
6442 u8 reserved_at_88[0x18];
6443
6444 u8 reserved_at_a0[0x20];
6445
6446 u8 encap_en[0x1];
6447 u8 decap_en[0x1];
6448 u8 reserved_at_c2[0x2];
6449 u8 table_miss_mode[0x4];
6450 u8 level[0x8];
6451 u8 reserved_at_d0[0x8];
6452 u8 log_size[0x8];
6453
6454 u8 reserved_at_e0[0x8];
6455 u8 table_miss_id[0x18];
6456
6457 u8 reserved_at_100[0x8];
6458 u8 lag_master_next_table_id[0x18];
6459
6460 u8 reserved_at_120[0x80];
6461 };
6462
6463 struct mlx5_ifc_create_flow_group_out_bits {
6464 u8 status[0x8];
6465 u8 reserved_at_8[0x18];
6466
6467 u8 syndrome[0x20];
6468
6469 u8 reserved_at_40[0x8];
6470 u8 group_id[0x18];
6471
6472 u8 reserved_at_60[0x20];
6473 };
6474
6475 enum {
6476 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6477 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6478 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6479 };
6480
6481 struct mlx5_ifc_create_flow_group_in_bits {
6482 u8 opcode[0x10];
6483 u8 reserved_at_10[0x10];
6484
6485 u8 reserved_at_20[0x10];
6486 u8 op_mod[0x10];
6487
6488 u8 other_vport[0x1];
6489 u8 reserved_at_41[0xf];
6490 u8 vport_number[0x10];
6491
6492 u8 reserved_at_60[0x20];
6493
6494 u8 table_type[0x8];
6495 u8 reserved_at_88[0x18];
6496
6497 u8 reserved_at_a0[0x8];
6498 u8 table_id[0x18];
6499
6500 u8 reserved_at_c0[0x20];
6501
6502 u8 start_flow_index[0x20];
6503
6504 u8 reserved_at_100[0x20];
6505
6506 u8 end_flow_index[0x20];
6507
6508 u8 reserved_at_140[0xa0];
6509
6510 u8 reserved_at_1e0[0x18];
6511 u8 match_criteria_enable[0x8];
6512
6513 struct mlx5_ifc_fte_match_param_bits match_criteria;
6514
6515 u8 reserved_at_1200[0xe00];
6516 };
6517
6518 struct mlx5_ifc_create_eq_out_bits {
6519 u8 status[0x8];
6520 u8 reserved_at_8[0x18];
6521
6522 u8 syndrome[0x20];
6523
6524 u8 reserved_at_40[0x18];
6525 u8 eq_number[0x8];
6526
6527 u8 reserved_at_60[0x20];
6528 };
6529
6530 struct mlx5_ifc_create_eq_in_bits {
6531 u8 opcode[0x10];
6532 u8 reserved_at_10[0x10];
6533
6534 u8 reserved_at_20[0x10];
6535 u8 op_mod[0x10];
6536
6537 u8 reserved_at_40[0x40];
6538
6539 struct mlx5_ifc_eqc_bits eq_context_entry;
6540
6541 u8 reserved_at_280[0x40];
6542
6543 u8 event_bitmask[0x40];
6544
6545 u8 reserved_at_300[0x580];
6546
6547 u8 pas[0][0x40];
6548 };
6549
6550 struct mlx5_ifc_create_dct_out_bits {
6551 u8 status[0x8];
6552 u8 reserved_at_8[0x18];
6553
6554 u8 syndrome[0x20];
6555
6556 u8 reserved_at_40[0x8];
6557 u8 dctn[0x18];
6558
6559 u8 reserved_at_60[0x20];
6560 };
6561
6562 struct mlx5_ifc_create_dct_in_bits {
6563 u8 opcode[0x10];
6564 u8 reserved_at_10[0x10];
6565
6566 u8 reserved_at_20[0x10];
6567 u8 op_mod[0x10];
6568
6569 u8 reserved_at_40[0x40];
6570
6571 struct mlx5_ifc_dctc_bits dct_context_entry;
6572
6573 u8 reserved_at_280[0x180];
6574 };
6575
6576 struct mlx5_ifc_create_cq_out_bits {
6577 u8 status[0x8];
6578 u8 reserved_at_8[0x18];
6579
6580 u8 syndrome[0x20];
6581
6582 u8 reserved_at_40[0x8];
6583 u8 cqn[0x18];
6584
6585 u8 reserved_at_60[0x20];
6586 };
6587
6588 struct mlx5_ifc_create_cq_in_bits {
6589 u8 opcode[0x10];
6590 u8 reserved_at_10[0x10];
6591
6592 u8 reserved_at_20[0x10];
6593 u8 op_mod[0x10];
6594
6595 u8 reserved_at_40[0x40];
6596
6597 struct mlx5_ifc_cqc_bits cq_context;
6598
6599 u8 reserved_at_280[0x600];
6600
6601 u8 pas[0][0x40];
6602 };
6603
6604 struct mlx5_ifc_config_int_moderation_out_bits {
6605 u8 status[0x8];
6606 u8 reserved_at_8[0x18];
6607
6608 u8 syndrome[0x20];
6609
6610 u8 reserved_at_40[0x4];
6611 u8 min_delay[0xc];
6612 u8 int_vector[0x10];
6613
6614 u8 reserved_at_60[0x20];
6615 };
6616
6617 enum {
6618 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6619 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6620 };
6621
6622 struct mlx5_ifc_config_int_moderation_in_bits {
6623 u8 opcode[0x10];
6624 u8 reserved_at_10[0x10];
6625
6626 u8 reserved_at_20[0x10];
6627 u8 op_mod[0x10];
6628
6629 u8 reserved_at_40[0x4];
6630 u8 min_delay[0xc];
6631 u8 int_vector[0x10];
6632
6633 u8 reserved_at_60[0x20];
6634 };
6635
6636 struct mlx5_ifc_attach_to_mcg_out_bits {
6637 u8 status[0x8];
6638 u8 reserved_at_8[0x18];
6639
6640 u8 syndrome[0x20];
6641
6642 u8 reserved_at_40[0x40];
6643 };
6644
6645 struct mlx5_ifc_attach_to_mcg_in_bits {
6646 u8 opcode[0x10];
6647 u8 reserved_at_10[0x10];
6648
6649 u8 reserved_at_20[0x10];
6650 u8 op_mod[0x10];
6651
6652 u8 reserved_at_40[0x8];
6653 u8 qpn[0x18];
6654
6655 u8 reserved_at_60[0x20];
6656
6657 u8 multicast_gid[16][0x8];
6658 };
6659
6660 struct mlx5_ifc_arm_xrq_out_bits {
6661 u8 status[0x8];
6662 u8 reserved_at_8[0x18];
6663
6664 u8 syndrome[0x20];
6665
6666 u8 reserved_at_40[0x40];
6667 };
6668
6669 struct mlx5_ifc_arm_xrq_in_bits {
6670 u8 opcode[0x10];
6671 u8 reserved_at_10[0x10];
6672
6673 u8 reserved_at_20[0x10];
6674 u8 op_mod[0x10];
6675
6676 u8 reserved_at_40[0x8];
6677 u8 xrqn[0x18];
6678
6679 u8 reserved_at_60[0x10];
6680 u8 lwm[0x10];
6681 };
6682
6683 struct mlx5_ifc_arm_xrc_srq_out_bits {
6684 u8 status[0x8];
6685 u8 reserved_at_8[0x18];
6686
6687 u8 syndrome[0x20];
6688
6689 u8 reserved_at_40[0x40];
6690 };
6691
6692 enum {
6693 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6694 };
6695
6696 struct mlx5_ifc_arm_xrc_srq_in_bits {
6697 u8 opcode[0x10];
6698 u8 reserved_at_10[0x10];
6699
6700 u8 reserved_at_20[0x10];
6701 u8 op_mod[0x10];
6702
6703 u8 reserved_at_40[0x8];
6704 u8 xrc_srqn[0x18];
6705
6706 u8 reserved_at_60[0x10];
6707 u8 lwm[0x10];
6708 };
6709
6710 struct mlx5_ifc_arm_rq_out_bits {
6711 u8 status[0x8];
6712 u8 reserved_at_8[0x18];
6713
6714 u8 syndrome[0x20];
6715
6716 u8 reserved_at_40[0x40];
6717 };
6718
6719 enum {
6720 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6721 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6722 };
6723
6724 struct mlx5_ifc_arm_rq_in_bits {
6725 u8 opcode[0x10];
6726 u8 reserved_at_10[0x10];
6727
6728 u8 reserved_at_20[0x10];
6729 u8 op_mod[0x10];
6730
6731 u8 reserved_at_40[0x8];
6732 u8 srq_number[0x18];
6733
6734 u8 reserved_at_60[0x10];
6735 u8 lwm[0x10];
6736 };
6737
6738 struct mlx5_ifc_arm_dct_out_bits {
6739 u8 status[0x8];
6740 u8 reserved_at_8[0x18];
6741
6742 u8 syndrome[0x20];
6743
6744 u8 reserved_at_40[0x40];
6745 };
6746
6747 struct mlx5_ifc_arm_dct_in_bits {
6748 u8 opcode[0x10];
6749 u8 reserved_at_10[0x10];
6750
6751 u8 reserved_at_20[0x10];
6752 u8 op_mod[0x10];
6753
6754 u8 reserved_at_40[0x8];
6755 u8 dct_number[0x18];
6756
6757 u8 reserved_at_60[0x20];
6758 };
6759
6760 struct mlx5_ifc_alloc_xrcd_out_bits {
6761 u8 status[0x8];
6762 u8 reserved_at_8[0x18];
6763
6764 u8 syndrome[0x20];
6765
6766 u8 reserved_at_40[0x8];
6767 u8 xrcd[0x18];
6768
6769 u8 reserved_at_60[0x20];
6770 };
6771
6772 struct mlx5_ifc_alloc_xrcd_in_bits {
6773 u8 opcode[0x10];
6774 u8 reserved_at_10[0x10];
6775
6776 u8 reserved_at_20[0x10];
6777 u8 op_mod[0x10];
6778
6779 u8 reserved_at_40[0x40];
6780 };
6781
6782 struct mlx5_ifc_alloc_uar_out_bits {
6783 u8 status[0x8];
6784 u8 reserved_at_8[0x18];
6785
6786 u8 syndrome[0x20];
6787
6788 u8 reserved_at_40[0x8];
6789 u8 uar[0x18];
6790
6791 u8 reserved_at_60[0x20];
6792 };
6793
6794 struct mlx5_ifc_alloc_uar_in_bits {
6795 u8 opcode[0x10];
6796 u8 reserved_at_10[0x10];
6797
6798 u8 reserved_at_20[0x10];
6799 u8 op_mod[0x10];
6800
6801 u8 reserved_at_40[0x40];
6802 };
6803
6804 struct mlx5_ifc_alloc_transport_domain_out_bits {
6805 u8 status[0x8];
6806 u8 reserved_at_8[0x18];
6807
6808 u8 syndrome[0x20];
6809
6810 u8 reserved_at_40[0x8];
6811 u8 transport_domain[0x18];
6812
6813 u8 reserved_at_60[0x20];
6814 };
6815
6816 struct mlx5_ifc_alloc_transport_domain_in_bits {
6817 u8 opcode[0x10];
6818 u8 reserved_at_10[0x10];
6819
6820 u8 reserved_at_20[0x10];
6821 u8 op_mod[0x10];
6822
6823 u8 reserved_at_40[0x40];
6824 };
6825
6826 struct mlx5_ifc_alloc_q_counter_out_bits {
6827 u8 status[0x8];
6828 u8 reserved_at_8[0x18];
6829
6830 u8 syndrome[0x20];
6831
6832 u8 reserved_at_40[0x18];
6833 u8 counter_set_id[0x8];
6834
6835 u8 reserved_at_60[0x20];
6836 };
6837
6838 struct mlx5_ifc_alloc_q_counter_in_bits {
6839 u8 opcode[0x10];
6840 u8 reserved_at_10[0x10];
6841
6842 u8 reserved_at_20[0x10];
6843 u8 op_mod[0x10];
6844
6845 u8 reserved_at_40[0x40];
6846 };
6847
6848 struct mlx5_ifc_alloc_pd_out_bits {
6849 u8 status[0x8];
6850 u8 reserved_at_8[0x18];
6851
6852 u8 syndrome[0x20];
6853
6854 u8 reserved_at_40[0x8];
6855 u8 pd[0x18];
6856
6857 u8 reserved_at_60[0x20];
6858 };
6859
6860 struct mlx5_ifc_alloc_pd_in_bits {
6861 u8 opcode[0x10];
6862 u8 reserved_at_10[0x10];
6863
6864 u8 reserved_at_20[0x10];
6865 u8 op_mod[0x10];
6866
6867 u8 reserved_at_40[0x40];
6868 };
6869
6870 struct mlx5_ifc_alloc_flow_counter_out_bits {
6871 u8 status[0x8];
6872 u8 reserved_at_8[0x18];
6873
6874 u8 syndrome[0x20];
6875
6876 u8 reserved_at_40[0x10];
6877 u8 flow_counter_id[0x10];
6878
6879 u8 reserved_at_60[0x20];
6880 };
6881
6882 struct mlx5_ifc_alloc_flow_counter_in_bits {
6883 u8 opcode[0x10];
6884 u8 reserved_at_10[0x10];
6885
6886 u8 reserved_at_20[0x10];
6887 u8 op_mod[0x10];
6888
6889 u8 reserved_at_40[0x40];
6890 };
6891
6892 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6893 u8 status[0x8];
6894 u8 reserved_at_8[0x18];
6895
6896 u8 syndrome[0x20];
6897
6898 u8 reserved_at_40[0x40];
6899 };
6900
6901 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6902 u8 opcode[0x10];
6903 u8 reserved_at_10[0x10];
6904
6905 u8 reserved_at_20[0x10];
6906 u8 op_mod[0x10];
6907
6908 u8 reserved_at_40[0x20];
6909
6910 u8 reserved_at_60[0x10];
6911 u8 vxlan_udp_port[0x10];
6912 };
6913
6914 struct mlx5_ifc_set_rate_limit_out_bits {
6915 u8 status[0x8];
6916 u8 reserved_at_8[0x18];
6917
6918 u8 syndrome[0x20];
6919
6920 u8 reserved_at_40[0x40];
6921 };
6922
6923 struct mlx5_ifc_set_rate_limit_in_bits {
6924 u8 opcode[0x10];
6925 u8 reserved_at_10[0x10];
6926
6927 u8 reserved_at_20[0x10];
6928 u8 op_mod[0x10];
6929
6930 u8 reserved_at_40[0x10];
6931 u8 rate_limit_index[0x10];
6932
6933 u8 reserved_at_60[0x20];
6934
6935 u8 rate_limit[0x20];
6936 };
6937
6938 struct mlx5_ifc_access_register_out_bits {
6939 u8 status[0x8];
6940 u8 reserved_at_8[0x18];
6941
6942 u8 syndrome[0x20];
6943
6944 u8 reserved_at_40[0x40];
6945
6946 u8 register_data[0][0x20];
6947 };
6948
6949 enum {
6950 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6951 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6952 };
6953
6954 struct mlx5_ifc_access_register_in_bits {
6955 u8 opcode[0x10];
6956 u8 reserved_at_10[0x10];
6957
6958 u8 reserved_at_20[0x10];
6959 u8 op_mod[0x10];
6960
6961 u8 reserved_at_40[0x10];
6962 u8 register_id[0x10];
6963
6964 u8 argument[0x20];
6965
6966 u8 register_data[0][0x20];
6967 };
6968
6969 struct mlx5_ifc_sltp_reg_bits {
6970 u8 status[0x4];
6971 u8 version[0x4];
6972 u8 local_port[0x8];
6973 u8 pnat[0x2];
6974 u8 reserved_at_12[0x2];
6975 u8 lane[0x4];
6976 u8 reserved_at_18[0x8];
6977
6978 u8 reserved_at_20[0x20];
6979
6980 u8 reserved_at_40[0x7];
6981 u8 polarity[0x1];
6982 u8 ob_tap0[0x8];
6983 u8 ob_tap1[0x8];
6984 u8 ob_tap2[0x8];
6985
6986 u8 reserved_at_60[0xc];
6987 u8 ob_preemp_mode[0x4];
6988 u8 ob_reg[0x8];
6989 u8 ob_bias[0x8];
6990
6991 u8 reserved_at_80[0x20];
6992 };
6993
6994 struct mlx5_ifc_slrg_reg_bits {
6995 u8 status[0x4];
6996 u8 version[0x4];
6997 u8 local_port[0x8];
6998 u8 pnat[0x2];
6999 u8 reserved_at_12[0x2];
7000 u8 lane[0x4];
7001 u8 reserved_at_18[0x8];
7002
7003 u8 time_to_link_up[0x10];
7004 u8 reserved_at_30[0xc];
7005 u8 grade_lane_speed[0x4];
7006
7007 u8 grade_version[0x8];
7008 u8 grade[0x18];
7009
7010 u8 reserved_at_60[0x4];
7011 u8 height_grade_type[0x4];
7012 u8 height_grade[0x18];
7013
7014 u8 height_dz[0x10];
7015 u8 height_dv[0x10];
7016
7017 u8 reserved_at_a0[0x10];
7018 u8 height_sigma[0x10];
7019
7020 u8 reserved_at_c0[0x20];
7021
7022 u8 reserved_at_e0[0x4];
7023 u8 phase_grade_type[0x4];
7024 u8 phase_grade[0x18];
7025
7026 u8 reserved_at_100[0x8];
7027 u8 phase_eo_pos[0x8];
7028 u8 reserved_at_110[0x8];
7029 u8 phase_eo_neg[0x8];
7030
7031 u8 ffe_set_tested[0x10];
7032 u8 test_errors_per_lane[0x10];
7033 };
7034
7035 struct mlx5_ifc_pvlc_reg_bits {
7036 u8 reserved_at_0[0x8];
7037 u8 local_port[0x8];
7038 u8 reserved_at_10[0x10];
7039
7040 u8 reserved_at_20[0x1c];
7041 u8 vl_hw_cap[0x4];
7042
7043 u8 reserved_at_40[0x1c];
7044 u8 vl_admin[0x4];
7045
7046 u8 reserved_at_60[0x1c];
7047 u8 vl_operational[0x4];
7048 };
7049
7050 struct mlx5_ifc_pude_reg_bits {
7051 u8 swid[0x8];
7052 u8 local_port[0x8];
7053 u8 reserved_at_10[0x4];
7054 u8 admin_status[0x4];
7055 u8 reserved_at_18[0x4];
7056 u8 oper_status[0x4];
7057
7058 u8 reserved_at_20[0x60];
7059 };
7060
7061 struct mlx5_ifc_ptys_reg_bits {
7062 u8 reserved_at_0[0x1];
7063 u8 an_disable_admin[0x1];
7064 u8 an_disable_cap[0x1];
7065 u8 reserved_at_3[0x5];
7066 u8 local_port[0x8];
7067 u8 reserved_at_10[0xd];
7068 u8 proto_mask[0x3];
7069
7070 u8 an_status[0x4];
7071 u8 reserved_at_24[0x3c];
7072
7073 u8 eth_proto_capability[0x20];
7074
7075 u8 ib_link_width_capability[0x10];
7076 u8 ib_proto_capability[0x10];
7077
7078 u8 reserved_at_a0[0x20];
7079
7080 u8 eth_proto_admin[0x20];
7081
7082 u8 ib_link_width_admin[0x10];
7083 u8 ib_proto_admin[0x10];
7084
7085 u8 reserved_at_100[0x20];
7086
7087 u8 eth_proto_oper[0x20];
7088
7089 u8 ib_link_width_oper[0x10];
7090 u8 ib_proto_oper[0x10];
7091
7092 u8 reserved_at_160[0x20];
7093
7094 u8 eth_proto_lp_advertise[0x20];
7095
7096 u8 reserved_at_1a0[0x60];
7097 };
7098
7099 struct mlx5_ifc_mlcr_reg_bits {
7100 u8 reserved_at_0[0x8];
7101 u8 local_port[0x8];
7102 u8 reserved_at_10[0x20];
7103
7104 u8 beacon_duration[0x10];
7105 u8 reserved_at_40[0x10];
7106
7107 u8 beacon_remain[0x10];
7108 };
7109
7110 struct mlx5_ifc_ptas_reg_bits {
7111 u8 reserved_at_0[0x20];
7112
7113 u8 algorithm_options[0x10];
7114 u8 reserved_at_30[0x4];
7115 u8 repetitions_mode[0x4];
7116 u8 num_of_repetitions[0x8];
7117
7118 u8 grade_version[0x8];
7119 u8 height_grade_type[0x4];
7120 u8 phase_grade_type[0x4];
7121 u8 height_grade_weight[0x8];
7122 u8 phase_grade_weight[0x8];
7123
7124 u8 gisim_measure_bits[0x10];
7125 u8 adaptive_tap_measure_bits[0x10];
7126
7127 u8 ber_bath_high_error_threshold[0x10];
7128 u8 ber_bath_mid_error_threshold[0x10];
7129
7130 u8 ber_bath_low_error_threshold[0x10];
7131 u8 one_ratio_high_threshold[0x10];
7132
7133 u8 one_ratio_high_mid_threshold[0x10];
7134 u8 one_ratio_low_mid_threshold[0x10];
7135
7136 u8 one_ratio_low_threshold[0x10];
7137 u8 ndeo_error_threshold[0x10];
7138
7139 u8 mixer_offset_step_size[0x10];
7140 u8 reserved_at_110[0x8];
7141 u8 mix90_phase_for_voltage_bath[0x8];
7142
7143 u8 mixer_offset_start[0x10];
7144 u8 mixer_offset_end[0x10];
7145
7146 u8 reserved_at_140[0x15];
7147 u8 ber_test_time[0xb];
7148 };
7149
7150 struct mlx5_ifc_pspa_reg_bits {
7151 u8 swid[0x8];
7152 u8 local_port[0x8];
7153 u8 sub_port[0x8];
7154 u8 reserved_at_18[0x8];
7155
7156 u8 reserved_at_20[0x20];
7157 };
7158
7159 struct mlx5_ifc_pqdr_reg_bits {
7160 u8 reserved_at_0[0x8];
7161 u8 local_port[0x8];
7162 u8 reserved_at_10[0x5];
7163 u8 prio[0x3];
7164 u8 reserved_at_18[0x6];
7165 u8 mode[0x2];
7166
7167 u8 reserved_at_20[0x20];
7168
7169 u8 reserved_at_40[0x10];
7170 u8 min_threshold[0x10];
7171
7172 u8 reserved_at_60[0x10];
7173 u8 max_threshold[0x10];
7174
7175 u8 reserved_at_80[0x10];
7176 u8 mark_probability_denominator[0x10];
7177
7178 u8 reserved_at_a0[0x60];
7179 };
7180
7181 struct mlx5_ifc_ppsc_reg_bits {
7182 u8 reserved_at_0[0x8];
7183 u8 local_port[0x8];
7184 u8 reserved_at_10[0x10];
7185
7186 u8 reserved_at_20[0x60];
7187
7188 u8 reserved_at_80[0x1c];
7189 u8 wrps_admin[0x4];
7190
7191 u8 reserved_at_a0[0x1c];
7192 u8 wrps_status[0x4];
7193
7194 u8 reserved_at_c0[0x8];
7195 u8 up_threshold[0x8];
7196 u8 reserved_at_d0[0x8];
7197 u8 down_threshold[0x8];
7198
7199 u8 reserved_at_e0[0x20];
7200
7201 u8 reserved_at_100[0x1c];
7202 u8 srps_admin[0x4];
7203
7204 u8 reserved_at_120[0x1c];
7205 u8 srps_status[0x4];
7206
7207 u8 reserved_at_140[0x40];
7208 };
7209
7210 struct mlx5_ifc_pplr_reg_bits {
7211 u8 reserved_at_0[0x8];
7212 u8 local_port[0x8];
7213 u8 reserved_at_10[0x10];
7214
7215 u8 reserved_at_20[0x8];
7216 u8 lb_cap[0x8];
7217 u8 reserved_at_30[0x8];
7218 u8 lb_en[0x8];
7219 };
7220
7221 struct mlx5_ifc_pplm_reg_bits {
7222 u8 reserved_at_0[0x8];
7223 u8 local_port[0x8];
7224 u8 reserved_at_10[0x10];
7225
7226 u8 reserved_at_20[0x20];
7227
7228 u8 port_profile_mode[0x8];
7229 u8 static_port_profile[0x8];
7230 u8 active_port_profile[0x8];
7231 u8 reserved_at_58[0x8];
7232
7233 u8 retransmission_active[0x8];
7234 u8 fec_mode_active[0x18];
7235
7236 u8 reserved_at_80[0x20];
7237 };
7238
7239 struct mlx5_ifc_ppcnt_reg_bits {
7240 u8 swid[0x8];
7241 u8 local_port[0x8];
7242 u8 pnat[0x2];
7243 u8 reserved_at_12[0x8];
7244 u8 grp[0x6];
7245
7246 u8 clr[0x1];
7247 u8 reserved_at_21[0x1c];
7248 u8 prio_tc[0x3];
7249
7250 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7251 };
7252
7253 struct mlx5_ifc_ppad_reg_bits {
7254 u8 reserved_at_0[0x3];
7255 u8 single_mac[0x1];
7256 u8 reserved_at_4[0x4];
7257 u8 local_port[0x8];
7258 u8 mac_47_32[0x10];
7259
7260 u8 mac_31_0[0x20];
7261
7262 u8 reserved_at_40[0x40];
7263 };
7264
7265 struct mlx5_ifc_pmtu_reg_bits {
7266 u8 reserved_at_0[0x8];
7267 u8 local_port[0x8];
7268 u8 reserved_at_10[0x10];
7269
7270 u8 max_mtu[0x10];
7271 u8 reserved_at_30[0x10];
7272
7273 u8 admin_mtu[0x10];
7274 u8 reserved_at_50[0x10];
7275
7276 u8 oper_mtu[0x10];
7277 u8 reserved_at_70[0x10];
7278 };
7279
7280 struct mlx5_ifc_pmpr_reg_bits {
7281 u8 reserved_at_0[0x8];
7282 u8 module[0x8];
7283 u8 reserved_at_10[0x10];
7284
7285 u8 reserved_at_20[0x18];
7286 u8 attenuation_5g[0x8];
7287
7288 u8 reserved_at_40[0x18];
7289 u8 attenuation_7g[0x8];
7290
7291 u8 reserved_at_60[0x18];
7292 u8 attenuation_12g[0x8];
7293 };
7294
7295 struct mlx5_ifc_pmpe_reg_bits {
7296 u8 reserved_at_0[0x8];
7297 u8 module[0x8];
7298 u8 reserved_at_10[0xc];
7299 u8 module_status[0x4];
7300
7301 u8 reserved_at_20[0x60];
7302 };
7303
7304 struct mlx5_ifc_pmpc_reg_bits {
7305 u8 module_state_updated[32][0x8];
7306 };
7307
7308 struct mlx5_ifc_pmlpn_reg_bits {
7309 u8 reserved_at_0[0x4];
7310 u8 mlpn_status[0x4];
7311 u8 local_port[0x8];
7312 u8 reserved_at_10[0x10];
7313
7314 u8 e[0x1];
7315 u8 reserved_at_21[0x1f];
7316 };
7317
7318 struct mlx5_ifc_pmlp_reg_bits {
7319 u8 rxtx[0x1];
7320 u8 reserved_at_1[0x7];
7321 u8 local_port[0x8];
7322 u8 reserved_at_10[0x8];
7323 u8 width[0x8];
7324
7325 u8 lane0_module_mapping[0x20];
7326
7327 u8 lane1_module_mapping[0x20];
7328
7329 u8 lane2_module_mapping[0x20];
7330
7331 u8 lane3_module_mapping[0x20];
7332
7333 u8 reserved_at_a0[0x160];
7334 };
7335
7336 struct mlx5_ifc_pmaos_reg_bits {
7337 u8 reserved_at_0[0x8];
7338 u8 module[0x8];
7339 u8 reserved_at_10[0x4];
7340 u8 admin_status[0x4];
7341 u8 reserved_at_18[0x4];
7342 u8 oper_status[0x4];
7343
7344 u8 ase[0x1];
7345 u8 ee[0x1];
7346 u8 reserved_at_22[0x1c];
7347 u8 e[0x2];
7348
7349 u8 reserved_at_40[0x40];
7350 };
7351
7352 struct mlx5_ifc_plpc_reg_bits {
7353 u8 reserved_at_0[0x4];
7354 u8 profile_id[0xc];
7355 u8 reserved_at_10[0x4];
7356 u8 proto_mask[0x4];
7357 u8 reserved_at_18[0x8];
7358
7359 u8 reserved_at_20[0x10];
7360 u8 lane_speed[0x10];
7361
7362 u8 reserved_at_40[0x17];
7363 u8 lpbf[0x1];
7364 u8 fec_mode_policy[0x8];
7365
7366 u8 retransmission_capability[0x8];
7367 u8 fec_mode_capability[0x18];
7368
7369 u8 retransmission_support_admin[0x8];
7370 u8 fec_mode_support_admin[0x18];
7371
7372 u8 retransmission_request_admin[0x8];
7373 u8 fec_mode_request_admin[0x18];
7374
7375 u8 reserved_at_c0[0x80];
7376 };
7377
7378 struct mlx5_ifc_plib_reg_bits {
7379 u8 reserved_at_0[0x8];
7380 u8 local_port[0x8];
7381 u8 reserved_at_10[0x8];
7382 u8 ib_port[0x8];
7383
7384 u8 reserved_at_20[0x60];
7385 };
7386
7387 struct mlx5_ifc_plbf_reg_bits {
7388 u8 reserved_at_0[0x8];
7389 u8 local_port[0x8];
7390 u8 reserved_at_10[0xd];
7391 u8 lbf_mode[0x3];
7392
7393 u8 reserved_at_20[0x20];
7394 };
7395
7396 struct mlx5_ifc_pipg_reg_bits {
7397 u8 reserved_at_0[0x8];
7398 u8 local_port[0x8];
7399 u8 reserved_at_10[0x10];
7400
7401 u8 dic[0x1];
7402 u8 reserved_at_21[0x19];
7403 u8 ipg[0x4];
7404 u8 reserved_at_3e[0x2];
7405 };
7406
7407 struct mlx5_ifc_pifr_reg_bits {
7408 u8 reserved_at_0[0x8];
7409 u8 local_port[0x8];
7410 u8 reserved_at_10[0x10];
7411
7412 u8 reserved_at_20[0xe0];
7413
7414 u8 port_filter[8][0x20];
7415
7416 u8 port_filter_update_en[8][0x20];
7417 };
7418
7419 struct mlx5_ifc_pfcc_reg_bits {
7420 u8 reserved_at_0[0x8];
7421 u8 local_port[0x8];
7422 u8 reserved_at_10[0x10];
7423
7424 u8 ppan[0x4];
7425 u8 reserved_at_24[0x4];
7426 u8 prio_mask_tx[0x8];
7427 u8 reserved_at_30[0x8];
7428 u8 prio_mask_rx[0x8];
7429
7430 u8 pptx[0x1];
7431 u8 aptx[0x1];
7432 u8 reserved_at_42[0x6];
7433 u8 pfctx[0x8];
7434 u8 reserved_at_50[0x10];
7435
7436 u8 pprx[0x1];
7437 u8 aprx[0x1];
7438 u8 reserved_at_62[0x6];
7439 u8 pfcrx[0x8];
7440 u8 reserved_at_70[0x10];
7441
7442 u8 reserved_at_80[0x80];
7443 };
7444
7445 struct mlx5_ifc_pelc_reg_bits {
7446 u8 op[0x4];
7447 u8 reserved_at_4[0x4];
7448 u8 local_port[0x8];
7449 u8 reserved_at_10[0x10];
7450
7451 u8 op_admin[0x8];
7452 u8 op_capability[0x8];
7453 u8 op_request[0x8];
7454 u8 op_active[0x8];
7455
7456 u8 admin[0x40];
7457
7458 u8 capability[0x40];
7459
7460 u8 request[0x40];
7461
7462 u8 active[0x40];
7463
7464 u8 reserved_at_140[0x80];
7465 };
7466
7467 struct mlx5_ifc_peir_reg_bits {
7468 u8 reserved_at_0[0x8];
7469 u8 local_port[0x8];
7470 u8 reserved_at_10[0x10];
7471
7472 u8 reserved_at_20[0xc];
7473 u8 error_count[0x4];
7474 u8 reserved_at_30[0x10];
7475
7476 u8 reserved_at_40[0xc];
7477 u8 lane[0x4];
7478 u8 reserved_at_50[0x8];
7479 u8 error_type[0x8];
7480 };
7481
7482 struct mlx5_ifc_pcap_reg_bits {
7483 u8 reserved_at_0[0x8];
7484 u8 local_port[0x8];
7485 u8 reserved_at_10[0x10];
7486
7487 u8 port_capability_mask[4][0x20];
7488 };
7489
7490 struct mlx5_ifc_paos_reg_bits {
7491 u8 swid[0x8];
7492 u8 local_port[0x8];
7493 u8 reserved_at_10[0x4];
7494 u8 admin_status[0x4];
7495 u8 reserved_at_18[0x4];
7496 u8 oper_status[0x4];
7497
7498 u8 ase[0x1];
7499 u8 ee[0x1];
7500 u8 reserved_at_22[0x1c];
7501 u8 e[0x2];
7502
7503 u8 reserved_at_40[0x40];
7504 };
7505
7506 struct mlx5_ifc_pamp_reg_bits {
7507 u8 reserved_at_0[0x8];
7508 u8 opamp_group[0x8];
7509 u8 reserved_at_10[0xc];
7510 u8 opamp_group_type[0x4];
7511
7512 u8 start_index[0x10];
7513 u8 reserved_at_30[0x4];
7514 u8 num_of_indices[0xc];
7515
7516 u8 index_data[18][0x10];
7517 };
7518
7519 struct mlx5_ifc_pcmr_reg_bits {
7520 u8 reserved_at_0[0x8];
7521 u8 local_port[0x8];
7522 u8 reserved_at_10[0x2e];
7523 u8 fcs_cap[0x1];
7524 u8 reserved_at_3f[0x1f];
7525 u8 fcs_chk[0x1];
7526 u8 reserved_at_5f[0x1];
7527 };
7528
7529 struct mlx5_ifc_lane_2_module_mapping_bits {
7530 u8 reserved_at_0[0x6];
7531 u8 rx_lane[0x2];
7532 u8 reserved_at_8[0x6];
7533 u8 tx_lane[0x2];
7534 u8 reserved_at_10[0x8];
7535 u8 module[0x8];
7536 };
7537
7538 struct mlx5_ifc_bufferx_reg_bits {
7539 u8 reserved_at_0[0x6];
7540 u8 lossy[0x1];
7541 u8 epsb[0x1];
7542 u8 reserved_at_8[0xc];
7543 u8 size[0xc];
7544
7545 u8 xoff_threshold[0x10];
7546 u8 xon_threshold[0x10];
7547 };
7548
7549 struct mlx5_ifc_set_node_in_bits {
7550 u8 node_description[64][0x8];
7551 };
7552
7553 struct mlx5_ifc_register_power_settings_bits {
7554 u8 reserved_at_0[0x18];
7555 u8 power_settings_level[0x8];
7556
7557 u8 reserved_at_20[0x60];
7558 };
7559
7560 struct mlx5_ifc_register_host_endianness_bits {
7561 u8 he[0x1];
7562 u8 reserved_at_1[0x1f];
7563
7564 u8 reserved_at_20[0x60];
7565 };
7566
7567 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7568 u8 reserved_at_0[0x20];
7569
7570 u8 mkey[0x20];
7571
7572 u8 addressh_63_32[0x20];
7573
7574 u8 addressl_31_0[0x20];
7575 };
7576
7577 struct mlx5_ifc_ud_adrs_vector_bits {
7578 u8 dc_key[0x40];
7579
7580 u8 ext[0x1];
7581 u8 reserved_at_41[0x7];
7582 u8 destination_qp_dct[0x18];
7583
7584 u8 static_rate[0x4];
7585 u8 sl_eth_prio[0x4];
7586 u8 fl[0x1];
7587 u8 mlid[0x7];
7588 u8 rlid_udp_sport[0x10];
7589
7590 u8 reserved_at_80[0x20];
7591
7592 u8 rmac_47_16[0x20];
7593
7594 u8 rmac_15_0[0x10];
7595 u8 tclass[0x8];
7596 u8 hop_limit[0x8];
7597
7598 u8 reserved_at_e0[0x1];
7599 u8 grh[0x1];
7600 u8 reserved_at_e2[0x2];
7601 u8 src_addr_index[0x8];
7602 u8 flow_label[0x14];
7603
7604 u8 rgid_rip[16][0x8];
7605 };
7606
7607 struct mlx5_ifc_pages_req_event_bits {
7608 u8 reserved_at_0[0x10];
7609 u8 function_id[0x10];
7610
7611 u8 num_pages[0x20];
7612
7613 u8 reserved_at_40[0xa0];
7614 };
7615
7616 struct mlx5_ifc_eqe_bits {
7617 u8 reserved_at_0[0x8];
7618 u8 event_type[0x8];
7619 u8 reserved_at_10[0x8];
7620 u8 event_sub_type[0x8];
7621
7622 u8 reserved_at_20[0xe0];
7623
7624 union mlx5_ifc_event_auto_bits event_data;
7625
7626 u8 reserved_at_1e0[0x10];
7627 u8 signature[0x8];
7628 u8 reserved_at_1f8[0x7];
7629 u8 owner[0x1];
7630 };
7631
7632 enum {
7633 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7634 };
7635
7636 struct mlx5_ifc_cmd_queue_entry_bits {
7637 u8 type[0x8];
7638 u8 reserved_at_8[0x18];
7639
7640 u8 input_length[0x20];
7641
7642 u8 input_mailbox_pointer_63_32[0x20];
7643
7644 u8 input_mailbox_pointer_31_9[0x17];
7645 u8 reserved_at_77[0x9];
7646
7647 u8 command_input_inline_data[16][0x8];
7648
7649 u8 command_output_inline_data[16][0x8];
7650
7651 u8 output_mailbox_pointer_63_32[0x20];
7652
7653 u8 output_mailbox_pointer_31_9[0x17];
7654 u8 reserved_at_1b7[0x9];
7655
7656 u8 output_length[0x20];
7657
7658 u8 token[0x8];
7659 u8 signature[0x8];
7660 u8 reserved_at_1f0[0x8];
7661 u8 status[0x7];
7662 u8 ownership[0x1];
7663 };
7664
7665 struct mlx5_ifc_cmd_out_bits {
7666 u8 status[0x8];
7667 u8 reserved_at_8[0x18];
7668
7669 u8 syndrome[0x20];
7670
7671 u8 command_output[0x20];
7672 };
7673
7674 struct mlx5_ifc_cmd_in_bits {
7675 u8 opcode[0x10];
7676 u8 reserved_at_10[0x10];
7677
7678 u8 reserved_at_20[0x10];
7679 u8 op_mod[0x10];
7680
7681 u8 command[0][0x20];
7682 };
7683
7684 struct mlx5_ifc_cmd_if_box_bits {
7685 u8 mailbox_data[512][0x8];
7686
7687 u8 reserved_at_1000[0x180];
7688
7689 u8 next_pointer_63_32[0x20];
7690
7691 u8 next_pointer_31_10[0x16];
7692 u8 reserved_at_11b6[0xa];
7693
7694 u8 block_number[0x20];
7695
7696 u8 reserved_at_11e0[0x8];
7697 u8 token[0x8];
7698 u8 ctrl_signature[0x8];
7699 u8 signature[0x8];
7700 };
7701
7702 struct mlx5_ifc_mtt_bits {
7703 u8 ptag_63_32[0x20];
7704
7705 u8 ptag_31_8[0x18];
7706 u8 reserved_at_38[0x6];
7707 u8 wr_en[0x1];
7708 u8 rd_en[0x1];
7709 };
7710
7711 struct mlx5_ifc_query_wol_rol_out_bits {
7712 u8 status[0x8];
7713 u8 reserved_at_8[0x18];
7714
7715 u8 syndrome[0x20];
7716
7717 u8 reserved_at_40[0x10];
7718 u8 rol_mode[0x8];
7719 u8 wol_mode[0x8];
7720
7721 u8 reserved_at_60[0x20];
7722 };
7723
7724 struct mlx5_ifc_query_wol_rol_in_bits {
7725 u8 opcode[0x10];
7726 u8 reserved_at_10[0x10];
7727
7728 u8 reserved_at_20[0x10];
7729 u8 op_mod[0x10];
7730
7731 u8 reserved_at_40[0x40];
7732 };
7733
7734 struct mlx5_ifc_set_wol_rol_out_bits {
7735 u8 status[0x8];
7736 u8 reserved_at_8[0x18];
7737
7738 u8 syndrome[0x20];
7739
7740 u8 reserved_at_40[0x40];
7741 };
7742
7743 struct mlx5_ifc_set_wol_rol_in_bits {
7744 u8 opcode[0x10];
7745 u8 reserved_at_10[0x10];
7746
7747 u8 reserved_at_20[0x10];
7748 u8 op_mod[0x10];
7749
7750 u8 rol_mode_valid[0x1];
7751 u8 wol_mode_valid[0x1];
7752 u8 reserved_at_42[0xe];
7753 u8 rol_mode[0x8];
7754 u8 wol_mode[0x8];
7755
7756 u8 reserved_at_60[0x20];
7757 };
7758
7759 enum {
7760 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7761 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7762 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7763 };
7764
7765 enum {
7766 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7767 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7768 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7769 };
7770
7771 enum {
7772 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7773 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7774 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7775 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7776 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7777 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7778 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7779 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7780 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7781 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7782 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7783 };
7784
7785 struct mlx5_ifc_initial_seg_bits {
7786 u8 fw_rev_minor[0x10];
7787 u8 fw_rev_major[0x10];
7788
7789 u8 cmd_interface_rev[0x10];
7790 u8 fw_rev_subminor[0x10];
7791
7792 u8 reserved_at_40[0x40];
7793
7794 u8 cmdq_phy_addr_63_32[0x20];
7795
7796 u8 cmdq_phy_addr_31_12[0x14];
7797 u8 reserved_at_b4[0x2];
7798 u8 nic_interface[0x2];
7799 u8 log_cmdq_size[0x4];
7800 u8 log_cmdq_stride[0x4];
7801
7802 u8 command_doorbell_vector[0x20];
7803
7804 u8 reserved_at_e0[0xf00];
7805
7806 u8 initializing[0x1];
7807 u8 reserved_at_fe1[0x4];
7808 u8 nic_interface_supported[0x3];
7809 u8 reserved_at_fe8[0x18];
7810
7811 struct mlx5_ifc_health_buffer_bits health_buffer;
7812
7813 u8 no_dram_nic_offset[0x20];
7814
7815 u8 reserved_at_1220[0x6e40];
7816
7817 u8 reserved_at_8060[0x1f];
7818 u8 clear_int[0x1];
7819
7820 u8 health_syndrome[0x8];
7821 u8 health_counter[0x18];
7822
7823 u8 reserved_at_80a0[0x17fc0];
7824 };
7825
7826 struct mlx5_ifc_mtpps_reg_bits {
7827 u8 reserved_at_0[0xc];
7828 u8 cap_number_of_pps_pins[0x4];
7829 u8 reserved_at_10[0x4];
7830 u8 cap_max_num_of_pps_in_pins[0x4];
7831 u8 reserved_at_18[0x4];
7832 u8 cap_max_num_of_pps_out_pins[0x4];
7833
7834 u8 reserved_at_20[0x24];
7835 u8 cap_pin_3_mode[0x4];
7836 u8 reserved_at_48[0x4];
7837 u8 cap_pin_2_mode[0x4];
7838 u8 reserved_at_50[0x4];
7839 u8 cap_pin_1_mode[0x4];
7840 u8 reserved_at_58[0x4];
7841 u8 cap_pin_0_mode[0x4];
7842
7843 u8 reserved_at_60[0x4];
7844 u8 cap_pin_7_mode[0x4];
7845 u8 reserved_at_68[0x4];
7846 u8 cap_pin_6_mode[0x4];
7847 u8 reserved_at_70[0x4];
7848 u8 cap_pin_5_mode[0x4];
7849 u8 reserved_at_78[0x4];
7850 u8 cap_pin_4_mode[0x4];
7851
7852 u8 reserved_at_80[0x80];
7853
7854 u8 enable[0x1];
7855 u8 reserved_at_101[0xb];
7856 u8 pattern[0x4];
7857 u8 reserved_at_110[0x4];
7858 u8 pin_mode[0x4];
7859 u8 pin[0x8];
7860
7861 u8 reserved_at_120[0x20];
7862
7863 u8 time_stamp[0x40];
7864
7865 u8 out_pulse_duration[0x10];
7866 u8 out_periodic_adjustment[0x10];
7867
7868 u8 reserved_at_1a0[0x60];
7869 };
7870
7871 struct mlx5_ifc_mtppse_reg_bits {
7872 u8 reserved_at_0[0x18];
7873 u8 pin[0x8];
7874 u8 event_arm[0x1];
7875 u8 reserved_at_21[0x1b];
7876 u8 event_generation_mode[0x4];
7877 u8 reserved_at_40[0x40];
7878 };
7879
7880 union mlx5_ifc_ports_control_registers_document_bits {
7881 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7882 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7883 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7884 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7885 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7886 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7887 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7888 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7889 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7890 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7891 struct mlx5_ifc_paos_reg_bits paos_reg;
7892 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7893 struct mlx5_ifc_peir_reg_bits peir_reg;
7894 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7895 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7896 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7897 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7898 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7899 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7900 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7901 struct mlx5_ifc_plib_reg_bits plib_reg;
7902 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7903 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7904 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7905 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7906 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7907 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7908 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7909 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7910 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7911 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7912 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7913 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7914 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7915 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7916 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7917 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7918 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7919 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7920 struct mlx5_ifc_pude_reg_bits pude_reg;
7921 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7922 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7923 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7924 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
7925 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
7926 u8 reserved_at_0[0x60e0];
7927 };
7928
7929 union mlx5_ifc_debug_enhancements_document_bits {
7930 struct mlx5_ifc_health_buffer_bits health_buffer;
7931 u8 reserved_at_0[0x200];
7932 };
7933
7934 union mlx5_ifc_uplink_pci_interface_document_bits {
7935 struct mlx5_ifc_initial_seg_bits initial_seg;
7936 u8 reserved_at_0[0x20060];
7937 };
7938
7939 struct mlx5_ifc_set_flow_table_root_out_bits {
7940 u8 status[0x8];
7941 u8 reserved_at_8[0x18];
7942
7943 u8 syndrome[0x20];
7944
7945 u8 reserved_at_40[0x40];
7946 };
7947
7948 struct mlx5_ifc_set_flow_table_root_in_bits {
7949 u8 opcode[0x10];
7950 u8 reserved_at_10[0x10];
7951
7952 u8 reserved_at_20[0x10];
7953 u8 op_mod[0x10];
7954
7955 u8 other_vport[0x1];
7956 u8 reserved_at_41[0xf];
7957 u8 vport_number[0x10];
7958
7959 u8 reserved_at_60[0x20];
7960
7961 u8 table_type[0x8];
7962 u8 reserved_at_88[0x18];
7963
7964 u8 reserved_at_a0[0x8];
7965 u8 table_id[0x18];
7966
7967 u8 reserved_at_c0[0x140];
7968 };
7969
7970 enum {
7971 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
7972 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
7973 };
7974
7975 struct mlx5_ifc_modify_flow_table_out_bits {
7976 u8 status[0x8];
7977 u8 reserved_at_8[0x18];
7978
7979 u8 syndrome[0x20];
7980
7981 u8 reserved_at_40[0x40];
7982 };
7983
7984 struct mlx5_ifc_modify_flow_table_in_bits {
7985 u8 opcode[0x10];
7986 u8 reserved_at_10[0x10];
7987
7988 u8 reserved_at_20[0x10];
7989 u8 op_mod[0x10];
7990
7991 u8 other_vport[0x1];
7992 u8 reserved_at_41[0xf];
7993 u8 vport_number[0x10];
7994
7995 u8 reserved_at_60[0x10];
7996 u8 modify_field_select[0x10];
7997
7998 u8 table_type[0x8];
7999 u8 reserved_at_88[0x18];
8000
8001 u8 reserved_at_a0[0x8];
8002 u8 table_id[0x18];
8003
8004 u8 reserved_at_c0[0x4];
8005 u8 table_miss_mode[0x4];
8006 u8 reserved_at_c8[0x18];
8007
8008 u8 reserved_at_e0[0x8];
8009 u8 table_miss_id[0x18];
8010
8011 u8 reserved_at_100[0x8];
8012 u8 lag_master_next_table_id[0x18];
8013
8014 u8 reserved_at_120[0x80];
8015 };
8016
8017 struct mlx5_ifc_ets_tcn_config_reg_bits {
8018 u8 g[0x1];
8019 u8 b[0x1];
8020 u8 r[0x1];
8021 u8 reserved_at_3[0x9];
8022 u8 group[0x4];
8023 u8 reserved_at_10[0x9];
8024 u8 bw_allocation[0x7];
8025
8026 u8 reserved_at_20[0xc];
8027 u8 max_bw_units[0x4];
8028 u8 reserved_at_30[0x8];
8029 u8 max_bw_value[0x8];
8030 };
8031
8032 struct mlx5_ifc_ets_global_config_reg_bits {
8033 u8 reserved_at_0[0x2];
8034 u8 r[0x1];
8035 u8 reserved_at_3[0x1d];
8036
8037 u8 reserved_at_20[0xc];
8038 u8 max_bw_units[0x4];
8039 u8 reserved_at_30[0x8];
8040 u8 max_bw_value[0x8];
8041 };
8042
8043 struct mlx5_ifc_qetc_reg_bits {
8044 u8 reserved_at_0[0x8];
8045 u8 port_number[0x8];
8046 u8 reserved_at_10[0x30];
8047
8048 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8049 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8050 };
8051
8052 struct mlx5_ifc_qtct_reg_bits {
8053 u8 reserved_at_0[0x8];
8054 u8 port_number[0x8];
8055 u8 reserved_at_10[0xd];
8056 u8 prio[0x3];
8057
8058 u8 reserved_at_20[0x1d];
8059 u8 tclass[0x3];
8060 };
8061
8062 struct mlx5_ifc_mcia_reg_bits {
8063 u8 l[0x1];
8064 u8 reserved_at_1[0x7];
8065 u8 module[0x8];
8066 u8 reserved_at_10[0x8];
8067 u8 status[0x8];
8068
8069 u8 i2c_device_address[0x8];
8070 u8 page_number[0x8];
8071 u8 device_address[0x10];
8072
8073 u8 reserved_at_40[0x10];
8074 u8 size[0x10];
8075
8076 u8 reserved_at_60[0x20];
8077
8078 u8 dword_0[0x20];
8079 u8 dword_1[0x20];
8080 u8 dword_2[0x20];
8081 u8 dword_3[0x20];
8082 u8 dword_4[0x20];
8083 u8 dword_5[0x20];
8084 u8 dword_6[0x20];
8085 u8 dword_7[0x20];
8086 u8 dword_8[0x20];
8087 u8 dword_9[0x20];
8088 u8 dword_10[0x20];
8089 u8 dword_11[0x20];
8090 };
8091
8092 struct mlx5_ifc_dcbx_param_bits {
8093 u8 dcbx_cee_cap[0x1];
8094 u8 dcbx_ieee_cap[0x1];
8095 u8 dcbx_standby_cap[0x1];
8096 u8 reserved_at_0[0x5];
8097 u8 port_number[0x8];
8098 u8 reserved_at_10[0xa];
8099 u8 max_application_table_size[6];
8100 u8 reserved_at_20[0x15];
8101 u8 version_oper[0x3];
8102 u8 reserved_at_38[5];
8103 u8 version_admin[0x3];
8104 u8 willing_admin[0x1];
8105 u8 reserved_at_41[0x3];
8106 u8 pfc_cap_oper[0x4];
8107 u8 reserved_at_48[0x4];
8108 u8 pfc_cap_admin[0x4];
8109 u8 reserved_at_50[0x4];
8110 u8 num_of_tc_oper[0x4];
8111 u8 reserved_at_58[0x4];
8112 u8 num_of_tc_admin[0x4];
8113 u8 remote_willing[0x1];
8114 u8 reserved_at_61[3];
8115 u8 remote_pfc_cap[4];
8116 u8 reserved_at_68[0x14];
8117 u8 remote_num_of_tc[0x4];
8118 u8 reserved_at_80[0x18];
8119 u8 error[0x8];
8120 u8 reserved_at_a0[0x160];
8121 };
8122
8123 struct mlx5_ifc_lagc_bits {
8124 u8 reserved_at_0[0x1d];
8125 u8 lag_state[0x3];
8126
8127 u8 reserved_at_20[0x14];
8128 u8 tx_remap_affinity_2[0x4];
8129 u8 reserved_at_38[0x4];
8130 u8 tx_remap_affinity_1[0x4];
8131 };
8132
8133 struct mlx5_ifc_create_lag_out_bits {
8134 u8 status[0x8];
8135 u8 reserved_at_8[0x18];
8136
8137 u8 syndrome[0x20];
8138
8139 u8 reserved_at_40[0x40];
8140 };
8141
8142 struct mlx5_ifc_create_lag_in_bits {
8143 u8 opcode[0x10];
8144 u8 reserved_at_10[0x10];
8145
8146 u8 reserved_at_20[0x10];
8147 u8 op_mod[0x10];
8148
8149 struct mlx5_ifc_lagc_bits ctx;
8150 };
8151
8152 struct mlx5_ifc_modify_lag_out_bits {
8153 u8 status[0x8];
8154 u8 reserved_at_8[0x18];
8155
8156 u8 syndrome[0x20];
8157
8158 u8 reserved_at_40[0x40];
8159 };
8160
8161 struct mlx5_ifc_modify_lag_in_bits {
8162 u8 opcode[0x10];
8163 u8 reserved_at_10[0x10];
8164
8165 u8 reserved_at_20[0x10];
8166 u8 op_mod[0x10];
8167
8168 u8 reserved_at_40[0x20];
8169 u8 field_select[0x20];
8170
8171 struct mlx5_ifc_lagc_bits ctx;
8172 };
8173
8174 struct mlx5_ifc_query_lag_out_bits {
8175 u8 status[0x8];
8176 u8 reserved_at_8[0x18];
8177
8178 u8 syndrome[0x20];
8179
8180 u8 reserved_at_40[0x40];
8181
8182 struct mlx5_ifc_lagc_bits ctx;
8183 };
8184
8185 struct mlx5_ifc_query_lag_in_bits {
8186 u8 opcode[0x10];
8187 u8 reserved_at_10[0x10];
8188
8189 u8 reserved_at_20[0x10];
8190 u8 op_mod[0x10];
8191
8192 u8 reserved_at_40[0x40];
8193 };
8194
8195 struct mlx5_ifc_destroy_lag_out_bits {
8196 u8 status[0x8];
8197 u8 reserved_at_8[0x18];
8198
8199 u8 syndrome[0x20];
8200
8201 u8 reserved_at_40[0x40];
8202 };
8203
8204 struct mlx5_ifc_destroy_lag_in_bits {
8205 u8 opcode[0x10];
8206 u8 reserved_at_10[0x10];
8207
8208 u8 reserved_at_20[0x10];
8209 u8 op_mod[0x10];
8210
8211 u8 reserved_at_40[0x40];
8212 };
8213
8214 struct mlx5_ifc_create_vport_lag_out_bits {
8215 u8 status[0x8];
8216 u8 reserved_at_8[0x18];
8217
8218 u8 syndrome[0x20];
8219
8220 u8 reserved_at_40[0x40];
8221 };
8222
8223 struct mlx5_ifc_create_vport_lag_in_bits {
8224 u8 opcode[0x10];
8225 u8 reserved_at_10[0x10];
8226
8227 u8 reserved_at_20[0x10];
8228 u8 op_mod[0x10];
8229
8230 u8 reserved_at_40[0x40];
8231 };
8232
8233 struct mlx5_ifc_destroy_vport_lag_out_bits {
8234 u8 status[0x8];
8235 u8 reserved_at_8[0x18];
8236
8237 u8 syndrome[0x20];
8238
8239 u8 reserved_at_40[0x40];
8240 };
8241
8242 struct mlx5_ifc_destroy_vport_lag_in_bits {
8243 u8 opcode[0x10];
8244 u8 reserved_at_10[0x10];
8245
8246 u8 reserved_at_20[0x10];
8247 u8 op_mod[0x10];
8248
8249 u8 reserved_at_40[0x40];
8250 };
8251
8252 #endif /* MLX5_IFC_H */
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