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1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 };
64
65 enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 };
71
72 enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 };
76
77 enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
96 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
97 MLX5_CMD_OP_CREATE_EQ = 0x301,
98 MLX5_CMD_OP_DESTROY_EQ = 0x302,
99 MLX5_CMD_OP_QUERY_EQ = 0x303,
100 MLX5_CMD_OP_GEN_EQE = 0x304,
101 MLX5_CMD_OP_CREATE_CQ = 0x400,
102 MLX5_CMD_OP_DESTROY_CQ = 0x401,
103 MLX5_CMD_OP_QUERY_CQ = 0x402,
104 MLX5_CMD_OP_MODIFY_CQ = 0x403,
105 MLX5_CMD_OP_CREATE_QP = 0x500,
106 MLX5_CMD_OP_DESTROY_QP = 0x501,
107 MLX5_CMD_OP_RST2INIT_QP = 0x502,
108 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
109 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
110 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
111 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
112 MLX5_CMD_OP_2ERR_QP = 0x507,
113 MLX5_CMD_OP_2RST_QP = 0x50a,
114 MLX5_CMD_OP_QUERY_QP = 0x50b,
115 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
116 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
117 MLX5_CMD_OP_CREATE_PSV = 0x600,
118 MLX5_CMD_OP_DESTROY_PSV = 0x601,
119 MLX5_CMD_OP_CREATE_SRQ = 0x700,
120 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
121 MLX5_CMD_OP_QUERY_SRQ = 0x702,
122 MLX5_CMD_OP_ARM_RQ = 0x703,
123 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
124 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
125 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
126 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
127 MLX5_CMD_OP_CREATE_DCT = 0x710,
128 MLX5_CMD_OP_DESTROY_DCT = 0x711,
129 MLX5_CMD_OP_DRAIN_DCT = 0x712,
130 MLX5_CMD_OP_QUERY_DCT = 0x713,
131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
132 MLX5_CMD_OP_CREATE_XRQ = 0x717,
133 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
134 MLX5_CMD_OP_QUERY_XRQ = 0x719,
135 MLX5_CMD_OP_ARM_XRQ = 0x71a,
136 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
137 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
138 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
139 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
140 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
141 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
142 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
143 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
145 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
146 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
147 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
148 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
149 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
150 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
151 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
152 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
153 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
154 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
155 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
156 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
157 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
158 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
159 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
160 MLX5_CMD_OP_ALLOC_PD = 0x800,
161 MLX5_CMD_OP_DEALLOC_PD = 0x801,
162 MLX5_CMD_OP_ALLOC_UAR = 0x802,
163 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
164 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
165 MLX5_CMD_OP_ACCESS_REG = 0x805,
166 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
167 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
168 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
169 MLX5_CMD_OP_MAD_IFC = 0x50d,
170 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
171 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
172 MLX5_CMD_OP_NOP = 0x80d,
173 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
174 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
175 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
176 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
177 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
178 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
179 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
180 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
181 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
182 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
183 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
184 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
185 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
186 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
187 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
188 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
189 MLX5_CMD_OP_CREATE_LAG = 0x840,
190 MLX5_CMD_OP_MODIFY_LAG = 0x841,
191 MLX5_CMD_OP_QUERY_LAG = 0x842,
192 MLX5_CMD_OP_DESTROY_LAG = 0x843,
193 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
194 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
195 MLX5_CMD_OP_CREATE_TIR = 0x900,
196 MLX5_CMD_OP_MODIFY_TIR = 0x901,
197 MLX5_CMD_OP_DESTROY_TIR = 0x902,
198 MLX5_CMD_OP_QUERY_TIR = 0x903,
199 MLX5_CMD_OP_CREATE_SQ = 0x904,
200 MLX5_CMD_OP_MODIFY_SQ = 0x905,
201 MLX5_CMD_OP_DESTROY_SQ = 0x906,
202 MLX5_CMD_OP_QUERY_SQ = 0x907,
203 MLX5_CMD_OP_CREATE_RQ = 0x908,
204 MLX5_CMD_OP_MODIFY_RQ = 0x909,
205 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
206 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
207 MLX5_CMD_OP_QUERY_RQ = 0x90b,
208 MLX5_CMD_OP_CREATE_RMP = 0x90c,
209 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
210 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
211 MLX5_CMD_OP_QUERY_RMP = 0x90f,
212 MLX5_CMD_OP_CREATE_TIS = 0x912,
213 MLX5_CMD_OP_MODIFY_TIS = 0x913,
214 MLX5_CMD_OP_DESTROY_TIS = 0x914,
215 MLX5_CMD_OP_QUERY_TIS = 0x915,
216 MLX5_CMD_OP_CREATE_RQT = 0x916,
217 MLX5_CMD_OP_MODIFY_RQT = 0x917,
218 MLX5_CMD_OP_DESTROY_RQT = 0x918,
219 MLX5_CMD_OP_QUERY_RQT = 0x919,
220 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
221 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
222 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
223 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
224 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
225 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
226 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
227 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
228 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
229 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
230 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
231 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
232 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
233 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
234 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
235 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
236 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
237 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
238 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
239 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
240 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
241 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
242 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
243 MLX5_CMD_OP_MAX
244 };
245
246 struct mlx5_ifc_flow_table_fields_supported_bits {
247 u8 outer_dmac[0x1];
248 u8 outer_smac[0x1];
249 u8 outer_ether_type[0x1];
250 u8 outer_ip_version[0x1];
251 u8 outer_first_prio[0x1];
252 u8 outer_first_cfi[0x1];
253 u8 outer_first_vid[0x1];
254 u8 outer_ipv4_ttl[0x1];
255 u8 outer_second_prio[0x1];
256 u8 outer_second_cfi[0x1];
257 u8 outer_second_vid[0x1];
258 u8 reserved_at_b[0x1];
259 u8 outer_sip[0x1];
260 u8 outer_dip[0x1];
261 u8 outer_frag[0x1];
262 u8 outer_ip_protocol[0x1];
263 u8 outer_ip_ecn[0x1];
264 u8 outer_ip_dscp[0x1];
265 u8 outer_udp_sport[0x1];
266 u8 outer_udp_dport[0x1];
267 u8 outer_tcp_sport[0x1];
268 u8 outer_tcp_dport[0x1];
269 u8 outer_tcp_flags[0x1];
270 u8 outer_gre_protocol[0x1];
271 u8 outer_gre_key[0x1];
272 u8 outer_vxlan_vni[0x1];
273 u8 reserved_at_1a[0x5];
274 u8 source_eswitch_port[0x1];
275
276 u8 inner_dmac[0x1];
277 u8 inner_smac[0x1];
278 u8 inner_ether_type[0x1];
279 u8 inner_ip_version[0x1];
280 u8 inner_first_prio[0x1];
281 u8 inner_first_cfi[0x1];
282 u8 inner_first_vid[0x1];
283 u8 reserved_at_27[0x1];
284 u8 inner_second_prio[0x1];
285 u8 inner_second_cfi[0x1];
286 u8 inner_second_vid[0x1];
287 u8 reserved_at_2b[0x1];
288 u8 inner_sip[0x1];
289 u8 inner_dip[0x1];
290 u8 inner_frag[0x1];
291 u8 inner_ip_protocol[0x1];
292 u8 inner_ip_ecn[0x1];
293 u8 inner_ip_dscp[0x1];
294 u8 inner_udp_sport[0x1];
295 u8 inner_udp_dport[0x1];
296 u8 inner_tcp_sport[0x1];
297 u8 inner_tcp_dport[0x1];
298 u8 inner_tcp_flags[0x1];
299 u8 reserved_at_37[0x9];
300 u8 reserved_at_40[0x17];
301 u8 outer_esp_spi[0x1];
302 u8 reserved_at_58[0x2];
303 u8 bth_dst_qp[0x1];
304
305 u8 reserved_at_5b[0x25];
306 };
307
308 struct mlx5_ifc_flow_table_prop_layout_bits {
309 u8 ft_support[0x1];
310 u8 reserved_at_1[0x1];
311 u8 flow_counter[0x1];
312 u8 flow_modify_en[0x1];
313 u8 modify_root[0x1];
314 u8 identified_miss_table_mode[0x1];
315 u8 flow_table_modify[0x1];
316 u8 encap[0x1];
317 u8 decap[0x1];
318 u8 reserved_at_9[0x17];
319
320 u8 reserved_at_20[0x2];
321 u8 log_max_ft_size[0x6];
322 u8 log_max_modify_header_context[0x8];
323 u8 max_modify_header_actions[0x8];
324 u8 max_ft_level[0x8];
325
326 u8 reserved_at_40[0x20];
327
328 u8 reserved_at_60[0x18];
329 u8 log_max_ft_num[0x8];
330
331 u8 reserved_at_80[0x18];
332 u8 log_max_destination[0x8];
333
334 u8 log_max_flow_counter[0x8];
335 u8 reserved_at_a8[0x10];
336 u8 log_max_flow[0x8];
337
338 u8 reserved_at_c0[0x40];
339
340 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
341
342 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
343 };
344
345 struct mlx5_ifc_odp_per_transport_service_cap_bits {
346 u8 send[0x1];
347 u8 receive[0x1];
348 u8 write[0x1];
349 u8 read[0x1];
350 u8 atomic[0x1];
351 u8 srq_receive[0x1];
352 u8 reserved_at_6[0x1a];
353 };
354
355 struct mlx5_ifc_ipv4_layout_bits {
356 u8 reserved_at_0[0x60];
357
358 u8 ipv4[0x20];
359 };
360
361 struct mlx5_ifc_ipv6_layout_bits {
362 u8 ipv6[16][0x8];
363 };
364
365 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
366 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
367 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
368 u8 reserved_at_0[0x80];
369 };
370
371 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
372 u8 smac_47_16[0x20];
373
374 u8 smac_15_0[0x10];
375 u8 ethertype[0x10];
376
377 u8 dmac_47_16[0x20];
378
379 u8 dmac_15_0[0x10];
380 u8 first_prio[0x3];
381 u8 first_cfi[0x1];
382 u8 first_vid[0xc];
383
384 u8 ip_protocol[0x8];
385 u8 ip_dscp[0x6];
386 u8 ip_ecn[0x2];
387 u8 cvlan_tag[0x1];
388 u8 svlan_tag[0x1];
389 u8 frag[0x1];
390 u8 ip_version[0x4];
391 u8 tcp_flags[0x9];
392
393 u8 tcp_sport[0x10];
394 u8 tcp_dport[0x10];
395
396 u8 reserved_at_c0[0x18];
397 u8 ttl_hoplimit[0x8];
398
399 u8 udp_sport[0x10];
400 u8 udp_dport[0x10];
401
402 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
403
404 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
405 };
406
407 struct mlx5_ifc_fte_match_set_misc_bits {
408 u8 reserved_at_0[0x8];
409 u8 source_sqn[0x18];
410
411 u8 reserved_at_20[0x10];
412 u8 source_port[0x10];
413
414 u8 outer_second_prio[0x3];
415 u8 outer_second_cfi[0x1];
416 u8 outer_second_vid[0xc];
417 u8 inner_second_prio[0x3];
418 u8 inner_second_cfi[0x1];
419 u8 inner_second_vid[0xc];
420
421 u8 outer_second_cvlan_tag[0x1];
422 u8 inner_second_cvlan_tag[0x1];
423 u8 outer_second_svlan_tag[0x1];
424 u8 inner_second_svlan_tag[0x1];
425 u8 reserved_at_64[0xc];
426 u8 gre_protocol[0x10];
427
428 u8 gre_key_h[0x18];
429 u8 gre_key_l[0x8];
430
431 u8 vxlan_vni[0x18];
432 u8 reserved_at_b8[0x8];
433
434 u8 reserved_at_c0[0x20];
435
436 u8 reserved_at_e0[0xc];
437 u8 outer_ipv6_flow_label[0x14];
438
439 u8 reserved_at_100[0xc];
440 u8 inner_ipv6_flow_label[0x14];
441
442 u8 reserved_at_120[0x28];
443 u8 bth_dst_qp[0x18];
444 u8 reserved_at_160[0x20];
445 u8 outer_esp_spi[0x20];
446 u8 reserved_at_1a0[0x60];
447 };
448
449 struct mlx5_ifc_cmd_pas_bits {
450 u8 pa_h[0x20];
451
452 u8 pa_l[0x14];
453 u8 reserved_at_34[0xc];
454 };
455
456 struct mlx5_ifc_uint64_bits {
457 u8 hi[0x20];
458
459 u8 lo[0x20];
460 };
461
462 enum {
463 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
464 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
465 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
466 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
467 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
468 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
469 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
470 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
471 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
472 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
473 };
474
475 struct mlx5_ifc_ads_bits {
476 u8 fl[0x1];
477 u8 free_ar[0x1];
478 u8 reserved_at_2[0xe];
479 u8 pkey_index[0x10];
480
481 u8 reserved_at_20[0x8];
482 u8 grh[0x1];
483 u8 mlid[0x7];
484 u8 rlid[0x10];
485
486 u8 ack_timeout[0x5];
487 u8 reserved_at_45[0x3];
488 u8 src_addr_index[0x8];
489 u8 reserved_at_50[0x4];
490 u8 stat_rate[0x4];
491 u8 hop_limit[0x8];
492
493 u8 reserved_at_60[0x4];
494 u8 tclass[0x8];
495 u8 flow_label[0x14];
496
497 u8 rgid_rip[16][0x8];
498
499 u8 reserved_at_100[0x4];
500 u8 f_dscp[0x1];
501 u8 f_ecn[0x1];
502 u8 reserved_at_106[0x1];
503 u8 f_eth_prio[0x1];
504 u8 ecn[0x2];
505 u8 dscp[0x6];
506 u8 udp_sport[0x10];
507
508 u8 dei_cfi[0x1];
509 u8 eth_prio[0x3];
510 u8 sl[0x4];
511 u8 vhca_port_num[0x8];
512 u8 rmac_47_32[0x10];
513
514 u8 rmac_31_0[0x20];
515 };
516
517 struct mlx5_ifc_flow_table_nic_cap_bits {
518 u8 nic_rx_multi_path_tirs[0x1];
519 u8 nic_rx_multi_path_tirs_fts[0x1];
520 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
521 u8 reserved_at_3[0x1fd];
522
523 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
524
525 u8 reserved_at_400[0x200];
526
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
528
529 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
530
531 u8 reserved_at_a00[0x200];
532
533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
534
535 u8 reserved_at_e00[0x7200];
536 };
537
538 struct mlx5_ifc_flow_table_eswitch_cap_bits {
539 u8 reserved_at_0[0x200];
540
541 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
542
543 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
544
545 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
546
547 u8 reserved_at_800[0x7800];
548 };
549
550 struct mlx5_ifc_e_switch_cap_bits {
551 u8 vport_svlan_strip[0x1];
552 u8 vport_cvlan_strip[0x1];
553 u8 vport_svlan_insert[0x1];
554 u8 vport_cvlan_insert_if_not_exist[0x1];
555 u8 vport_cvlan_insert_overwrite[0x1];
556 u8 reserved_at_5[0x19];
557 u8 nic_vport_node_guid_modify[0x1];
558 u8 nic_vport_port_guid_modify[0x1];
559
560 u8 vxlan_encap_decap[0x1];
561 u8 nvgre_encap_decap[0x1];
562 u8 reserved_at_22[0x9];
563 u8 log_max_encap_headers[0x5];
564 u8 reserved_2b[0x6];
565 u8 max_encap_header_size[0xa];
566
567 u8 reserved_40[0x7c0];
568
569 };
570
571 struct mlx5_ifc_qos_cap_bits {
572 u8 packet_pacing[0x1];
573 u8 esw_scheduling[0x1];
574 u8 esw_bw_share[0x1];
575 u8 esw_rate_limit[0x1];
576 u8 reserved_at_4[0x1];
577 u8 packet_pacing_burst_bound[0x1];
578 u8 packet_pacing_typical_size[0x1];
579 u8 reserved_at_7[0x19];
580
581 u8 reserved_at_20[0x20];
582
583 u8 packet_pacing_max_rate[0x20];
584
585 u8 packet_pacing_min_rate[0x20];
586
587 u8 reserved_at_80[0x10];
588 u8 packet_pacing_rate_table_size[0x10];
589
590 u8 esw_element_type[0x10];
591 u8 esw_tsar_type[0x10];
592
593 u8 reserved_at_c0[0x10];
594 u8 max_qos_para_vport[0x10];
595
596 u8 max_tsar_bw_share[0x20];
597
598 u8 reserved_at_100[0x700];
599 };
600
601 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
602 u8 csum_cap[0x1];
603 u8 vlan_cap[0x1];
604 u8 lro_cap[0x1];
605 u8 lro_psh_flag[0x1];
606 u8 lro_time_stamp[0x1];
607 u8 reserved_at_5[0x2];
608 u8 wqe_vlan_insert[0x1];
609 u8 self_lb_en_modifiable[0x1];
610 u8 reserved_at_9[0x2];
611 u8 max_lso_cap[0x5];
612 u8 multi_pkt_send_wqe[0x2];
613 u8 wqe_inline_mode[0x2];
614 u8 rss_ind_tbl_cap[0x4];
615 u8 reg_umr_sq[0x1];
616 u8 scatter_fcs[0x1];
617 u8 enhanced_multi_pkt_send_wqe[0x1];
618 u8 tunnel_lso_const_out_ip_id[0x1];
619 u8 reserved_at_1c[0x2];
620 u8 tunnel_stateless_gre[0x1];
621 u8 tunnel_stateless_vxlan[0x1];
622
623 u8 swp[0x1];
624 u8 swp_csum[0x1];
625 u8 swp_lso[0x1];
626 u8 reserved_at_23[0x1b];
627 u8 max_geneve_opt_len[0x1];
628 u8 tunnel_stateless_geneve_rx[0x1];
629
630 u8 reserved_at_40[0x10];
631 u8 lro_min_mss_size[0x10];
632
633 u8 reserved_at_60[0x120];
634
635 u8 lro_timer_supported_periods[4][0x20];
636
637 u8 reserved_at_200[0x600];
638 };
639
640 struct mlx5_ifc_roce_cap_bits {
641 u8 roce_apm[0x1];
642 u8 reserved_at_1[0x1f];
643
644 u8 reserved_at_20[0x60];
645
646 u8 reserved_at_80[0xc];
647 u8 l3_type[0x4];
648 u8 reserved_at_90[0x8];
649 u8 roce_version[0x8];
650
651 u8 reserved_at_a0[0x10];
652 u8 r_roce_dest_udp_port[0x10];
653
654 u8 r_roce_max_src_udp_port[0x10];
655 u8 r_roce_min_src_udp_port[0x10];
656
657 u8 reserved_at_e0[0x10];
658 u8 roce_address_table_size[0x10];
659
660 u8 reserved_at_100[0x700];
661 };
662
663 struct mlx5_ifc_device_mem_cap_bits {
664 u8 memic[0x1];
665 u8 reserved_at_1[0x1f];
666
667 u8 reserved_at_20[0xb];
668 u8 log_min_memic_alloc_size[0x5];
669 u8 reserved_at_30[0x8];
670 u8 log_max_memic_addr_alignment[0x8];
671
672 u8 memic_bar_start_addr[0x40];
673
674 u8 memic_bar_size[0x20];
675
676 u8 max_memic_size[0x20];
677
678 u8 reserved_at_c0[0x740];
679 };
680
681 enum {
682 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
683 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
684 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
685 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
686 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
687 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
688 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
689 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
690 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
691 };
692
693 enum {
694 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
695 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
696 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
701 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
702 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
703 };
704
705 struct mlx5_ifc_atomic_caps_bits {
706 u8 reserved_at_0[0x40];
707
708 u8 atomic_req_8B_endianness_mode[0x2];
709 u8 reserved_at_42[0x4];
710 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
711
712 u8 reserved_at_47[0x19];
713
714 u8 reserved_at_60[0x20];
715
716 u8 reserved_at_80[0x10];
717 u8 atomic_operations[0x10];
718
719 u8 reserved_at_a0[0x10];
720 u8 atomic_size_qp[0x10];
721
722 u8 reserved_at_c0[0x10];
723 u8 atomic_size_dc[0x10];
724
725 u8 reserved_at_e0[0x720];
726 };
727
728 struct mlx5_ifc_odp_cap_bits {
729 u8 reserved_at_0[0x40];
730
731 u8 sig[0x1];
732 u8 reserved_at_41[0x1f];
733
734 u8 reserved_at_60[0x20];
735
736 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
737
738 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
739
740 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
741
742 u8 reserved_at_e0[0x720];
743 };
744
745 struct mlx5_ifc_calc_op {
746 u8 reserved_at_0[0x10];
747 u8 reserved_at_10[0x9];
748 u8 op_swap_endianness[0x1];
749 u8 op_min[0x1];
750 u8 op_xor[0x1];
751 u8 op_or[0x1];
752 u8 op_and[0x1];
753 u8 op_max[0x1];
754 u8 op_add[0x1];
755 };
756
757 struct mlx5_ifc_vector_calc_cap_bits {
758 u8 calc_matrix[0x1];
759 u8 reserved_at_1[0x1f];
760 u8 reserved_at_20[0x8];
761 u8 max_vec_count[0x8];
762 u8 reserved_at_30[0xd];
763 u8 max_chunk_size[0x3];
764 struct mlx5_ifc_calc_op calc0;
765 struct mlx5_ifc_calc_op calc1;
766 struct mlx5_ifc_calc_op calc2;
767 struct mlx5_ifc_calc_op calc3;
768
769 u8 reserved_at_e0[0x720];
770 };
771
772 enum {
773 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
774 MLX5_WQ_TYPE_CYCLIC = 0x1,
775 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
776 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
777 };
778
779 enum {
780 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
781 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
782 };
783
784 enum {
785 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
786 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
787 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
788 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
789 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
790 };
791
792 enum {
793 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
794 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
795 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
796 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
797 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
798 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
799 };
800
801 enum {
802 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
803 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
804 };
805
806 enum {
807 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
808 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
809 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
810 };
811
812 enum {
813 MLX5_CAP_PORT_TYPE_IB = 0x0,
814 MLX5_CAP_PORT_TYPE_ETH = 0x1,
815 };
816
817 enum {
818 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
819 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
820 MLX5_CAP_UMR_FENCE_NONE = 0x2,
821 };
822
823 struct mlx5_ifc_cmd_hca_cap_bits {
824 u8 reserved_at_0[0x30];
825 u8 vhca_id[0x10];
826
827 u8 reserved_at_40[0x40];
828
829 u8 log_max_srq_sz[0x8];
830 u8 log_max_qp_sz[0x8];
831 u8 reserved_at_90[0xb];
832 u8 log_max_qp[0x5];
833
834 u8 reserved_at_a0[0xb];
835 u8 log_max_srq[0x5];
836 u8 reserved_at_b0[0x10];
837
838 u8 reserved_at_c0[0x8];
839 u8 log_max_cq_sz[0x8];
840 u8 reserved_at_d0[0xb];
841 u8 log_max_cq[0x5];
842
843 u8 log_max_eq_sz[0x8];
844 u8 reserved_at_e8[0x2];
845 u8 log_max_mkey[0x6];
846 u8 reserved_at_f0[0xc];
847 u8 log_max_eq[0x4];
848
849 u8 max_indirection[0x8];
850 u8 fixed_buffer_size[0x1];
851 u8 log_max_mrw_sz[0x7];
852 u8 force_teardown[0x1];
853 u8 reserved_at_111[0x1];
854 u8 log_max_bsf_list_size[0x6];
855 u8 umr_extended_translation_offset[0x1];
856 u8 null_mkey[0x1];
857 u8 log_max_klm_list_size[0x6];
858
859 u8 reserved_at_120[0xa];
860 u8 log_max_ra_req_dc[0x6];
861 u8 reserved_at_130[0xa];
862 u8 log_max_ra_res_dc[0x6];
863
864 u8 reserved_at_140[0xa];
865 u8 log_max_ra_req_qp[0x6];
866 u8 reserved_at_150[0xa];
867 u8 log_max_ra_res_qp[0x6];
868
869 u8 end_pad[0x1];
870 u8 cc_query_allowed[0x1];
871 u8 cc_modify_allowed[0x1];
872 u8 start_pad[0x1];
873 u8 cache_line_128byte[0x1];
874 u8 reserved_at_165[0xa];
875 u8 qcam_reg[0x1];
876 u8 gid_table_size[0x10];
877
878 u8 out_of_seq_cnt[0x1];
879 u8 vport_counters[0x1];
880 u8 retransmission_q_counters[0x1];
881 u8 reserved_at_183[0x1];
882 u8 modify_rq_counter_set_id[0x1];
883 u8 rq_delay_drop[0x1];
884 u8 max_qp_cnt[0xa];
885 u8 pkey_table_size[0x10];
886
887 u8 vport_group_manager[0x1];
888 u8 vhca_group_manager[0x1];
889 u8 ib_virt[0x1];
890 u8 eth_virt[0x1];
891 u8 reserved_at_1a4[0x1];
892 u8 ets[0x1];
893 u8 nic_flow_table[0x1];
894 u8 eswitch_flow_table[0x1];
895 u8 device_memory[0x1];
896 u8 mcam_reg[0x1];
897 u8 pcam_reg[0x1];
898 u8 local_ca_ack_delay[0x5];
899 u8 port_module_event[0x1];
900 u8 enhanced_error_q_counters[0x1];
901 u8 ports_check[0x1];
902 u8 reserved_at_1b3[0x1];
903 u8 disable_link_up[0x1];
904 u8 beacon_led[0x1];
905 u8 port_type[0x2];
906 u8 num_ports[0x8];
907
908 u8 reserved_at_1c0[0x1];
909 u8 pps[0x1];
910 u8 pps_modify[0x1];
911 u8 log_max_msg[0x5];
912 u8 reserved_at_1c8[0x4];
913 u8 max_tc[0x4];
914 u8 reserved_at_1d0[0x1];
915 u8 dcbx[0x1];
916 u8 general_notification_event[0x1];
917 u8 reserved_at_1d3[0x2];
918 u8 fpga[0x1];
919 u8 rol_s[0x1];
920 u8 rol_g[0x1];
921 u8 reserved_at_1d8[0x1];
922 u8 wol_s[0x1];
923 u8 wol_g[0x1];
924 u8 wol_a[0x1];
925 u8 wol_b[0x1];
926 u8 wol_m[0x1];
927 u8 wol_u[0x1];
928 u8 wol_p[0x1];
929
930 u8 stat_rate_support[0x10];
931 u8 reserved_at_1f0[0xc];
932 u8 cqe_version[0x4];
933
934 u8 compact_address_vector[0x1];
935 u8 striding_rq[0x1];
936 u8 reserved_at_202[0x1];
937 u8 ipoib_enhanced_offloads[0x1];
938 u8 ipoib_basic_offloads[0x1];
939 u8 reserved_at_205[0x1];
940 u8 repeated_block_disabled[0x1];
941 u8 umr_modify_entity_size_disabled[0x1];
942 u8 umr_modify_atomic_disabled[0x1];
943 u8 umr_indirect_mkey_disabled[0x1];
944 u8 umr_fence[0x2];
945 u8 reserved_at_20c[0x3];
946 u8 drain_sigerr[0x1];
947 u8 cmdif_checksum[0x2];
948 u8 sigerr_cqe[0x1];
949 u8 reserved_at_213[0x1];
950 u8 wq_signature[0x1];
951 u8 sctr_data_cqe[0x1];
952 u8 reserved_at_216[0x1];
953 u8 sho[0x1];
954 u8 tph[0x1];
955 u8 rf[0x1];
956 u8 dct[0x1];
957 u8 qos[0x1];
958 u8 eth_net_offloads[0x1];
959 u8 roce[0x1];
960 u8 atomic[0x1];
961 u8 reserved_at_21f[0x1];
962
963 u8 cq_oi[0x1];
964 u8 cq_resize[0x1];
965 u8 cq_moderation[0x1];
966 u8 reserved_at_223[0x3];
967 u8 cq_eq_remap[0x1];
968 u8 pg[0x1];
969 u8 block_lb_mc[0x1];
970 u8 reserved_at_229[0x1];
971 u8 scqe_break_moderation[0x1];
972 u8 cq_period_start_from_cqe[0x1];
973 u8 cd[0x1];
974 u8 reserved_at_22d[0x1];
975 u8 apm[0x1];
976 u8 vector_calc[0x1];
977 u8 umr_ptr_rlky[0x1];
978 u8 imaicl[0x1];
979 u8 reserved_at_232[0x4];
980 u8 qkv[0x1];
981 u8 pkv[0x1];
982 u8 set_deth_sqpn[0x1];
983 u8 reserved_at_239[0x3];
984 u8 xrc[0x1];
985 u8 ud[0x1];
986 u8 uc[0x1];
987 u8 rc[0x1];
988
989 u8 uar_4k[0x1];
990 u8 reserved_at_241[0x9];
991 u8 uar_sz[0x6];
992 u8 reserved_at_250[0x8];
993 u8 log_pg_sz[0x8];
994
995 u8 bf[0x1];
996 u8 driver_version[0x1];
997 u8 pad_tx_eth_packet[0x1];
998 u8 reserved_at_263[0x8];
999 u8 log_bf_reg_size[0x5];
1000
1001 u8 reserved_at_270[0xb];
1002 u8 lag_master[0x1];
1003 u8 num_lag_ports[0x4];
1004
1005 u8 reserved_at_280[0x10];
1006 u8 max_wqe_sz_sq[0x10];
1007
1008 u8 reserved_at_2a0[0x10];
1009 u8 max_wqe_sz_rq[0x10];
1010
1011 u8 max_flow_counter_31_16[0x10];
1012 u8 max_wqe_sz_sq_dc[0x10];
1013
1014 u8 reserved_at_2e0[0x7];
1015 u8 max_qp_mcg[0x19];
1016
1017 u8 reserved_at_300[0x18];
1018 u8 log_max_mcg[0x8];
1019
1020 u8 reserved_at_320[0x3];
1021 u8 log_max_transport_domain[0x5];
1022 u8 reserved_at_328[0x3];
1023 u8 log_max_pd[0x5];
1024 u8 reserved_at_330[0xb];
1025 u8 log_max_xrcd[0x5];
1026
1027 u8 reserved_at_340[0x8];
1028 u8 log_max_flow_counter_bulk[0x8];
1029 u8 max_flow_counter_15_0[0x10];
1030
1031
1032 u8 reserved_at_360[0x3];
1033 u8 log_max_rq[0x5];
1034 u8 reserved_at_368[0x3];
1035 u8 log_max_sq[0x5];
1036 u8 reserved_at_370[0x3];
1037 u8 log_max_tir[0x5];
1038 u8 reserved_at_378[0x3];
1039 u8 log_max_tis[0x5];
1040
1041 u8 basic_cyclic_rcv_wqe[0x1];
1042 u8 reserved_at_381[0x2];
1043 u8 log_max_rmp[0x5];
1044 u8 reserved_at_388[0x3];
1045 u8 log_max_rqt[0x5];
1046 u8 reserved_at_390[0x3];
1047 u8 log_max_rqt_size[0x5];
1048 u8 reserved_at_398[0x3];
1049 u8 log_max_tis_per_sq[0x5];
1050
1051 u8 reserved_at_3a0[0x3];
1052 u8 log_max_stride_sz_rq[0x5];
1053 u8 reserved_at_3a8[0x3];
1054 u8 log_min_stride_sz_rq[0x5];
1055 u8 reserved_at_3b0[0x3];
1056 u8 log_max_stride_sz_sq[0x5];
1057 u8 reserved_at_3b8[0x3];
1058 u8 log_min_stride_sz_sq[0x5];
1059
1060 u8 hairpin[0x1];
1061 u8 reserved_at_3c1[0x2];
1062 u8 log_max_hairpin_queues[0x5];
1063 u8 reserved_at_3c8[0x3];
1064 u8 log_max_hairpin_wq_data_sz[0x5];
1065 u8 reserved_at_3d0[0x3];
1066 u8 log_max_hairpin_num_packets[0x5];
1067 u8 reserved_at_3d8[0x3];
1068 u8 log_max_wq_sz[0x5];
1069
1070 u8 nic_vport_change_event[0x1];
1071 u8 disable_local_lb_uc[0x1];
1072 u8 disable_local_lb_mc[0x1];
1073 u8 log_min_hairpin_wq_data_sz[0x5];
1074 u8 reserved_at_3e8[0x3];
1075 u8 log_max_vlan_list[0x5];
1076 u8 reserved_at_3f0[0x3];
1077 u8 log_max_current_mc_list[0x5];
1078 u8 reserved_at_3f8[0x3];
1079 u8 log_max_current_uc_list[0x5];
1080
1081 u8 reserved_at_400[0x80];
1082
1083 u8 reserved_at_480[0x3];
1084 u8 log_max_l2_table[0x5];
1085 u8 reserved_at_488[0x8];
1086 u8 log_uar_page_sz[0x10];
1087
1088 u8 reserved_at_4a0[0x20];
1089 u8 device_frequency_mhz[0x20];
1090 u8 device_frequency_khz[0x20];
1091
1092 u8 reserved_at_500[0x20];
1093 u8 num_of_uars_per_page[0x20];
1094 u8 reserved_at_540[0x40];
1095
1096 u8 reserved_at_580[0x3d];
1097 u8 cqe_128_always[0x1];
1098 u8 cqe_compression_128[0x1];
1099 u8 cqe_compression[0x1];
1100
1101 u8 cqe_compression_timeout[0x10];
1102 u8 cqe_compression_max_num[0x10];
1103
1104 u8 reserved_at_5e0[0x10];
1105 u8 tag_matching[0x1];
1106 u8 rndv_offload_rc[0x1];
1107 u8 rndv_offload_dc[0x1];
1108 u8 log_tag_matching_list_sz[0x5];
1109 u8 reserved_at_5f8[0x3];
1110 u8 log_max_xrq[0x5];
1111
1112 u8 affiliate_nic_vport_criteria[0x8];
1113 u8 native_port_num[0x8];
1114 u8 num_vhca_ports[0x8];
1115 u8 reserved_at_618[0x6];
1116 u8 sw_owner_id[0x1];
1117 u8 reserved_at_61f[0x1e1];
1118 };
1119
1120 enum mlx5_flow_destination_type {
1121 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1122 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1123 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1124
1125 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1126 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1127 };
1128
1129 struct mlx5_ifc_dest_format_struct_bits {
1130 u8 destination_type[0x8];
1131 u8 destination_id[0x18];
1132
1133 u8 reserved_at_20[0x20];
1134 };
1135
1136 struct mlx5_ifc_flow_counter_list_bits {
1137 u8 flow_counter_id[0x20];
1138
1139 u8 reserved_at_20[0x20];
1140 };
1141
1142 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1143 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1144 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1145 u8 reserved_at_0[0x40];
1146 };
1147
1148 struct mlx5_ifc_fte_match_param_bits {
1149 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1150
1151 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1152
1153 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1154
1155 u8 reserved_at_600[0xa00];
1156 };
1157
1158 enum {
1159 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1160 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1161 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1162 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1163 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1164 };
1165
1166 struct mlx5_ifc_rx_hash_field_select_bits {
1167 u8 l3_prot_type[0x1];
1168 u8 l4_prot_type[0x1];
1169 u8 selected_fields[0x1e];
1170 };
1171
1172 enum {
1173 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1174 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1175 };
1176
1177 enum {
1178 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1179 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1180 };
1181
1182 struct mlx5_ifc_wq_bits {
1183 u8 wq_type[0x4];
1184 u8 wq_signature[0x1];
1185 u8 end_padding_mode[0x2];
1186 u8 cd_slave[0x1];
1187 u8 reserved_at_8[0x18];
1188
1189 u8 hds_skip_first_sge[0x1];
1190 u8 log2_hds_buf_size[0x3];
1191 u8 reserved_at_24[0x7];
1192 u8 page_offset[0x5];
1193 u8 lwm[0x10];
1194
1195 u8 reserved_at_40[0x8];
1196 u8 pd[0x18];
1197
1198 u8 reserved_at_60[0x8];
1199 u8 uar_page[0x18];
1200
1201 u8 dbr_addr[0x40];
1202
1203 u8 hw_counter[0x20];
1204
1205 u8 sw_counter[0x20];
1206
1207 u8 reserved_at_100[0xc];
1208 u8 log_wq_stride[0x4];
1209 u8 reserved_at_110[0x3];
1210 u8 log_wq_pg_sz[0x5];
1211 u8 reserved_at_118[0x3];
1212 u8 log_wq_sz[0x5];
1213
1214 u8 reserved_at_120[0x3];
1215 u8 log_hairpin_num_packets[0x5];
1216 u8 reserved_at_128[0x3];
1217 u8 log_hairpin_data_sz[0x5];
1218 u8 reserved_at_130[0x5];
1219
1220 u8 log_wqe_num_of_strides[0x3];
1221 u8 two_byte_shift_en[0x1];
1222 u8 reserved_at_139[0x4];
1223 u8 log_wqe_stride_size[0x3];
1224
1225 u8 reserved_at_140[0x4c0];
1226
1227 struct mlx5_ifc_cmd_pas_bits pas[0];
1228 };
1229
1230 struct mlx5_ifc_rq_num_bits {
1231 u8 reserved_at_0[0x8];
1232 u8 rq_num[0x18];
1233 };
1234
1235 struct mlx5_ifc_mac_address_layout_bits {
1236 u8 reserved_at_0[0x10];
1237 u8 mac_addr_47_32[0x10];
1238
1239 u8 mac_addr_31_0[0x20];
1240 };
1241
1242 struct mlx5_ifc_vlan_layout_bits {
1243 u8 reserved_at_0[0x14];
1244 u8 vlan[0x0c];
1245
1246 u8 reserved_at_20[0x20];
1247 };
1248
1249 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1250 u8 reserved_at_0[0xa0];
1251
1252 u8 min_time_between_cnps[0x20];
1253
1254 u8 reserved_at_c0[0x12];
1255 u8 cnp_dscp[0x6];
1256 u8 reserved_at_d8[0x4];
1257 u8 cnp_prio_mode[0x1];
1258 u8 cnp_802p_prio[0x3];
1259
1260 u8 reserved_at_e0[0x720];
1261 };
1262
1263 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1264 u8 reserved_at_0[0x60];
1265
1266 u8 reserved_at_60[0x4];
1267 u8 clamp_tgt_rate[0x1];
1268 u8 reserved_at_65[0x3];
1269 u8 clamp_tgt_rate_after_time_inc[0x1];
1270 u8 reserved_at_69[0x17];
1271
1272 u8 reserved_at_80[0x20];
1273
1274 u8 rpg_time_reset[0x20];
1275
1276 u8 rpg_byte_reset[0x20];
1277
1278 u8 rpg_threshold[0x20];
1279
1280 u8 rpg_max_rate[0x20];
1281
1282 u8 rpg_ai_rate[0x20];
1283
1284 u8 rpg_hai_rate[0x20];
1285
1286 u8 rpg_gd[0x20];
1287
1288 u8 rpg_min_dec_fac[0x20];
1289
1290 u8 rpg_min_rate[0x20];
1291
1292 u8 reserved_at_1c0[0xe0];
1293
1294 u8 rate_to_set_on_first_cnp[0x20];
1295
1296 u8 dce_tcp_g[0x20];
1297
1298 u8 dce_tcp_rtt[0x20];
1299
1300 u8 rate_reduce_monitor_period[0x20];
1301
1302 u8 reserved_at_320[0x20];
1303
1304 u8 initial_alpha_value[0x20];
1305
1306 u8 reserved_at_360[0x4a0];
1307 };
1308
1309 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1310 u8 reserved_at_0[0x80];
1311
1312 u8 rppp_max_rps[0x20];
1313
1314 u8 rpg_time_reset[0x20];
1315
1316 u8 rpg_byte_reset[0x20];
1317
1318 u8 rpg_threshold[0x20];
1319
1320 u8 rpg_max_rate[0x20];
1321
1322 u8 rpg_ai_rate[0x20];
1323
1324 u8 rpg_hai_rate[0x20];
1325
1326 u8 rpg_gd[0x20];
1327
1328 u8 rpg_min_dec_fac[0x20];
1329
1330 u8 rpg_min_rate[0x20];
1331
1332 u8 reserved_at_1c0[0x640];
1333 };
1334
1335 enum {
1336 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1337 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1338 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1339 };
1340
1341 struct mlx5_ifc_resize_field_select_bits {
1342 u8 resize_field_select[0x20];
1343 };
1344
1345 enum {
1346 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1347 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1348 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1349 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1350 };
1351
1352 struct mlx5_ifc_modify_field_select_bits {
1353 u8 modify_field_select[0x20];
1354 };
1355
1356 struct mlx5_ifc_field_select_r_roce_np_bits {
1357 u8 field_select_r_roce_np[0x20];
1358 };
1359
1360 struct mlx5_ifc_field_select_r_roce_rp_bits {
1361 u8 field_select_r_roce_rp[0x20];
1362 };
1363
1364 enum {
1365 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1366 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1367 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1368 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1369 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1370 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1371 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1372 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1373 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1374 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1375 };
1376
1377 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1378 u8 field_select_8021qaurp[0x20];
1379 };
1380
1381 struct mlx5_ifc_phys_layer_cntrs_bits {
1382 u8 time_since_last_clear_high[0x20];
1383
1384 u8 time_since_last_clear_low[0x20];
1385
1386 u8 symbol_errors_high[0x20];
1387
1388 u8 symbol_errors_low[0x20];
1389
1390 u8 sync_headers_errors_high[0x20];
1391
1392 u8 sync_headers_errors_low[0x20];
1393
1394 u8 edpl_bip_errors_lane0_high[0x20];
1395
1396 u8 edpl_bip_errors_lane0_low[0x20];
1397
1398 u8 edpl_bip_errors_lane1_high[0x20];
1399
1400 u8 edpl_bip_errors_lane1_low[0x20];
1401
1402 u8 edpl_bip_errors_lane2_high[0x20];
1403
1404 u8 edpl_bip_errors_lane2_low[0x20];
1405
1406 u8 edpl_bip_errors_lane3_high[0x20];
1407
1408 u8 edpl_bip_errors_lane3_low[0x20];
1409
1410 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1411
1412 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1413
1414 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1415
1416 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1417
1418 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1419
1420 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1421
1422 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1423
1424 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1425
1426 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1427
1428 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1429
1430 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1431
1432 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1433
1434 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1435
1436 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1437
1438 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1439
1440 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1441
1442 u8 rs_fec_corrected_blocks_high[0x20];
1443
1444 u8 rs_fec_corrected_blocks_low[0x20];
1445
1446 u8 rs_fec_uncorrectable_blocks_high[0x20];
1447
1448 u8 rs_fec_uncorrectable_blocks_low[0x20];
1449
1450 u8 rs_fec_no_errors_blocks_high[0x20];
1451
1452 u8 rs_fec_no_errors_blocks_low[0x20];
1453
1454 u8 rs_fec_single_error_blocks_high[0x20];
1455
1456 u8 rs_fec_single_error_blocks_low[0x20];
1457
1458 u8 rs_fec_corrected_symbols_total_high[0x20];
1459
1460 u8 rs_fec_corrected_symbols_total_low[0x20];
1461
1462 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1463
1464 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1465
1466 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1467
1468 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1469
1470 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1471
1472 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1473
1474 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1475
1476 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1477
1478 u8 link_down_events[0x20];
1479
1480 u8 successful_recovery_events[0x20];
1481
1482 u8 reserved_at_640[0x180];
1483 };
1484
1485 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1486 u8 time_since_last_clear_high[0x20];
1487
1488 u8 time_since_last_clear_low[0x20];
1489
1490 u8 phy_received_bits_high[0x20];
1491
1492 u8 phy_received_bits_low[0x20];
1493
1494 u8 phy_symbol_errors_high[0x20];
1495
1496 u8 phy_symbol_errors_low[0x20];
1497
1498 u8 phy_corrected_bits_high[0x20];
1499
1500 u8 phy_corrected_bits_low[0x20];
1501
1502 u8 phy_corrected_bits_lane0_high[0x20];
1503
1504 u8 phy_corrected_bits_lane0_low[0x20];
1505
1506 u8 phy_corrected_bits_lane1_high[0x20];
1507
1508 u8 phy_corrected_bits_lane1_low[0x20];
1509
1510 u8 phy_corrected_bits_lane2_high[0x20];
1511
1512 u8 phy_corrected_bits_lane2_low[0x20];
1513
1514 u8 phy_corrected_bits_lane3_high[0x20];
1515
1516 u8 phy_corrected_bits_lane3_low[0x20];
1517
1518 u8 reserved_at_200[0x5c0];
1519 };
1520
1521 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1522 u8 symbol_error_counter[0x10];
1523
1524 u8 link_error_recovery_counter[0x8];
1525
1526 u8 link_downed_counter[0x8];
1527
1528 u8 port_rcv_errors[0x10];
1529
1530 u8 port_rcv_remote_physical_errors[0x10];
1531
1532 u8 port_rcv_switch_relay_errors[0x10];
1533
1534 u8 port_xmit_discards[0x10];
1535
1536 u8 port_xmit_constraint_errors[0x8];
1537
1538 u8 port_rcv_constraint_errors[0x8];
1539
1540 u8 reserved_at_70[0x8];
1541
1542 u8 link_overrun_errors[0x8];
1543
1544 u8 reserved_at_80[0x10];
1545
1546 u8 vl_15_dropped[0x10];
1547
1548 u8 reserved_at_a0[0x80];
1549
1550 u8 port_xmit_wait[0x20];
1551 };
1552
1553 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1554 u8 transmit_queue_high[0x20];
1555
1556 u8 transmit_queue_low[0x20];
1557
1558 u8 reserved_at_40[0x780];
1559 };
1560
1561 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1562 u8 rx_octets_high[0x20];
1563
1564 u8 rx_octets_low[0x20];
1565
1566 u8 reserved_at_40[0xc0];
1567
1568 u8 rx_frames_high[0x20];
1569
1570 u8 rx_frames_low[0x20];
1571
1572 u8 tx_octets_high[0x20];
1573
1574 u8 tx_octets_low[0x20];
1575
1576 u8 reserved_at_180[0xc0];
1577
1578 u8 tx_frames_high[0x20];
1579
1580 u8 tx_frames_low[0x20];
1581
1582 u8 rx_pause_high[0x20];
1583
1584 u8 rx_pause_low[0x20];
1585
1586 u8 rx_pause_duration_high[0x20];
1587
1588 u8 rx_pause_duration_low[0x20];
1589
1590 u8 tx_pause_high[0x20];
1591
1592 u8 tx_pause_low[0x20];
1593
1594 u8 tx_pause_duration_high[0x20];
1595
1596 u8 tx_pause_duration_low[0x20];
1597
1598 u8 rx_pause_transition_high[0x20];
1599
1600 u8 rx_pause_transition_low[0x20];
1601
1602 u8 reserved_at_3c0[0x400];
1603 };
1604
1605 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1606 u8 port_transmit_wait_high[0x20];
1607
1608 u8 port_transmit_wait_low[0x20];
1609
1610 u8 reserved_at_40[0x100];
1611
1612 u8 rx_buffer_almost_full_high[0x20];
1613
1614 u8 rx_buffer_almost_full_low[0x20];
1615
1616 u8 rx_buffer_full_high[0x20];
1617
1618 u8 rx_buffer_full_low[0x20];
1619
1620 u8 reserved_at_1c0[0x600];
1621 };
1622
1623 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1624 u8 dot3stats_alignment_errors_high[0x20];
1625
1626 u8 dot3stats_alignment_errors_low[0x20];
1627
1628 u8 dot3stats_fcs_errors_high[0x20];
1629
1630 u8 dot3stats_fcs_errors_low[0x20];
1631
1632 u8 dot3stats_single_collision_frames_high[0x20];
1633
1634 u8 dot3stats_single_collision_frames_low[0x20];
1635
1636 u8 dot3stats_multiple_collision_frames_high[0x20];
1637
1638 u8 dot3stats_multiple_collision_frames_low[0x20];
1639
1640 u8 dot3stats_sqe_test_errors_high[0x20];
1641
1642 u8 dot3stats_sqe_test_errors_low[0x20];
1643
1644 u8 dot3stats_deferred_transmissions_high[0x20];
1645
1646 u8 dot3stats_deferred_transmissions_low[0x20];
1647
1648 u8 dot3stats_late_collisions_high[0x20];
1649
1650 u8 dot3stats_late_collisions_low[0x20];
1651
1652 u8 dot3stats_excessive_collisions_high[0x20];
1653
1654 u8 dot3stats_excessive_collisions_low[0x20];
1655
1656 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1657
1658 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1659
1660 u8 dot3stats_carrier_sense_errors_high[0x20];
1661
1662 u8 dot3stats_carrier_sense_errors_low[0x20];
1663
1664 u8 dot3stats_frame_too_longs_high[0x20];
1665
1666 u8 dot3stats_frame_too_longs_low[0x20];
1667
1668 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1669
1670 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1671
1672 u8 dot3stats_symbol_errors_high[0x20];
1673
1674 u8 dot3stats_symbol_errors_low[0x20];
1675
1676 u8 dot3control_in_unknown_opcodes_high[0x20];
1677
1678 u8 dot3control_in_unknown_opcodes_low[0x20];
1679
1680 u8 dot3in_pause_frames_high[0x20];
1681
1682 u8 dot3in_pause_frames_low[0x20];
1683
1684 u8 dot3out_pause_frames_high[0x20];
1685
1686 u8 dot3out_pause_frames_low[0x20];
1687
1688 u8 reserved_at_400[0x3c0];
1689 };
1690
1691 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1692 u8 ether_stats_drop_events_high[0x20];
1693
1694 u8 ether_stats_drop_events_low[0x20];
1695
1696 u8 ether_stats_octets_high[0x20];
1697
1698 u8 ether_stats_octets_low[0x20];
1699
1700 u8 ether_stats_pkts_high[0x20];
1701
1702 u8 ether_stats_pkts_low[0x20];
1703
1704 u8 ether_stats_broadcast_pkts_high[0x20];
1705
1706 u8 ether_stats_broadcast_pkts_low[0x20];
1707
1708 u8 ether_stats_multicast_pkts_high[0x20];
1709
1710 u8 ether_stats_multicast_pkts_low[0x20];
1711
1712 u8 ether_stats_crc_align_errors_high[0x20];
1713
1714 u8 ether_stats_crc_align_errors_low[0x20];
1715
1716 u8 ether_stats_undersize_pkts_high[0x20];
1717
1718 u8 ether_stats_undersize_pkts_low[0x20];
1719
1720 u8 ether_stats_oversize_pkts_high[0x20];
1721
1722 u8 ether_stats_oversize_pkts_low[0x20];
1723
1724 u8 ether_stats_fragments_high[0x20];
1725
1726 u8 ether_stats_fragments_low[0x20];
1727
1728 u8 ether_stats_jabbers_high[0x20];
1729
1730 u8 ether_stats_jabbers_low[0x20];
1731
1732 u8 ether_stats_collisions_high[0x20];
1733
1734 u8 ether_stats_collisions_low[0x20];
1735
1736 u8 ether_stats_pkts64octets_high[0x20];
1737
1738 u8 ether_stats_pkts64octets_low[0x20];
1739
1740 u8 ether_stats_pkts65to127octets_high[0x20];
1741
1742 u8 ether_stats_pkts65to127octets_low[0x20];
1743
1744 u8 ether_stats_pkts128to255octets_high[0x20];
1745
1746 u8 ether_stats_pkts128to255octets_low[0x20];
1747
1748 u8 ether_stats_pkts256to511octets_high[0x20];
1749
1750 u8 ether_stats_pkts256to511octets_low[0x20];
1751
1752 u8 ether_stats_pkts512to1023octets_high[0x20];
1753
1754 u8 ether_stats_pkts512to1023octets_low[0x20];
1755
1756 u8 ether_stats_pkts1024to1518octets_high[0x20];
1757
1758 u8 ether_stats_pkts1024to1518octets_low[0x20];
1759
1760 u8 ether_stats_pkts1519to2047octets_high[0x20];
1761
1762 u8 ether_stats_pkts1519to2047octets_low[0x20];
1763
1764 u8 ether_stats_pkts2048to4095octets_high[0x20];
1765
1766 u8 ether_stats_pkts2048to4095octets_low[0x20];
1767
1768 u8 ether_stats_pkts4096to8191octets_high[0x20];
1769
1770 u8 ether_stats_pkts4096to8191octets_low[0x20];
1771
1772 u8 ether_stats_pkts8192to10239octets_high[0x20];
1773
1774 u8 ether_stats_pkts8192to10239octets_low[0x20];
1775
1776 u8 reserved_at_540[0x280];
1777 };
1778
1779 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1780 u8 if_in_octets_high[0x20];
1781
1782 u8 if_in_octets_low[0x20];
1783
1784 u8 if_in_ucast_pkts_high[0x20];
1785
1786 u8 if_in_ucast_pkts_low[0x20];
1787
1788 u8 if_in_discards_high[0x20];
1789
1790 u8 if_in_discards_low[0x20];
1791
1792 u8 if_in_errors_high[0x20];
1793
1794 u8 if_in_errors_low[0x20];
1795
1796 u8 if_in_unknown_protos_high[0x20];
1797
1798 u8 if_in_unknown_protos_low[0x20];
1799
1800 u8 if_out_octets_high[0x20];
1801
1802 u8 if_out_octets_low[0x20];
1803
1804 u8 if_out_ucast_pkts_high[0x20];
1805
1806 u8 if_out_ucast_pkts_low[0x20];
1807
1808 u8 if_out_discards_high[0x20];
1809
1810 u8 if_out_discards_low[0x20];
1811
1812 u8 if_out_errors_high[0x20];
1813
1814 u8 if_out_errors_low[0x20];
1815
1816 u8 if_in_multicast_pkts_high[0x20];
1817
1818 u8 if_in_multicast_pkts_low[0x20];
1819
1820 u8 if_in_broadcast_pkts_high[0x20];
1821
1822 u8 if_in_broadcast_pkts_low[0x20];
1823
1824 u8 if_out_multicast_pkts_high[0x20];
1825
1826 u8 if_out_multicast_pkts_low[0x20];
1827
1828 u8 if_out_broadcast_pkts_high[0x20];
1829
1830 u8 if_out_broadcast_pkts_low[0x20];
1831
1832 u8 reserved_at_340[0x480];
1833 };
1834
1835 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1836 u8 a_frames_transmitted_ok_high[0x20];
1837
1838 u8 a_frames_transmitted_ok_low[0x20];
1839
1840 u8 a_frames_received_ok_high[0x20];
1841
1842 u8 a_frames_received_ok_low[0x20];
1843
1844 u8 a_frame_check_sequence_errors_high[0x20];
1845
1846 u8 a_frame_check_sequence_errors_low[0x20];
1847
1848 u8 a_alignment_errors_high[0x20];
1849
1850 u8 a_alignment_errors_low[0x20];
1851
1852 u8 a_octets_transmitted_ok_high[0x20];
1853
1854 u8 a_octets_transmitted_ok_low[0x20];
1855
1856 u8 a_octets_received_ok_high[0x20];
1857
1858 u8 a_octets_received_ok_low[0x20];
1859
1860 u8 a_multicast_frames_xmitted_ok_high[0x20];
1861
1862 u8 a_multicast_frames_xmitted_ok_low[0x20];
1863
1864 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1865
1866 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1867
1868 u8 a_multicast_frames_received_ok_high[0x20];
1869
1870 u8 a_multicast_frames_received_ok_low[0x20];
1871
1872 u8 a_broadcast_frames_received_ok_high[0x20];
1873
1874 u8 a_broadcast_frames_received_ok_low[0x20];
1875
1876 u8 a_in_range_length_errors_high[0x20];
1877
1878 u8 a_in_range_length_errors_low[0x20];
1879
1880 u8 a_out_of_range_length_field_high[0x20];
1881
1882 u8 a_out_of_range_length_field_low[0x20];
1883
1884 u8 a_frame_too_long_errors_high[0x20];
1885
1886 u8 a_frame_too_long_errors_low[0x20];
1887
1888 u8 a_symbol_error_during_carrier_high[0x20];
1889
1890 u8 a_symbol_error_during_carrier_low[0x20];
1891
1892 u8 a_mac_control_frames_transmitted_high[0x20];
1893
1894 u8 a_mac_control_frames_transmitted_low[0x20];
1895
1896 u8 a_mac_control_frames_received_high[0x20];
1897
1898 u8 a_mac_control_frames_received_low[0x20];
1899
1900 u8 a_unsupported_opcodes_received_high[0x20];
1901
1902 u8 a_unsupported_opcodes_received_low[0x20];
1903
1904 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1905
1906 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1907
1908 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1909
1910 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1911
1912 u8 reserved_at_4c0[0x300];
1913 };
1914
1915 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1916 u8 life_time_counter_high[0x20];
1917
1918 u8 life_time_counter_low[0x20];
1919
1920 u8 rx_errors[0x20];
1921
1922 u8 tx_errors[0x20];
1923
1924 u8 l0_to_recovery_eieos[0x20];
1925
1926 u8 l0_to_recovery_ts[0x20];
1927
1928 u8 l0_to_recovery_framing[0x20];
1929
1930 u8 l0_to_recovery_retrain[0x20];
1931
1932 u8 crc_error_dllp[0x20];
1933
1934 u8 crc_error_tlp[0x20];
1935
1936 u8 tx_overflow_buffer_pkt_high[0x20];
1937
1938 u8 tx_overflow_buffer_pkt_low[0x20];
1939
1940 u8 outbound_stalled_reads[0x20];
1941
1942 u8 outbound_stalled_writes[0x20];
1943
1944 u8 outbound_stalled_reads_events[0x20];
1945
1946 u8 outbound_stalled_writes_events[0x20];
1947
1948 u8 reserved_at_200[0x5c0];
1949 };
1950
1951 struct mlx5_ifc_cmd_inter_comp_event_bits {
1952 u8 command_completion_vector[0x20];
1953
1954 u8 reserved_at_20[0xc0];
1955 };
1956
1957 struct mlx5_ifc_stall_vl_event_bits {
1958 u8 reserved_at_0[0x18];
1959 u8 port_num[0x1];
1960 u8 reserved_at_19[0x3];
1961 u8 vl[0x4];
1962
1963 u8 reserved_at_20[0xa0];
1964 };
1965
1966 struct mlx5_ifc_db_bf_congestion_event_bits {
1967 u8 event_subtype[0x8];
1968 u8 reserved_at_8[0x8];
1969 u8 congestion_level[0x8];
1970 u8 reserved_at_18[0x8];
1971
1972 u8 reserved_at_20[0xa0];
1973 };
1974
1975 struct mlx5_ifc_gpio_event_bits {
1976 u8 reserved_at_0[0x60];
1977
1978 u8 gpio_event_hi[0x20];
1979
1980 u8 gpio_event_lo[0x20];
1981
1982 u8 reserved_at_a0[0x40];
1983 };
1984
1985 struct mlx5_ifc_port_state_change_event_bits {
1986 u8 reserved_at_0[0x40];
1987
1988 u8 port_num[0x4];
1989 u8 reserved_at_44[0x1c];
1990
1991 u8 reserved_at_60[0x80];
1992 };
1993
1994 struct mlx5_ifc_dropped_packet_logged_bits {
1995 u8 reserved_at_0[0xe0];
1996 };
1997
1998 enum {
1999 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2000 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2001 };
2002
2003 struct mlx5_ifc_cq_error_bits {
2004 u8 reserved_at_0[0x8];
2005 u8 cqn[0x18];
2006
2007 u8 reserved_at_20[0x20];
2008
2009 u8 reserved_at_40[0x18];
2010 u8 syndrome[0x8];
2011
2012 u8 reserved_at_60[0x80];
2013 };
2014
2015 struct mlx5_ifc_rdma_page_fault_event_bits {
2016 u8 bytes_committed[0x20];
2017
2018 u8 r_key[0x20];
2019
2020 u8 reserved_at_40[0x10];
2021 u8 packet_len[0x10];
2022
2023 u8 rdma_op_len[0x20];
2024
2025 u8 rdma_va[0x40];
2026
2027 u8 reserved_at_c0[0x5];
2028 u8 rdma[0x1];
2029 u8 write[0x1];
2030 u8 requestor[0x1];
2031 u8 qp_number[0x18];
2032 };
2033
2034 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2035 u8 bytes_committed[0x20];
2036
2037 u8 reserved_at_20[0x10];
2038 u8 wqe_index[0x10];
2039
2040 u8 reserved_at_40[0x10];
2041 u8 len[0x10];
2042
2043 u8 reserved_at_60[0x60];
2044
2045 u8 reserved_at_c0[0x5];
2046 u8 rdma[0x1];
2047 u8 write_read[0x1];
2048 u8 requestor[0x1];
2049 u8 qpn[0x18];
2050 };
2051
2052 struct mlx5_ifc_qp_events_bits {
2053 u8 reserved_at_0[0xa0];
2054
2055 u8 type[0x8];
2056 u8 reserved_at_a8[0x18];
2057
2058 u8 reserved_at_c0[0x8];
2059 u8 qpn_rqn_sqn[0x18];
2060 };
2061
2062 struct mlx5_ifc_dct_events_bits {
2063 u8 reserved_at_0[0xc0];
2064
2065 u8 reserved_at_c0[0x8];
2066 u8 dct_number[0x18];
2067 };
2068
2069 struct mlx5_ifc_comp_event_bits {
2070 u8 reserved_at_0[0xc0];
2071
2072 u8 reserved_at_c0[0x8];
2073 u8 cq_number[0x18];
2074 };
2075
2076 enum {
2077 MLX5_QPC_STATE_RST = 0x0,
2078 MLX5_QPC_STATE_INIT = 0x1,
2079 MLX5_QPC_STATE_RTR = 0x2,
2080 MLX5_QPC_STATE_RTS = 0x3,
2081 MLX5_QPC_STATE_SQER = 0x4,
2082 MLX5_QPC_STATE_ERR = 0x6,
2083 MLX5_QPC_STATE_SQD = 0x7,
2084 MLX5_QPC_STATE_SUSPENDED = 0x9,
2085 };
2086
2087 enum {
2088 MLX5_QPC_ST_RC = 0x0,
2089 MLX5_QPC_ST_UC = 0x1,
2090 MLX5_QPC_ST_UD = 0x2,
2091 MLX5_QPC_ST_XRC = 0x3,
2092 MLX5_QPC_ST_DCI = 0x5,
2093 MLX5_QPC_ST_QP0 = 0x7,
2094 MLX5_QPC_ST_QP1 = 0x8,
2095 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2096 MLX5_QPC_ST_REG_UMR = 0xc,
2097 };
2098
2099 enum {
2100 MLX5_QPC_PM_STATE_ARMED = 0x0,
2101 MLX5_QPC_PM_STATE_REARM = 0x1,
2102 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2103 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2104 };
2105
2106 enum {
2107 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2108 };
2109
2110 enum {
2111 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2112 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2113 };
2114
2115 enum {
2116 MLX5_QPC_MTU_256_BYTES = 0x1,
2117 MLX5_QPC_MTU_512_BYTES = 0x2,
2118 MLX5_QPC_MTU_1K_BYTES = 0x3,
2119 MLX5_QPC_MTU_2K_BYTES = 0x4,
2120 MLX5_QPC_MTU_4K_BYTES = 0x5,
2121 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2122 };
2123
2124 enum {
2125 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2126 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2127 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2128 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2129 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2130 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2131 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2132 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2133 };
2134
2135 enum {
2136 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2137 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2138 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2139 };
2140
2141 enum {
2142 MLX5_QPC_CS_RES_DISABLE = 0x0,
2143 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2144 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2145 };
2146
2147 struct mlx5_ifc_qpc_bits {
2148 u8 state[0x4];
2149 u8 lag_tx_port_affinity[0x4];
2150 u8 st[0x8];
2151 u8 reserved_at_10[0x3];
2152 u8 pm_state[0x2];
2153 u8 reserved_at_15[0x3];
2154 u8 offload_type[0x4];
2155 u8 end_padding_mode[0x2];
2156 u8 reserved_at_1e[0x2];
2157
2158 u8 wq_signature[0x1];
2159 u8 block_lb_mc[0x1];
2160 u8 atomic_like_write_en[0x1];
2161 u8 latency_sensitive[0x1];
2162 u8 reserved_at_24[0x1];
2163 u8 drain_sigerr[0x1];
2164 u8 reserved_at_26[0x2];
2165 u8 pd[0x18];
2166
2167 u8 mtu[0x3];
2168 u8 log_msg_max[0x5];
2169 u8 reserved_at_48[0x1];
2170 u8 log_rq_size[0x4];
2171 u8 log_rq_stride[0x3];
2172 u8 no_sq[0x1];
2173 u8 log_sq_size[0x4];
2174 u8 reserved_at_55[0x6];
2175 u8 rlky[0x1];
2176 u8 ulp_stateless_offload_mode[0x4];
2177
2178 u8 counter_set_id[0x8];
2179 u8 uar_page[0x18];
2180
2181 u8 reserved_at_80[0x8];
2182 u8 user_index[0x18];
2183
2184 u8 reserved_at_a0[0x3];
2185 u8 log_page_size[0x5];
2186 u8 remote_qpn[0x18];
2187
2188 struct mlx5_ifc_ads_bits primary_address_path;
2189
2190 struct mlx5_ifc_ads_bits secondary_address_path;
2191
2192 u8 log_ack_req_freq[0x4];
2193 u8 reserved_at_384[0x4];
2194 u8 log_sra_max[0x3];
2195 u8 reserved_at_38b[0x2];
2196 u8 retry_count[0x3];
2197 u8 rnr_retry[0x3];
2198 u8 reserved_at_393[0x1];
2199 u8 fre[0x1];
2200 u8 cur_rnr_retry[0x3];
2201 u8 cur_retry_count[0x3];
2202 u8 reserved_at_39b[0x5];
2203
2204 u8 reserved_at_3a0[0x20];
2205
2206 u8 reserved_at_3c0[0x8];
2207 u8 next_send_psn[0x18];
2208
2209 u8 reserved_at_3e0[0x8];
2210 u8 cqn_snd[0x18];
2211
2212 u8 reserved_at_400[0x8];
2213 u8 deth_sqpn[0x18];
2214
2215 u8 reserved_at_420[0x20];
2216
2217 u8 reserved_at_440[0x8];
2218 u8 last_acked_psn[0x18];
2219
2220 u8 reserved_at_460[0x8];
2221 u8 ssn[0x18];
2222
2223 u8 reserved_at_480[0x8];
2224 u8 log_rra_max[0x3];
2225 u8 reserved_at_48b[0x1];
2226 u8 atomic_mode[0x4];
2227 u8 rre[0x1];
2228 u8 rwe[0x1];
2229 u8 rae[0x1];
2230 u8 reserved_at_493[0x1];
2231 u8 page_offset[0x6];
2232 u8 reserved_at_49a[0x3];
2233 u8 cd_slave_receive[0x1];
2234 u8 cd_slave_send[0x1];
2235 u8 cd_master[0x1];
2236
2237 u8 reserved_at_4a0[0x3];
2238 u8 min_rnr_nak[0x5];
2239 u8 next_rcv_psn[0x18];
2240
2241 u8 reserved_at_4c0[0x8];
2242 u8 xrcd[0x18];
2243
2244 u8 reserved_at_4e0[0x8];
2245 u8 cqn_rcv[0x18];
2246
2247 u8 dbr_addr[0x40];
2248
2249 u8 q_key[0x20];
2250
2251 u8 reserved_at_560[0x5];
2252 u8 rq_type[0x3];
2253 u8 srqn_rmpn_xrqn[0x18];
2254
2255 u8 reserved_at_580[0x8];
2256 u8 rmsn[0x18];
2257
2258 u8 hw_sq_wqebb_counter[0x10];
2259 u8 sw_sq_wqebb_counter[0x10];
2260
2261 u8 hw_rq_counter[0x20];
2262
2263 u8 sw_rq_counter[0x20];
2264
2265 u8 reserved_at_600[0x20];
2266
2267 u8 reserved_at_620[0xf];
2268 u8 cgs[0x1];
2269 u8 cs_req[0x8];
2270 u8 cs_res[0x8];
2271
2272 u8 dc_access_key[0x40];
2273
2274 u8 reserved_at_680[0xc0];
2275 };
2276
2277 struct mlx5_ifc_roce_addr_layout_bits {
2278 u8 source_l3_address[16][0x8];
2279
2280 u8 reserved_at_80[0x3];
2281 u8 vlan_valid[0x1];
2282 u8 vlan_id[0xc];
2283 u8 source_mac_47_32[0x10];
2284
2285 u8 source_mac_31_0[0x20];
2286
2287 u8 reserved_at_c0[0x14];
2288 u8 roce_l3_type[0x4];
2289 u8 roce_version[0x8];
2290
2291 u8 reserved_at_e0[0x20];
2292 };
2293
2294 union mlx5_ifc_hca_cap_union_bits {
2295 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2296 struct mlx5_ifc_odp_cap_bits odp_cap;
2297 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2298 struct mlx5_ifc_roce_cap_bits roce_cap;
2299 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2300 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2301 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2302 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2303 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2304 struct mlx5_ifc_qos_cap_bits qos_cap;
2305 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2306 u8 reserved_at_0[0x8000];
2307 };
2308
2309 enum {
2310 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2311 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2312 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2313 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2314 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2315 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2316 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2317 };
2318
2319 struct mlx5_ifc_flow_context_bits {
2320 u8 reserved_at_0[0x20];
2321
2322 u8 group_id[0x20];
2323
2324 u8 reserved_at_40[0x8];
2325 u8 flow_tag[0x18];
2326
2327 u8 reserved_at_60[0x10];
2328 u8 action[0x10];
2329
2330 u8 reserved_at_80[0x8];
2331 u8 destination_list_size[0x18];
2332
2333 u8 reserved_at_a0[0x8];
2334 u8 flow_counter_list_size[0x18];
2335
2336 u8 encap_id[0x20];
2337
2338 u8 modify_header_id[0x20];
2339
2340 u8 reserved_at_100[0x100];
2341
2342 struct mlx5_ifc_fte_match_param_bits match_value;
2343
2344 u8 reserved_at_1200[0x600];
2345
2346 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2347 };
2348
2349 enum {
2350 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2351 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2352 };
2353
2354 struct mlx5_ifc_xrc_srqc_bits {
2355 u8 state[0x4];
2356 u8 log_xrc_srq_size[0x4];
2357 u8 reserved_at_8[0x18];
2358
2359 u8 wq_signature[0x1];
2360 u8 cont_srq[0x1];
2361 u8 reserved_at_22[0x1];
2362 u8 rlky[0x1];
2363 u8 basic_cyclic_rcv_wqe[0x1];
2364 u8 log_rq_stride[0x3];
2365 u8 xrcd[0x18];
2366
2367 u8 page_offset[0x6];
2368 u8 reserved_at_46[0x2];
2369 u8 cqn[0x18];
2370
2371 u8 reserved_at_60[0x20];
2372
2373 u8 user_index_equal_xrc_srqn[0x1];
2374 u8 reserved_at_81[0x1];
2375 u8 log_page_size[0x6];
2376 u8 user_index[0x18];
2377
2378 u8 reserved_at_a0[0x20];
2379
2380 u8 reserved_at_c0[0x8];
2381 u8 pd[0x18];
2382
2383 u8 lwm[0x10];
2384 u8 wqe_cnt[0x10];
2385
2386 u8 reserved_at_100[0x40];
2387
2388 u8 db_record_addr_h[0x20];
2389
2390 u8 db_record_addr_l[0x1e];
2391 u8 reserved_at_17e[0x2];
2392
2393 u8 reserved_at_180[0x80];
2394 };
2395
2396 struct mlx5_ifc_traffic_counter_bits {
2397 u8 packets[0x40];
2398
2399 u8 octets[0x40];
2400 };
2401
2402 struct mlx5_ifc_tisc_bits {
2403 u8 strict_lag_tx_port_affinity[0x1];
2404 u8 reserved_at_1[0x3];
2405 u8 lag_tx_port_affinity[0x04];
2406
2407 u8 reserved_at_8[0x4];
2408 u8 prio[0x4];
2409 u8 reserved_at_10[0x10];
2410
2411 u8 reserved_at_20[0x100];
2412
2413 u8 reserved_at_120[0x8];
2414 u8 transport_domain[0x18];
2415
2416 u8 reserved_at_140[0x8];
2417 u8 underlay_qpn[0x18];
2418 u8 reserved_at_160[0x3a0];
2419 };
2420
2421 enum {
2422 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2423 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2424 };
2425
2426 enum {
2427 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2428 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2429 };
2430
2431 enum {
2432 MLX5_RX_HASH_FN_NONE = 0x0,
2433 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2434 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2435 };
2436
2437 enum {
2438 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2439 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2440 };
2441
2442 struct mlx5_ifc_tirc_bits {
2443 u8 reserved_at_0[0x20];
2444
2445 u8 disp_type[0x4];
2446 u8 reserved_at_24[0x1c];
2447
2448 u8 reserved_at_40[0x40];
2449
2450 u8 reserved_at_80[0x4];
2451 u8 lro_timeout_period_usecs[0x10];
2452 u8 lro_enable_mask[0x4];
2453 u8 lro_max_ip_payload_size[0x8];
2454
2455 u8 reserved_at_a0[0x40];
2456
2457 u8 reserved_at_e0[0x8];
2458 u8 inline_rqn[0x18];
2459
2460 u8 rx_hash_symmetric[0x1];
2461 u8 reserved_at_101[0x1];
2462 u8 tunneled_offload_en[0x1];
2463 u8 reserved_at_103[0x5];
2464 u8 indirect_table[0x18];
2465
2466 u8 rx_hash_fn[0x4];
2467 u8 reserved_at_124[0x2];
2468 u8 self_lb_block[0x2];
2469 u8 transport_domain[0x18];
2470
2471 u8 rx_hash_toeplitz_key[10][0x20];
2472
2473 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2474
2475 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2476
2477 u8 reserved_at_2c0[0x4c0];
2478 };
2479
2480 enum {
2481 MLX5_SRQC_STATE_GOOD = 0x0,
2482 MLX5_SRQC_STATE_ERROR = 0x1,
2483 };
2484
2485 struct mlx5_ifc_srqc_bits {
2486 u8 state[0x4];
2487 u8 log_srq_size[0x4];
2488 u8 reserved_at_8[0x18];
2489
2490 u8 wq_signature[0x1];
2491 u8 cont_srq[0x1];
2492 u8 reserved_at_22[0x1];
2493 u8 rlky[0x1];
2494 u8 reserved_at_24[0x1];
2495 u8 log_rq_stride[0x3];
2496 u8 xrcd[0x18];
2497
2498 u8 page_offset[0x6];
2499 u8 reserved_at_46[0x2];
2500 u8 cqn[0x18];
2501
2502 u8 reserved_at_60[0x20];
2503
2504 u8 reserved_at_80[0x2];
2505 u8 log_page_size[0x6];
2506 u8 reserved_at_88[0x18];
2507
2508 u8 reserved_at_a0[0x20];
2509
2510 u8 reserved_at_c0[0x8];
2511 u8 pd[0x18];
2512
2513 u8 lwm[0x10];
2514 u8 wqe_cnt[0x10];
2515
2516 u8 reserved_at_100[0x40];
2517
2518 u8 dbr_addr[0x40];
2519
2520 u8 reserved_at_180[0x80];
2521 };
2522
2523 enum {
2524 MLX5_SQC_STATE_RST = 0x0,
2525 MLX5_SQC_STATE_RDY = 0x1,
2526 MLX5_SQC_STATE_ERR = 0x3,
2527 };
2528
2529 struct mlx5_ifc_sqc_bits {
2530 u8 rlky[0x1];
2531 u8 cd_master[0x1];
2532 u8 fre[0x1];
2533 u8 flush_in_error_en[0x1];
2534 u8 allow_multi_pkt_send_wqe[0x1];
2535 u8 min_wqe_inline_mode[0x3];
2536 u8 state[0x4];
2537 u8 reg_umr[0x1];
2538 u8 allow_swp[0x1];
2539 u8 hairpin[0x1];
2540 u8 reserved_at_f[0x11];
2541
2542 u8 reserved_at_20[0x8];
2543 u8 user_index[0x18];
2544
2545 u8 reserved_at_40[0x8];
2546 u8 cqn[0x18];
2547
2548 u8 reserved_at_60[0x8];
2549 u8 hairpin_peer_rq[0x18];
2550
2551 u8 reserved_at_80[0x10];
2552 u8 hairpin_peer_vhca[0x10];
2553
2554 u8 reserved_at_a0[0x50];
2555
2556 u8 packet_pacing_rate_limit_index[0x10];
2557 u8 tis_lst_sz[0x10];
2558 u8 reserved_at_110[0x10];
2559
2560 u8 reserved_at_120[0x40];
2561
2562 u8 reserved_at_160[0x8];
2563 u8 tis_num_0[0x18];
2564
2565 struct mlx5_ifc_wq_bits wq;
2566 };
2567
2568 enum {
2569 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2570 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2571 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2572 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2573 };
2574
2575 struct mlx5_ifc_scheduling_context_bits {
2576 u8 element_type[0x8];
2577 u8 reserved_at_8[0x18];
2578
2579 u8 element_attributes[0x20];
2580
2581 u8 parent_element_id[0x20];
2582
2583 u8 reserved_at_60[0x40];
2584
2585 u8 bw_share[0x20];
2586
2587 u8 max_average_bw[0x20];
2588
2589 u8 reserved_at_e0[0x120];
2590 };
2591
2592 struct mlx5_ifc_rqtc_bits {
2593 u8 reserved_at_0[0xa0];
2594
2595 u8 reserved_at_a0[0x10];
2596 u8 rqt_max_size[0x10];
2597
2598 u8 reserved_at_c0[0x10];
2599 u8 rqt_actual_size[0x10];
2600
2601 u8 reserved_at_e0[0x6a0];
2602
2603 struct mlx5_ifc_rq_num_bits rq_num[0];
2604 };
2605
2606 enum {
2607 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2608 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2609 };
2610
2611 enum {
2612 MLX5_RQC_STATE_RST = 0x0,
2613 MLX5_RQC_STATE_RDY = 0x1,
2614 MLX5_RQC_STATE_ERR = 0x3,
2615 };
2616
2617 struct mlx5_ifc_rqc_bits {
2618 u8 rlky[0x1];
2619 u8 delay_drop_en[0x1];
2620 u8 scatter_fcs[0x1];
2621 u8 vsd[0x1];
2622 u8 mem_rq_type[0x4];
2623 u8 state[0x4];
2624 u8 reserved_at_c[0x1];
2625 u8 flush_in_error_en[0x1];
2626 u8 hairpin[0x1];
2627 u8 reserved_at_f[0x11];
2628
2629 u8 reserved_at_20[0x8];
2630 u8 user_index[0x18];
2631
2632 u8 reserved_at_40[0x8];
2633 u8 cqn[0x18];
2634
2635 u8 counter_set_id[0x8];
2636 u8 reserved_at_68[0x18];
2637
2638 u8 reserved_at_80[0x8];
2639 u8 rmpn[0x18];
2640
2641 u8 reserved_at_a0[0x8];
2642 u8 hairpin_peer_sq[0x18];
2643
2644 u8 reserved_at_c0[0x10];
2645 u8 hairpin_peer_vhca[0x10];
2646
2647 u8 reserved_at_e0[0xa0];
2648
2649 struct mlx5_ifc_wq_bits wq;
2650 };
2651
2652 enum {
2653 MLX5_RMPC_STATE_RDY = 0x1,
2654 MLX5_RMPC_STATE_ERR = 0x3,
2655 };
2656
2657 struct mlx5_ifc_rmpc_bits {
2658 u8 reserved_at_0[0x8];
2659 u8 state[0x4];
2660 u8 reserved_at_c[0x14];
2661
2662 u8 basic_cyclic_rcv_wqe[0x1];
2663 u8 reserved_at_21[0x1f];
2664
2665 u8 reserved_at_40[0x140];
2666
2667 struct mlx5_ifc_wq_bits wq;
2668 };
2669
2670 struct mlx5_ifc_nic_vport_context_bits {
2671 u8 reserved_at_0[0x5];
2672 u8 min_wqe_inline_mode[0x3];
2673 u8 reserved_at_8[0x15];
2674 u8 disable_mc_local_lb[0x1];
2675 u8 disable_uc_local_lb[0x1];
2676 u8 roce_en[0x1];
2677
2678 u8 arm_change_event[0x1];
2679 u8 reserved_at_21[0x1a];
2680 u8 event_on_mtu[0x1];
2681 u8 event_on_promisc_change[0x1];
2682 u8 event_on_vlan_change[0x1];
2683 u8 event_on_mc_address_change[0x1];
2684 u8 event_on_uc_address_change[0x1];
2685
2686 u8 reserved_at_40[0xc];
2687
2688 u8 affiliation_criteria[0x4];
2689 u8 affiliated_vhca_id[0x10];
2690
2691 u8 reserved_at_60[0xd0];
2692
2693 u8 mtu[0x10];
2694
2695 u8 system_image_guid[0x40];
2696 u8 port_guid[0x40];
2697 u8 node_guid[0x40];
2698
2699 u8 reserved_at_200[0x140];
2700 u8 qkey_violation_counter[0x10];
2701 u8 reserved_at_350[0x430];
2702
2703 u8 promisc_uc[0x1];
2704 u8 promisc_mc[0x1];
2705 u8 promisc_all[0x1];
2706 u8 reserved_at_783[0x2];
2707 u8 allowed_list_type[0x3];
2708 u8 reserved_at_788[0xc];
2709 u8 allowed_list_size[0xc];
2710
2711 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2712
2713 u8 reserved_at_7e0[0x20];
2714
2715 u8 current_uc_mac_address[0][0x40];
2716 };
2717
2718 enum {
2719 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2720 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2721 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2722 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2723 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2724 };
2725
2726 struct mlx5_ifc_mkc_bits {
2727 u8 reserved_at_0[0x1];
2728 u8 free[0x1];
2729 u8 reserved_at_2[0x1];
2730 u8 access_mode_4_2[0x3];
2731 u8 reserved_at_6[0x7];
2732 u8 relaxed_ordering_write[0x1];
2733 u8 reserved_at_e[0x1];
2734 u8 small_fence_on_rdma_read_response[0x1];
2735 u8 umr_en[0x1];
2736 u8 a[0x1];
2737 u8 rw[0x1];
2738 u8 rr[0x1];
2739 u8 lw[0x1];
2740 u8 lr[0x1];
2741 u8 access_mode_1_0[0x2];
2742 u8 reserved_at_18[0x8];
2743
2744 u8 qpn[0x18];
2745 u8 mkey_7_0[0x8];
2746
2747 u8 reserved_at_40[0x20];
2748
2749 u8 length64[0x1];
2750 u8 bsf_en[0x1];
2751 u8 sync_umr[0x1];
2752 u8 reserved_at_63[0x2];
2753 u8 expected_sigerr_count[0x1];
2754 u8 reserved_at_66[0x1];
2755 u8 en_rinval[0x1];
2756 u8 pd[0x18];
2757
2758 u8 start_addr[0x40];
2759
2760 u8 len[0x40];
2761
2762 u8 bsf_octword_size[0x20];
2763
2764 u8 reserved_at_120[0x80];
2765
2766 u8 translations_octword_size[0x20];
2767
2768 u8 reserved_at_1c0[0x1b];
2769 u8 log_page_size[0x5];
2770
2771 u8 reserved_at_1e0[0x20];
2772 };
2773
2774 struct mlx5_ifc_pkey_bits {
2775 u8 reserved_at_0[0x10];
2776 u8 pkey[0x10];
2777 };
2778
2779 struct mlx5_ifc_array128_auto_bits {
2780 u8 array128_auto[16][0x8];
2781 };
2782
2783 struct mlx5_ifc_hca_vport_context_bits {
2784 u8 field_select[0x20];
2785
2786 u8 reserved_at_20[0xe0];
2787
2788 u8 sm_virt_aware[0x1];
2789 u8 has_smi[0x1];
2790 u8 has_raw[0x1];
2791 u8 grh_required[0x1];
2792 u8 reserved_at_104[0xc];
2793 u8 port_physical_state[0x4];
2794 u8 vport_state_policy[0x4];
2795 u8 port_state[0x4];
2796 u8 vport_state[0x4];
2797
2798 u8 reserved_at_120[0x20];
2799
2800 u8 system_image_guid[0x40];
2801
2802 u8 port_guid[0x40];
2803
2804 u8 node_guid[0x40];
2805
2806 u8 cap_mask1[0x20];
2807
2808 u8 cap_mask1_field_select[0x20];
2809
2810 u8 cap_mask2[0x20];
2811
2812 u8 cap_mask2_field_select[0x20];
2813
2814 u8 reserved_at_280[0x80];
2815
2816 u8 lid[0x10];
2817 u8 reserved_at_310[0x4];
2818 u8 init_type_reply[0x4];
2819 u8 lmc[0x3];
2820 u8 subnet_timeout[0x5];
2821
2822 u8 sm_lid[0x10];
2823 u8 sm_sl[0x4];
2824 u8 reserved_at_334[0xc];
2825
2826 u8 qkey_violation_counter[0x10];
2827 u8 pkey_violation_counter[0x10];
2828
2829 u8 reserved_at_360[0xca0];
2830 };
2831
2832 struct mlx5_ifc_esw_vport_context_bits {
2833 u8 reserved_at_0[0x3];
2834 u8 vport_svlan_strip[0x1];
2835 u8 vport_cvlan_strip[0x1];
2836 u8 vport_svlan_insert[0x1];
2837 u8 vport_cvlan_insert[0x2];
2838 u8 reserved_at_8[0x18];
2839
2840 u8 reserved_at_20[0x20];
2841
2842 u8 svlan_cfi[0x1];
2843 u8 svlan_pcp[0x3];
2844 u8 svlan_id[0xc];
2845 u8 cvlan_cfi[0x1];
2846 u8 cvlan_pcp[0x3];
2847 u8 cvlan_id[0xc];
2848
2849 u8 reserved_at_60[0x7a0];
2850 };
2851
2852 enum {
2853 MLX5_EQC_STATUS_OK = 0x0,
2854 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2855 };
2856
2857 enum {
2858 MLX5_EQC_ST_ARMED = 0x9,
2859 MLX5_EQC_ST_FIRED = 0xa,
2860 };
2861
2862 struct mlx5_ifc_eqc_bits {
2863 u8 status[0x4];
2864 u8 reserved_at_4[0x9];
2865 u8 ec[0x1];
2866 u8 oi[0x1];
2867 u8 reserved_at_f[0x5];
2868 u8 st[0x4];
2869 u8 reserved_at_18[0x8];
2870
2871 u8 reserved_at_20[0x20];
2872
2873 u8 reserved_at_40[0x14];
2874 u8 page_offset[0x6];
2875 u8 reserved_at_5a[0x6];
2876
2877 u8 reserved_at_60[0x3];
2878 u8 log_eq_size[0x5];
2879 u8 uar_page[0x18];
2880
2881 u8 reserved_at_80[0x20];
2882
2883 u8 reserved_at_a0[0x18];
2884 u8 intr[0x8];
2885
2886 u8 reserved_at_c0[0x3];
2887 u8 log_page_size[0x5];
2888 u8 reserved_at_c8[0x18];
2889
2890 u8 reserved_at_e0[0x60];
2891
2892 u8 reserved_at_140[0x8];
2893 u8 consumer_counter[0x18];
2894
2895 u8 reserved_at_160[0x8];
2896 u8 producer_counter[0x18];
2897
2898 u8 reserved_at_180[0x80];
2899 };
2900
2901 enum {
2902 MLX5_DCTC_STATE_ACTIVE = 0x0,
2903 MLX5_DCTC_STATE_DRAINING = 0x1,
2904 MLX5_DCTC_STATE_DRAINED = 0x2,
2905 };
2906
2907 enum {
2908 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2909 MLX5_DCTC_CS_RES_NA = 0x1,
2910 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2911 };
2912
2913 enum {
2914 MLX5_DCTC_MTU_256_BYTES = 0x1,
2915 MLX5_DCTC_MTU_512_BYTES = 0x2,
2916 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2917 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2918 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2919 };
2920
2921 struct mlx5_ifc_dctc_bits {
2922 u8 reserved_at_0[0x4];
2923 u8 state[0x4];
2924 u8 reserved_at_8[0x18];
2925
2926 u8 reserved_at_20[0x8];
2927 u8 user_index[0x18];
2928
2929 u8 reserved_at_40[0x8];
2930 u8 cqn[0x18];
2931
2932 u8 counter_set_id[0x8];
2933 u8 atomic_mode[0x4];
2934 u8 rre[0x1];
2935 u8 rwe[0x1];
2936 u8 rae[0x1];
2937 u8 atomic_like_write_en[0x1];
2938 u8 latency_sensitive[0x1];
2939 u8 rlky[0x1];
2940 u8 free_ar[0x1];
2941 u8 reserved_at_73[0xd];
2942
2943 u8 reserved_at_80[0x8];
2944 u8 cs_res[0x8];
2945 u8 reserved_at_90[0x3];
2946 u8 min_rnr_nak[0x5];
2947 u8 reserved_at_98[0x8];
2948
2949 u8 reserved_at_a0[0x8];
2950 u8 srqn_xrqn[0x18];
2951
2952 u8 reserved_at_c0[0x8];
2953 u8 pd[0x18];
2954
2955 u8 tclass[0x8];
2956 u8 reserved_at_e8[0x4];
2957 u8 flow_label[0x14];
2958
2959 u8 dc_access_key[0x40];
2960
2961 u8 reserved_at_140[0x5];
2962 u8 mtu[0x3];
2963 u8 port[0x8];
2964 u8 pkey_index[0x10];
2965
2966 u8 reserved_at_160[0x8];
2967 u8 my_addr_index[0x8];
2968 u8 reserved_at_170[0x8];
2969 u8 hop_limit[0x8];
2970
2971 u8 dc_access_key_violation_count[0x20];
2972
2973 u8 reserved_at_1a0[0x14];
2974 u8 dei_cfi[0x1];
2975 u8 eth_prio[0x3];
2976 u8 ecn[0x2];
2977 u8 dscp[0x6];
2978
2979 u8 reserved_at_1c0[0x40];
2980 };
2981
2982 enum {
2983 MLX5_CQC_STATUS_OK = 0x0,
2984 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2985 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2986 };
2987
2988 enum {
2989 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2990 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2991 };
2992
2993 enum {
2994 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2995 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2996 MLX5_CQC_ST_FIRED = 0xa,
2997 };
2998
2999 enum {
3000 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3001 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3002 MLX5_CQ_PERIOD_NUM_MODES
3003 };
3004
3005 struct mlx5_ifc_cqc_bits {
3006 u8 status[0x4];
3007 u8 reserved_at_4[0x4];
3008 u8 cqe_sz[0x3];
3009 u8 cc[0x1];
3010 u8 reserved_at_c[0x1];
3011 u8 scqe_break_moderation_en[0x1];
3012 u8 oi[0x1];
3013 u8 cq_period_mode[0x2];
3014 u8 cqe_comp_en[0x1];
3015 u8 mini_cqe_res_format[0x2];
3016 u8 st[0x4];
3017 u8 reserved_at_18[0x8];
3018
3019 u8 reserved_at_20[0x20];
3020
3021 u8 reserved_at_40[0x14];
3022 u8 page_offset[0x6];
3023 u8 reserved_at_5a[0x6];
3024
3025 u8 reserved_at_60[0x3];
3026 u8 log_cq_size[0x5];
3027 u8 uar_page[0x18];
3028
3029 u8 reserved_at_80[0x4];
3030 u8 cq_period[0xc];
3031 u8 cq_max_count[0x10];
3032
3033 u8 reserved_at_a0[0x18];
3034 u8 c_eqn[0x8];
3035
3036 u8 reserved_at_c0[0x3];
3037 u8 log_page_size[0x5];
3038 u8 reserved_at_c8[0x18];
3039
3040 u8 reserved_at_e0[0x20];
3041
3042 u8 reserved_at_100[0x8];
3043 u8 last_notified_index[0x18];
3044
3045 u8 reserved_at_120[0x8];
3046 u8 last_solicit_index[0x18];
3047
3048 u8 reserved_at_140[0x8];
3049 u8 consumer_counter[0x18];
3050
3051 u8 reserved_at_160[0x8];
3052 u8 producer_counter[0x18];
3053
3054 u8 reserved_at_180[0x40];
3055
3056 u8 dbr_addr[0x40];
3057 };
3058
3059 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3060 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3061 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3062 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3063 u8 reserved_at_0[0x800];
3064 };
3065
3066 struct mlx5_ifc_query_adapter_param_block_bits {
3067 u8 reserved_at_0[0xc0];
3068
3069 u8 reserved_at_c0[0x8];
3070 u8 ieee_vendor_id[0x18];
3071
3072 u8 reserved_at_e0[0x10];
3073 u8 vsd_vendor_id[0x10];
3074
3075 u8 vsd[208][0x8];
3076
3077 u8 vsd_contd_psid[16][0x8];
3078 };
3079
3080 enum {
3081 MLX5_XRQC_STATE_GOOD = 0x0,
3082 MLX5_XRQC_STATE_ERROR = 0x1,
3083 };
3084
3085 enum {
3086 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3087 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3088 };
3089
3090 enum {
3091 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3092 };
3093
3094 struct mlx5_ifc_tag_matching_topology_context_bits {
3095 u8 log_matching_list_sz[0x4];
3096 u8 reserved_at_4[0xc];
3097 u8 append_next_index[0x10];
3098
3099 u8 sw_phase_cnt[0x10];
3100 u8 hw_phase_cnt[0x10];
3101
3102 u8 reserved_at_40[0x40];
3103 };
3104
3105 struct mlx5_ifc_xrqc_bits {
3106 u8 state[0x4];
3107 u8 rlkey[0x1];
3108 u8 reserved_at_5[0xf];
3109 u8 topology[0x4];
3110 u8 reserved_at_18[0x4];
3111 u8 offload[0x4];
3112
3113 u8 reserved_at_20[0x8];
3114 u8 user_index[0x18];
3115
3116 u8 reserved_at_40[0x8];
3117 u8 cqn[0x18];
3118
3119 u8 reserved_at_60[0xa0];
3120
3121 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3122
3123 u8 reserved_at_180[0x280];
3124
3125 struct mlx5_ifc_wq_bits wq;
3126 };
3127
3128 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3129 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3130 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3131 u8 reserved_at_0[0x20];
3132 };
3133
3134 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3135 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3136 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3137 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3138 u8 reserved_at_0[0x20];
3139 };
3140
3141 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3142 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3143 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3144 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3145 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3146 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3147 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3148 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3149 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3150 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3151 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3152 u8 reserved_at_0[0x7c0];
3153 };
3154
3155 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3156 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3157 u8 reserved_at_0[0x7c0];
3158 };
3159
3160 union mlx5_ifc_event_auto_bits {
3161 struct mlx5_ifc_comp_event_bits comp_event;
3162 struct mlx5_ifc_dct_events_bits dct_events;
3163 struct mlx5_ifc_qp_events_bits qp_events;
3164 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3165 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3166 struct mlx5_ifc_cq_error_bits cq_error;
3167 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3168 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3169 struct mlx5_ifc_gpio_event_bits gpio_event;
3170 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3171 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3172 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3173 u8 reserved_at_0[0xe0];
3174 };
3175
3176 struct mlx5_ifc_health_buffer_bits {
3177 u8 reserved_at_0[0x100];
3178
3179 u8 assert_existptr[0x20];
3180
3181 u8 assert_callra[0x20];
3182
3183 u8 reserved_at_140[0x40];
3184
3185 u8 fw_version[0x20];
3186
3187 u8 hw_id[0x20];
3188
3189 u8 reserved_at_1c0[0x20];
3190
3191 u8 irisc_index[0x8];
3192 u8 synd[0x8];
3193 u8 ext_synd[0x10];
3194 };
3195
3196 struct mlx5_ifc_register_loopback_control_bits {
3197 u8 no_lb[0x1];
3198 u8 reserved_at_1[0x7];
3199 u8 port[0x8];
3200 u8 reserved_at_10[0x10];
3201
3202 u8 reserved_at_20[0x60];
3203 };
3204
3205 struct mlx5_ifc_vport_tc_element_bits {
3206 u8 traffic_class[0x4];
3207 u8 reserved_at_4[0xc];
3208 u8 vport_number[0x10];
3209 };
3210
3211 struct mlx5_ifc_vport_element_bits {
3212 u8 reserved_at_0[0x10];
3213 u8 vport_number[0x10];
3214 };
3215
3216 enum {
3217 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3218 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3219 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3220 };
3221
3222 struct mlx5_ifc_tsar_element_bits {
3223 u8 reserved_at_0[0x8];
3224 u8 tsar_type[0x8];
3225 u8 reserved_at_10[0x10];
3226 };
3227
3228 enum {
3229 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3230 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3231 };
3232
3233 struct mlx5_ifc_teardown_hca_out_bits {
3234 u8 status[0x8];
3235 u8 reserved_at_8[0x18];
3236
3237 u8 syndrome[0x20];
3238
3239 u8 reserved_at_40[0x3f];
3240
3241 u8 force_state[0x1];
3242 };
3243
3244 enum {
3245 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3246 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3247 };
3248
3249 struct mlx5_ifc_teardown_hca_in_bits {
3250 u8 opcode[0x10];
3251 u8 reserved_at_10[0x10];
3252
3253 u8 reserved_at_20[0x10];
3254 u8 op_mod[0x10];
3255
3256 u8 reserved_at_40[0x10];
3257 u8 profile[0x10];
3258
3259 u8 reserved_at_60[0x20];
3260 };
3261
3262 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3263 u8 status[0x8];
3264 u8 reserved_at_8[0x18];
3265
3266 u8 syndrome[0x20];
3267
3268 u8 reserved_at_40[0x40];
3269 };
3270
3271 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3272 u8 opcode[0x10];
3273 u8 reserved_at_10[0x10];
3274
3275 u8 reserved_at_20[0x10];
3276 u8 op_mod[0x10];
3277
3278 u8 reserved_at_40[0x8];
3279 u8 qpn[0x18];
3280
3281 u8 reserved_at_60[0x20];
3282
3283 u8 opt_param_mask[0x20];
3284
3285 u8 reserved_at_a0[0x20];
3286
3287 struct mlx5_ifc_qpc_bits qpc;
3288
3289 u8 reserved_at_800[0x80];
3290 };
3291
3292 struct mlx5_ifc_sqd2rts_qp_out_bits {
3293 u8 status[0x8];
3294 u8 reserved_at_8[0x18];
3295
3296 u8 syndrome[0x20];
3297
3298 u8 reserved_at_40[0x40];
3299 };
3300
3301 struct mlx5_ifc_sqd2rts_qp_in_bits {
3302 u8 opcode[0x10];
3303 u8 reserved_at_10[0x10];
3304
3305 u8 reserved_at_20[0x10];
3306 u8 op_mod[0x10];
3307
3308 u8 reserved_at_40[0x8];
3309 u8 qpn[0x18];
3310
3311 u8 reserved_at_60[0x20];
3312
3313 u8 opt_param_mask[0x20];
3314
3315 u8 reserved_at_a0[0x20];
3316
3317 struct mlx5_ifc_qpc_bits qpc;
3318
3319 u8 reserved_at_800[0x80];
3320 };
3321
3322 struct mlx5_ifc_set_roce_address_out_bits {
3323 u8 status[0x8];
3324 u8 reserved_at_8[0x18];
3325
3326 u8 syndrome[0x20];
3327
3328 u8 reserved_at_40[0x40];
3329 };
3330
3331 struct mlx5_ifc_set_roce_address_in_bits {
3332 u8 opcode[0x10];
3333 u8 reserved_at_10[0x10];
3334
3335 u8 reserved_at_20[0x10];
3336 u8 op_mod[0x10];
3337
3338 u8 roce_address_index[0x10];
3339 u8 reserved_at_50[0xc];
3340 u8 vhca_port_num[0x4];
3341
3342 u8 reserved_at_60[0x20];
3343
3344 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3345 };
3346
3347 struct mlx5_ifc_set_mad_demux_out_bits {
3348 u8 status[0x8];
3349 u8 reserved_at_8[0x18];
3350
3351 u8 syndrome[0x20];
3352
3353 u8 reserved_at_40[0x40];
3354 };
3355
3356 enum {
3357 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3358 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3359 };
3360
3361 struct mlx5_ifc_set_mad_demux_in_bits {
3362 u8 opcode[0x10];
3363 u8 reserved_at_10[0x10];
3364
3365 u8 reserved_at_20[0x10];
3366 u8 op_mod[0x10];
3367
3368 u8 reserved_at_40[0x20];
3369
3370 u8 reserved_at_60[0x6];
3371 u8 demux_mode[0x2];
3372 u8 reserved_at_68[0x18];
3373 };
3374
3375 struct mlx5_ifc_set_l2_table_entry_out_bits {
3376 u8 status[0x8];
3377 u8 reserved_at_8[0x18];
3378
3379 u8 syndrome[0x20];
3380
3381 u8 reserved_at_40[0x40];
3382 };
3383
3384 struct mlx5_ifc_set_l2_table_entry_in_bits {
3385 u8 opcode[0x10];
3386 u8 reserved_at_10[0x10];
3387
3388 u8 reserved_at_20[0x10];
3389 u8 op_mod[0x10];
3390
3391 u8 reserved_at_40[0x60];
3392
3393 u8 reserved_at_a0[0x8];
3394 u8 table_index[0x18];
3395
3396 u8 reserved_at_c0[0x20];
3397
3398 u8 reserved_at_e0[0x13];
3399 u8 vlan_valid[0x1];
3400 u8 vlan[0xc];
3401
3402 struct mlx5_ifc_mac_address_layout_bits mac_address;
3403
3404 u8 reserved_at_140[0xc0];
3405 };
3406
3407 struct mlx5_ifc_set_issi_out_bits {
3408 u8 status[0x8];
3409 u8 reserved_at_8[0x18];
3410
3411 u8 syndrome[0x20];
3412
3413 u8 reserved_at_40[0x40];
3414 };
3415
3416 struct mlx5_ifc_set_issi_in_bits {
3417 u8 opcode[0x10];
3418 u8 reserved_at_10[0x10];
3419
3420 u8 reserved_at_20[0x10];
3421 u8 op_mod[0x10];
3422
3423 u8 reserved_at_40[0x10];
3424 u8 current_issi[0x10];
3425
3426 u8 reserved_at_60[0x20];
3427 };
3428
3429 struct mlx5_ifc_set_hca_cap_out_bits {
3430 u8 status[0x8];
3431 u8 reserved_at_8[0x18];
3432
3433 u8 syndrome[0x20];
3434
3435 u8 reserved_at_40[0x40];
3436 };
3437
3438 struct mlx5_ifc_set_hca_cap_in_bits {
3439 u8 opcode[0x10];
3440 u8 reserved_at_10[0x10];
3441
3442 u8 reserved_at_20[0x10];
3443 u8 op_mod[0x10];
3444
3445 u8 reserved_at_40[0x40];
3446
3447 union mlx5_ifc_hca_cap_union_bits capability;
3448 };
3449
3450 enum {
3451 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3452 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3453 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3454 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3455 };
3456
3457 struct mlx5_ifc_set_fte_out_bits {
3458 u8 status[0x8];
3459 u8 reserved_at_8[0x18];
3460
3461 u8 syndrome[0x20];
3462
3463 u8 reserved_at_40[0x40];
3464 };
3465
3466 struct mlx5_ifc_set_fte_in_bits {
3467 u8 opcode[0x10];
3468 u8 reserved_at_10[0x10];
3469
3470 u8 reserved_at_20[0x10];
3471 u8 op_mod[0x10];
3472
3473 u8 other_vport[0x1];
3474 u8 reserved_at_41[0xf];
3475 u8 vport_number[0x10];
3476
3477 u8 reserved_at_60[0x20];
3478
3479 u8 table_type[0x8];
3480 u8 reserved_at_88[0x18];
3481
3482 u8 reserved_at_a0[0x8];
3483 u8 table_id[0x18];
3484
3485 u8 reserved_at_c0[0x18];
3486 u8 modify_enable_mask[0x8];
3487
3488 u8 reserved_at_e0[0x20];
3489
3490 u8 flow_index[0x20];
3491
3492 u8 reserved_at_120[0xe0];
3493
3494 struct mlx5_ifc_flow_context_bits flow_context;
3495 };
3496
3497 struct mlx5_ifc_rts2rts_qp_out_bits {
3498 u8 status[0x8];
3499 u8 reserved_at_8[0x18];
3500
3501 u8 syndrome[0x20];
3502
3503 u8 reserved_at_40[0x40];
3504 };
3505
3506 struct mlx5_ifc_rts2rts_qp_in_bits {
3507 u8 opcode[0x10];
3508 u8 reserved_at_10[0x10];
3509
3510 u8 reserved_at_20[0x10];
3511 u8 op_mod[0x10];
3512
3513 u8 reserved_at_40[0x8];
3514 u8 qpn[0x18];
3515
3516 u8 reserved_at_60[0x20];
3517
3518 u8 opt_param_mask[0x20];
3519
3520 u8 reserved_at_a0[0x20];
3521
3522 struct mlx5_ifc_qpc_bits qpc;
3523
3524 u8 reserved_at_800[0x80];
3525 };
3526
3527 struct mlx5_ifc_rtr2rts_qp_out_bits {
3528 u8 status[0x8];
3529 u8 reserved_at_8[0x18];
3530
3531 u8 syndrome[0x20];
3532
3533 u8 reserved_at_40[0x40];
3534 };
3535
3536 struct mlx5_ifc_rtr2rts_qp_in_bits {
3537 u8 opcode[0x10];
3538 u8 reserved_at_10[0x10];
3539
3540 u8 reserved_at_20[0x10];
3541 u8 op_mod[0x10];
3542
3543 u8 reserved_at_40[0x8];
3544 u8 qpn[0x18];
3545
3546 u8 reserved_at_60[0x20];
3547
3548 u8 opt_param_mask[0x20];
3549
3550 u8 reserved_at_a0[0x20];
3551
3552 struct mlx5_ifc_qpc_bits qpc;
3553
3554 u8 reserved_at_800[0x80];
3555 };
3556
3557 struct mlx5_ifc_rst2init_qp_out_bits {
3558 u8 status[0x8];
3559 u8 reserved_at_8[0x18];
3560
3561 u8 syndrome[0x20];
3562
3563 u8 reserved_at_40[0x40];
3564 };
3565
3566 struct mlx5_ifc_rst2init_qp_in_bits {
3567 u8 opcode[0x10];
3568 u8 reserved_at_10[0x10];
3569
3570 u8 reserved_at_20[0x10];
3571 u8 op_mod[0x10];
3572
3573 u8 reserved_at_40[0x8];
3574 u8 qpn[0x18];
3575
3576 u8 reserved_at_60[0x20];
3577
3578 u8 opt_param_mask[0x20];
3579
3580 u8 reserved_at_a0[0x20];
3581
3582 struct mlx5_ifc_qpc_bits qpc;
3583
3584 u8 reserved_at_800[0x80];
3585 };
3586
3587 struct mlx5_ifc_query_xrq_out_bits {
3588 u8 status[0x8];
3589 u8 reserved_at_8[0x18];
3590
3591 u8 syndrome[0x20];
3592
3593 u8 reserved_at_40[0x40];
3594
3595 struct mlx5_ifc_xrqc_bits xrq_context;
3596 };
3597
3598 struct mlx5_ifc_query_xrq_in_bits {
3599 u8 opcode[0x10];
3600 u8 reserved_at_10[0x10];
3601
3602 u8 reserved_at_20[0x10];
3603 u8 op_mod[0x10];
3604
3605 u8 reserved_at_40[0x8];
3606 u8 xrqn[0x18];
3607
3608 u8 reserved_at_60[0x20];
3609 };
3610
3611 struct mlx5_ifc_query_xrc_srq_out_bits {
3612 u8 status[0x8];
3613 u8 reserved_at_8[0x18];
3614
3615 u8 syndrome[0x20];
3616
3617 u8 reserved_at_40[0x40];
3618
3619 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3620
3621 u8 reserved_at_280[0x600];
3622
3623 u8 pas[0][0x40];
3624 };
3625
3626 struct mlx5_ifc_query_xrc_srq_in_bits {
3627 u8 opcode[0x10];
3628 u8 reserved_at_10[0x10];
3629
3630 u8 reserved_at_20[0x10];
3631 u8 op_mod[0x10];
3632
3633 u8 reserved_at_40[0x8];
3634 u8 xrc_srqn[0x18];
3635
3636 u8 reserved_at_60[0x20];
3637 };
3638
3639 enum {
3640 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3641 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3642 };
3643
3644 struct mlx5_ifc_query_vport_state_out_bits {
3645 u8 status[0x8];
3646 u8 reserved_at_8[0x18];
3647
3648 u8 syndrome[0x20];
3649
3650 u8 reserved_at_40[0x20];
3651
3652 u8 reserved_at_60[0x18];
3653 u8 admin_state[0x4];
3654 u8 state[0x4];
3655 };
3656
3657 enum {
3658 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3659 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3660 };
3661
3662 struct mlx5_ifc_query_vport_state_in_bits {
3663 u8 opcode[0x10];
3664 u8 reserved_at_10[0x10];
3665
3666 u8 reserved_at_20[0x10];
3667 u8 op_mod[0x10];
3668
3669 u8 other_vport[0x1];
3670 u8 reserved_at_41[0xf];
3671 u8 vport_number[0x10];
3672
3673 u8 reserved_at_60[0x20];
3674 };
3675
3676 struct mlx5_ifc_query_vport_counter_out_bits {
3677 u8 status[0x8];
3678 u8 reserved_at_8[0x18];
3679
3680 u8 syndrome[0x20];
3681
3682 u8 reserved_at_40[0x40];
3683
3684 struct mlx5_ifc_traffic_counter_bits received_errors;
3685
3686 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3687
3688 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3689
3690 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3691
3692 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3693
3694 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3695
3696 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3697
3698 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3699
3700 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3701
3702 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3703
3704 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3705
3706 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3707
3708 u8 reserved_at_680[0xa00];
3709 };
3710
3711 enum {
3712 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3713 };
3714
3715 struct mlx5_ifc_query_vport_counter_in_bits {
3716 u8 opcode[0x10];
3717 u8 reserved_at_10[0x10];
3718
3719 u8 reserved_at_20[0x10];
3720 u8 op_mod[0x10];
3721
3722 u8 other_vport[0x1];
3723 u8 reserved_at_41[0xb];
3724 u8 port_num[0x4];
3725 u8 vport_number[0x10];
3726
3727 u8 reserved_at_60[0x60];
3728
3729 u8 clear[0x1];
3730 u8 reserved_at_c1[0x1f];
3731
3732 u8 reserved_at_e0[0x20];
3733 };
3734
3735 struct mlx5_ifc_query_tis_out_bits {
3736 u8 status[0x8];
3737 u8 reserved_at_8[0x18];
3738
3739 u8 syndrome[0x20];
3740
3741 u8 reserved_at_40[0x40];
3742
3743 struct mlx5_ifc_tisc_bits tis_context;
3744 };
3745
3746 struct mlx5_ifc_query_tis_in_bits {
3747 u8 opcode[0x10];
3748 u8 reserved_at_10[0x10];
3749
3750 u8 reserved_at_20[0x10];
3751 u8 op_mod[0x10];
3752
3753 u8 reserved_at_40[0x8];
3754 u8 tisn[0x18];
3755
3756 u8 reserved_at_60[0x20];
3757 };
3758
3759 struct mlx5_ifc_query_tir_out_bits {
3760 u8 status[0x8];
3761 u8 reserved_at_8[0x18];
3762
3763 u8 syndrome[0x20];
3764
3765 u8 reserved_at_40[0xc0];
3766
3767 struct mlx5_ifc_tirc_bits tir_context;
3768 };
3769
3770 struct mlx5_ifc_query_tir_in_bits {
3771 u8 opcode[0x10];
3772 u8 reserved_at_10[0x10];
3773
3774 u8 reserved_at_20[0x10];
3775 u8 op_mod[0x10];
3776
3777 u8 reserved_at_40[0x8];
3778 u8 tirn[0x18];
3779
3780 u8 reserved_at_60[0x20];
3781 };
3782
3783 struct mlx5_ifc_query_srq_out_bits {
3784 u8 status[0x8];
3785 u8 reserved_at_8[0x18];
3786
3787 u8 syndrome[0x20];
3788
3789 u8 reserved_at_40[0x40];
3790
3791 struct mlx5_ifc_srqc_bits srq_context_entry;
3792
3793 u8 reserved_at_280[0x600];
3794
3795 u8 pas[0][0x40];
3796 };
3797
3798 struct mlx5_ifc_query_srq_in_bits {
3799 u8 opcode[0x10];
3800 u8 reserved_at_10[0x10];
3801
3802 u8 reserved_at_20[0x10];
3803 u8 op_mod[0x10];
3804
3805 u8 reserved_at_40[0x8];
3806 u8 srqn[0x18];
3807
3808 u8 reserved_at_60[0x20];
3809 };
3810
3811 struct mlx5_ifc_query_sq_out_bits {
3812 u8 status[0x8];
3813 u8 reserved_at_8[0x18];
3814
3815 u8 syndrome[0x20];
3816
3817 u8 reserved_at_40[0xc0];
3818
3819 struct mlx5_ifc_sqc_bits sq_context;
3820 };
3821
3822 struct mlx5_ifc_query_sq_in_bits {
3823 u8 opcode[0x10];
3824 u8 reserved_at_10[0x10];
3825
3826 u8 reserved_at_20[0x10];
3827 u8 op_mod[0x10];
3828
3829 u8 reserved_at_40[0x8];
3830 u8 sqn[0x18];
3831
3832 u8 reserved_at_60[0x20];
3833 };
3834
3835 struct mlx5_ifc_query_special_contexts_out_bits {
3836 u8 status[0x8];
3837 u8 reserved_at_8[0x18];
3838
3839 u8 syndrome[0x20];
3840
3841 u8 dump_fill_mkey[0x20];
3842
3843 u8 resd_lkey[0x20];
3844
3845 u8 null_mkey[0x20];
3846
3847 u8 reserved_at_a0[0x60];
3848 };
3849
3850 struct mlx5_ifc_query_special_contexts_in_bits {
3851 u8 opcode[0x10];
3852 u8 reserved_at_10[0x10];
3853
3854 u8 reserved_at_20[0x10];
3855 u8 op_mod[0x10];
3856
3857 u8 reserved_at_40[0x40];
3858 };
3859
3860 struct mlx5_ifc_query_scheduling_element_out_bits {
3861 u8 opcode[0x10];
3862 u8 reserved_at_10[0x10];
3863
3864 u8 reserved_at_20[0x10];
3865 u8 op_mod[0x10];
3866
3867 u8 reserved_at_40[0xc0];
3868
3869 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3870
3871 u8 reserved_at_300[0x100];
3872 };
3873
3874 enum {
3875 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3876 };
3877
3878 struct mlx5_ifc_query_scheduling_element_in_bits {
3879 u8 opcode[0x10];
3880 u8 reserved_at_10[0x10];
3881
3882 u8 reserved_at_20[0x10];
3883 u8 op_mod[0x10];
3884
3885 u8 scheduling_hierarchy[0x8];
3886 u8 reserved_at_48[0x18];
3887
3888 u8 scheduling_element_id[0x20];
3889
3890 u8 reserved_at_80[0x180];
3891 };
3892
3893 struct mlx5_ifc_query_rqt_out_bits {
3894 u8 status[0x8];
3895 u8 reserved_at_8[0x18];
3896
3897 u8 syndrome[0x20];
3898
3899 u8 reserved_at_40[0xc0];
3900
3901 struct mlx5_ifc_rqtc_bits rqt_context;
3902 };
3903
3904 struct mlx5_ifc_query_rqt_in_bits {
3905 u8 opcode[0x10];
3906 u8 reserved_at_10[0x10];
3907
3908 u8 reserved_at_20[0x10];
3909 u8 op_mod[0x10];
3910
3911 u8 reserved_at_40[0x8];
3912 u8 rqtn[0x18];
3913
3914 u8 reserved_at_60[0x20];
3915 };
3916
3917 struct mlx5_ifc_query_rq_out_bits {
3918 u8 status[0x8];
3919 u8 reserved_at_8[0x18];
3920
3921 u8 syndrome[0x20];
3922
3923 u8 reserved_at_40[0xc0];
3924
3925 struct mlx5_ifc_rqc_bits rq_context;
3926 };
3927
3928 struct mlx5_ifc_query_rq_in_bits {
3929 u8 opcode[0x10];
3930 u8 reserved_at_10[0x10];
3931
3932 u8 reserved_at_20[0x10];
3933 u8 op_mod[0x10];
3934
3935 u8 reserved_at_40[0x8];
3936 u8 rqn[0x18];
3937
3938 u8 reserved_at_60[0x20];
3939 };
3940
3941 struct mlx5_ifc_query_roce_address_out_bits {
3942 u8 status[0x8];
3943 u8 reserved_at_8[0x18];
3944
3945 u8 syndrome[0x20];
3946
3947 u8 reserved_at_40[0x40];
3948
3949 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3950 };
3951
3952 struct mlx5_ifc_query_roce_address_in_bits {
3953 u8 opcode[0x10];
3954 u8 reserved_at_10[0x10];
3955
3956 u8 reserved_at_20[0x10];
3957 u8 op_mod[0x10];
3958
3959 u8 roce_address_index[0x10];
3960 u8 reserved_at_50[0xc];
3961 u8 vhca_port_num[0x4];
3962
3963 u8 reserved_at_60[0x20];
3964 };
3965
3966 struct mlx5_ifc_query_rmp_out_bits {
3967 u8 status[0x8];
3968 u8 reserved_at_8[0x18];
3969
3970 u8 syndrome[0x20];
3971
3972 u8 reserved_at_40[0xc0];
3973
3974 struct mlx5_ifc_rmpc_bits rmp_context;
3975 };
3976
3977 struct mlx5_ifc_query_rmp_in_bits {
3978 u8 opcode[0x10];
3979 u8 reserved_at_10[0x10];
3980
3981 u8 reserved_at_20[0x10];
3982 u8 op_mod[0x10];
3983
3984 u8 reserved_at_40[0x8];
3985 u8 rmpn[0x18];
3986
3987 u8 reserved_at_60[0x20];
3988 };
3989
3990 struct mlx5_ifc_query_qp_out_bits {
3991 u8 status[0x8];
3992 u8 reserved_at_8[0x18];
3993
3994 u8 syndrome[0x20];
3995
3996 u8 reserved_at_40[0x40];
3997
3998 u8 opt_param_mask[0x20];
3999
4000 u8 reserved_at_a0[0x20];
4001
4002 struct mlx5_ifc_qpc_bits qpc;
4003
4004 u8 reserved_at_800[0x80];
4005
4006 u8 pas[0][0x40];
4007 };
4008
4009 struct mlx5_ifc_query_qp_in_bits {
4010 u8 opcode[0x10];
4011 u8 reserved_at_10[0x10];
4012
4013 u8 reserved_at_20[0x10];
4014 u8 op_mod[0x10];
4015
4016 u8 reserved_at_40[0x8];
4017 u8 qpn[0x18];
4018
4019 u8 reserved_at_60[0x20];
4020 };
4021
4022 struct mlx5_ifc_query_q_counter_out_bits {
4023 u8 status[0x8];
4024 u8 reserved_at_8[0x18];
4025
4026 u8 syndrome[0x20];
4027
4028 u8 reserved_at_40[0x40];
4029
4030 u8 rx_write_requests[0x20];
4031
4032 u8 reserved_at_a0[0x20];
4033
4034 u8 rx_read_requests[0x20];
4035
4036 u8 reserved_at_e0[0x20];
4037
4038 u8 rx_atomic_requests[0x20];
4039
4040 u8 reserved_at_120[0x20];
4041
4042 u8 rx_dct_connect[0x20];
4043
4044 u8 reserved_at_160[0x20];
4045
4046 u8 out_of_buffer[0x20];
4047
4048 u8 reserved_at_1a0[0x20];
4049
4050 u8 out_of_sequence[0x20];
4051
4052 u8 reserved_at_1e0[0x20];
4053
4054 u8 duplicate_request[0x20];
4055
4056 u8 reserved_at_220[0x20];
4057
4058 u8 rnr_nak_retry_err[0x20];
4059
4060 u8 reserved_at_260[0x20];
4061
4062 u8 packet_seq_err[0x20];
4063
4064 u8 reserved_at_2a0[0x20];
4065
4066 u8 implied_nak_seq_err[0x20];
4067
4068 u8 reserved_at_2e0[0x20];
4069
4070 u8 local_ack_timeout_err[0x20];
4071
4072 u8 reserved_at_320[0xa0];
4073
4074 u8 resp_local_length_error[0x20];
4075
4076 u8 req_local_length_error[0x20];
4077
4078 u8 resp_local_qp_error[0x20];
4079
4080 u8 local_operation_error[0x20];
4081
4082 u8 resp_local_protection[0x20];
4083
4084 u8 req_local_protection[0x20];
4085
4086 u8 resp_cqe_error[0x20];
4087
4088 u8 req_cqe_error[0x20];
4089
4090 u8 req_mw_binding[0x20];
4091
4092 u8 req_bad_response[0x20];
4093
4094 u8 req_remote_invalid_request[0x20];
4095
4096 u8 resp_remote_invalid_request[0x20];
4097
4098 u8 req_remote_access_errors[0x20];
4099
4100 u8 resp_remote_access_errors[0x20];
4101
4102 u8 req_remote_operation_errors[0x20];
4103
4104 u8 req_transport_retries_exceeded[0x20];
4105
4106 u8 cq_overflow[0x20];
4107
4108 u8 resp_cqe_flush_error[0x20];
4109
4110 u8 req_cqe_flush_error[0x20];
4111
4112 u8 reserved_at_620[0x1e0];
4113 };
4114
4115 struct mlx5_ifc_query_q_counter_in_bits {
4116 u8 opcode[0x10];
4117 u8 reserved_at_10[0x10];
4118
4119 u8 reserved_at_20[0x10];
4120 u8 op_mod[0x10];
4121
4122 u8 reserved_at_40[0x80];
4123
4124 u8 clear[0x1];
4125 u8 reserved_at_c1[0x1f];
4126
4127 u8 reserved_at_e0[0x18];
4128 u8 counter_set_id[0x8];
4129 };
4130
4131 struct mlx5_ifc_query_pages_out_bits {
4132 u8 status[0x8];
4133 u8 reserved_at_8[0x18];
4134
4135 u8 syndrome[0x20];
4136
4137 u8 reserved_at_40[0x10];
4138 u8 function_id[0x10];
4139
4140 u8 num_pages[0x20];
4141 };
4142
4143 enum {
4144 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4145 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4146 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4147 };
4148
4149 struct mlx5_ifc_query_pages_in_bits {
4150 u8 opcode[0x10];
4151 u8 reserved_at_10[0x10];
4152
4153 u8 reserved_at_20[0x10];
4154 u8 op_mod[0x10];
4155
4156 u8 reserved_at_40[0x10];
4157 u8 function_id[0x10];
4158
4159 u8 reserved_at_60[0x20];
4160 };
4161
4162 struct mlx5_ifc_query_nic_vport_context_out_bits {
4163 u8 status[0x8];
4164 u8 reserved_at_8[0x18];
4165
4166 u8 syndrome[0x20];
4167
4168 u8 reserved_at_40[0x40];
4169
4170 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4171 };
4172
4173 struct mlx5_ifc_query_nic_vport_context_in_bits {
4174 u8 opcode[0x10];
4175 u8 reserved_at_10[0x10];
4176
4177 u8 reserved_at_20[0x10];
4178 u8 op_mod[0x10];
4179
4180 u8 other_vport[0x1];
4181 u8 reserved_at_41[0xf];
4182 u8 vport_number[0x10];
4183
4184 u8 reserved_at_60[0x5];
4185 u8 allowed_list_type[0x3];
4186 u8 reserved_at_68[0x18];
4187 };
4188
4189 struct mlx5_ifc_query_mkey_out_bits {
4190 u8 status[0x8];
4191 u8 reserved_at_8[0x18];
4192
4193 u8 syndrome[0x20];
4194
4195 u8 reserved_at_40[0x40];
4196
4197 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4198
4199 u8 reserved_at_280[0x600];
4200
4201 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4202
4203 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4204 };
4205
4206 struct mlx5_ifc_query_mkey_in_bits {
4207 u8 opcode[0x10];
4208 u8 reserved_at_10[0x10];
4209
4210 u8 reserved_at_20[0x10];
4211 u8 op_mod[0x10];
4212
4213 u8 reserved_at_40[0x8];
4214 u8 mkey_index[0x18];
4215
4216 u8 pg_access[0x1];
4217 u8 reserved_at_61[0x1f];
4218 };
4219
4220 struct mlx5_ifc_query_mad_demux_out_bits {
4221 u8 status[0x8];
4222 u8 reserved_at_8[0x18];
4223
4224 u8 syndrome[0x20];
4225
4226 u8 reserved_at_40[0x40];
4227
4228 u8 mad_dumux_parameters_block[0x20];
4229 };
4230
4231 struct mlx5_ifc_query_mad_demux_in_bits {
4232 u8 opcode[0x10];
4233 u8 reserved_at_10[0x10];
4234
4235 u8 reserved_at_20[0x10];
4236 u8 op_mod[0x10];
4237
4238 u8 reserved_at_40[0x40];
4239 };
4240
4241 struct mlx5_ifc_query_l2_table_entry_out_bits {
4242 u8 status[0x8];
4243 u8 reserved_at_8[0x18];
4244
4245 u8 syndrome[0x20];
4246
4247 u8 reserved_at_40[0xa0];
4248
4249 u8 reserved_at_e0[0x13];
4250 u8 vlan_valid[0x1];
4251 u8 vlan[0xc];
4252
4253 struct mlx5_ifc_mac_address_layout_bits mac_address;
4254
4255 u8 reserved_at_140[0xc0];
4256 };
4257
4258 struct mlx5_ifc_query_l2_table_entry_in_bits {
4259 u8 opcode[0x10];
4260 u8 reserved_at_10[0x10];
4261
4262 u8 reserved_at_20[0x10];
4263 u8 op_mod[0x10];
4264
4265 u8 reserved_at_40[0x60];
4266
4267 u8 reserved_at_a0[0x8];
4268 u8 table_index[0x18];
4269
4270 u8 reserved_at_c0[0x140];
4271 };
4272
4273 struct mlx5_ifc_query_issi_out_bits {
4274 u8 status[0x8];
4275 u8 reserved_at_8[0x18];
4276
4277 u8 syndrome[0x20];
4278
4279 u8 reserved_at_40[0x10];
4280 u8 current_issi[0x10];
4281
4282 u8 reserved_at_60[0xa0];
4283
4284 u8 reserved_at_100[76][0x8];
4285 u8 supported_issi_dw0[0x20];
4286 };
4287
4288 struct mlx5_ifc_query_issi_in_bits {
4289 u8 opcode[0x10];
4290 u8 reserved_at_10[0x10];
4291
4292 u8 reserved_at_20[0x10];
4293 u8 op_mod[0x10];
4294
4295 u8 reserved_at_40[0x40];
4296 };
4297
4298 struct mlx5_ifc_set_driver_version_out_bits {
4299 u8 status[0x8];
4300 u8 reserved_0[0x18];
4301
4302 u8 syndrome[0x20];
4303 u8 reserved_1[0x40];
4304 };
4305
4306 struct mlx5_ifc_set_driver_version_in_bits {
4307 u8 opcode[0x10];
4308 u8 reserved_0[0x10];
4309
4310 u8 reserved_1[0x10];
4311 u8 op_mod[0x10];
4312
4313 u8 reserved_2[0x40];
4314 u8 driver_version[64][0x8];
4315 };
4316
4317 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4318 u8 status[0x8];
4319 u8 reserved_at_8[0x18];
4320
4321 u8 syndrome[0x20];
4322
4323 u8 reserved_at_40[0x40];
4324
4325 struct mlx5_ifc_pkey_bits pkey[0];
4326 };
4327
4328 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4329 u8 opcode[0x10];
4330 u8 reserved_at_10[0x10];
4331
4332 u8 reserved_at_20[0x10];
4333 u8 op_mod[0x10];
4334
4335 u8 other_vport[0x1];
4336 u8 reserved_at_41[0xb];
4337 u8 port_num[0x4];
4338 u8 vport_number[0x10];
4339
4340 u8 reserved_at_60[0x10];
4341 u8 pkey_index[0x10];
4342 };
4343
4344 enum {
4345 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4346 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4347 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4348 };
4349
4350 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4351 u8 status[0x8];
4352 u8 reserved_at_8[0x18];
4353
4354 u8 syndrome[0x20];
4355
4356 u8 reserved_at_40[0x20];
4357
4358 u8 gids_num[0x10];
4359 u8 reserved_at_70[0x10];
4360
4361 struct mlx5_ifc_array128_auto_bits gid[0];
4362 };
4363
4364 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4365 u8 opcode[0x10];
4366 u8 reserved_at_10[0x10];
4367
4368 u8 reserved_at_20[0x10];
4369 u8 op_mod[0x10];
4370
4371 u8 other_vport[0x1];
4372 u8 reserved_at_41[0xb];
4373 u8 port_num[0x4];
4374 u8 vport_number[0x10];
4375
4376 u8 reserved_at_60[0x10];
4377 u8 gid_index[0x10];
4378 };
4379
4380 struct mlx5_ifc_query_hca_vport_context_out_bits {
4381 u8 status[0x8];
4382 u8 reserved_at_8[0x18];
4383
4384 u8 syndrome[0x20];
4385
4386 u8 reserved_at_40[0x40];
4387
4388 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4389 };
4390
4391 struct mlx5_ifc_query_hca_vport_context_in_bits {
4392 u8 opcode[0x10];
4393 u8 reserved_at_10[0x10];
4394
4395 u8 reserved_at_20[0x10];
4396 u8 op_mod[0x10];
4397
4398 u8 other_vport[0x1];
4399 u8 reserved_at_41[0xb];
4400 u8 port_num[0x4];
4401 u8 vport_number[0x10];
4402
4403 u8 reserved_at_60[0x20];
4404 };
4405
4406 struct mlx5_ifc_query_hca_cap_out_bits {
4407 u8 status[0x8];
4408 u8 reserved_at_8[0x18];
4409
4410 u8 syndrome[0x20];
4411
4412 u8 reserved_at_40[0x40];
4413
4414 union mlx5_ifc_hca_cap_union_bits capability;
4415 };
4416
4417 struct mlx5_ifc_query_hca_cap_in_bits {
4418 u8 opcode[0x10];
4419 u8 reserved_at_10[0x10];
4420
4421 u8 reserved_at_20[0x10];
4422 u8 op_mod[0x10];
4423
4424 u8 reserved_at_40[0x40];
4425 };
4426
4427 struct mlx5_ifc_query_flow_table_out_bits {
4428 u8 status[0x8];
4429 u8 reserved_at_8[0x18];
4430
4431 u8 syndrome[0x20];
4432
4433 u8 reserved_at_40[0x80];
4434
4435 u8 reserved_at_c0[0x8];
4436 u8 level[0x8];
4437 u8 reserved_at_d0[0x8];
4438 u8 log_size[0x8];
4439
4440 u8 reserved_at_e0[0x120];
4441 };
4442
4443 struct mlx5_ifc_query_flow_table_in_bits {
4444 u8 opcode[0x10];
4445 u8 reserved_at_10[0x10];
4446
4447 u8 reserved_at_20[0x10];
4448 u8 op_mod[0x10];
4449
4450 u8 reserved_at_40[0x40];
4451
4452 u8 table_type[0x8];
4453 u8 reserved_at_88[0x18];
4454
4455 u8 reserved_at_a0[0x8];
4456 u8 table_id[0x18];
4457
4458 u8 reserved_at_c0[0x140];
4459 };
4460
4461 struct mlx5_ifc_query_fte_out_bits {
4462 u8 status[0x8];
4463 u8 reserved_at_8[0x18];
4464
4465 u8 syndrome[0x20];
4466
4467 u8 reserved_at_40[0x1c0];
4468
4469 struct mlx5_ifc_flow_context_bits flow_context;
4470 };
4471
4472 struct mlx5_ifc_query_fte_in_bits {
4473 u8 opcode[0x10];
4474 u8 reserved_at_10[0x10];
4475
4476 u8 reserved_at_20[0x10];
4477 u8 op_mod[0x10];
4478
4479 u8 reserved_at_40[0x40];
4480
4481 u8 table_type[0x8];
4482 u8 reserved_at_88[0x18];
4483
4484 u8 reserved_at_a0[0x8];
4485 u8 table_id[0x18];
4486
4487 u8 reserved_at_c0[0x40];
4488
4489 u8 flow_index[0x20];
4490
4491 u8 reserved_at_120[0xe0];
4492 };
4493
4494 enum {
4495 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4496 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4497 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4498 };
4499
4500 struct mlx5_ifc_query_flow_group_out_bits {
4501 u8 status[0x8];
4502 u8 reserved_at_8[0x18];
4503
4504 u8 syndrome[0x20];
4505
4506 u8 reserved_at_40[0xa0];
4507
4508 u8 start_flow_index[0x20];
4509
4510 u8 reserved_at_100[0x20];
4511
4512 u8 end_flow_index[0x20];
4513
4514 u8 reserved_at_140[0xa0];
4515
4516 u8 reserved_at_1e0[0x18];
4517 u8 match_criteria_enable[0x8];
4518
4519 struct mlx5_ifc_fte_match_param_bits match_criteria;
4520
4521 u8 reserved_at_1200[0xe00];
4522 };
4523
4524 struct mlx5_ifc_query_flow_group_in_bits {
4525 u8 opcode[0x10];
4526 u8 reserved_at_10[0x10];
4527
4528 u8 reserved_at_20[0x10];
4529 u8 op_mod[0x10];
4530
4531 u8 reserved_at_40[0x40];
4532
4533 u8 table_type[0x8];
4534 u8 reserved_at_88[0x18];
4535
4536 u8 reserved_at_a0[0x8];
4537 u8 table_id[0x18];
4538
4539 u8 group_id[0x20];
4540
4541 u8 reserved_at_e0[0x120];
4542 };
4543
4544 struct mlx5_ifc_query_flow_counter_out_bits {
4545 u8 status[0x8];
4546 u8 reserved_at_8[0x18];
4547
4548 u8 syndrome[0x20];
4549
4550 u8 reserved_at_40[0x40];
4551
4552 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4553 };
4554
4555 struct mlx5_ifc_query_flow_counter_in_bits {
4556 u8 opcode[0x10];
4557 u8 reserved_at_10[0x10];
4558
4559 u8 reserved_at_20[0x10];
4560 u8 op_mod[0x10];
4561
4562 u8 reserved_at_40[0x80];
4563
4564 u8 clear[0x1];
4565 u8 reserved_at_c1[0xf];
4566 u8 num_of_counters[0x10];
4567
4568 u8 flow_counter_id[0x20];
4569 };
4570
4571 struct mlx5_ifc_query_esw_vport_context_out_bits {
4572 u8 status[0x8];
4573 u8 reserved_at_8[0x18];
4574
4575 u8 syndrome[0x20];
4576
4577 u8 reserved_at_40[0x40];
4578
4579 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4580 };
4581
4582 struct mlx5_ifc_query_esw_vport_context_in_bits {
4583 u8 opcode[0x10];
4584 u8 reserved_at_10[0x10];
4585
4586 u8 reserved_at_20[0x10];
4587 u8 op_mod[0x10];
4588
4589 u8 other_vport[0x1];
4590 u8 reserved_at_41[0xf];
4591 u8 vport_number[0x10];
4592
4593 u8 reserved_at_60[0x20];
4594 };
4595
4596 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4597 u8 status[0x8];
4598 u8 reserved_at_8[0x18];
4599
4600 u8 syndrome[0x20];
4601
4602 u8 reserved_at_40[0x40];
4603 };
4604
4605 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4606 u8 reserved_at_0[0x1c];
4607 u8 vport_cvlan_insert[0x1];
4608 u8 vport_svlan_insert[0x1];
4609 u8 vport_cvlan_strip[0x1];
4610 u8 vport_svlan_strip[0x1];
4611 };
4612
4613 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4614 u8 opcode[0x10];
4615 u8 reserved_at_10[0x10];
4616
4617 u8 reserved_at_20[0x10];
4618 u8 op_mod[0x10];
4619
4620 u8 other_vport[0x1];
4621 u8 reserved_at_41[0xf];
4622 u8 vport_number[0x10];
4623
4624 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4625
4626 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4627 };
4628
4629 struct mlx5_ifc_query_eq_out_bits {
4630 u8 status[0x8];
4631 u8 reserved_at_8[0x18];
4632
4633 u8 syndrome[0x20];
4634
4635 u8 reserved_at_40[0x40];
4636
4637 struct mlx5_ifc_eqc_bits eq_context_entry;
4638
4639 u8 reserved_at_280[0x40];
4640
4641 u8 event_bitmask[0x40];
4642
4643 u8 reserved_at_300[0x580];
4644
4645 u8 pas[0][0x40];
4646 };
4647
4648 struct mlx5_ifc_query_eq_in_bits {
4649 u8 opcode[0x10];
4650 u8 reserved_at_10[0x10];
4651
4652 u8 reserved_at_20[0x10];
4653 u8 op_mod[0x10];
4654
4655 u8 reserved_at_40[0x18];
4656 u8 eq_number[0x8];
4657
4658 u8 reserved_at_60[0x20];
4659 };
4660
4661 struct mlx5_ifc_encap_header_in_bits {
4662 u8 reserved_at_0[0x5];
4663 u8 header_type[0x3];
4664 u8 reserved_at_8[0xe];
4665 u8 encap_header_size[0xa];
4666
4667 u8 reserved_at_20[0x10];
4668 u8 encap_header[2][0x8];
4669
4670 u8 more_encap_header[0][0x8];
4671 };
4672
4673 struct mlx5_ifc_query_encap_header_out_bits {
4674 u8 status[0x8];
4675 u8 reserved_at_8[0x18];
4676
4677 u8 syndrome[0x20];
4678
4679 u8 reserved_at_40[0xa0];
4680
4681 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4682 };
4683
4684 struct mlx5_ifc_query_encap_header_in_bits {
4685 u8 opcode[0x10];
4686 u8 reserved_at_10[0x10];
4687
4688 u8 reserved_at_20[0x10];
4689 u8 op_mod[0x10];
4690
4691 u8 encap_id[0x20];
4692
4693 u8 reserved_at_60[0xa0];
4694 };
4695
4696 struct mlx5_ifc_alloc_encap_header_out_bits {
4697 u8 status[0x8];
4698 u8 reserved_at_8[0x18];
4699
4700 u8 syndrome[0x20];
4701
4702 u8 encap_id[0x20];
4703
4704 u8 reserved_at_60[0x20];
4705 };
4706
4707 struct mlx5_ifc_alloc_encap_header_in_bits {
4708 u8 opcode[0x10];
4709 u8 reserved_at_10[0x10];
4710
4711 u8 reserved_at_20[0x10];
4712 u8 op_mod[0x10];
4713
4714 u8 reserved_at_40[0xa0];
4715
4716 struct mlx5_ifc_encap_header_in_bits encap_header;
4717 };
4718
4719 struct mlx5_ifc_dealloc_encap_header_out_bits {
4720 u8 status[0x8];
4721 u8 reserved_at_8[0x18];
4722
4723 u8 syndrome[0x20];
4724
4725 u8 reserved_at_40[0x40];
4726 };
4727
4728 struct mlx5_ifc_dealloc_encap_header_in_bits {
4729 u8 opcode[0x10];
4730 u8 reserved_at_10[0x10];
4731
4732 u8 reserved_20[0x10];
4733 u8 op_mod[0x10];
4734
4735 u8 encap_id[0x20];
4736
4737 u8 reserved_60[0x20];
4738 };
4739
4740 struct mlx5_ifc_set_action_in_bits {
4741 u8 action_type[0x4];
4742 u8 field[0xc];
4743 u8 reserved_at_10[0x3];
4744 u8 offset[0x5];
4745 u8 reserved_at_18[0x3];
4746 u8 length[0x5];
4747
4748 u8 data[0x20];
4749 };
4750
4751 struct mlx5_ifc_add_action_in_bits {
4752 u8 action_type[0x4];
4753 u8 field[0xc];
4754 u8 reserved_at_10[0x10];
4755
4756 u8 data[0x20];
4757 };
4758
4759 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4760 struct mlx5_ifc_set_action_in_bits set_action_in;
4761 struct mlx5_ifc_add_action_in_bits add_action_in;
4762 u8 reserved_at_0[0x40];
4763 };
4764
4765 enum {
4766 MLX5_ACTION_TYPE_SET = 0x1,
4767 MLX5_ACTION_TYPE_ADD = 0x2,
4768 };
4769
4770 enum {
4771 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4772 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4773 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4774 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4775 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4776 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4777 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4778 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4779 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4780 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4781 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4782 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4783 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4784 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4785 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4786 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4787 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4788 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4789 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4790 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4791 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4792 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4793 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4794 };
4795
4796 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4797 u8 status[0x8];
4798 u8 reserved_at_8[0x18];
4799
4800 u8 syndrome[0x20];
4801
4802 u8 modify_header_id[0x20];
4803
4804 u8 reserved_at_60[0x20];
4805 };
4806
4807 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4808 u8 opcode[0x10];
4809 u8 reserved_at_10[0x10];
4810
4811 u8 reserved_at_20[0x10];
4812 u8 op_mod[0x10];
4813
4814 u8 reserved_at_40[0x20];
4815
4816 u8 table_type[0x8];
4817 u8 reserved_at_68[0x10];
4818 u8 num_of_actions[0x8];
4819
4820 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4821 };
4822
4823 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4824 u8 status[0x8];
4825 u8 reserved_at_8[0x18];
4826
4827 u8 syndrome[0x20];
4828
4829 u8 reserved_at_40[0x40];
4830 };
4831
4832 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4833 u8 opcode[0x10];
4834 u8 reserved_at_10[0x10];
4835
4836 u8 reserved_at_20[0x10];
4837 u8 op_mod[0x10];
4838
4839 u8 modify_header_id[0x20];
4840
4841 u8 reserved_at_60[0x20];
4842 };
4843
4844 struct mlx5_ifc_query_dct_out_bits {
4845 u8 status[0x8];
4846 u8 reserved_at_8[0x18];
4847
4848 u8 syndrome[0x20];
4849
4850 u8 reserved_at_40[0x40];
4851
4852 struct mlx5_ifc_dctc_bits dct_context_entry;
4853
4854 u8 reserved_at_280[0x180];
4855 };
4856
4857 struct mlx5_ifc_query_dct_in_bits {
4858 u8 opcode[0x10];
4859 u8 reserved_at_10[0x10];
4860
4861 u8 reserved_at_20[0x10];
4862 u8 op_mod[0x10];
4863
4864 u8 reserved_at_40[0x8];
4865 u8 dctn[0x18];
4866
4867 u8 reserved_at_60[0x20];
4868 };
4869
4870 struct mlx5_ifc_query_cq_out_bits {
4871 u8 status[0x8];
4872 u8 reserved_at_8[0x18];
4873
4874 u8 syndrome[0x20];
4875
4876 u8 reserved_at_40[0x40];
4877
4878 struct mlx5_ifc_cqc_bits cq_context;
4879
4880 u8 reserved_at_280[0x600];
4881
4882 u8 pas[0][0x40];
4883 };
4884
4885 struct mlx5_ifc_query_cq_in_bits {
4886 u8 opcode[0x10];
4887 u8 reserved_at_10[0x10];
4888
4889 u8 reserved_at_20[0x10];
4890 u8 op_mod[0x10];
4891
4892 u8 reserved_at_40[0x8];
4893 u8 cqn[0x18];
4894
4895 u8 reserved_at_60[0x20];
4896 };
4897
4898 struct mlx5_ifc_query_cong_status_out_bits {
4899 u8 status[0x8];
4900 u8 reserved_at_8[0x18];
4901
4902 u8 syndrome[0x20];
4903
4904 u8 reserved_at_40[0x20];
4905
4906 u8 enable[0x1];
4907 u8 tag_enable[0x1];
4908 u8 reserved_at_62[0x1e];
4909 };
4910
4911 struct mlx5_ifc_query_cong_status_in_bits {
4912 u8 opcode[0x10];
4913 u8 reserved_at_10[0x10];
4914
4915 u8 reserved_at_20[0x10];
4916 u8 op_mod[0x10];
4917
4918 u8 reserved_at_40[0x18];
4919 u8 priority[0x4];
4920 u8 cong_protocol[0x4];
4921
4922 u8 reserved_at_60[0x20];
4923 };
4924
4925 struct mlx5_ifc_query_cong_statistics_out_bits {
4926 u8 status[0x8];
4927 u8 reserved_at_8[0x18];
4928
4929 u8 syndrome[0x20];
4930
4931 u8 reserved_at_40[0x40];
4932
4933 u8 rp_cur_flows[0x20];
4934
4935 u8 sum_flows[0x20];
4936
4937 u8 rp_cnp_ignored_high[0x20];
4938
4939 u8 rp_cnp_ignored_low[0x20];
4940
4941 u8 rp_cnp_handled_high[0x20];
4942
4943 u8 rp_cnp_handled_low[0x20];
4944
4945 u8 reserved_at_140[0x100];
4946
4947 u8 time_stamp_high[0x20];
4948
4949 u8 time_stamp_low[0x20];
4950
4951 u8 accumulators_period[0x20];
4952
4953 u8 np_ecn_marked_roce_packets_high[0x20];
4954
4955 u8 np_ecn_marked_roce_packets_low[0x20];
4956
4957 u8 np_cnp_sent_high[0x20];
4958
4959 u8 np_cnp_sent_low[0x20];
4960
4961 u8 reserved_at_320[0x560];
4962 };
4963
4964 struct mlx5_ifc_query_cong_statistics_in_bits {
4965 u8 opcode[0x10];
4966 u8 reserved_at_10[0x10];
4967
4968 u8 reserved_at_20[0x10];
4969 u8 op_mod[0x10];
4970
4971 u8 clear[0x1];
4972 u8 reserved_at_41[0x1f];
4973
4974 u8 reserved_at_60[0x20];
4975 };
4976
4977 struct mlx5_ifc_query_cong_params_out_bits {
4978 u8 status[0x8];
4979 u8 reserved_at_8[0x18];
4980
4981 u8 syndrome[0x20];
4982
4983 u8 reserved_at_40[0x40];
4984
4985 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4986 };
4987
4988 struct mlx5_ifc_query_cong_params_in_bits {
4989 u8 opcode[0x10];
4990 u8 reserved_at_10[0x10];
4991
4992 u8 reserved_at_20[0x10];
4993 u8 op_mod[0x10];
4994
4995 u8 reserved_at_40[0x1c];
4996 u8 cong_protocol[0x4];
4997
4998 u8 reserved_at_60[0x20];
4999 };
5000
5001 struct mlx5_ifc_query_adapter_out_bits {
5002 u8 status[0x8];
5003 u8 reserved_at_8[0x18];
5004
5005 u8 syndrome[0x20];
5006
5007 u8 reserved_at_40[0x40];
5008
5009 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5010 };
5011
5012 struct mlx5_ifc_query_adapter_in_bits {
5013 u8 opcode[0x10];
5014 u8 reserved_at_10[0x10];
5015
5016 u8 reserved_at_20[0x10];
5017 u8 op_mod[0x10];
5018
5019 u8 reserved_at_40[0x40];
5020 };
5021
5022 struct mlx5_ifc_qp_2rst_out_bits {
5023 u8 status[0x8];
5024 u8 reserved_at_8[0x18];
5025
5026 u8 syndrome[0x20];
5027
5028 u8 reserved_at_40[0x40];
5029 };
5030
5031 struct mlx5_ifc_qp_2rst_in_bits {
5032 u8 opcode[0x10];
5033 u8 reserved_at_10[0x10];
5034
5035 u8 reserved_at_20[0x10];
5036 u8 op_mod[0x10];
5037
5038 u8 reserved_at_40[0x8];
5039 u8 qpn[0x18];
5040
5041 u8 reserved_at_60[0x20];
5042 };
5043
5044 struct mlx5_ifc_qp_2err_out_bits {
5045 u8 status[0x8];
5046 u8 reserved_at_8[0x18];
5047
5048 u8 syndrome[0x20];
5049
5050 u8 reserved_at_40[0x40];
5051 };
5052
5053 struct mlx5_ifc_qp_2err_in_bits {
5054 u8 opcode[0x10];
5055 u8 reserved_at_10[0x10];
5056
5057 u8 reserved_at_20[0x10];
5058 u8 op_mod[0x10];
5059
5060 u8 reserved_at_40[0x8];
5061 u8 qpn[0x18];
5062
5063 u8 reserved_at_60[0x20];
5064 };
5065
5066 struct mlx5_ifc_page_fault_resume_out_bits {
5067 u8 status[0x8];
5068 u8 reserved_at_8[0x18];
5069
5070 u8 syndrome[0x20];
5071
5072 u8 reserved_at_40[0x40];
5073 };
5074
5075 struct mlx5_ifc_page_fault_resume_in_bits {
5076 u8 opcode[0x10];
5077 u8 reserved_at_10[0x10];
5078
5079 u8 reserved_at_20[0x10];
5080 u8 op_mod[0x10];
5081
5082 u8 error[0x1];
5083 u8 reserved_at_41[0x4];
5084 u8 page_fault_type[0x3];
5085 u8 wq_number[0x18];
5086
5087 u8 reserved_at_60[0x8];
5088 u8 token[0x18];
5089 };
5090
5091 struct mlx5_ifc_nop_out_bits {
5092 u8 status[0x8];
5093 u8 reserved_at_8[0x18];
5094
5095 u8 syndrome[0x20];
5096
5097 u8 reserved_at_40[0x40];
5098 };
5099
5100 struct mlx5_ifc_nop_in_bits {
5101 u8 opcode[0x10];
5102 u8 reserved_at_10[0x10];
5103
5104 u8 reserved_at_20[0x10];
5105 u8 op_mod[0x10];
5106
5107 u8 reserved_at_40[0x40];
5108 };
5109
5110 struct mlx5_ifc_modify_vport_state_out_bits {
5111 u8 status[0x8];
5112 u8 reserved_at_8[0x18];
5113
5114 u8 syndrome[0x20];
5115
5116 u8 reserved_at_40[0x40];
5117 };
5118
5119 struct mlx5_ifc_modify_vport_state_in_bits {
5120 u8 opcode[0x10];
5121 u8 reserved_at_10[0x10];
5122
5123 u8 reserved_at_20[0x10];
5124 u8 op_mod[0x10];
5125
5126 u8 other_vport[0x1];
5127 u8 reserved_at_41[0xf];
5128 u8 vport_number[0x10];
5129
5130 u8 reserved_at_60[0x18];
5131 u8 admin_state[0x4];
5132 u8 reserved_at_7c[0x4];
5133 };
5134
5135 struct mlx5_ifc_modify_tis_out_bits {
5136 u8 status[0x8];
5137 u8 reserved_at_8[0x18];
5138
5139 u8 syndrome[0x20];
5140
5141 u8 reserved_at_40[0x40];
5142 };
5143
5144 struct mlx5_ifc_modify_tis_bitmask_bits {
5145 u8 reserved_at_0[0x20];
5146
5147 u8 reserved_at_20[0x1d];
5148 u8 lag_tx_port_affinity[0x1];
5149 u8 strict_lag_tx_port_affinity[0x1];
5150 u8 prio[0x1];
5151 };
5152
5153 struct mlx5_ifc_modify_tis_in_bits {
5154 u8 opcode[0x10];
5155 u8 reserved_at_10[0x10];
5156
5157 u8 reserved_at_20[0x10];
5158 u8 op_mod[0x10];
5159
5160 u8 reserved_at_40[0x8];
5161 u8 tisn[0x18];
5162
5163 u8 reserved_at_60[0x20];
5164
5165 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5166
5167 u8 reserved_at_c0[0x40];
5168
5169 struct mlx5_ifc_tisc_bits ctx;
5170 };
5171
5172 struct mlx5_ifc_modify_tir_bitmask_bits {
5173 u8 reserved_at_0[0x20];
5174
5175 u8 reserved_at_20[0x1b];
5176 u8 self_lb_en[0x1];
5177 u8 reserved_at_3c[0x1];
5178 u8 hash[0x1];
5179 u8 reserved_at_3e[0x1];
5180 u8 lro[0x1];
5181 };
5182
5183 struct mlx5_ifc_modify_tir_out_bits {
5184 u8 status[0x8];
5185 u8 reserved_at_8[0x18];
5186
5187 u8 syndrome[0x20];
5188
5189 u8 reserved_at_40[0x40];
5190 };
5191
5192 struct mlx5_ifc_modify_tir_in_bits {
5193 u8 opcode[0x10];
5194 u8 reserved_at_10[0x10];
5195
5196 u8 reserved_at_20[0x10];
5197 u8 op_mod[0x10];
5198
5199 u8 reserved_at_40[0x8];
5200 u8 tirn[0x18];
5201
5202 u8 reserved_at_60[0x20];
5203
5204 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5205
5206 u8 reserved_at_c0[0x40];
5207
5208 struct mlx5_ifc_tirc_bits ctx;
5209 };
5210
5211 struct mlx5_ifc_modify_sq_out_bits {
5212 u8 status[0x8];
5213 u8 reserved_at_8[0x18];
5214
5215 u8 syndrome[0x20];
5216
5217 u8 reserved_at_40[0x40];
5218 };
5219
5220 struct mlx5_ifc_modify_sq_in_bits {
5221 u8 opcode[0x10];
5222 u8 reserved_at_10[0x10];
5223
5224 u8 reserved_at_20[0x10];
5225 u8 op_mod[0x10];
5226
5227 u8 sq_state[0x4];
5228 u8 reserved_at_44[0x4];
5229 u8 sqn[0x18];
5230
5231 u8 reserved_at_60[0x20];
5232
5233 u8 modify_bitmask[0x40];
5234
5235 u8 reserved_at_c0[0x40];
5236
5237 struct mlx5_ifc_sqc_bits ctx;
5238 };
5239
5240 struct mlx5_ifc_modify_scheduling_element_out_bits {
5241 u8 status[0x8];
5242 u8 reserved_at_8[0x18];
5243
5244 u8 syndrome[0x20];
5245
5246 u8 reserved_at_40[0x1c0];
5247 };
5248
5249 enum {
5250 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5251 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5252 };
5253
5254 struct mlx5_ifc_modify_scheduling_element_in_bits {
5255 u8 opcode[0x10];
5256 u8 reserved_at_10[0x10];
5257
5258 u8 reserved_at_20[0x10];
5259 u8 op_mod[0x10];
5260
5261 u8 scheduling_hierarchy[0x8];
5262 u8 reserved_at_48[0x18];
5263
5264 u8 scheduling_element_id[0x20];
5265
5266 u8 reserved_at_80[0x20];
5267
5268 u8 modify_bitmask[0x20];
5269
5270 u8 reserved_at_c0[0x40];
5271
5272 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5273
5274 u8 reserved_at_300[0x100];
5275 };
5276
5277 struct mlx5_ifc_modify_rqt_out_bits {
5278 u8 status[0x8];
5279 u8 reserved_at_8[0x18];
5280
5281 u8 syndrome[0x20];
5282
5283 u8 reserved_at_40[0x40];
5284 };
5285
5286 struct mlx5_ifc_rqt_bitmask_bits {
5287 u8 reserved_at_0[0x20];
5288
5289 u8 reserved_at_20[0x1f];
5290 u8 rqn_list[0x1];
5291 };
5292
5293 struct mlx5_ifc_modify_rqt_in_bits {
5294 u8 opcode[0x10];
5295 u8 reserved_at_10[0x10];
5296
5297 u8 reserved_at_20[0x10];
5298 u8 op_mod[0x10];
5299
5300 u8 reserved_at_40[0x8];
5301 u8 rqtn[0x18];
5302
5303 u8 reserved_at_60[0x20];
5304
5305 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5306
5307 u8 reserved_at_c0[0x40];
5308
5309 struct mlx5_ifc_rqtc_bits ctx;
5310 };
5311
5312 struct mlx5_ifc_modify_rq_out_bits {
5313 u8 status[0x8];
5314 u8 reserved_at_8[0x18];
5315
5316 u8 syndrome[0x20];
5317
5318 u8 reserved_at_40[0x40];
5319 };
5320
5321 enum {
5322 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5323 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5324 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5325 };
5326
5327 struct mlx5_ifc_modify_rq_in_bits {
5328 u8 opcode[0x10];
5329 u8 reserved_at_10[0x10];
5330
5331 u8 reserved_at_20[0x10];
5332 u8 op_mod[0x10];
5333
5334 u8 rq_state[0x4];
5335 u8 reserved_at_44[0x4];
5336 u8 rqn[0x18];
5337
5338 u8 reserved_at_60[0x20];
5339
5340 u8 modify_bitmask[0x40];
5341
5342 u8 reserved_at_c0[0x40];
5343
5344 struct mlx5_ifc_rqc_bits ctx;
5345 };
5346
5347 struct mlx5_ifc_modify_rmp_out_bits {
5348 u8 status[0x8];
5349 u8 reserved_at_8[0x18];
5350
5351 u8 syndrome[0x20];
5352
5353 u8 reserved_at_40[0x40];
5354 };
5355
5356 struct mlx5_ifc_rmp_bitmask_bits {
5357 u8 reserved_at_0[0x20];
5358
5359 u8 reserved_at_20[0x1f];
5360 u8 lwm[0x1];
5361 };
5362
5363 struct mlx5_ifc_modify_rmp_in_bits {
5364 u8 opcode[0x10];
5365 u8 reserved_at_10[0x10];
5366
5367 u8 reserved_at_20[0x10];
5368 u8 op_mod[0x10];
5369
5370 u8 rmp_state[0x4];
5371 u8 reserved_at_44[0x4];
5372 u8 rmpn[0x18];
5373
5374 u8 reserved_at_60[0x20];
5375
5376 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5377
5378 u8 reserved_at_c0[0x40];
5379
5380 struct mlx5_ifc_rmpc_bits ctx;
5381 };
5382
5383 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5384 u8 status[0x8];
5385 u8 reserved_at_8[0x18];
5386
5387 u8 syndrome[0x20];
5388
5389 u8 reserved_at_40[0x40];
5390 };
5391
5392 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5393 u8 reserved_at_0[0x12];
5394 u8 affiliation[0x1];
5395 u8 reserved_at_e[0x1];
5396 u8 disable_uc_local_lb[0x1];
5397 u8 disable_mc_local_lb[0x1];
5398 u8 node_guid[0x1];
5399 u8 port_guid[0x1];
5400 u8 min_inline[0x1];
5401 u8 mtu[0x1];
5402 u8 change_event[0x1];
5403 u8 promisc[0x1];
5404 u8 permanent_address[0x1];
5405 u8 addresses_list[0x1];
5406 u8 roce_en[0x1];
5407 u8 reserved_at_1f[0x1];
5408 };
5409
5410 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5411 u8 opcode[0x10];
5412 u8 reserved_at_10[0x10];
5413
5414 u8 reserved_at_20[0x10];
5415 u8 op_mod[0x10];
5416
5417 u8 other_vport[0x1];
5418 u8 reserved_at_41[0xf];
5419 u8 vport_number[0x10];
5420
5421 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5422
5423 u8 reserved_at_80[0x780];
5424
5425 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5426 };
5427
5428 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5429 u8 status[0x8];
5430 u8 reserved_at_8[0x18];
5431
5432 u8 syndrome[0x20];
5433
5434 u8 reserved_at_40[0x40];
5435 };
5436
5437 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5438 u8 opcode[0x10];
5439 u8 reserved_at_10[0x10];
5440
5441 u8 reserved_at_20[0x10];
5442 u8 op_mod[0x10];
5443
5444 u8 other_vport[0x1];
5445 u8 reserved_at_41[0xb];
5446 u8 port_num[0x4];
5447 u8 vport_number[0x10];
5448
5449 u8 reserved_at_60[0x20];
5450
5451 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5452 };
5453
5454 struct mlx5_ifc_modify_cq_out_bits {
5455 u8 status[0x8];
5456 u8 reserved_at_8[0x18];
5457
5458 u8 syndrome[0x20];
5459
5460 u8 reserved_at_40[0x40];
5461 };
5462
5463 enum {
5464 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5465 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5466 };
5467
5468 struct mlx5_ifc_modify_cq_in_bits {
5469 u8 opcode[0x10];
5470 u8 reserved_at_10[0x10];
5471
5472 u8 reserved_at_20[0x10];
5473 u8 op_mod[0x10];
5474
5475 u8 reserved_at_40[0x8];
5476 u8 cqn[0x18];
5477
5478 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5479
5480 struct mlx5_ifc_cqc_bits cq_context;
5481
5482 u8 reserved_at_280[0x600];
5483
5484 u8 pas[0][0x40];
5485 };
5486
5487 struct mlx5_ifc_modify_cong_status_out_bits {
5488 u8 status[0x8];
5489 u8 reserved_at_8[0x18];
5490
5491 u8 syndrome[0x20];
5492
5493 u8 reserved_at_40[0x40];
5494 };
5495
5496 struct mlx5_ifc_modify_cong_status_in_bits {
5497 u8 opcode[0x10];
5498 u8 reserved_at_10[0x10];
5499
5500 u8 reserved_at_20[0x10];
5501 u8 op_mod[0x10];
5502
5503 u8 reserved_at_40[0x18];
5504 u8 priority[0x4];
5505 u8 cong_protocol[0x4];
5506
5507 u8 enable[0x1];
5508 u8 tag_enable[0x1];
5509 u8 reserved_at_62[0x1e];
5510 };
5511
5512 struct mlx5_ifc_modify_cong_params_out_bits {
5513 u8 status[0x8];
5514 u8 reserved_at_8[0x18];
5515
5516 u8 syndrome[0x20];
5517
5518 u8 reserved_at_40[0x40];
5519 };
5520
5521 struct mlx5_ifc_modify_cong_params_in_bits {
5522 u8 opcode[0x10];
5523 u8 reserved_at_10[0x10];
5524
5525 u8 reserved_at_20[0x10];
5526 u8 op_mod[0x10];
5527
5528 u8 reserved_at_40[0x1c];
5529 u8 cong_protocol[0x4];
5530
5531 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5532
5533 u8 reserved_at_80[0x80];
5534
5535 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5536 };
5537
5538 struct mlx5_ifc_manage_pages_out_bits {
5539 u8 status[0x8];
5540 u8 reserved_at_8[0x18];
5541
5542 u8 syndrome[0x20];
5543
5544 u8 output_num_entries[0x20];
5545
5546 u8 reserved_at_60[0x20];
5547
5548 u8 pas[0][0x40];
5549 };
5550
5551 enum {
5552 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5553 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5554 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5555 };
5556
5557 struct mlx5_ifc_manage_pages_in_bits {
5558 u8 opcode[0x10];
5559 u8 reserved_at_10[0x10];
5560
5561 u8 reserved_at_20[0x10];
5562 u8 op_mod[0x10];
5563
5564 u8 reserved_at_40[0x10];
5565 u8 function_id[0x10];
5566
5567 u8 input_num_entries[0x20];
5568
5569 u8 pas[0][0x40];
5570 };
5571
5572 struct mlx5_ifc_mad_ifc_out_bits {
5573 u8 status[0x8];
5574 u8 reserved_at_8[0x18];
5575
5576 u8 syndrome[0x20];
5577
5578 u8 reserved_at_40[0x40];
5579
5580 u8 response_mad_packet[256][0x8];
5581 };
5582
5583 struct mlx5_ifc_mad_ifc_in_bits {
5584 u8 opcode[0x10];
5585 u8 reserved_at_10[0x10];
5586
5587 u8 reserved_at_20[0x10];
5588 u8 op_mod[0x10];
5589
5590 u8 remote_lid[0x10];
5591 u8 reserved_at_50[0x8];
5592 u8 port[0x8];
5593
5594 u8 reserved_at_60[0x20];
5595
5596 u8 mad[256][0x8];
5597 };
5598
5599 struct mlx5_ifc_init_hca_out_bits {
5600 u8 status[0x8];
5601 u8 reserved_at_8[0x18];
5602
5603 u8 syndrome[0x20];
5604
5605 u8 reserved_at_40[0x40];
5606 };
5607
5608 struct mlx5_ifc_init_hca_in_bits {
5609 u8 opcode[0x10];
5610 u8 reserved_at_10[0x10];
5611
5612 u8 reserved_at_20[0x10];
5613 u8 op_mod[0x10];
5614
5615 u8 reserved_at_40[0x40];
5616 u8 sw_owner_id[4][0x20];
5617 };
5618
5619 struct mlx5_ifc_init2rtr_qp_out_bits {
5620 u8 status[0x8];
5621 u8 reserved_at_8[0x18];
5622
5623 u8 syndrome[0x20];
5624
5625 u8 reserved_at_40[0x40];
5626 };
5627
5628 struct mlx5_ifc_init2rtr_qp_in_bits {
5629 u8 opcode[0x10];
5630 u8 reserved_at_10[0x10];
5631
5632 u8 reserved_at_20[0x10];
5633 u8 op_mod[0x10];
5634
5635 u8 reserved_at_40[0x8];
5636 u8 qpn[0x18];
5637
5638 u8 reserved_at_60[0x20];
5639
5640 u8 opt_param_mask[0x20];
5641
5642 u8 reserved_at_a0[0x20];
5643
5644 struct mlx5_ifc_qpc_bits qpc;
5645
5646 u8 reserved_at_800[0x80];
5647 };
5648
5649 struct mlx5_ifc_init2init_qp_out_bits {
5650 u8 status[0x8];
5651 u8 reserved_at_8[0x18];
5652
5653 u8 syndrome[0x20];
5654
5655 u8 reserved_at_40[0x40];
5656 };
5657
5658 struct mlx5_ifc_init2init_qp_in_bits {
5659 u8 opcode[0x10];
5660 u8 reserved_at_10[0x10];
5661
5662 u8 reserved_at_20[0x10];
5663 u8 op_mod[0x10];
5664
5665 u8 reserved_at_40[0x8];
5666 u8 qpn[0x18];
5667
5668 u8 reserved_at_60[0x20];
5669
5670 u8 opt_param_mask[0x20];
5671
5672 u8 reserved_at_a0[0x20];
5673
5674 struct mlx5_ifc_qpc_bits qpc;
5675
5676 u8 reserved_at_800[0x80];
5677 };
5678
5679 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5680 u8 status[0x8];
5681 u8 reserved_at_8[0x18];
5682
5683 u8 syndrome[0x20];
5684
5685 u8 reserved_at_40[0x40];
5686
5687 u8 packet_headers_log[128][0x8];
5688
5689 u8 packet_syndrome[64][0x8];
5690 };
5691
5692 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5693 u8 opcode[0x10];
5694 u8 reserved_at_10[0x10];
5695
5696 u8 reserved_at_20[0x10];
5697 u8 op_mod[0x10];
5698
5699 u8 reserved_at_40[0x40];
5700 };
5701
5702 struct mlx5_ifc_gen_eqe_in_bits {
5703 u8 opcode[0x10];
5704 u8 reserved_at_10[0x10];
5705
5706 u8 reserved_at_20[0x10];
5707 u8 op_mod[0x10];
5708
5709 u8 reserved_at_40[0x18];
5710 u8 eq_number[0x8];
5711
5712 u8 reserved_at_60[0x20];
5713
5714 u8 eqe[64][0x8];
5715 };
5716
5717 struct mlx5_ifc_gen_eq_out_bits {
5718 u8 status[0x8];
5719 u8 reserved_at_8[0x18];
5720
5721 u8 syndrome[0x20];
5722
5723 u8 reserved_at_40[0x40];
5724 };
5725
5726 struct mlx5_ifc_enable_hca_out_bits {
5727 u8 status[0x8];
5728 u8 reserved_at_8[0x18];
5729
5730 u8 syndrome[0x20];
5731
5732 u8 reserved_at_40[0x20];
5733 };
5734
5735 struct mlx5_ifc_enable_hca_in_bits {
5736 u8 opcode[0x10];
5737 u8 reserved_at_10[0x10];
5738
5739 u8 reserved_at_20[0x10];
5740 u8 op_mod[0x10];
5741
5742 u8 reserved_at_40[0x10];
5743 u8 function_id[0x10];
5744
5745 u8 reserved_at_60[0x20];
5746 };
5747
5748 struct mlx5_ifc_drain_dct_out_bits {
5749 u8 status[0x8];
5750 u8 reserved_at_8[0x18];
5751
5752 u8 syndrome[0x20];
5753
5754 u8 reserved_at_40[0x40];
5755 };
5756
5757 struct mlx5_ifc_drain_dct_in_bits {
5758 u8 opcode[0x10];
5759 u8 reserved_at_10[0x10];
5760
5761 u8 reserved_at_20[0x10];
5762 u8 op_mod[0x10];
5763
5764 u8 reserved_at_40[0x8];
5765 u8 dctn[0x18];
5766
5767 u8 reserved_at_60[0x20];
5768 };
5769
5770 struct mlx5_ifc_disable_hca_out_bits {
5771 u8 status[0x8];
5772 u8 reserved_at_8[0x18];
5773
5774 u8 syndrome[0x20];
5775
5776 u8 reserved_at_40[0x20];
5777 };
5778
5779 struct mlx5_ifc_disable_hca_in_bits {
5780 u8 opcode[0x10];
5781 u8 reserved_at_10[0x10];
5782
5783 u8 reserved_at_20[0x10];
5784 u8 op_mod[0x10];
5785
5786 u8 reserved_at_40[0x10];
5787 u8 function_id[0x10];
5788
5789 u8 reserved_at_60[0x20];
5790 };
5791
5792 struct mlx5_ifc_detach_from_mcg_out_bits {
5793 u8 status[0x8];
5794 u8 reserved_at_8[0x18];
5795
5796 u8 syndrome[0x20];
5797
5798 u8 reserved_at_40[0x40];
5799 };
5800
5801 struct mlx5_ifc_detach_from_mcg_in_bits {
5802 u8 opcode[0x10];
5803 u8 reserved_at_10[0x10];
5804
5805 u8 reserved_at_20[0x10];
5806 u8 op_mod[0x10];
5807
5808 u8 reserved_at_40[0x8];
5809 u8 qpn[0x18];
5810
5811 u8 reserved_at_60[0x20];
5812
5813 u8 multicast_gid[16][0x8];
5814 };
5815
5816 struct mlx5_ifc_destroy_xrq_out_bits {
5817 u8 status[0x8];
5818 u8 reserved_at_8[0x18];
5819
5820 u8 syndrome[0x20];
5821
5822 u8 reserved_at_40[0x40];
5823 };
5824
5825 struct mlx5_ifc_destroy_xrq_in_bits {
5826 u8 opcode[0x10];
5827 u8 reserved_at_10[0x10];
5828
5829 u8 reserved_at_20[0x10];
5830 u8 op_mod[0x10];
5831
5832 u8 reserved_at_40[0x8];
5833 u8 xrqn[0x18];
5834
5835 u8 reserved_at_60[0x20];
5836 };
5837
5838 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5839 u8 status[0x8];
5840 u8 reserved_at_8[0x18];
5841
5842 u8 syndrome[0x20];
5843
5844 u8 reserved_at_40[0x40];
5845 };
5846
5847 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5848 u8 opcode[0x10];
5849 u8 reserved_at_10[0x10];
5850
5851 u8 reserved_at_20[0x10];
5852 u8 op_mod[0x10];
5853
5854 u8 reserved_at_40[0x8];
5855 u8 xrc_srqn[0x18];
5856
5857 u8 reserved_at_60[0x20];
5858 };
5859
5860 struct mlx5_ifc_destroy_tis_out_bits {
5861 u8 status[0x8];
5862 u8 reserved_at_8[0x18];
5863
5864 u8 syndrome[0x20];
5865
5866 u8 reserved_at_40[0x40];
5867 };
5868
5869 struct mlx5_ifc_destroy_tis_in_bits {
5870 u8 opcode[0x10];
5871 u8 reserved_at_10[0x10];
5872
5873 u8 reserved_at_20[0x10];
5874 u8 op_mod[0x10];
5875
5876 u8 reserved_at_40[0x8];
5877 u8 tisn[0x18];
5878
5879 u8 reserved_at_60[0x20];
5880 };
5881
5882 struct mlx5_ifc_destroy_tir_out_bits {
5883 u8 status[0x8];
5884 u8 reserved_at_8[0x18];
5885
5886 u8 syndrome[0x20];
5887
5888 u8 reserved_at_40[0x40];
5889 };
5890
5891 struct mlx5_ifc_destroy_tir_in_bits {
5892 u8 opcode[0x10];
5893 u8 reserved_at_10[0x10];
5894
5895 u8 reserved_at_20[0x10];
5896 u8 op_mod[0x10];
5897
5898 u8 reserved_at_40[0x8];
5899 u8 tirn[0x18];
5900
5901 u8 reserved_at_60[0x20];
5902 };
5903
5904 struct mlx5_ifc_destroy_srq_out_bits {
5905 u8 status[0x8];
5906 u8 reserved_at_8[0x18];
5907
5908 u8 syndrome[0x20];
5909
5910 u8 reserved_at_40[0x40];
5911 };
5912
5913 struct mlx5_ifc_destroy_srq_in_bits {
5914 u8 opcode[0x10];
5915 u8 reserved_at_10[0x10];
5916
5917 u8 reserved_at_20[0x10];
5918 u8 op_mod[0x10];
5919
5920 u8 reserved_at_40[0x8];
5921 u8 srqn[0x18];
5922
5923 u8 reserved_at_60[0x20];
5924 };
5925
5926 struct mlx5_ifc_destroy_sq_out_bits {
5927 u8 status[0x8];
5928 u8 reserved_at_8[0x18];
5929
5930 u8 syndrome[0x20];
5931
5932 u8 reserved_at_40[0x40];
5933 };
5934
5935 struct mlx5_ifc_destroy_sq_in_bits {
5936 u8 opcode[0x10];
5937 u8 reserved_at_10[0x10];
5938
5939 u8 reserved_at_20[0x10];
5940 u8 op_mod[0x10];
5941
5942 u8 reserved_at_40[0x8];
5943 u8 sqn[0x18];
5944
5945 u8 reserved_at_60[0x20];
5946 };
5947
5948 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5949 u8 status[0x8];
5950 u8 reserved_at_8[0x18];
5951
5952 u8 syndrome[0x20];
5953
5954 u8 reserved_at_40[0x1c0];
5955 };
5956
5957 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5958 u8 opcode[0x10];
5959 u8 reserved_at_10[0x10];
5960
5961 u8 reserved_at_20[0x10];
5962 u8 op_mod[0x10];
5963
5964 u8 scheduling_hierarchy[0x8];
5965 u8 reserved_at_48[0x18];
5966
5967 u8 scheduling_element_id[0x20];
5968
5969 u8 reserved_at_80[0x180];
5970 };
5971
5972 struct mlx5_ifc_destroy_rqt_out_bits {
5973 u8 status[0x8];
5974 u8 reserved_at_8[0x18];
5975
5976 u8 syndrome[0x20];
5977
5978 u8 reserved_at_40[0x40];
5979 };
5980
5981 struct mlx5_ifc_destroy_rqt_in_bits {
5982 u8 opcode[0x10];
5983 u8 reserved_at_10[0x10];
5984
5985 u8 reserved_at_20[0x10];
5986 u8 op_mod[0x10];
5987
5988 u8 reserved_at_40[0x8];
5989 u8 rqtn[0x18];
5990
5991 u8 reserved_at_60[0x20];
5992 };
5993
5994 struct mlx5_ifc_destroy_rq_out_bits {
5995 u8 status[0x8];
5996 u8 reserved_at_8[0x18];
5997
5998 u8 syndrome[0x20];
5999
6000 u8 reserved_at_40[0x40];
6001 };
6002
6003 struct mlx5_ifc_destroy_rq_in_bits {
6004 u8 opcode[0x10];
6005 u8 reserved_at_10[0x10];
6006
6007 u8 reserved_at_20[0x10];
6008 u8 op_mod[0x10];
6009
6010 u8 reserved_at_40[0x8];
6011 u8 rqn[0x18];
6012
6013 u8 reserved_at_60[0x20];
6014 };
6015
6016 struct mlx5_ifc_set_delay_drop_params_in_bits {
6017 u8 opcode[0x10];
6018 u8 reserved_at_10[0x10];
6019
6020 u8 reserved_at_20[0x10];
6021 u8 op_mod[0x10];
6022
6023 u8 reserved_at_40[0x20];
6024
6025 u8 reserved_at_60[0x10];
6026 u8 delay_drop_timeout[0x10];
6027 };
6028
6029 struct mlx5_ifc_set_delay_drop_params_out_bits {
6030 u8 status[0x8];
6031 u8 reserved_at_8[0x18];
6032
6033 u8 syndrome[0x20];
6034
6035 u8 reserved_at_40[0x40];
6036 };
6037
6038 struct mlx5_ifc_destroy_rmp_out_bits {
6039 u8 status[0x8];
6040 u8 reserved_at_8[0x18];
6041
6042 u8 syndrome[0x20];
6043
6044 u8 reserved_at_40[0x40];
6045 };
6046
6047 struct mlx5_ifc_destroy_rmp_in_bits {
6048 u8 opcode[0x10];
6049 u8 reserved_at_10[0x10];
6050
6051 u8 reserved_at_20[0x10];
6052 u8 op_mod[0x10];
6053
6054 u8 reserved_at_40[0x8];
6055 u8 rmpn[0x18];
6056
6057 u8 reserved_at_60[0x20];
6058 };
6059
6060 struct mlx5_ifc_destroy_qp_out_bits {
6061 u8 status[0x8];
6062 u8 reserved_at_8[0x18];
6063
6064 u8 syndrome[0x20];
6065
6066 u8 reserved_at_40[0x40];
6067 };
6068
6069 struct mlx5_ifc_destroy_qp_in_bits {
6070 u8 opcode[0x10];
6071 u8 reserved_at_10[0x10];
6072
6073 u8 reserved_at_20[0x10];
6074 u8 op_mod[0x10];
6075
6076 u8 reserved_at_40[0x8];
6077 u8 qpn[0x18];
6078
6079 u8 reserved_at_60[0x20];
6080 };
6081
6082 struct mlx5_ifc_destroy_psv_out_bits {
6083 u8 status[0x8];
6084 u8 reserved_at_8[0x18];
6085
6086 u8 syndrome[0x20];
6087
6088 u8 reserved_at_40[0x40];
6089 };
6090
6091 struct mlx5_ifc_destroy_psv_in_bits {
6092 u8 opcode[0x10];
6093 u8 reserved_at_10[0x10];
6094
6095 u8 reserved_at_20[0x10];
6096 u8 op_mod[0x10];
6097
6098 u8 reserved_at_40[0x8];
6099 u8 psvn[0x18];
6100
6101 u8 reserved_at_60[0x20];
6102 };
6103
6104 struct mlx5_ifc_destroy_mkey_out_bits {
6105 u8 status[0x8];
6106 u8 reserved_at_8[0x18];
6107
6108 u8 syndrome[0x20];
6109
6110 u8 reserved_at_40[0x40];
6111 };
6112
6113 struct mlx5_ifc_destroy_mkey_in_bits {
6114 u8 opcode[0x10];
6115 u8 reserved_at_10[0x10];
6116
6117 u8 reserved_at_20[0x10];
6118 u8 op_mod[0x10];
6119
6120 u8 reserved_at_40[0x8];
6121 u8 mkey_index[0x18];
6122
6123 u8 reserved_at_60[0x20];
6124 };
6125
6126 struct mlx5_ifc_destroy_flow_table_out_bits {
6127 u8 status[0x8];
6128 u8 reserved_at_8[0x18];
6129
6130 u8 syndrome[0x20];
6131
6132 u8 reserved_at_40[0x40];
6133 };
6134
6135 struct mlx5_ifc_destroy_flow_table_in_bits {
6136 u8 opcode[0x10];
6137 u8 reserved_at_10[0x10];
6138
6139 u8 reserved_at_20[0x10];
6140 u8 op_mod[0x10];
6141
6142 u8 other_vport[0x1];
6143 u8 reserved_at_41[0xf];
6144 u8 vport_number[0x10];
6145
6146 u8 reserved_at_60[0x20];
6147
6148 u8 table_type[0x8];
6149 u8 reserved_at_88[0x18];
6150
6151 u8 reserved_at_a0[0x8];
6152 u8 table_id[0x18];
6153
6154 u8 reserved_at_c0[0x140];
6155 };
6156
6157 struct mlx5_ifc_destroy_flow_group_out_bits {
6158 u8 status[0x8];
6159 u8 reserved_at_8[0x18];
6160
6161 u8 syndrome[0x20];
6162
6163 u8 reserved_at_40[0x40];
6164 };
6165
6166 struct mlx5_ifc_destroy_flow_group_in_bits {
6167 u8 opcode[0x10];
6168 u8 reserved_at_10[0x10];
6169
6170 u8 reserved_at_20[0x10];
6171 u8 op_mod[0x10];
6172
6173 u8 other_vport[0x1];
6174 u8 reserved_at_41[0xf];
6175 u8 vport_number[0x10];
6176
6177 u8 reserved_at_60[0x20];
6178
6179 u8 table_type[0x8];
6180 u8 reserved_at_88[0x18];
6181
6182 u8 reserved_at_a0[0x8];
6183 u8 table_id[0x18];
6184
6185 u8 group_id[0x20];
6186
6187 u8 reserved_at_e0[0x120];
6188 };
6189
6190 struct mlx5_ifc_destroy_eq_out_bits {
6191 u8 status[0x8];
6192 u8 reserved_at_8[0x18];
6193
6194 u8 syndrome[0x20];
6195
6196 u8 reserved_at_40[0x40];
6197 };
6198
6199 struct mlx5_ifc_destroy_eq_in_bits {
6200 u8 opcode[0x10];
6201 u8 reserved_at_10[0x10];
6202
6203 u8 reserved_at_20[0x10];
6204 u8 op_mod[0x10];
6205
6206 u8 reserved_at_40[0x18];
6207 u8 eq_number[0x8];
6208
6209 u8 reserved_at_60[0x20];
6210 };
6211
6212 struct mlx5_ifc_destroy_dct_out_bits {
6213 u8 status[0x8];
6214 u8 reserved_at_8[0x18];
6215
6216 u8 syndrome[0x20];
6217
6218 u8 reserved_at_40[0x40];
6219 };
6220
6221 struct mlx5_ifc_destroy_dct_in_bits {
6222 u8 opcode[0x10];
6223 u8 reserved_at_10[0x10];
6224
6225 u8 reserved_at_20[0x10];
6226 u8 op_mod[0x10];
6227
6228 u8 reserved_at_40[0x8];
6229 u8 dctn[0x18];
6230
6231 u8 reserved_at_60[0x20];
6232 };
6233
6234 struct mlx5_ifc_destroy_cq_out_bits {
6235 u8 status[0x8];
6236 u8 reserved_at_8[0x18];
6237
6238 u8 syndrome[0x20];
6239
6240 u8 reserved_at_40[0x40];
6241 };
6242
6243 struct mlx5_ifc_destroy_cq_in_bits {
6244 u8 opcode[0x10];
6245 u8 reserved_at_10[0x10];
6246
6247 u8 reserved_at_20[0x10];
6248 u8 op_mod[0x10];
6249
6250 u8 reserved_at_40[0x8];
6251 u8 cqn[0x18];
6252
6253 u8 reserved_at_60[0x20];
6254 };
6255
6256 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6257 u8 status[0x8];
6258 u8 reserved_at_8[0x18];
6259
6260 u8 syndrome[0x20];
6261
6262 u8 reserved_at_40[0x40];
6263 };
6264
6265 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6266 u8 opcode[0x10];
6267 u8 reserved_at_10[0x10];
6268
6269 u8 reserved_at_20[0x10];
6270 u8 op_mod[0x10];
6271
6272 u8 reserved_at_40[0x20];
6273
6274 u8 reserved_at_60[0x10];
6275 u8 vxlan_udp_port[0x10];
6276 };
6277
6278 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6279 u8 status[0x8];
6280 u8 reserved_at_8[0x18];
6281
6282 u8 syndrome[0x20];
6283
6284 u8 reserved_at_40[0x40];
6285 };
6286
6287 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6288 u8 opcode[0x10];
6289 u8 reserved_at_10[0x10];
6290
6291 u8 reserved_at_20[0x10];
6292 u8 op_mod[0x10];
6293
6294 u8 reserved_at_40[0x60];
6295
6296 u8 reserved_at_a0[0x8];
6297 u8 table_index[0x18];
6298
6299 u8 reserved_at_c0[0x140];
6300 };
6301
6302 struct mlx5_ifc_delete_fte_out_bits {
6303 u8 status[0x8];
6304 u8 reserved_at_8[0x18];
6305
6306 u8 syndrome[0x20];
6307
6308 u8 reserved_at_40[0x40];
6309 };
6310
6311 struct mlx5_ifc_delete_fte_in_bits {
6312 u8 opcode[0x10];
6313 u8 reserved_at_10[0x10];
6314
6315 u8 reserved_at_20[0x10];
6316 u8 op_mod[0x10];
6317
6318 u8 other_vport[0x1];
6319 u8 reserved_at_41[0xf];
6320 u8 vport_number[0x10];
6321
6322 u8 reserved_at_60[0x20];
6323
6324 u8 table_type[0x8];
6325 u8 reserved_at_88[0x18];
6326
6327 u8 reserved_at_a0[0x8];
6328 u8 table_id[0x18];
6329
6330 u8 reserved_at_c0[0x40];
6331
6332 u8 flow_index[0x20];
6333
6334 u8 reserved_at_120[0xe0];
6335 };
6336
6337 struct mlx5_ifc_dealloc_xrcd_out_bits {
6338 u8 status[0x8];
6339 u8 reserved_at_8[0x18];
6340
6341 u8 syndrome[0x20];
6342
6343 u8 reserved_at_40[0x40];
6344 };
6345
6346 struct mlx5_ifc_dealloc_xrcd_in_bits {
6347 u8 opcode[0x10];
6348 u8 reserved_at_10[0x10];
6349
6350 u8 reserved_at_20[0x10];
6351 u8 op_mod[0x10];
6352
6353 u8 reserved_at_40[0x8];
6354 u8 xrcd[0x18];
6355
6356 u8 reserved_at_60[0x20];
6357 };
6358
6359 struct mlx5_ifc_dealloc_uar_out_bits {
6360 u8 status[0x8];
6361 u8 reserved_at_8[0x18];
6362
6363 u8 syndrome[0x20];
6364
6365 u8 reserved_at_40[0x40];
6366 };
6367
6368 struct mlx5_ifc_dealloc_uar_in_bits {
6369 u8 opcode[0x10];
6370 u8 reserved_at_10[0x10];
6371
6372 u8 reserved_at_20[0x10];
6373 u8 op_mod[0x10];
6374
6375 u8 reserved_at_40[0x8];
6376 u8 uar[0x18];
6377
6378 u8 reserved_at_60[0x20];
6379 };
6380
6381 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6382 u8 status[0x8];
6383 u8 reserved_at_8[0x18];
6384
6385 u8 syndrome[0x20];
6386
6387 u8 reserved_at_40[0x40];
6388 };
6389
6390 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6391 u8 opcode[0x10];
6392 u8 reserved_at_10[0x10];
6393
6394 u8 reserved_at_20[0x10];
6395 u8 op_mod[0x10];
6396
6397 u8 reserved_at_40[0x8];
6398 u8 transport_domain[0x18];
6399
6400 u8 reserved_at_60[0x20];
6401 };
6402
6403 struct mlx5_ifc_dealloc_q_counter_out_bits {
6404 u8 status[0x8];
6405 u8 reserved_at_8[0x18];
6406
6407 u8 syndrome[0x20];
6408
6409 u8 reserved_at_40[0x40];
6410 };
6411
6412 struct mlx5_ifc_dealloc_q_counter_in_bits {
6413 u8 opcode[0x10];
6414 u8 reserved_at_10[0x10];
6415
6416 u8 reserved_at_20[0x10];
6417 u8 op_mod[0x10];
6418
6419 u8 reserved_at_40[0x18];
6420 u8 counter_set_id[0x8];
6421
6422 u8 reserved_at_60[0x20];
6423 };
6424
6425 struct mlx5_ifc_dealloc_pd_out_bits {
6426 u8 status[0x8];
6427 u8 reserved_at_8[0x18];
6428
6429 u8 syndrome[0x20];
6430
6431 u8 reserved_at_40[0x40];
6432 };
6433
6434 struct mlx5_ifc_dealloc_pd_in_bits {
6435 u8 opcode[0x10];
6436 u8 reserved_at_10[0x10];
6437
6438 u8 reserved_at_20[0x10];
6439 u8 op_mod[0x10];
6440
6441 u8 reserved_at_40[0x8];
6442 u8 pd[0x18];
6443
6444 u8 reserved_at_60[0x20];
6445 };
6446
6447 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6448 u8 status[0x8];
6449 u8 reserved_at_8[0x18];
6450
6451 u8 syndrome[0x20];
6452
6453 u8 reserved_at_40[0x40];
6454 };
6455
6456 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6457 u8 opcode[0x10];
6458 u8 reserved_at_10[0x10];
6459
6460 u8 reserved_at_20[0x10];
6461 u8 op_mod[0x10];
6462
6463 u8 flow_counter_id[0x20];
6464
6465 u8 reserved_at_60[0x20];
6466 };
6467
6468 struct mlx5_ifc_create_xrq_out_bits {
6469 u8 status[0x8];
6470 u8 reserved_at_8[0x18];
6471
6472 u8 syndrome[0x20];
6473
6474 u8 reserved_at_40[0x8];
6475 u8 xrqn[0x18];
6476
6477 u8 reserved_at_60[0x20];
6478 };
6479
6480 struct mlx5_ifc_create_xrq_in_bits {
6481 u8 opcode[0x10];
6482 u8 reserved_at_10[0x10];
6483
6484 u8 reserved_at_20[0x10];
6485 u8 op_mod[0x10];
6486
6487 u8 reserved_at_40[0x40];
6488
6489 struct mlx5_ifc_xrqc_bits xrq_context;
6490 };
6491
6492 struct mlx5_ifc_create_xrc_srq_out_bits {
6493 u8 status[0x8];
6494 u8 reserved_at_8[0x18];
6495
6496 u8 syndrome[0x20];
6497
6498 u8 reserved_at_40[0x8];
6499 u8 xrc_srqn[0x18];
6500
6501 u8 reserved_at_60[0x20];
6502 };
6503
6504 struct mlx5_ifc_create_xrc_srq_in_bits {
6505 u8 opcode[0x10];
6506 u8 reserved_at_10[0x10];
6507
6508 u8 reserved_at_20[0x10];
6509 u8 op_mod[0x10];
6510
6511 u8 reserved_at_40[0x40];
6512
6513 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6514
6515 u8 reserved_at_280[0x600];
6516
6517 u8 pas[0][0x40];
6518 };
6519
6520 struct mlx5_ifc_create_tis_out_bits {
6521 u8 status[0x8];
6522 u8 reserved_at_8[0x18];
6523
6524 u8 syndrome[0x20];
6525
6526 u8 reserved_at_40[0x8];
6527 u8 tisn[0x18];
6528
6529 u8 reserved_at_60[0x20];
6530 };
6531
6532 struct mlx5_ifc_create_tis_in_bits {
6533 u8 opcode[0x10];
6534 u8 reserved_at_10[0x10];
6535
6536 u8 reserved_at_20[0x10];
6537 u8 op_mod[0x10];
6538
6539 u8 reserved_at_40[0xc0];
6540
6541 struct mlx5_ifc_tisc_bits ctx;
6542 };
6543
6544 struct mlx5_ifc_create_tir_out_bits {
6545 u8 status[0x8];
6546 u8 reserved_at_8[0x18];
6547
6548 u8 syndrome[0x20];
6549
6550 u8 reserved_at_40[0x8];
6551 u8 tirn[0x18];
6552
6553 u8 reserved_at_60[0x20];
6554 };
6555
6556 struct mlx5_ifc_create_tir_in_bits {
6557 u8 opcode[0x10];
6558 u8 reserved_at_10[0x10];
6559
6560 u8 reserved_at_20[0x10];
6561 u8 op_mod[0x10];
6562
6563 u8 reserved_at_40[0xc0];
6564
6565 struct mlx5_ifc_tirc_bits ctx;
6566 };
6567
6568 struct mlx5_ifc_create_srq_out_bits {
6569 u8 status[0x8];
6570 u8 reserved_at_8[0x18];
6571
6572 u8 syndrome[0x20];
6573
6574 u8 reserved_at_40[0x8];
6575 u8 srqn[0x18];
6576
6577 u8 reserved_at_60[0x20];
6578 };
6579
6580 struct mlx5_ifc_create_srq_in_bits {
6581 u8 opcode[0x10];
6582 u8 reserved_at_10[0x10];
6583
6584 u8 reserved_at_20[0x10];
6585 u8 op_mod[0x10];
6586
6587 u8 reserved_at_40[0x40];
6588
6589 struct mlx5_ifc_srqc_bits srq_context_entry;
6590
6591 u8 reserved_at_280[0x600];
6592
6593 u8 pas[0][0x40];
6594 };
6595
6596 struct mlx5_ifc_create_sq_out_bits {
6597 u8 status[0x8];
6598 u8 reserved_at_8[0x18];
6599
6600 u8 syndrome[0x20];
6601
6602 u8 reserved_at_40[0x8];
6603 u8 sqn[0x18];
6604
6605 u8 reserved_at_60[0x20];
6606 };
6607
6608 struct mlx5_ifc_create_sq_in_bits {
6609 u8 opcode[0x10];
6610 u8 reserved_at_10[0x10];
6611
6612 u8 reserved_at_20[0x10];
6613 u8 op_mod[0x10];
6614
6615 u8 reserved_at_40[0xc0];
6616
6617 struct mlx5_ifc_sqc_bits ctx;
6618 };
6619
6620 struct mlx5_ifc_create_scheduling_element_out_bits {
6621 u8 status[0x8];
6622 u8 reserved_at_8[0x18];
6623
6624 u8 syndrome[0x20];
6625
6626 u8 reserved_at_40[0x40];
6627
6628 u8 scheduling_element_id[0x20];
6629
6630 u8 reserved_at_a0[0x160];
6631 };
6632
6633 struct mlx5_ifc_create_scheduling_element_in_bits {
6634 u8 opcode[0x10];
6635 u8 reserved_at_10[0x10];
6636
6637 u8 reserved_at_20[0x10];
6638 u8 op_mod[0x10];
6639
6640 u8 scheduling_hierarchy[0x8];
6641 u8 reserved_at_48[0x18];
6642
6643 u8 reserved_at_60[0xa0];
6644
6645 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6646
6647 u8 reserved_at_300[0x100];
6648 };
6649
6650 struct mlx5_ifc_create_rqt_out_bits {
6651 u8 status[0x8];
6652 u8 reserved_at_8[0x18];
6653
6654 u8 syndrome[0x20];
6655
6656 u8 reserved_at_40[0x8];
6657 u8 rqtn[0x18];
6658
6659 u8 reserved_at_60[0x20];
6660 };
6661
6662 struct mlx5_ifc_create_rqt_in_bits {
6663 u8 opcode[0x10];
6664 u8 reserved_at_10[0x10];
6665
6666 u8 reserved_at_20[0x10];
6667 u8 op_mod[0x10];
6668
6669 u8 reserved_at_40[0xc0];
6670
6671 struct mlx5_ifc_rqtc_bits rqt_context;
6672 };
6673
6674 struct mlx5_ifc_create_rq_out_bits {
6675 u8 status[0x8];
6676 u8 reserved_at_8[0x18];
6677
6678 u8 syndrome[0x20];
6679
6680 u8 reserved_at_40[0x8];
6681 u8 rqn[0x18];
6682
6683 u8 reserved_at_60[0x20];
6684 };
6685
6686 struct mlx5_ifc_create_rq_in_bits {
6687 u8 opcode[0x10];
6688 u8 reserved_at_10[0x10];
6689
6690 u8 reserved_at_20[0x10];
6691 u8 op_mod[0x10];
6692
6693 u8 reserved_at_40[0xc0];
6694
6695 struct mlx5_ifc_rqc_bits ctx;
6696 };
6697
6698 struct mlx5_ifc_create_rmp_out_bits {
6699 u8 status[0x8];
6700 u8 reserved_at_8[0x18];
6701
6702 u8 syndrome[0x20];
6703
6704 u8 reserved_at_40[0x8];
6705 u8 rmpn[0x18];
6706
6707 u8 reserved_at_60[0x20];
6708 };
6709
6710 struct mlx5_ifc_create_rmp_in_bits {
6711 u8 opcode[0x10];
6712 u8 reserved_at_10[0x10];
6713
6714 u8 reserved_at_20[0x10];
6715 u8 op_mod[0x10];
6716
6717 u8 reserved_at_40[0xc0];
6718
6719 struct mlx5_ifc_rmpc_bits ctx;
6720 };
6721
6722 struct mlx5_ifc_create_qp_out_bits {
6723 u8 status[0x8];
6724 u8 reserved_at_8[0x18];
6725
6726 u8 syndrome[0x20];
6727
6728 u8 reserved_at_40[0x8];
6729 u8 qpn[0x18];
6730
6731 u8 reserved_at_60[0x20];
6732 };
6733
6734 struct mlx5_ifc_create_qp_in_bits {
6735 u8 opcode[0x10];
6736 u8 reserved_at_10[0x10];
6737
6738 u8 reserved_at_20[0x10];
6739 u8 op_mod[0x10];
6740
6741 u8 reserved_at_40[0x40];
6742
6743 u8 opt_param_mask[0x20];
6744
6745 u8 reserved_at_a0[0x20];
6746
6747 struct mlx5_ifc_qpc_bits qpc;
6748
6749 u8 reserved_at_800[0x80];
6750
6751 u8 pas[0][0x40];
6752 };
6753
6754 struct mlx5_ifc_create_psv_out_bits {
6755 u8 status[0x8];
6756 u8 reserved_at_8[0x18];
6757
6758 u8 syndrome[0x20];
6759
6760 u8 reserved_at_40[0x40];
6761
6762 u8 reserved_at_80[0x8];
6763 u8 psv0_index[0x18];
6764
6765 u8 reserved_at_a0[0x8];
6766 u8 psv1_index[0x18];
6767
6768 u8 reserved_at_c0[0x8];
6769 u8 psv2_index[0x18];
6770
6771 u8 reserved_at_e0[0x8];
6772 u8 psv3_index[0x18];
6773 };
6774
6775 struct mlx5_ifc_create_psv_in_bits {
6776 u8 opcode[0x10];
6777 u8 reserved_at_10[0x10];
6778
6779 u8 reserved_at_20[0x10];
6780 u8 op_mod[0x10];
6781
6782 u8 num_psv[0x4];
6783 u8 reserved_at_44[0x4];
6784 u8 pd[0x18];
6785
6786 u8 reserved_at_60[0x20];
6787 };
6788
6789 struct mlx5_ifc_create_mkey_out_bits {
6790 u8 status[0x8];
6791 u8 reserved_at_8[0x18];
6792
6793 u8 syndrome[0x20];
6794
6795 u8 reserved_at_40[0x8];
6796 u8 mkey_index[0x18];
6797
6798 u8 reserved_at_60[0x20];
6799 };
6800
6801 struct mlx5_ifc_create_mkey_in_bits {
6802 u8 opcode[0x10];
6803 u8 reserved_at_10[0x10];
6804
6805 u8 reserved_at_20[0x10];
6806 u8 op_mod[0x10];
6807
6808 u8 reserved_at_40[0x20];
6809
6810 u8 pg_access[0x1];
6811 u8 reserved_at_61[0x1f];
6812
6813 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6814
6815 u8 reserved_at_280[0x80];
6816
6817 u8 translations_octword_actual_size[0x20];
6818
6819 u8 reserved_at_320[0x560];
6820
6821 u8 klm_pas_mtt[0][0x20];
6822 };
6823
6824 struct mlx5_ifc_create_flow_table_out_bits {
6825 u8 status[0x8];
6826 u8 reserved_at_8[0x18];
6827
6828 u8 syndrome[0x20];
6829
6830 u8 reserved_at_40[0x8];
6831 u8 table_id[0x18];
6832
6833 u8 reserved_at_60[0x20];
6834 };
6835
6836 struct mlx5_ifc_flow_table_context_bits {
6837 u8 encap_en[0x1];
6838 u8 decap_en[0x1];
6839 u8 reserved_at_2[0x2];
6840 u8 table_miss_action[0x4];
6841 u8 level[0x8];
6842 u8 reserved_at_10[0x8];
6843 u8 log_size[0x8];
6844
6845 u8 reserved_at_20[0x8];
6846 u8 table_miss_id[0x18];
6847
6848 u8 reserved_at_40[0x8];
6849 u8 lag_master_next_table_id[0x18];
6850
6851 u8 reserved_at_60[0xe0];
6852 };
6853
6854 struct mlx5_ifc_create_flow_table_in_bits {
6855 u8 opcode[0x10];
6856 u8 reserved_at_10[0x10];
6857
6858 u8 reserved_at_20[0x10];
6859 u8 op_mod[0x10];
6860
6861 u8 other_vport[0x1];
6862 u8 reserved_at_41[0xf];
6863 u8 vport_number[0x10];
6864
6865 u8 reserved_at_60[0x20];
6866
6867 u8 table_type[0x8];
6868 u8 reserved_at_88[0x18];
6869
6870 u8 reserved_at_a0[0x20];
6871
6872 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6873 };
6874
6875 struct mlx5_ifc_create_flow_group_out_bits {
6876 u8 status[0x8];
6877 u8 reserved_at_8[0x18];
6878
6879 u8 syndrome[0x20];
6880
6881 u8 reserved_at_40[0x8];
6882 u8 group_id[0x18];
6883
6884 u8 reserved_at_60[0x20];
6885 };
6886
6887 enum {
6888 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6889 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6890 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6891 };
6892
6893 struct mlx5_ifc_create_flow_group_in_bits {
6894 u8 opcode[0x10];
6895 u8 reserved_at_10[0x10];
6896
6897 u8 reserved_at_20[0x10];
6898 u8 op_mod[0x10];
6899
6900 u8 other_vport[0x1];
6901 u8 reserved_at_41[0xf];
6902 u8 vport_number[0x10];
6903
6904 u8 reserved_at_60[0x20];
6905
6906 u8 table_type[0x8];
6907 u8 reserved_at_88[0x18];
6908
6909 u8 reserved_at_a0[0x8];
6910 u8 table_id[0x18];
6911
6912 u8 reserved_at_c0[0x20];
6913
6914 u8 start_flow_index[0x20];
6915
6916 u8 reserved_at_100[0x20];
6917
6918 u8 end_flow_index[0x20];
6919
6920 u8 reserved_at_140[0xa0];
6921
6922 u8 reserved_at_1e0[0x18];
6923 u8 match_criteria_enable[0x8];
6924
6925 struct mlx5_ifc_fte_match_param_bits match_criteria;
6926
6927 u8 reserved_at_1200[0xe00];
6928 };
6929
6930 struct mlx5_ifc_create_eq_out_bits {
6931 u8 status[0x8];
6932 u8 reserved_at_8[0x18];
6933
6934 u8 syndrome[0x20];
6935
6936 u8 reserved_at_40[0x18];
6937 u8 eq_number[0x8];
6938
6939 u8 reserved_at_60[0x20];
6940 };
6941
6942 struct mlx5_ifc_create_eq_in_bits {
6943 u8 opcode[0x10];
6944 u8 reserved_at_10[0x10];
6945
6946 u8 reserved_at_20[0x10];
6947 u8 op_mod[0x10];
6948
6949 u8 reserved_at_40[0x40];
6950
6951 struct mlx5_ifc_eqc_bits eq_context_entry;
6952
6953 u8 reserved_at_280[0x40];
6954
6955 u8 event_bitmask[0x40];
6956
6957 u8 reserved_at_300[0x580];
6958
6959 u8 pas[0][0x40];
6960 };
6961
6962 struct mlx5_ifc_create_dct_out_bits {
6963 u8 status[0x8];
6964 u8 reserved_at_8[0x18];
6965
6966 u8 syndrome[0x20];
6967
6968 u8 reserved_at_40[0x8];
6969 u8 dctn[0x18];
6970
6971 u8 reserved_at_60[0x20];
6972 };
6973
6974 struct mlx5_ifc_create_dct_in_bits {
6975 u8 opcode[0x10];
6976 u8 reserved_at_10[0x10];
6977
6978 u8 reserved_at_20[0x10];
6979 u8 op_mod[0x10];
6980
6981 u8 reserved_at_40[0x40];
6982
6983 struct mlx5_ifc_dctc_bits dct_context_entry;
6984
6985 u8 reserved_at_280[0x180];
6986 };
6987
6988 struct mlx5_ifc_create_cq_out_bits {
6989 u8 status[0x8];
6990 u8 reserved_at_8[0x18];
6991
6992 u8 syndrome[0x20];
6993
6994 u8 reserved_at_40[0x8];
6995 u8 cqn[0x18];
6996
6997 u8 reserved_at_60[0x20];
6998 };
6999
7000 struct mlx5_ifc_create_cq_in_bits {
7001 u8 opcode[0x10];
7002 u8 reserved_at_10[0x10];
7003
7004 u8 reserved_at_20[0x10];
7005 u8 op_mod[0x10];
7006
7007 u8 reserved_at_40[0x40];
7008
7009 struct mlx5_ifc_cqc_bits cq_context;
7010
7011 u8 reserved_at_280[0x600];
7012
7013 u8 pas[0][0x40];
7014 };
7015
7016 struct mlx5_ifc_config_int_moderation_out_bits {
7017 u8 status[0x8];
7018 u8 reserved_at_8[0x18];
7019
7020 u8 syndrome[0x20];
7021
7022 u8 reserved_at_40[0x4];
7023 u8 min_delay[0xc];
7024 u8 int_vector[0x10];
7025
7026 u8 reserved_at_60[0x20];
7027 };
7028
7029 enum {
7030 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7031 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7032 };
7033
7034 struct mlx5_ifc_config_int_moderation_in_bits {
7035 u8 opcode[0x10];
7036 u8 reserved_at_10[0x10];
7037
7038 u8 reserved_at_20[0x10];
7039 u8 op_mod[0x10];
7040
7041 u8 reserved_at_40[0x4];
7042 u8 min_delay[0xc];
7043 u8 int_vector[0x10];
7044
7045 u8 reserved_at_60[0x20];
7046 };
7047
7048 struct mlx5_ifc_attach_to_mcg_out_bits {
7049 u8 status[0x8];
7050 u8 reserved_at_8[0x18];
7051
7052 u8 syndrome[0x20];
7053
7054 u8 reserved_at_40[0x40];
7055 };
7056
7057 struct mlx5_ifc_attach_to_mcg_in_bits {
7058 u8 opcode[0x10];
7059 u8 reserved_at_10[0x10];
7060
7061 u8 reserved_at_20[0x10];
7062 u8 op_mod[0x10];
7063
7064 u8 reserved_at_40[0x8];
7065 u8 qpn[0x18];
7066
7067 u8 reserved_at_60[0x20];
7068
7069 u8 multicast_gid[16][0x8];
7070 };
7071
7072 struct mlx5_ifc_arm_xrq_out_bits {
7073 u8 status[0x8];
7074 u8 reserved_at_8[0x18];
7075
7076 u8 syndrome[0x20];
7077
7078 u8 reserved_at_40[0x40];
7079 };
7080
7081 struct mlx5_ifc_arm_xrq_in_bits {
7082 u8 opcode[0x10];
7083 u8 reserved_at_10[0x10];
7084
7085 u8 reserved_at_20[0x10];
7086 u8 op_mod[0x10];
7087
7088 u8 reserved_at_40[0x8];
7089 u8 xrqn[0x18];
7090
7091 u8 reserved_at_60[0x10];
7092 u8 lwm[0x10];
7093 };
7094
7095 struct mlx5_ifc_arm_xrc_srq_out_bits {
7096 u8 status[0x8];
7097 u8 reserved_at_8[0x18];
7098
7099 u8 syndrome[0x20];
7100
7101 u8 reserved_at_40[0x40];
7102 };
7103
7104 enum {
7105 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7106 };
7107
7108 struct mlx5_ifc_arm_xrc_srq_in_bits {
7109 u8 opcode[0x10];
7110 u8 reserved_at_10[0x10];
7111
7112 u8 reserved_at_20[0x10];
7113 u8 op_mod[0x10];
7114
7115 u8 reserved_at_40[0x8];
7116 u8 xrc_srqn[0x18];
7117
7118 u8 reserved_at_60[0x10];
7119 u8 lwm[0x10];
7120 };
7121
7122 struct mlx5_ifc_arm_rq_out_bits {
7123 u8 status[0x8];
7124 u8 reserved_at_8[0x18];
7125
7126 u8 syndrome[0x20];
7127
7128 u8 reserved_at_40[0x40];
7129 };
7130
7131 enum {
7132 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7133 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7134 };
7135
7136 struct mlx5_ifc_arm_rq_in_bits {
7137 u8 opcode[0x10];
7138 u8 reserved_at_10[0x10];
7139
7140 u8 reserved_at_20[0x10];
7141 u8 op_mod[0x10];
7142
7143 u8 reserved_at_40[0x8];
7144 u8 srq_number[0x18];
7145
7146 u8 reserved_at_60[0x10];
7147 u8 lwm[0x10];
7148 };
7149
7150 struct mlx5_ifc_arm_dct_out_bits {
7151 u8 status[0x8];
7152 u8 reserved_at_8[0x18];
7153
7154 u8 syndrome[0x20];
7155
7156 u8 reserved_at_40[0x40];
7157 };
7158
7159 struct mlx5_ifc_arm_dct_in_bits {
7160 u8 opcode[0x10];
7161 u8 reserved_at_10[0x10];
7162
7163 u8 reserved_at_20[0x10];
7164 u8 op_mod[0x10];
7165
7166 u8 reserved_at_40[0x8];
7167 u8 dct_number[0x18];
7168
7169 u8 reserved_at_60[0x20];
7170 };
7171
7172 struct mlx5_ifc_alloc_xrcd_out_bits {
7173 u8 status[0x8];
7174 u8 reserved_at_8[0x18];
7175
7176 u8 syndrome[0x20];
7177
7178 u8 reserved_at_40[0x8];
7179 u8 xrcd[0x18];
7180
7181 u8 reserved_at_60[0x20];
7182 };
7183
7184 struct mlx5_ifc_alloc_xrcd_in_bits {
7185 u8 opcode[0x10];
7186 u8 reserved_at_10[0x10];
7187
7188 u8 reserved_at_20[0x10];
7189 u8 op_mod[0x10];
7190
7191 u8 reserved_at_40[0x40];
7192 };
7193
7194 struct mlx5_ifc_alloc_uar_out_bits {
7195 u8 status[0x8];
7196 u8 reserved_at_8[0x18];
7197
7198 u8 syndrome[0x20];
7199
7200 u8 reserved_at_40[0x8];
7201 u8 uar[0x18];
7202
7203 u8 reserved_at_60[0x20];
7204 };
7205
7206 struct mlx5_ifc_alloc_uar_in_bits {
7207 u8 opcode[0x10];
7208 u8 reserved_at_10[0x10];
7209
7210 u8 reserved_at_20[0x10];
7211 u8 op_mod[0x10];
7212
7213 u8 reserved_at_40[0x40];
7214 };
7215
7216 struct mlx5_ifc_alloc_transport_domain_out_bits {
7217 u8 status[0x8];
7218 u8 reserved_at_8[0x18];
7219
7220 u8 syndrome[0x20];
7221
7222 u8 reserved_at_40[0x8];
7223 u8 transport_domain[0x18];
7224
7225 u8 reserved_at_60[0x20];
7226 };
7227
7228 struct mlx5_ifc_alloc_transport_domain_in_bits {
7229 u8 opcode[0x10];
7230 u8 reserved_at_10[0x10];
7231
7232 u8 reserved_at_20[0x10];
7233 u8 op_mod[0x10];
7234
7235 u8 reserved_at_40[0x40];
7236 };
7237
7238 struct mlx5_ifc_alloc_q_counter_out_bits {
7239 u8 status[0x8];
7240 u8 reserved_at_8[0x18];
7241
7242 u8 syndrome[0x20];
7243
7244 u8 reserved_at_40[0x18];
7245 u8 counter_set_id[0x8];
7246
7247 u8 reserved_at_60[0x20];
7248 };
7249
7250 struct mlx5_ifc_alloc_q_counter_in_bits {
7251 u8 opcode[0x10];
7252 u8 reserved_at_10[0x10];
7253
7254 u8 reserved_at_20[0x10];
7255 u8 op_mod[0x10];
7256
7257 u8 reserved_at_40[0x40];
7258 };
7259
7260 struct mlx5_ifc_alloc_pd_out_bits {
7261 u8 status[0x8];
7262 u8 reserved_at_8[0x18];
7263
7264 u8 syndrome[0x20];
7265
7266 u8 reserved_at_40[0x8];
7267 u8 pd[0x18];
7268
7269 u8 reserved_at_60[0x20];
7270 };
7271
7272 struct mlx5_ifc_alloc_pd_in_bits {
7273 u8 opcode[0x10];
7274 u8 reserved_at_10[0x10];
7275
7276 u8 reserved_at_20[0x10];
7277 u8 op_mod[0x10];
7278
7279 u8 reserved_at_40[0x40];
7280 };
7281
7282 struct mlx5_ifc_alloc_flow_counter_out_bits {
7283 u8 status[0x8];
7284 u8 reserved_at_8[0x18];
7285
7286 u8 syndrome[0x20];
7287
7288 u8 flow_counter_id[0x20];
7289
7290 u8 reserved_at_60[0x20];
7291 };
7292
7293 struct mlx5_ifc_alloc_flow_counter_in_bits {
7294 u8 opcode[0x10];
7295 u8 reserved_at_10[0x10];
7296
7297 u8 reserved_at_20[0x10];
7298 u8 op_mod[0x10];
7299
7300 u8 reserved_at_40[0x40];
7301 };
7302
7303 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7304 u8 status[0x8];
7305 u8 reserved_at_8[0x18];
7306
7307 u8 syndrome[0x20];
7308
7309 u8 reserved_at_40[0x40];
7310 };
7311
7312 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7313 u8 opcode[0x10];
7314 u8 reserved_at_10[0x10];
7315
7316 u8 reserved_at_20[0x10];
7317 u8 op_mod[0x10];
7318
7319 u8 reserved_at_40[0x20];
7320
7321 u8 reserved_at_60[0x10];
7322 u8 vxlan_udp_port[0x10];
7323 };
7324
7325 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7326 u8 status[0x8];
7327 u8 reserved_at_8[0x18];
7328
7329 u8 syndrome[0x20];
7330
7331 u8 reserved_at_40[0x40];
7332 };
7333
7334 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7335 u8 opcode[0x10];
7336 u8 reserved_at_10[0x10];
7337
7338 u8 reserved_at_20[0x10];
7339 u8 op_mod[0x10];
7340
7341 u8 reserved_at_40[0x10];
7342 u8 rate_limit_index[0x10];
7343
7344 u8 reserved_at_60[0x20];
7345
7346 u8 rate_limit[0x20];
7347
7348 u8 burst_upper_bound[0x20];
7349
7350 u8 reserved_at_c0[0x10];
7351 u8 typical_packet_size[0x10];
7352
7353 u8 reserved_at_e0[0x120];
7354 };
7355
7356 struct mlx5_ifc_access_register_out_bits {
7357 u8 status[0x8];
7358 u8 reserved_at_8[0x18];
7359
7360 u8 syndrome[0x20];
7361
7362 u8 reserved_at_40[0x40];
7363
7364 u8 register_data[0][0x20];
7365 };
7366
7367 enum {
7368 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7369 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7370 };
7371
7372 struct mlx5_ifc_access_register_in_bits {
7373 u8 opcode[0x10];
7374 u8 reserved_at_10[0x10];
7375
7376 u8 reserved_at_20[0x10];
7377 u8 op_mod[0x10];
7378
7379 u8 reserved_at_40[0x10];
7380 u8 register_id[0x10];
7381
7382 u8 argument[0x20];
7383
7384 u8 register_data[0][0x20];
7385 };
7386
7387 struct mlx5_ifc_sltp_reg_bits {
7388 u8 status[0x4];
7389 u8 version[0x4];
7390 u8 local_port[0x8];
7391 u8 pnat[0x2];
7392 u8 reserved_at_12[0x2];
7393 u8 lane[0x4];
7394 u8 reserved_at_18[0x8];
7395
7396 u8 reserved_at_20[0x20];
7397
7398 u8 reserved_at_40[0x7];
7399 u8 polarity[0x1];
7400 u8 ob_tap0[0x8];
7401 u8 ob_tap1[0x8];
7402 u8 ob_tap2[0x8];
7403
7404 u8 reserved_at_60[0xc];
7405 u8 ob_preemp_mode[0x4];
7406 u8 ob_reg[0x8];
7407 u8 ob_bias[0x8];
7408
7409 u8 reserved_at_80[0x20];
7410 };
7411
7412 struct mlx5_ifc_slrg_reg_bits {
7413 u8 status[0x4];
7414 u8 version[0x4];
7415 u8 local_port[0x8];
7416 u8 pnat[0x2];
7417 u8 reserved_at_12[0x2];
7418 u8 lane[0x4];
7419 u8 reserved_at_18[0x8];
7420
7421 u8 time_to_link_up[0x10];
7422 u8 reserved_at_30[0xc];
7423 u8 grade_lane_speed[0x4];
7424
7425 u8 grade_version[0x8];
7426 u8 grade[0x18];
7427
7428 u8 reserved_at_60[0x4];
7429 u8 height_grade_type[0x4];
7430 u8 height_grade[0x18];
7431
7432 u8 height_dz[0x10];
7433 u8 height_dv[0x10];
7434
7435 u8 reserved_at_a0[0x10];
7436 u8 height_sigma[0x10];
7437
7438 u8 reserved_at_c0[0x20];
7439
7440 u8 reserved_at_e0[0x4];
7441 u8 phase_grade_type[0x4];
7442 u8 phase_grade[0x18];
7443
7444 u8 reserved_at_100[0x8];
7445 u8 phase_eo_pos[0x8];
7446 u8 reserved_at_110[0x8];
7447 u8 phase_eo_neg[0x8];
7448
7449 u8 ffe_set_tested[0x10];
7450 u8 test_errors_per_lane[0x10];
7451 };
7452
7453 struct mlx5_ifc_pvlc_reg_bits {
7454 u8 reserved_at_0[0x8];
7455 u8 local_port[0x8];
7456 u8 reserved_at_10[0x10];
7457
7458 u8 reserved_at_20[0x1c];
7459 u8 vl_hw_cap[0x4];
7460
7461 u8 reserved_at_40[0x1c];
7462 u8 vl_admin[0x4];
7463
7464 u8 reserved_at_60[0x1c];
7465 u8 vl_operational[0x4];
7466 };
7467
7468 struct mlx5_ifc_pude_reg_bits {
7469 u8 swid[0x8];
7470 u8 local_port[0x8];
7471 u8 reserved_at_10[0x4];
7472 u8 admin_status[0x4];
7473 u8 reserved_at_18[0x4];
7474 u8 oper_status[0x4];
7475
7476 u8 reserved_at_20[0x60];
7477 };
7478
7479 struct mlx5_ifc_ptys_reg_bits {
7480 u8 reserved_at_0[0x1];
7481 u8 an_disable_admin[0x1];
7482 u8 an_disable_cap[0x1];
7483 u8 reserved_at_3[0x5];
7484 u8 local_port[0x8];
7485 u8 reserved_at_10[0xd];
7486 u8 proto_mask[0x3];
7487
7488 u8 an_status[0x4];
7489 u8 reserved_at_24[0x3c];
7490
7491 u8 eth_proto_capability[0x20];
7492
7493 u8 ib_link_width_capability[0x10];
7494 u8 ib_proto_capability[0x10];
7495
7496 u8 reserved_at_a0[0x20];
7497
7498 u8 eth_proto_admin[0x20];
7499
7500 u8 ib_link_width_admin[0x10];
7501 u8 ib_proto_admin[0x10];
7502
7503 u8 reserved_at_100[0x20];
7504
7505 u8 eth_proto_oper[0x20];
7506
7507 u8 ib_link_width_oper[0x10];
7508 u8 ib_proto_oper[0x10];
7509
7510 u8 reserved_at_160[0x1c];
7511 u8 connector_type[0x4];
7512
7513 u8 eth_proto_lp_advertise[0x20];
7514
7515 u8 reserved_at_1a0[0x60];
7516 };
7517
7518 struct mlx5_ifc_mlcr_reg_bits {
7519 u8 reserved_at_0[0x8];
7520 u8 local_port[0x8];
7521 u8 reserved_at_10[0x20];
7522
7523 u8 beacon_duration[0x10];
7524 u8 reserved_at_40[0x10];
7525
7526 u8 beacon_remain[0x10];
7527 };
7528
7529 struct mlx5_ifc_ptas_reg_bits {
7530 u8 reserved_at_0[0x20];
7531
7532 u8 algorithm_options[0x10];
7533 u8 reserved_at_30[0x4];
7534 u8 repetitions_mode[0x4];
7535 u8 num_of_repetitions[0x8];
7536
7537 u8 grade_version[0x8];
7538 u8 height_grade_type[0x4];
7539 u8 phase_grade_type[0x4];
7540 u8 height_grade_weight[0x8];
7541 u8 phase_grade_weight[0x8];
7542
7543 u8 gisim_measure_bits[0x10];
7544 u8 adaptive_tap_measure_bits[0x10];
7545
7546 u8 ber_bath_high_error_threshold[0x10];
7547 u8 ber_bath_mid_error_threshold[0x10];
7548
7549 u8 ber_bath_low_error_threshold[0x10];
7550 u8 one_ratio_high_threshold[0x10];
7551
7552 u8 one_ratio_high_mid_threshold[0x10];
7553 u8 one_ratio_low_mid_threshold[0x10];
7554
7555 u8 one_ratio_low_threshold[0x10];
7556 u8 ndeo_error_threshold[0x10];
7557
7558 u8 mixer_offset_step_size[0x10];
7559 u8 reserved_at_110[0x8];
7560 u8 mix90_phase_for_voltage_bath[0x8];
7561
7562 u8 mixer_offset_start[0x10];
7563 u8 mixer_offset_end[0x10];
7564
7565 u8 reserved_at_140[0x15];
7566 u8 ber_test_time[0xb];
7567 };
7568
7569 struct mlx5_ifc_pspa_reg_bits {
7570 u8 swid[0x8];
7571 u8 local_port[0x8];
7572 u8 sub_port[0x8];
7573 u8 reserved_at_18[0x8];
7574
7575 u8 reserved_at_20[0x20];
7576 };
7577
7578 struct mlx5_ifc_pqdr_reg_bits {
7579 u8 reserved_at_0[0x8];
7580 u8 local_port[0x8];
7581 u8 reserved_at_10[0x5];
7582 u8 prio[0x3];
7583 u8 reserved_at_18[0x6];
7584 u8 mode[0x2];
7585
7586 u8 reserved_at_20[0x20];
7587
7588 u8 reserved_at_40[0x10];
7589 u8 min_threshold[0x10];
7590
7591 u8 reserved_at_60[0x10];
7592 u8 max_threshold[0x10];
7593
7594 u8 reserved_at_80[0x10];
7595 u8 mark_probability_denominator[0x10];
7596
7597 u8 reserved_at_a0[0x60];
7598 };
7599
7600 struct mlx5_ifc_ppsc_reg_bits {
7601 u8 reserved_at_0[0x8];
7602 u8 local_port[0x8];
7603 u8 reserved_at_10[0x10];
7604
7605 u8 reserved_at_20[0x60];
7606
7607 u8 reserved_at_80[0x1c];
7608 u8 wrps_admin[0x4];
7609
7610 u8 reserved_at_a0[0x1c];
7611 u8 wrps_status[0x4];
7612
7613 u8 reserved_at_c0[0x8];
7614 u8 up_threshold[0x8];
7615 u8 reserved_at_d0[0x8];
7616 u8 down_threshold[0x8];
7617
7618 u8 reserved_at_e0[0x20];
7619
7620 u8 reserved_at_100[0x1c];
7621 u8 srps_admin[0x4];
7622
7623 u8 reserved_at_120[0x1c];
7624 u8 srps_status[0x4];
7625
7626 u8 reserved_at_140[0x40];
7627 };
7628
7629 struct mlx5_ifc_pplr_reg_bits {
7630 u8 reserved_at_0[0x8];
7631 u8 local_port[0x8];
7632 u8 reserved_at_10[0x10];
7633
7634 u8 reserved_at_20[0x8];
7635 u8 lb_cap[0x8];
7636 u8 reserved_at_30[0x8];
7637 u8 lb_en[0x8];
7638 };
7639
7640 struct mlx5_ifc_pplm_reg_bits {
7641 u8 reserved_at_0[0x8];
7642 u8 local_port[0x8];
7643 u8 reserved_at_10[0x10];
7644
7645 u8 reserved_at_20[0x20];
7646
7647 u8 port_profile_mode[0x8];
7648 u8 static_port_profile[0x8];
7649 u8 active_port_profile[0x8];
7650 u8 reserved_at_58[0x8];
7651
7652 u8 retransmission_active[0x8];
7653 u8 fec_mode_active[0x18];
7654
7655 u8 reserved_at_80[0x20];
7656 };
7657
7658 struct mlx5_ifc_ppcnt_reg_bits {
7659 u8 swid[0x8];
7660 u8 local_port[0x8];
7661 u8 pnat[0x2];
7662 u8 reserved_at_12[0x8];
7663 u8 grp[0x6];
7664
7665 u8 clr[0x1];
7666 u8 reserved_at_21[0x1c];
7667 u8 prio_tc[0x3];
7668
7669 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7670 };
7671
7672 struct mlx5_ifc_mpcnt_reg_bits {
7673 u8 reserved_at_0[0x8];
7674 u8 pcie_index[0x8];
7675 u8 reserved_at_10[0xa];
7676 u8 grp[0x6];
7677
7678 u8 clr[0x1];
7679 u8 reserved_at_21[0x1f];
7680
7681 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7682 };
7683
7684 struct mlx5_ifc_ppad_reg_bits {
7685 u8 reserved_at_0[0x3];
7686 u8 single_mac[0x1];
7687 u8 reserved_at_4[0x4];
7688 u8 local_port[0x8];
7689 u8 mac_47_32[0x10];
7690
7691 u8 mac_31_0[0x20];
7692
7693 u8 reserved_at_40[0x40];
7694 };
7695
7696 struct mlx5_ifc_pmtu_reg_bits {
7697 u8 reserved_at_0[0x8];
7698 u8 local_port[0x8];
7699 u8 reserved_at_10[0x10];
7700
7701 u8 max_mtu[0x10];
7702 u8 reserved_at_30[0x10];
7703
7704 u8 admin_mtu[0x10];
7705 u8 reserved_at_50[0x10];
7706
7707 u8 oper_mtu[0x10];
7708 u8 reserved_at_70[0x10];
7709 };
7710
7711 struct mlx5_ifc_pmpr_reg_bits {
7712 u8 reserved_at_0[0x8];
7713 u8 module[0x8];
7714 u8 reserved_at_10[0x10];
7715
7716 u8 reserved_at_20[0x18];
7717 u8 attenuation_5g[0x8];
7718
7719 u8 reserved_at_40[0x18];
7720 u8 attenuation_7g[0x8];
7721
7722 u8 reserved_at_60[0x18];
7723 u8 attenuation_12g[0x8];
7724 };
7725
7726 struct mlx5_ifc_pmpe_reg_bits {
7727 u8 reserved_at_0[0x8];
7728 u8 module[0x8];
7729 u8 reserved_at_10[0xc];
7730 u8 module_status[0x4];
7731
7732 u8 reserved_at_20[0x60];
7733 };
7734
7735 struct mlx5_ifc_pmpc_reg_bits {
7736 u8 module_state_updated[32][0x8];
7737 };
7738
7739 struct mlx5_ifc_pmlpn_reg_bits {
7740 u8 reserved_at_0[0x4];
7741 u8 mlpn_status[0x4];
7742 u8 local_port[0x8];
7743 u8 reserved_at_10[0x10];
7744
7745 u8 e[0x1];
7746 u8 reserved_at_21[0x1f];
7747 };
7748
7749 struct mlx5_ifc_pmlp_reg_bits {
7750 u8 rxtx[0x1];
7751 u8 reserved_at_1[0x7];
7752 u8 local_port[0x8];
7753 u8 reserved_at_10[0x8];
7754 u8 width[0x8];
7755
7756 u8 lane0_module_mapping[0x20];
7757
7758 u8 lane1_module_mapping[0x20];
7759
7760 u8 lane2_module_mapping[0x20];
7761
7762 u8 lane3_module_mapping[0x20];
7763
7764 u8 reserved_at_a0[0x160];
7765 };
7766
7767 struct mlx5_ifc_pmaos_reg_bits {
7768 u8 reserved_at_0[0x8];
7769 u8 module[0x8];
7770 u8 reserved_at_10[0x4];
7771 u8 admin_status[0x4];
7772 u8 reserved_at_18[0x4];
7773 u8 oper_status[0x4];
7774
7775 u8 ase[0x1];
7776 u8 ee[0x1];
7777 u8 reserved_at_22[0x1c];
7778 u8 e[0x2];
7779
7780 u8 reserved_at_40[0x40];
7781 };
7782
7783 struct mlx5_ifc_plpc_reg_bits {
7784 u8 reserved_at_0[0x4];
7785 u8 profile_id[0xc];
7786 u8 reserved_at_10[0x4];
7787 u8 proto_mask[0x4];
7788 u8 reserved_at_18[0x8];
7789
7790 u8 reserved_at_20[0x10];
7791 u8 lane_speed[0x10];
7792
7793 u8 reserved_at_40[0x17];
7794 u8 lpbf[0x1];
7795 u8 fec_mode_policy[0x8];
7796
7797 u8 retransmission_capability[0x8];
7798 u8 fec_mode_capability[0x18];
7799
7800 u8 retransmission_support_admin[0x8];
7801 u8 fec_mode_support_admin[0x18];
7802
7803 u8 retransmission_request_admin[0x8];
7804 u8 fec_mode_request_admin[0x18];
7805
7806 u8 reserved_at_c0[0x80];
7807 };
7808
7809 struct mlx5_ifc_plib_reg_bits {
7810 u8 reserved_at_0[0x8];
7811 u8 local_port[0x8];
7812 u8 reserved_at_10[0x8];
7813 u8 ib_port[0x8];
7814
7815 u8 reserved_at_20[0x60];
7816 };
7817
7818 struct mlx5_ifc_plbf_reg_bits {
7819 u8 reserved_at_0[0x8];
7820 u8 local_port[0x8];
7821 u8 reserved_at_10[0xd];
7822 u8 lbf_mode[0x3];
7823
7824 u8 reserved_at_20[0x20];
7825 };
7826
7827 struct mlx5_ifc_pipg_reg_bits {
7828 u8 reserved_at_0[0x8];
7829 u8 local_port[0x8];
7830 u8 reserved_at_10[0x10];
7831
7832 u8 dic[0x1];
7833 u8 reserved_at_21[0x19];
7834 u8 ipg[0x4];
7835 u8 reserved_at_3e[0x2];
7836 };
7837
7838 struct mlx5_ifc_pifr_reg_bits {
7839 u8 reserved_at_0[0x8];
7840 u8 local_port[0x8];
7841 u8 reserved_at_10[0x10];
7842
7843 u8 reserved_at_20[0xe0];
7844
7845 u8 port_filter[8][0x20];
7846
7847 u8 port_filter_update_en[8][0x20];
7848 };
7849
7850 struct mlx5_ifc_pfcc_reg_bits {
7851 u8 reserved_at_0[0x8];
7852 u8 local_port[0x8];
7853 u8 reserved_at_10[0x10];
7854
7855 u8 ppan[0x4];
7856 u8 reserved_at_24[0x4];
7857 u8 prio_mask_tx[0x8];
7858 u8 reserved_at_30[0x8];
7859 u8 prio_mask_rx[0x8];
7860
7861 u8 pptx[0x1];
7862 u8 aptx[0x1];
7863 u8 reserved_at_42[0x6];
7864 u8 pfctx[0x8];
7865 u8 reserved_at_50[0x10];
7866
7867 u8 pprx[0x1];
7868 u8 aprx[0x1];
7869 u8 reserved_at_62[0x6];
7870 u8 pfcrx[0x8];
7871 u8 reserved_at_70[0x10];
7872
7873 u8 reserved_at_80[0x80];
7874 };
7875
7876 struct mlx5_ifc_pelc_reg_bits {
7877 u8 op[0x4];
7878 u8 reserved_at_4[0x4];
7879 u8 local_port[0x8];
7880 u8 reserved_at_10[0x10];
7881
7882 u8 op_admin[0x8];
7883 u8 op_capability[0x8];
7884 u8 op_request[0x8];
7885 u8 op_active[0x8];
7886
7887 u8 admin[0x40];
7888
7889 u8 capability[0x40];
7890
7891 u8 request[0x40];
7892
7893 u8 active[0x40];
7894
7895 u8 reserved_at_140[0x80];
7896 };
7897
7898 struct mlx5_ifc_peir_reg_bits {
7899 u8 reserved_at_0[0x8];
7900 u8 local_port[0x8];
7901 u8 reserved_at_10[0x10];
7902
7903 u8 reserved_at_20[0xc];
7904 u8 error_count[0x4];
7905 u8 reserved_at_30[0x10];
7906
7907 u8 reserved_at_40[0xc];
7908 u8 lane[0x4];
7909 u8 reserved_at_50[0x8];
7910 u8 error_type[0x8];
7911 };
7912
7913 struct mlx5_ifc_pcam_enhanced_features_bits {
7914 u8 reserved_at_0[0x7b];
7915
7916 u8 rx_buffer_fullness_counters[0x1];
7917 u8 ptys_connector_type[0x1];
7918 u8 reserved_at_7d[0x1];
7919 u8 ppcnt_discard_group[0x1];
7920 u8 ppcnt_statistical_group[0x1];
7921 };
7922
7923 struct mlx5_ifc_pcam_reg_bits {
7924 u8 reserved_at_0[0x8];
7925 u8 feature_group[0x8];
7926 u8 reserved_at_10[0x8];
7927 u8 access_reg_group[0x8];
7928
7929 u8 reserved_at_20[0x20];
7930
7931 union {
7932 u8 reserved_at_0[0x80];
7933 } port_access_reg_cap_mask;
7934
7935 u8 reserved_at_c0[0x80];
7936
7937 union {
7938 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7939 u8 reserved_at_0[0x80];
7940 } feature_cap_mask;
7941
7942 u8 reserved_at_1c0[0xc0];
7943 };
7944
7945 struct mlx5_ifc_mcam_enhanced_features_bits {
7946 u8 reserved_at_0[0x7b];
7947 u8 pcie_outbound_stalled[0x1];
7948 u8 tx_overflow_buffer_pkt[0x1];
7949 u8 mtpps_enh_out_per_adj[0x1];
7950 u8 mtpps_fs[0x1];
7951 u8 pcie_performance_group[0x1];
7952 };
7953
7954 struct mlx5_ifc_mcam_access_reg_bits {
7955 u8 reserved_at_0[0x1c];
7956 u8 mcda[0x1];
7957 u8 mcc[0x1];
7958 u8 mcqi[0x1];
7959 u8 reserved_at_1f[0x1];
7960
7961 u8 regs_95_to_64[0x20];
7962 u8 regs_63_to_32[0x20];
7963 u8 regs_31_to_0[0x20];
7964 };
7965
7966 struct mlx5_ifc_mcam_reg_bits {
7967 u8 reserved_at_0[0x8];
7968 u8 feature_group[0x8];
7969 u8 reserved_at_10[0x8];
7970 u8 access_reg_group[0x8];
7971
7972 u8 reserved_at_20[0x20];
7973
7974 union {
7975 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7976 u8 reserved_at_0[0x80];
7977 } mng_access_reg_cap_mask;
7978
7979 u8 reserved_at_c0[0x80];
7980
7981 union {
7982 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7983 u8 reserved_at_0[0x80];
7984 } mng_feature_cap_mask;
7985
7986 u8 reserved_at_1c0[0x80];
7987 };
7988
7989 struct mlx5_ifc_qcam_access_reg_cap_mask {
7990 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
7991 u8 qpdpm[0x1];
7992 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
7993 u8 qdpm[0x1];
7994 u8 qpts[0x1];
7995 u8 qcap[0x1];
7996 u8 qcam_access_reg_cap_mask_0[0x1];
7997 };
7998
7999 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8000 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8001 u8 qpts_trust_both[0x1];
8002 };
8003
8004 struct mlx5_ifc_qcam_reg_bits {
8005 u8 reserved_at_0[0x8];
8006 u8 feature_group[0x8];
8007 u8 reserved_at_10[0x8];
8008 u8 access_reg_group[0x8];
8009 u8 reserved_at_20[0x20];
8010
8011 union {
8012 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8013 u8 reserved_at_0[0x80];
8014 } qos_access_reg_cap_mask;
8015
8016 u8 reserved_at_c0[0x80];
8017
8018 union {
8019 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8020 u8 reserved_at_0[0x80];
8021 } qos_feature_cap_mask;
8022
8023 u8 reserved_at_1c0[0x80];
8024 };
8025
8026 struct mlx5_ifc_pcap_reg_bits {
8027 u8 reserved_at_0[0x8];
8028 u8 local_port[0x8];
8029 u8 reserved_at_10[0x10];
8030
8031 u8 port_capability_mask[4][0x20];
8032 };
8033
8034 struct mlx5_ifc_paos_reg_bits {
8035 u8 swid[0x8];
8036 u8 local_port[0x8];
8037 u8 reserved_at_10[0x4];
8038 u8 admin_status[0x4];
8039 u8 reserved_at_18[0x4];
8040 u8 oper_status[0x4];
8041
8042 u8 ase[0x1];
8043 u8 ee[0x1];
8044 u8 reserved_at_22[0x1c];
8045 u8 e[0x2];
8046
8047 u8 reserved_at_40[0x40];
8048 };
8049
8050 struct mlx5_ifc_pamp_reg_bits {
8051 u8 reserved_at_0[0x8];
8052 u8 opamp_group[0x8];
8053 u8 reserved_at_10[0xc];
8054 u8 opamp_group_type[0x4];
8055
8056 u8 start_index[0x10];
8057 u8 reserved_at_30[0x4];
8058 u8 num_of_indices[0xc];
8059
8060 u8 index_data[18][0x10];
8061 };
8062
8063 struct mlx5_ifc_pcmr_reg_bits {
8064 u8 reserved_at_0[0x8];
8065 u8 local_port[0x8];
8066 u8 reserved_at_10[0x2e];
8067 u8 fcs_cap[0x1];
8068 u8 reserved_at_3f[0x1f];
8069 u8 fcs_chk[0x1];
8070 u8 reserved_at_5f[0x1];
8071 };
8072
8073 struct mlx5_ifc_lane_2_module_mapping_bits {
8074 u8 reserved_at_0[0x6];
8075 u8 rx_lane[0x2];
8076 u8 reserved_at_8[0x6];
8077 u8 tx_lane[0x2];
8078 u8 reserved_at_10[0x8];
8079 u8 module[0x8];
8080 };
8081
8082 struct mlx5_ifc_bufferx_reg_bits {
8083 u8 reserved_at_0[0x6];
8084 u8 lossy[0x1];
8085 u8 epsb[0x1];
8086 u8 reserved_at_8[0xc];
8087 u8 size[0xc];
8088
8089 u8 xoff_threshold[0x10];
8090 u8 xon_threshold[0x10];
8091 };
8092
8093 struct mlx5_ifc_set_node_in_bits {
8094 u8 node_description[64][0x8];
8095 };
8096
8097 struct mlx5_ifc_register_power_settings_bits {
8098 u8 reserved_at_0[0x18];
8099 u8 power_settings_level[0x8];
8100
8101 u8 reserved_at_20[0x60];
8102 };
8103
8104 struct mlx5_ifc_register_host_endianness_bits {
8105 u8 he[0x1];
8106 u8 reserved_at_1[0x1f];
8107
8108 u8 reserved_at_20[0x60];
8109 };
8110
8111 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8112 u8 reserved_at_0[0x20];
8113
8114 u8 mkey[0x20];
8115
8116 u8 addressh_63_32[0x20];
8117
8118 u8 addressl_31_0[0x20];
8119 };
8120
8121 struct mlx5_ifc_ud_adrs_vector_bits {
8122 u8 dc_key[0x40];
8123
8124 u8 ext[0x1];
8125 u8 reserved_at_41[0x7];
8126 u8 destination_qp_dct[0x18];
8127
8128 u8 static_rate[0x4];
8129 u8 sl_eth_prio[0x4];
8130 u8 fl[0x1];
8131 u8 mlid[0x7];
8132 u8 rlid_udp_sport[0x10];
8133
8134 u8 reserved_at_80[0x20];
8135
8136 u8 rmac_47_16[0x20];
8137
8138 u8 rmac_15_0[0x10];
8139 u8 tclass[0x8];
8140 u8 hop_limit[0x8];
8141
8142 u8 reserved_at_e0[0x1];
8143 u8 grh[0x1];
8144 u8 reserved_at_e2[0x2];
8145 u8 src_addr_index[0x8];
8146 u8 flow_label[0x14];
8147
8148 u8 rgid_rip[16][0x8];
8149 };
8150
8151 struct mlx5_ifc_pages_req_event_bits {
8152 u8 reserved_at_0[0x10];
8153 u8 function_id[0x10];
8154
8155 u8 num_pages[0x20];
8156
8157 u8 reserved_at_40[0xa0];
8158 };
8159
8160 struct mlx5_ifc_eqe_bits {
8161 u8 reserved_at_0[0x8];
8162 u8 event_type[0x8];
8163 u8 reserved_at_10[0x8];
8164 u8 event_sub_type[0x8];
8165
8166 u8 reserved_at_20[0xe0];
8167
8168 union mlx5_ifc_event_auto_bits event_data;
8169
8170 u8 reserved_at_1e0[0x10];
8171 u8 signature[0x8];
8172 u8 reserved_at_1f8[0x7];
8173 u8 owner[0x1];
8174 };
8175
8176 enum {
8177 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8178 };
8179
8180 struct mlx5_ifc_cmd_queue_entry_bits {
8181 u8 type[0x8];
8182 u8 reserved_at_8[0x18];
8183
8184 u8 input_length[0x20];
8185
8186 u8 input_mailbox_pointer_63_32[0x20];
8187
8188 u8 input_mailbox_pointer_31_9[0x17];
8189 u8 reserved_at_77[0x9];
8190
8191 u8 command_input_inline_data[16][0x8];
8192
8193 u8 command_output_inline_data[16][0x8];
8194
8195 u8 output_mailbox_pointer_63_32[0x20];
8196
8197 u8 output_mailbox_pointer_31_9[0x17];
8198 u8 reserved_at_1b7[0x9];
8199
8200 u8 output_length[0x20];
8201
8202 u8 token[0x8];
8203 u8 signature[0x8];
8204 u8 reserved_at_1f0[0x8];
8205 u8 status[0x7];
8206 u8 ownership[0x1];
8207 };
8208
8209 struct mlx5_ifc_cmd_out_bits {
8210 u8 status[0x8];
8211 u8 reserved_at_8[0x18];
8212
8213 u8 syndrome[0x20];
8214
8215 u8 command_output[0x20];
8216 };
8217
8218 struct mlx5_ifc_cmd_in_bits {
8219 u8 opcode[0x10];
8220 u8 reserved_at_10[0x10];
8221
8222 u8 reserved_at_20[0x10];
8223 u8 op_mod[0x10];
8224
8225 u8 command[0][0x20];
8226 };
8227
8228 struct mlx5_ifc_cmd_if_box_bits {
8229 u8 mailbox_data[512][0x8];
8230
8231 u8 reserved_at_1000[0x180];
8232
8233 u8 next_pointer_63_32[0x20];
8234
8235 u8 next_pointer_31_10[0x16];
8236 u8 reserved_at_11b6[0xa];
8237
8238 u8 block_number[0x20];
8239
8240 u8 reserved_at_11e0[0x8];
8241 u8 token[0x8];
8242 u8 ctrl_signature[0x8];
8243 u8 signature[0x8];
8244 };
8245
8246 struct mlx5_ifc_mtt_bits {
8247 u8 ptag_63_32[0x20];
8248
8249 u8 ptag_31_8[0x18];
8250 u8 reserved_at_38[0x6];
8251 u8 wr_en[0x1];
8252 u8 rd_en[0x1];
8253 };
8254
8255 struct mlx5_ifc_query_wol_rol_out_bits {
8256 u8 status[0x8];
8257 u8 reserved_at_8[0x18];
8258
8259 u8 syndrome[0x20];
8260
8261 u8 reserved_at_40[0x10];
8262 u8 rol_mode[0x8];
8263 u8 wol_mode[0x8];
8264
8265 u8 reserved_at_60[0x20];
8266 };
8267
8268 struct mlx5_ifc_query_wol_rol_in_bits {
8269 u8 opcode[0x10];
8270 u8 reserved_at_10[0x10];
8271
8272 u8 reserved_at_20[0x10];
8273 u8 op_mod[0x10];
8274
8275 u8 reserved_at_40[0x40];
8276 };
8277
8278 struct mlx5_ifc_set_wol_rol_out_bits {
8279 u8 status[0x8];
8280 u8 reserved_at_8[0x18];
8281
8282 u8 syndrome[0x20];
8283
8284 u8 reserved_at_40[0x40];
8285 };
8286
8287 struct mlx5_ifc_set_wol_rol_in_bits {
8288 u8 opcode[0x10];
8289 u8 reserved_at_10[0x10];
8290
8291 u8 reserved_at_20[0x10];
8292 u8 op_mod[0x10];
8293
8294 u8 rol_mode_valid[0x1];
8295 u8 wol_mode_valid[0x1];
8296 u8 reserved_at_42[0xe];
8297 u8 rol_mode[0x8];
8298 u8 wol_mode[0x8];
8299
8300 u8 reserved_at_60[0x20];
8301 };
8302
8303 enum {
8304 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8305 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8306 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8307 };
8308
8309 enum {
8310 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8311 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8312 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8313 };
8314
8315 enum {
8316 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8317 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8318 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8319 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8320 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8321 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8322 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8323 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8324 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8325 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8326 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8327 };
8328
8329 struct mlx5_ifc_initial_seg_bits {
8330 u8 fw_rev_minor[0x10];
8331 u8 fw_rev_major[0x10];
8332
8333 u8 cmd_interface_rev[0x10];
8334 u8 fw_rev_subminor[0x10];
8335
8336 u8 reserved_at_40[0x40];
8337
8338 u8 cmdq_phy_addr_63_32[0x20];
8339
8340 u8 cmdq_phy_addr_31_12[0x14];
8341 u8 reserved_at_b4[0x2];
8342 u8 nic_interface[0x2];
8343 u8 log_cmdq_size[0x4];
8344 u8 log_cmdq_stride[0x4];
8345
8346 u8 command_doorbell_vector[0x20];
8347
8348 u8 reserved_at_e0[0xf00];
8349
8350 u8 initializing[0x1];
8351 u8 reserved_at_fe1[0x4];
8352 u8 nic_interface_supported[0x3];
8353 u8 reserved_at_fe8[0x18];
8354
8355 struct mlx5_ifc_health_buffer_bits health_buffer;
8356
8357 u8 no_dram_nic_offset[0x20];
8358
8359 u8 reserved_at_1220[0x6e40];
8360
8361 u8 reserved_at_8060[0x1f];
8362 u8 clear_int[0x1];
8363
8364 u8 health_syndrome[0x8];
8365 u8 health_counter[0x18];
8366
8367 u8 reserved_at_80a0[0x17fc0];
8368 };
8369
8370 struct mlx5_ifc_mtpps_reg_bits {
8371 u8 reserved_at_0[0xc];
8372 u8 cap_number_of_pps_pins[0x4];
8373 u8 reserved_at_10[0x4];
8374 u8 cap_max_num_of_pps_in_pins[0x4];
8375 u8 reserved_at_18[0x4];
8376 u8 cap_max_num_of_pps_out_pins[0x4];
8377
8378 u8 reserved_at_20[0x24];
8379 u8 cap_pin_3_mode[0x4];
8380 u8 reserved_at_48[0x4];
8381 u8 cap_pin_2_mode[0x4];
8382 u8 reserved_at_50[0x4];
8383 u8 cap_pin_1_mode[0x4];
8384 u8 reserved_at_58[0x4];
8385 u8 cap_pin_0_mode[0x4];
8386
8387 u8 reserved_at_60[0x4];
8388 u8 cap_pin_7_mode[0x4];
8389 u8 reserved_at_68[0x4];
8390 u8 cap_pin_6_mode[0x4];
8391 u8 reserved_at_70[0x4];
8392 u8 cap_pin_5_mode[0x4];
8393 u8 reserved_at_78[0x4];
8394 u8 cap_pin_4_mode[0x4];
8395
8396 u8 field_select[0x20];
8397 u8 reserved_at_a0[0x60];
8398
8399 u8 enable[0x1];
8400 u8 reserved_at_101[0xb];
8401 u8 pattern[0x4];
8402 u8 reserved_at_110[0x4];
8403 u8 pin_mode[0x4];
8404 u8 pin[0x8];
8405
8406 u8 reserved_at_120[0x20];
8407
8408 u8 time_stamp[0x40];
8409
8410 u8 out_pulse_duration[0x10];
8411 u8 out_periodic_adjustment[0x10];
8412 u8 enhanced_out_periodic_adjustment[0x20];
8413
8414 u8 reserved_at_1c0[0x20];
8415 };
8416
8417 struct mlx5_ifc_mtppse_reg_bits {
8418 u8 reserved_at_0[0x18];
8419 u8 pin[0x8];
8420 u8 event_arm[0x1];
8421 u8 reserved_at_21[0x1b];
8422 u8 event_generation_mode[0x4];
8423 u8 reserved_at_40[0x40];
8424 };
8425
8426 struct mlx5_ifc_mcqi_cap_bits {
8427 u8 supported_info_bitmask[0x20];
8428
8429 u8 component_size[0x20];
8430
8431 u8 max_component_size[0x20];
8432
8433 u8 log_mcda_word_size[0x4];
8434 u8 reserved_at_64[0xc];
8435 u8 mcda_max_write_size[0x10];
8436
8437 u8 rd_en[0x1];
8438 u8 reserved_at_81[0x1];
8439 u8 match_chip_id[0x1];
8440 u8 match_psid[0x1];
8441 u8 check_user_timestamp[0x1];
8442 u8 match_base_guid_mac[0x1];
8443 u8 reserved_at_86[0x1a];
8444 };
8445
8446 struct mlx5_ifc_mcqi_reg_bits {
8447 u8 read_pending_component[0x1];
8448 u8 reserved_at_1[0xf];
8449 u8 component_index[0x10];
8450
8451 u8 reserved_at_20[0x20];
8452
8453 u8 reserved_at_40[0x1b];
8454 u8 info_type[0x5];
8455
8456 u8 info_size[0x20];
8457
8458 u8 offset[0x20];
8459
8460 u8 reserved_at_a0[0x10];
8461 u8 data_size[0x10];
8462
8463 u8 data[0][0x20];
8464 };
8465
8466 struct mlx5_ifc_mcc_reg_bits {
8467 u8 reserved_at_0[0x4];
8468 u8 time_elapsed_since_last_cmd[0xc];
8469 u8 reserved_at_10[0x8];
8470 u8 instruction[0x8];
8471
8472 u8 reserved_at_20[0x10];
8473 u8 component_index[0x10];
8474
8475 u8 reserved_at_40[0x8];
8476 u8 update_handle[0x18];
8477
8478 u8 handle_owner_type[0x4];
8479 u8 handle_owner_host_id[0x4];
8480 u8 reserved_at_68[0x1];
8481 u8 control_progress[0x7];
8482 u8 error_code[0x8];
8483 u8 reserved_at_78[0x4];
8484 u8 control_state[0x4];
8485
8486 u8 component_size[0x20];
8487
8488 u8 reserved_at_a0[0x60];
8489 };
8490
8491 struct mlx5_ifc_mcda_reg_bits {
8492 u8 reserved_at_0[0x8];
8493 u8 update_handle[0x18];
8494
8495 u8 offset[0x20];
8496
8497 u8 reserved_at_40[0x10];
8498 u8 size[0x10];
8499
8500 u8 reserved_at_60[0x20];
8501
8502 u8 data[0][0x20];
8503 };
8504
8505 union mlx5_ifc_ports_control_registers_document_bits {
8506 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8507 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8508 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8509 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8510 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8511 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8512 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8513 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8514 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8515 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8516 struct mlx5_ifc_paos_reg_bits paos_reg;
8517 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8518 struct mlx5_ifc_peir_reg_bits peir_reg;
8519 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8520 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8521 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8522 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8523 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8524 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8525 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8526 struct mlx5_ifc_plib_reg_bits plib_reg;
8527 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8528 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8529 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8530 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8531 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8532 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8533 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8534 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8535 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8536 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8537 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8538 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8539 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8540 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8541 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8542 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8543 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8544 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8545 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8546 struct mlx5_ifc_pude_reg_bits pude_reg;
8547 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8548 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8549 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8550 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8551 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8552 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8553 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8554 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8555 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8556 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8557 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8558 u8 reserved_at_0[0x60e0];
8559 };
8560
8561 union mlx5_ifc_debug_enhancements_document_bits {
8562 struct mlx5_ifc_health_buffer_bits health_buffer;
8563 u8 reserved_at_0[0x200];
8564 };
8565
8566 union mlx5_ifc_uplink_pci_interface_document_bits {
8567 struct mlx5_ifc_initial_seg_bits initial_seg;
8568 u8 reserved_at_0[0x20060];
8569 };
8570
8571 struct mlx5_ifc_set_flow_table_root_out_bits {
8572 u8 status[0x8];
8573 u8 reserved_at_8[0x18];
8574
8575 u8 syndrome[0x20];
8576
8577 u8 reserved_at_40[0x40];
8578 };
8579
8580 struct mlx5_ifc_set_flow_table_root_in_bits {
8581 u8 opcode[0x10];
8582 u8 reserved_at_10[0x10];
8583
8584 u8 reserved_at_20[0x10];
8585 u8 op_mod[0x10];
8586
8587 u8 other_vport[0x1];
8588 u8 reserved_at_41[0xf];
8589 u8 vport_number[0x10];
8590
8591 u8 reserved_at_60[0x20];
8592
8593 u8 table_type[0x8];
8594 u8 reserved_at_88[0x18];
8595
8596 u8 reserved_at_a0[0x8];
8597 u8 table_id[0x18];
8598
8599 u8 reserved_at_c0[0x8];
8600 u8 underlay_qpn[0x18];
8601 u8 reserved_at_e0[0x120];
8602 };
8603
8604 enum {
8605 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8606 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8607 };
8608
8609 struct mlx5_ifc_modify_flow_table_out_bits {
8610 u8 status[0x8];
8611 u8 reserved_at_8[0x18];
8612
8613 u8 syndrome[0x20];
8614
8615 u8 reserved_at_40[0x40];
8616 };
8617
8618 struct mlx5_ifc_modify_flow_table_in_bits {
8619 u8 opcode[0x10];
8620 u8 reserved_at_10[0x10];
8621
8622 u8 reserved_at_20[0x10];
8623 u8 op_mod[0x10];
8624
8625 u8 other_vport[0x1];
8626 u8 reserved_at_41[0xf];
8627 u8 vport_number[0x10];
8628
8629 u8 reserved_at_60[0x10];
8630 u8 modify_field_select[0x10];
8631
8632 u8 table_type[0x8];
8633 u8 reserved_at_88[0x18];
8634
8635 u8 reserved_at_a0[0x8];
8636 u8 table_id[0x18];
8637
8638 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8639 };
8640
8641 struct mlx5_ifc_ets_tcn_config_reg_bits {
8642 u8 g[0x1];
8643 u8 b[0x1];
8644 u8 r[0x1];
8645 u8 reserved_at_3[0x9];
8646 u8 group[0x4];
8647 u8 reserved_at_10[0x9];
8648 u8 bw_allocation[0x7];
8649
8650 u8 reserved_at_20[0xc];
8651 u8 max_bw_units[0x4];
8652 u8 reserved_at_30[0x8];
8653 u8 max_bw_value[0x8];
8654 };
8655
8656 struct mlx5_ifc_ets_global_config_reg_bits {
8657 u8 reserved_at_0[0x2];
8658 u8 r[0x1];
8659 u8 reserved_at_3[0x1d];
8660
8661 u8 reserved_at_20[0xc];
8662 u8 max_bw_units[0x4];
8663 u8 reserved_at_30[0x8];
8664 u8 max_bw_value[0x8];
8665 };
8666
8667 struct mlx5_ifc_qetc_reg_bits {
8668 u8 reserved_at_0[0x8];
8669 u8 port_number[0x8];
8670 u8 reserved_at_10[0x30];
8671
8672 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8673 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8674 };
8675
8676 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8677 u8 e[0x1];
8678 u8 reserved_at_01[0x0b];
8679 u8 prio[0x04];
8680 };
8681
8682 struct mlx5_ifc_qpdpm_reg_bits {
8683 u8 reserved_at_0[0x8];
8684 u8 local_port[0x8];
8685 u8 reserved_at_10[0x10];
8686 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8687 };
8688
8689 struct mlx5_ifc_qpts_reg_bits {
8690 u8 reserved_at_0[0x8];
8691 u8 local_port[0x8];
8692 u8 reserved_at_10[0x2d];
8693 u8 trust_state[0x3];
8694 };
8695
8696 struct mlx5_ifc_qtct_reg_bits {
8697 u8 reserved_at_0[0x8];
8698 u8 port_number[0x8];
8699 u8 reserved_at_10[0xd];
8700 u8 prio[0x3];
8701
8702 u8 reserved_at_20[0x1d];
8703 u8 tclass[0x3];
8704 };
8705
8706 struct mlx5_ifc_mcia_reg_bits {
8707 u8 l[0x1];
8708 u8 reserved_at_1[0x7];
8709 u8 module[0x8];
8710 u8 reserved_at_10[0x8];
8711 u8 status[0x8];
8712
8713 u8 i2c_device_address[0x8];
8714 u8 page_number[0x8];
8715 u8 device_address[0x10];
8716
8717 u8 reserved_at_40[0x10];
8718 u8 size[0x10];
8719
8720 u8 reserved_at_60[0x20];
8721
8722 u8 dword_0[0x20];
8723 u8 dword_1[0x20];
8724 u8 dword_2[0x20];
8725 u8 dword_3[0x20];
8726 u8 dword_4[0x20];
8727 u8 dword_5[0x20];
8728 u8 dword_6[0x20];
8729 u8 dword_7[0x20];
8730 u8 dword_8[0x20];
8731 u8 dword_9[0x20];
8732 u8 dword_10[0x20];
8733 u8 dword_11[0x20];
8734 };
8735
8736 struct mlx5_ifc_dcbx_param_bits {
8737 u8 dcbx_cee_cap[0x1];
8738 u8 dcbx_ieee_cap[0x1];
8739 u8 dcbx_standby_cap[0x1];
8740 u8 reserved_at_0[0x5];
8741 u8 port_number[0x8];
8742 u8 reserved_at_10[0xa];
8743 u8 max_application_table_size[6];
8744 u8 reserved_at_20[0x15];
8745 u8 version_oper[0x3];
8746 u8 reserved_at_38[5];
8747 u8 version_admin[0x3];
8748 u8 willing_admin[0x1];
8749 u8 reserved_at_41[0x3];
8750 u8 pfc_cap_oper[0x4];
8751 u8 reserved_at_48[0x4];
8752 u8 pfc_cap_admin[0x4];
8753 u8 reserved_at_50[0x4];
8754 u8 num_of_tc_oper[0x4];
8755 u8 reserved_at_58[0x4];
8756 u8 num_of_tc_admin[0x4];
8757 u8 remote_willing[0x1];
8758 u8 reserved_at_61[3];
8759 u8 remote_pfc_cap[4];
8760 u8 reserved_at_68[0x14];
8761 u8 remote_num_of_tc[0x4];
8762 u8 reserved_at_80[0x18];
8763 u8 error[0x8];
8764 u8 reserved_at_a0[0x160];
8765 };
8766
8767 struct mlx5_ifc_lagc_bits {
8768 u8 reserved_at_0[0x1d];
8769 u8 lag_state[0x3];
8770
8771 u8 reserved_at_20[0x14];
8772 u8 tx_remap_affinity_2[0x4];
8773 u8 reserved_at_38[0x4];
8774 u8 tx_remap_affinity_1[0x4];
8775 };
8776
8777 struct mlx5_ifc_create_lag_out_bits {
8778 u8 status[0x8];
8779 u8 reserved_at_8[0x18];
8780
8781 u8 syndrome[0x20];
8782
8783 u8 reserved_at_40[0x40];
8784 };
8785
8786 struct mlx5_ifc_create_lag_in_bits {
8787 u8 opcode[0x10];
8788 u8 reserved_at_10[0x10];
8789
8790 u8 reserved_at_20[0x10];
8791 u8 op_mod[0x10];
8792
8793 struct mlx5_ifc_lagc_bits ctx;
8794 };
8795
8796 struct mlx5_ifc_modify_lag_out_bits {
8797 u8 status[0x8];
8798 u8 reserved_at_8[0x18];
8799
8800 u8 syndrome[0x20];
8801
8802 u8 reserved_at_40[0x40];
8803 };
8804
8805 struct mlx5_ifc_modify_lag_in_bits {
8806 u8 opcode[0x10];
8807 u8 reserved_at_10[0x10];
8808
8809 u8 reserved_at_20[0x10];
8810 u8 op_mod[0x10];
8811
8812 u8 reserved_at_40[0x20];
8813 u8 field_select[0x20];
8814
8815 struct mlx5_ifc_lagc_bits ctx;
8816 };
8817
8818 struct mlx5_ifc_query_lag_out_bits {
8819 u8 status[0x8];
8820 u8 reserved_at_8[0x18];
8821
8822 u8 syndrome[0x20];
8823
8824 u8 reserved_at_40[0x40];
8825
8826 struct mlx5_ifc_lagc_bits ctx;
8827 };
8828
8829 struct mlx5_ifc_query_lag_in_bits {
8830 u8 opcode[0x10];
8831 u8 reserved_at_10[0x10];
8832
8833 u8 reserved_at_20[0x10];
8834 u8 op_mod[0x10];
8835
8836 u8 reserved_at_40[0x40];
8837 };
8838
8839 struct mlx5_ifc_destroy_lag_out_bits {
8840 u8 status[0x8];
8841 u8 reserved_at_8[0x18];
8842
8843 u8 syndrome[0x20];
8844
8845 u8 reserved_at_40[0x40];
8846 };
8847
8848 struct mlx5_ifc_destroy_lag_in_bits {
8849 u8 opcode[0x10];
8850 u8 reserved_at_10[0x10];
8851
8852 u8 reserved_at_20[0x10];
8853 u8 op_mod[0x10];
8854
8855 u8 reserved_at_40[0x40];
8856 };
8857
8858 struct mlx5_ifc_create_vport_lag_out_bits {
8859 u8 status[0x8];
8860 u8 reserved_at_8[0x18];
8861
8862 u8 syndrome[0x20];
8863
8864 u8 reserved_at_40[0x40];
8865 };
8866
8867 struct mlx5_ifc_create_vport_lag_in_bits {
8868 u8 opcode[0x10];
8869 u8 reserved_at_10[0x10];
8870
8871 u8 reserved_at_20[0x10];
8872 u8 op_mod[0x10];
8873
8874 u8 reserved_at_40[0x40];
8875 };
8876
8877 struct mlx5_ifc_destroy_vport_lag_out_bits {
8878 u8 status[0x8];
8879 u8 reserved_at_8[0x18];
8880
8881 u8 syndrome[0x20];
8882
8883 u8 reserved_at_40[0x40];
8884 };
8885
8886 struct mlx5_ifc_destroy_vport_lag_in_bits {
8887 u8 opcode[0x10];
8888 u8 reserved_at_10[0x10];
8889
8890 u8 reserved_at_20[0x10];
8891 u8 op_mod[0x10];
8892
8893 u8 reserved_at_40[0x40];
8894 };
8895
8896 struct mlx5_ifc_alloc_memic_in_bits {
8897 u8 opcode[0x10];
8898 u8 reserved_at_10[0x10];
8899
8900 u8 reserved_at_20[0x10];
8901 u8 op_mod[0x10];
8902
8903 u8 reserved_at_30[0x20];
8904
8905 u8 reserved_at_40[0x18];
8906 u8 log_memic_addr_alignment[0x8];
8907
8908 u8 range_start_addr[0x40];
8909
8910 u8 range_size[0x20];
8911
8912 u8 memic_size[0x20];
8913 };
8914
8915 struct mlx5_ifc_alloc_memic_out_bits {
8916 u8 status[0x8];
8917 u8 reserved_at_8[0x18];
8918
8919 u8 syndrome[0x20];
8920
8921 u8 memic_start_addr[0x40];
8922 };
8923
8924 struct mlx5_ifc_dealloc_memic_in_bits {
8925 u8 opcode[0x10];
8926 u8 reserved_at_10[0x10];
8927
8928 u8 reserved_at_20[0x10];
8929 u8 op_mod[0x10];
8930
8931 u8 reserved_at_40[0x40];
8932
8933 u8 memic_start_addr[0x40];
8934
8935 u8 memic_size[0x20];
8936
8937 u8 reserved_at_e0[0x20];
8938 };
8939
8940 struct mlx5_ifc_dealloc_memic_out_bits {
8941 u8 status[0x8];
8942 u8 reserved_at_8[0x18];
8943
8944 u8 syndrome[0x20];
8945
8946 u8 reserved_at_40[0x40];
8947 };
8948
8949 #endif /* MLX5_IFC_H */
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