2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS
= 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED
= 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED
= 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED
= 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED
= 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT
= 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED
= 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION
= 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR
= 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR
= 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED
= 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT
= 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR
= 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR
= 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR
= 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR
= 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE
= 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT
= 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT
= 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT
= 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT
= 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT
= 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION
= 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST
= 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR
= 0x20,
66 MLX5_MODIFY_TIR_BITMASK_LRO
= 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE
= 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH
= 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN
= 0x3
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
= 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
= 0x3,
78 MLX5_CMD_OP_QUERY_HCA_CAP
= 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER
= 0x101,
80 MLX5_CMD_OP_INIT_HCA
= 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA
= 0x103,
82 MLX5_CMD_OP_ENABLE_HCA
= 0x104,
83 MLX5_CMD_OP_DISABLE_HCA
= 0x105,
84 MLX5_CMD_OP_QUERY_PAGES
= 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES
= 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP
= 0x109,
87 MLX5_CMD_OP_QUERY_ISSI
= 0x10a,
88 MLX5_CMD_OP_SET_ISSI
= 0x10b,
89 MLX5_CMD_OP_SET_DRIVER_VERSION
= 0x10d,
90 MLX5_CMD_OP_CREATE_MKEY
= 0x200,
91 MLX5_CMD_OP_QUERY_MKEY
= 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY
= 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS
= 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME
= 0x204,
95 MLX5_CMD_OP_ALLOC_MEMIC
= 0x205,
96 MLX5_CMD_OP_DEALLOC_MEMIC
= 0x206,
97 MLX5_CMD_OP_CREATE_EQ
= 0x301,
98 MLX5_CMD_OP_DESTROY_EQ
= 0x302,
99 MLX5_CMD_OP_QUERY_EQ
= 0x303,
100 MLX5_CMD_OP_GEN_EQE
= 0x304,
101 MLX5_CMD_OP_CREATE_CQ
= 0x400,
102 MLX5_CMD_OP_DESTROY_CQ
= 0x401,
103 MLX5_CMD_OP_QUERY_CQ
= 0x402,
104 MLX5_CMD_OP_MODIFY_CQ
= 0x403,
105 MLX5_CMD_OP_CREATE_QP
= 0x500,
106 MLX5_CMD_OP_DESTROY_QP
= 0x501,
107 MLX5_CMD_OP_RST2INIT_QP
= 0x502,
108 MLX5_CMD_OP_INIT2RTR_QP
= 0x503,
109 MLX5_CMD_OP_RTR2RTS_QP
= 0x504,
110 MLX5_CMD_OP_RTS2RTS_QP
= 0x505,
111 MLX5_CMD_OP_SQERR2RTS_QP
= 0x506,
112 MLX5_CMD_OP_2ERR_QP
= 0x507,
113 MLX5_CMD_OP_2RST_QP
= 0x50a,
114 MLX5_CMD_OP_QUERY_QP
= 0x50b,
115 MLX5_CMD_OP_SQD_RTS_QP
= 0x50c,
116 MLX5_CMD_OP_INIT2INIT_QP
= 0x50e,
117 MLX5_CMD_OP_CREATE_PSV
= 0x600,
118 MLX5_CMD_OP_DESTROY_PSV
= 0x601,
119 MLX5_CMD_OP_CREATE_SRQ
= 0x700,
120 MLX5_CMD_OP_DESTROY_SRQ
= 0x701,
121 MLX5_CMD_OP_QUERY_SRQ
= 0x702,
122 MLX5_CMD_OP_ARM_RQ
= 0x703,
123 MLX5_CMD_OP_CREATE_XRC_SRQ
= 0x705,
124 MLX5_CMD_OP_DESTROY_XRC_SRQ
= 0x706,
125 MLX5_CMD_OP_QUERY_XRC_SRQ
= 0x707,
126 MLX5_CMD_OP_ARM_XRC_SRQ
= 0x708,
127 MLX5_CMD_OP_CREATE_DCT
= 0x710,
128 MLX5_CMD_OP_DESTROY_DCT
= 0x711,
129 MLX5_CMD_OP_DRAIN_DCT
= 0x712,
130 MLX5_CMD_OP_QUERY_DCT
= 0x713,
131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION
= 0x714,
132 MLX5_CMD_OP_CREATE_XRQ
= 0x717,
133 MLX5_CMD_OP_DESTROY_XRQ
= 0x718,
134 MLX5_CMD_OP_QUERY_XRQ
= 0x719,
135 MLX5_CMD_OP_ARM_XRQ
= 0x71a,
136 MLX5_CMD_OP_QUERY_VPORT_STATE
= 0x750,
137 MLX5_CMD_OP_MODIFY_VPORT_STATE
= 0x751,
138 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT
= 0x752,
139 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT
= 0x753,
140 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT
= 0x754,
141 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT
= 0x755,
142 MLX5_CMD_OP_QUERY_ROCE_ADDRESS
= 0x760,
143 MLX5_CMD_OP_SET_ROCE_ADDRESS
= 0x761,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT
= 0x762,
145 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT
= 0x763,
146 MLX5_CMD_OP_QUERY_HCA_VPORT_GID
= 0x764,
147 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY
= 0x765,
148 MLX5_CMD_OP_QUERY_VPORT_COUNTER
= 0x770,
149 MLX5_CMD_OP_ALLOC_Q_COUNTER
= 0x771,
150 MLX5_CMD_OP_DEALLOC_Q_COUNTER
= 0x772,
151 MLX5_CMD_OP_QUERY_Q_COUNTER
= 0x773,
152 MLX5_CMD_OP_SET_PP_RATE_LIMIT
= 0x780,
153 MLX5_CMD_OP_QUERY_RATE_LIMIT
= 0x781,
154 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT
= 0x782,
155 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT
= 0x783,
156 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT
= 0x784,
157 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT
= 0x785,
158 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT
= 0x786,
159 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT
= 0x787,
160 MLX5_CMD_OP_ALLOC_PD
= 0x800,
161 MLX5_CMD_OP_DEALLOC_PD
= 0x801,
162 MLX5_CMD_OP_ALLOC_UAR
= 0x802,
163 MLX5_CMD_OP_DEALLOC_UAR
= 0x803,
164 MLX5_CMD_OP_CONFIG_INT_MODERATION
= 0x804,
165 MLX5_CMD_OP_ACCESS_REG
= 0x805,
166 MLX5_CMD_OP_ATTACH_TO_MCG
= 0x806,
167 MLX5_CMD_OP_DETACH_FROM_MCG
= 0x807,
168 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG
= 0x80a,
169 MLX5_CMD_OP_MAD_IFC
= 0x50d,
170 MLX5_CMD_OP_QUERY_MAD_DEMUX
= 0x80b,
171 MLX5_CMD_OP_SET_MAD_DEMUX
= 0x80c,
172 MLX5_CMD_OP_NOP
= 0x80d,
173 MLX5_CMD_OP_ALLOC_XRCD
= 0x80e,
174 MLX5_CMD_OP_DEALLOC_XRCD
= 0x80f,
175 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN
= 0x816,
176 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN
= 0x817,
177 MLX5_CMD_OP_QUERY_CONG_STATUS
= 0x822,
178 MLX5_CMD_OP_MODIFY_CONG_STATUS
= 0x823,
179 MLX5_CMD_OP_QUERY_CONG_PARAMS
= 0x824,
180 MLX5_CMD_OP_MODIFY_CONG_PARAMS
= 0x825,
181 MLX5_CMD_OP_QUERY_CONG_STATISTICS
= 0x826,
182 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT
= 0x827,
183 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT
= 0x828,
184 MLX5_CMD_OP_SET_L2_TABLE_ENTRY
= 0x829,
185 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY
= 0x82a,
186 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY
= 0x82b,
187 MLX5_CMD_OP_SET_WOL_ROL
= 0x830,
188 MLX5_CMD_OP_QUERY_WOL_ROL
= 0x831,
189 MLX5_CMD_OP_CREATE_LAG
= 0x840,
190 MLX5_CMD_OP_MODIFY_LAG
= 0x841,
191 MLX5_CMD_OP_QUERY_LAG
= 0x842,
192 MLX5_CMD_OP_DESTROY_LAG
= 0x843,
193 MLX5_CMD_OP_CREATE_VPORT_LAG
= 0x844,
194 MLX5_CMD_OP_DESTROY_VPORT_LAG
= 0x845,
195 MLX5_CMD_OP_CREATE_TIR
= 0x900,
196 MLX5_CMD_OP_MODIFY_TIR
= 0x901,
197 MLX5_CMD_OP_DESTROY_TIR
= 0x902,
198 MLX5_CMD_OP_QUERY_TIR
= 0x903,
199 MLX5_CMD_OP_CREATE_SQ
= 0x904,
200 MLX5_CMD_OP_MODIFY_SQ
= 0x905,
201 MLX5_CMD_OP_DESTROY_SQ
= 0x906,
202 MLX5_CMD_OP_QUERY_SQ
= 0x907,
203 MLX5_CMD_OP_CREATE_RQ
= 0x908,
204 MLX5_CMD_OP_MODIFY_RQ
= 0x909,
205 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS
= 0x910,
206 MLX5_CMD_OP_DESTROY_RQ
= 0x90a,
207 MLX5_CMD_OP_QUERY_RQ
= 0x90b,
208 MLX5_CMD_OP_CREATE_RMP
= 0x90c,
209 MLX5_CMD_OP_MODIFY_RMP
= 0x90d,
210 MLX5_CMD_OP_DESTROY_RMP
= 0x90e,
211 MLX5_CMD_OP_QUERY_RMP
= 0x90f,
212 MLX5_CMD_OP_CREATE_TIS
= 0x912,
213 MLX5_CMD_OP_MODIFY_TIS
= 0x913,
214 MLX5_CMD_OP_DESTROY_TIS
= 0x914,
215 MLX5_CMD_OP_QUERY_TIS
= 0x915,
216 MLX5_CMD_OP_CREATE_RQT
= 0x916,
217 MLX5_CMD_OP_MODIFY_RQT
= 0x917,
218 MLX5_CMD_OP_DESTROY_RQT
= 0x918,
219 MLX5_CMD_OP_QUERY_RQT
= 0x919,
220 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT
= 0x92f,
221 MLX5_CMD_OP_CREATE_FLOW_TABLE
= 0x930,
222 MLX5_CMD_OP_DESTROY_FLOW_TABLE
= 0x931,
223 MLX5_CMD_OP_QUERY_FLOW_TABLE
= 0x932,
224 MLX5_CMD_OP_CREATE_FLOW_GROUP
= 0x933,
225 MLX5_CMD_OP_DESTROY_FLOW_GROUP
= 0x934,
226 MLX5_CMD_OP_QUERY_FLOW_GROUP
= 0x935,
227 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY
= 0x936,
228 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY
= 0x937,
229 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY
= 0x938,
230 MLX5_CMD_OP_ALLOC_FLOW_COUNTER
= 0x939,
231 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER
= 0x93a,
232 MLX5_CMD_OP_QUERY_FLOW_COUNTER
= 0x93b,
233 MLX5_CMD_OP_MODIFY_FLOW_TABLE
= 0x93c,
234 MLX5_CMD_OP_ALLOC_ENCAP_HEADER
= 0x93d,
235 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER
= 0x93e,
236 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT
= 0x940,
237 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT
= 0x941,
238 MLX5_CMD_OP_FPGA_CREATE_QP
= 0x960,
239 MLX5_CMD_OP_FPGA_MODIFY_QP
= 0x961,
240 MLX5_CMD_OP_FPGA_QUERY_QP
= 0x962,
241 MLX5_CMD_OP_FPGA_DESTROY_QP
= 0x963,
242 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS
= 0x964,
246 struct mlx5_ifc_flow_table_fields_supported_bits
{
249 u8 outer_ether_type
[0x1];
250 u8 outer_ip_version
[0x1];
251 u8 outer_first_prio
[0x1];
252 u8 outer_first_cfi
[0x1];
253 u8 outer_first_vid
[0x1];
254 u8 outer_ipv4_ttl
[0x1];
255 u8 outer_second_prio
[0x1];
256 u8 outer_second_cfi
[0x1];
257 u8 outer_second_vid
[0x1];
258 u8 reserved_at_b
[0x1];
262 u8 outer_ip_protocol
[0x1];
263 u8 outer_ip_ecn
[0x1];
264 u8 outer_ip_dscp
[0x1];
265 u8 outer_udp_sport
[0x1];
266 u8 outer_udp_dport
[0x1];
267 u8 outer_tcp_sport
[0x1];
268 u8 outer_tcp_dport
[0x1];
269 u8 outer_tcp_flags
[0x1];
270 u8 outer_gre_protocol
[0x1];
271 u8 outer_gre_key
[0x1];
272 u8 outer_vxlan_vni
[0x1];
273 u8 reserved_at_1a
[0x5];
274 u8 source_eswitch_port
[0x1];
278 u8 inner_ether_type
[0x1];
279 u8 inner_ip_version
[0x1];
280 u8 inner_first_prio
[0x1];
281 u8 inner_first_cfi
[0x1];
282 u8 inner_first_vid
[0x1];
283 u8 reserved_at_27
[0x1];
284 u8 inner_second_prio
[0x1];
285 u8 inner_second_cfi
[0x1];
286 u8 inner_second_vid
[0x1];
287 u8 reserved_at_2b
[0x1];
291 u8 inner_ip_protocol
[0x1];
292 u8 inner_ip_ecn
[0x1];
293 u8 inner_ip_dscp
[0x1];
294 u8 inner_udp_sport
[0x1];
295 u8 inner_udp_dport
[0x1];
296 u8 inner_tcp_sport
[0x1];
297 u8 inner_tcp_dport
[0x1];
298 u8 inner_tcp_flags
[0x1];
299 u8 reserved_at_37
[0x9];
300 u8 reserved_at_40
[0x17];
301 u8 outer_esp_spi
[0x1];
302 u8 reserved_at_58
[0x2];
305 u8 reserved_at_5b
[0x25];
308 struct mlx5_ifc_flow_table_prop_layout_bits
{
310 u8 reserved_at_1
[0x1];
311 u8 flow_counter
[0x1];
312 u8 flow_modify_en
[0x1];
314 u8 identified_miss_table_mode
[0x1];
315 u8 flow_table_modify
[0x1];
318 u8 reserved_at_9
[0x17];
320 u8 reserved_at_20
[0x2];
321 u8 log_max_ft_size
[0x6];
322 u8 log_max_modify_header_context
[0x8];
323 u8 max_modify_header_actions
[0x8];
324 u8 max_ft_level
[0x8];
326 u8 reserved_at_40
[0x20];
328 u8 reserved_at_60
[0x18];
329 u8 log_max_ft_num
[0x8];
331 u8 reserved_at_80
[0x18];
332 u8 log_max_destination
[0x8];
334 u8 log_max_flow_counter
[0x8];
335 u8 reserved_at_a8
[0x10];
336 u8 log_max_flow
[0x8];
338 u8 reserved_at_c0
[0x40];
340 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support
;
342 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support
;
345 struct mlx5_ifc_odp_per_transport_service_cap_bits
{
352 u8 reserved_at_6
[0x1a];
355 struct mlx5_ifc_ipv4_layout_bits
{
356 u8 reserved_at_0
[0x60];
361 struct mlx5_ifc_ipv6_layout_bits
{
365 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits
{
366 struct mlx5_ifc_ipv6_layout_bits ipv6_layout
;
367 struct mlx5_ifc_ipv4_layout_bits ipv4_layout
;
368 u8 reserved_at_0
[0x80];
371 struct mlx5_ifc_fte_match_set_lyr_2_4_bits
{
396 u8 reserved_at_c0
[0x18];
397 u8 ttl_hoplimit
[0x8];
402 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6
;
404 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6
;
407 struct mlx5_ifc_fte_match_set_misc_bits
{
408 u8 reserved_at_0
[0x8];
411 u8 reserved_at_20
[0x10];
412 u8 source_port
[0x10];
414 u8 outer_second_prio
[0x3];
415 u8 outer_second_cfi
[0x1];
416 u8 outer_second_vid
[0xc];
417 u8 inner_second_prio
[0x3];
418 u8 inner_second_cfi
[0x1];
419 u8 inner_second_vid
[0xc];
421 u8 outer_second_cvlan_tag
[0x1];
422 u8 inner_second_cvlan_tag
[0x1];
423 u8 outer_second_svlan_tag
[0x1];
424 u8 inner_second_svlan_tag
[0x1];
425 u8 reserved_at_64
[0xc];
426 u8 gre_protocol
[0x10];
432 u8 reserved_at_b8
[0x8];
434 u8 reserved_at_c0
[0x20];
436 u8 reserved_at_e0
[0xc];
437 u8 outer_ipv6_flow_label
[0x14];
439 u8 reserved_at_100
[0xc];
440 u8 inner_ipv6_flow_label
[0x14];
442 u8 reserved_at_120
[0x28];
444 u8 reserved_at_160
[0x20];
445 u8 outer_esp_spi
[0x20];
446 u8 reserved_at_1a0
[0x60];
449 struct mlx5_ifc_cmd_pas_bits
{
453 u8 reserved_at_34
[0xc];
456 struct mlx5_ifc_uint64_bits
{
463 MLX5_ADS_STAT_RATE_NO_LIMIT
= 0x0,
464 MLX5_ADS_STAT_RATE_2_5GBPS
= 0x7,
465 MLX5_ADS_STAT_RATE_10GBPS
= 0x8,
466 MLX5_ADS_STAT_RATE_30GBPS
= 0x9,
467 MLX5_ADS_STAT_RATE_5GBPS
= 0xa,
468 MLX5_ADS_STAT_RATE_20GBPS
= 0xb,
469 MLX5_ADS_STAT_RATE_40GBPS
= 0xc,
470 MLX5_ADS_STAT_RATE_60GBPS
= 0xd,
471 MLX5_ADS_STAT_RATE_80GBPS
= 0xe,
472 MLX5_ADS_STAT_RATE_120GBPS
= 0xf,
475 struct mlx5_ifc_ads_bits
{
478 u8 reserved_at_2
[0xe];
481 u8 reserved_at_20
[0x8];
487 u8 reserved_at_45
[0x3];
488 u8 src_addr_index
[0x8];
489 u8 reserved_at_50
[0x4];
493 u8 reserved_at_60
[0x4];
497 u8 rgid_rip
[16][0x8];
499 u8 reserved_at_100
[0x4];
502 u8 reserved_at_106
[0x1];
511 u8 vhca_port_num
[0x8];
517 struct mlx5_ifc_flow_table_nic_cap_bits
{
518 u8 nic_rx_multi_path_tirs
[0x1];
519 u8 nic_rx_multi_path_tirs_fts
[0x1];
520 u8 allow_sniffer_and_nic_rx_shared_tir
[0x1];
521 u8 reserved_at_3
[0x1fd];
523 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive
;
525 u8 reserved_at_400
[0x200];
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer
;
529 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit
;
531 u8 reserved_at_a00
[0x200];
533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer
;
535 u8 reserved_at_e00
[0x7200];
538 struct mlx5_ifc_flow_table_eswitch_cap_bits
{
539 u8 reserved_at_0
[0x200];
541 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb
;
543 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress
;
545 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress
;
547 u8 reserved_at_800
[0x7800];
550 struct mlx5_ifc_e_switch_cap_bits
{
551 u8 vport_svlan_strip
[0x1];
552 u8 vport_cvlan_strip
[0x1];
553 u8 vport_svlan_insert
[0x1];
554 u8 vport_cvlan_insert_if_not_exist
[0x1];
555 u8 vport_cvlan_insert_overwrite
[0x1];
556 u8 reserved_at_5
[0x19];
557 u8 nic_vport_node_guid_modify
[0x1];
558 u8 nic_vport_port_guid_modify
[0x1];
560 u8 vxlan_encap_decap
[0x1];
561 u8 nvgre_encap_decap
[0x1];
562 u8 reserved_at_22
[0x9];
563 u8 log_max_encap_headers
[0x5];
565 u8 max_encap_header_size
[0xa];
567 u8 reserved_40
[0x7c0];
571 struct mlx5_ifc_qos_cap_bits
{
572 u8 packet_pacing
[0x1];
573 u8 esw_scheduling
[0x1];
574 u8 esw_bw_share
[0x1];
575 u8 esw_rate_limit
[0x1];
576 u8 reserved_at_4
[0x1];
577 u8 packet_pacing_burst_bound
[0x1];
578 u8 packet_pacing_typical_size
[0x1];
579 u8 reserved_at_7
[0x19];
581 u8 reserved_at_20
[0x20];
583 u8 packet_pacing_max_rate
[0x20];
585 u8 packet_pacing_min_rate
[0x20];
587 u8 reserved_at_80
[0x10];
588 u8 packet_pacing_rate_table_size
[0x10];
590 u8 esw_element_type
[0x10];
591 u8 esw_tsar_type
[0x10];
593 u8 reserved_at_c0
[0x10];
594 u8 max_qos_para_vport
[0x10];
596 u8 max_tsar_bw_share
[0x20];
598 u8 reserved_at_100
[0x700];
601 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
{
605 u8 lro_psh_flag
[0x1];
606 u8 lro_time_stamp
[0x1];
607 u8 reserved_at_5
[0x2];
608 u8 wqe_vlan_insert
[0x1];
609 u8 self_lb_en_modifiable
[0x1];
610 u8 reserved_at_9
[0x2];
612 u8 multi_pkt_send_wqe
[0x2];
613 u8 wqe_inline_mode
[0x2];
614 u8 rss_ind_tbl_cap
[0x4];
617 u8 enhanced_multi_pkt_send_wqe
[0x1];
618 u8 tunnel_lso_const_out_ip_id
[0x1];
619 u8 reserved_at_1c
[0x2];
620 u8 tunnel_stateless_gre
[0x1];
621 u8 tunnel_stateless_vxlan
[0x1];
626 u8 reserved_at_23
[0x1b];
627 u8 max_geneve_opt_len
[0x1];
628 u8 tunnel_stateless_geneve_rx
[0x1];
630 u8 reserved_at_40
[0x10];
631 u8 lro_min_mss_size
[0x10];
633 u8 reserved_at_60
[0x120];
635 u8 lro_timer_supported_periods
[4][0x20];
637 u8 reserved_at_200
[0x600];
640 struct mlx5_ifc_roce_cap_bits
{
642 u8 reserved_at_1
[0x1f];
644 u8 reserved_at_20
[0x60];
646 u8 reserved_at_80
[0xc];
648 u8 reserved_at_90
[0x8];
649 u8 roce_version
[0x8];
651 u8 reserved_at_a0
[0x10];
652 u8 r_roce_dest_udp_port
[0x10];
654 u8 r_roce_max_src_udp_port
[0x10];
655 u8 r_roce_min_src_udp_port
[0x10];
657 u8 reserved_at_e0
[0x10];
658 u8 roce_address_table_size
[0x10];
660 u8 reserved_at_100
[0x700];
663 struct mlx5_ifc_device_mem_cap_bits
{
665 u8 reserved_at_1
[0x1f];
667 u8 reserved_at_20
[0xb];
668 u8 log_min_memic_alloc_size
[0x5];
669 u8 reserved_at_30
[0x8];
670 u8 log_max_memic_addr_alignment
[0x8];
672 u8 memic_bar_start_addr
[0x40];
674 u8 memic_bar_size
[0x20];
676 u8 max_memic_size
[0x20];
678 u8 reserved_at_c0
[0x740];
682 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE
= 0x0,
683 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES
= 0x2,
684 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES
= 0x4,
685 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES
= 0x8,
686 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES
= 0x10,
687 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES
= 0x20,
688 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES
= 0x40,
689 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES
= 0x80,
690 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES
= 0x100,
694 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE
= 0x1,
695 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES
= 0x2,
696 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES
= 0x4,
697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES
= 0x8,
698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES
= 0x10,
699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES
= 0x20,
700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES
= 0x40,
701 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES
= 0x80,
702 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES
= 0x100,
705 struct mlx5_ifc_atomic_caps_bits
{
706 u8 reserved_at_0
[0x40];
708 u8 atomic_req_8B_endianness_mode
[0x2];
709 u8 reserved_at_42
[0x4];
710 u8 supported_atomic_req_8B_endianness_mode_1
[0x1];
712 u8 reserved_at_47
[0x19];
714 u8 reserved_at_60
[0x20];
716 u8 reserved_at_80
[0x10];
717 u8 atomic_operations
[0x10];
719 u8 reserved_at_a0
[0x10];
720 u8 atomic_size_qp
[0x10];
722 u8 reserved_at_c0
[0x10];
723 u8 atomic_size_dc
[0x10];
725 u8 reserved_at_e0
[0x720];
728 struct mlx5_ifc_odp_cap_bits
{
729 u8 reserved_at_0
[0x40];
732 u8 reserved_at_41
[0x1f];
734 u8 reserved_at_60
[0x20];
736 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps
;
738 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps
;
740 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps
;
742 u8 reserved_at_e0
[0x720];
745 struct mlx5_ifc_calc_op
{
746 u8 reserved_at_0
[0x10];
747 u8 reserved_at_10
[0x9];
748 u8 op_swap_endianness
[0x1];
757 struct mlx5_ifc_vector_calc_cap_bits
{
759 u8 reserved_at_1
[0x1f];
760 u8 reserved_at_20
[0x8];
761 u8 max_vec_count
[0x8];
762 u8 reserved_at_30
[0xd];
763 u8 max_chunk_size
[0x3];
764 struct mlx5_ifc_calc_op calc0
;
765 struct mlx5_ifc_calc_op calc1
;
766 struct mlx5_ifc_calc_op calc2
;
767 struct mlx5_ifc_calc_op calc3
;
769 u8 reserved_at_e0
[0x720];
773 MLX5_WQ_TYPE_LINKED_LIST
= 0x0,
774 MLX5_WQ_TYPE_CYCLIC
= 0x1,
775 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
= 0x2,
776 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ
= 0x3,
780 MLX5_WQ_END_PAD_MODE_NONE
= 0x0,
781 MLX5_WQ_END_PAD_MODE_ALIGN
= 0x1,
785 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES
= 0x0,
786 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES
= 0x1,
787 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES
= 0x2,
788 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES
= 0x3,
789 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES
= 0x4,
793 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES
= 0x0,
794 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES
= 0x1,
795 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES
= 0x2,
796 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES
= 0x3,
797 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES
= 0x4,
798 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES
= 0x5,
802 MLX5_CMD_HCA_CAP_PORT_TYPE_IB
= 0x0,
803 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET
= 0x1,
807 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED
= 0x0,
808 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE
= 0x1,
809 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED
= 0x3,
813 MLX5_CAP_PORT_TYPE_IB
= 0x0,
814 MLX5_CAP_PORT_TYPE_ETH
= 0x1,
818 MLX5_CAP_UMR_FENCE_STRONG
= 0x0,
819 MLX5_CAP_UMR_FENCE_SMALL
= 0x1,
820 MLX5_CAP_UMR_FENCE_NONE
= 0x2,
823 struct mlx5_ifc_cmd_hca_cap_bits
{
824 u8 reserved_at_0
[0x30];
827 u8 reserved_at_40
[0x40];
829 u8 log_max_srq_sz
[0x8];
830 u8 log_max_qp_sz
[0x8];
831 u8 reserved_at_90
[0xb];
834 u8 reserved_at_a0
[0xb];
836 u8 reserved_at_b0
[0x10];
838 u8 reserved_at_c0
[0x8];
839 u8 log_max_cq_sz
[0x8];
840 u8 reserved_at_d0
[0xb];
843 u8 log_max_eq_sz
[0x8];
844 u8 reserved_at_e8
[0x2];
845 u8 log_max_mkey
[0x6];
846 u8 reserved_at_f0
[0xc];
849 u8 max_indirection
[0x8];
850 u8 fixed_buffer_size
[0x1];
851 u8 log_max_mrw_sz
[0x7];
852 u8 force_teardown
[0x1];
853 u8 reserved_at_111
[0x1];
854 u8 log_max_bsf_list_size
[0x6];
855 u8 umr_extended_translation_offset
[0x1];
857 u8 log_max_klm_list_size
[0x6];
859 u8 reserved_at_120
[0xa];
860 u8 log_max_ra_req_dc
[0x6];
861 u8 reserved_at_130
[0xa];
862 u8 log_max_ra_res_dc
[0x6];
864 u8 reserved_at_140
[0xa];
865 u8 log_max_ra_req_qp
[0x6];
866 u8 reserved_at_150
[0xa];
867 u8 log_max_ra_res_qp
[0x6];
870 u8 cc_query_allowed
[0x1];
871 u8 cc_modify_allowed
[0x1];
873 u8 cache_line_128byte
[0x1];
874 u8 reserved_at_165
[0xa];
876 u8 gid_table_size
[0x10];
878 u8 out_of_seq_cnt
[0x1];
879 u8 vport_counters
[0x1];
880 u8 retransmission_q_counters
[0x1];
881 u8 reserved_at_183
[0x1];
882 u8 modify_rq_counter_set_id
[0x1];
883 u8 rq_delay_drop
[0x1];
885 u8 pkey_table_size
[0x10];
887 u8 vport_group_manager
[0x1];
888 u8 vhca_group_manager
[0x1];
891 u8 reserved_at_1a4
[0x1];
893 u8 nic_flow_table
[0x1];
894 u8 eswitch_flow_table
[0x1];
895 u8 device_memory
[0x1];
898 u8 local_ca_ack_delay
[0x5];
899 u8 port_module_event
[0x1];
900 u8 enhanced_error_q_counters
[0x1];
902 u8 reserved_at_1b3
[0x1];
903 u8 disable_link_up
[0x1];
908 u8 reserved_at_1c0
[0x1];
912 u8 reserved_at_1c8
[0x4];
914 u8 reserved_at_1d0
[0x1];
916 u8 general_notification_event
[0x1];
917 u8 reserved_at_1d3
[0x2];
921 u8 reserved_at_1d8
[0x1];
930 u8 stat_rate_support
[0x10];
931 u8 reserved_at_1f0
[0xc];
934 u8 compact_address_vector
[0x1];
936 u8 reserved_at_202
[0x1];
937 u8 ipoib_enhanced_offloads
[0x1];
938 u8 ipoib_basic_offloads
[0x1];
939 u8 reserved_at_205
[0x1];
940 u8 repeated_block_disabled
[0x1];
941 u8 umr_modify_entity_size_disabled
[0x1];
942 u8 umr_modify_atomic_disabled
[0x1];
943 u8 umr_indirect_mkey_disabled
[0x1];
945 u8 reserved_at_20c
[0x3];
946 u8 drain_sigerr
[0x1];
947 u8 cmdif_checksum
[0x2];
949 u8 reserved_at_213
[0x1];
950 u8 wq_signature
[0x1];
951 u8 sctr_data_cqe
[0x1];
952 u8 reserved_at_216
[0x1];
958 u8 eth_net_offloads
[0x1];
961 u8 reserved_at_21f
[0x1];
965 u8 cq_moderation
[0x1];
966 u8 reserved_at_223
[0x3];
970 u8 reserved_at_229
[0x1];
971 u8 scqe_break_moderation
[0x1];
972 u8 cq_period_start_from_cqe
[0x1];
974 u8 reserved_at_22d
[0x1];
977 u8 umr_ptr_rlky
[0x1];
979 u8 reserved_at_232
[0x4];
982 u8 set_deth_sqpn
[0x1];
983 u8 reserved_at_239
[0x3];
990 u8 reserved_at_241
[0x9];
992 u8 reserved_at_250
[0x8];
996 u8 driver_version
[0x1];
997 u8 pad_tx_eth_packet
[0x1];
998 u8 reserved_at_263
[0x8];
999 u8 log_bf_reg_size
[0x5];
1001 u8 reserved_at_270
[0xb];
1003 u8 num_lag_ports
[0x4];
1005 u8 reserved_at_280
[0x10];
1006 u8 max_wqe_sz_sq
[0x10];
1008 u8 reserved_at_2a0
[0x10];
1009 u8 max_wqe_sz_rq
[0x10];
1011 u8 max_flow_counter_31_16
[0x10];
1012 u8 max_wqe_sz_sq_dc
[0x10];
1014 u8 reserved_at_2e0
[0x7];
1015 u8 max_qp_mcg
[0x19];
1017 u8 reserved_at_300
[0x18];
1018 u8 log_max_mcg
[0x8];
1020 u8 reserved_at_320
[0x3];
1021 u8 log_max_transport_domain
[0x5];
1022 u8 reserved_at_328
[0x3];
1024 u8 reserved_at_330
[0xb];
1025 u8 log_max_xrcd
[0x5];
1027 u8 reserved_at_340
[0x8];
1028 u8 log_max_flow_counter_bulk
[0x8];
1029 u8 max_flow_counter_15_0
[0x10];
1032 u8 reserved_at_360
[0x3];
1034 u8 reserved_at_368
[0x3];
1036 u8 reserved_at_370
[0x3];
1037 u8 log_max_tir
[0x5];
1038 u8 reserved_at_378
[0x3];
1039 u8 log_max_tis
[0x5];
1041 u8 basic_cyclic_rcv_wqe
[0x1];
1042 u8 reserved_at_381
[0x2];
1043 u8 log_max_rmp
[0x5];
1044 u8 reserved_at_388
[0x3];
1045 u8 log_max_rqt
[0x5];
1046 u8 reserved_at_390
[0x3];
1047 u8 log_max_rqt_size
[0x5];
1048 u8 reserved_at_398
[0x3];
1049 u8 log_max_tis_per_sq
[0x5];
1051 u8 reserved_at_3a0
[0x3];
1052 u8 log_max_stride_sz_rq
[0x5];
1053 u8 reserved_at_3a8
[0x3];
1054 u8 log_min_stride_sz_rq
[0x5];
1055 u8 reserved_at_3b0
[0x3];
1056 u8 log_max_stride_sz_sq
[0x5];
1057 u8 reserved_at_3b8
[0x3];
1058 u8 log_min_stride_sz_sq
[0x5];
1061 u8 reserved_at_3c1
[0x2];
1062 u8 log_max_hairpin_queues
[0x5];
1063 u8 reserved_at_3c8
[0x3];
1064 u8 log_max_hairpin_wq_data_sz
[0x5];
1065 u8 reserved_at_3d0
[0x3];
1066 u8 log_max_hairpin_num_packets
[0x5];
1067 u8 reserved_at_3d8
[0x3];
1068 u8 log_max_wq_sz
[0x5];
1070 u8 nic_vport_change_event
[0x1];
1071 u8 disable_local_lb_uc
[0x1];
1072 u8 disable_local_lb_mc
[0x1];
1073 u8 log_min_hairpin_wq_data_sz
[0x5];
1074 u8 reserved_at_3e8
[0x3];
1075 u8 log_max_vlan_list
[0x5];
1076 u8 reserved_at_3f0
[0x3];
1077 u8 log_max_current_mc_list
[0x5];
1078 u8 reserved_at_3f8
[0x3];
1079 u8 log_max_current_uc_list
[0x5];
1081 u8 reserved_at_400
[0x80];
1083 u8 reserved_at_480
[0x3];
1084 u8 log_max_l2_table
[0x5];
1085 u8 reserved_at_488
[0x8];
1086 u8 log_uar_page_sz
[0x10];
1088 u8 reserved_at_4a0
[0x20];
1089 u8 device_frequency_mhz
[0x20];
1090 u8 device_frequency_khz
[0x20];
1092 u8 reserved_at_500
[0x20];
1093 u8 num_of_uars_per_page
[0x20];
1094 u8 reserved_at_540
[0x40];
1096 u8 reserved_at_580
[0x3d];
1097 u8 cqe_128_always
[0x1];
1098 u8 cqe_compression_128
[0x1];
1099 u8 cqe_compression
[0x1];
1101 u8 cqe_compression_timeout
[0x10];
1102 u8 cqe_compression_max_num
[0x10];
1104 u8 reserved_at_5e0
[0x10];
1105 u8 tag_matching
[0x1];
1106 u8 rndv_offload_rc
[0x1];
1107 u8 rndv_offload_dc
[0x1];
1108 u8 log_tag_matching_list_sz
[0x5];
1109 u8 reserved_at_5f8
[0x3];
1110 u8 log_max_xrq
[0x5];
1112 u8 affiliate_nic_vport_criteria
[0x8];
1113 u8 native_port_num
[0x8];
1114 u8 num_vhca_ports
[0x8];
1115 u8 reserved_at_618
[0x6];
1116 u8 sw_owner_id
[0x1];
1117 u8 reserved_at_61f
[0x1e1];
1120 enum mlx5_flow_destination_type
{
1121 MLX5_FLOW_DESTINATION_TYPE_VPORT
= 0x0,
1122 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE
= 0x1,
1123 MLX5_FLOW_DESTINATION_TYPE_TIR
= 0x2,
1125 MLX5_FLOW_DESTINATION_TYPE_PORT
= 0x99,
1126 MLX5_FLOW_DESTINATION_TYPE_COUNTER
= 0x100,
1129 struct mlx5_ifc_dest_format_struct_bits
{
1130 u8 destination_type
[0x8];
1131 u8 destination_id
[0x18];
1133 u8 reserved_at_20
[0x20];
1136 struct mlx5_ifc_flow_counter_list_bits
{
1137 u8 flow_counter_id
[0x20];
1139 u8 reserved_at_20
[0x20];
1142 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits
{
1143 struct mlx5_ifc_dest_format_struct_bits dest_format_struct
;
1144 struct mlx5_ifc_flow_counter_list_bits flow_counter_list
;
1145 u8 reserved_at_0
[0x40];
1148 struct mlx5_ifc_fte_match_param_bits
{
1149 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers
;
1151 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters
;
1153 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers
;
1155 u8 reserved_at_600
[0xa00];
1159 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP
= 0x0,
1160 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP
= 0x1,
1161 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT
= 0x2,
1162 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT
= 0x3,
1163 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI
= 0x4,
1166 struct mlx5_ifc_rx_hash_field_select_bits
{
1167 u8 l3_prot_type
[0x1];
1168 u8 l4_prot_type
[0x1];
1169 u8 selected_fields
[0x1e];
1173 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST
= 0x0,
1174 MLX5_WQ_WQ_TYPE_WQ_CYCLIC
= 0x1,
1178 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE
= 0x0,
1179 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN
= 0x1,
1182 struct mlx5_ifc_wq_bits
{
1184 u8 wq_signature
[0x1];
1185 u8 end_padding_mode
[0x2];
1187 u8 reserved_at_8
[0x18];
1189 u8 hds_skip_first_sge
[0x1];
1190 u8 log2_hds_buf_size
[0x3];
1191 u8 reserved_at_24
[0x7];
1192 u8 page_offset
[0x5];
1195 u8 reserved_at_40
[0x8];
1198 u8 reserved_at_60
[0x8];
1203 u8 hw_counter
[0x20];
1205 u8 sw_counter
[0x20];
1207 u8 reserved_at_100
[0xc];
1208 u8 log_wq_stride
[0x4];
1209 u8 reserved_at_110
[0x3];
1210 u8 log_wq_pg_sz
[0x5];
1211 u8 reserved_at_118
[0x3];
1214 u8 reserved_at_120
[0x3];
1215 u8 log_hairpin_num_packets
[0x5];
1216 u8 reserved_at_128
[0x3];
1217 u8 log_hairpin_data_sz
[0x5];
1218 u8 reserved_at_130
[0x5];
1220 u8 log_wqe_num_of_strides
[0x3];
1221 u8 two_byte_shift_en
[0x1];
1222 u8 reserved_at_139
[0x4];
1223 u8 log_wqe_stride_size
[0x3];
1225 u8 reserved_at_140
[0x4c0];
1227 struct mlx5_ifc_cmd_pas_bits pas
[0];
1230 struct mlx5_ifc_rq_num_bits
{
1231 u8 reserved_at_0
[0x8];
1235 struct mlx5_ifc_mac_address_layout_bits
{
1236 u8 reserved_at_0
[0x10];
1237 u8 mac_addr_47_32
[0x10];
1239 u8 mac_addr_31_0
[0x20];
1242 struct mlx5_ifc_vlan_layout_bits
{
1243 u8 reserved_at_0
[0x14];
1246 u8 reserved_at_20
[0x20];
1249 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits
{
1250 u8 reserved_at_0
[0xa0];
1252 u8 min_time_between_cnps
[0x20];
1254 u8 reserved_at_c0
[0x12];
1256 u8 reserved_at_d8
[0x4];
1257 u8 cnp_prio_mode
[0x1];
1258 u8 cnp_802p_prio
[0x3];
1260 u8 reserved_at_e0
[0x720];
1263 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits
{
1264 u8 reserved_at_0
[0x60];
1266 u8 reserved_at_60
[0x4];
1267 u8 clamp_tgt_rate
[0x1];
1268 u8 reserved_at_65
[0x3];
1269 u8 clamp_tgt_rate_after_time_inc
[0x1];
1270 u8 reserved_at_69
[0x17];
1272 u8 reserved_at_80
[0x20];
1274 u8 rpg_time_reset
[0x20];
1276 u8 rpg_byte_reset
[0x20];
1278 u8 rpg_threshold
[0x20];
1280 u8 rpg_max_rate
[0x20];
1282 u8 rpg_ai_rate
[0x20];
1284 u8 rpg_hai_rate
[0x20];
1288 u8 rpg_min_dec_fac
[0x20];
1290 u8 rpg_min_rate
[0x20];
1292 u8 reserved_at_1c0
[0xe0];
1294 u8 rate_to_set_on_first_cnp
[0x20];
1298 u8 dce_tcp_rtt
[0x20];
1300 u8 rate_reduce_monitor_period
[0x20];
1302 u8 reserved_at_320
[0x20];
1304 u8 initial_alpha_value
[0x20];
1306 u8 reserved_at_360
[0x4a0];
1309 struct mlx5_ifc_cong_control_802_1qau_rp_bits
{
1310 u8 reserved_at_0
[0x80];
1312 u8 rppp_max_rps
[0x20];
1314 u8 rpg_time_reset
[0x20];
1316 u8 rpg_byte_reset
[0x20];
1318 u8 rpg_threshold
[0x20];
1320 u8 rpg_max_rate
[0x20];
1322 u8 rpg_ai_rate
[0x20];
1324 u8 rpg_hai_rate
[0x20];
1328 u8 rpg_min_dec_fac
[0x20];
1330 u8 rpg_min_rate
[0x20];
1332 u8 reserved_at_1c0
[0x640];
1336 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE
= 0x1,
1337 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET
= 0x2,
1338 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE
= 0x4,
1341 struct mlx5_ifc_resize_field_select_bits
{
1342 u8 resize_field_select
[0x20];
1346 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD
= 0x1,
1347 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT
= 0x2,
1348 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI
= 0x4,
1349 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN
= 0x8,
1352 struct mlx5_ifc_modify_field_select_bits
{
1353 u8 modify_field_select
[0x20];
1356 struct mlx5_ifc_field_select_r_roce_np_bits
{
1357 u8 field_select_r_roce_np
[0x20];
1360 struct mlx5_ifc_field_select_r_roce_rp_bits
{
1361 u8 field_select_r_roce_rp
[0x20];
1365 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS
= 0x4,
1366 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET
= 0x8,
1367 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET
= 0x10,
1368 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD
= 0x20,
1369 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE
= 0x40,
1370 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE
= 0x80,
1371 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE
= 0x100,
1372 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD
= 0x200,
1373 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC
= 0x400,
1374 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE
= 0x800,
1377 struct mlx5_ifc_field_select_802_1qau_rp_bits
{
1378 u8 field_select_8021qaurp
[0x20];
1381 struct mlx5_ifc_phys_layer_cntrs_bits
{
1382 u8 time_since_last_clear_high
[0x20];
1384 u8 time_since_last_clear_low
[0x20];
1386 u8 symbol_errors_high
[0x20];
1388 u8 symbol_errors_low
[0x20];
1390 u8 sync_headers_errors_high
[0x20];
1392 u8 sync_headers_errors_low
[0x20];
1394 u8 edpl_bip_errors_lane0_high
[0x20];
1396 u8 edpl_bip_errors_lane0_low
[0x20];
1398 u8 edpl_bip_errors_lane1_high
[0x20];
1400 u8 edpl_bip_errors_lane1_low
[0x20];
1402 u8 edpl_bip_errors_lane2_high
[0x20];
1404 u8 edpl_bip_errors_lane2_low
[0x20];
1406 u8 edpl_bip_errors_lane3_high
[0x20];
1408 u8 edpl_bip_errors_lane3_low
[0x20];
1410 u8 fc_fec_corrected_blocks_lane0_high
[0x20];
1412 u8 fc_fec_corrected_blocks_lane0_low
[0x20];
1414 u8 fc_fec_corrected_blocks_lane1_high
[0x20];
1416 u8 fc_fec_corrected_blocks_lane1_low
[0x20];
1418 u8 fc_fec_corrected_blocks_lane2_high
[0x20];
1420 u8 fc_fec_corrected_blocks_lane2_low
[0x20];
1422 u8 fc_fec_corrected_blocks_lane3_high
[0x20];
1424 u8 fc_fec_corrected_blocks_lane3_low
[0x20];
1426 u8 fc_fec_uncorrectable_blocks_lane0_high
[0x20];
1428 u8 fc_fec_uncorrectable_blocks_lane0_low
[0x20];
1430 u8 fc_fec_uncorrectable_blocks_lane1_high
[0x20];
1432 u8 fc_fec_uncorrectable_blocks_lane1_low
[0x20];
1434 u8 fc_fec_uncorrectable_blocks_lane2_high
[0x20];
1436 u8 fc_fec_uncorrectable_blocks_lane2_low
[0x20];
1438 u8 fc_fec_uncorrectable_blocks_lane3_high
[0x20];
1440 u8 fc_fec_uncorrectable_blocks_lane3_low
[0x20];
1442 u8 rs_fec_corrected_blocks_high
[0x20];
1444 u8 rs_fec_corrected_blocks_low
[0x20];
1446 u8 rs_fec_uncorrectable_blocks_high
[0x20];
1448 u8 rs_fec_uncorrectable_blocks_low
[0x20];
1450 u8 rs_fec_no_errors_blocks_high
[0x20];
1452 u8 rs_fec_no_errors_blocks_low
[0x20];
1454 u8 rs_fec_single_error_blocks_high
[0x20];
1456 u8 rs_fec_single_error_blocks_low
[0x20];
1458 u8 rs_fec_corrected_symbols_total_high
[0x20];
1460 u8 rs_fec_corrected_symbols_total_low
[0x20];
1462 u8 rs_fec_corrected_symbols_lane0_high
[0x20];
1464 u8 rs_fec_corrected_symbols_lane0_low
[0x20];
1466 u8 rs_fec_corrected_symbols_lane1_high
[0x20];
1468 u8 rs_fec_corrected_symbols_lane1_low
[0x20];
1470 u8 rs_fec_corrected_symbols_lane2_high
[0x20];
1472 u8 rs_fec_corrected_symbols_lane2_low
[0x20];
1474 u8 rs_fec_corrected_symbols_lane3_high
[0x20];
1476 u8 rs_fec_corrected_symbols_lane3_low
[0x20];
1478 u8 link_down_events
[0x20];
1480 u8 successful_recovery_events
[0x20];
1482 u8 reserved_at_640
[0x180];
1485 struct mlx5_ifc_phys_layer_statistical_cntrs_bits
{
1486 u8 time_since_last_clear_high
[0x20];
1488 u8 time_since_last_clear_low
[0x20];
1490 u8 phy_received_bits_high
[0x20];
1492 u8 phy_received_bits_low
[0x20];
1494 u8 phy_symbol_errors_high
[0x20];
1496 u8 phy_symbol_errors_low
[0x20];
1498 u8 phy_corrected_bits_high
[0x20];
1500 u8 phy_corrected_bits_low
[0x20];
1502 u8 phy_corrected_bits_lane0_high
[0x20];
1504 u8 phy_corrected_bits_lane0_low
[0x20];
1506 u8 phy_corrected_bits_lane1_high
[0x20];
1508 u8 phy_corrected_bits_lane1_low
[0x20];
1510 u8 phy_corrected_bits_lane2_high
[0x20];
1512 u8 phy_corrected_bits_lane2_low
[0x20];
1514 u8 phy_corrected_bits_lane3_high
[0x20];
1516 u8 phy_corrected_bits_lane3_low
[0x20];
1518 u8 reserved_at_200
[0x5c0];
1521 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits
{
1522 u8 symbol_error_counter
[0x10];
1524 u8 link_error_recovery_counter
[0x8];
1526 u8 link_downed_counter
[0x8];
1528 u8 port_rcv_errors
[0x10];
1530 u8 port_rcv_remote_physical_errors
[0x10];
1532 u8 port_rcv_switch_relay_errors
[0x10];
1534 u8 port_xmit_discards
[0x10];
1536 u8 port_xmit_constraint_errors
[0x8];
1538 u8 port_rcv_constraint_errors
[0x8];
1540 u8 reserved_at_70
[0x8];
1542 u8 link_overrun_errors
[0x8];
1544 u8 reserved_at_80
[0x10];
1546 u8 vl_15_dropped
[0x10];
1548 u8 reserved_at_a0
[0x80];
1550 u8 port_xmit_wait
[0x20];
1553 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits
{
1554 u8 transmit_queue_high
[0x20];
1556 u8 transmit_queue_low
[0x20];
1558 u8 reserved_at_40
[0x780];
1561 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits
{
1562 u8 rx_octets_high
[0x20];
1564 u8 rx_octets_low
[0x20];
1566 u8 reserved_at_40
[0xc0];
1568 u8 rx_frames_high
[0x20];
1570 u8 rx_frames_low
[0x20];
1572 u8 tx_octets_high
[0x20];
1574 u8 tx_octets_low
[0x20];
1576 u8 reserved_at_180
[0xc0];
1578 u8 tx_frames_high
[0x20];
1580 u8 tx_frames_low
[0x20];
1582 u8 rx_pause_high
[0x20];
1584 u8 rx_pause_low
[0x20];
1586 u8 rx_pause_duration_high
[0x20];
1588 u8 rx_pause_duration_low
[0x20];
1590 u8 tx_pause_high
[0x20];
1592 u8 tx_pause_low
[0x20];
1594 u8 tx_pause_duration_high
[0x20];
1596 u8 tx_pause_duration_low
[0x20];
1598 u8 rx_pause_transition_high
[0x20];
1600 u8 rx_pause_transition_low
[0x20];
1602 u8 reserved_at_3c0
[0x400];
1605 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits
{
1606 u8 port_transmit_wait_high
[0x20];
1608 u8 port_transmit_wait_low
[0x20];
1610 u8 reserved_at_40
[0x100];
1612 u8 rx_buffer_almost_full_high
[0x20];
1614 u8 rx_buffer_almost_full_low
[0x20];
1616 u8 rx_buffer_full_high
[0x20];
1618 u8 rx_buffer_full_low
[0x20];
1620 u8 reserved_at_1c0
[0x600];
1623 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits
{
1624 u8 dot3stats_alignment_errors_high
[0x20];
1626 u8 dot3stats_alignment_errors_low
[0x20];
1628 u8 dot3stats_fcs_errors_high
[0x20];
1630 u8 dot3stats_fcs_errors_low
[0x20];
1632 u8 dot3stats_single_collision_frames_high
[0x20];
1634 u8 dot3stats_single_collision_frames_low
[0x20];
1636 u8 dot3stats_multiple_collision_frames_high
[0x20];
1638 u8 dot3stats_multiple_collision_frames_low
[0x20];
1640 u8 dot3stats_sqe_test_errors_high
[0x20];
1642 u8 dot3stats_sqe_test_errors_low
[0x20];
1644 u8 dot3stats_deferred_transmissions_high
[0x20];
1646 u8 dot3stats_deferred_transmissions_low
[0x20];
1648 u8 dot3stats_late_collisions_high
[0x20];
1650 u8 dot3stats_late_collisions_low
[0x20];
1652 u8 dot3stats_excessive_collisions_high
[0x20];
1654 u8 dot3stats_excessive_collisions_low
[0x20];
1656 u8 dot3stats_internal_mac_transmit_errors_high
[0x20];
1658 u8 dot3stats_internal_mac_transmit_errors_low
[0x20];
1660 u8 dot3stats_carrier_sense_errors_high
[0x20];
1662 u8 dot3stats_carrier_sense_errors_low
[0x20];
1664 u8 dot3stats_frame_too_longs_high
[0x20];
1666 u8 dot3stats_frame_too_longs_low
[0x20];
1668 u8 dot3stats_internal_mac_receive_errors_high
[0x20];
1670 u8 dot3stats_internal_mac_receive_errors_low
[0x20];
1672 u8 dot3stats_symbol_errors_high
[0x20];
1674 u8 dot3stats_symbol_errors_low
[0x20];
1676 u8 dot3control_in_unknown_opcodes_high
[0x20];
1678 u8 dot3control_in_unknown_opcodes_low
[0x20];
1680 u8 dot3in_pause_frames_high
[0x20];
1682 u8 dot3in_pause_frames_low
[0x20];
1684 u8 dot3out_pause_frames_high
[0x20];
1686 u8 dot3out_pause_frames_low
[0x20];
1688 u8 reserved_at_400
[0x3c0];
1691 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits
{
1692 u8 ether_stats_drop_events_high
[0x20];
1694 u8 ether_stats_drop_events_low
[0x20];
1696 u8 ether_stats_octets_high
[0x20];
1698 u8 ether_stats_octets_low
[0x20];
1700 u8 ether_stats_pkts_high
[0x20];
1702 u8 ether_stats_pkts_low
[0x20];
1704 u8 ether_stats_broadcast_pkts_high
[0x20];
1706 u8 ether_stats_broadcast_pkts_low
[0x20];
1708 u8 ether_stats_multicast_pkts_high
[0x20];
1710 u8 ether_stats_multicast_pkts_low
[0x20];
1712 u8 ether_stats_crc_align_errors_high
[0x20];
1714 u8 ether_stats_crc_align_errors_low
[0x20];
1716 u8 ether_stats_undersize_pkts_high
[0x20];
1718 u8 ether_stats_undersize_pkts_low
[0x20];
1720 u8 ether_stats_oversize_pkts_high
[0x20];
1722 u8 ether_stats_oversize_pkts_low
[0x20];
1724 u8 ether_stats_fragments_high
[0x20];
1726 u8 ether_stats_fragments_low
[0x20];
1728 u8 ether_stats_jabbers_high
[0x20];
1730 u8 ether_stats_jabbers_low
[0x20];
1732 u8 ether_stats_collisions_high
[0x20];
1734 u8 ether_stats_collisions_low
[0x20];
1736 u8 ether_stats_pkts64octets_high
[0x20];
1738 u8 ether_stats_pkts64octets_low
[0x20];
1740 u8 ether_stats_pkts65to127octets_high
[0x20];
1742 u8 ether_stats_pkts65to127octets_low
[0x20];
1744 u8 ether_stats_pkts128to255octets_high
[0x20];
1746 u8 ether_stats_pkts128to255octets_low
[0x20];
1748 u8 ether_stats_pkts256to511octets_high
[0x20];
1750 u8 ether_stats_pkts256to511octets_low
[0x20];
1752 u8 ether_stats_pkts512to1023octets_high
[0x20];
1754 u8 ether_stats_pkts512to1023octets_low
[0x20];
1756 u8 ether_stats_pkts1024to1518octets_high
[0x20];
1758 u8 ether_stats_pkts1024to1518octets_low
[0x20];
1760 u8 ether_stats_pkts1519to2047octets_high
[0x20];
1762 u8 ether_stats_pkts1519to2047octets_low
[0x20];
1764 u8 ether_stats_pkts2048to4095octets_high
[0x20];
1766 u8 ether_stats_pkts2048to4095octets_low
[0x20];
1768 u8 ether_stats_pkts4096to8191octets_high
[0x20];
1770 u8 ether_stats_pkts4096to8191octets_low
[0x20];
1772 u8 ether_stats_pkts8192to10239octets_high
[0x20];
1774 u8 ether_stats_pkts8192to10239octets_low
[0x20];
1776 u8 reserved_at_540
[0x280];
1779 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits
{
1780 u8 if_in_octets_high
[0x20];
1782 u8 if_in_octets_low
[0x20];
1784 u8 if_in_ucast_pkts_high
[0x20];
1786 u8 if_in_ucast_pkts_low
[0x20];
1788 u8 if_in_discards_high
[0x20];
1790 u8 if_in_discards_low
[0x20];
1792 u8 if_in_errors_high
[0x20];
1794 u8 if_in_errors_low
[0x20];
1796 u8 if_in_unknown_protos_high
[0x20];
1798 u8 if_in_unknown_protos_low
[0x20];
1800 u8 if_out_octets_high
[0x20];
1802 u8 if_out_octets_low
[0x20];
1804 u8 if_out_ucast_pkts_high
[0x20];
1806 u8 if_out_ucast_pkts_low
[0x20];
1808 u8 if_out_discards_high
[0x20];
1810 u8 if_out_discards_low
[0x20];
1812 u8 if_out_errors_high
[0x20];
1814 u8 if_out_errors_low
[0x20];
1816 u8 if_in_multicast_pkts_high
[0x20];
1818 u8 if_in_multicast_pkts_low
[0x20];
1820 u8 if_in_broadcast_pkts_high
[0x20];
1822 u8 if_in_broadcast_pkts_low
[0x20];
1824 u8 if_out_multicast_pkts_high
[0x20];
1826 u8 if_out_multicast_pkts_low
[0x20];
1828 u8 if_out_broadcast_pkts_high
[0x20];
1830 u8 if_out_broadcast_pkts_low
[0x20];
1832 u8 reserved_at_340
[0x480];
1835 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits
{
1836 u8 a_frames_transmitted_ok_high
[0x20];
1838 u8 a_frames_transmitted_ok_low
[0x20];
1840 u8 a_frames_received_ok_high
[0x20];
1842 u8 a_frames_received_ok_low
[0x20];
1844 u8 a_frame_check_sequence_errors_high
[0x20];
1846 u8 a_frame_check_sequence_errors_low
[0x20];
1848 u8 a_alignment_errors_high
[0x20];
1850 u8 a_alignment_errors_low
[0x20];
1852 u8 a_octets_transmitted_ok_high
[0x20];
1854 u8 a_octets_transmitted_ok_low
[0x20];
1856 u8 a_octets_received_ok_high
[0x20];
1858 u8 a_octets_received_ok_low
[0x20];
1860 u8 a_multicast_frames_xmitted_ok_high
[0x20];
1862 u8 a_multicast_frames_xmitted_ok_low
[0x20];
1864 u8 a_broadcast_frames_xmitted_ok_high
[0x20];
1866 u8 a_broadcast_frames_xmitted_ok_low
[0x20];
1868 u8 a_multicast_frames_received_ok_high
[0x20];
1870 u8 a_multicast_frames_received_ok_low
[0x20];
1872 u8 a_broadcast_frames_received_ok_high
[0x20];
1874 u8 a_broadcast_frames_received_ok_low
[0x20];
1876 u8 a_in_range_length_errors_high
[0x20];
1878 u8 a_in_range_length_errors_low
[0x20];
1880 u8 a_out_of_range_length_field_high
[0x20];
1882 u8 a_out_of_range_length_field_low
[0x20];
1884 u8 a_frame_too_long_errors_high
[0x20];
1886 u8 a_frame_too_long_errors_low
[0x20];
1888 u8 a_symbol_error_during_carrier_high
[0x20];
1890 u8 a_symbol_error_during_carrier_low
[0x20];
1892 u8 a_mac_control_frames_transmitted_high
[0x20];
1894 u8 a_mac_control_frames_transmitted_low
[0x20];
1896 u8 a_mac_control_frames_received_high
[0x20];
1898 u8 a_mac_control_frames_received_low
[0x20];
1900 u8 a_unsupported_opcodes_received_high
[0x20];
1902 u8 a_unsupported_opcodes_received_low
[0x20];
1904 u8 a_pause_mac_ctrl_frames_received_high
[0x20];
1906 u8 a_pause_mac_ctrl_frames_received_low
[0x20];
1908 u8 a_pause_mac_ctrl_frames_transmitted_high
[0x20];
1910 u8 a_pause_mac_ctrl_frames_transmitted_low
[0x20];
1912 u8 reserved_at_4c0
[0x300];
1915 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits
{
1916 u8 life_time_counter_high
[0x20];
1918 u8 life_time_counter_low
[0x20];
1924 u8 l0_to_recovery_eieos
[0x20];
1926 u8 l0_to_recovery_ts
[0x20];
1928 u8 l0_to_recovery_framing
[0x20];
1930 u8 l0_to_recovery_retrain
[0x20];
1932 u8 crc_error_dllp
[0x20];
1934 u8 crc_error_tlp
[0x20];
1936 u8 tx_overflow_buffer_pkt_high
[0x20];
1938 u8 tx_overflow_buffer_pkt_low
[0x20];
1940 u8 outbound_stalled_reads
[0x20];
1942 u8 outbound_stalled_writes
[0x20];
1944 u8 outbound_stalled_reads_events
[0x20];
1946 u8 outbound_stalled_writes_events
[0x20];
1948 u8 reserved_at_200
[0x5c0];
1951 struct mlx5_ifc_cmd_inter_comp_event_bits
{
1952 u8 command_completion_vector
[0x20];
1954 u8 reserved_at_20
[0xc0];
1957 struct mlx5_ifc_stall_vl_event_bits
{
1958 u8 reserved_at_0
[0x18];
1960 u8 reserved_at_19
[0x3];
1963 u8 reserved_at_20
[0xa0];
1966 struct mlx5_ifc_db_bf_congestion_event_bits
{
1967 u8 event_subtype
[0x8];
1968 u8 reserved_at_8
[0x8];
1969 u8 congestion_level
[0x8];
1970 u8 reserved_at_18
[0x8];
1972 u8 reserved_at_20
[0xa0];
1975 struct mlx5_ifc_gpio_event_bits
{
1976 u8 reserved_at_0
[0x60];
1978 u8 gpio_event_hi
[0x20];
1980 u8 gpio_event_lo
[0x20];
1982 u8 reserved_at_a0
[0x40];
1985 struct mlx5_ifc_port_state_change_event_bits
{
1986 u8 reserved_at_0
[0x40];
1989 u8 reserved_at_44
[0x1c];
1991 u8 reserved_at_60
[0x80];
1994 struct mlx5_ifc_dropped_packet_logged_bits
{
1995 u8 reserved_at_0
[0xe0];
1999 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN
= 0x1,
2000 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR
= 0x2,
2003 struct mlx5_ifc_cq_error_bits
{
2004 u8 reserved_at_0
[0x8];
2007 u8 reserved_at_20
[0x20];
2009 u8 reserved_at_40
[0x18];
2012 u8 reserved_at_60
[0x80];
2015 struct mlx5_ifc_rdma_page_fault_event_bits
{
2016 u8 bytes_committed
[0x20];
2020 u8 reserved_at_40
[0x10];
2021 u8 packet_len
[0x10];
2023 u8 rdma_op_len
[0x20];
2027 u8 reserved_at_c0
[0x5];
2034 struct mlx5_ifc_wqe_associated_page_fault_event_bits
{
2035 u8 bytes_committed
[0x20];
2037 u8 reserved_at_20
[0x10];
2040 u8 reserved_at_40
[0x10];
2043 u8 reserved_at_60
[0x60];
2045 u8 reserved_at_c0
[0x5];
2052 struct mlx5_ifc_qp_events_bits
{
2053 u8 reserved_at_0
[0xa0];
2056 u8 reserved_at_a8
[0x18];
2058 u8 reserved_at_c0
[0x8];
2059 u8 qpn_rqn_sqn
[0x18];
2062 struct mlx5_ifc_dct_events_bits
{
2063 u8 reserved_at_0
[0xc0];
2065 u8 reserved_at_c0
[0x8];
2066 u8 dct_number
[0x18];
2069 struct mlx5_ifc_comp_event_bits
{
2070 u8 reserved_at_0
[0xc0];
2072 u8 reserved_at_c0
[0x8];
2077 MLX5_QPC_STATE_RST
= 0x0,
2078 MLX5_QPC_STATE_INIT
= 0x1,
2079 MLX5_QPC_STATE_RTR
= 0x2,
2080 MLX5_QPC_STATE_RTS
= 0x3,
2081 MLX5_QPC_STATE_SQER
= 0x4,
2082 MLX5_QPC_STATE_ERR
= 0x6,
2083 MLX5_QPC_STATE_SQD
= 0x7,
2084 MLX5_QPC_STATE_SUSPENDED
= 0x9,
2088 MLX5_QPC_ST_RC
= 0x0,
2089 MLX5_QPC_ST_UC
= 0x1,
2090 MLX5_QPC_ST_UD
= 0x2,
2091 MLX5_QPC_ST_XRC
= 0x3,
2092 MLX5_QPC_ST_DCI
= 0x5,
2093 MLX5_QPC_ST_QP0
= 0x7,
2094 MLX5_QPC_ST_QP1
= 0x8,
2095 MLX5_QPC_ST_RAW_DATAGRAM
= 0x9,
2096 MLX5_QPC_ST_REG_UMR
= 0xc,
2100 MLX5_QPC_PM_STATE_ARMED
= 0x0,
2101 MLX5_QPC_PM_STATE_REARM
= 0x1,
2102 MLX5_QPC_PM_STATE_RESERVED
= 0x2,
2103 MLX5_QPC_PM_STATE_MIGRATED
= 0x3,
2107 MLX5_QPC_OFFLOAD_TYPE_RNDV
= 0x1,
2111 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS
= 0x0,
2112 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT
= 0x1,
2116 MLX5_QPC_MTU_256_BYTES
= 0x1,
2117 MLX5_QPC_MTU_512_BYTES
= 0x2,
2118 MLX5_QPC_MTU_1K_BYTES
= 0x3,
2119 MLX5_QPC_MTU_2K_BYTES
= 0x4,
2120 MLX5_QPC_MTU_4K_BYTES
= 0x5,
2121 MLX5_QPC_MTU_RAW_ETHERNET_QP
= 0x7,
2125 MLX5_QPC_ATOMIC_MODE_IB_SPEC
= 0x1,
2126 MLX5_QPC_ATOMIC_MODE_ONLY_8B
= 0x2,
2127 MLX5_QPC_ATOMIC_MODE_UP_TO_8B
= 0x3,
2128 MLX5_QPC_ATOMIC_MODE_UP_TO_16B
= 0x4,
2129 MLX5_QPC_ATOMIC_MODE_UP_TO_32B
= 0x5,
2130 MLX5_QPC_ATOMIC_MODE_UP_TO_64B
= 0x6,
2131 MLX5_QPC_ATOMIC_MODE_UP_TO_128B
= 0x7,
2132 MLX5_QPC_ATOMIC_MODE_UP_TO_256B
= 0x8,
2136 MLX5_QPC_CS_REQ_DISABLE
= 0x0,
2137 MLX5_QPC_CS_REQ_UP_TO_32B
= 0x11,
2138 MLX5_QPC_CS_REQ_UP_TO_64B
= 0x22,
2142 MLX5_QPC_CS_RES_DISABLE
= 0x0,
2143 MLX5_QPC_CS_RES_UP_TO_32B
= 0x1,
2144 MLX5_QPC_CS_RES_UP_TO_64B
= 0x2,
2147 struct mlx5_ifc_qpc_bits
{
2149 u8 lag_tx_port_affinity
[0x4];
2151 u8 reserved_at_10
[0x3];
2153 u8 reserved_at_15
[0x3];
2154 u8 offload_type
[0x4];
2155 u8 end_padding_mode
[0x2];
2156 u8 reserved_at_1e
[0x2];
2158 u8 wq_signature
[0x1];
2159 u8 block_lb_mc
[0x1];
2160 u8 atomic_like_write_en
[0x1];
2161 u8 latency_sensitive
[0x1];
2162 u8 reserved_at_24
[0x1];
2163 u8 drain_sigerr
[0x1];
2164 u8 reserved_at_26
[0x2];
2168 u8 log_msg_max
[0x5];
2169 u8 reserved_at_48
[0x1];
2170 u8 log_rq_size
[0x4];
2171 u8 log_rq_stride
[0x3];
2173 u8 log_sq_size
[0x4];
2174 u8 reserved_at_55
[0x6];
2176 u8 ulp_stateless_offload_mode
[0x4];
2178 u8 counter_set_id
[0x8];
2181 u8 reserved_at_80
[0x8];
2182 u8 user_index
[0x18];
2184 u8 reserved_at_a0
[0x3];
2185 u8 log_page_size
[0x5];
2186 u8 remote_qpn
[0x18];
2188 struct mlx5_ifc_ads_bits primary_address_path
;
2190 struct mlx5_ifc_ads_bits secondary_address_path
;
2192 u8 log_ack_req_freq
[0x4];
2193 u8 reserved_at_384
[0x4];
2194 u8 log_sra_max
[0x3];
2195 u8 reserved_at_38b
[0x2];
2196 u8 retry_count
[0x3];
2198 u8 reserved_at_393
[0x1];
2200 u8 cur_rnr_retry
[0x3];
2201 u8 cur_retry_count
[0x3];
2202 u8 reserved_at_39b
[0x5];
2204 u8 reserved_at_3a0
[0x20];
2206 u8 reserved_at_3c0
[0x8];
2207 u8 next_send_psn
[0x18];
2209 u8 reserved_at_3e0
[0x8];
2212 u8 reserved_at_400
[0x8];
2215 u8 reserved_at_420
[0x20];
2217 u8 reserved_at_440
[0x8];
2218 u8 last_acked_psn
[0x18];
2220 u8 reserved_at_460
[0x8];
2223 u8 reserved_at_480
[0x8];
2224 u8 log_rra_max
[0x3];
2225 u8 reserved_at_48b
[0x1];
2226 u8 atomic_mode
[0x4];
2230 u8 reserved_at_493
[0x1];
2231 u8 page_offset
[0x6];
2232 u8 reserved_at_49a
[0x3];
2233 u8 cd_slave_receive
[0x1];
2234 u8 cd_slave_send
[0x1];
2237 u8 reserved_at_4a0
[0x3];
2238 u8 min_rnr_nak
[0x5];
2239 u8 next_rcv_psn
[0x18];
2241 u8 reserved_at_4c0
[0x8];
2244 u8 reserved_at_4e0
[0x8];
2251 u8 reserved_at_560
[0x5];
2253 u8 srqn_rmpn_xrqn
[0x18];
2255 u8 reserved_at_580
[0x8];
2258 u8 hw_sq_wqebb_counter
[0x10];
2259 u8 sw_sq_wqebb_counter
[0x10];
2261 u8 hw_rq_counter
[0x20];
2263 u8 sw_rq_counter
[0x20];
2265 u8 reserved_at_600
[0x20];
2267 u8 reserved_at_620
[0xf];
2272 u8 dc_access_key
[0x40];
2274 u8 reserved_at_680
[0xc0];
2277 struct mlx5_ifc_roce_addr_layout_bits
{
2278 u8 source_l3_address
[16][0x8];
2280 u8 reserved_at_80
[0x3];
2283 u8 source_mac_47_32
[0x10];
2285 u8 source_mac_31_0
[0x20];
2287 u8 reserved_at_c0
[0x14];
2288 u8 roce_l3_type
[0x4];
2289 u8 roce_version
[0x8];
2291 u8 reserved_at_e0
[0x20];
2294 union mlx5_ifc_hca_cap_union_bits
{
2295 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap
;
2296 struct mlx5_ifc_odp_cap_bits odp_cap
;
2297 struct mlx5_ifc_atomic_caps_bits atomic_caps
;
2298 struct mlx5_ifc_roce_cap_bits roce_cap
;
2299 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps
;
2300 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap
;
2301 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap
;
2302 struct mlx5_ifc_e_switch_cap_bits e_switch_cap
;
2303 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap
;
2304 struct mlx5_ifc_qos_cap_bits qos_cap
;
2305 struct mlx5_ifc_fpga_cap_bits fpga_cap
;
2306 u8 reserved_at_0
[0x8000];
2310 MLX5_FLOW_CONTEXT_ACTION_ALLOW
= 0x1,
2311 MLX5_FLOW_CONTEXT_ACTION_DROP
= 0x2,
2312 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
= 0x4,
2313 MLX5_FLOW_CONTEXT_ACTION_COUNT
= 0x8,
2314 MLX5_FLOW_CONTEXT_ACTION_ENCAP
= 0x10,
2315 MLX5_FLOW_CONTEXT_ACTION_DECAP
= 0x20,
2316 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR
= 0x40,
2319 struct mlx5_ifc_flow_context_bits
{
2320 u8 reserved_at_0
[0x20];
2324 u8 reserved_at_40
[0x8];
2327 u8 reserved_at_60
[0x10];
2330 u8 reserved_at_80
[0x8];
2331 u8 destination_list_size
[0x18];
2333 u8 reserved_at_a0
[0x8];
2334 u8 flow_counter_list_size
[0x18];
2338 u8 modify_header_id
[0x20];
2340 u8 reserved_at_100
[0x100];
2342 struct mlx5_ifc_fte_match_param_bits match_value
;
2344 u8 reserved_at_1200
[0x600];
2346 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination
[0];
2350 MLX5_XRC_SRQC_STATE_GOOD
= 0x0,
2351 MLX5_XRC_SRQC_STATE_ERROR
= 0x1,
2354 struct mlx5_ifc_xrc_srqc_bits
{
2356 u8 log_xrc_srq_size
[0x4];
2357 u8 reserved_at_8
[0x18];
2359 u8 wq_signature
[0x1];
2361 u8 reserved_at_22
[0x1];
2363 u8 basic_cyclic_rcv_wqe
[0x1];
2364 u8 log_rq_stride
[0x3];
2367 u8 page_offset
[0x6];
2368 u8 reserved_at_46
[0x2];
2371 u8 reserved_at_60
[0x20];
2373 u8 user_index_equal_xrc_srqn
[0x1];
2374 u8 reserved_at_81
[0x1];
2375 u8 log_page_size
[0x6];
2376 u8 user_index
[0x18];
2378 u8 reserved_at_a0
[0x20];
2380 u8 reserved_at_c0
[0x8];
2386 u8 reserved_at_100
[0x40];
2388 u8 db_record_addr_h
[0x20];
2390 u8 db_record_addr_l
[0x1e];
2391 u8 reserved_at_17e
[0x2];
2393 u8 reserved_at_180
[0x80];
2396 struct mlx5_ifc_traffic_counter_bits
{
2402 struct mlx5_ifc_tisc_bits
{
2403 u8 strict_lag_tx_port_affinity
[0x1];
2404 u8 reserved_at_1
[0x3];
2405 u8 lag_tx_port_affinity
[0x04];
2407 u8 reserved_at_8
[0x4];
2409 u8 reserved_at_10
[0x10];
2411 u8 reserved_at_20
[0x100];
2413 u8 reserved_at_120
[0x8];
2414 u8 transport_domain
[0x18];
2416 u8 reserved_at_140
[0x8];
2417 u8 underlay_qpn
[0x18];
2418 u8 reserved_at_160
[0x3a0];
2422 MLX5_TIRC_DISP_TYPE_DIRECT
= 0x0,
2423 MLX5_TIRC_DISP_TYPE_INDIRECT
= 0x1,
2427 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
= 0x1,
2428 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
= 0x2,
2432 MLX5_RX_HASH_FN_NONE
= 0x0,
2433 MLX5_RX_HASH_FN_INVERTED_XOR8
= 0x1,
2434 MLX5_RX_HASH_FN_TOEPLITZ
= 0x2,
2438 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_
= 0x1,
2439 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_
= 0x2,
2442 struct mlx5_ifc_tirc_bits
{
2443 u8 reserved_at_0
[0x20];
2446 u8 reserved_at_24
[0x1c];
2448 u8 reserved_at_40
[0x40];
2450 u8 reserved_at_80
[0x4];
2451 u8 lro_timeout_period_usecs
[0x10];
2452 u8 lro_enable_mask
[0x4];
2453 u8 lro_max_ip_payload_size
[0x8];
2455 u8 reserved_at_a0
[0x40];
2457 u8 reserved_at_e0
[0x8];
2458 u8 inline_rqn
[0x18];
2460 u8 rx_hash_symmetric
[0x1];
2461 u8 reserved_at_101
[0x1];
2462 u8 tunneled_offload_en
[0x1];
2463 u8 reserved_at_103
[0x5];
2464 u8 indirect_table
[0x18];
2467 u8 reserved_at_124
[0x2];
2468 u8 self_lb_block
[0x2];
2469 u8 transport_domain
[0x18];
2471 u8 rx_hash_toeplitz_key
[10][0x20];
2473 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer
;
2475 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner
;
2477 u8 reserved_at_2c0
[0x4c0];
2481 MLX5_SRQC_STATE_GOOD
= 0x0,
2482 MLX5_SRQC_STATE_ERROR
= 0x1,
2485 struct mlx5_ifc_srqc_bits
{
2487 u8 log_srq_size
[0x4];
2488 u8 reserved_at_8
[0x18];
2490 u8 wq_signature
[0x1];
2492 u8 reserved_at_22
[0x1];
2494 u8 reserved_at_24
[0x1];
2495 u8 log_rq_stride
[0x3];
2498 u8 page_offset
[0x6];
2499 u8 reserved_at_46
[0x2];
2502 u8 reserved_at_60
[0x20];
2504 u8 reserved_at_80
[0x2];
2505 u8 log_page_size
[0x6];
2506 u8 reserved_at_88
[0x18];
2508 u8 reserved_at_a0
[0x20];
2510 u8 reserved_at_c0
[0x8];
2516 u8 reserved_at_100
[0x40];
2520 u8 reserved_at_180
[0x80];
2524 MLX5_SQC_STATE_RST
= 0x0,
2525 MLX5_SQC_STATE_RDY
= 0x1,
2526 MLX5_SQC_STATE_ERR
= 0x3,
2529 struct mlx5_ifc_sqc_bits
{
2533 u8 flush_in_error_en
[0x1];
2534 u8 allow_multi_pkt_send_wqe
[0x1];
2535 u8 min_wqe_inline_mode
[0x3];
2540 u8 reserved_at_f
[0x11];
2542 u8 reserved_at_20
[0x8];
2543 u8 user_index
[0x18];
2545 u8 reserved_at_40
[0x8];
2548 u8 reserved_at_60
[0x8];
2549 u8 hairpin_peer_rq
[0x18];
2551 u8 reserved_at_80
[0x10];
2552 u8 hairpin_peer_vhca
[0x10];
2554 u8 reserved_at_a0
[0x50];
2556 u8 packet_pacing_rate_limit_index
[0x10];
2557 u8 tis_lst_sz
[0x10];
2558 u8 reserved_at_110
[0x10];
2560 u8 reserved_at_120
[0x40];
2562 u8 reserved_at_160
[0x8];
2565 struct mlx5_ifc_wq_bits wq
;
2569 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR
= 0x0,
2570 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT
= 0x1,
2571 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC
= 0x2,
2572 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC
= 0x3,
2575 struct mlx5_ifc_scheduling_context_bits
{
2576 u8 element_type
[0x8];
2577 u8 reserved_at_8
[0x18];
2579 u8 element_attributes
[0x20];
2581 u8 parent_element_id
[0x20];
2583 u8 reserved_at_60
[0x40];
2587 u8 max_average_bw
[0x20];
2589 u8 reserved_at_e0
[0x120];
2592 struct mlx5_ifc_rqtc_bits
{
2593 u8 reserved_at_0
[0xa0];
2595 u8 reserved_at_a0
[0x10];
2596 u8 rqt_max_size
[0x10];
2598 u8 reserved_at_c0
[0x10];
2599 u8 rqt_actual_size
[0x10];
2601 u8 reserved_at_e0
[0x6a0];
2603 struct mlx5_ifc_rq_num_bits rq_num
[0];
2607 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
= 0x0,
2608 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP
= 0x1,
2612 MLX5_RQC_STATE_RST
= 0x0,
2613 MLX5_RQC_STATE_RDY
= 0x1,
2614 MLX5_RQC_STATE_ERR
= 0x3,
2617 struct mlx5_ifc_rqc_bits
{
2619 u8 delay_drop_en
[0x1];
2620 u8 scatter_fcs
[0x1];
2622 u8 mem_rq_type
[0x4];
2624 u8 reserved_at_c
[0x1];
2625 u8 flush_in_error_en
[0x1];
2627 u8 reserved_at_f
[0x11];
2629 u8 reserved_at_20
[0x8];
2630 u8 user_index
[0x18];
2632 u8 reserved_at_40
[0x8];
2635 u8 counter_set_id
[0x8];
2636 u8 reserved_at_68
[0x18];
2638 u8 reserved_at_80
[0x8];
2641 u8 reserved_at_a0
[0x8];
2642 u8 hairpin_peer_sq
[0x18];
2644 u8 reserved_at_c0
[0x10];
2645 u8 hairpin_peer_vhca
[0x10];
2647 u8 reserved_at_e0
[0xa0];
2649 struct mlx5_ifc_wq_bits wq
;
2653 MLX5_RMPC_STATE_RDY
= 0x1,
2654 MLX5_RMPC_STATE_ERR
= 0x3,
2657 struct mlx5_ifc_rmpc_bits
{
2658 u8 reserved_at_0
[0x8];
2660 u8 reserved_at_c
[0x14];
2662 u8 basic_cyclic_rcv_wqe
[0x1];
2663 u8 reserved_at_21
[0x1f];
2665 u8 reserved_at_40
[0x140];
2667 struct mlx5_ifc_wq_bits wq
;
2670 struct mlx5_ifc_nic_vport_context_bits
{
2671 u8 reserved_at_0
[0x5];
2672 u8 min_wqe_inline_mode
[0x3];
2673 u8 reserved_at_8
[0x15];
2674 u8 disable_mc_local_lb
[0x1];
2675 u8 disable_uc_local_lb
[0x1];
2678 u8 arm_change_event
[0x1];
2679 u8 reserved_at_21
[0x1a];
2680 u8 event_on_mtu
[0x1];
2681 u8 event_on_promisc_change
[0x1];
2682 u8 event_on_vlan_change
[0x1];
2683 u8 event_on_mc_address_change
[0x1];
2684 u8 event_on_uc_address_change
[0x1];
2686 u8 reserved_at_40
[0xc];
2688 u8 affiliation_criteria
[0x4];
2689 u8 affiliated_vhca_id
[0x10];
2691 u8 reserved_at_60
[0xd0];
2695 u8 system_image_guid
[0x40];
2699 u8 reserved_at_200
[0x140];
2700 u8 qkey_violation_counter
[0x10];
2701 u8 reserved_at_350
[0x430];
2705 u8 promisc_all
[0x1];
2706 u8 reserved_at_783
[0x2];
2707 u8 allowed_list_type
[0x3];
2708 u8 reserved_at_788
[0xc];
2709 u8 allowed_list_size
[0xc];
2711 struct mlx5_ifc_mac_address_layout_bits permanent_address
;
2713 u8 reserved_at_7e0
[0x20];
2715 u8 current_uc_mac_address
[0][0x40];
2719 MLX5_MKC_ACCESS_MODE_PA
= 0x0,
2720 MLX5_MKC_ACCESS_MODE_MTT
= 0x1,
2721 MLX5_MKC_ACCESS_MODE_KLMS
= 0x2,
2722 MLX5_MKC_ACCESS_MODE_KSM
= 0x3,
2723 MLX5_MKC_ACCESS_MODE_MEMIC
= 0x5,
2726 struct mlx5_ifc_mkc_bits
{
2727 u8 reserved_at_0
[0x1];
2729 u8 reserved_at_2
[0x1];
2730 u8 access_mode_4_2
[0x3];
2731 u8 reserved_at_6
[0x7];
2732 u8 relaxed_ordering_write
[0x1];
2733 u8 reserved_at_e
[0x1];
2734 u8 small_fence_on_rdma_read_response
[0x1];
2741 u8 access_mode_1_0
[0x2];
2742 u8 reserved_at_18
[0x8];
2747 u8 reserved_at_40
[0x20];
2752 u8 reserved_at_63
[0x2];
2753 u8 expected_sigerr_count
[0x1];
2754 u8 reserved_at_66
[0x1];
2758 u8 start_addr
[0x40];
2762 u8 bsf_octword_size
[0x20];
2764 u8 reserved_at_120
[0x80];
2766 u8 translations_octword_size
[0x20];
2768 u8 reserved_at_1c0
[0x1b];
2769 u8 log_page_size
[0x5];
2771 u8 reserved_at_1e0
[0x20];
2774 struct mlx5_ifc_pkey_bits
{
2775 u8 reserved_at_0
[0x10];
2779 struct mlx5_ifc_array128_auto_bits
{
2780 u8 array128_auto
[16][0x8];
2783 struct mlx5_ifc_hca_vport_context_bits
{
2784 u8 field_select
[0x20];
2786 u8 reserved_at_20
[0xe0];
2788 u8 sm_virt_aware
[0x1];
2791 u8 grh_required
[0x1];
2792 u8 reserved_at_104
[0xc];
2793 u8 port_physical_state
[0x4];
2794 u8 vport_state_policy
[0x4];
2796 u8 vport_state
[0x4];
2798 u8 reserved_at_120
[0x20];
2800 u8 system_image_guid
[0x40];
2808 u8 cap_mask1_field_select
[0x20];
2812 u8 cap_mask2_field_select
[0x20];
2814 u8 reserved_at_280
[0x80];
2817 u8 reserved_at_310
[0x4];
2818 u8 init_type_reply
[0x4];
2820 u8 subnet_timeout
[0x5];
2824 u8 reserved_at_334
[0xc];
2826 u8 qkey_violation_counter
[0x10];
2827 u8 pkey_violation_counter
[0x10];
2829 u8 reserved_at_360
[0xca0];
2832 struct mlx5_ifc_esw_vport_context_bits
{
2833 u8 reserved_at_0
[0x3];
2834 u8 vport_svlan_strip
[0x1];
2835 u8 vport_cvlan_strip
[0x1];
2836 u8 vport_svlan_insert
[0x1];
2837 u8 vport_cvlan_insert
[0x2];
2838 u8 reserved_at_8
[0x18];
2840 u8 reserved_at_20
[0x20];
2849 u8 reserved_at_60
[0x7a0];
2853 MLX5_EQC_STATUS_OK
= 0x0,
2854 MLX5_EQC_STATUS_EQ_WRITE_FAILURE
= 0xa,
2858 MLX5_EQC_ST_ARMED
= 0x9,
2859 MLX5_EQC_ST_FIRED
= 0xa,
2862 struct mlx5_ifc_eqc_bits
{
2864 u8 reserved_at_4
[0x9];
2867 u8 reserved_at_f
[0x5];
2869 u8 reserved_at_18
[0x8];
2871 u8 reserved_at_20
[0x20];
2873 u8 reserved_at_40
[0x14];
2874 u8 page_offset
[0x6];
2875 u8 reserved_at_5a
[0x6];
2877 u8 reserved_at_60
[0x3];
2878 u8 log_eq_size
[0x5];
2881 u8 reserved_at_80
[0x20];
2883 u8 reserved_at_a0
[0x18];
2886 u8 reserved_at_c0
[0x3];
2887 u8 log_page_size
[0x5];
2888 u8 reserved_at_c8
[0x18];
2890 u8 reserved_at_e0
[0x60];
2892 u8 reserved_at_140
[0x8];
2893 u8 consumer_counter
[0x18];
2895 u8 reserved_at_160
[0x8];
2896 u8 producer_counter
[0x18];
2898 u8 reserved_at_180
[0x80];
2902 MLX5_DCTC_STATE_ACTIVE
= 0x0,
2903 MLX5_DCTC_STATE_DRAINING
= 0x1,
2904 MLX5_DCTC_STATE_DRAINED
= 0x2,
2908 MLX5_DCTC_CS_RES_DISABLE
= 0x0,
2909 MLX5_DCTC_CS_RES_NA
= 0x1,
2910 MLX5_DCTC_CS_RES_UP_TO_64B
= 0x2,
2914 MLX5_DCTC_MTU_256_BYTES
= 0x1,
2915 MLX5_DCTC_MTU_512_BYTES
= 0x2,
2916 MLX5_DCTC_MTU_1K_BYTES
= 0x3,
2917 MLX5_DCTC_MTU_2K_BYTES
= 0x4,
2918 MLX5_DCTC_MTU_4K_BYTES
= 0x5,
2921 struct mlx5_ifc_dctc_bits
{
2922 u8 reserved_at_0
[0x4];
2924 u8 reserved_at_8
[0x18];
2926 u8 reserved_at_20
[0x8];
2927 u8 user_index
[0x18];
2929 u8 reserved_at_40
[0x8];
2932 u8 counter_set_id
[0x8];
2933 u8 atomic_mode
[0x4];
2937 u8 atomic_like_write_en
[0x1];
2938 u8 latency_sensitive
[0x1];
2941 u8 reserved_at_73
[0xd];
2943 u8 reserved_at_80
[0x8];
2945 u8 reserved_at_90
[0x3];
2946 u8 min_rnr_nak
[0x5];
2947 u8 reserved_at_98
[0x8];
2949 u8 reserved_at_a0
[0x8];
2952 u8 reserved_at_c0
[0x8];
2956 u8 reserved_at_e8
[0x4];
2957 u8 flow_label
[0x14];
2959 u8 dc_access_key
[0x40];
2961 u8 reserved_at_140
[0x5];
2964 u8 pkey_index
[0x10];
2966 u8 reserved_at_160
[0x8];
2967 u8 my_addr_index
[0x8];
2968 u8 reserved_at_170
[0x8];
2971 u8 dc_access_key_violation_count
[0x20];
2973 u8 reserved_at_1a0
[0x14];
2979 u8 reserved_at_1c0
[0x40];
2983 MLX5_CQC_STATUS_OK
= 0x0,
2984 MLX5_CQC_STATUS_CQ_OVERFLOW
= 0x9,
2985 MLX5_CQC_STATUS_CQ_WRITE_FAIL
= 0xa,
2989 MLX5_CQC_CQE_SZ_64_BYTES
= 0x0,
2990 MLX5_CQC_CQE_SZ_128_BYTES
= 0x1,
2994 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED
= 0x6,
2995 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED
= 0x9,
2996 MLX5_CQC_ST_FIRED
= 0xa,
3000 MLX5_CQ_PERIOD_MODE_START_FROM_EQE
= 0x0,
3001 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
= 0x1,
3002 MLX5_CQ_PERIOD_NUM_MODES
3005 struct mlx5_ifc_cqc_bits
{
3007 u8 reserved_at_4
[0x4];
3010 u8 reserved_at_c
[0x1];
3011 u8 scqe_break_moderation_en
[0x1];
3013 u8 cq_period_mode
[0x2];
3014 u8 cqe_comp_en
[0x1];
3015 u8 mini_cqe_res_format
[0x2];
3017 u8 reserved_at_18
[0x8];
3019 u8 reserved_at_20
[0x20];
3021 u8 reserved_at_40
[0x14];
3022 u8 page_offset
[0x6];
3023 u8 reserved_at_5a
[0x6];
3025 u8 reserved_at_60
[0x3];
3026 u8 log_cq_size
[0x5];
3029 u8 reserved_at_80
[0x4];
3031 u8 cq_max_count
[0x10];
3033 u8 reserved_at_a0
[0x18];
3036 u8 reserved_at_c0
[0x3];
3037 u8 log_page_size
[0x5];
3038 u8 reserved_at_c8
[0x18];
3040 u8 reserved_at_e0
[0x20];
3042 u8 reserved_at_100
[0x8];
3043 u8 last_notified_index
[0x18];
3045 u8 reserved_at_120
[0x8];
3046 u8 last_solicit_index
[0x18];
3048 u8 reserved_at_140
[0x8];
3049 u8 consumer_counter
[0x18];
3051 u8 reserved_at_160
[0x8];
3052 u8 producer_counter
[0x18];
3054 u8 reserved_at_180
[0x40];
3059 union mlx5_ifc_cong_control_roce_ecn_auto_bits
{
3060 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp
;
3061 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp
;
3062 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np
;
3063 u8 reserved_at_0
[0x800];
3066 struct mlx5_ifc_query_adapter_param_block_bits
{
3067 u8 reserved_at_0
[0xc0];
3069 u8 reserved_at_c0
[0x8];
3070 u8 ieee_vendor_id
[0x18];
3072 u8 reserved_at_e0
[0x10];
3073 u8 vsd_vendor_id
[0x10];
3077 u8 vsd_contd_psid
[16][0x8];
3081 MLX5_XRQC_STATE_GOOD
= 0x0,
3082 MLX5_XRQC_STATE_ERROR
= 0x1,
3086 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY
= 0x0,
3087 MLX5_XRQC_TOPOLOGY_TAG_MATCHING
= 0x1,
3091 MLX5_XRQC_OFFLOAD_RNDV
= 0x1,
3094 struct mlx5_ifc_tag_matching_topology_context_bits
{
3095 u8 log_matching_list_sz
[0x4];
3096 u8 reserved_at_4
[0xc];
3097 u8 append_next_index
[0x10];
3099 u8 sw_phase_cnt
[0x10];
3100 u8 hw_phase_cnt
[0x10];
3102 u8 reserved_at_40
[0x40];
3105 struct mlx5_ifc_xrqc_bits
{
3108 u8 reserved_at_5
[0xf];
3110 u8 reserved_at_18
[0x4];
3113 u8 reserved_at_20
[0x8];
3114 u8 user_index
[0x18];
3116 u8 reserved_at_40
[0x8];
3119 u8 reserved_at_60
[0xa0];
3121 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context
;
3123 u8 reserved_at_180
[0x280];
3125 struct mlx5_ifc_wq_bits wq
;
3128 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits
{
3129 struct mlx5_ifc_modify_field_select_bits modify_field_select
;
3130 struct mlx5_ifc_resize_field_select_bits resize_field_select
;
3131 u8 reserved_at_0
[0x20];
3134 union mlx5_ifc_field_select_802_1_r_roce_auto_bits
{
3135 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp
;
3136 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp
;
3137 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np
;
3138 u8 reserved_at_0
[0x20];
3141 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits
{
3142 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
3143 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
3144 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
3145 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
3146 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
3147 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
3148 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
3149 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
3150 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
3151 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs
;
3152 u8 reserved_at_0
[0x7c0];
3155 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits
{
3156 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout
;
3157 u8 reserved_at_0
[0x7c0];
3160 union mlx5_ifc_event_auto_bits
{
3161 struct mlx5_ifc_comp_event_bits comp_event
;
3162 struct mlx5_ifc_dct_events_bits dct_events
;
3163 struct mlx5_ifc_qp_events_bits qp_events
;
3164 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event
;
3165 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event
;
3166 struct mlx5_ifc_cq_error_bits cq_error
;
3167 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged
;
3168 struct mlx5_ifc_port_state_change_event_bits port_state_change_event
;
3169 struct mlx5_ifc_gpio_event_bits gpio_event
;
3170 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event
;
3171 struct mlx5_ifc_stall_vl_event_bits stall_vl_event
;
3172 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event
;
3173 u8 reserved_at_0
[0xe0];
3176 struct mlx5_ifc_health_buffer_bits
{
3177 u8 reserved_at_0
[0x100];
3179 u8 assert_existptr
[0x20];
3181 u8 assert_callra
[0x20];
3183 u8 reserved_at_140
[0x40];
3185 u8 fw_version
[0x20];
3189 u8 reserved_at_1c0
[0x20];
3191 u8 irisc_index
[0x8];
3196 struct mlx5_ifc_register_loopback_control_bits
{
3198 u8 reserved_at_1
[0x7];
3200 u8 reserved_at_10
[0x10];
3202 u8 reserved_at_20
[0x60];
3205 struct mlx5_ifc_vport_tc_element_bits
{
3206 u8 traffic_class
[0x4];
3207 u8 reserved_at_4
[0xc];
3208 u8 vport_number
[0x10];
3211 struct mlx5_ifc_vport_element_bits
{
3212 u8 reserved_at_0
[0x10];
3213 u8 vport_number
[0x10];
3217 TSAR_ELEMENT_TSAR_TYPE_DWRR
= 0x0,
3218 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN
= 0x1,
3219 TSAR_ELEMENT_TSAR_TYPE_ETS
= 0x2,
3222 struct mlx5_ifc_tsar_element_bits
{
3223 u8 reserved_at_0
[0x8];
3225 u8 reserved_at_10
[0x10];
3229 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS
= 0x0,
3230 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL
= 0x1,
3233 struct mlx5_ifc_teardown_hca_out_bits
{
3235 u8 reserved_at_8
[0x18];
3239 u8 reserved_at_40
[0x3f];
3241 u8 force_state
[0x1];
3245 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE
= 0x0,
3246 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE
= 0x1,
3249 struct mlx5_ifc_teardown_hca_in_bits
{
3251 u8 reserved_at_10
[0x10];
3253 u8 reserved_at_20
[0x10];
3256 u8 reserved_at_40
[0x10];
3259 u8 reserved_at_60
[0x20];
3262 struct mlx5_ifc_sqerr2rts_qp_out_bits
{
3264 u8 reserved_at_8
[0x18];
3268 u8 reserved_at_40
[0x40];
3271 struct mlx5_ifc_sqerr2rts_qp_in_bits
{
3273 u8 reserved_at_10
[0x10];
3275 u8 reserved_at_20
[0x10];
3278 u8 reserved_at_40
[0x8];
3281 u8 reserved_at_60
[0x20];
3283 u8 opt_param_mask
[0x20];
3285 u8 reserved_at_a0
[0x20];
3287 struct mlx5_ifc_qpc_bits qpc
;
3289 u8 reserved_at_800
[0x80];
3292 struct mlx5_ifc_sqd2rts_qp_out_bits
{
3294 u8 reserved_at_8
[0x18];
3298 u8 reserved_at_40
[0x40];
3301 struct mlx5_ifc_sqd2rts_qp_in_bits
{
3303 u8 reserved_at_10
[0x10];
3305 u8 reserved_at_20
[0x10];
3308 u8 reserved_at_40
[0x8];
3311 u8 reserved_at_60
[0x20];
3313 u8 opt_param_mask
[0x20];
3315 u8 reserved_at_a0
[0x20];
3317 struct mlx5_ifc_qpc_bits qpc
;
3319 u8 reserved_at_800
[0x80];
3322 struct mlx5_ifc_set_roce_address_out_bits
{
3324 u8 reserved_at_8
[0x18];
3328 u8 reserved_at_40
[0x40];
3331 struct mlx5_ifc_set_roce_address_in_bits
{
3333 u8 reserved_at_10
[0x10];
3335 u8 reserved_at_20
[0x10];
3338 u8 roce_address_index
[0x10];
3339 u8 reserved_at_50
[0xc];
3340 u8 vhca_port_num
[0x4];
3342 u8 reserved_at_60
[0x20];
3344 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
3347 struct mlx5_ifc_set_mad_demux_out_bits
{
3349 u8 reserved_at_8
[0x18];
3353 u8 reserved_at_40
[0x40];
3357 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL
= 0x0,
3358 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE
= 0x2,
3361 struct mlx5_ifc_set_mad_demux_in_bits
{
3363 u8 reserved_at_10
[0x10];
3365 u8 reserved_at_20
[0x10];
3368 u8 reserved_at_40
[0x20];
3370 u8 reserved_at_60
[0x6];
3372 u8 reserved_at_68
[0x18];
3375 struct mlx5_ifc_set_l2_table_entry_out_bits
{
3377 u8 reserved_at_8
[0x18];
3381 u8 reserved_at_40
[0x40];
3384 struct mlx5_ifc_set_l2_table_entry_in_bits
{
3386 u8 reserved_at_10
[0x10];
3388 u8 reserved_at_20
[0x10];
3391 u8 reserved_at_40
[0x60];
3393 u8 reserved_at_a0
[0x8];
3394 u8 table_index
[0x18];
3396 u8 reserved_at_c0
[0x20];
3398 u8 reserved_at_e0
[0x13];
3402 struct mlx5_ifc_mac_address_layout_bits mac_address
;
3404 u8 reserved_at_140
[0xc0];
3407 struct mlx5_ifc_set_issi_out_bits
{
3409 u8 reserved_at_8
[0x18];
3413 u8 reserved_at_40
[0x40];
3416 struct mlx5_ifc_set_issi_in_bits
{
3418 u8 reserved_at_10
[0x10];
3420 u8 reserved_at_20
[0x10];
3423 u8 reserved_at_40
[0x10];
3424 u8 current_issi
[0x10];
3426 u8 reserved_at_60
[0x20];
3429 struct mlx5_ifc_set_hca_cap_out_bits
{
3431 u8 reserved_at_8
[0x18];
3435 u8 reserved_at_40
[0x40];
3438 struct mlx5_ifc_set_hca_cap_in_bits
{
3440 u8 reserved_at_10
[0x10];
3442 u8 reserved_at_20
[0x10];
3445 u8 reserved_at_40
[0x40];
3447 union mlx5_ifc_hca_cap_union_bits capability
;
3451 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION
= 0x0,
3452 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG
= 0x1,
3453 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST
= 0x2,
3454 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS
= 0x3
3457 struct mlx5_ifc_set_fte_out_bits
{
3459 u8 reserved_at_8
[0x18];
3463 u8 reserved_at_40
[0x40];
3466 struct mlx5_ifc_set_fte_in_bits
{
3468 u8 reserved_at_10
[0x10];
3470 u8 reserved_at_20
[0x10];
3473 u8 other_vport
[0x1];
3474 u8 reserved_at_41
[0xf];
3475 u8 vport_number
[0x10];
3477 u8 reserved_at_60
[0x20];
3480 u8 reserved_at_88
[0x18];
3482 u8 reserved_at_a0
[0x8];
3485 u8 reserved_at_c0
[0x18];
3486 u8 modify_enable_mask
[0x8];
3488 u8 reserved_at_e0
[0x20];
3490 u8 flow_index
[0x20];
3492 u8 reserved_at_120
[0xe0];
3494 struct mlx5_ifc_flow_context_bits flow_context
;
3497 struct mlx5_ifc_rts2rts_qp_out_bits
{
3499 u8 reserved_at_8
[0x18];
3503 u8 reserved_at_40
[0x40];
3506 struct mlx5_ifc_rts2rts_qp_in_bits
{
3508 u8 reserved_at_10
[0x10];
3510 u8 reserved_at_20
[0x10];
3513 u8 reserved_at_40
[0x8];
3516 u8 reserved_at_60
[0x20];
3518 u8 opt_param_mask
[0x20];
3520 u8 reserved_at_a0
[0x20];
3522 struct mlx5_ifc_qpc_bits qpc
;
3524 u8 reserved_at_800
[0x80];
3527 struct mlx5_ifc_rtr2rts_qp_out_bits
{
3529 u8 reserved_at_8
[0x18];
3533 u8 reserved_at_40
[0x40];
3536 struct mlx5_ifc_rtr2rts_qp_in_bits
{
3538 u8 reserved_at_10
[0x10];
3540 u8 reserved_at_20
[0x10];
3543 u8 reserved_at_40
[0x8];
3546 u8 reserved_at_60
[0x20];
3548 u8 opt_param_mask
[0x20];
3550 u8 reserved_at_a0
[0x20];
3552 struct mlx5_ifc_qpc_bits qpc
;
3554 u8 reserved_at_800
[0x80];
3557 struct mlx5_ifc_rst2init_qp_out_bits
{
3559 u8 reserved_at_8
[0x18];
3563 u8 reserved_at_40
[0x40];
3566 struct mlx5_ifc_rst2init_qp_in_bits
{
3568 u8 reserved_at_10
[0x10];
3570 u8 reserved_at_20
[0x10];
3573 u8 reserved_at_40
[0x8];
3576 u8 reserved_at_60
[0x20];
3578 u8 opt_param_mask
[0x20];
3580 u8 reserved_at_a0
[0x20];
3582 struct mlx5_ifc_qpc_bits qpc
;
3584 u8 reserved_at_800
[0x80];
3587 struct mlx5_ifc_query_xrq_out_bits
{
3589 u8 reserved_at_8
[0x18];
3593 u8 reserved_at_40
[0x40];
3595 struct mlx5_ifc_xrqc_bits xrq_context
;
3598 struct mlx5_ifc_query_xrq_in_bits
{
3600 u8 reserved_at_10
[0x10];
3602 u8 reserved_at_20
[0x10];
3605 u8 reserved_at_40
[0x8];
3608 u8 reserved_at_60
[0x20];
3611 struct mlx5_ifc_query_xrc_srq_out_bits
{
3613 u8 reserved_at_8
[0x18];
3617 u8 reserved_at_40
[0x40];
3619 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
3621 u8 reserved_at_280
[0x600];
3626 struct mlx5_ifc_query_xrc_srq_in_bits
{
3628 u8 reserved_at_10
[0x10];
3630 u8 reserved_at_20
[0x10];
3633 u8 reserved_at_40
[0x8];
3636 u8 reserved_at_60
[0x20];
3640 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN
= 0x0,
3641 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP
= 0x1,
3644 struct mlx5_ifc_query_vport_state_out_bits
{
3646 u8 reserved_at_8
[0x18];
3650 u8 reserved_at_40
[0x20];
3652 u8 reserved_at_60
[0x18];
3653 u8 admin_state
[0x4];
3658 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
= 0x0,
3659 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT
= 0x1,
3662 struct mlx5_ifc_query_vport_state_in_bits
{
3664 u8 reserved_at_10
[0x10];
3666 u8 reserved_at_20
[0x10];
3669 u8 other_vport
[0x1];
3670 u8 reserved_at_41
[0xf];
3671 u8 vport_number
[0x10];
3673 u8 reserved_at_60
[0x20];
3676 struct mlx5_ifc_query_vport_counter_out_bits
{
3678 u8 reserved_at_8
[0x18];
3682 u8 reserved_at_40
[0x40];
3684 struct mlx5_ifc_traffic_counter_bits received_errors
;
3686 struct mlx5_ifc_traffic_counter_bits transmit_errors
;
3688 struct mlx5_ifc_traffic_counter_bits received_ib_unicast
;
3690 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast
;
3692 struct mlx5_ifc_traffic_counter_bits received_ib_multicast
;
3694 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast
;
3696 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast
;
3698 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast
;
3700 struct mlx5_ifc_traffic_counter_bits received_eth_unicast
;
3702 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast
;
3704 struct mlx5_ifc_traffic_counter_bits received_eth_multicast
;
3706 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast
;
3708 u8 reserved_at_680
[0xa00];
3712 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS
= 0x0,
3715 struct mlx5_ifc_query_vport_counter_in_bits
{
3717 u8 reserved_at_10
[0x10];
3719 u8 reserved_at_20
[0x10];
3722 u8 other_vport
[0x1];
3723 u8 reserved_at_41
[0xb];
3725 u8 vport_number
[0x10];
3727 u8 reserved_at_60
[0x60];
3730 u8 reserved_at_c1
[0x1f];
3732 u8 reserved_at_e0
[0x20];
3735 struct mlx5_ifc_query_tis_out_bits
{
3737 u8 reserved_at_8
[0x18];
3741 u8 reserved_at_40
[0x40];
3743 struct mlx5_ifc_tisc_bits tis_context
;
3746 struct mlx5_ifc_query_tis_in_bits
{
3748 u8 reserved_at_10
[0x10];
3750 u8 reserved_at_20
[0x10];
3753 u8 reserved_at_40
[0x8];
3756 u8 reserved_at_60
[0x20];
3759 struct mlx5_ifc_query_tir_out_bits
{
3761 u8 reserved_at_8
[0x18];
3765 u8 reserved_at_40
[0xc0];
3767 struct mlx5_ifc_tirc_bits tir_context
;
3770 struct mlx5_ifc_query_tir_in_bits
{
3772 u8 reserved_at_10
[0x10];
3774 u8 reserved_at_20
[0x10];
3777 u8 reserved_at_40
[0x8];
3780 u8 reserved_at_60
[0x20];
3783 struct mlx5_ifc_query_srq_out_bits
{
3785 u8 reserved_at_8
[0x18];
3789 u8 reserved_at_40
[0x40];
3791 struct mlx5_ifc_srqc_bits srq_context_entry
;
3793 u8 reserved_at_280
[0x600];
3798 struct mlx5_ifc_query_srq_in_bits
{
3800 u8 reserved_at_10
[0x10];
3802 u8 reserved_at_20
[0x10];
3805 u8 reserved_at_40
[0x8];
3808 u8 reserved_at_60
[0x20];
3811 struct mlx5_ifc_query_sq_out_bits
{
3813 u8 reserved_at_8
[0x18];
3817 u8 reserved_at_40
[0xc0];
3819 struct mlx5_ifc_sqc_bits sq_context
;
3822 struct mlx5_ifc_query_sq_in_bits
{
3824 u8 reserved_at_10
[0x10];
3826 u8 reserved_at_20
[0x10];
3829 u8 reserved_at_40
[0x8];
3832 u8 reserved_at_60
[0x20];
3835 struct mlx5_ifc_query_special_contexts_out_bits
{
3837 u8 reserved_at_8
[0x18];
3841 u8 dump_fill_mkey
[0x20];
3847 u8 reserved_at_a0
[0x60];
3850 struct mlx5_ifc_query_special_contexts_in_bits
{
3852 u8 reserved_at_10
[0x10];
3854 u8 reserved_at_20
[0x10];
3857 u8 reserved_at_40
[0x40];
3860 struct mlx5_ifc_query_scheduling_element_out_bits
{
3862 u8 reserved_at_10
[0x10];
3864 u8 reserved_at_20
[0x10];
3867 u8 reserved_at_40
[0xc0];
3869 struct mlx5_ifc_scheduling_context_bits scheduling_context
;
3871 u8 reserved_at_300
[0x100];
3875 SCHEDULING_HIERARCHY_E_SWITCH
= 0x2,
3878 struct mlx5_ifc_query_scheduling_element_in_bits
{
3880 u8 reserved_at_10
[0x10];
3882 u8 reserved_at_20
[0x10];
3885 u8 scheduling_hierarchy
[0x8];
3886 u8 reserved_at_48
[0x18];
3888 u8 scheduling_element_id
[0x20];
3890 u8 reserved_at_80
[0x180];
3893 struct mlx5_ifc_query_rqt_out_bits
{
3895 u8 reserved_at_8
[0x18];
3899 u8 reserved_at_40
[0xc0];
3901 struct mlx5_ifc_rqtc_bits rqt_context
;
3904 struct mlx5_ifc_query_rqt_in_bits
{
3906 u8 reserved_at_10
[0x10];
3908 u8 reserved_at_20
[0x10];
3911 u8 reserved_at_40
[0x8];
3914 u8 reserved_at_60
[0x20];
3917 struct mlx5_ifc_query_rq_out_bits
{
3919 u8 reserved_at_8
[0x18];
3923 u8 reserved_at_40
[0xc0];
3925 struct mlx5_ifc_rqc_bits rq_context
;
3928 struct mlx5_ifc_query_rq_in_bits
{
3930 u8 reserved_at_10
[0x10];
3932 u8 reserved_at_20
[0x10];
3935 u8 reserved_at_40
[0x8];
3938 u8 reserved_at_60
[0x20];
3941 struct mlx5_ifc_query_roce_address_out_bits
{
3943 u8 reserved_at_8
[0x18];
3947 u8 reserved_at_40
[0x40];
3949 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
3952 struct mlx5_ifc_query_roce_address_in_bits
{
3954 u8 reserved_at_10
[0x10];
3956 u8 reserved_at_20
[0x10];
3959 u8 roce_address_index
[0x10];
3960 u8 reserved_at_50
[0xc];
3961 u8 vhca_port_num
[0x4];
3963 u8 reserved_at_60
[0x20];
3966 struct mlx5_ifc_query_rmp_out_bits
{
3968 u8 reserved_at_8
[0x18];
3972 u8 reserved_at_40
[0xc0];
3974 struct mlx5_ifc_rmpc_bits rmp_context
;
3977 struct mlx5_ifc_query_rmp_in_bits
{
3979 u8 reserved_at_10
[0x10];
3981 u8 reserved_at_20
[0x10];
3984 u8 reserved_at_40
[0x8];
3987 u8 reserved_at_60
[0x20];
3990 struct mlx5_ifc_query_qp_out_bits
{
3992 u8 reserved_at_8
[0x18];
3996 u8 reserved_at_40
[0x40];
3998 u8 opt_param_mask
[0x20];
4000 u8 reserved_at_a0
[0x20];
4002 struct mlx5_ifc_qpc_bits qpc
;
4004 u8 reserved_at_800
[0x80];
4009 struct mlx5_ifc_query_qp_in_bits
{
4011 u8 reserved_at_10
[0x10];
4013 u8 reserved_at_20
[0x10];
4016 u8 reserved_at_40
[0x8];
4019 u8 reserved_at_60
[0x20];
4022 struct mlx5_ifc_query_q_counter_out_bits
{
4024 u8 reserved_at_8
[0x18];
4028 u8 reserved_at_40
[0x40];
4030 u8 rx_write_requests
[0x20];
4032 u8 reserved_at_a0
[0x20];
4034 u8 rx_read_requests
[0x20];
4036 u8 reserved_at_e0
[0x20];
4038 u8 rx_atomic_requests
[0x20];
4040 u8 reserved_at_120
[0x20];
4042 u8 rx_dct_connect
[0x20];
4044 u8 reserved_at_160
[0x20];
4046 u8 out_of_buffer
[0x20];
4048 u8 reserved_at_1a0
[0x20];
4050 u8 out_of_sequence
[0x20];
4052 u8 reserved_at_1e0
[0x20];
4054 u8 duplicate_request
[0x20];
4056 u8 reserved_at_220
[0x20];
4058 u8 rnr_nak_retry_err
[0x20];
4060 u8 reserved_at_260
[0x20];
4062 u8 packet_seq_err
[0x20];
4064 u8 reserved_at_2a0
[0x20];
4066 u8 implied_nak_seq_err
[0x20];
4068 u8 reserved_at_2e0
[0x20];
4070 u8 local_ack_timeout_err
[0x20];
4072 u8 reserved_at_320
[0xa0];
4074 u8 resp_local_length_error
[0x20];
4076 u8 req_local_length_error
[0x20];
4078 u8 resp_local_qp_error
[0x20];
4080 u8 local_operation_error
[0x20];
4082 u8 resp_local_protection
[0x20];
4084 u8 req_local_protection
[0x20];
4086 u8 resp_cqe_error
[0x20];
4088 u8 req_cqe_error
[0x20];
4090 u8 req_mw_binding
[0x20];
4092 u8 req_bad_response
[0x20];
4094 u8 req_remote_invalid_request
[0x20];
4096 u8 resp_remote_invalid_request
[0x20];
4098 u8 req_remote_access_errors
[0x20];
4100 u8 resp_remote_access_errors
[0x20];
4102 u8 req_remote_operation_errors
[0x20];
4104 u8 req_transport_retries_exceeded
[0x20];
4106 u8 cq_overflow
[0x20];
4108 u8 resp_cqe_flush_error
[0x20];
4110 u8 req_cqe_flush_error
[0x20];
4112 u8 reserved_at_620
[0x1e0];
4115 struct mlx5_ifc_query_q_counter_in_bits
{
4117 u8 reserved_at_10
[0x10];
4119 u8 reserved_at_20
[0x10];
4122 u8 reserved_at_40
[0x80];
4125 u8 reserved_at_c1
[0x1f];
4127 u8 reserved_at_e0
[0x18];
4128 u8 counter_set_id
[0x8];
4131 struct mlx5_ifc_query_pages_out_bits
{
4133 u8 reserved_at_8
[0x18];
4137 u8 reserved_at_40
[0x10];
4138 u8 function_id
[0x10];
4144 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES
= 0x1,
4145 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES
= 0x2,
4146 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES
= 0x3,
4149 struct mlx5_ifc_query_pages_in_bits
{
4151 u8 reserved_at_10
[0x10];
4153 u8 reserved_at_20
[0x10];
4156 u8 reserved_at_40
[0x10];
4157 u8 function_id
[0x10];
4159 u8 reserved_at_60
[0x20];
4162 struct mlx5_ifc_query_nic_vport_context_out_bits
{
4164 u8 reserved_at_8
[0x18];
4168 u8 reserved_at_40
[0x40];
4170 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
4173 struct mlx5_ifc_query_nic_vport_context_in_bits
{
4175 u8 reserved_at_10
[0x10];
4177 u8 reserved_at_20
[0x10];
4180 u8 other_vport
[0x1];
4181 u8 reserved_at_41
[0xf];
4182 u8 vport_number
[0x10];
4184 u8 reserved_at_60
[0x5];
4185 u8 allowed_list_type
[0x3];
4186 u8 reserved_at_68
[0x18];
4189 struct mlx5_ifc_query_mkey_out_bits
{
4191 u8 reserved_at_8
[0x18];
4195 u8 reserved_at_40
[0x40];
4197 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
4199 u8 reserved_at_280
[0x600];
4201 u8 bsf0_klm0_pas_mtt0_1
[16][0x8];
4203 u8 bsf1_klm1_pas_mtt2_3
[16][0x8];
4206 struct mlx5_ifc_query_mkey_in_bits
{
4208 u8 reserved_at_10
[0x10];
4210 u8 reserved_at_20
[0x10];
4213 u8 reserved_at_40
[0x8];
4214 u8 mkey_index
[0x18];
4217 u8 reserved_at_61
[0x1f];
4220 struct mlx5_ifc_query_mad_demux_out_bits
{
4222 u8 reserved_at_8
[0x18];
4226 u8 reserved_at_40
[0x40];
4228 u8 mad_dumux_parameters_block
[0x20];
4231 struct mlx5_ifc_query_mad_demux_in_bits
{
4233 u8 reserved_at_10
[0x10];
4235 u8 reserved_at_20
[0x10];
4238 u8 reserved_at_40
[0x40];
4241 struct mlx5_ifc_query_l2_table_entry_out_bits
{
4243 u8 reserved_at_8
[0x18];
4247 u8 reserved_at_40
[0xa0];
4249 u8 reserved_at_e0
[0x13];
4253 struct mlx5_ifc_mac_address_layout_bits mac_address
;
4255 u8 reserved_at_140
[0xc0];
4258 struct mlx5_ifc_query_l2_table_entry_in_bits
{
4260 u8 reserved_at_10
[0x10];
4262 u8 reserved_at_20
[0x10];
4265 u8 reserved_at_40
[0x60];
4267 u8 reserved_at_a0
[0x8];
4268 u8 table_index
[0x18];
4270 u8 reserved_at_c0
[0x140];
4273 struct mlx5_ifc_query_issi_out_bits
{
4275 u8 reserved_at_8
[0x18];
4279 u8 reserved_at_40
[0x10];
4280 u8 current_issi
[0x10];
4282 u8 reserved_at_60
[0xa0];
4284 u8 reserved_at_100
[76][0x8];
4285 u8 supported_issi_dw0
[0x20];
4288 struct mlx5_ifc_query_issi_in_bits
{
4290 u8 reserved_at_10
[0x10];
4292 u8 reserved_at_20
[0x10];
4295 u8 reserved_at_40
[0x40];
4298 struct mlx5_ifc_set_driver_version_out_bits
{
4300 u8 reserved_0
[0x18];
4303 u8 reserved_1
[0x40];
4306 struct mlx5_ifc_set_driver_version_in_bits
{
4308 u8 reserved_0
[0x10];
4310 u8 reserved_1
[0x10];
4313 u8 reserved_2
[0x40];
4314 u8 driver_version
[64][0x8];
4317 struct mlx5_ifc_query_hca_vport_pkey_out_bits
{
4319 u8 reserved_at_8
[0x18];
4323 u8 reserved_at_40
[0x40];
4325 struct mlx5_ifc_pkey_bits pkey
[0];
4328 struct mlx5_ifc_query_hca_vport_pkey_in_bits
{
4330 u8 reserved_at_10
[0x10];
4332 u8 reserved_at_20
[0x10];
4335 u8 other_vport
[0x1];
4336 u8 reserved_at_41
[0xb];
4338 u8 vport_number
[0x10];
4340 u8 reserved_at_60
[0x10];
4341 u8 pkey_index
[0x10];
4345 MLX5_HCA_VPORT_SEL_PORT_GUID
= 1 << 0,
4346 MLX5_HCA_VPORT_SEL_NODE_GUID
= 1 << 1,
4347 MLX5_HCA_VPORT_SEL_STATE_POLICY
= 1 << 2,
4350 struct mlx5_ifc_query_hca_vport_gid_out_bits
{
4352 u8 reserved_at_8
[0x18];
4356 u8 reserved_at_40
[0x20];
4359 u8 reserved_at_70
[0x10];
4361 struct mlx5_ifc_array128_auto_bits gid
[0];
4364 struct mlx5_ifc_query_hca_vport_gid_in_bits
{
4366 u8 reserved_at_10
[0x10];
4368 u8 reserved_at_20
[0x10];
4371 u8 other_vport
[0x1];
4372 u8 reserved_at_41
[0xb];
4374 u8 vport_number
[0x10];
4376 u8 reserved_at_60
[0x10];
4380 struct mlx5_ifc_query_hca_vport_context_out_bits
{
4382 u8 reserved_at_8
[0x18];
4386 u8 reserved_at_40
[0x40];
4388 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
4391 struct mlx5_ifc_query_hca_vport_context_in_bits
{
4393 u8 reserved_at_10
[0x10];
4395 u8 reserved_at_20
[0x10];
4398 u8 other_vport
[0x1];
4399 u8 reserved_at_41
[0xb];
4401 u8 vport_number
[0x10];
4403 u8 reserved_at_60
[0x20];
4406 struct mlx5_ifc_query_hca_cap_out_bits
{
4408 u8 reserved_at_8
[0x18];
4412 u8 reserved_at_40
[0x40];
4414 union mlx5_ifc_hca_cap_union_bits capability
;
4417 struct mlx5_ifc_query_hca_cap_in_bits
{
4419 u8 reserved_at_10
[0x10];
4421 u8 reserved_at_20
[0x10];
4424 u8 reserved_at_40
[0x40];
4427 struct mlx5_ifc_query_flow_table_out_bits
{
4429 u8 reserved_at_8
[0x18];
4433 u8 reserved_at_40
[0x80];
4435 u8 reserved_at_c0
[0x8];
4437 u8 reserved_at_d0
[0x8];
4440 u8 reserved_at_e0
[0x120];
4443 struct mlx5_ifc_query_flow_table_in_bits
{
4445 u8 reserved_at_10
[0x10];
4447 u8 reserved_at_20
[0x10];
4450 u8 reserved_at_40
[0x40];
4453 u8 reserved_at_88
[0x18];
4455 u8 reserved_at_a0
[0x8];
4458 u8 reserved_at_c0
[0x140];
4461 struct mlx5_ifc_query_fte_out_bits
{
4463 u8 reserved_at_8
[0x18];
4467 u8 reserved_at_40
[0x1c0];
4469 struct mlx5_ifc_flow_context_bits flow_context
;
4472 struct mlx5_ifc_query_fte_in_bits
{
4474 u8 reserved_at_10
[0x10];
4476 u8 reserved_at_20
[0x10];
4479 u8 reserved_at_40
[0x40];
4482 u8 reserved_at_88
[0x18];
4484 u8 reserved_at_a0
[0x8];
4487 u8 reserved_at_c0
[0x40];
4489 u8 flow_index
[0x20];
4491 u8 reserved_at_120
[0xe0];
4495 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
4496 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
4497 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
4500 struct mlx5_ifc_query_flow_group_out_bits
{
4502 u8 reserved_at_8
[0x18];
4506 u8 reserved_at_40
[0xa0];
4508 u8 start_flow_index
[0x20];
4510 u8 reserved_at_100
[0x20];
4512 u8 end_flow_index
[0x20];
4514 u8 reserved_at_140
[0xa0];
4516 u8 reserved_at_1e0
[0x18];
4517 u8 match_criteria_enable
[0x8];
4519 struct mlx5_ifc_fte_match_param_bits match_criteria
;
4521 u8 reserved_at_1200
[0xe00];
4524 struct mlx5_ifc_query_flow_group_in_bits
{
4526 u8 reserved_at_10
[0x10];
4528 u8 reserved_at_20
[0x10];
4531 u8 reserved_at_40
[0x40];
4534 u8 reserved_at_88
[0x18];
4536 u8 reserved_at_a0
[0x8];
4541 u8 reserved_at_e0
[0x120];
4544 struct mlx5_ifc_query_flow_counter_out_bits
{
4546 u8 reserved_at_8
[0x18];
4550 u8 reserved_at_40
[0x40];
4552 struct mlx5_ifc_traffic_counter_bits flow_statistics
[0];
4555 struct mlx5_ifc_query_flow_counter_in_bits
{
4557 u8 reserved_at_10
[0x10];
4559 u8 reserved_at_20
[0x10];
4562 u8 reserved_at_40
[0x80];
4565 u8 reserved_at_c1
[0xf];
4566 u8 num_of_counters
[0x10];
4568 u8 flow_counter_id
[0x20];
4571 struct mlx5_ifc_query_esw_vport_context_out_bits
{
4573 u8 reserved_at_8
[0x18];
4577 u8 reserved_at_40
[0x40];
4579 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
4582 struct mlx5_ifc_query_esw_vport_context_in_bits
{
4584 u8 reserved_at_10
[0x10];
4586 u8 reserved_at_20
[0x10];
4589 u8 other_vport
[0x1];
4590 u8 reserved_at_41
[0xf];
4591 u8 vport_number
[0x10];
4593 u8 reserved_at_60
[0x20];
4596 struct mlx5_ifc_modify_esw_vport_context_out_bits
{
4598 u8 reserved_at_8
[0x18];
4602 u8 reserved_at_40
[0x40];
4605 struct mlx5_ifc_esw_vport_context_fields_select_bits
{
4606 u8 reserved_at_0
[0x1c];
4607 u8 vport_cvlan_insert
[0x1];
4608 u8 vport_svlan_insert
[0x1];
4609 u8 vport_cvlan_strip
[0x1];
4610 u8 vport_svlan_strip
[0x1];
4613 struct mlx5_ifc_modify_esw_vport_context_in_bits
{
4615 u8 reserved_at_10
[0x10];
4617 u8 reserved_at_20
[0x10];
4620 u8 other_vport
[0x1];
4621 u8 reserved_at_41
[0xf];
4622 u8 vport_number
[0x10];
4624 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select
;
4626 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
4629 struct mlx5_ifc_query_eq_out_bits
{
4631 u8 reserved_at_8
[0x18];
4635 u8 reserved_at_40
[0x40];
4637 struct mlx5_ifc_eqc_bits eq_context_entry
;
4639 u8 reserved_at_280
[0x40];
4641 u8 event_bitmask
[0x40];
4643 u8 reserved_at_300
[0x580];
4648 struct mlx5_ifc_query_eq_in_bits
{
4650 u8 reserved_at_10
[0x10];
4652 u8 reserved_at_20
[0x10];
4655 u8 reserved_at_40
[0x18];
4658 u8 reserved_at_60
[0x20];
4661 struct mlx5_ifc_encap_header_in_bits
{
4662 u8 reserved_at_0
[0x5];
4663 u8 header_type
[0x3];
4664 u8 reserved_at_8
[0xe];
4665 u8 encap_header_size
[0xa];
4667 u8 reserved_at_20
[0x10];
4668 u8 encap_header
[2][0x8];
4670 u8 more_encap_header
[0][0x8];
4673 struct mlx5_ifc_query_encap_header_out_bits
{
4675 u8 reserved_at_8
[0x18];
4679 u8 reserved_at_40
[0xa0];
4681 struct mlx5_ifc_encap_header_in_bits encap_header
[0];
4684 struct mlx5_ifc_query_encap_header_in_bits
{
4686 u8 reserved_at_10
[0x10];
4688 u8 reserved_at_20
[0x10];
4693 u8 reserved_at_60
[0xa0];
4696 struct mlx5_ifc_alloc_encap_header_out_bits
{
4698 u8 reserved_at_8
[0x18];
4704 u8 reserved_at_60
[0x20];
4707 struct mlx5_ifc_alloc_encap_header_in_bits
{
4709 u8 reserved_at_10
[0x10];
4711 u8 reserved_at_20
[0x10];
4714 u8 reserved_at_40
[0xa0];
4716 struct mlx5_ifc_encap_header_in_bits encap_header
;
4719 struct mlx5_ifc_dealloc_encap_header_out_bits
{
4721 u8 reserved_at_8
[0x18];
4725 u8 reserved_at_40
[0x40];
4728 struct mlx5_ifc_dealloc_encap_header_in_bits
{
4730 u8 reserved_at_10
[0x10];
4732 u8 reserved_20
[0x10];
4737 u8 reserved_60
[0x20];
4740 struct mlx5_ifc_set_action_in_bits
{
4741 u8 action_type
[0x4];
4743 u8 reserved_at_10
[0x3];
4745 u8 reserved_at_18
[0x3];
4751 struct mlx5_ifc_add_action_in_bits
{
4752 u8 action_type
[0x4];
4754 u8 reserved_at_10
[0x10];
4759 union mlx5_ifc_set_action_in_add_action_in_auto_bits
{
4760 struct mlx5_ifc_set_action_in_bits set_action_in
;
4761 struct mlx5_ifc_add_action_in_bits add_action_in
;
4762 u8 reserved_at_0
[0x40];
4766 MLX5_ACTION_TYPE_SET
= 0x1,
4767 MLX5_ACTION_TYPE_ADD
= 0x2,
4771 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16
= 0x1,
4772 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0
= 0x2,
4773 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE
= 0x3,
4774 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16
= 0x4,
4775 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0
= 0x5,
4776 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP
= 0x6,
4777 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS
= 0x7,
4778 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT
= 0x8,
4779 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT
= 0x9,
4780 MLX5_ACTION_IN_FIELD_OUT_IP_TTL
= 0xa,
4781 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT
= 0xb,
4782 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT
= 0xc,
4783 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96
= 0xd,
4784 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64
= 0xe,
4785 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32
= 0xf,
4786 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0
= 0x10,
4787 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96
= 0x11,
4788 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64
= 0x12,
4789 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32
= 0x13,
4790 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0
= 0x14,
4791 MLX5_ACTION_IN_FIELD_OUT_SIPV4
= 0x15,
4792 MLX5_ACTION_IN_FIELD_OUT_DIPV4
= 0x16,
4793 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT
= 0x47,
4796 struct mlx5_ifc_alloc_modify_header_context_out_bits
{
4798 u8 reserved_at_8
[0x18];
4802 u8 modify_header_id
[0x20];
4804 u8 reserved_at_60
[0x20];
4807 struct mlx5_ifc_alloc_modify_header_context_in_bits
{
4809 u8 reserved_at_10
[0x10];
4811 u8 reserved_at_20
[0x10];
4814 u8 reserved_at_40
[0x20];
4817 u8 reserved_at_68
[0x10];
4818 u8 num_of_actions
[0x8];
4820 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions
[0];
4823 struct mlx5_ifc_dealloc_modify_header_context_out_bits
{
4825 u8 reserved_at_8
[0x18];
4829 u8 reserved_at_40
[0x40];
4832 struct mlx5_ifc_dealloc_modify_header_context_in_bits
{
4834 u8 reserved_at_10
[0x10];
4836 u8 reserved_at_20
[0x10];
4839 u8 modify_header_id
[0x20];
4841 u8 reserved_at_60
[0x20];
4844 struct mlx5_ifc_query_dct_out_bits
{
4846 u8 reserved_at_8
[0x18];
4850 u8 reserved_at_40
[0x40];
4852 struct mlx5_ifc_dctc_bits dct_context_entry
;
4854 u8 reserved_at_280
[0x180];
4857 struct mlx5_ifc_query_dct_in_bits
{
4859 u8 reserved_at_10
[0x10];
4861 u8 reserved_at_20
[0x10];
4864 u8 reserved_at_40
[0x8];
4867 u8 reserved_at_60
[0x20];
4870 struct mlx5_ifc_query_cq_out_bits
{
4872 u8 reserved_at_8
[0x18];
4876 u8 reserved_at_40
[0x40];
4878 struct mlx5_ifc_cqc_bits cq_context
;
4880 u8 reserved_at_280
[0x600];
4885 struct mlx5_ifc_query_cq_in_bits
{
4887 u8 reserved_at_10
[0x10];
4889 u8 reserved_at_20
[0x10];
4892 u8 reserved_at_40
[0x8];
4895 u8 reserved_at_60
[0x20];
4898 struct mlx5_ifc_query_cong_status_out_bits
{
4900 u8 reserved_at_8
[0x18];
4904 u8 reserved_at_40
[0x20];
4908 u8 reserved_at_62
[0x1e];
4911 struct mlx5_ifc_query_cong_status_in_bits
{
4913 u8 reserved_at_10
[0x10];
4915 u8 reserved_at_20
[0x10];
4918 u8 reserved_at_40
[0x18];
4920 u8 cong_protocol
[0x4];
4922 u8 reserved_at_60
[0x20];
4925 struct mlx5_ifc_query_cong_statistics_out_bits
{
4927 u8 reserved_at_8
[0x18];
4931 u8 reserved_at_40
[0x40];
4933 u8 rp_cur_flows
[0x20];
4937 u8 rp_cnp_ignored_high
[0x20];
4939 u8 rp_cnp_ignored_low
[0x20];
4941 u8 rp_cnp_handled_high
[0x20];
4943 u8 rp_cnp_handled_low
[0x20];
4945 u8 reserved_at_140
[0x100];
4947 u8 time_stamp_high
[0x20];
4949 u8 time_stamp_low
[0x20];
4951 u8 accumulators_period
[0x20];
4953 u8 np_ecn_marked_roce_packets_high
[0x20];
4955 u8 np_ecn_marked_roce_packets_low
[0x20];
4957 u8 np_cnp_sent_high
[0x20];
4959 u8 np_cnp_sent_low
[0x20];
4961 u8 reserved_at_320
[0x560];
4964 struct mlx5_ifc_query_cong_statistics_in_bits
{
4966 u8 reserved_at_10
[0x10];
4968 u8 reserved_at_20
[0x10];
4972 u8 reserved_at_41
[0x1f];
4974 u8 reserved_at_60
[0x20];
4977 struct mlx5_ifc_query_cong_params_out_bits
{
4979 u8 reserved_at_8
[0x18];
4983 u8 reserved_at_40
[0x40];
4985 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
4988 struct mlx5_ifc_query_cong_params_in_bits
{
4990 u8 reserved_at_10
[0x10];
4992 u8 reserved_at_20
[0x10];
4995 u8 reserved_at_40
[0x1c];
4996 u8 cong_protocol
[0x4];
4998 u8 reserved_at_60
[0x20];
5001 struct mlx5_ifc_query_adapter_out_bits
{
5003 u8 reserved_at_8
[0x18];
5007 u8 reserved_at_40
[0x40];
5009 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct
;
5012 struct mlx5_ifc_query_adapter_in_bits
{
5014 u8 reserved_at_10
[0x10];
5016 u8 reserved_at_20
[0x10];
5019 u8 reserved_at_40
[0x40];
5022 struct mlx5_ifc_qp_2rst_out_bits
{
5024 u8 reserved_at_8
[0x18];
5028 u8 reserved_at_40
[0x40];
5031 struct mlx5_ifc_qp_2rst_in_bits
{
5033 u8 reserved_at_10
[0x10];
5035 u8 reserved_at_20
[0x10];
5038 u8 reserved_at_40
[0x8];
5041 u8 reserved_at_60
[0x20];
5044 struct mlx5_ifc_qp_2err_out_bits
{
5046 u8 reserved_at_8
[0x18];
5050 u8 reserved_at_40
[0x40];
5053 struct mlx5_ifc_qp_2err_in_bits
{
5055 u8 reserved_at_10
[0x10];
5057 u8 reserved_at_20
[0x10];
5060 u8 reserved_at_40
[0x8];
5063 u8 reserved_at_60
[0x20];
5066 struct mlx5_ifc_page_fault_resume_out_bits
{
5068 u8 reserved_at_8
[0x18];
5072 u8 reserved_at_40
[0x40];
5075 struct mlx5_ifc_page_fault_resume_in_bits
{
5077 u8 reserved_at_10
[0x10];
5079 u8 reserved_at_20
[0x10];
5083 u8 reserved_at_41
[0x4];
5084 u8 page_fault_type
[0x3];
5087 u8 reserved_at_60
[0x8];
5091 struct mlx5_ifc_nop_out_bits
{
5093 u8 reserved_at_8
[0x18];
5097 u8 reserved_at_40
[0x40];
5100 struct mlx5_ifc_nop_in_bits
{
5102 u8 reserved_at_10
[0x10];
5104 u8 reserved_at_20
[0x10];
5107 u8 reserved_at_40
[0x40];
5110 struct mlx5_ifc_modify_vport_state_out_bits
{
5112 u8 reserved_at_8
[0x18];
5116 u8 reserved_at_40
[0x40];
5119 struct mlx5_ifc_modify_vport_state_in_bits
{
5121 u8 reserved_at_10
[0x10];
5123 u8 reserved_at_20
[0x10];
5126 u8 other_vport
[0x1];
5127 u8 reserved_at_41
[0xf];
5128 u8 vport_number
[0x10];
5130 u8 reserved_at_60
[0x18];
5131 u8 admin_state
[0x4];
5132 u8 reserved_at_7c
[0x4];
5135 struct mlx5_ifc_modify_tis_out_bits
{
5137 u8 reserved_at_8
[0x18];
5141 u8 reserved_at_40
[0x40];
5144 struct mlx5_ifc_modify_tis_bitmask_bits
{
5145 u8 reserved_at_0
[0x20];
5147 u8 reserved_at_20
[0x1d];
5148 u8 lag_tx_port_affinity
[0x1];
5149 u8 strict_lag_tx_port_affinity
[0x1];
5153 struct mlx5_ifc_modify_tis_in_bits
{
5155 u8 reserved_at_10
[0x10];
5157 u8 reserved_at_20
[0x10];
5160 u8 reserved_at_40
[0x8];
5163 u8 reserved_at_60
[0x20];
5165 struct mlx5_ifc_modify_tis_bitmask_bits bitmask
;
5167 u8 reserved_at_c0
[0x40];
5169 struct mlx5_ifc_tisc_bits ctx
;
5172 struct mlx5_ifc_modify_tir_bitmask_bits
{
5173 u8 reserved_at_0
[0x20];
5175 u8 reserved_at_20
[0x1b];
5177 u8 reserved_at_3c
[0x1];
5179 u8 reserved_at_3e
[0x1];
5183 struct mlx5_ifc_modify_tir_out_bits
{
5185 u8 reserved_at_8
[0x18];
5189 u8 reserved_at_40
[0x40];
5192 struct mlx5_ifc_modify_tir_in_bits
{
5194 u8 reserved_at_10
[0x10];
5196 u8 reserved_at_20
[0x10];
5199 u8 reserved_at_40
[0x8];
5202 u8 reserved_at_60
[0x20];
5204 struct mlx5_ifc_modify_tir_bitmask_bits bitmask
;
5206 u8 reserved_at_c0
[0x40];
5208 struct mlx5_ifc_tirc_bits ctx
;
5211 struct mlx5_ifc_modify_sq_out_bits
{
5213 u8 reserved_at_8
[0x18];
5217 u8 reserved_at_40
[0x40];
5220 struct mlx5_ifc_modify_sq_in_bits
{
5222 u8 reserved_at_10
[0x10];
5224 u8 reserved_at_20
[0x10];
5228 u8 reserved_at_44
[0x4];
5231 u8 reserved_at_60
[0x20];
5233 u8 modify_bitmask
[0x40];
5235 u8 reserved_at_c0
[0x40];
5237 struct mlx5_ifc_sqc_bits ctx
;
5240 struct mlx5_ifc_modify_scheduling_element_out_bits
{
5242 u8 reserved_at_8
[0x18];
5246 u8 reserved_at_40
[0x1c0];
5250 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE
= 0x1,
5251 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW
= 0x2,
5254 struct mlx5_ifc_modify_scheduling_element_in_bits
{
5256 u8 reserved_at_10
[0x10];
5258 u8 reserved_at_20
[0x10];
5261 u8 scheduling_hierarchy
[0x8];
5262 u8 reserved_at_48
[0x18];
5264 u8 scheduling_element_id
[0x20];
5266 u8 reserved_at_80
[0x20];
5268 u8 modify_bitmask
[0x20];
5270 u8 reserved_at_c0
[0x40];
5272 struct mlx5_ifc_scheduling_context_bits scheduling_context
;
5274 u8 reserved_at_300
[0x100];
5277 struct mlx5_ifc_modify_rqt_out_bits
{
5279 u8 reserved_at_8
[0x18];
5283 u8 reserved_at_40
[0x40];
5286 struct mlx5_ifc_rqt_bitmask_bits
{
5287 u8 reserved_at_0
[0x20];
5289 u8 reserved_at_20
[0x1f];
5293 struct mlx5_ifc_modify_rqt_in_bits
{
5295 u8 reserved_at_10
[0x10];
5297 u8 reserved_at_20
[0x10];
5300 u8 reserved_at_40
[0x8];
5303 u8 reserved_at_60
[0x20];
5305 struct mlx5_ifc_rqt_bitmask_bits bitmask
;
5307 u8 reserved_at_c0
[0x40];
5309 struct mlx5_ifc_rqtc_bits ctx
;
5312 struct mlx5_ifc_modify_rq_out_bits
{
5314 u8 reserved_at_8
[0x18];
5318 u8 reserved_at_40
[0x40];
5322 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD
= 1ULL << 1,
5323 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS
= 1ULL << 2,
5324 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID
= 1ULL << 3,
5327 struct mlx5_ifc_modify_rq_in_bits
{
5329 u8 reserved_at_10
[0x10];
5331 u8 reserved_at_20
[0x10];
5335 u8 reserved_at_44
[0x4];
5338 u8 reserved_at_60
[0x20];
5340 u8 modify_bitmask
[0x40];
5342 u8 reserved_at_c0
[0x40];
5344 struct mlx5_ifc_rqc_bits ctx
;
5347 struct mlx5_ifc_modify_rmp_out_bits
{
5349 u8 reserved_at_8
[0x18];
5353 u8 reserved_at_40
[0x40];
5356 struct mlx5_ifc_rmp_bitmask_bits
{
5357 u8 reserved_at_0
[0x20];
5359 u8 reserved_at_20
[0x1f];
5363 struct mlx5_ifc_modify_rmp_in_bits
{
5365 u8 reserved_at_10
[0x10];
5367 u8 reserved_at_20
[0x10];
5371 u8 reserved_at_44
[0x4];
5374 u8 reserved_at_60
[0x20];
5376 struct mlx5_ifc_rmp_bitmask_bits bitmask
;
5378 u8 reserved_at_c0
[0x40];
5380 struct mlx5_ifc_rmpc_bits ctx
;
5383 struct mlx5_ifc_modify_nic_vport_context_out_bits
{
5385 u8 reserved_at_8
[0x18];
5389 u8 reserved_at_40
[0x40];
5392 struct mlx5_ifc_modify_nic_vport_field_select_bits
{
5393 u8 reserved_at_0
[0x12];
5394 u8 affiliation
[0x1];
5395 u8 reserved_at_e
[0x1];
5396 u8 disable_uc_local_lb
[0x1];
5397 u8 disable_mc_local_lb
[0x1];
5402 u8 change_event
[0x1];
5404 u8 permanent_address
[0x1];
5405 u8 addresses_list
[0x1];
5407 u8 reserved_at_1f
[0x1];
5410 struct mlx5_ifc_modify_nic_vport_context_in_bits
{
5412 u8 reserved_at_10
[0x10];
5414 u8 reserved_at_20
[0x10];
5417 u8 other_vport
[0x1];
5418 u8 reserved_at_41
[0xf];
5419 u8 vport_number
[0x10];
5421 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select
;
5423 u8 reserved_at_80
[0x780];
5425 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
5428 struct mlx5_ifc_modify_hca_vport_context_out_bits
{
5430 u8 reserved_at_8
[0x18];
5434 u8 reserved_at_40
[0x40];
5437 struct mlx5_ifc_modify_hca_vport_context_in_bits
{
5439 u8 reserved_at_10
[0x10];
5441 u8 reserved_at_20
[0x10];
5444 u8 other_vport
[0x1];
5445 u8 reserved_at_41
[0xb];
5447 u8 vport_number
[0x10];
5449 u8 reserved_at_60
[0x20];
5451 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
5454 struct mlx5_ifc_modify_cq_out_bits
{
5456 u8 reserved_at_8
[0x18];
5460 u8 reserved_at_40
[0x40];
5464 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ
= 0x0,
5465 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ
= 0x1,
5468 struct mlx5_ifc_modify_cq_in_bits
{
5470 u8 reserved_at_10
[0x10];
5472 u8 reserved_at_20
[0x10];
5475 u8 reserved_at_40
[0x8];
5478 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select
;
5480 struct mlx5_ifc_cqc_bits cq_context
;
5482 u8 reserved_at_280
[0x600];
5487 struct mlx5_ifc_modify_cong_status_out_bits
{
5489 u8 reserved_at_8
[0x18];
5493 u8 reserved_at_40
[0x40];
5496 struct mlx5_ifc_modify_cong_status_in_bits
{
5498 u8 reserved_at_10
[0x10];
5500 u8 reserved_at_20
[0x10];
5503 u8 reserved_at_40
[0x18];
5505 u8 cong_protocol
[0x4];
5509 u8 reserved_at_62
[0x1e];
5512 struct mlx5_ifc_modify_cong_params_out_bits
{
5514 u8 reserved_at_8
[0x18];
5518 u8 reserved_at_40
[0x40];
5521 struct mlx5_ifc_modify_cong_params_in_bits
{
5523 u8 reserved_at_10
[0x10];
5525 u8 reserved_at_20
[0x10];
5528 u8 reserved_at_40
[0x1c];
5529 u8 cong_protocol
[0x4];
5531 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select
;
5533 u8 reserved_at_80
[0x80];
5535 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
5538 struct mlx5_ifc_manage_pages_out_bits
{
5540 u8 reserved_at_8
[0x18];
5544 u8 output_num_entries
[0x20];
5546 u8 reserved_at_60
[0x20];
5552 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL
= 0x0,
5553 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS
= 0x1,
5554 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES
= 0x2,
5557 struct mlx5_ifc_manage_pages_in_bits
{
5559 u8 reserved_at_10
[0x10];
5561 u8 reserved_at_20
[0x10];
5564 u8 reserved_at_40
[0x10];
5565 u8 function_id
[0x10];
5567 u8 input_num_entries
[0x20];
5572 struct mlx5_ifc_mad_ifc_out_bits
{
5574 u8 reserved_at_8
[0x18];
5578 u8 reserved_at_40
[0x40];
5580 u8 response_mad_packet
[256][0x8];
5583 struct mlx5_ifc_mad_ifc_in_bits
{
5585 u8 reserved_at_10
[0x10];
5587 u8 reserved_at_20
[0x10];
5590 u8 remote_lid
[0x10];
5591 u8 reserved_at_50
[0x8];
5594 u8 reserved_at_60
[0x20];
5599 struct mlx5_ifc_init_hca_out_bits
{
5601 u8 reserved_at_8
[0x18];
5605 u8 reserved_at_40
[0x40];
5608 struct mlx5_ifc_init_hca_in_bits
{
5610 u8 reserved_at_10
[0x10];
5612 u8 reserved_at_20
[0x10];
5615 u8 reserved_at_40
[0x40];
5616 u8 sw_owner_id
[4][0x20];
5619 struct mlx5_ifc_init2rtr_qp_out_bits
{
5621 u8 reserved_at_8
[0x18];
5625 u8 reserved_at_40
[0x40];
5628 struct mlx5_ifc_init2rtr_qp_in_bits
{
5630 u8 reserved_at_10
[0x10];
5632 u8 reserved_at_20
[0x10];
5635 u8 reserved_at_40
[0x8];
5638 u8 reserved_at_60
[0x20];
5640 u8 opt_param_mask
[0x20];
5642 u8 reserved_at_a0
[0x20];
5644 struct mlx5_ifc_qpc_bits qpc
;
5646 u8 reserved_at_800
[0x80];
5649 struct mlx5_ifc_init2init_qp_out_bits
{
5651 u8 reserved_at_8
[0x18];
5655 u8 reserved_at_40
[0x40];
5658 struct mlx5_ifc_init2init_qp_in_bits
{
5660 u8 reserved_at_10
[0x10];
5662 u8 reserved_at_20
[0x10];
5665 u8 reserved_at_40
[0x8];
5668 u8 reserved_at_60
[0x20];
5670 u8 opt_param_mask
[0x20];
5672 u8 reserved_at_a0
[0x20];
5674 struct mlx5_ifc_qpc_bits qpc
;
5676 u8 reserved_at_800
[0x80];
5679 struct mlx5_ifc_get_dropped_packet_log_out_bits
{
5681 u8 reserved_at_8
[0x18];
5685 u8 reserved_at_40
[0x40];
5687 u8 packet_headers_log
[128][0x8];
5689 u8 packet_syndrome
[64][0x8];
5692 struct mlx5_ifc_get_dropped_packet_log_in_bits
{
5694 u8 reserved_at_10
[0x10];
5696 u8 reserved_at_20
[0x10];
5699 u8 reserved_at_40
[0x40];
5702 struct mlx5_ifc_gen_eqe_in_bits
{
5704 u8 reserved_at_10
[0x10];
5706 u8 reserved_at_20
[0x10];
5709 u8 reserved_at_40
[0x18];
5712 u8 reserved_at_60
[0x20];
5717 struct mlx5_ifc_gen_eq_out_bits
{
5719 u8 reserved_at_8
[0x18];
5723 u8 reserved_at_40
[0x40];
5726 struct mlx5_ifc_enable_hca_out_bits
{
5728 u8 reserved_at_8
[0x18];
5732 u8 reserved_at_40
[0x20];
5735 struct mlx5_ifc_enable_hca_in_bits
{
5737 u8 reserved_at_10
[0x10];
5739 u8 reserved_at_20
[0x10];
5742 u8 reserved_at_40
[0x10];
5743 u8 function_id
[0x10];
5745 u8 reserved_at_60
[0x20];
5748 struct mlx5_ifc_drain_dct_out_bits
{
5750 u8 reserved_at_8
[0x18];
5754 u8 reserved_at_40
[0x40];
5757 struct mlx5_ifc_drain_dct_in_bits
{
5759 u8 reserved_at_10
[0x10];
5761 u8 reserved_at_20
[0x10];
5764 u8 reserved_at_40
[0x8];
5767 u8 reserved_at_60
[0x20];
5770 struct mlx5_ifc_disable_hca_out_bits
{
5772 u8 reserved_at_8
[0x18];
5776 u8 reserved_at_40
[0x20];
5779 struct mlx5_ifc_disable_hca_in_bits
{
5781 u8 reserved_at_10
[0x10];
5783 u8 reserved_at_20
[0x10];
5786 u8 reserved_at_40
[0x10];
5787 u8 function_id
[0x10];
5789 u8 reserved_at_60
[0x20];
5792 struct mlx5_ifc_detach_from_mcg_out_bits
{
5794 u8 reserved_at_8
[0x18];
5798 u8 reserved_at_40
[0x40];
5801 struct mlx5_ifc_detach_from_mcg_in_bits
{
5803 u8 reserved_at_10
[0x10];
5805 u8 reserved_at_20
[0x10];
5808 u8 reserved_at_40
[0x8];
5811 u8 reserved_at_60
[0x20];
5813 u8 multicast_gid
[16][0x8];
5816 struct mlx5_ifc_destroy_xrq_out_bits
{
5818 u8 reserved_at_8
[0x18];
5822 u8 reserved_at_40
[0x40];
5825 struct mlx5_ifc_destroy_xrq_in_bits
{
5827 u8 reserved_at_10
[0x10];
5829 u8 reserved_at_20
[0x10];
5832 u8 reserved_at_40
[0x8];
5835 u8 reserved_at_60
[0x20];
5838 struct mlx5_ifc_destroy_xrc_srq_out_bits
{
5840 u8 reserved_at_8
[0x18];
5844 u8 reserved_at_40
[0x40];
5847 struct mlx5_ifc_destroy_xrc_srq_in_bits
{
5849 u8 reserved_at_10
[0x10];
5851 u8 reserved_at_20
[0x10];
5854 u8 reserved_at_40
[0x8];
5857 u8 reserved_at_60
[0x20];
5860 struct mlx5_ifc_destroy_tis_out_bits
{
5862 u8 reserved_at_8
[0x18];
5866 u8 reserved_at_40
[0x40];
5869 struct mlx5_ifc_destroy_tis_in_bits
{
5871 u8 reserved_at_10
[0x10];
5873 u8 reserved_at_20
[0x10];
5876 u8 reserved_at_40
[0x8];
5879 u8 reserved_at_60
[0x20];
5882 struct mlx5_ifc_destroy_tir_out_bits
{
5884 u8 reserved_at_8
[0x18];
5888 u8 reserved_at_40
[0x40];
5891 struct mlx5_ifc_destroy_tir_in_bits
{
5893 u8 reserved_at_10
[0x10];
5895 u8 reserved_at_20
[0x10];
5898 u8 reserved_at_40
[0x8];
5901 u8 reserved_at_60
[0x20];
5904 struct mlx5_ifc_destroy_srq_out_bits
{
5906 u8 reserved_at_8
[0x18];
5910 u8 reserved_at_40
[0x40];
5913 struct mlx5_ifc_destroy_srq_in_bits
{
5915 u8 reserved_at_10
[0x10];
5917 u8 reserved_at_20
[0x10];
5920 u8 reserved_at_40
[0x8];
5923 u8 reserved_at_60
[0x20];
5926 struct mlx5_ifc_destroy_sq_out_bits
{
5928 u8 reserved_at_8
[0x18];
5932 u8 reserved_at_40
[0x40];
5935 struct mlx5_ifc_destroy_sq_in_bits
{
5937 u8 reserved_at_10
[0x10];
5939 u8 reserved_at_20
[0x10];
5942 u8 reserved_at_40
[0x8];
5945 u8 reserved_at_60
[0x20];
5948 struct mlx5_ifc_destroy_scheduling_element_out_bits
{
5950 u8 reserved_at_8
[0x18];
5954 u8 reserved_at_40
[0x1c0];
5957 struct mlx5_ifc_destroy_scheduling_element_in_bits
{
5959 u8 reserved_at_10
[0x10];
5961 u8 reserved_at_20
[0x10];
5964 u8 scheduling_hierarchy
[0x8];
5965 u8 reserved_at_48
[0x18];
5967 u8 scheduling_element_id
[0x20];
5969 u8 reserved_at_80
[0x180];
5972 struct mlx5_ifc_destroy_rqt_out_bits
{
5974 u8 reserved_at_8
[0x18];
5978 u8 reserved_at_40
[0x40];
5981 struct mlx5_ifc_destroy_rqt_in_bits
{
5983 u8 reserved_at_10
[0x10];
5985 u8 reserved_at_20
[0x10];
5988 u8 reserved_at_40
[0x8];
5991 u8 reserved_at_60
[0x20];
5994 struct mlx5_ifc_destroy_rq_out_bits
{
5996 u8 reserved_at_8
[0x18];
6000 u8 reserved_at_40
[0x40];
6003 struct mlx5_ifc_destroy_rq_in_bits
{
6005 u8 reserved_at_10
[0x10];
6007 u8 reserved_at_20
[0x10];
6010 u8 reserved_at_40
[0x8];
6013 u8 reserved_at_60
[0x20];
6016 struct mlx5_ifc_set_delay_drop_params_in_bits
{
6018 u8 reserved_at_10
[0x10];
6020 u8 reserved_at_20
[0x10];
6023 u8 reserved_at_40
[0x20];
6025 u8 reserved_at_60
[0x10];
6026 u8 delay_drop_timeout
[0x10];
6029 struct mlx5_ifc_set_delay_drop_params_out_bits
{
6031 u8 reserved_at_8
[0x18];
6035 u8 reserved_at_40
[0x40];
6038 struct mlx5_ifc_destroy_rmp_out_bits
{
6040 u8 reserved_at_8
[0x18];
6044 u8 reserved_at_40
[0x40];
6047 struct mlx5_ifc_destroy_rmp_in_bits
{
6049 u8 reserved_at_10
[0x10];
6051 u8 reserved_at_20
[0x10];
6054 u8 reserved_at_40
[0x8];
6057 u8 reserved_at_60
[0x20];
6060 struct mlx5_ifc_destroy_qp_out_bits
{
6062 u8 reserved_at_8
[0x18];
6066 u8 reserved_at_40
[0x40];
6069 struct mlx5_ifc_destroy_qp_in_bits
{
6071 u8 reserved_at_10
[0x10];
6073 u8 reserved_at_20
[0x10];
6076 u8 reserved_at_40
[0x8];
6079 u8 reserved_at_60
[0x20];
6082 struct mlx5_ifc_destroy_psv_out_bits
{
6084 u8 reserved_at_8
[0x18];
6088 u8 reserved_at_40
[0x40];
6091 struct mlx5_ifc_destroy_psv_in_bits
{
6093 u8 reserved_at_10
[0x10];
6095 u8 reserved_at_20
[0x10];
6098 u8 reserved_at_40
[0x8];
6101 u8 reserved_at_60
[0x20];
6104 struct mlx5_ifc_destroy_mkey_out_bits
{
6106 u8 reserved_at_8
[0x18];
6110 u8 reserved_at_40
[0x40];
6113 struct mlx5_ifc_destroy_mkey_in_bits
{
6115 u8 reserved_at_10
[0x10];
6117 u8 reserved_at_20
[0x10];
6120 u8 reserved_at_40
[0x8];
6121 u8 mkey_index
[0x18];
6123 u8 reserved_at_60
[0x20];
6126 struct mlx5_ifc_destroy_flow_table_out_bits
{
6128 u8 reserved_at_8
[0x18];
6132 u8 reserved_at_40
[0x40];
6135 struct mlx5_ifc_destroy_flow_table_in_bits
{
6137 u8 reserved_at_10
[0x10];
6139 u8 reserved_at_20
[0x10];
6142 u8 other_vport
[0x1];
6143 u8 reserved_at_41
[0xf];
6144 u8 vport_number
[0x10];
6146 u8 reserved_at_60
[0x20];
6149 u8 reserved_at_88
[0x18];
6151 u8 reserved_at_a0
[0x8];
6154 u8 reserved_at_c0
[0x140];
6157 struct mlx5_ifc_destroy_flow_group_out_bits
{
6159 u8 reserved_at_8
[0x18];
6163 u8 reserved_at_40
[0x40];
6166 struct mlx5_ifc_destroy_flow_group_in_bits
{
6168 u8 reserved_at_10
[0x10];
6170 u8 reserved_at_20
[0x10];
6173 u8 other_vport
[0x1];
6174 u8 reserved_at_41
[0xf];
6175 u8 vport_number
[0x10];
6177 u8 reserved_at_60
[0x20];
6180 u8 reserved_at_88
[0x18];
6182 u8 reserved_at_a0
[0x8];
6187 u8 reserved_at_e0
[0x120];
6190 struct mlx5_ifc_destroy_eq_out_bits
{
6192 u8 reserved_at_8
[0x18];
6196 u8 reserved_at_40
[0x40];
6199 struct mlx5_ifc_destroy_eq_in_bits
{
6201 u8 reserved_at_10
[0x10];
6203 u8 reserved_at_20
[0x10];
6206 u8 reserved_at_40
[0x18];
6209 u8 reserved_at_60
[0x20];
6212 struct mlx5_ifc_destroy_dct_out_bits
{
6214 u8 reserved_at_8
[0x18];
6218 u8 reserved_at_40
[0x40];
6221 struct mlx5_ifc_destroy_dct_in_bits
{
6223 u8 reserved_at_10
[0x10];
6225 u8 reserved_at_20
[0x10];
6228 u8 reserved_at_40
[0x8];
6231 u8 reserved_at_60
[0x20];
6234 struct mlx5_ifc_destroy_cq_out_bits
{
6236 u8 reserved_at_8
[0x18];
6240 u8 reserved_at_40
[0x40];
6243 struct mlx5_ifc_destroy_cq_in_bits
{
6245 u8 reserved_at_10
[0x10];
6247 u8 reserved_at_20
[0x10];
6250 u8 reserved_at_40
[0x8];
6253 u8 reserved_at_60
[0x20];
6256 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits
{
6258 u8 reserved_at_8
[0x18];
6262 u8 reserved_at_40
[0x40];
6265 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits
{
6267 u8 reserved_at_10
[0x10];
6269 u8 reserved_at_20
[0x10];
6272 u8 reserved_at_40
[0x20];
6274 u8 reserved_at_60
[0x10];
6275 u8 vxlan_udp_port
[0x10];
6278 struct mlx5_ifc_delete_l2_table_entry_out_bits
{
6280 u8 reserved_at_8
[0x18];
6284 u8 reserved_at_40
[0x40];
6287 struct mlx5_ifc_delete_l2_table_entry_in_bits
{
6289 u8 reserved_at_10
[0x10];
6291 u8 reserved_at_20
[0x10];
6294 u8 reserved_at_40
[0x60];
6296 u8 reserved_at_a0
[0x8];
6297 u8 table_index
[0x18];
6299 u8 reserved_at_c0
[0x140];
6302 struct mlx5_ifc_delete_fte_out_bits
{
6304 u8 reserved_at_8
[0x18];
6308 u8 reserved_at_40
[0x40];
6311 struct mlx5_ifc_delete_fte_in_bits
{
6313 u8 reserved_at_10
[0x10];
6315 u8 reserved_at_20
[0x10];
6318 u8 other_vport
[0x1];
6319 u8 reserved_at_41
[0xf];
6320 u8 vport_number
[0x10];
6322 u8 reserved_at_60
[0x20];
6325 u8 reserved_at_88
[0x18];
6327 u8 reserved_at_a0
[0x8];
6330 u8 reserved_at_c0
[0x40];
6332 u8 flow_index
[0x20];
6334 u8 reserved_at_120
[0xe0];
6337 struct mlx5_ifc_dealloc_xrcd_out_bits
{
6339 u8 reserved_at_8
[0x18];
6343 u8 reserved_at_40
[0x40];
6346 struct mlx5_ifc_dealloc_xrcd_in_bits
{
6348 u8 reserved_at_10
[0x10];
6350 u8 reserved_at_20
[0x10];
6353 u8 reserved_at_40
[0x8];
6356 u8 reserved_at_60
[0x20];
6359 struct mlx5_ifc_dealloc_uar_out_bits
{
6361 u8 reserved_at_8
[0x18];
6365 u8 reserved_at_40
[0x40];
6368 struct mlx5_ifc_dealloc_uar_in_bits
{
6370 u8 reserved_at_10
[0x10];
6372 u8 reserved_at_20
[0x10];
6375 u8 reserved_at_40
[0x8];
6378 u8 reserved_at_60
[0x20];
6381 struct mlx5_ifc_dealloc_transport_domain_out_bits
{
6383 u8 reserved_at_8
[0x18];
6387 u8 reserved_at_40
[0x40];
6390 struct mlx5_ifc_dealloc_transport_domain_in_bits
{
6392 u8 reserved_at_10
[0x10];
6394 u8 reserved_at_20
[0x10];
6397 u8 reserved_at_40
[0x8];
6398 u8 transport_domain
[0x18];
6400 u8 reserved_at_60
[0x20];
6403 struct mlx5_ifc_dealloc_q_counter_out_bits
{
6405 u8 reserved_at_8
[0x18];
6409 u8 reserved_at_40
[0x40];
6412 struct mlx5_ifc_dealloc_q_counter_in_bits
{
6414 u8 reserved_at_10
[0x10];
6416 u8 reserved_at_20
[0x10];
6419 u8 reserved_at_40
[0x18];
6420 u8 counter_set_id
[0x8];
6422 u8 reserved_at_60
[0x20];
6425 struct mlx5_ifc_dealloc_pd_out_bits
{
6427 u8 reserved_at_8
[0x18];
6431 u8 reserved_at_40
[0x40];
6434 struct mlx5_ifc_dealloc_pd_in_bits
{
6436 u8 reserved_at_10
[0x10];
6438 u8 reserved_at_20
[0x10];
6441 u8 reserved_at_40
[0x8];
6444 u8 reserved_at_60
[0x20];
6447 struct mlx5_ifc_dealloc_flow_counter_out_bits
{
6449 u8 reserved_at_8
[0x18];
6453 u8 reserved_at_40
[0x40];
6456 struct mlx5_ifc_dealloc_flow_counter_in_bits
{
6458 u8 reserved_at_10
[0x10];
6460 u8 reserved_at_20
[0x10];
6463 u8 flow_counter_id
[0x20];
6465 u8 reserved_at_60
[0x20];
6468 struct mlx5_ifc_create_xrq_out_bits
{
6470 u8 reserved_at_8
[0x18];
6474 u8 reserved_at_40
[0x8];
6477 u8 reserved_at_60
[0x20];
6480 struct mlx5_ifc_create_xrq_in_bits
{
6482 u8 reserved_at_10
[0x10];
6484 u8 reserved_at_20
[0x10];
6487 u8 reserved_at_40
[0x40];
6489 struct mlx5_ifc_xrqc_bits xrq_context
;
6492 struct mlx5_ifc_create_xrc_srq_out_bits
{
6494 u8 reserved_at_8
[0x18];
6498 u8 reserved_at_40
[0x8];
6501 u8 reserved_at_60
[0x20];
6504 struct mlx5_ifc_create_xrc_srq_in_bits
{
6506 u8 reserved_at_10
[0x10];
6508 u8 reserved_at_20
[0x10];
6511 u8 reserved_at_40
[0x40];
6513 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
6515 u8 reserved_at_280
[0x600];
6520 struct mlx5_ifc_create_tis_out_bits
{
6522 u8 reserved_at_8
[0x18];
6526 u8 reserved_at_40
[0x8];
6529 u8 reserved_at_60
[0x20];
6532 struct mlx5_ifc_create_tis_in_bits
{
6534 u8 reserved_at_10
[0x10];
6536 u8 reserved_at_20
[0x10];
6539 u8 reserved_at_40
[0xc0];
6541 struct mlx5_ifc_tisc_bits ctx
;
6544 struct mlx5_ifc_create_tir_out_bits
{
6546 u8 reserved_at_8
[0x18];
6550 u8 reserved_at_40
[0x8];
6553 u8 reserved_at_60
[0x20];
6556 struct mlx5_ifc_create_tir_in_bits
{
6558 u8 reserved_at_10
[0x10];
6560 u8 reserved_at_20
[0x10];
6563 u8 reserved_at_40
[0xc0];
6565 struct mlx5_ifc_tirc_bits ctx
;
6568 struct mlx5_ifc_create_srq_out_bits
{
6570 u8 reserved_at_8
[0x18];
6574 u8 reserved_at_40
[0x8];
6577 u8 reserved_at_60
[0x20];
6580 struct mlx5_ifc_create_srq_in_bits
{
6582 u8 reserved_at_10
[0x10];
6584 u8 reserved_at_20
[0x10];
6587 u8 reserved_at_40
[0x40];
6589 struct mlx5_ifc_srqc_bits srq_context_entry
;
6591 u8 reserved_at_280
[0x600];
6596 struct mlx5_ifc_create_sq_out_bits
{
6598 u8 reserved_at_8
[0x18];
6602 u8 reserved_at_40
[0x8];
6605 u8 reserved_at_60
[0x20];
6608 struct mlx5_ifc_create_sq_in_bits
{
6610 u8 reserved_at_10
[0x10];
6612 u8 reserved_at_20
[0x10];
6615 u8 reserved_at_40
[0xc0];
6617 struct mlx5_ifc_sqc_bits ctx
;
6620 struct mlx5_ifc_create_scheduling_element_out_bits
{
6622 u8 reserved_at_8
[0x18];
6626 u8 reserved_at_40
[0x40];
6628 u8 scheduling_element_id
[0x20];
6630 u8 reserved_at_a0
[0x160];
6633 struct mlx5_ifc_create_scheduling_element_in_bits
{
6635 u8 reserved_at_10
[0x10];
6637 u8 reserved_at_20
[0x10];
6640 u8 scheduling_hierarchy
[0x8];
6641 u8 reserved_at_48
[0x18];
6643 u8 reserved_at_60
[0xa0];
6645 struct mlx5_ifc_scheduling_context_bits scheduling_context
;
6647 u8 reserved_at_300
[0x100];
6650 struct mlx5_ifc_create_rqt_out_bits
{
6652 u8 reserved_at_8
[0x18];
6656 u8 reserved_at_40
[0x8];
6659 u8 reserved_at_60
[0x20];
6662 struct mlx5_ifc_create_rqt_in_bits
{
6664 u8 reserved_at_10
[0x10];
6666 u8 reserved_at_20
[0x10];
6669 u8 reserved_at_40
[0xc0];
6671 struct mlx5_ifc_rqtc_bits rqt_context
;
6674 struct mlx5_ifc_create_rq_out_bits
{
6676 u8 reserved_at_8
[0x18];
6680 u8 reserved_at_40
[0x8];
6683 u8 reserved_at_60
[0x20];
6686 struct mlx5_ifc_create_rq_in_bits
{
6688 u8 reserved_at_10
[0x10];
6690 u8 reserved_at_20
[0x10];
6693 u8 reserved_at_40
[0xc0];
6695 struct mlx5_ifc_rqc_bits ctx
;
6698 struct mlx5_ifc_create_rmp_out_bits
{
6700 u8 reserved_at_8
[0x18];
6704 u8 reserved_at_40
[0x8];
6707 u8 reserved_at_60
[0x20];
6710 struct mlx5_ifc_create_rmp_in_bits
{
6712 u8 reserved_at_10
[0x10];
6714 u8 reserved_at_20
[0x10];
6717 u8 reserved_at_40
[0xc0];
6719 struct mlx5_ifc_rmpc_bits ctx
;
6722 struct mlx5_ifc_create_qp_out_bits
{
6724 u8 reserved_at_8
[0x18];
6728 u8 reserved_at_40
[0x8];
6731 u8 reserved_at_60
[0x20];
6734 struct mlx5_ifc_create_qp_in_bits
{
6736 u8 reserved_at_10
[0x10];
6738 u8 reserved_at_20
[0x10];
6741 u8 reserved_at_40
[0x40];
6743 u8 opt_param_mask
[0x20];
6745 u8 reserved_at_a0
[0x20];
6747 struct mlx5_ifc_qpc_bits qpc
;
6749 u8 reserved_at_800
[0x80];
6754 struct mlx5_ifc_create_psv_out_bits
{
6756 u8 reserved_at_8
[0x18];
6760 u8 reserved_at_40
[0x40];
6762 u8 reserved_at_80
[0x8];
6763 u8 psv0_index
[0x18];
6765 u8 reserved_at_a0
[0x8];
6766 u8 psv1_index
[0x18];
6768 u8 reserved_at_c0
[0x8];
6769 u8 psv2_index
[0x18];
6771 u8 reserved_at_e0
[0x8];
6772 u8 psv3_index
[0x18];
6775 struct mlx5_ifc_create_psv_in_bits
{
6777 u8 reserved_at_10
[0x10];
6779 u8 reserved_at_20
[0x10];
6783 u8 reserved_at_44
[0x4];
6786 u8 reserved_at_60
[0x20];
6789 struct mlx5_ifc_create_mkey_out_bits
{
6791 u8 reserved_at_8
[0x18];
6795 u8 reserved_at_40
[0x8];
6796 u8 mkey_index
[0x18];
6798 u8 reserved_at_60
[0x20];
6801 struct mlx5_ifc_create_mkey_in_bits
{
6803 u8 reserved_at_10
[0x10];
6805 u8 reserved_at_20
[0x10];
6808 u8 reserved_at_40
[0x20];
6811 u8 reserved_at_61
[0x1f];
6813 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
6815 u8 reserved_at_280
[0x80];
6817 u8 translations_octword_actual_size
[0x20];
6819 u8 reserved_at_320
[0x560];
6821 u8 klm_pas_mtt
[0][0x20];
6824 struct mlx5_ifc_create_flow_table_out_bits
{
6826 u8 reserved_at_8
[0x18];
6830 u8 reserved_at_40
[0x8];
6833 u8 reserved_at_60
[0x20];
6836 struct mlx5_ifc_flow_table_context_bits
{
6839 u8 reserved_at_2
[0x2];
6840 u8 table_miss_action
[0x4];
6842 u8 reserved_at_10
[0x8];
6845 u8 reserved_at_20
[0x8];
6846 u8 table_miss_id
[0x18];
6848 u8 reserved_at_40
[0x8];
6849 u8 lag_master_next_table_id
[0x18];
6851 u8 reserved_at_60
[0xe0];
6854 struct mlx5_ifc_create_flow_table_in_bits
{
6856 u8 reserved_at_10
[0x10];
6858 u8 reserved_at_20
[0x10];
6861 u8 other_vport
[0x1];
6862 u8 reserved_at_41
[0xf];
6863 u8 vport_number
[0x10];
6865 u8 reserved_at_60
[0x20];
6868 u8 reserved_at_88
[0x18];
6870 u8 reserved_at_a0
[0x20];
6872 struct mlx5_ifc_flow_table_context_bits flow_table_context
;
6875 struct mlx5_ifc_create_flow_group_out_bits
{
6877 u8 reserved_at_8
[0x18];
6881 u8 reserved_at_40
[0x8];
6884 u8 reserved_at_60
[0x20];
6888 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
6889 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
6890 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
6893 struct mlx5_ifc_create_flow_group_in_bits
{
6895 u8 reserved_at_10
[0x10];
6897 u8 reserved_at_20
[0x10];
6900 u8 other_vport
[0x1];
6901 u8 reserved_at_41
[0xf];
6902 u8 vport_number
[0x10];
6904 u8 reserved_at_60
[0x20];
6907 u8 reserved_at_88
[0x18];
6909 u8 reserved_at_a0
[0x8];
6912 u8 reserved_at_c0
[0x20];
6914 u8 start_flow_index
[0x20];
6916 u8 reserved_at_100
[0x20];
6918 u8 end_flow_index
[0x20];
6920 u8 reserved_at_140
[0xa0];
6922 u8 reserved_at_1e0
[0x18];
6923 u8 match_criteria_enable
[0x8];
6925 struct mlx5_ifc_fte_match_param_bits match_criteria
;
6927 u8 reserved_at_1200
[0xe00];
6930 struct mlx5_ifc_create_eq_out_bits
{
6932 u8 reserved_at_8
[0x18];
6936 u8 reserved_at_40
[0x18];
6939 u8 reserved_at_60
[0x20];
6942 struct mlx5_ifc_create_eq_in_bits
{
6944 u8 reserved_at_10
[0x10];
6946 u8 reserved_at_20
[0x10];
6949 u8 reserved_at_40
[0x40];
6951 struct mlx5_ifc_eqc_bits eq_context_entry
;
6953 u8 reserved_at_280
[0x40];
6955 u8 event_bitmask
[0x40];
6957 u8 reserved_at_300
[0x580];
6962 struct mlx5_ifc_create_dct_out_bits
{
6964 u8 reserved_at_8
[0x18];
6968 u8 reserved_at_40
[0x8];
6971 u8 reserved_at_60
[0x20];
6974 struct mlx5_ifc_create_dct_in_bits
{
6976 u8 reserved_at_10
[0x10];
6978 u8 reserved_at_20
[0x10];
6981 u8 reserved_at_40
[0x40];
6983 struct mlx5_ifc_dctc_bits dct_context_entry
;
6985 u8 reserved_at_280
[0x180];
6988 struct mlx5_ifc_create_cq_out_bits
{
6990 u8 reserved_at_8
[0x18];
6994 u8 reserved_at_40
[0x8];
6997 u8 reserved_at_60
[0x20];
7000 struct mlx5_ifc_create_cq_in_bits
{
7002 u8 reserved_at_10
[0x10];
7004 u8 reserved_at_20
[0x10];
7007 u8 reserved_at_40
[0x40];
7009 struct mlx5_ifc_cqc_bits cq_context
;
7011 u8 reserved_at_280
[0x600];
7016 struct mlx5_ifc_config_int_moderation_out_bits
{
7018 u8 reserved_at_8
[0x18];
7022 u8 reserved_at_40
[0x4];
7024 u8 int_vector
[0x10];
7026 u8 reserved_at_60
[0x20];
7030 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE
= 0x0,
7031 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ
= 0x1,
7034 struct mlx5_ifc_config_int_moderation_in_bits
{
7036 u8 reserved_at_10
[0x10];
7038 u8 reserved_at_20
[0x10];
7041 u8 reserved_at_40
[0x4];
7043 u8 int_vector
[0x10];
7045 u8 reserved_at_60
[0x20];
7048 struct mlx5_ifc_attach_to_mcg_out_bits
{
7050 u8 reserved_at_8
[0x18];
7054 u8 reserved_at_40
[0x40];
7057 struct mlx5_ifc_attach_to_mcg_in_bits
{
7059 u8 reserved_at_10
[0x10];
7061 u8 reserved_at_20
[0x10];
7064 u8 reserved_at_40
[0x8];
7067 u8 reserved_at_60
[0x20];
7069 u8 multicast_gid
[16][0x8];
7072 struct mlx5_ifc_arm_xrq_out_bits
{
7074 u8 reserved_at_8
[0x18];
7078 u8 reserved_at_40
[0x40];
7081 struct mlx5_ifc_arm_xrq_in_bits
{
7083 u8 reserved_at_10
[0x10];
7085 u8 reserved_at_20
[0x10];
7088 u8 reserved_at_40
[0x8];
7091 u8 reserved_at_60
[0x10];
7095 struct mlx5_ifc_arm_xrc_srq_out_bits
{
7097 u8 reserved_at_8
[0x18];
7101 u8 reserved_at_40
[0x40];
7105 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ
= 0x1,
7108 struct mlx5_ifc_arm_xrc_srq_in_bits
{
7110 u8 reserved_at_10
[0x10];
7112 u8 reserved_at_20
[0x10];
7115 u8 reserved_at_40
[0x8];
7118 u8 reserved_at_60
[0x10];
7122 struct mlx5_ifc_arm_rq_out_bits
{
7124 u8 reserved_at_8
[0x18];
7128 u8 reserved_at_40
[0x40];
7132 MLX5_ARM_RQ_IN_OP_MOD_SRQ
= 0x1,
7133 MLX5_ARM_RQ_IN_OP_MOD_XRQ
= 0x2,
7136 struct mlx5_ifc_arm_rq_in_bits
{
7138 u8 reserved_at_10
[0x10];
7140 u8 reserved_at_20
[0x10];
7143 u8 reserved_at_40
[0x8];
7144 u8 srq_number
[0x18];
7146 u8 reserved_at_60
[0x10];
7150 struct mlx5_ifc_arm_dct_out_bits
{
7152 u8 reserved_at_8
[0x18];
7156 u8 reserved_at_40
[0x40];
7159 struct mlx5_ifc_arm_dct_in_bits
{
7161 u8 reserved_at_10
[0x10];
7163 u8 reserved_at_20
[0x10];
7166 u8 reserved_at_40
[0x8];
7167 u8 dct_number
[0x18];
7169 u8 reserved_at_60
[0x20];
7172 struct mlx5_ifc_alloc_xrcd_out_bits
{
7174 u8 reserved_at_8
[0x18];
7178 u8 reserved_at_40
[0x8];
7181 u8 reserved_at_60
[0x20];
7184 struct mlx5_ifc_alloc_xrcd_in_bits
{
7186 u8 reserved_at_10
[0x10];
7188 u8 reserved_at_20
[0x10];
7191 u8 reserved_at_40
[0x40];
7194 struct mlx5_ifc_alloc_uar_out_bits
{
7196 u8 reserved_at_8
[0x18];
7200 u8 reserved_at_40
[0x8];
7203 u8 reserved_at_60
[0x20];
7206 struct mlx5_ifc_alloc_uar_in_bits
{
7208 u8 reserved_at_10
[0x10];
7210 u8 reserved_at_20
[0x10];
7213 u8 reserved_at_40
[0x40];
7216 struct mlx5_ifc_alloc_transport_domain_out_bits
{
7218 u8 reserved_at_8
[0x18];
7222 u8 reserved_at_40
[0x8];
7223 u8 transport_domain
[0x18];
7225 u8 reserved_at_60
[0x20];
7228 struct mlx5_ifc_alloc_transport_domain_in_bits
{
7230 u8 reserved_at_10
[0x10];
7232 u8 reserved_at_20
[0x10];
7235 u8 reserved_at_40
[0x40];
7238 struct mlx5_ifc_alloc_q_counter_out_bits
{
7240 u8 reserved_at_8
[0x18];
7244 u8 reserved_at_40
[0x18];
7245 u8 counter_set_id
[0x8];
7247 u8 reserved_at_60
[0x20];
7250 struct mlx5_ifc_alloc_q_counter_in_bits
{
7252 u8 reserved_at_10
[0x10];
7254 u8 reserved_at_20
[0x10];
7257 u8 reserved_at_40
[0x40];
7260 struct mlx5_ifc_alloc_pd_out_bits
{
7262 u8 reserved_at_8
[0x18];
7266 u8 reserved_at_40
[0x8];
7269 u8 reserved_at_60
[0x20];
7272 struct mlx5_ifc_alloc_pd_in_bits
{
7274 u8 reserved_at_10
[0x10];
7276 u8 reserved_at_20
[0x10];
7279 u8 reserved_at_40
[0x40];
7282 struct mlx5_ifc_alloc_flow_counter_out_bits
{
7284 u8 reserved_at_8
[0x18];
7288 u8 flow_counter_id
[0x20];
7290 u8 reserved_at_60
[0x20];
7293 struct mlx5_ifc_alloc_flow_counter_in_bits
{
7295 u8 reserved_at_10
[0x10];
7297 u8 reserved_at_20
[0x10];
7300 u8 reserved_at_40
[0x40];
7303 struct mlx5_ifc_add_vxlan_udp_dport_out_bits
{
7305 u8 reserved_at_8
[0x18];
7309 u8 reserved_at_40
[0x40];
7312 struct mlx5_ifc_add_vxlan_udp_dport_in_bits
{
7314 u8 reserved_at_10
[0x10];
7316 u8 reserved_at_20
[0x10];
7319 u8 reserved_at_40
[0x20];
7321 u8 reserved_at_60
[0x10];
7322 u8 vxlan_udp_port
[0x10];
7325 struct mlx5_ifc_set_pp_rate_limit_out_bits
{
7327 u8 reserved_at_8
[0x18];
7331 u8 reserved_at_40
[0x40];
7334 struct mlx5_ifc_set_pp_rate_limit_in_bits
{
7336 u8 reserved_at_10
[0x10];
7338 u8 reserved_at_20
[0x10];
7341 u8 reserved_at_40
[0x10];
7342 u8 rate_limit_index
[0x10];
7344 u8 reserved_at_60
[0x20];
7346 u8 rate_limit
[0x20];
7348 u8 burst_upper_bound
[0x20];
7350 u8 reserved_at_c0
[0x10];
7351 u8 typical_packet_size
[0x10];
7353 u8 reserved_at_e0
[0x120];
7356 struct mlx5_ifc_access_register_out_bits
{
7358 u8 reserved_at_8
[0x18];
7362 u8 reserved_at_40
[0x40];
7364 u8 register_data
[0][0x20];
7368 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE
= 0x0,
7369 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ
= 0x1,
7372 struct mlx5_ifc_access_register_in_bits
{
7374 u8 reserved_at_10
[0x10];
7376 u8 reserved_at_20
[0x10];
7379 u8 reserved_at_40
[0x10];
7380 u8 register_id
[0x10];
7384 u8 register_data
[0][0x20];
7387 struct mlx5_ifc_sltp_reg_bits
{
7392 u8 reserved_at_12
[0x2];
7394 u8 reserved_at_18
[0x8];
7396 u8 reserved_at_20
[0x20];
7398 u8 reserved_at_40
[0x7];
7404 u8 reserved_at_60
[0xc];
7405 u8 ob_preemp_mode
[0x4];
7409 u8 reserved_at_80
[0x20];
7412 struct mlx5_ifc_slrg_reg_bits
{
7417 u8 reserved_at_12
[0x2];
7419 u8 reserved_at_18
[0x8];
7421 u8 time_to_link_up
[0x10];
7422 u8 reserved_at_30
[0xc];
7423 u8 grade_lane_speed
[0x4];
7425 u8 grade_version
[0x8];
7428 u8 reserved_at_60
[0x4];
7429 u8 height_grade_type
[0x4];
7430 u8 height_grade
[0x18];
7435 u8 reserved_at_a0
[0x10];
7436 u8 height_sigma
[0x10];
7438 u8 reserved_at_c0
[0x20];
7440 u8 reserved_at_e0
[0x4];
7441 u8 phase_grade_type
[0x4];
7442 u8 phase_grade
[0x18];
7444 u8 reserved_at_100
[0x8];
7445 u8 phase_eo_pos
[0x8];
7446 u8 reserved_at_110
[0x8];
7447 u8 phase_eo_neg
[0x8];
7449 u8 ffe_set_tested
[0x10];
7450 u8 test_errors_per_lane
[0x10];
7453 struct mlx5_ifc_pvlc_reg_bits
{
7454 u8 reserved_at_0
[0x8];
7456 u8 reserved_at_10
[0x10];
7458 u8 reserved_at_20
[0x1c];
7461 u8 reserved_at_40
[0x1c];
7464 u8 reserved_at_60
[0x1c];
7465 u8 vl_operational
[0x4];
7468 struct mlx5_ifc_pude_reg_bits
{
7471 u8 reserved_at_10
[0x4];
7472 u8 admin_status
[0x4];
7473 u8 reserved_at_18
[0x4];
7474 u8 oper_status
[0x4];
7476 u8 reserved_at_20
[0x60];
7479 struct mlx5_ifc_ptys_reg_bits
{
7480 u8 reserved_at_0
[0x1];
7481 u8 an_disable_admin
[0x1];
7482 u8 an_disable_cap
[0x1];
7483 u8 reserved_at_3
[0x5];
7485 u8 reserved_at_10
[0xd];
7489 u8 reserved_at_24
[0x3c];
7491 u8 eth_proto_capability
[0x20];
7493 u8 ib_link_width_capability
[0x10];
7494 u8 ib_proto_capability
[0x10];
7496 u8 reserved_at_a0
[0x20];
7498 u8 eth_proto_admin
[0x20];
7500 u8 ib_link_width_admin
[0x10];
7501 u8 ib_proto_admin
[0x10];
7503 u8 reserved_at_100
[0x20];
7505 u8 eth_proto_oper
[0x20];
7507 u8 ib_link_width_oper
[0x10];
7508 u8 ib_proto_oper
[0x10];
7510 u8 reserved_at_160
[0x1c];
7511 u8 connector_type
[0x4];
7513 u8 eth_proto_lp_advertise
[0x20];
7515 u8 reserved_at_1a0
[0x60];
7518 struct mlx5_ifc_mlcr_reg_bits
{
7519 u8 reserved_at_0
[0x8];
7521 u8 reserved_at_10
[0x20];
7523 u8 beacon_duration
[0x10];
7524 u8 reserved_at_40
[0x10];
7526 u8 beacon_remain
[0x10];
7529 struct mlx5_ifc_ptas_reg_bits
{
7530 u8 reserved_at_0
[0x20];
7532 u8 algorithm_options
[0x10];
7533 u8 reserved_at_30
[0x4];
7534 u8 repetitions_mode
[0x4];
7535 u8 num_of_repetitions
[0x8];
7537 u8 grade_version
[0x8];
7538 u8 height_grade_type
[0x4];
7539 u8 phase_grade_type
[0x4];
7540 u8 height_grade_weight
[0x8];
7541 u8 phase_grade_weight
[0x8];
7543 u8 gisim_measure_bits
[0x10];
7544 u8 adaptive_tap_measure_bits
[0x10];
7546 u8 ber_bath_high_error_threshold
[0x10];
7547 u8 ber_bath_mid_error_threshold
[0x10];
7549 u8 ber_bath_low_error_threshold
[0x10];
7550 u8 one_ratio_high_threshold
[0x10];
7552 u8 one_ratio_high_mid_threshold
[0x10];
7553 u8 one_ratio_low_mid_threshold
[0x10];
7555 u8 one_ratio_low_threshold
[0x10];
7556 u8 ndeo_error_threshold
[0x10];
7558 u8 mixer_offset_step_size
[0x10];
7559 u8 reserved_at_110
[0x8];
7560 u8 mix90_phase_for_voltage_bath
[0x8];
7562 u8 mixer_offset_start
[0x10];
7563 u8 mixer_offset_end
[0x10];
7565 u8 reserved_at_140
[0x15];
7566 u8 ber_test_time
[0xb];
7569 struct mlx5_ifc_pspa_reg_bits
{
7573 u8 reserved_at_18
[0x8];
7575 u8 reserved_at_20
[0x20];
7578 struct mlx5_ifc_pqdr_reg_bits
{
7579 u8 reserved_at_0
[0x8];
7581 u8 reserved_at_10
[0x5];
7583 u8 reserved_at_18
[0x6];
7586 u8 reserved_at_20
[0x20];
7588 u8 reserved_at_40
[0x10];
7589 u8 min_threshold
[0x10];
7591 u8 reserved_at_60
[0x10];
7592 u8 max_threshold
[0x10];
7594 u8 reserved_at_80
[0x10];
7595 u8 mark_probability_denominator
[0x10];
7597 u8 reserved_at_a0
[0x60];
7600 struct mlx5_ifc_ppsc_reg_bits
{
7601 u8 reserved_at_0
[0x8];
7603 u8 reserved_at_10
[0x10];
7605 u8 reserved_at_20
[0x60];
7607 u8 reserved_at_80
[0x1c];
7610 u8 reserved_at_a0
[0x1c];
7611 u8 wrps_status
[0x4];
7613 u8 reserved_at_c0
[0x8];
7614 u8 up_threshold
[0x8];
7615 u8 reserved_at_d0
[0x8];
7616 u8 down_threshold
[0x8];
7618 u8 reserved_at_e0
[0x20];
7620 u8 reserved_at_100
[0x1c];
7623 u8 reserved_at_120
[0x1c];
7624 u8 srps_status
[0x4];
7626 u8 reserved_at_140
[0x40];
7629 struct mlx5_ifc_pplr_reg_bits
{
7630 u8 reserved_at_0
[0x8];
7632 u8 reserved_at_10
[0x10];
7634 u8 reserved_at_20
[0x8];
7636 u8 reserved_at_30
[0x8];
7640 struct mlx5_ifc_pplm_reg_bits
{
7641 u8 reserved_at_0
[0x8];
7643 u8 reserved_at_10
[0x10];
7645 u8 reserved_at_20
[0x20];
7647 u8 port_profile_mode
[0x8];
7648 u8 static_port_profile
[0x8];
7649 u8 active_port_profile
[0x8];
7650 u8 reserved_at_58
[0x8];
7652 u8 retransmission_active
[0x8];
7653 u8 fec_mode_active
[0x18];
7655 u8 reserved_at_80
[0x20];
7658 struct mlx5_ifc_ppcnt_reg_bits
{
7662 u8 reserved_at_12
[0x8];
7666 u8 reserved_at_21
[0x1c];
7669 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set
;
7672 struct mlx5_ifc_mpcnt_reg_bits
{
7673 u8 reserved_at_0
[0x8];
7675 u8 reserved_at_10
[0xa];
7679 u8 reserved_at_21
[0x1f];
7681 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set
;
7684 struct mlx5_ifc_ppad_reg_bits
{
7685 u8 reserved_at_0
[0x3];
7687 u8 reserved_at_4
[0x4];
7693 u8 reserved_at_40
[0x40];
7696 struct mlx5_ifc_pmtu_reg_bits
{
7697 u8 reserved_at_0
[0x8];
7699 u8 reserved_at_10
[0x10];
7702 u8 reserved_at_30
[0x10];
7705 u8 reserved_at_50
[0x10];
7708 u8 reserved_at_70
[0x10];
7711 struct mlx5_ifc_pmpr_reg_bits
{
7712 u8 reserved_at_0
[0x8];
7714 u8 reserved_at_10
[0x10];
7716 u8 reserved_at_20
[0x18];
7717 u8 attenuation_5g
[0x8];
7719 u8 reserved_at_40
[0x18];
7720 u8 attenuation_7g
[0x8];
7722 u8 reserved_at_60
[0x18];
7723 u8 attenuation_12g
[0x8];
7726 struct mlx5_ifc_pmpe_reg_bits
{
7727 u8 reserved_at_0
[0x8];
7729 u8 reserved_at_10
[0xc];
7730 u8 module_status
[0x4];
7732 u8 reserved_at_20
[0x60];
7735 struct mlx5_ifc_pmpc_reg_bits
{
7736 u8 module_state_updated
[32][0x8];
7739 struct mlx5_ifc_pmlpn_reg_bits
{
7740 u8 reserved_at_0
[0x4];
7741 u8 mlpn_status
[0x4];
7743 u8 reserved_at_10
[0x10];
7746 u8 reserved_at_21
[0x1f];
7749 struct mlx5_ifc_pmlp_reg_bits
{
7751 u8 reserved_at_1
[0x7];
7753 u8 reserved_at_10
[0x8];
7756 u8 lane0_module_mapping
[0x20];
7758 u8 lane1_module_mapping
[0x20];
7760 u8 lane2_module_mapping
[0x20];
7762 u8 lane3_module_mapping
[0x20];
7764 u8 reserved_at_a0
[0x160];
7767 struct mlx5_ifc_pmaos_reg_bits
{
7768 u8 reserved_at_0
[0x8];
7770 u8 reserved_at_10
[0x4];
7771 u8 admin_status
[0x4];
7772 u8 reserved_at_18
[0x4];
7773 u8 oper_status
[0x4];
7777 u8 reserved_at_22
[0x1c];
7780 u8 reserved_at_40
[0x40];
7783 struct mlx5_ifc_plpc_reg_bits
{
7784 u8 reserved_at_0
[0x4];
7786 u8 reserved_at_10
[0x4];
7788 u8 reserved_at_18
[0x8];
7790 u8 reserved_at_20
[0x10];
7791 u8 lane_speed
[0x10];
7793 u8 reserved_at_40
[0x17];
7795 u8 fec_mode_policy
[0x8];
7797 u8 retransmission_capability
[0x8];
7798 u8 fec_mode_capability
[0x18];
7800 u8 retransmission_support_admin
[0x8];
7801 u8 fec_mode_support_admin
[0x18];
7803 u8 retransmission_request_admin
[0x8];
7804 u8 fec_mode_request_admin
[0x18];
7806 u8 reserved_at_c0
[0x80];
7809 struct mlx5_ifc_plib_reg_bits
{
7810 u8 reserved_at_0
[0x8];
7812 u8 reserved_at_10
[0x8];
7815 u8 reserved_at_20
[0x60];
7818 struct mlx5_ifc_plbf_reg_bits
{
7819 u8 reserved_at_0
[0x8];
7821 u8 reserved_at_10
[0xd];
7824 u8 reserved_at_20
[0x20];
7827 struct mlx5_ifc_pipg_reg_bits
{
7828 u8 reserved_at_0
[0x8];
7830 u8 reserved_at_10
[0x10];
7833 u8 reserved_at_21
[0x19];
7835 u8 reserved_at_3e
[0x2];
7838 struct mlx5_ifc_pifr_reg_bits
{
7839 u8 reserved_at_0
[0x8];
7841 u8 reserved_at_10
[0x10];
7843 u8 reserved_at_20
[0xe0];
7845 u8 port_filter
[8][0x20];
7847 u8 port_filter_update_en
[8][0x20];
7850 struct mlx5_ifc_pfcc_reg_bits
{
7851 u8 reserved_at_0
[0x8];
7853 u8 reserved_at_10
[0x10];
7856 u8 reserved_at_24
[0x4];
7857 u8 prio_mask_tx
[0x8];
7858 u8 reserved_at_30
[0x8];
7859 u8 prio_mask_rx
[0x8];
7863 u8 reserved_at_42
[0x6];
7865 u8 reserved_at_50
[0x10];
7869 u8 reserved_at_62
[0x6];
7871 u8 reserved_at_70
[0x10];
7873 u8 reserved_at_80
[0x80];
7876 struct mlx5_ifc_pelc_reg_bits
{
7878 u8 reserved_at_4
[0x4];
7880 u8 reserved_at_10
[0x10];
7883 u8 op_capability
[0x8];
7889 u8 capability
[0x40];
7895 u8 reserved_at_140
[0x80];
7898 struct mlx5_ifc_peir_reg_bits
{
7899 u8 reserved_at_0
[0x8];
7901 u8 reserved_at_10
[0x10];
7903 u8 reserved_at_20
[0xc];
7904 u8 error_count
[0x4];
7905 u8 reserved_at_30
[0x10];
7907 u8 reserved_at_40
[0xc];
7909 u8 reserved_at_50
[0x8];
7913 struct mlx5_ifc_pcam_enhanced_features_bits
{
7914 u8 reserved_at_0
[0x7b];
7916 u8 rx_buffer_fullness_counters
[0x1];
7917 u8 ptys_connector_type
[0x1];
7918 u8 reserved_at_7d
[0x1];
7919 u8 ppcnt_discard_group
[0x1];
7920 u8 ppcnt_statistical_group
[0x1];
7923 struct mlx5_ifc_pcam_reg_bits
{
7924 u8 reserved_at_0
[0x8];
7925 u8 feature_group
[0x8];
7926 u8 reserved_at_10
[0x8];
7927 u8 access_reg_group
[0x8];
7929 u8 reserved_at_20
[0x20];
7932 u8 reserved_at_0
[0x80];
7933 } port_access_reg_cap_mask
;
7935 u8 reserved_at_c0
[0x80];
7938 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features
;
7939 u8 reserved_at_0
[0x80];
7942 u8 reserved_at_1c0
[0xc0];
7945 struct mlx5_ifc_mcam_enhanced_features_bits
{
7946 u8 reserved_at_0
[0x7b];
7947 u8 pcie_outbound_stalled
[0x1];
7948 u8 tx_overflow_buffer_pkt
[0x1];
7949 u8 mtpps_enh_out_per_adj
[0x1];
7951 u8 pcie_performance_group
[0x1];
7954 struct mlx5_ifc_mcam_access_reg_bits
{
7955 u8 reserved_at_0
[0x1c];
7959 u8 reserved_at_1f
[0x1];
7961 u8 regs_95_to_64
[0x20];
7962 u8 regs_63_to_32
[0x20];
7963 u8 regs_31_to_0
[0x20];
7966 struct mlx5_ifc_mcam_reg_bits
{
7967 u8 reserved_at_0
[0x8];
7968 u8 feature_group
[0x8];
7969 u8 reserved_at_10
[0x8];
7970 u8 access_reg_group
[0x8];
7972 u8 reserved_at_20
[0x20];
7975 struct mlx5_ifc_mcam_access_reg_bits access_regs
;
7976 u8 reserved_at_0
[0x80];
7977 } mng_access_reg_cap_mask
;
7979 u8 reserved_at_c0
[0x80];
7982 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features
;
7983 u8 reserved_at_0
[0x80];
7984 } mng_feature_cap_mask
;
7986 u8 reserved_at_1c0
[0x80];
7989 struct mlx5_ifc_qcam_access_reg_cap_mask
{
7990 u8 qcam_access_reg_cap_mask_127_to_20
[0x6C];
7992 u8 qcam_access_reg_cap_mask_18_to_4
[0x0F];
7996 u8 qcam_access_reg_cap_mask_0
[0x1];
7999 struct mlx5_ifc_qcam_qos_feature_cap_mask
{
8000 u8 qcam_qos_feature_cap_mask_127_to_1
[0x7F];
8001 u8 qpts_trust_both
[0x1];
8004 struct mlx5_ifc_qcam_reg_bits
{
8005 u8 reserved_at_0
[0x8];
8006 u8 feature_group
[0x8];
8007 u8 reserved_at_10
[0x8];
8008 u8 access_reg_group
[0x8];
8009 u8 reserved_at_20
[0x20];
8012 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap
;
8013 u8 reserved_at_0
[0x80];
8014 } qos_access_reg_cap_mask
;
8016 u8 reserved_at_c0
[0x80];
8019 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap
;
8020 u8 reserved_at_0
[0x80];
8021 } qos_feature_cap_mask
;
8023 u8 reserved_at_1c0
[0x80];
8026 struct mlx5_ifc_pcap_reg_bits
{
8027 u8 reserved_at_0
[0x8];
8029 u8 reserved_at_10
[0x10];
8031 u8 port_capability_mask
[4][0x20];
8034 struct mlx5_ifc_paos_reg_bits
{
8037 u8 reserved_at_10
[0x4];
8038 u8 admin_status
[0x4];
8039 u8 reserved_at_18
[0x4];
8040 u8 oper_status
[0x4];
8044 u8 reserved_at_22
[0x1c];
8047 u8 reserved_at_40
[0x40];
8050 struct mlx5_ifc_pamp_reg_bits
{
8051 u8 reserved_at_0
[0x8];
8052 u8 opamp_group
[0x8];
8053 u8 reserved_at_10
[0xc];
8054 u8 opamp_group_type
[0x4];
8056 u8 start_index
[0x10];
8057 u8 reserved_at_30
[0x4];
8058 u8 num_of_indices
[0xc];
8060 u8 index_data
[18][0x10];
8063 struct mlx5_ifc_pcmr_reg_bits
{
8064 u8 reserved_at_0
[0x8];
8066 u8 reserved_at_10
[0x2e];
8068 u8 reserved_at_3f
[0x1f];
8070 u8 reserved_at_5f
[0x1];
8073 struct mlx5_ifc_lane_2_module_mapping_bits
{
8074 u8 reserved_at_0
[0x6];
8076 u8 reserved_at_8
[0x6];
8078 u8 reserved_at_10
[0x8];
8082 struct mlx5_ifc_bufferx_reg_bits
{
8083 u8 reserved_at_0
[0x6];
8086 u8 reserved_at_8
[0xc];
8089 u8 xoff_threshold
[0x10];
8090 u8 xon_threshold
[0x10];
8093 struct mlx5_ifc_set_node_in_bits
{
8094 u8 node_description
[64][0x8];
8097 struct mlx5_ifc_register_power_settings_bits
{
8098 u8 reserved_at_0
[0x18];
8099 u8 power_settings_level
[0x8];
8101 u8 reserved_at_20
[0x60];
8104 struct mlx5_ifc_register_host_endianness_bits
{
8106 u8 reserved_at_1
[0x1f];
8108 u8 reserved_at_20
[0x60];
8111 struct mlx5_ifc_umr_pointer_desc_argument_bits
{
8112 u8 reserved_at_0
[0x20];
8116 u8 addressh_63_32
[0x20];
8118 u8 addressl_31_0
[0x20];
8121 struct mlx5_ifc_ud_adrs_vector_bits
{
8125 u8 reserved_at_41
[0x7];
8126 u8 destination_qp_dct
[0x18];
8128 u8 static_rate
[0x4];
8129 u8 sl_eth_prio
[0x4];
8132 u8 rlid_udp_sport
[0x10];
8134 u8 reserved_at_80
[0x20];
8136 u8 rmac_47_16
[0x20];
8142 u8 reserved_at_e0
[0x1];
8144 u8 reserved_at_e2
[0x2];
8145 u8 src_addr_index
[0x8];
8146 u8 flow_label
[0x14];
8148 u8 rgid_rip
[16][0x8];
8151 struct mlx5_ifc_pages_req_event_bits
{
8152 u8 reserved_at_0
[0x10];
8153 u8 function_id
[0x10];
8157 u8 reserved_at_40
[0xa0];
8160 struct mlx5_ifc_eqe_bits
{
8161 u8 reserved_at_0
[0x8];
8163 u8 reserved_at_10
[0x8];
8164 u8 event_sub_type
[0x8];
8166 u8 reserved_at_20
[0xe0];
8168 union mlx5_ifc_event_auto_bits event_data
;
8170 u8 reserved_at_1e0
[0x10];
8172 u8 reserved_at_1f8
[0x7];
8177 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT
= 0x7,
8180 struct mlx5_ifc_cmd_queue_entry_bits
{
8182 u8 reserved_at_8
[0x18];
8184 u8 input_length
[0x20];
8186 u8 input_mailbox_pointer_63_32
[0x20];
8188 u8 input_mailbox_pointer_31_9
[0x17];
8189 u8 reserved_at_77
[0x9];
8191 u8 command_input_inline_data
[16][0x8];
8193 u8 command_output_inline_data
[16][0x8];
8195 u8 output_mailbox_pointer_63_32
[0x20];
8197 u8 output_mailbox_pointer_31_9
[0x17];
8198 u8 reserved_at_1b7
[0x9];
8200 u8 output_length
[0x20];
8204 u8 reserved_at_1f0
[0x8];
8209 struct mlx5_ifc_cmd_out_bits
{
8211 u8 reserved_at_8
[0x18];
8215 u8 command_output
[0x20];
8218 struct mlx5_ifc_cmd_in_bits
{
8220 u8 reserved_at_10
[0x10];
8222 u8 reserved_at_20
[0x10];
8225 u8 command
[0][0x20];
8228 struct mlx5_ifc_cmd_if_box_bits
{
8229 u8 mailbox_data
[512][0x8];
8231 u8 reserved_at_1000
[0x180];
8233 u8 next_pointer_63_32
[0x20];
8235 u8 next_pointer_31_10
[0x16];
8236 u8 reserved_at_11b6
[0xa];
8238 u8 block_number
[0x20];
8240 u8 reserved_at_11e0
[0x8];
8242 u8 ctrl_signature
[0x8];
8246 struct mlx5_ifc_mtt_bits
{
8247 u8 ptag_63_32
[0x20];
8250 u8 reserved_at_38
[0x6];
8255 struct mlx5_ifc_query_wol_rol_out_bits
{
8257 u8 reserved_at_8
[0x18];
8261 u8 reserved_at_40
[0x10];
8265 u8 reserved_at_60
[0x20];
8268 struct mlx5_ifc_query_wol_rol_in_bits
{
8270 u8 reserved_at_10
[0x10];
8272 u8 reserved_at_20
[0x10];
8275 u8 reserved_at_40
[0x40];
8278 struct mlx5_ifc_set_wol_rol_out_bits
{
8280 u8 reserved_at_8
[0x18];
8284 u8 reserved_at_40
[0x40];
8287 struct mlx5_ifc_set_wol_rol_in_bits
{
8289 u8 reserved_at_10
[0x10];
8291 u8 reserved_at_20
[0x10];
8294 u8 rol_mode_valid
[0x1];
8295 u8 wol_mode_valid
[0x1];
8296 u8 reserved_at_42
[0xe];
8300 u8 reserved_at_60
[0x20];
8304 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER
= 0x0,
8305 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED
= 0x1,
8306 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC
= 0x2,
8310 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER
= 0x0,
8311 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED
= 0x1,
8312 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC
= 0x2,
8316 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR
= 0x1,
8317 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC
= 0x7,
8318 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR
= 0x8,
8319 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR
= 0x9,
8320 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR
= 0xa,
8321 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR
= 0xb,
8322 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN
= 0xc,
8323 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR
= 0xd,
8324 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV
= 0xe,
8325 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR
= 0xf,
8326 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR
= 0x10,
8329 struct mlx5_ifc_initial_seg_bits
{
8330 u8 fw_rev_minor
[0x10];
8331 u8 fw_rev_major
[0x10];
8333 u8 cmd_interface_rev
[0x10];
8334 u8 fw_rev_subminor
[0x10];
8336 u8 reserved_at_40
[0x40];
8338 u8 cmdq_phy_addr_63_32
[0x20];
8340 u8 cmdq_phy_addr_31_12
[0x14];
8341 u8 reserved_at_b4
[0x2];
8342 u8 nic_interface
[0x2];
8343 u8 log_cmdq_size
[0x4];
8344 u8 log_cmdq_stride
[0x4];
8346 u8 command_doorbell_vector
[0x20];
8348 u8 reserved_at_e0
[0xf00];
8350 u8 initializing
[0x1];
8351 u8 reserved_at_fe1
[0x4];
8352 u8 nic_interface_supported
[0x3];
8353 u8 reserved_at_fe8
[0x18];
8355 struct mlx5_ifc_health_buffer_bits health_buffer
;
8357 u8 no_dram_nic_offset
[0x20];
8359 u8 reserved_at_1220
[0x6e40];
8361 u8 reserved_at_8060
[0x1f];
8364 u8 health_syndrome
[0x8];
8365 u8 health_counter
[0x18];
8367 u8 reserved_at_80a0
[0x17fc0];
8370 struct mlx5_ifc_mtpps_reg_bits
{
8371 u8 reserved_at_0
[0xc];
8372 u8 cap_number_of_pps_pins
[0x4];
8373 u8 reserved_at_10
[0x4];
8374 u8 cap_max_num_of_pps_in_pins
[0x4];
8375 u8 reserved_at_18
[0x4];
8376 u8 cap_max_num_of_pps_out_pins
[0x4];
8378 u8 reserved_at_20
[0x24];
8379 u8 cap_pin_3_mode
[0x4];
8380 u8 reserved_at_48
[0x4];
8381 u8 cap_pin_2_mode
[0x4];
8382 u8 reserved_at_50
[0x4];
8383 u8 cap_pin_1_mode
[0x4];
8384 u8 reserved_at_58
[0x4];
8385 u8 cap_pin_0_mode
[0x4];
8387 u8 reserved_at_60
[0x4];
8388 u8 cap_pin_7_mode
[0x4];
8389 u8 reserved_at_68
[0x4];
8390 u8 cap_pin_6_mode
[0x4];
8391 u8 reserved_at_70
[0x4];
8392 u8 cap_pin_5_mode
[0x4];
8393 u8 reserved_at_78
[0x4];
8394 u8 cap_pin_4_mode
[0x4];
8396 u8 field_select
[0x20];
8397 u8 reserved_at_a0
[0x60];
8400 u8 reserved_at_101
[0xb];
8402 u8 reserved_at_110
[0x4];
8406 u8 reserved_at_120
[0x20];
8408 u8 time_stamp
[0x40];
8410 u8 out_pulse_duration
[0x10];
8411 u8 out_periodic_adjustment
[0x10];
8412 u8 enhanced_out_periodic_adjustment
[0x20];
8414 u8 reserved_at_1c0
[0x20];
8417 struct mlx5_ifc_mtppse_reg_bits
{
8418 u8 reserved_at_0
[0x18];
8421 u8 reserved_at_21
[0x1b];
8422 u8 event_generation_mode
[0x4];
8423 u8 reserved_at_40
[0x40];
8426 struct mlx5_ifc_mcqi_cap_bits
{
8427 u8 supported_info_bitmask
[0x20];
8429 u8 component_size
[0x20];
8431 u8 max_component_size
[0x20];
8433 u8 log_mcda_word_size
[0x4];
8434 u8 reserved_at_64
[0xc];
8435 u8 mcda_max_write_size
[0x10];
8438 u8 reserved_at_81
[0x1];
8439 u8 match_chip_id
[0x1];
8441 u8 check_user_timestamp
[0x1];
8442 u8 match_base_guid_mac
[0x1];
8443 u8 reserved_at_86
[0x1a];
8446 struct mlx5_ifc_mcqi_reg_bits
{
8447 u8 read_pending_component
[0x1];
8448 u8 reserved_at_1
[0xf];
8449 u8 component_index
[0x10];
8451 u8 reserved_at_20
[0x20];
8453 u8 reserved_at_40
[0x1b];
8460 u8 reserved_at_a0
[0x10];
8466 struct mlx5_ifc_mcc_reg_bits
{
8467 u8 reserved_at_0
[0x4];
8468 u8 time_elapsed_since_last_cmd
[0xc];
8469 u8 reserved_at_10
[0x8];
8470 u8 instruction
[0x8];
8472 u8 reserved_at_20
[0x10];
8473 u8 component_index
[0x10];
8475 u8 reserved_at_40
[0x8];
8476 u8 update_handle
[0x18];
8478 u8 handle_owner_type
[0x4];
8479 u8 handle_owner_host_id
[0x4];
8480 u8 reserved_at_68
[0x1];
8481 u8 control_progress
[0x7];
8483 u8 reserved_at_78
[0x4];
8484 u8 control_state
[0x4];
8486 u8 component_size
[0x20];
8488 u8 reserved_at_a0
[0x60];
8491 struct mlx5_ifc_mcda_reg_bits
{
8492 u8 reserved_at_0
[0x8];
8493 u8 update_handle
[0x18];
8497 u8 reserved_at_40
[0x10];
8500 u8 reserved_at_60
[0x20];
8505 union mlx5_ifc_ports_control_registers_document_bits
{
8506 struct mlx5_ifc_bufferx_reg_bits bufferx_reg
;
8507 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
8508 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
8509 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
8510 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
8511 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
8512 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
8513 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
8514 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping
;
8515 struct mlx5_ifc_pamp_reg_bits pamp_reg
;
8516 struct mlx5_ifc_paos_reg_bits paos_reg
;
8517 struct mlx5_ifc_pcap_reg_bits pcap_reg
;
8518 struct mlx5_ifc_peir_reg_bits peir_reg
;
8519 struct mlx5_ifc_pelc_reg_bits pelc_reg
;
8520 struct mlx5_ifc_pfcc_reg_bits pfcc_reg
;
8521 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
8522 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
8523 struct mlx5_ifc_pifr_reg_bits pifr_reg
;
8524 struct mlx5_ifc_pipg_reg_bits pipg_reg
;
8525 struct mlx5_ifc_plbf_reg_bits plbf_reg
;
8526 struct mlx5_ifc_plib_reg_bits plib_reg
;
8527 struct mlx5_ifc_plpc_reg_bits plpc_reg
;
8528 struct mlx5_ifc_pmaos_reg_bits pmaos_reg
;
8529 struct mlx5_ifc_pmlp_reg_bits pmlp_reg
;
8530 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg
;
8531 struct mlx5_ifc_pmpc_reg_bits pmpc_reg
;
8532 struct mlx5_ifc_pmpe_reg_bits pmpe_reg
;
8533 struct mlx5_ifc_pmpr_reg_bits pmpr_reg
;
8534 struct mlx5_ifc_pmtu_reg_bits pmtu_reg
;
8535 struct mlx5_ifc_ppad_reg_bits ppad_reg
;
8536 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg
;
8537 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg
;
8538 struct mlx5_ifc_pplm_reg_bits pplm_reg
;
8539 struct mlx5_ifc_pplr_reg_bits pplr_reg
;
8540 struct mlx5_ifc_ppsc_reg_bits ppsc_reg
;
8541 struct mlx5_ifc_pqdr_reg_bits pqdr_reg
;
8542 struct mlx5_ifc_pspa_reg_bits pspa_reg
;
8543 struct mlx5_ifc_ptas_reg_bits ptas_reg
;
8544 struct mlx5_ifc_ptys_reg_bits ptys_reg
;
8545 struct mlx5_ifc_mlcr_reg_bits mlcr_reg
;
8546 struct mlx5_ifc_pude_reg_bits pude_reg
;
8547 struct mlx5_ifc_pvlc_reg_bits pvlc_reg
;
8548 struct mlx5_ifc_slrg_reg_bits slrg_reg
;
8549 struct mlx5_ifc_sltp_reg_bits sltp_reg
;
8550 struct mlx5_ifc_mtpps_reg_bits mtpps_reg
;
8551 struct mlx5_ifc_mtppse_reg_bits mtppse_reg
;
8552 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg
;
8553 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits
;
8554 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits
;
8555 struct mlx5_ifc_mcqi_reg_bits mcqi_reg
;
8556 struct mlx5_ifc_mcc_reg_bits mcc_reg
;
8557 struct mlx5_ifc_mcda_reg_bits mcda_reg
;
8558 u8 reserved_at_0
[0x60e0];
8561 union mlx5_ifc_debug_enhancements_document_bits
{
8562 struct mlx5_ifc_health_buffer_bits health_buffer
;
8563 u8 reserved_at_0
[0x200];
8566 union mlx5_ifc_uplink_pci_interface_document_bits
{
8567 struct mlx5_ifc_initial_seg_bits initial_seg
;
8568 u8 reserved_at_0
[0x20060];
8571 struct mlx5_ifc_set_flow_table_root_out_bits
{
8573 u8 reserved_at_8
[0x18];
8577 u8 reserved_at_40
[0x40];
8580 struct mlx5_ifc_set_flow_table_root_in_bits
{
8582 u8 reserved_at_10
[0x10];
8584 u8 reserved_at_20
[0x10];
8587 u8 other_vport
[0x1];
8588 u8 reserved_at_41
[0xf];
8589 u8 vport_number
[0x10];
8591 u8 reserved_at_60
[0x20];
8594 u8 reserved_at_88
[0x18];
8596 u8 reserved_at_a0
[0x8];
8599 u8 reserved_at_c0
[0x8];
8600 u8 underlay_qpn
[0x18];
8601 u8 reserved_at_e0
[0x120];
8605 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID
= (1UL << 0),
8606 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID
= (1UL << 15),
8609 struct mlx5_ifc_modify_flow_table_out_bits
{
8611 u8 reserved_at_8
[0x18];
8615 u8 reserved_at_40
[0x40];
8618 struct mlx5_ifc_modify_flow_table_in_bits
{
8620 u8 reserved_at_10
[0x10];
8622 u8 reserved_at_20
[0x10];
8625 u8 other_vport
[0x1];
8626 u8 reserved_at_41
[0xf];
8627 u8 vport_number
[0x10];
8629 u8 reserved_at_60
[0x10];
8630 u8 modify_field_select
[0x10];
8633 u8 reserved_at_88
[0x18];
8635 u8 reserved_at_a0
[0x8];
8638 struct mlx5_ifc_flow_table_context_bits flow_table_context
;
8641 struct mlx5_ifc_ets_tcn_config_reg_bits
{
8645 u8 reserved_at_3
[0x9];
8647 u8 reserved_at_10
[0x9];
8648 u8 bw_allocation
[0x7];
8650 u8 reserved_at_20
[0xc];
8651 u8 max_bw_units
[0x4];
8652 u8 reserved_at_30
[0x8];
8653 u8 max_bw_value
[0x8];
8656 struct mlx5_ifc_ets_global_config_reg_bits
{
8657 u8 reserved_at_0
[0x2];
8659 u8 reserved_at_3
[0x1d];
8661 u8 reserved_at_20
[0xc];
8662 u8 max_bw_units
[0x4];
8663 u8 reserved_at_30
[0x8];
8664 u8 max_bw_value
[0x8];
8667 struct mlx5_ifc_qetc_reg_bits
{
8668 u8 reserved_at_0
[0x8];
8669 u8 port_number
[0x8];
8670 u8 reserved_at_10
[0x30];
8672 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration
[0x8];
8673 struct mlx5_ifc_ets_global_config_reg_bits global_configuration
;
8676 struct mlx5_ifc_qpdpm_dscp_reg_bits
{
8678 u8 reserved_at_01
[0x0b];
8682 struct mlx5_ifc_qpdpm_reg_bits
{
8683 u8 reserved_at_0
[0x8];
8685 u8 reserved_at_10
[0x10];
8686 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp
[64];
8689 struct mlx5_ifc_qpts_reg_bits
{
8690 u8 reserved_at_0
[0x8];
8692 u8 reserved_at_10
[0x2d];
8693 u8 trust_state
[0x3];
8696 struct mlx5_ifc_qtct_reg_bits
{
8697 u8 reserved_at_0
[0x8];
8698 u8 port_number
[0x8];
8699 u8 reserved_at_10
[0xd];
8702 u8 reserved_at_20
[0x1d];
8706 struct mlx5_ifc_mcia_reg_bits
{
8708 u8 reserved_at_1
[0x7];
8710 u8 reserved_at_10
[0x8];
8713 u8 i2c_device_address
[0x8];
8714 u8 page_number
[0x8];
8715 u8 device_address
[0x10];
8717 u8 reserved_at_40
[0x10];
8720 u8 reserved_at_60
[0x20];
8736 struct mlx5_ifc_dcbx_param_bits
{
8737 u8 dcbx_cee_cap
[0x1];
8738 u8 dcbx_ieee_cap
[0x1];
8739 u8 dcbx_standby_cap
[0x1];
8740 u8 reserved_at_0
[0x5];
8741 u8 port_number
[0x8];
8742 u8 reserved_at_10
[0xa];
8743 u8 max_application_table_size
[6];
8744 u8 reserved_at_20
[0x15];
8745 u8 version_oper
[0x3];
8746 u8 reserved_at_38
[5];
8747 u8 version_admin
[0x3];
8748 u8 willing_admin
[0x1];
8749 u8 reserved_at_41
[0x3];
8750 u8 pfc_cap_oper
[0x4];
8751 u8 reserved_at_48
[0x4];
8752 u8 pfc_cap_admin
[0x4];
8753 u8 reserved_at_50
[0x4];
8754 u8 num_of_tc_oper
[0x4];
8755 u8 reserved_at_58
[0x4];
8756 u8 num_of_tc_admin
[0x4];
8757 u8 remote_willing
[0x1];
8758 u8 reserved_at_61
[3];
8759 u8 remote_pfc_cap
[4];
8760 u8 reserved_at_68
[0x14];
8761 u8 remote_num_of_tc
[0x4];
8762 u8 reserved_at_80
[0x18];
8764 u8 reserved_at_a0
[0x160];
8767 struct mlx5_ifc_lagc_bits
{
8768 u8 reserved_at_0
[0x1d];
8771 u8 reserved_at_20
[0x14];
8772 u8 tx_remap_affinity_2
[0x4];
8773 u8 reserved_at_38
[0x4];
8774 u8 tx_remap_affinity_1
[0x4];
8777 struct mlx5_ifc_create_lag_out_bits
{
8779 u8 reserved_at_8
[0x18];
8783 u8 reserved_at_40
[0x40];
8786 struct mlx5_ifc_create_lag_in_bits
{
8788 u8 reserved_at_10
[0x10];
8790 u8 reserved_at_20
[0x10];
8793 struct mlx5_ifc_lagc_bits ctx
;
8796 struct mlx5_ifc_modify_lag_out_bits
{
8798 u8 reserved_at_8
[0x18];
8802 u8 reserved_at_40
[0x40];
8805 struct mlx5_ifc_modify_lag_in_bits
{
8807 u8 reserved_at_10
[0x10];
8809 u8 reserved_at_20
[0x10];
8812 u8 reserved_at_40
[0x20];
8813 u8 field_select
[0x20];
8815 struct mlx5_ifc_lagc_bits ctx
;
8818 struct mlx5_ifc_query_lag_out_bits
{
8820 u8 reserved_at_8
[0x18];
8824 u8 reserved_at_40
[0x40];
8826 struct mlx5_ifc_lagc_bits ctx
;
8829 struct mlx5_ifc_query_lag_in_bits
{
8831 u8 reserved_at_10
[0x10];
8833 u8 reserved_at_20
[0x10];
8836 u8 reserved_at_40
[0x40];
8839 struct mlx5_ifc_destroy_lag_out_bits
{
8841 u8 reserved_at_8
[0x18];
8845 u8 reserved_at_40
[0x40];
8848 struct mlx5_ifc_destroy_lag_in_bits
{
8850 u8 reserved_at_10
[0x10];
8852 u8 reserved_at_20
[0x10];
8855 u8 reserved_at_40
[0x40];
8858 struct mlx5_ifc_create_vport_lag_out_bits
{
8860 u8 reserved_at_8
[0x18];
8864 u8 reserved_at_40
[0x40];
8867 struct mlx5_ifc_create_vport_lag_in_bits
{
8869 u8 reserved_at_10
[0x10];
8871 u8 reserved_at_20
[0x10];
8874 u8 reserved_at_40
[0x40];
8877 struct mlx5_ifc_destroy_vport_lag_out_bits
{
8879 u8 reserved_at_8
[0x18];
8883 u8 reserved_at_40
[0x40];
8886 struct mlx5_ifc_destroy_vport_lag_in_bits
{
8888 u8 reserved_at_10
[0x10];
8890 u8 reserved_at_20
[0x10];
8893 u8 reserved_at_40
[0x40];
8896 struct mlx5_ifc_alloc_memic_in_bits
{
8898 u8 reserved_at_10
[0x10];
8900 u8 reserved_at_20
[0x10];
8903 u8 reserved_at_30
[0x20];
8905 u8 reserved_at_40
[0x18];
8906 u8 log_memic_addr_alignment
[0x8];
8908 u8 range_start_addr
[0x40];
8910 u8 range_size
[0x20];
8912 u8 memic_size
[0x20];
8915 struct mlx5_ifc_alloc_memic_out_bits
{
8917 u8 reserved_at_8
[0x18];
8921 u8 memic_start_addr
[0x40];
8924 struct mlx5_ifc_dealloc_memic_in_bits
{
8926 u8 reserved_at_10
[0x10];
8928 u8 reserved_at_20
[0x10];
8931 u8 reserved_at_40
[0x40];
8933 u8 memic_start_addr
[0x40];
8935 u8 memic_size
[0x20];
8937 u8 reserved_at_e0
[0x20];
8940 struct mlx5_ifc_dealloc_memic_out_bits
{
8942 u8 reserved_at_8
[0x18];
8946 u8 reserved_at_40
[0x40];
8949 #endif /* MLX5_IFC_H */