2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS
= 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED
= 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED
= 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED
= 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED
= 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT
= 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED
= 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION
= 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR
= 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR
= 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED
= 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT
= 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR
= 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR
= 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR
= 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR
= 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE
= 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT
= 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT
= 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT
= 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT
= 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT
= 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION
= 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST
= 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR
= 0x20,
66 MLX5_MODIFY_TIR_BITMASK_LRO
= 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE
= 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH
= 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN
= 0x3
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
= 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
= 0x3,
78 MLX5_CMD_OP_QUERY_HCA_CAP
= 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER
= 0x101,
80 MLX5_CMD_OP_INIT_HCA
= 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA
= 0x103,
82 MLX5_CMD_OP_ENABLE_HCA
= 0x104,
83 MLX5_CMD_OP_DISABLE_HCA
= 0x105,
84 MLX5_CMD_OP_QUERY_PAGES
= 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES
= 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP
= 0x109,
87 MLX5_CMD_OP_QUERY_ISSI
= 0x10a,
88 MLX5_CMD_OP_SET_ISSI
= 0x10b,
89 MLX5_CMD_OP_SET_DRIVER_VERSION
= 0x10d,
90 MLX5_CMD_OP_CREATE_MKEY
= 0x200,
91 MLX5_CMD_OP_QUERY_MKEY
= 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY
= 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS
= 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME
= 0x204,
95 MLX5_CMD_OP_CREATE_EQ
= 0x301,
96 MLX5_CMD_OP_DESTROY_EQ
= 0x302,
97 MLX5_CMD_OP_QUERY_EQ
= 0x303,
98 MLX5_CMD_OP_GEN_EQE
= 0x304,
99 MLX5_CMD_OP_CREATE_CQ
= 0x400,
100 MLX5_CMD_OP_DESTROY_CQ
= 0x401,
101 MLX5_CMD_OP_QUERY_CQ
= 0x402,
102 MLX5_CMD_OP_MODIFY_CQ
= 0x403,
103 MLX5_CMD_OP_CREATE_QP
= 0x500,
104 MLX5_CMD_OP_DESTROY_QP
= 0x501,
105 MLX5_CMD_OP_RST2INIT_QP
= 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP
= 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP
= 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP
= 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP
= 0x506,
110 MLX5_CMD_OP_2ERR_QP
= 0x507,
111 MLX5_CMD_OP_2RST_QP
= 0x50a,
112 MLX5_CMD_OP_QUERY_QP
= 0x50b,
113 MLX5_CMD_OP_SQD_RTS_QP
= 0x50c,
114 MLX5_CMD_OP_INIT2INIT_QP
= 0x50e,
115 MLX5_CMD_OP_CREATE_PSV
= 0x600,
116 MLX5_CMD_OP_DESTROY_PSV
= 0x601,
117 MLX5_CMD_OP_CREATE_SRQ
= 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ
= 0x701,
119 MLX5_CMD_OP_QUERY_SRQ
= 0x702,
120 MLX5_CMD_OP_ARM_RQ
= 0x703,
121 MLX5_CMD_OP_CREATE_XRC_SRQ
= 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ
= 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ
= 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ
= 0x708,
125 MLX5_CMD_OP_CREATE_DCT
= 0x710,
126 MLX5_CMD_OP_DESTROY_DCT
= 0x711,
127 MLX5_CMD_OP_DRAIN_DCT
= 0x712,
128 MLX5_CMD_OP_QUERY_DCT
= 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION
= 0x714,
130 MLX5_CMD_OP_CREATE_XRQ
= 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ
= 0x718,
132 MLX5_CMD_OP_QUERY_XRQ
= 0x719,
133 MLX5_CMD_OP_ARM_XRQ
= 0x71a,
134 MLX5_CMD_OP_QUERY_VPORT_STATE
= 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE
= 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT
= 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT
= 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT
= 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT
= 0x755,
140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS
= 0x760,
141 MLX5_CMD_OP_SET_ROCE_ADDRESS
= 0x761,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT
= 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT
= 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID
= 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY
= 0x765,
146 MLX5_CMD_OP_QUERY_VPORT_COUNTER
= 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER
= 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER
= 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER
= 0x773,
150 MLX5_CMD_OP_SET_RATE_LIMIT
= 0x780,
151 MLX5_CMD_OP_QUERY_RATE_LIMIT
= 0x781,
152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT
= 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT
= 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT
= 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT
= 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT
= 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT
= 0x787,
158 MLX5_CMD_OP_ALLOC_PD
= 0x800,
159 MLX5_CMD_OP_DEALLOC_PD
= 0x801,
160 MLX5_CMD_OP_ALLOC_UAR
= 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR
= 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION
= 0x804,
163 MLX5_CMD_OP_ACCESS_REG
= 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG
= 0x806,
165 MLX5_CMD_OP_DETACH_FROM_MCG
= 0x807,
166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG
= 0x80a,
167 MLX5_CMD_OP_MAD_IFC
= 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX
= 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX
= 0x80c,
170 MLX5_CMD_OP_NOP
= 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD
= 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD
= 0x80f,
173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN
= 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN
= 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS
= 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS
= 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS
= 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS
= 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS
= 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT
= 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT
= 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY
= 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY
= 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY
= 0x82b,
185 MLX5_CMD_OP_SET_WOL_ROL
= 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL
= 0x831,
187 MLX5_CMD_OP_CREATE_LAG
= 0x840,
188 MLX5_CMD_OP_MODIFY_LAG
= 0x841,
189 MLX5_CMD_OP_QUERY_LAG
= 0x842,
190 MLX5_CMD_OP_DESTROY_LAG
= 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG
= 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG
= 0x845,
193 MLX5_CMD_OP_CREATE_TIR
= 0x900,
194 MLX5_CMD_OP_MODIFY_TIR
= 0x901,
195 MLX5_CMD_OP_DESTROY_TIR
= 0x902,
196 MLX5_CMD_OP_QUERY_TIR
= 0x903,
197 MLX5_CMD_OP_CREATE_SQ
= 0x904,
198 MLX5_CMD_OP_MODIFY_SQ
= 0x905,
199 MLX5_CMD_OP_DESTROY_SQ
= 0x906,
200 MLX5_CMD_OP_QUERY_SQ
= 0x907,
201 MLX5_CMD_OP_CREATE_RQ
= 0x908,
202 MLX5_CMD_OP_MODIFY_RQ
= 0x909,
203 MLX5_CMD_OP_DESTROY_RQ
= 0x90a,
204 MLX5_CMD_OP_QUERY_RQ
= 0x90b,
205 MLX5_CMD_OP_CREATE_RMP
= 0x90c,
206 MLX5_CMD_OP_MODIFY_RMP
= 0x90d,
207 MLX5_CMD_OP_DESTROY_RMP
= 0x90e,
208 MLX5_CMD_OP_QUERY_RMP
= 0x90f,
209 MLX5_CMD_OP_CREATE_TIS
= 0x912,
210 MLX5_CMD_OP_MODIFY_TIS
= 0x913,
211 MLX5_CMD_OP_DESTROY_TIS
= 0x914,
212 MLX5_CMD_OP_QUERY_TIS
= 0x915,
213 MLX5_CMD_OP_CREATE_RQT
= 0x916,
214 MLX5_CMD_OP_MODIFY_RQT
= 0x917,
215 MLX5_CMD_OP_DESTROY_RQT
= 0x918,
216 MLX5_CMD_OP_QUERY_RQT
= 0x919,
217 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT
= 0x92f,
218 MLX5_CMD_OP_CREATE_FLOW_TABLE
= 0x930,
219 MLX5_CMD_OP_DESTROY_FLOW_TABLE
= 0x931,
220 MLX5_CMD_OP_QUERY_FLOW_TABLE
= 0x932,
221 MLX5_CMD_OP_CREATE_FLOW_GROUP
= 0x933,
222 MLX5_CMD_OP_DESTROY_FLOW_GROUP
= 0x934,
223 MLX5_CMD_OP_QUERY_FLOW_GROUP
= 0x935,
224 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY
= 0x936,
225 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY
= 0x937,
226 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY
= 0x938,
227 MLX5_CMD_OP_ALLOC_FLOW_COUNTER
= 0x939,
228 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER
= 0x93a,
229 MLX5_CMD_OP_QUERY_FLOW_COUNTER
= 0x93b,
230 MLX5_CMD_OP_MODIFY_FLOW_TABLE
= 0x93c,
231 MLX5_CMD_OP_ALLOC_ENCAP_HEADER
= 0x93d,
232 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER
= 0x93e,
233 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT
= 0x940,
234 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT
= 0x941,
235 MLX5_CMD_OP_FPGA_CREATE_QP
= 0x960,
236 MLX5_CMD_OP_FPGA_MODIFY_QP
= 0x961,
237 MLX5_CMD_OP_FPGA_QUERY_QP
= 0x962,
238 MLX5_CMD_OP_FPGA_DESTROY_QP
= 0x963,
239 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS
= 0x964,
243 struct mlx5_ifc_flow_table_fields_supported_bits
{
246 u8 outer_ether_type
[0x1];
247 u8 outer_ip_version
[0x1];
248 u8 outer_first_prio
[0x1];
249 u8 outer_first_cfi
[0x1];
250 u8 outer_first_vid
[0x1];
251 u8 outer_ipv4_ttl
[0x1];
252 u8 outer_second_prio
[0x1];
253 u8 outer_second_cfi
[0x1];
254 u8 outer_second_vid
[0x1];
255 u8 reserved_at_b
[0x1];
259 u8 outer_ip_protocol
[0x1];
260 u8 outer_ip_ecn
[0x1];
261 u8 outer_ip_dscp
[0x1];
262 u8 outer_udp_sport
[0x1];
263 u8 outer_udp_dport
[0x1];
264 u8 outer_tcp_sport
[0x1];
265 u8 outer_tcp_dport
[0x1];
266 u8 outer_tcp_flags
[0x1];
267 u8 outer_gre_protocol
[0x1];
268 u8 outer_gre_key
[0x1];
269 u8 outer_vxlan_vni
[0x1];
270 u8 reserved_at_1a
[0x5];
271 u8 source_eswitch_port
[0x1];
275 u8 inner_ether_type
[0x1];
276 u8 inner_ip_version
[0x1];
277 u8 inner_first_prio
[0x1];
278 u8 inner_first_cfi
[0x1];
279 u8 inner_first_vid
[0x1];
280 u8 reserved_at_27
[0x1];
281 u8 inner_second_prio
[0x1];
282 u8 inner_second_cfi
[0x1];
283 u8 inner_second_vid
[0x1];
284 u8 reserved_at_2b
[0x1];
288 u8 inner_ip_protocol
[0x1];
289 u8 inner_ip_ecn
[0x1];
290 u8 inner_ip_dscp
[0x1];
291 u8 inner_udp_sport
[0x1];
292 u8 inner_udp_dport
[0x1];
293 u8 inner_tcp_sport
[0x1];
294 u8 inner_tcp_dport
[0x1];
295 u8 inner_tcp_flags
[0x1];
296 u8 reserved_at_37
[0x9];
298 u8 reserved_at_40
[0x40];
301 struct mlx5_ifc_flow_table_prop_layout_bits
{
303 u8 reserved_at_1
[0x1];
304 u8 flow_counter
[0x1];
305 u8 flow_modify_en
[0x1];
307 u8 identified_miss_table_mode
[0x1];
308 u8 flow_table_modify
[0x1];
311 u8 reserved_at_9
[0x17];
313 u8 reserved_at_20
[0x2];
314 u8 log_max_ft_size
[0x6];
315 u8 log_max_modify_header_context
[0x8];
316 u8 max_modify_header_actions
[0x8];
317 u8 max_ft_level
[0x8];
319 u8 reserved_at_40
[0x20];
321 u8 reserved_at_60
[0x18];
322 u8 log_max_ft_num
[0x8];
324 u8 reserved_at_80
[0x18];
325 u8 log_max_destination
[0x8];
327 u8 reserved_at_a0
[0x18];
328 u8 log_max_flow
[0x8];
330 u8 reserved_at_c0
[0x40];
332 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support
;
334 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support
;
337 struct mlx5_ifc_odp_per_transport_service_cap_bits
{
344 u8 reserved_at_6
[0x1a];
347 struct mlx5_ifc_ipv4_layout_bits
{
348 u8 reserved_at_0
[0x60];
353 struct mlx5_ifc_ipv6_layout_bits
{
357 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits
{
358 struct mlx5_ifc_ipv6_layout_bits ipv6_layout
;
359 struct mlx5_ifc_ipv4_layout_bits ipv4_layout
;
360 u8 reserved_at_0
[0x80];
363 struct mlx5_ifc_fte_match_set_lyr_2_4_bits
{
388 u8 reserved_at_c0
[0x18];
389 u8 ttl_hoplimit
[0x8];
394 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6
;
396 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6
;
399 struct mlx5_ifc_fte_match_set_misc_bits
{
400 u8 reserved_at_0
[0x8];
403 u8 reserved_at_20
[0x10];
404 u8 source_port
[0x10];
406 u8 outer_second_prio
[0x3];
407 u8 outer_second_cfi
[0x1];
408 u8 outer_second_vid
[0xc];
409 u8 inner_second_prio
[0x3];
410 u8 inner_second_cfi
[0x1];
411 u8 inner_second_vid
[0xc];
413 u8 outer_second_cvlan_tag
[0x1];
414 u8 inner_second_cvlan_tag
[0x1];
415 u8 outer_second_svlan_tag
[0x1];
416 u8 inner_second_svlan_tag
[0x1];
417 u8 reserved_at_64
[0xc];
418 u8 gre_protocol
[0x10];
424 u8 reserved_at_b8
[0x8];
426 u8 reserved_at_c0
[0x20];
428 u8 reserved_at_e0
[0xc];
429 u8 outer_ipv6_flow_label
[0x14];
431 u8 reserved_at_100
[0xc];
432 u8 inner_ipv6_flow_label
[0x14];
434 u8 reserved_at_120
[0xe0];
437 struct mlx5_ifc_cmd_pas_bits
{
441 u8 reserved_at_34
[0xc];
444 struct mlx5_ifc_uint64_bits
{
451 MLX5_ADS_STAT_RATE_NO_LIMIT
= 0x0,
452 MLX5_ADS_STAT_RATE_2_5GBPS
= 0x7,
453 MLX5_ADS_STAT_RATE_10GBPS
= 0x8,
454 MLX5_ADS_STAT_RATE_30GBPS
= 0x9,
455 MLX5_ADS_STAT_RATE_5GBPS
= 0xa,
456 MLX5_ADS_STAT_RATE_20GBPS
= 0xb,
457 MLX5_ADS_STAT_RATE_40GBPS
= 0xc,
458 MLX5_ADS_STAT_RATE_60GBPS
= 0xd,
459 MLX5_ADS_STAT_RATE_80GBPS
= 0xe,
460 MLX5_ADS_STAT_RATE_120GBPS
= 0xf,
463 struct mlx5_ifc_ads_bits
{
466 u8 reserved_at_2
[0xe];
469 u8 reserved_at_20
[0x8];
475 u8 reserved_at_45
[0x3];
476 u8 src_addr_index
[0x8];
477 u8 reserved_at_50
[0x4];
481 u8 reserved_at_60
[0x4];
485 u8 rgid_rip
[16][0x8];
487 u8 reserved_at_100
[0x4];
490 u8 reserved_at_106
[0x1];
505 struct mlx5_ifc_flow_table_nic_cap_bits
{
506 u8 nic_rx_multi_path_tirs
[0x1];
507 u8 nic_rx_multi_path_tirs_fts
[0x1];
508 u8 allow_sniffer_and_nic_rx_shared_tir
[0x1];
509 u8 reserved_at_3
[0x1fd];
511 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive
;
513 u8 reserved_at_400
[0x200];
515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer
;
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit
;
519 u8 reserved_at_a00
[0x200];
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer
;
523 u8 reserved_at_e00
[0x7200];
526 struct mlx5_ifc_flow_table_eswitch_cap_bits
{
527 u8 reserved_at_0
[0x200];
529 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb
;
531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress
;
533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress
;
535 u8 reserved_at_800
[0x7800];
538 struct mlx5_ifc_e_switch_cap_bits
{
539 u8 vport_svlan_strip
[0x1];
540 u8 vport_cvlan_strip
[0x1];
541 u8 vport_svlan_insert
[0x1];
542 u8 vport_cvlan_insert_if_not_exist
[0x1];
543 u8 vport_cvlan_insert_overwrite
[0x1];
544 u8 reserved_at_5
[0x19];
545 u8 nic_vport_node_guid_modify
[0x1];
546 u8 nic_vport_port_guid_modify
[0x1];
548 u8 vxlan_encap_decap
[0x1];
549 u8 nvgre_encap_decap
[0x1];
550 u8 reserved_at_22
[0x9];
551 u8 log_max_encap_headers
[0x5];
553 u8 max_encap_header_size
[0xa];
555 u8 reserved_40
[0x7c0];
559 struct mlx5_ifc_qos_cap_bits
{
560 u8 packet_pacing
[0x1];
561 u8 esw_scheduling
[0x1];
562 u8 esw_bw_share
[0x1];
563 u8 esw_rate_limit
[0x1];
564 u8 reserved_at_4
[0x1c];
566 u8 reserved_at_20
[0x20];
568 u8 packet_pacing_max_rate
[0x20];
570 u8 packet_pacing_min_rate
[0x20];
572 u8 reserved_at_80
[0x10];
573 u8 packet_pacing_rate_table_size
[0x10];
575 u8 esw_element_type
[0x10];
576 u8 esw_tsar_type
[0x10];
578 u8 reserved_at_c0
[0x10];
579 u8 max_qos_para_vport
[0x10];
581 u8 max_tsar_bw_share
[0x20];
583 u8 reserved_at_100
[0x700];
586 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
{
590 u8 lro_psh_flag
[0x1];
591 u8 lro_time_stamp
[0x1];
592 u8 reserved_at_5
[0x2];
593 u8 wqe_vlan_insert
[0x1];
594 u8 self_lb_en_modifiable
[0x1];
595 u8 reserved_at_9
[0x2];
597 u8 multi_pkt_send_wqe
[0x2];
598 u8 wqe_inline_mode
[0x2];
599 u8 rss_ind_tbl_cap
[0x4];
602 u8 reserved_at_1a
[0x1];
603 u8 tunnel_lso_const_out_ip_id
[0x1];
604 u8 reserved_at_1c
[0x2];
605 u8 tunnel_statless_gre
[0x1];
606 u8 tunnel_stateless_vxlan
[0x1];
611 u8 reserved_at_23
[0x1d];
613 u8 reserved_at_40
[0x10];
614 u8 lro_min_mss_size
[0x10];
616 u8 reserved_at_60
[0x120];
618 u8 lro_timer_supported_periods
[4][0x20];
620 u8 reserved_at_200
[0x600];
623 struct mlx5_ifc_roce_cap_bits
{
625 u8 reserved_at_1
[0x1f];
627 u8 reserved_at_20
[0x60];
629 u8 reserved_at_80
[0xc];
631 u8 reserved_at_90
[0x8];
632 u8 roce_version
[0x8];
634 u8 reserved_at_a0
[0x10];
635 u8 r_roce_dest_udp_port
[0x10];
637 u8 r_roce_max_src_udp_port
[0x10];
638 u8 r_roce_min_src_udp_port
[0x10];
640 u8 reserved_at_e0
[0x10];
641 u8 roce_address_table_size
[0x10];
643 u8 reserved_at_100
[0x700];
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE
= 0x0,
648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES
= 0x2,
649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES
= 0x4,
650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES
= 0x8,
651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES
= 0x10,
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES
= 0x20,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES
= 0x40,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES
= 0x80,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES
= 0x100,
659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE
= 0x1,
660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES
= 0x2,
661 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES
= 0x4,
662 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES
= 0x8,
663 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES
= 0x10,
664 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES
= 0x20,
665 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES
= 0x40,
666 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES
= 0x80,
667 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES
= 0x100,
670 struct mlx5_ifc_atomic_caps_bits
{
671 u8 reserved_at_0
[0x40];
673 u8 atomic_req_8B_endianness_mode
[0x2];
674 u8 reserved_at_42
[0x4];
675 u8 supported_atomic_req_8B_endianness_mode_1
[0x1];
677 u8 reserved_at_47
[0x19];
679 u8 reserved_at_60
[0x20];
681 u8 reserved_at_80
[0x10];
682 u8 atomic_operations
[0x10];
684 u8 reserved_at_a0
[0x10];
685 u8 atomic_size_qp
[0x10];
687 u8 reserved_at_c0
[0x10];
688 u8 atomic_size_dc
[0x10];
690 u8 reserved_at_e0
[0x720];
693 struct mlx5_ifc_odp_cap_bits
{
694 u8 reserved_at_0
[0x40];
697 u8 reserved_at_41
[0x1f];
699 u8 reserved_at_60
[0x20];
701 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps
;
703 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps
;
705 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps
;
707 u8 reserved_at_e0
[0x720];
710 struct mlx5_ifc_calc_op
{
711 u8 reserved_at_0
[0x10];
712 u8 reserved_at_10
[0x9];
713 u8 op_swap_endianness
[0x1];
722 struct mlx5_ifc_vector_calc_cap_bits
{
724 u8 reserved_at_1
[0x1f];
725 u8 reserved_at_20
[0x8];
726 u8 max_vec_count
[0x8];
727 u8 reserved_at_30
[0xd];
728 u8 max_chunk_size
[0x3];
729 struct mlx5_ifc_calc_op calc0
;
730 struct mlx5_ifc_calc_op calc1
;
731 struct mlx5_ifc_calc_op calc2
;
732 struct mlx5_ifc_calc_op calc3
;
734 u8 reserved_at_e0
[0x720];
738 MLX5_WQ_TYPE_LINKED_LIST
= 0x0,
739 MLX5_WQ_TYPE_CYCLIC
= 0x1,
740 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
= 0x2,
744 MLX5_WQ_END_PAD_MODE_NONE
= 0x0,
745 MLX5_WQ_END_PAD_MODE_ALIGN
= 0x1,
749 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES
= 0x0,
750 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES
= 0x1,
751 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES
= 0x2,
752 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES
= 0x3,
753 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES
= 0x4,
757 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES
= 0x0,
758 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES
= 0x1,
759 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES
= 0x2,
760 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES
= 0x3,
761 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES
= 0x4,
762 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES
= 0x5,
766 MLX5_CMD_HCA_CAP_PORT_TYPE_IB
= 0x0,
767 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET
= 0x1,
771 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED
= 0x0,
772 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE
= 0x1,
773 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED
= 0x3,
777 MLX5_CAP_PORT_TYPE_IB
= 0x0,
778 MLX5_CAP_PORT_TYPE_ETH
= 0x1,
782 MLX5_CAP_UMR_FENCE_STRONG
= 0x0,
783 MLX5_CAP_UMR_FENCE_SMALL
= 0x1,
784 MLX5_CAP_UMR_FENCE_NONE
= 0x2,
787 struct mlx5_ifc_cmd_hca_cap_bits
{
788 u8 reserved_at_0
[0x80];
790 u8 log_max_srq_sz
[0x8];
791 u8 log_max_qp_sz
[0x8];
792 u8 reserved_at_90
[0xb];
795 u8 reserved_at_a0
[0xb];
797 u8 reserved_at_b0
[0x10];
799 u8 reserved_at_c0
[0x8];
800 u8 log_max_cq_sz
[0x8];
801 u8 reserved_at_d0
[0xb];
804 u8 log_max_eq_sz
[0x8];
805 u8 reserved_at_e8
[0x2];
806 u8 log_max_mkey
[0x6];
807 u8 reserved_at_f0
[0xc];
810 u8 max_indirection
[0x8];
811 u8 fixed_buffer_size
[0x1];
812 u8 log_max_mrw_sz
[0x7];
813 u8 force_teardown
[0x1];
814 u8 reserved_at_111
[0x1];
815 u8 log_max_bsf_list_size
[0x6];
816 u8 umr_extended_translation_offset
[0x1];
818 u8 log_max_klm_list_size
[0x6];
820 u8 reserved_at_120
[0xa];
821 u8 log_max_ra_req_dc
[0x6];
822 u8 reserved_at_130
[0xa];
823 u8 log_max_ra_res_dc
[0x6];
825 u8 reserved_at_140
[0xa];
826 u8 log_max_ra_req_qp
[0x6];
827 u8 reserved_at_150
[0xa];
828 u8 log_max_ra_res_qp
[0x6];
831 u8 cc_query_allowed
[0x1];
832 u8 cc_modify_allowed
[0x1];
834 u8 cache_line_128byte
[0x1];
835 u8 reserved_at_165
[0xb];
836 u8 gid_table_size
[0x10];
838 u8 out_of_seq_cnt
[0x1];
839 u8 vport_counters
[0x1];
840 u8 retransmission_q_counters
[0x1];
841 u8 reserved_at_183
[0x1];
842 u8 modify_rq_counter_set_id
[0x1];
843 u8 reserved_at_185
[0x1];
845 u8 pkey_table_size
[0x10];
847 u8 vport_group_manager
[0x1];
848 u8 vhca_group_manager
[0x1];
851 u8 reserved_at_1a4
[0x1];
853 u8 nic_flow_table
[0x1];
854 u8 eswitch_flow_table
[0x1];
855 u8 early_vf_enable
[0x1];
858 u8 local_ca_ack_delay
[0x5];
859 u8 port_module_event
[0x1];
860 u8 reserved_at_1b1
[0x1];
862 u8 reserved_at_1b3
[0x1];
863 u8 disable_link_up
[0x1];
868 u8 reserved_at_1c0
[0x1];
872 u8 reserved_at_1c8
[0x4];
874 u8 reserved_at_1d0
[0x1];
876 u8 reserved_at_1d2
[0x3];
880 u8 reserved_at_1d8
[0x1];
889 u8 stat_rate_support
[0x10];
890 u8 reserved_at_1f0
[0xc];
893 u8 compact_address_vector
[0x1];
895 u8 reserved_at_202
[0x1];
896 u8 ipoib_enhanced_offloads
[0x1];
897 u8 ipoib_basic_offloads
[0x1];
898 u8 reserved_at_205
[0x5];
900 u8 reserved_at_20c
[0x3];
901 u8 drain_sigerr
[0x1];
902 u8 cmdif_checksum
[0x2];
904 u8 reserved_at_213
[0x1];
905 u8 wq_signature
[0x1];
906 u8 sctr_data_cqe
[0x1];
907 u8 reserved_at_216
[0x1];
913 u8 eth_net_offloads
[0x1];
916 u8 reserved_at_21f
[0x1];
920 u8 cq_moderation
[0x1];
921 u8 reserved_at_223
[0x3];
925 u8 reserved_at_229
[0x1];
926 u8 scqe_break_moderation
[0x1];
927 u8 cq_period_start_from_cqe
[0x1];
929 u8 reserved_at_22d
[0x1];
932 u8 umr_ptr_rlky
[0x1];
934 u8 reserved_at_232
[0x4];
937 u8 set_deth_sqpn
[0x1];
938 u8 reserved_at_239
[0x3];
945 u8 reserved_at_241
[0x9];
947 u8 reserved_at_250
[0x8];
951 u8 driver_version
[0x1];
952 u8 pad_tx_eth_packet
[0x1];
953 u8 reserved_at_263
[0x8];
954 u8 log_bf_reg_size
[0x5];
956 u8 reserved_at_270
[0xb];
958 u8 num_lag_ports
[0x4];
960 u8 reserved_at_280
[0x10];
961 u8 max_wqe_sz_sq
[0x10];
963 u8 reserved_at_2a0
[0x10];
964 u8 max_wqe_sz_rq
[0x10];
966 u8 reserved_at_2c0
[0x10];
967 u8 max_wqe_sz_sq_dc
[0x10];
969 u8 reserved_at_2e0
[0x7];
972 u8 reserved_at_300
[0x18];
975 u8 reserved_at_320
[0x3];
976 u8 log_max_transport_domain
[0x5];
977 u8 reserved_at_328
[0x3];
979 u8 reserved_at_330
[0xb];
980 u8 log_max_xrcd
[0x5];
982 u8 reserved_at_340
[0x8];
983 u8 log_max_flow_counter_bulk
[0x8];
984 u8 max_flow_counter
[0x10];
987 u8 reserved_at_360
[0x3];
989 u8 reserved_at_368
[0x3];
991 u8 reserved_at_370
[0x3];
993 u8 reserved_at_378
[0x3];
996 u8 basic_cyclic_rcv_wqe
[0x1];
997 u8 reserved_at_381
[0x2];
999 u8 reserved_at_388
[0x3];
1000 u8 log_max_rqt
[0x5];
1001 u8 reserved_at_390
[0x3];
1002 u8 log_max_rqt_size
[0x5];
1003 u8 reserved_at_398
[0x3];
1004 u8 log_max_tis_per_sq
[0x5];
1006 u8 reserved_at_3a0
[0x3];
1007 u8 log_max_stride_sz_rq
[0x5];
1008 u8 reserved_at_3a8
[0x3];
1009 u8 log_min_stride_sz_rq
[0x5];
1010 u8 reserved_at_3b0
[0x3];
1011 u8 log_max_stride_sz_sq
[0x5];
1012 u8 reserved_at_3b8
[0x3];
1013 u8 log_min_stride_sz_sq
[0x5];
1015 u8 reserved_at_3c0
[0x1b];
1016 u8 log_max_wq_sz
[0x5];
1018 u8 nic_vport_change_event
[0x1];
1019 u8 reserved_at_3e1
[0xa];
1020 u8 log_max_vlan_list
[0x5];
1021 u8 reserved_at_3f0
[0x3];
1022 u8 log_max_current_mc_list
[0x5];
1023 u8 reserved_at_3f8
[0x3];
1024 u8 log_max_current_uc_list
[0x5];
1026 u8 reserved_at_400
[0x80];
1028 u8 reserved_at_480
[0x3];
1029 u8 log_max_l2_table
[0x5];
1030 u8 reserved_at_488
[0x8];
1031 u8 log_uar_page_sz
[0x10];
1033 u8 reserved_at_4a0
[0x20];
1034 u8 device_frequency_mhz
[0x20];
1035 u8 device_frequency_khz
[0x20];
1037 u8 reserved_at_500
[0x20];
1038 u8 num_of_uars_per_page
[0x20];
1039 u8 reserved_at_540
[0x40];
1041 u8 reserved_at_580
[0x3f];
1042 u8 cqe_compression
[0x1];
1044 u8 cqe_compression_timeout
[0x10];
1045 u8 cqe_compression_max_num
[0x10];
1047 u8 reserved_at_5e0
[0x10];
1048 u8 tag_matching
[0x1];
1049 u8 rndv_offload_rc
[0x1];
1050 u8 rndv_offload_dc
[0x1];
1051 u8 log_tag_matching_list_sz
[0x5];
1052 u8 reserved_at_5f8
[0x3];
1053 u8 log_max_xrq
[0x5];
1055 u8 reserved_at_600
[0x200];
1058 enum mlx5_flow_destination_type
{
1059 MLX5_FLOW_DESTINATION_TYPE_VPORT
= 0x0,
1060 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE
= 0x1,
1061 MLX5_FLOW_DESTINATION_TYPE_TIR
= 0x2,
1063 MLX5_FLOW_DESTINATION_TYPE_COUNTER
= 0x100,
1066 struct mlx5_ifc_dest_format_struct_bits
{
1067 u8 destination_type
[0x8];
1068 u8 destination_id
[0x18];
1070 u8 reserved_at_20
[0x20];
1073 struct mlx5_ifc_flow_counter_list_bits
{
1075 u8 num_of_counters
[0xf];
1076 u8 flow_counter_id
[0x10];
1078 u8 reserved_at_20
[0x20];
1081 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits
{
1082 struct mlx5_ifc_dest_format_struct_bits dest_format_struct
;
1083 struct mlx5_ifc_flow_counter_list_bits flow_counter_list
;
1084 u8 reserved_at_0
[0x40];
1087 struct mlx5_ifc_fte_match_param_bits
{
1088 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers
;
1090 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters
;
1092 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers
;
1094 u8 reserved_at_600
[0xa00];
1098 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP
= 0x0,
1099 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP
= 0x1,
1100 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT
= 0x2,
1101 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT
= 0x3,
1102 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI
= 0x4,
1105 struct mlx5_ifc_rx_hash_field_select_bits
{
1106 u8 l3_prot_type
[0x1];
1107 u8 l4_prot_type
[0x1];
1108 u8 selected_fields
[0x1e];
1112 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST
= 0x0,
1113 MLX5_WQ_WQ_TYPE_WQ_CYCLIC
= 0x1,
1117 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE
= 0x0,
1118 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN
= 0x1,
1121 struct mlx5_ifc_wq_bits
{
1123 u8 wq_signature
[0x1];
1124 u8 end_padding_mode
[0x2];
1126 u8 reserved_at_8
[0x18];
1128 u8 hds_skip_first_sge
[0x1];
1129 u8 log2_hds_buf_size
[0x3];
1130 u8 reserved_at_24
[0x7];
1131 u8 page_offset
[0x5];
1134 u8 reserved_at_40
[0x8];
1137 u8 reserved_at_60
[0x8];
1142 u8 hw_counter
[0x20];
1144 u8 sw_counter
[0x20];
1146 u8 reserved_at_100
[0xc];
1147 u8 log_wq_stride
[0x4];
1148 u8 reserved_at_110
[0x3];
1149 u8 log_wq_pg_sz
[0x5];
1150 u8 reserved_at_118
[0x3];
1153 u8 reserved_at_120
[0x15];
1154 u8 log_wqe_num_of_strides
[0x3];
1155 u8 two_byte_shift_en
[0x1];
1156 u8 reserved_at_139
[0x4];
1157 u8 log_wqe_stride_size
[0x3];
1159 u8 reserved_at_140
[0x4c0];
1161 struct mlx5_ifc_cmd_pas_bits pas
[0];
1164 struct mlx5_ifc_rq_num_bits
{
1165 u8 reserved_at_0
[0x8];
1169 struct mlx5_ifc_mac_address_layout_bits
{
1170 u8 reserved_at_0
[0x10];
1171 u8 mac_addr_47_32
[0x10];
1173 u8 mac_addr_31_0
[0x20];
1176 struct mlx5_ifc_vlan_layout_bits
{
1177 u8 reserved_at_0
[0x14];
1180 u8 reserved_at_20
[0x20];
1183 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits
{
1184 u8 reserved_at_0
[0xa0];
1186 u8 min_time_between_cnps
[0x20];
1188 u8 reserved_at_c0
[0x12];
1190 u8 reserved_at_d8
[0x5];
1191 u8 cnp_802p_prio
[0x3];
1193 u8 reserved_at_e0
[0x720];
1196 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits
{
1197 u8 reserved_at_0
[0x60];
1199 u8 reserved_at_60
[0x4];
1200 u8 clamp_tgt_rate
[0x1];
1201 u8 reserved_at_65
[0x3];
1202 u8 clamp_tgt_rate_after_time_inc
[0x1];
1203 u8 reserved_at_69
[0x17];
1205 u8 reserved_at_80
[0x20];
1207 u8 rpg_time_reset
[0x20];
1209 u8 rpg_byte_reset
[0x20];
1211 u8 rpg_threshold
[0x20];
1213 u8 rpg_max_rate
[0x20];
1215 u8 rpg_ai_rate
[0x20];
1217 u8 rpg_hai_rate
[0x20];
1221 u8 rpg_min_dec_fac
[0x20];
1223 u8 rpg_min_rate
[0x20];
1225 u8 reserved_at_1c0
[0xe0];
1227 u8 rate_to_set_on_first_cnp
[0x20];
1231 u8 dce_tcp_rtt
[0x20];
1233 u8 rate_reduce_monitor_period
[0x20];
1235 u8 reserved_at_320
[0x20];
1237 u8 initial_alpha_value
[0x20];
1239 u8 reserved_at_360
[0x4a0];
1242 struct mlx5_ifc_cong_control_802_1qau_rp_bits
{
1243 u8 reserved_at_0
[0x80];
1245 u8 rppp_max_rps
[0x20];
1247 u8 rpg_time_reset
[0x20];
1249 u8 rpg_byte_reset
[0x20];
1251 u8 rpg_threshold
[0x20];
1253 u8 rpg_max_rate
[0x20];
1255 u8 rpg_ai_rate
[0x20];
1257 u8 rpg_hai_rate
[0x20];
1261 u8 rpg_min_dec_fac
[0x20];
1263 u8 rpg_min_rate
[0x20];
1265 u8 reserved_at_1c0
[0x640];
1269 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE
= 0x1,
1270 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET
= 0x2,
1271 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE
= 0x4,
1274 struct mlx5_ifc_resize_field_select_bits
{
1275 u8 resize_field_select
[0x20];
1279 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD
= 0x1,
1280 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT
= 0x2,
1281 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI
= 0x4,
1282 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN
= 0x8,
1285 struct mlx5_ifc_modify_field_select_bits
{
1286 u8 modify_field_select
[0x20];
1289 struct mlx5_ifc_field_select_r_roce_np_bits
{
1290 u8 field_select_r_roce_np
[0x20];
1293 struct mlx5_ifc_field_select_r_roce_rp_bits
{
1294 u8 field_select_r_roce_rp
[0x20];
1298 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS
= 0x4,
1299 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET
= 0x8,
1300 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET
= 0x10,
1301 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD
= 0x20,
1302 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE
= 0x40,
1303 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE
= 0x80,
1304 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE
= 0x100,
1305 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD
= 0x200,
1306 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC
= 0x400,
1307 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE
= 0x800,
1310 struct mlx5_ifc_field_select_802_1qau_rp_bits
{
1311 u8 field_select_8021qaurp
[0x20];
1314 struct mlx5_ifc_phys_layer_cntrs_bits
{
1315 u8 time_since_last_clear_high
[0x20];
1317 u8 time_since_last_clear_low
[0x20];
1319 u8 symbol_errors_high
[0x20];
1321 u8 symbol_errors_low
[0x20];
1323 u8 sync_headers_errors_high
[0x20];
1325 u8 sync_headers_errors_low
[0x20];
1327 u8 edpl_bip_errors_lane0_high
[0x20];
1329 u8 edpl_bip_errors_lane0_low
[0x20];
1331 u8 edpl_bip_errors_lane1_high
[0x20];
1333 u8 edpl_bip_errors_lane1_low
[0x20];
1335 u8 edpl_bip_errors_lane2_high
[0x20];
1337 u8 edpl_bip_errors_lane2_low
[0x20];
1339 u8 edpl_bip_errors_lane3_high
[0x20];
1341 u8 edpl_bip_errors_lane3_low
[0x20];
1343 u8 fc_fec_corrected_blocks_lane0_high
[0x20];
1345 u8 fc_fec_corrected_blocks_lane0_low
[0x20];
1347 u8 fc_fec_corrected_blocks_lane1_high
[0x20];
1349 u8 fc_fec_corrected_blocks_lane1_low
[0x20];
1351 u8 fc_fec_corrected_blocks_lane2_high
[0x20];
1353 u8 fc_fec_corrected_blocks_lane2_low
[0x20];
1355 u8 fc_fec_corrected_blocks_lane3_high
[0x20];
1357 u8 fc_fec_corrected_blocks_lane3_low
[0x20];
1359 u8 fc_fec_uncorrectable_blocks_lane0_high
[0x20];
1361 u8 fc_fec_uncorrectable_blocks_lane0_low
[0x20];
1363 u8 fc_fec_uncorrectable_blocks_lane1_high
[0x20];
1365 u8 fc_fec_uncorrectable_blocks_lane1_low
[0x20];
1367 u8 fc_fec_uncorrectable_blocks_lane2_high
[0x20];
1369 u8 fc_fec_uncorrectable_blocks_lane2_low
[0x20];
1371 u8 fc_fec_uncorrectable_blocks_lane3_high
[0x20];
1373 u8 fc_fec_uncorrectable_blocks_lane3_low
[0x20];
1375 u8 rs_fec_corrected_blocks_high
[0x20];
1377 u8 rs_fec_corrected_blocks_low
[0x20];
1379 u8 rs_fec_uncorrectable_blocks_high
[0x20];
1381 u8 rs_fec_uncorrectable_blocks_low
[0x20];
1383 u8 rs_fec_no_errors_blocks_high
[0x20];
1385 u8 rs_fec_no_errors_blocks_low
[0x20];
1387 u8 rs_fec_single_error_blocks_high
[0x20];
1389 u8 rs_fec_single_error_blocks_low
[0x20];
1391 u8 rs_fec_corrected_symbols_total_high
[0x20];
1393 u8 rs_fec_corrected_symbols_total_low
[0x20];
1395 u8 rs_fec_corrected_symbols_lane0_high
[0x20];
1397 u8 rs_fec_corrected_symbols_lane0_low
[0x20];
1399 u8 rs_fec_corrected_symbols_lane1_high
[0x20];
1401 u8 rs_fec_corrected_symbols_lane1_low
[0x20];
1403 u8 rs_fec_corrected_symbols_lane2_high
[0x20];
1405 u8 rs_fec_corrected_symbols_lane2_low
[0x20];
1407 u8 rs_fec_corrected_symbols_lane3_high
[0x20];
1409 u8 rs_fec_corrected_symbols_lane3_low
[0x20];
1411 u8 link_down_events
[0x20];
1413 u8 successful_recovery_events
[0x20];
1415 u8 reserved_at_640
[0x180];
1418 struct mlx5_ifc_phys_layer_statistical_cntrs_bits
{
1419 u8 time_since_last_clear_high
[0x20];
1421 u8 time_since_last_clear_low
[0x20];
1423 u8 phy_received_bits_high
[0x20];
1425 u8 phy_received_bits_low
[0x20];
1427 u8 phy_symbol_errors_high
[0x20];
1429 u8 phy_symbol_errors_low
[0x20];
1431 u8 phy_corrected_bits_high
[0x20];
1433 u8 phy_corrected_bits_low
[0x20];
1435 u8 phy_corrected_bits_lane0_high
[0x20];
1437 u8 phy_corrected_bits_lane0_low
[0x20];
1439 u8 phy_corrected_bits_lane1_high
[0x20];
1441 u8 phy_corrected_bits_lane1_low
[0x20];
1443 u8 phy_corrected_bits_lane2_high
[0x20];
1445 u8 phy_corrected_bits_lane2_low
[0x20];
1447 u8 phy_corrected_bits_lane3_high
[0x20];
1449 u8 phy_corrected_bits_lane3_low
[0x20];
1451 u8 reserved_at_200
[0x5c0];
1454 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits
{
1455 u8 symbol_error_counter
[0x10];
1457 u8 link_error_recovery_counter
[0x8];
1459 u8 link_downed_counter
[0x8];
1461 u8 port_rcv_errors
[0x10];
1463 u8 port_rcv_remote_physical_errors
[0x10];
1465 u8 port_rcv_switch_relay_errors
[0x10];
1467 u8 port_xmit_discards
[0x10];
1469 u8 port_xmit_constraint_errors
[0x8];
1471 u8 port_rcv_constraint_errors
[0x8];
1473 u8 reserved_at_70
[0x8];
1475 u8 link_overrun_errors
[0x8];
1477 u8 reserved_at_80
[0x10];
1479 u8 vl_15_dropped
[0x10];
1481 u8 reserved_at_a0
[0x80];
1483 u8 port_xmit_wait
[0x20];
1486 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits
{
1487 u8 transmit_queue_high
[0x20];
1489 u8 transmit_queue_low
[0x20];
1491 u8 reserved_at_40
[0x780];
1494 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits
{
1495 u8 rx_octets_high
[0x20];
1497 u8 rx_octets_low
[0x20];
1499 u8 reserved_at_40
[0xc0];
1501 u8 rx_frames_high
[0x20];
1503 u8 rx_frames_low
[0x20];
1505 u8 tx_octets_high
[0x20];
1507 u8 tx_octets_low
[0x20];
1509 u8 reserved_at_180
[0xc0];
1511 u8 tx_frames_high
[0x20];
1513 u8 tx_frames_low
[0x20];
1515 u8 rx_pause_high
[0x20];
1517 u8 rx_pause_low
[0x20];
1519 u8 rx_pause_duration_high
[0x20];
1521 u8 rx_pause_duration_low
[0x20];
1523 u8 tx_pause_high
[0x20];
1525 u8 tx_pause_low
[0x20];
1527 u8 tx_pause_duration_high
[0x20];
1529 u8 tx_pause_duration_low
[0x20];
1531 u8 rx_pause_transition_high
[0x20];
1533 u8 rx_pause_transition_low
[0x20];
1535 u8 reserved_at_3c0
[0x400];
1538 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits
{
1539 u8 port_transmit_wait_high
[0x20];
1541 u8 port_transmit_wait_low
[0x20];
1543 u8 reserved_at_40
[0x780];
1546 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits
{
1547 u8 dot3stats_alignment_errors_high
[0x20];
1549 u8 dot3stats_alignment_errors_low
[0x20];
1551 u8 dot3stats_fcs_errors_high
[0x20];
1553 u8 dot3stats_fcs_errors_low
[0x20];
1555 u8 dot3stats_single_collision_frames_high
[0x20];
1557 u8 dot3stats_single_collision_frames_low
[0x20];
1559 u8 dot3stats_multiple_collision_frames_high
[0x20];
1561 u8 dot3stats_multiple_collision_frames_low
[0x20];
1563 u8 dot3stats_sqe_test_errors_high
[0x20];
1565 u8 dot3stats_sqe_test_errors_low
[0x20];
1567 u8 dot3stats_deferred_transmissions_high
[0x20];
1569 u8 dot3stats_deferred_transmissions_low
[0x20];
1571 u8 dot3stats_late_collisions_high
[0x20];
1573 u8 dot3stats_late_collisions_low
[0x20];
1575 u8 dot3stats_excessive_collisions_high
[0x20];
1577 u8 dot3stats_excessive_collisions_low
[0x20];
1579 u8 dot3stats_internal_mac_transmit_errors_high
[0x20];
1581 u8 dot3stats_internal_mac_transmit_errors_low
[0x20];
1583 u8 dot3stats_carrier_sense_errors_high
[0x20];
1585 u8 dot3stats_carrier_sense_errors_low
[0x20];
1587 u8 dot3stats_frame_too_longs_high
[0x20];
1589 u8 dot3stats_frame_too_longs_low
[0x20];
1591 u8 dot3stats_internal_mac_receive_errors_high
[0x20];
1593 u8 dot3stats_internal_mac_receive_errors_low
[0x20];
1595 u8 dot3stats_symbol_errors_high
[0x20];
1597 u8 dot3stats_symbol_errors_low
[0x20];
1599 u8 dot3control_in_unknown_opcodes_high
[0x20];
1601 u8 dot3control_in_unknown_opcodes_low
[0x20];
1603 u8 dot3in_pause_frames_high
[0x20];
1605 u8 dot3in_pause_frames_low
[0x20];
1607 u8 dot3out_pause_frames_high
[0x20];
1609 u8 dot3out_pause_frames_low
[0x20];
1611 u8 reserved_at_400
[0x3c0];
1614 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits
{
1615 u8 ether_stats_drop_events_high
[0x20];
1617 u8 ether_stats_drop_events_low
[0x20];
1619 u8 ether_stats_octets_high
[0x20];
1621 u8 ether_stats_octets_low
[0x20];
1623 u8 ether_stats_pkts_high
[0x20];
1625 u8 ether_stats_pkts_low
[0x20];
1627 u8 ether_stats_broadcast_pkts_high
[0x20];
1629 u8 ether_stats_broadcast_pkts_low
[0x20];
1631 u8 ether_stats_multicast_pkts_high
[0x20];
1633 u8 ether_stats_multicast_pkts_low
[0x20];
1635 u8 ether_stats_crc_align_errors_high
[0x20];
1637 u8 ether_stats_crc_align_errors_low
[0x20];
1639 u8 ether_stats_undersize_pkts_high
[0x20];
1641 u8 ether_stats_undersize_pkts_low
[0x20];
1643 u8 ether_stats_oversize_pkts_high
[0x20];
1645 u8 ether_stats_oversize_pkts_low
[0x20];
1647 u8 ether_stats_fragments_high
[0x20];
1649 u8 ether_stats_fragments_low
[0x20];
1651 u8 ether_stats_jabbers_high
[0x20];
1653 u8 ether_stats_jabbers_low
[0x20];
1655 u8 ether_stats_collisions_high
[0x20];
1657 u8 ether_stats_collisions_low
[0x20];
1659 u8 ether_stats_pkts64octets_high
[0x20];
1661 u8 ether_stats_pkts64octets_low
[0x20];
1663 u8 ether_stats_pkts65to127octets_high
[0x20];
1665 u8 ether_stats_pkts65to127octets_low
[0x20];
1667 u8 ether_stats_pkts128to255octets_high
[0x20];
1669 u8 ether_stats_pkts128to255octets_low
[0x20];
1671 u8 ether_stats_pkts256to511octets_high
[0x20];
1673 u8 ether_stats_pkts256to511octets_low
[0x20];
1675 u8 ether_stats_pkts512to1023octets_high
[0x20];
1677 u8 ether_stats_pkts512to1023octets_low
[0x20];
1679 u8 ether_stats_pkts1024to1518octets_high
[0x20];
1681 u8 ether_stats_pkts1024to1518octets_low
[0x20];
1683 u8 ether_stats_pkts1519to2047octets_high
[0x20];
1685 u8 ether_stats_pkts1519to2047octets_low
[0x20];
1687 u8 ether_stats_pkts2048to4095octets_high
[0x20];
1689 u8 ether_stats_pkts2048to4095octets_low
[0x20];
1691 u8 ether_stats_pkts4096to8191octets_high
[0x20];
1693 u8 ether_stats_pkts4096to8191octets_low
[0x20];
1695 u8 ether_stats_pkts8192to10239octets_high
[0x20];
1697 u8 ether_stats_pkts8192to10239octets_low
[0x20];
1699 u8 reserved_at_540
[0x280];
1702 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits
{
1703 u8 if_in_octets_high
[0x20];
1705 u8 if_in_octets_low
[0x20];
1707 u8 if_in_ucast_pkts_high
[0x20];
1709 u8 if_in_ucast_pkts_low
[0x20];
1711 u8 if_in_discards_high
[0x20];
1713 u8 if_in_discards_low
[0x20];
1715 u8 if_in_errors_high
[0x20];
1717 u8 if_in_errors_low
[0x20];
1719 u8 if_in_unknown_protos_high
[0x20];
1721 u8 if_in_unknown_protos_low
[0x20];
1723 u8 if_out_octets_high
[0x20];
1725 u8 if_out_octets_low
[0x20];
1727 u8 if_out_ucast_pkts_high
[0x20];
1729 u8 if_out_ucast_pkts_low
[0x20];
1731 u8 if_out_discards_high
[0x20];
1733 u8 if_out_discards_low
[0x20];
1735 u8 if_out_errors_high
[0x20];
1737 u8 if_out_errors_low
[0x20];
1739 u8 if_in_multicast_pkts_high
[0x20];
1741 u8 if_in_multicast_pkts_low
[0x20];
1743 u8 if_in_broadcast_pkts_high
[0x20];
1745 u8 if_in_broadcast_pkts_low
[0x20];
1747 u8 if_out_multicast_pkts_high
[0x20];
1749 u8 if_out_multicast_pkts_low
[0x20];
1751 u8 if_out_broadcast_pkts_high
[0x20];
1753 u8 if_out_broadcast_pkts_low
[0x20];
1755 u8 reserved_at_340
[0x480];
1758 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits
{
1759 u8 a_frames_transmitted_ok_high
[0x20];
1761 u8 a_frames_transmitted_ok_low
[0x20];
1763 u8 a_frames_received_ok_high
[0x20];
1765 u8 a_frames_received_ok_low
[0x20];
1767 u8 a_frame_check_sequence_errors_high
[0x20];
1769 u8 a_frame_check_sequence_errors_low
[0x20];
1771 u8 a_alignment_errors_high
[0x20];
1773 u8 a_alignment_errors_low
[0x20];
1775 u8 a_octets_transmitted_ok_high
[0x20];
1777 u8 a_octets_transmitted_ok_low
[0x20];
1779 u8 a_octets_received_ok_high
[0x20];
1781 u8 a_octets_received_ok_low
[0x20];
1783 u8 a_multicast_frames_xmitted_ok_high
[0x20];
1785 u8 a_multicast_frames_xmitted_ok_low
[0x20];
1787 u8 a_broadcast_frames_xmitted_ok_high
[0x20];
1789 u8 a_broadcast_frames_xmitted_ok_low
[0x20];
1791 u8 a_multicast_frames_received_ok_high
[0x20];
1793 u8 a_multicast_frames_received_ok_low
[0x20];
1795 u8 a_broadcast_frames_received_ok_high
[0x20];
1797 u8 a_broadcast_frames_received_ok_low
[0x20];
1799 u8 a_in_range_length_errors_high
[0x20];
1801 u8 a_in_range_length_errors_low
[0x20];
1803 u8 a_out_of_range_length_field_high
[0x20];
1805 u8 a_out_of_range_length_field_low
[0x20];
1807 u8 a_frame_too_long_errors_high
[0x20];
1809 u8 a_frame_too_long_errors_low
[0x20];
1811 u8 a_symbol_error_during_carrier_high
[0x20];
1813 u8 a_symbol_error_during_carrier_low
[0x20];
1815 u8 a_mac_control_frames_transmitted_high
[0x20];
1817 u8 a_mac_control_frames_transmitted_low
[0x20];
1819 u8 a_mac_control_frames_received_high
[0x20];
1821 u8 a_mac_control_frames_received_low
[0x20];
1823 u8 a_unsupported_opcodes_received_high
[0x20];
1825 u8 a_unsupported_opcodes_received_low
[0x20];
1827 u8 a_pause_mac_ctrl_frames_received_high
[0x20];
1829 u8 a_pause_mac_ctrl_frames_received_low
[0x20];
1831 u8 a_pause_mac_ctrl_frames_transmitted_high
[0x20];
1833 u8 a_pause_mac_ctrl_frames_transmitted_low
[0x20];
1835 u8 reserved_at_4c0
[0x300];
1838 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits
{
1839 u8 life_time_counter_high
[0x20];
1841 u8 life_time_counter_low
[0x20];
1847 u8 l0_to_recovery_eieos
[0x20];
1849 u8 l0_to_recovery_ts
[0x20];
1851 u8 l0_to_recovery_framing
[0x20];
1853 u8 l0_to_recovery_retrain
[0x20];
1855 u8 crc_error_dllp
[0x20];
1857 u8 crc_error_tlp
[0x20];
1859 u8 reserved_at_140
[0x680];
1862 struct mlx5_ifc_cmd_inter_comp_event_bits
{
1863 u8 command_completion_vector
[0x20];
1865 u8 reserved_at_20
[0xc0];
1868 struct mlx5_ifc_stall_vl_event_bits
{
1869 u8 reserved_at_0
[0x18];
1871 u8 reserved_at_19
[0x3];
1874 u8 reserved_at_20
[0xa0];
1877 struct mlx5_ifc_db_bf_congestion_event_bits
{
1878 u8 event_subtype
[0x8];
1879 u8 reserved_at_8
[0x8];
1880 u8 congestion_level
[0x8];
1881 u8 reserved_at_18
[0x8];
1883 u8 reserved_at_20
[0xa0];
1886 struct mlx5_ifc_gpio_event_bits
{
1887 u8 reserved_at_0
[0x60];
1889 u8 gpio_event_hi
[0x20];
1891 u8 gpio_event_lo
[0x20];
1893 u8 reserved_at_a0
[0x40];
1896 struct mlx5_ifc_port_state_change_event_bits
{
1897 u8 reserved_at_0
[0x40];
1900 u8 reserved_at_44
[0x1c];
1902 u8 reserved_at_60
[0x80];
1905 struct mlx5_ifc_dropped_packet_logged_bits
{
1906 u8 reserved_at_0
[0xe0];
1910 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN
= 0x1,
1911 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR
= 0x2,
1914 struct mlx5_ifc_cq_error_bits
{
1915 u8 reserved_at_0
[0x8];
1918 u8 reserved_at_20
[0x20];
1920 u8 reserved_at_40
[0x18];
1923 u8 reserved_at_60
[0x80];
1926 struct mlx5_ifc_rdma_page_fault_event_bits
{
1927 u8 bytes_committed
[0x20];
1931 u8 reserved_at_40
[0x10];
1932 u8 packet_len
[0x10];
1934 u8 rdma_op_len
[0x20];
1938 u8 reserved_at_c0
[0x5];
1945 struct mlx5_ifc_wqe_associated_page_fault_event_bits
{
1946 u8 bytes_committed
[0x20];
1948 u8 reserved_at_20
[0x10];
1951 u8 reserved_at_40
[0x10];
1954 u8 reserved_at_60
[0x60];
1956 u8 reserved_at_c0
[0x5];
1963 struct mlx5_ifc_qp_events_bits
{
1964 u8 reserved_at_0
[0xa0];
1967 u8 reserved_at_a8
[0x18];
1969 u8 reserved_at_c0
[0x8];
1970 u8 qpn_rqn_sqn
[0x18];
1973 struct mlx5_ifc_dct_events_bits
{
1974 u8 reserved_at_0
[0xc0];
1976 u8 reserved_at_c0
[0x8];
1977 u8 dct_number
[0x18];
1980 struct mlx5_ifc_comp_event_bits
{
1981 u8 reserved_at_0
[0xc0];
1983 u8 reserved_at_c0
[0x8];
1988 MLX5_QPC_STATE_RST
= 0x0,
1989 MLX5_QPC_STATE_INIT
= 0x1,
1990 MLX5_QPC_STATE_RTR
= 0x2,
1991 MLX5_QPC_STATE_RTS
= 0x3,
1992 MLX5_QPC_STATE_SQER
= 0x4,
1993 MLX5_QPC_STATE_ERR
= 0x6,
1994 MLX5_QPC_STATE_SQD
= 0x7,
1995 MLX5_QPC_STATE_SUSPENDED
= 0x9,
1999 MLX5_QPC_ST_RC
= 0x0,
2000 MLX5_QPC_ST_UC
= 0x1,
2001 MLX5_QPC_ST_UD
= 0x2,
2002 MLX5_QPC_ST_XRC
= 0x3,
2003 MLX5_QPC_ST_DCI
= 0x5,
2004 MLX5_QPC_ST_QP0
= 0x7,
2005 MLX5_QPC_ST_QP1
= 0x8,
2006 MLX5_QPC_ST_RAW_DATAGRAM
= 0x9,
2007 MLX5_QPC_ST_REG_UMR
= 0xc,
2011 MLX5_QPC_PM_STATE_ARMED
= 0x0,
2012 MLX5_QPC_PM_STATE_REARM
= 0x1,
2013 MLX5_QPC_PM_STATE_RESERVED
= 0x2,
2014 MLX5_QPC_PM_STATE_MIGRATED
= 0x3,
2018 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS
= 0x0,
2019 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT
= 0x1,
2023 MLX5_QPC_MTU_256_BYTES
= 0x1,
2024 MLX5_QPC_MTU_512_BYTES
= 0x2,
2025 MLX5_QPC_MTU_1K_BYTES
= 0x3,
2026 MLX5_QPC_MTU_2K_BYTES
= 0x4,
2027 MLX5_QPC_MTU_4K_BYTES
= 0x5,
2028 MLX5_QPC_MTU_RAW_ETHERNET_QP
= 0x7,
2032 MLX5_QPC_ATOMIC_MODE_IB_SPEC
= 0x1,
2033 MLX5_QPC_ATOMIC_MODE_ONLY_8B
= 0x2,
2034 MLX5_QPC_ATOMIC_MODE_UP_TO_8B
= 0x3,
2035 MLX5_QPC_ATOMIC_MODE_UP_TO_16B
= 0x4,
2036 MLX5_QPC_ATOMIC_MODE_UP_TO_32B
= 0x5,
2037 MLX5_QPC_ATOMIC_MODE_UP_TO_64B
= 0x6,
2038 MLX5_QPC_ATOMIC_MODE_UP_TO_128B
= 0x7,
2039 MLX5_QPC_ATOMIC_MODE_UP_TO_256B
= 0x8,
2043 MLX5_QPC_CS_REQ_DISABLE
= 0x0,
2044 MLX5_QPC_CS_REQ_UP_TO_32B
= 0x11,
2045 MLX5_QPC_CS_REQ_UP_TO_64B
= 0x22,
2049 MLX5_QPC_CS_RES_DISABLE
= 0x0,
2050 MLX5_QPC_CS_RES_UP_TO_32B
= 0x1,
2051 MLX5_QPC_CS_RES_UP_TO_64B
= 0x2,
2054 struct mlx5_ifc_qpc_bits
{
2056 u8 lag_tx_port_affinity
[0x4];
2058 u8 reserved_at_10
[0x3];
2060 u8 reserved_at_15
[0x7];
2061 u8 end_padding_mode
[0x2];
2062 u8 reserved_at_1e
[0x2];
2064 u8 wq_signature
[0x1];
2065 u8 block_lb_mc
[0x1];
2066 u8 atomic_like_write_en
[0x1];
2067 u8 latency_sensitive
[0x1];
2068 u8 reserved_at_24
[0x1];
2069 u8 drain_sigerr
[0x1];
2070 u8 reserved_at_26
[0x2];
2074 u8 log_msg_max
[0x5];
2075 u8 reserved_at_48
[0x1];
2076 u8 log_rq_size
[0x4];
2077 u8 log_rq_stride
[0x3];
2079 u8 log_sq_size
[0x4];
2080 u8 reserved_at_55
[0x6];
2082 u8 ulp_stateless_offload_mode
[0x4];
2084 u8 counter_set_id
[0x8];
2087 u8 reserved_at_80
[0x8];
2088 u8 user_index
[0x18];
2090 u8 reserved_at_a0
[0x3];
2091 u8 log_page_size
[0x5];
2092 u8 remote_qpn
[0x18];
2094 struct mlx5_ifc_ads_bits primary_address_path
;
2096 struct mlx5_ifc_ads_bits secondary_address_path
;
2098 u8 log_ack_req_freq
[0x4];
2099 u8 reserved_at_384
[0x4];
2100 u8 log_sra_max
[0x3];
2101 u8 reserved_at_38b
[0x2];
2102 u8 retry_count
[0x3];
2104 u8 reserved_at_393
[0x1];
2106 u8 cur_rnr_retry
[0x3];
2107 u8 cur_retry_count
[0x3];
2108 u8 reserved_at_39b
[0x5];
2110 u8 reserved_at_3a0
[0x20];
2112 u8 reserved_at_3c0
[0x8];
2113 u8 next_send_psn
[0x18];
2115 u8 reserved_at_3e0
[0x8];
2118 u8 reserved_at_400
[0x8];
2121 u8 reserved_at_420
[0x20];
2123 u8 reserved_at_440
[0x8];
2124 u8 last_acked_psn
[0x18];
2126 u8 reserved_at_460
[0x8];
2129 u8 reserved_at_480
[0x8];
2130 u8 log_rra_max
[0x3];
2131 u8 reserved_at_48b
[0x1];
2132 u8 atomic_mode
[0x4];
2136 u8 reserved_at_493
[0x1];
2137 u8 page_offset
[0x6];
2138 u8 reserved_at_49a
[0x3];
2139 u8 cd_slave_receive
[0x1];
2140 u8 cd_slave_send
[0x1];
2143 u8 reserved_at_4a0
[0x3];
2144 u8 min_rnr_nak
[0x5];
2145 u8 next_rcv_psn
[0x18];
2147 u8 reserved_at_4c0
[0x8];
2150 u8 reserved_at_4e0
[0x8];
2157 u8 reserved_at_560
[0x5];
2159 u8 srqn_rmpn_xrqn
[0x18];
2161 u8 reserved_at_580
[0x8];
2164 u8 hw_sq_wqebb_counter
[0x10];
2165 u8 sw_sq_wqebb_counter
[0x10];
2167 u8 hw_rq_counter
[0x20];
2169 u8 sw_rq_counter
[0x20];
2171 u8 reserved_at_600
[0x20];
2173 u8 reserved_at_620
[0xf];
2178 u8 dc_access_key
[0x40];
2180 u8 reserved_at_680
[0xc0];
2183 struct mlx5_ifc_roce_addr_layout_bits
{
2184 u8 source_l3_address
[16][0x8];
2186 u8 reserved_at_80
[0x3];
2189 u8 source_mac_47_32
[0x10];
2191 u8 source_mac_31_0
[0x20];
2193 u8 reserved_at_c0
[0x14];
2194 u8 roce_l3_type
[0x4];
2195 u8 roce_version
[0x8];
2197 u8 reserved_at_e0
[0x20];
2200 union mlx5_ifc_hca_cap_union_bits
{
2201 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap
;
2202 struct mlx5_ifc_odp_cap_bits odp_cap
;
2203 struct mlx5_ifc_atomic_caps_bits atomic_caps
;
2204 struct mlx5_ifc_roce_cap_bits roce_cap
;
2205 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps
;
2206 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap
;
2207 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap
;
2208 struct mlx5_ifc_e_switch_cap_bits e_switch_cap
;
2209 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap
;
2210 struct mlx5_ifc_qos_cap_bits qos_cap
;
2211 struct mlx5_ifc_fpga_cap_bits fpga_cap
;
2212 u8 reserved_at_0
[0x8000];
2216 MLX5_FLOW_CONTEXT_ACTION_ALLOW
= 0x1,
2217 MLX5_FLOW_CONTEXT_ACTION_DROP
= 0x2,
2218 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
= 0x4,
2219 MLX5_FLOW_CONTEXT_ACTION_COUNT
= 0x8,
2220 MLX5_FLOW_CONTEXT_ACTION_ENCAP
= 0x10,
2221 MLX5_FLOW_CONTEXT_ACTION_DECAP
= 0x20,
2222 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR
= 0x40,
2225 struct mlx5_ifc_flow_context_bits
{
2226 u8 reserved_at_0
[0x20];
2230 u8 reserved_at_40
[0x8];
2233 u8 reserved_at_60
[0x10];
2236 u8 reserved_at_80
[0x8];
2237 u8 destination_list_size
[0x18];
2239 u8 reserved_at_a0
[0x8];
2240 u8 flow_counter_list_size
[0x18];
2244 u8 modify_header_id
[0x20];
2246 u8 reserved_at_100
[0x100];
2248 struct mlx5_ifc_fte_match_param_bits match_value
;
2250 u8 reserved_at_1200
[0x600];
2252 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination
[0];
2256 MLX5_XRC_SRQC_STATE_GOOD
= 0x0,
2257 MLX5_XRC_SRQC_STATE_ERROR
= 0x1,
2260 struct mlx5_ifc_xrc_srqc_bits
{
2262 u8 log_xrc_srq_size
[0x4];
2263 u8 reserved_at_8
[0x18];
2265 u8 wq_signature
[0x1];
2267 u8 reserved_at_22
[0x1];
2269 u8 basic_cyclic_rcv_wqe
[0x1];
2270 u8 log_rq_stride
[0x3];
2273 u8 page_offset
[0x6];
2274 u8 reserved_at_46
[0x2];
2277 u8 reserved_at_60
[0x20];
2279 u8 user_index_equal_xrc_srqn
[0x1];
2280 u8 reserved_at_81
[0x1];
2281 u8 log_page_size
[0x6];
2282 u8 user_index
[0x18];
2284 u8 reserved_at_a0
[0x20];
2286 u8 reserved_at_c0
[0x8];
2292 u8 reserved_at_100
[0x40];
2294 u8 db_record_addr_h
[0x20];
2296 u8 db_record_addr_l
[0x1e];
2297 u8 reserved_at_17e
[0x2];
2299 u8 reserved_at_180
[0x80];
2302 struct mlx5_ifc_traffic_counter_bits
{
2308 struct mlx5_ifc_tisc_bits
{
2309 u8 strict_lag_tx_port_affinity
[0x1];
2310 u8 reserved_at_1
[0x3];
2311 u8 lag_tx_port_affinity
[0x04];
2313 u8 reserved_at_8
[0x4];
2315 u8 reserved_at_10
[0x10];
2317 u8 reserved_at_20
[0x100];
2319 u8 reserved_at_120
[0x8];
2320 u8 transport_domain
[0x18];
2322 u8 reserved_at_140
[0x8];
2323 u8 underlay_qpn
[0x18];
2324 u8 reserved_at_160
[0x3a0];
2328 MLX5_TIRC_DISP_TYPE_DIRECT
= 0x0,
2329 MLX5_TIRC_DISP_TYPE_INDIRECT
= 0x1,
2333 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
= 0x1,
2334 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
= 0x2,
2338 MLX5_RX_HASH_FN_NONE
= 0x0,
2339 MLX5_RX_HASH_FN_INVERTED_XOR8
= 0x1,
2340 MLX5_RX_HASH_FN_TOEPLITZ
= 0x2,
2344 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_
= 0x1,
2345 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_
= 0x2,
2348 struct mlx5_ifc_tirc_bits
{
2349 u8 reserved_at_0
[0x20];
2352 u8 reserved_at_24
[0x1c];
2354 u8 reserved_at_40
[0x40];
2356 u8 reserved_at_80
[0x4];
2357 u8 lro_timeout_period_usecs
[0x10];
2358 u8 lro_enable_mask
[0x4];
2359 u8 lro_max_ip_payload_size
[0x8];
2361 u8 reserved_at_a0
[0x40];
2363 u8 reserved_at_e0
[0x8];
2364 u8 inline_rqn
[0x18];
2366 u8 rx_hash_symmetric
[0x1];
2367 u8 reserved_at_101
[0x1];
2368 u8 tunneled_offload_en
[0x1];
2369 u8 reserved_at_103
[0x5];
2370 u8 indirect_table
[0x18];
2373 u8 reserved_at_124
[0x2];
2374 u8 self_lb_block
[0x2];
2375 u8 transport_domain
[0x18];
2377 u8 rx_hash_toeplitz_key
[10][0x20];
2379 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer
;
2381 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner
;
2383 u8 reserved_at_2c0
[0x4c0];
2387 MLX5_SRQC_STATE_GOOD
= 0x0,
2388 MLX5_SRQC_STATE_ERROR
= 0x1,
2391 struct mlx5_ifc_srqc_bits
{
2393 u8 log_srq_size
[0x4];
2394 u8 reserved_at_8
[0x18];
2396 u8 wq_signature
[0x1];
2398 u8 reserved_at_22
[0x1];
2400 u8 reserved_at_24
[0x1];
2401 u8 log_rq_stride
[0x3];
2404 u8 page_offset
[0x6];
2405 u8 reserved_at_46
[0x2];
2408 u8 reserved_at_60
[0x20];
2410 u8 reserved_at_80
[0x2];
2411 u8 log_page_size
[0x6];
2412 u8 reserved_at_88
[0x18];
2414 u8 reserved_at_a0
[0x20];
2416 u8 reserved_at_c0
[0x8];
2422 u8 reserved_at_100
[0x40];
2426 u8 reserved_at_180
[0x80];
2430 MLX5_SQC_STATE_RST
= 0x0,
2431 MLX5_SQC_STATE_RDY
= 0x1,
2432 MLX5_SQC_STATE_ERR
= 0x3,
2435 struct mlx5_ifc_sqc_bits
{
2439 u8 flush_in_error_en
[0x1];
2440 u8 reserved_at_4
[0x1];
2441 u8 min_wqe_inline_mode
[0x3];
2445 u8 reserved_at_e
[0x12];
2447 u8 reserved_at_20
[0x8];
2448 u8 user_index
[0x18];
2450 u8 reserved_at_40
[0x8];
2453 u8 reserved_at_60
[0x90];
2455 u8 packet_pacing_rate_limit_index
[0x10];
2456 u8 tis_lst_sz
[0x10];
2457 u8 reserved_at_110
[0x10];
2459 u8 reserved_at_120
[0x40];
2461 u8 reserved_at_160
[0x8];
2464 struct mlx5_ifc_wq_bits wq
;
2468 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR
= 0x0,
2469 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT
= 0x1,
2470 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC
= 0x2,
2471 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC
= 0x3,
2474 struct mlx5_ifc_scheduling_context_bits
{
2475 u8 element_type
[0x8];
2476 u8 reserved_at_8
[0x18];
2478 u8 element_attributes
[0x20];
2480 u8 parent_element_id
[0x20];
2482 u8 reserved_at_60
[0x40];
2486 u8 max_average_bw
[0x20];
2488 u8 reserved_at_e0
[0x120];
2491 struct mlx5_ifc_rqtc_bits
{
2492 u8 reserved_at_0
[0xa0];
2494 u8 reserved_at_a0
[0x10];
2495 u8 rqt_max_size
[0x10];
2497 u8 reserved_at_c0
[0x10];
2498 u8 rqt_actual_size
[0x10];
2500 u8 reserved_at_e0
[0x6a0];
2502 struct mlx5_ifc_rq_num_bits rq_num
[0];
2506 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
= 0x0,
2507 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP
= 0x1,
2511 MLX5_RQC_STATE_RST
= 0x0,
2512 MLX5_RQC_STATE_RDY
= 0x1,
2513 MLX5_RQC_STATE_ERR
= 0x3,
2516 struct mlx5_ifc_rqc_bits
{
2518 u8 reserved_at_1
[0x1];
2519 u8 scatter_fcs
[0x1];
2521 u8 mem_rq_type
[0x4];
2523 u8 reserved_at_c
[0x1];
2524 u8 flush_in_error_en
[0x1];
2525 u8 reserved_at_e
[0x12];
2527 u8 reserved_at_20
[0x8];
2528 u8 user_index
[0x18];
2530 u8 reserved_at_40
[0x8];
2533 u8 counter_set_id
[0x8];
2534 u8 reserved_at_68
[0x18];
2536 u8 reserved_at_80
[0x8];
2539 u8 reserved_at_a0
[0xe0];
2541 struct mlx5_ifc_wq_bits wq
;
2545 MLX5_RMPC_STATE_RDY
= 0x1,
2546 MLX5_RMPC_STATE_ERR
= 0x3,
2549 struct mlx5_ifc_rmpc_bits
{
2550 u8 reserved_at_0
[0x8];
2552 u8 reserved_at_c
[0x14];
2554 u8 basic_cyclic_rcv_wqe
[0x1];
2555 u8 reserved_at_21
[0x1f];
2557 u8 reserved_at_40
[0x140];
2559 struct mlx5_ifc_wq_bits wq
;
2562 struct mlx5_ifc_nic_vport_context_bits
{
2563 u8 reserved_at_0
[0x5];
2564 u8 min_wqe_inline_mode
[0x3];
2565 u8 reserved_at_8
[0x17];
2568 u8 arm_change_event
[0x1];
2569 u8 reserved_at_21
[0x1a];
2570 u8 event_on_mtu
[0x1];
2571 u8 event_on_promisc_change
[0x1];
2572 u8 event_on_vlan_change
[0x1];
2573 u8 event_on_mc_address_change
[0x1];
2574 u8 event_on_uc_address_change
[0x1];
2576 u8 reserved_at_40
[0xf0];
2580 u8 system_image_guid
[0x40];
2584 u8 reserved_at_200
[0x140];
2585 u8 qkey_violation_counter
[0x10];
2586 u8 reserved_at_350
[0x430];
2590 u8 promisc_all
[0x1];
2591 u8 reserved_at_783
[0x2];
2592 u8 allowed_list_type
[0x3];
2593 u8 reserved_at_788
[0xc];
2594 u8 allowed_list_size
[0xc];
2596 struct mlx5_ifc_mac_address_layout_bits permanent_address
;
2598 u8 reserved_at_7e0
[0x20];
2600 u8 current_uc_mac_address
[0][0x40];
2604 MLX5_MKC_ACCESS_MODE_PA
= 0x0,
2605 MLX5_MKC_ACCESS_MODE_MTT
= 0x1,
2606 MLX5_MKC_ACCESS_MODE_KLMS
= 0x2,
2607 MLX5_MKC_ACCESS_MODE_KSM
= 0x3,
2610 struct mlx5_ifc_mkc_bits
{
2611 u8 reserved_at_0
[0x1];
2613 u8 reserved_at_2
[0xd];
2614 u8 small_fence_on_rdma_read_response
[0x1];
2621 u8 access_mode
[0x2];
2622 u8 reserved_at_18
[0x8];
2627 u8 reserved_at_40
[0x20];
2632 u8 reserved_at_63
[0x2];
2633 u8 expected_sigerr_count
[0x1];
2634 u8 reserved_at_66
[0x1];
2638 u8 start_addr
[0x40];
2642 u8 bsf_octword_size
[0x20];
2644 u8 reserved_at_120
[0x80];
2646 u8 translations_octword_size
[0x20];
2648 u8 reserved_at_1c0
[0x1b];
2649 u8 log_page_size
[0x5];
2651 u8 reserved_at_1e0
[0x20];
2654 struct mlx5_ifc_pkey_bits
{
2655 u8 reserved_at_0
[0x10];
2659 struct mlx5_ifc_array128_auto_bits
{
2660 u8 array128_auto
[16][0x8];
2663 struct mlx5_ifc_hca_vport_context_bits
{
2664 u8 field_select
[0x20];
2666 u8 reserved_at_20
[0xe0];
2668 u8 sm_virt_aware
[0x1];
2671 u8 grh_required
[0x1];
2672 u8 reserved_at_104
[0xc];
2673 u8 port_physical_state
[0x4];
2674 u8 vport_state_policy
[0x4];
2676 u8 vport_state
[0x4];
2678 u8 reserved_at_120
[0x20];
2680 u8 system_image_guid
[0x40];
2688 u8 cap_mask1_field_select
[0x20];
2692 u8 cap_mask2_field_select
[0x20];
2694 u8 reserved_at_280
[0x80];
2697 u8 reserved_at_310
[0x4];
2698 u8 init_type_reply
[0x4];
2700 u8 subnet_timeout
[0x5];
2704 u8 reserved_at_334
[0xc];
2706 u8 qkey_violation_counter
[0x10];
2707 u8 pkey_violation_counter
[0x10];
2709 u8 reserved_at_360
[0xca0];
2712 struct mlx5_ifc_esw_vport_context_bits
{
2713 u8 reserved_at_0
[0x3];
2714 u8 vport_svlan_strip
[0x1];
2715 u8 vport_cvlan_strip
[0x1];
2716 u8 vport_svlan_insert
[0x1];
2717 u8 vport_cvlan_insert
[0x2];
2718 u8 reserved_at_8
[0x18];
2720 u8 reserved_at_20
[0x20];
2729 u8 reserved_at_60
[0x7a0];
2733 MLX5_EQC_STATUS_OK
= 0x0,
2734 MLX5_EQC_STATUS_EQ_WRITE_FAILURE
= 0xa,
2738 MLX5_EQC_ST_ARMED
= 0x9,
2739 MLX5_EQC_ST_FIRED
= 0xa,
2742 struct mlx5_ifc_eqc_bits
{
2744 u8 reserved_at_4
[0x9];
2747 u8 reserved_at_f
[0x5];
2749 u8 reserved_at_18
[0x8];
2751 u8 reserved_at_20
[0x20];
2753 u8 reserved_at_40
[0x14];
2754 u8 page_offset
[0x6];
2755 u8 reserved_at_5a
[0x6];
2757 u8 reserved_at_60
[0x3];
2758 u8 log_eq_size
[0x5];
2761 u8 reserved_at_80
[0x20];
2763 u8 reserved_at_a0
[0x18];
2766 u8 reserved_at_c0
[0x3];
2767 u8 log_page_size
[0x5];
2768 u8 reserved_at_c8
[0x18];
2770 u8 reserved_at_e0
[0x60];
2772 u8 reserved_at_140
[0x8];
2773 u8 consumer_counter
[0x18];
2775 u8 reserved_at_160
[0x8];
2776 u8 producer_counter
[0x18];
2778 u8 reserved_at_180
[0x80];
2782 MLX5_DCTC_STATE_ACTIVE
= 0x0,
2783 MLX5_DCTC_STATE_DRAINING
= 0x1,
2784 MLX5_DCTC_STATE_DRAINED
= 0x2,
2788 MLX5_DCTC_CS_RES_DISABLE
= 0x0,
2789 MLX5_DCTC_CS_RES_NA
= 0x1,
2790 MLX5_DCTC_CS_RES_UP_TO_64B
= 0x2,
2794 MLX5_DCTC_MTU_256_BYTES
= 0x1,
2795 MLX5_DCTC_MTU_512_BYTES
= 0x2,
2796 MLX5_DCTC_MTU_1K_BYTES
= 0x3,
2797 MLX5_DCTC_MTU_2K_BYTES
= 0x4,
2798 MLX5_DCTC_MTU_4K_BYTES
= 0x5,
2801 struct mlx5_ifc_dctc_bits
{
2802 u8 reserved_at_0
[0x4];
2804 u8 reserved_at_8
[0x18];
2806 u8 reserved_at_20
[0x8];
2807 u8 user_index
[0x18];
2809 u8 reserved_at_40
[0x8];
2812 u8 counter_set_id
[0x8];
2813 u8 atomic_mode
[0x4];
2817 u8 atomic_like_write_en
[0x1];
2818 u8 latency_sensitive
[0x1];
2821 u8 reserved_at_73
[0xd];
2823 u8 reserved_at_80
[0x8];
2825 u8 reserved_at_90
[0x3];
2826 u8 min_rnr_nak
[0x5];
2827 u8 reserved_at_98
[0x8];
2829 u8 reserved_at_a0
[0x8];
2832 u8 reserved_at_c0
[0x8];
2836 u8 reserved_at_e8
[0x4];
2837 u8 flow_label
[0x14];
2839 u8 dc_access_key
[0x40];
2841 u8 reserved_at_140
[0x5];
2844 u8 pkey_index
[0x10];
2846 u8 reserved_at_160
[0x8];
2847 u8 my_addr_index
[0x8];
2848 u8 reserved_at_170
[0x8];
2851 u8 dc_access_key_violation_count
[0x20];
2853 u8 reserved_at_1a0
[0x14];
2859 u8 reserved_at_1c0
[0x40];
2863 MLX5_CQC_STATUS_OK
= 0x0,
2864 MLX5_CQC_STATUS_CQ_OVERFLOW
= 0x9,
2865 MLX5_CQC_STATUS_CQ_WRITE_FAIL
= 0xa,
2869 MLX5_CQC_CQE_SZ_64_BYTES
= 0x0,
2870 MLX5_CQC_CQE_SZ_128_BYTES
= 0x1,
2874 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED
= 0x6,
2875 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED
= 0x9,
2876 MLX5_CQC_ST_FIRED
= 0xa,
2880 MLX5_CQ_PERIOD_MODE_START_FROM_EQE
= 0x0,
2881 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
= 0x1,
2882 MLX5_CQ_PERIOD_NUM_MODES
2885 struct mlx5_ifc_cqc_bits
{
2887 u8 reserved_at_4
[0x4];
2890 u8 reserved_at_c
[0x1];
2891 u8 scqe_break_moderation_en
[0x1];
2893 u8 cq_period_mode
[0x2];
2894 u8 cqe_comp_en
[0x1];
2895 u8 mini_cqe_res_format
[0x2];
2897 u8 reserved_at_18
[0x8];
2899 u8 reserved_at_20
[0x20];
2901 u8 reserved_at_40
[0x14];
2902 u8 page_offset
[0x6];
2903 u8 reserved_at_5a
[0x6];
2905 u8 reserved_at_60
[0x3];
2906 u8 log_cq_size
[0x5];
2909 u8 reserved_at_80
[0x4];
2911 u8 cq_max_count
[0x10];
2913 u8 reserved_at_a0
[0x18];
2916 u8 reserved_at_c0
[0x3];
2917 u8 log_page_size
[0x5];
2918 u8 reserved_at_c8
[0x18];
2920 u8 reserved_at_e0
[0x20];
2922 u8 reserved_at_100
[0x8];
2923 u8 last_notified_index
[0x18];
2925 u8 reserved_at_120
[0x8];
2926 u8 last_solicit_index
[0x18];
2928 u8 reserved_at_140
[0x8];
2929 u8 consumer_counter
[0x18];
2931 u8 reserved_at_160
[0x8];
2932 u8 producer_counter
[0x18];
2934 u8 reserved_at_180
[0x40];
2939 union mlx5_ifc_cong_control_roce_ecn_auto_bits
{
2940 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp
;
2941 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp
;
2942 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np
;
2943 u8 reserved_at_0
[0x800];
2946 struct mlx5_ifc_query_adapter_param_block_bits
{
2947 u8 reserved_at_0
[0xc0];
2949 u8 reserved_at_c0
[0x8];
2950 u8 ieee_vendor_id
[0x18];
2952 u8 reserved_at_e0
[0x10];
2953 u8 vsd_vendor_id
[0x10];
2957 u8 vsd_contd_psid
[16][0x8];
2961 MLX5_XRQC_STATE_GOOD
= 0x0,
2962 MLX5_XRQC_STATE_ERROR
= 0x1,
2966 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY
= 0x0,
2967 MLX5_XRQC_TOPOLOGY_TAG_MATCHING
= 0x1,
2971 MLX5_XRQC_OFFLOAD_RNDV
= 0x1,
2974 struct mlx5_ifc_tag_matching_topology_context_bits
{
2975 u8 log_matching_list_sz
[0x4];
2976 u8 reserved_at_4
[0xc];
2977 u8 append_next_index
[0x10];
2979 u8 sw_phase_cnt
[0x10];
2980 u8 hw_phase_cnt
[0x10];
2982 u8 reserved_at_40
[0x40];
2985 struct mlx5_ifc_xrqc_bits
{
2988 u8 reserved_at_5
[0xf];
2990 u8 reserved_at_18
[0x4];
2993 u8 reserved_at_20
[0x8];
2994 u8 user_index
[0x18];
2996 u8 reserved_at_40
[0x8];
2999 u8 reserved_at_60
[0xa0];
3001 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context
;
3003 u8 reserved_at_180
[0x880];
3005 struct mlx5_ifc_wq_bits wq
;
3008 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits
{
3009 struct mlx5_ifc_modify_field_select_bits modify_field_select
;
3010 struct mlx5_ifc_resize_field_select_bits resize_field_select
;
3011 u8 reserved_at_0
[0x20];
3014 union mlx5_ifc_field_select_802_1_r_roce_auto_bits
{
3015 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp
;
3016 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp
;
3017 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np
;
3018 u8 reserved_at_0
[0x20];
3021 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits
{
3022 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
3023 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
3024 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
3025 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
3026 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
3027 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
3028 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
3029 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
3030 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
3031 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs
;
3032 u8 reserved_at_0
[0x7c0];
3035 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits
{
3036 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout
;
3037 u8 reserved_at_0
[0x7c0];
3040 union mlx5_ifc_event_auto_bits
{
3041 struct mlx5_ifc_comp_event_bits comp_event
;
3042 struct mlx5_ifc_dct_events_bits dct_events
;
3043 struct mlx5_ifc_qp_events_bits qp_events
;
3044 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event
;
3045 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event
;
3046 struct mlx5_ifc_cq_error_bits cq_error
;
3047 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged
;
3048 struct mlx5_ifc_port_state_change_event_bits port_state_change_event
;
3049 struct mlx5_ifc_gpio_event_bits gpio_event
;
3050 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event
;
3051 struct mlx5_ifc_stall_vl_event_bits stall_vl_event
;
3052 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event
;
3053 u8 reserved_at_0
[0xe0];
3056 struct mlx5_ifc_health_buffer_bits
{
3057 u8 reserved_at_0
[0x100];
3059 u8 assert_existptr
[0x20];
3061 u8 assert_callra
[0x20];
3063 u8 reserved_at_140
[0x40];
3065 u8 fw_version
[0x20];
3069 u8 reserved_at_1c0
[0x20];
3071 u8 irisc_index
[0x8];
3076 struct mlx5_ifc_register_loopback_control_bits
{
3078 u8 reserved_at_1
[0x7];
3080 u8 reserved_at_10
[0x10];
3082 u8 reserved_at_20
[0x60];
3085 struct mlx5_ifc_vport_tc_element_bits
{
3086 u8 traffic_class
[0x4];
3087 u8 reserved_at_4
[0xc];
3088 u8 vport_number
[0x10];
3091 struct mlx5_ifc_vport_element_bits
{
3092 u8 reserved_at_0
[0x10];
3093 u8 vport_number
[0x10];
3097 TSAR_ELEMENT_TSAR_TYPE_DWRR
= 0x0,
3098 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN
= 0x1,
3099 TSAR_ELEMENT_TSAR_TYPE_ETS
= 0x2,
3102 struct mlx5_ifc_tsar_element_bits
{
3103 u8 reserved_at_0
[0x8];
3105 u8 reserved_at_10
[0x10];
3109 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS
= 0x0,
3110 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL
= 0x1,
3113 struct mlx5_ifc_teardown_hca_out_bits
{
3115 u8 reserved_at_8
[0x18];
3119 u8 reserved_at_40
[0x3f];
3121 u8 force_state
[0x1];
3125 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE
= 0x0,
3126 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE
= 0x1,
3129 struct mlx5_ifc_teardown_hca_in_bits
{
3131 u8 reserved_at_10
[0x10];
3133 u8 reserved_at_20
[0x10];
3136 u8 reserved_at_40
[0x10];
3139 u8 reserved_at_60
[0x20];
3142 struct mlx5_ifc_sqerr2rts_qp_out_bits
{
3144 u8 reserved_at_8
[0x18];
3148 u8 reserved_at_40
[0x40];
3151 struct mlx5_ifc_sqerr2rts_qp_in_bits
{
3153 u8 reserved_at_10
[0x10];
3155 u8 reserved_at_20
[0x10];
3158 u8 reserved_at_40
[0x8];
3161 u8 reserved_at_60
[0x20];
3163 u8 opt_param_mask
[0x20];
3165 u8 reserved_at_a0
[0x20];
3167 struct mlx5_ifc_qpc_bits qpc
;
3169 u8 reserved_at_800
[0x80];
3172 struct mlx5_ifc_sqd2rts_qp_out_bits
{
3174 u8 reserved_at_8
[0x18];
3178 u8 reserved_at_40
[0x40];
3181 struct mlx5_ifc_sqd2rts_qp_in_bits
{
3183 u8 reserved_at_10
[0x10];
3185 u8 reserved_at_20
[0x10];
3188 u8 reserved_at_40
[0x8];
3191 u8 reserved_at_60
[0x20];
3193 u8 opt_param_mask
[0x20];
3195 u8 reserved_at_a0
[0x20];
3197 struct mlx5_ifc_qpc_bits qpc
;
3199 u8 reserved_at_800
[0x80];
3202 struct mlx5_ifc_set_roce_address_out_bits
{
3204 u8 reserved_at_8
[0x18];
3208 u8 reserved_at_40
[0x40];
3211 struct mlx5_ifc_set_roce_address_in_bits
{
3213 u8 reserved_at_10
[0x10];
3215 u8 reserved_at_20
[0x10];
3218 u8 roce_address_index
[0x10];
3219 u8 reserved_at_50
[0x10];
3221 u8 reserved_at_60
[0x20];
3223 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
3226 struct mlx5_ifc_set_mad_demux_out_bits
{
3228 u8 reserved_at_8
[0x18];
3232 u8 reserved_at_40
[0x40];
3236 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL
= 0x0,
3237 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE
= 0x2,
3240 struct mlx5_ifc_set_mad_demux_in_bits
{
3242 u8 reserved_at_10
[0x10];
3244 u8 reserved_at_20
[0x10];
3247 u8 reserved_at_40
[0x20];
3249 u8 reserved_at_60
[0x6];
3251 u8 reserved_at_68
[0x18];
3254 struct mlx5_ifc_set_l2_table_entry_out_bits
{
3256 u8 reserved_at_8
[0x18];
3260 u8 reserved_at_40
[0x40];
3263 struct mlx5_ifc_set_l2_table_entry_in_bits
{
3265 u8 reserved_at_10
[0x10];
3267 u8 reserved_at_20
[0x10];
3270 u8 reserved_at_40
[0x60];
3272 u8 reserved_at_a0
[0x8];
3273 u8 table_index
[0x18];
3275 u8 reserved_at_c0
[0x20];
3277 u8 reserved_at_e0
[0x13];
3281 struct mlx5_ifc_mac_address_layout_bits mac_address
;
3283 u8 reserved_at_140
[0xc0];
3286 struct mlx5_ifc_set_issi_out_bits
{
3288 u8 reserved_at_8
[0x18];
3292 u8 reserved_at_40
[0x40];
3295 struct mlx5_ifc_set_issi_in_bits
{
3297 u8 reserved_at_10
[0x10];
3299 u8 reserved_at_20
[0x10];
3302 u8 reserved_at_40
[0x10];
3303 u8 current_issi
[0x10];
3305 u8 reserved_at_60
[0x20];
3308 struct mlx5_ifc_set_hca_cap_out_bits
{
3310 u8 reserved_at_8
[0x18];
3314 u8 reserved_at_40
[0x40];
3317 struct mlx5_ifc_set_hca_cap_in_bits
{
3319 u8 reserved_at_10
[0x10];
3321 u8 reserved_at_20
[0x10];
3324 u8 reserved_at_40
[0x40];
3326 union mlx5_ifc_hca_cap_union_bits capability
;
3330 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION
= 0x0,
3331 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG
= 0x1,
3332 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST
= 0x2,
3333 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS
= 0x3
3336 struct mlx5_ifc_set_fte_out_bits
{
3338 u8 reserved_at_8
[0x18];
3342 u8 reserved_at_40
[0x40];
3345 struct mlx5_ifc_set_fte_in_bits
{
3347 u8 reserved_at_10
[0x10];
3349 u8 reserved_at_20
[0x10];
3352 u8 other_vport
[0x1];
3353 u8 reserved_at_41
[0xf];
3354 u8 vport_number
[0x10];
3356 u8 reserved_at_60
[0x20];
3359 u8 reserved_at_88
[0x18];
3361 u8 reserved_at_a0
[0x8];
3364 u8 reserved_at_c0
[0x18];
3365 u8 modify_enable_mask
[0x8];
3367 u8 reserved_at_e0
[0x20];
3369 u8 flow_index
[0x20];
3371 u8 reserved_at_120
[0xe0];
3373 struct mlx5_ifc_flow_context_bits flow_context
;
3376 struct mlx5_ifc_rts2rts_qp_out_bits
{
3378 u8 reserved_at_8
[0x18];
3382 u8 reserved_at_40
[0x40];
3385 struct mlx5_ifc_rts2rts_qp_in_bits
{
3387 u8 reserved_at_10
[0x10];
3389 u8 reserved_at_20
[0x10];
3392 u8 reserved_at_40
[0x8];
3395 u8 reserved_at_60
[0x20];
3397 u8 opt_param_mask
[0x20];
3399 u8 reserved_at_a0
[0x20];
3401 struct mlx5_ifc_qpc_bits qpc
;
3403 u8 reserved_at_800
[0x80];
3406 struct mlx5_ifc_rtr2rts_qp_out_bits
{
3408 u8 reserved_at_8
[0x18];
3412 u8 reserved_at_40
[0x40];
3415 struct mlx5_ifc_rtr2rts_qp_in_bits
{
3417 u8 reserved_at_10
[0x10];
3419 u8 reserved_at_20
[0x10];
3422 u8 reserved_at_40
[0x8];
3425 u8 reserved_at_60
[0x20];
3427 u8 opt_param_mask
[0x20];
3429 u8 reserved_at_a0
[0x20];
3431 struct mlx5_ifc_qpc_bits qpc
;
3433 u8 reserved_at_800
[0x80];
3436 struct mlx5_ifc_rst2init_qp_out_bits
{
3438 u8 reserved_at_8
[0x18];
3442 u8 reserved_at_40
[0x40];
3445 struct mlx5_ifc_rst2init_qp_in_bits
{
3447 u8 reserved_at_10
[0x10];
3449 u8 reserved_at_20
[0x10];
3452 u8 reserved_at_40
[0x8];
3455 u8 reserved_at_60
[0x20];
3457 u8 opt_param_mask
[0x20];
3459 u8 reserved_at_a0
[0x20];
3461 struct mlx5_ifc_qpc_bits qpc
;
3463 u8 reserved_at_800
[0x80];
3466 struct mlx5_ifc_query_xrq_out_bits
{
3468 u8 reserved_at_8
[0x18];
3472 u8 reserved_at_40
[0x40];
3474 struct mlx5_ifc_xrqc_bits xrq_context
;
3477 struct mlx5_ifc_query_xrq_in_bits
{
3479 u8 reserved_at_10
[0x10];
3481 u8 reserved_at_20
[0x10];
3484 u8 reserved_at_40
[0x8];
3487 u8 reserved_at_60
[0x20];
3490 struct mlx5_ifc_query_xrc_srq_out_bits
{
3492 u8 reserved_at_8
[0x18];
3496 u8 reserved_at_40
[0x40];
3498 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
3500 u8 reserved_at_280
[0x600];
3505 struct mlx5_ifc_query_xrc_srq_in_bits
{
3507 u8 reserved_at_10
[0x10];
3509 u8 reserved_at_20
[0x10];
3512 u8 reserved_at_40
[0x8];
3515 u8 reserved_at_60
[0x20];
3519 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN
= 0x0,
3520 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP
= 0x1,
3523 struct mlx5_ifc_query_vport_state_out_bits
{
3525 u8 reserved_at_8
[0x18];
3529 u8 reserved_at_40
[0x20];
3531 u8 reserved_at_60
[0x18];
3532 u8 admin_state
[0x4];
3537 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
= 0x0,
3538 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT
= 0x1,
3541 struct mlx5_ifc_query_vport_state_in_bits
{
3543 u8 reserved_at_10
[0x10];
3545 u8 reserved_at_20
[0x10];
3548 u8 other_vport
[0x1];
3549 u8 reserved_at_41
[0xf];
3550 u8 vport_number
[0x10];
3552 u8 reserved_at_60
[0x20];
3555 struct mlx5_ifc_query_vport_counter_out_bits
{
3557 u8 reserved_at_8
[0x18];
3561 u8 reserved_at_40
[0x40];
3563 struct mlx5_ifc_traffic_counter_bits received_errors
;
3565 struct mlx5_ifc_traffic_counter_bits transmit_errors
;
3567 struct mlx5_ifc_traffic_counter_bits received_ib_unicast
;
3569 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast
;
3571 struct mlx5_ifc_traffic_counter_bits received_ib_multicast
;
3573 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast
;
3575 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast
;
3577 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast
;
3579 struct mlx5_ifc_traffic_counter_bits received_eth_unicast
;
3581 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast
;
3583 struct mlx5_ifc_traffic_counter_bits received_eth_multicast
;
3585 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast
;
3587 u8 reserved_at_680
[0xa00];
3591 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS
= 0x0,
3594 struct mlx5_ifc_query_vport_counter_in_bits
{
3596 u8 reserved_at_10
[0x10];
3598 u8 reserved_at_20
[0x10];
3601 u8 other_vport
[0x1];
3602 u8 reserved_at_41
[0xb];
3604 u8 vport_number
[0x10];
3606 u8 reserved_at_60
[0x60];
3609 u8 reserved_at_c1
[0x1f];
3611 u8 reserved_at_e0
[0x20];
3614 struct mlx5_ifc_query_tis_out_bits
{
3616 u8 reserved_at_8
[0x18];
3620 u8 reserved_at_40
[0x40];
3622 struct mlx5_ifc_tisc_bits tis_context
;
3625 struct mlx5_ifc_query_tis_in_bits
{
3627 u8 reserved_at_10
[0x10];
3629 u8 reserved_at_20
[0x10];
3632 u8 reserved_at_40
[0x8];
3635 u8 reserved_at_60
[0x20];
3638 struct mlx5_ifc_query_tir_out_bits
{
3640 u8 reserved_at_8
[0x18];
3644 u8 reserved_at_40
[0xc0];
3646 struct mlx5_ifc_tirc_bits tir_context
;
3649 struct mlx5_ifc_query_tir_in_bits
{
3651 u8 reserved_at_10
[0x10];
3653 u8 reserved_at_20
[0x10];
3656 u8 reserved_at_40
[0x8];
3659 u8 reserved_at_60
[0x20];
3662 struct mlx5_ifc_query_srq_out_bits
{
3664 u8 reserved_at_8
[0x18];
3668 u8 reserved_at_40
[0x40];
3670 struct mlx5_ifc_srqc_bits srq_context_entry
;
3672 u8 reserved_at_280
[0x600];
3677 struct mlx5_ifc_query_srq_in_bits
{
3679 u8 reserved_at_10
[0x10];
3681 u8 reserved_at_20
[0x10];
3684 u8 reserved_at_40
[0x8];
3687 u8 reserved_at_60
[0x20];
3690 struct mlx5_ifc_query_sq_out_bits
{
3692 u8 reserved_at_8
[0x18];
3696 u8 reserved_at_40
[0xc0];
3698 struct mlx5_ifc_sqc_bits sq_context
;
3701 struct mlx5_ifc_query_sq_in_bits
{
3703 u8 reserved_at_10
[0x10];
3705 u8 reserved_at_20
[0x10];
3708 u8 reserved_at_40
[0x8];
3711 u8 reserved_at_60
[0x20];
3714 struct mlx5_ifc_query_special_contexts_out_bits
{
3716 u8 reserved_at_8
[0x18];
3720 u8 dump_fill_mkey
[0x20];
3726 u8 reserved_at_a0
[0x60];
3729 struct mlx5_ifc_query_special_contexts_in_bits
{
3731 u8 reserved_at_10
[0x10];
3733 u8 reserved_at_20
[0x10];
3736 u8 reserved_at_40
[0x40];
3739 struct mlx5_ifc_query_scheduling_element_out_bits
{
3741 u8 reserved_at_10
[0x10];
3743 u8 reserved_at_20
[0x10];
3746 u8 reserved_at_40
[0xc0];
3748 struct mlx5_ifc_scheduling_context_bits scheduling_context
;
3750 u8 reserved_at_300
[0x100];
3754 SCHEDULING_HIERARCHY_E_SWITCH
= 0x2,
3757 struct mlx5_ifc_query_scheduling_element_in_bits
{
3759 u8 reserved_at_10
[0x10];
3761 u8 reserved_at_20
[0x10];
3764 u8 scheduling_hierarchy
[0x8];
3765 u8 reserved_at_48
[0x18];
3767 u8 scheduling_element_id
[0x20];
3769 u8 reserved_at_80
[0x180];
3772 struct mlx5_ifc_query_rqt_out_bits
{
3774 u8 reserved_at_8
[0x18];
3778 u8 reserved_at_40
[0xc0];
3780 struct mlx5_ifc_rqtc_bits rqt_context
;
3783 struct mlx5_ifc_query_rqt_in_bits
{
3785 u8 reserved_at_10
[0x10];
3787 u8 reserved_at_20
[0x10];
3790 u8 reserved_at_40
[0x8];
3793 u8 reserved_at_60
[0x20];
3796 struct mlx5_ifc_query_rq_out_bits
{
3798 u8 reserved_at_8
[0x18];
3802 u8 reserved_at_40
[0xc0];
3804 struct mlx5_ifc_rqc_bits rq_context
;
3807 struct mlx5_ifc_query_rq_in_bits
{
3809 u8 reserved_at_10
[0x10];
3811 u8 reserved_at_20
[0x10];
3814 u8 reserved_at_40
[0x8];
3817 u8 reserved_at_60
[0x20];
3820 struct mlx5_ifc_query_roce_address_out_bits
{
3822 u8 reserved_at_8
[0x18];
3826 u8 reserved_at_40
[0x40];
3828 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
3831 struct mlx5_ifc_query_roce_address_in_bits
{
3833 u8 reserved_at_10
[0x10];
3835 u8 reserved_at_20
[0x10];
3838 u8 roce_address_index
[0x10];
3839 u8 reserved_at_50
[0x10];
3841 u8 reserved_at_60
[0x20];
3844 struct mlx5_ifc_query_rmp_out_bits
{
3846 u8 reserved_at_8
[0x18];
3850 u8 reserved_at_40
[0xc0];
3852 struct mlx5_ifc_rmpc_bits rmp_context
;
3855 struct mlx5_ifc_query_rmp_in_bits
{
3857 u8 reserved_at_10
[0x10];
3859 u8 reserved_at_20
[0x10];
3862 u8 reserved_at_40
[0x8];
3865 u8 reserved_at_60
[0x20];
3868 struct mlx5_ifc_query_qp_out_bits
{
3870 u8 reserved_at_8
[0x18];
3874 u8 reserved_at_40
[0x40];
3876 u8 opt_param_mask
[0x20];
3878 u8 reserved_at_a0
[0x20];
3880 struct mlx5_ifc_qpc_bits qpc
;
3882 u8 reserved_at_800
[0x80];
3887 struct mlx5_ifc_query_qp_in_bits
{
3889 u8 reserved_at_10
[0x10];
3891 u8 reserved_at_20
[0x10];
3894 u8 reserved_at_40
[0x8];
3897 u8 reserved_at_60
[0x20];
3900 struct mlx5_ifc_query_q_counter_out_bits
{
3902 u8 reserved_at_8
[0x18];
3906 u8 reserved_at_40
[0x40];
3908 u8 rx_write_requests
[0x20];
3910 u8 reserved_at_a0
[0x20];
3912 u8 rx_read_requests
[0x20];
3914 u8 reserved_at_e0
[0x20];
3916 u8 rx_atomic_requests
[0x20];
3918 u8 reserved_at_120
[0x20];
3920 u8 rx_dct_connect
[0x20];
3922 u8 reserved_at_160
[0x20];
3924 u8 out_of_buffer
[0x20];
3926 u8 reserved_at_1a0
[0x20];
3928 u8 out_of_sequence
[0x20];
3930 u8 reserved_at_1e0
[0x20];
3932 u8 duplicate_request
[0x20];
3934 u8 reserved_at_220
[0x20];
3936 u8 rnr_nak_retry_err
[0x20];
3938 u8 reserved_at_260
[0x20];
3940 u8 packet_seq_err
[0x20];
3942 u8 reserved_at_2a0
[0x20];
3944 u8 implied_nak_seq_err
[0x20];
3946 u8 reserved_at_2e0
[0x20];
3948 u8 local_ack_timeout_err
[0x20];
3950 u8 reserved_at_320
[0x4e0];
3953 struct mlx5_ifc_query_q_counter_in_bits
{
3955 u8 reserved_at_10
[0x10];
3957 u8 reserved_at_20
[0x10];
3960 u8 reserved_at_40
[0x80];
3963 u8 reserved_at_c1
[0x1f];
3965 u8 reserved_at_e0
[0x18];
3966 u8 counter_set_id
[0x8];
3969 struct mlx5_ifc_query_pages_out_bits
{
3971 u8 reserved_at_8
[0x18];
3975 u8 reserved_at_40
[0x10];
3976 u8 function_id
[0x10];
3982 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES
= 0x1,
3983 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES
= 0x2,
3984 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES
= 0x3,
3987 struct mlx5_ifc_query_pages_in_bits
{
3989 u8 reserved_at_10
[0x10];
3991 u8 reserved_at_20
[0x10];
3994 u8 reserved_at_40
[0x10];
3995 u8 function_id
[0x10];
3997 u8 reserved_at_60
[0x20];
4000 struct mlx5_ifc_query_nic_vport_context_out_bits
{
4002 u8 reserved_at_8
[0x18];
4006 u8 reserved_at_40
[0x40];
4008 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
4011 struct mlx5_ifc_query_nic_vport_context_in_bits
{
4013 u8 reserved_at_10
[0x10];
4015 u8 reserved_at_20
[0x10];
4018 u8 other_vport
[0x1];
4019 u8 reserved_at_41
[0xf];
4020 u8 vport_number
[0x10];
4022 u8 reserved_at_60
[0x5];
4023 u8 allowed_list_type
[0x3];
4024 u8 reserved_at_68
[0x18];
4027 struct mlx5_ifc_query_mkey_out_bits
{
4029 u8 reserved_at_8
[0x18];
4033 u8 reserved_at_40
[0x40];
4035 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
4037 u8 reserved_at_280
[0x600];
4039 u8 bsf0_klm0_pas_mtt0_1
[16][0x8];
4041 u8 bsf1_klm1_pas_mtt2_3
[16][0x8];
4044 struct mlx5_ifc_query_mkey_in_bits
{
4046 u8 reserved_at_10
[0x10];
4048 u8 reserved_at_20
[0x10];
4051 u8 reserved_at_40
[0x8];
4052 u8 mkey_index
[0x18];
4055 u8 reserved_at_61
[0x1f];
4058 struct mlx5_ifc_query_mad_demux_out_bits
{
4060 u8 reserved_at_8
[0x18];
4064 u8 reserved_at_40
[0x40];
4066 u8 mad_dumux_parameters_block
[0x20];
4069 struct mlx5_ifc_query_mad_demux_in_bits
{
4071 u8 reserved_at_10
[0x10];
4073 u8 reserved_at_20
[0x10];
4076 u8 reserved_at_40
[0x40];
4079 struct mlx5_ifc_query_l2_table_entry_out_bits
{
4081 u8 reserved_at_8
[0x18];
4085 u8 reserved_at_40
[0xa0];
4087 u8 reserved_at_e0
[0x13];
4091 struct mlx5_ifc_mac_address_layout_bits mac_address
;
4093 u8 reserved_at_140
[0xc0];
4096 struct mlx5_ifc_query_l2_table_entry_in_bits
{
4098 u8 reserved_at_10
[0x10];
4100 u8 reserved_at_20
[0x10];
4103 u8 reserved_at_40
[0x60];
4105 u8 reserved_at_a0
[0x8];
4106 u8 table_index
[0x18];
4108 u8 reserved_at_c0
[0x140];
4111 struct mlx5_ifc_query_issi_out_bits
{
4113 u8 reserved_at_8
[0x18];
4117 u8 reserved_at_40
[0x10];
4118 u8 current_issi
[0x10];
4120 u8 reserved_at_60
[0xa0];
4122 u8 reserved_at_100
[76][0x8];
4123 u8 supported_issi_dw0
[0x20];
4126 struct mlx5_ifc_query_issi_in_bits
{
4128 u8 reserved_at_10
[0x10];
4130 u8 reserved_at_20
[0x10];
4133 u8 reserved_at_40
[0x40];
4136 struct mlx5_ifc_set_driver_version_out_bits
{
4138 u8 reserved_0
[0x18];
4141 u8 reserved_1
[0x40];
4144 struct mlx5_ifc_set_driver_version_in_bits
{
4146 u8 reserved_0
[0x10];
4148 u8 reserved_1
[0x10];
4151 u8 reserved_2
[0x40];
4152 u8 driver_version
[64][0x8];
4155 struct mlx5_ifc_query_hca_vport_pkey_out_bits
{
4157 u8 reserved_at_8
[0x18];
4161 u8 reserved_at_40
[0x40];
4163 struct mlx5_ifc_pkey_bits pkey
[0];
4166 struct mlx5_ifc_query_hca_vport_pkey_in_bits
{
4168 u8 reserved_at_10
[0x10];
4170 u8 reserved_at_20
[0x10];
4173 u8 other_vport
[0x1];
4174 u8 reserved_at_41
[0xb];
4176 u8 vport_number
[0x10];
4178 u8 reserved_at_60
[0x10];
4179 u8 pkey_index
[0x10];
4183 MLX5_HCA_VPORT_SEL_PORT_GUID
= 1 << 0,
4184 MLX5_HCA_VPORT_SEL_NODE_GUID
= 1 << 1,
4185 MLX5_HCA_VPORT_SEL_STATE_POLICY
= 1 << 2,
4188 struct mlx5_ifc_query_hca_vport_gid_out_bits
{
4190 u8 reserved_at_8
[0x18];
4194 u8 reserved_at_40
[0x20];
4197 u8 reserved_at_70
[0x10];
4199 struct mlx5_ifc_array128_auto_bits gid
[0];
4202 struct mlx5_ifc_query_hca_vport_gid_in_bits
{
4204 u8 reserved_at_10
[0x10];
4206 u8 reserved_at_20
[0x10];
4209 u8 other_vport
[0x1];
4210 u8 reserved_at_41
[0xb];
4212 u8 vport_number
[0x10];
4214 u8 reserved_at_60
[0x10];
4218 struct mlx5_ifc_query_hca_vport_context_out_bits
{
4220 u8 reserved_at_8
[0x18];
4224 u8 reserved_at_40
[0x40];
4226 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
4229 struct mlx5_ifc_query_hca_vport_context_in_bits
{
4231 u8 reserved_at_10
[0x10];
4233 u8 reserved_at_20
[0x10];
4236 u8 other_vport
[0x1];
4237 u8 reserved_at_41
[0xb];
4239 u8 vport_number
[0x10];
4241 u8 reserved_at_60
[0x20];
4244 struct mlx5_ifc_query_hca_cap_out_bits
{
4246 u8 reserved_at_8
[0x18];
4250 u8 reserved_at_40
[0x40];
4252 union mlx5_ifc_hca_cap_union_bits capability
;
4255 struct mlx5_ifc_query_hca_cap_in_bits
{
4257 u8 reserved_at_10
[0x10];
4259 u8 reserved_at_20
[0x10];
4262 u8 reserved_at_40
[0x40];
4265 struct mlx5_ifc_query_flow_table_out_bits
{
4267 u8 reserved_at_8
[0x18];
4271 u8 reserved_at_40
[0x80];
4273 u8 reserved_at_c0
[0x8];
4275 u8 reserved_at_d0
[0x8];
4278 u8 reserved_at_e0
[0x120];
4281 struct mlx5_ifc_query_flow_table_in_bits
{
4283 u8 reserved_at_10
[0x10];
4285 u8 reserved_at_20
[0x10];
4288 u8 reserved_at_40
[0x40];
4291 u8 reserved_at_88
[0x18];
4293 u8 reserved_at_a0
[0x8];
4296 u8 reserved_at_c0
[0x140];
4299 struct mlx5_ifc_query_fte_out_bits
{
4301 u8 reserved_at_8
[0x18];
4305 u8 reserved_at_40
[0x1c0];
4307 struct mlx5_ifc_flow_context_bits flow_context
;
4310 struct mlx5_ifc_query_fte_in_bits
{
4312 u8 reserved_at_10
[0x10];
4314 u8 reserved_at_20
[0x10];
4317 u8 reserved_at_40
[0x40];
4320 u8 reserved_at_88
[0x18];
4322 u8 reserved_at_a0
[0x8];
4325 u8 reserved_at_c0
[0x40];
4327 u8 flow_index
[0x20];
4329 u8 reserved_at_120
[0xe0];
4333 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
4334 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
4335 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
4338 struct mlx5_ifc_query_flow_group_out_bits
{
4340 u8 reserved_at_8
[0x18];
4344 u8 reserved_at_40
[0xa0];
4346 u8 start_flow_index
[0x20];
4348 u8 reserved_at_100
[0x20];
4350 u8 end_flow_index
[0x20];
4352 u8 reserved_at_140
[0xa0];
4354 u8 reserved_at_1e0
[0x18];
4355 u8 match_criteria_enable
[0x8];
4357 struct mlx5_ifc_fte_match_param_bits match_criteria
;
4359 u8 reserved_at_1200
[0xe00];
4362 struct mlx5_ifc_query_flow_group_in_bits
{
4364 u8 reserved_at_10
[0x10];
4366 u8 reserved_at_20
[0x10];
4369 u8 reserved_at_40
[0x40];
4372 u8 reserved_at_88
[0x18];
4374 u8 reserved_at_a0
[0x8];
4379 u8 reserved_at_e0
[0x120];
4382 struct mlx5_ifc_query_flow_counter_out_bits
{
4384 u8 reserved_at_8
[0x18];
4388 u8 reserved_at_40
[0x40];
4390 struct mlx5_ifc_traffic_counter_bits flow_statistics
[0];
4393 struct mlx5_ifc_query_flow_counter_in_bits
{
4395 u8 reserved_at_10
[0x10];
4397 u8 reserved_at_20
[0x10];
4400 u8 reserved_at_40
[0x80];
4403 u8 reserved_at_c1
[0xf];
4404 u8 num_of_counters
[0x10];
4406 u8 reserved_at_e0
[0x10];
4407 u8 flow_counter_id
[0x10];
4410 struct mlx5_ifc_query_esw_vport_context_out_bits
{
4412 u8 reserved_at_8
[0x18];
4416 u8 reserved_at_40
[0x40];
4418 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
4421 struct mlx5_ifc_query_esw_vport_context_in_bits
{
4423 u8 reserved_at_10
[0x10];
4425 u8 reserved_at_20
[0x10];
4428 u8 other_vport
[0x1];
4429 u8 reserved_at_41
[0xf];
4430 u8 vport_number
[0x10];
4432 u8 reserved_at_60
[0x20];
4435 struct mlx5_ifc_modify_esw_vport_context_out_bits
{
4437 u8 reserved_at_8
[0x18];
4441 u8 reserved_at_40
[0x40];
4444 struct mlx5_ifc_esw_vport_context_fields_select_bits
{
4445 u8 reserved_at_0
[0x1c];
4446 u8 vport_cvlan_insert
[0x1];
4447 u8 vport_svlan_insert
[0x1];
4448 u8 vport_cvlan_strip
[0x1];
4449 u8 vport_svlan_strip
[0x1];
4452 struct mlx5_ifc_modify_esw_vport_context_in_bits
{
4454 u8 reserved_at_10
[0x10];
4456 u8 reserved_at_20
[0x10];
4459 u8 other_vport
[0x1];
4460 u8 reserved_at_41
[0xf];
4461 u8 vport_number
[0x10];
4463 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select
;
4465 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
4468 struct mlx5_ifc_query_eq_out_bits
{
4470 u8 reserved_at_8
[0x18];
4474 u8 reserved_at_40
[0x40];
4476 struct mlx5_ifc_eqc_bits eq_context_entry
;
4478 u8 reserved_at_280
[0x40];
4480 u8 event_bitmask
[0x40];
4482 u8 reserved_at_300
[0x580];
4487 struct mlx5_ifc_query_eq_in_bits
{
4489 u8 reserved_at_10
[0x10];
4491 u8 reserved_at_20
[0x10];
4494 u8 reserved_at_40
[0x18];
4497 u8 reserved_at_60
[0x20];
4500 struct mlx5_ifc_encap_header_in_bits
{
4501 u8 reserved_at_0
[0x5];
4502 u8 header_type
[0x3];
4503 u8 reserved_at_8
[0xe];
4504 u8 encap_header_size
[0xa];
4506 u8 reserved_at_20
[0x10];
4507 u8 encap_header
[2][0x8];
4509 u8 more_encap_header
[0][0x8];
4512 struct mlx5_ifc_query_encap_header_out_bits
{
4514 u8 reserved_at_8
[0x18];
4518 u8 reserved_at_40
[0xa0];
4520 struct mlx5_ifc_encap_header_in_bits encap_header
[0];
4523 struct mlx5_ifc_query_encap_header_in_bits
{
4525 u8 reserved_at_10
[0x10];
4527 u8 reserved_at_20
[0x10];
4532 u8 reserved_at_60
[0xa0];
4535 struct mlx5_ifc_alloc_encap_header_out_bits
{
4537 u8 reserved_at_8
[0x18];
4543 u8 reserved_at_60
[0x20];
4546 struct mlx5_ifc_alloc_encap_header_in_bits
{
4548 u8 reserved_at_10
[0x10];
4550 u8 reserved_at_20
[0x10];
4553 u8 reserved_at_40
[0xa0];
4555 struct mlx5_ifc_encap_header_in_bits encap_header
;
4558 struct mlx5_ifc_dealloc_encap_header_out_bits
{
4560 u8 reserved_at_8
[0x18];
4564 u8 reserved_at_40
[0x40];
4567 struct mlx5_ifc_dealloc_encap_header_in_bits
{
4569 u8 reserved_at_10
[0x10];
4571 u8 reserved_20
[0x10];
4576 u8 reserved_60
[0x20];
4579 struct mlx5_ifc_set_action_in_bits
{
4580 u8 action_type
[0x4];
4582 u8 reserved_at_10
[0x3];
4584 u8 reserved_at_18
[0x3];
4590 struct mlx5_ifc_add_action_in_bits
{
4591 u8 action_type
[0x4];
4593 u8 reserved_at_10
[0x10];
4598 union mlx5_ifc_set_action_in_add_action_in_auto_bits
{
4599 struct mlx5_ifc_set_action_in_bits set_action_in
;
4600 struct mlx5_ifc_add_action_in_bits add_action_in
;
4601 u8 reserved_at_0
[0x40];
4605 MLX5_ACTION_TYPE_SET
= 0x1,
4606 MLX5_ACTION_TYPE_ADD
= 0x2,
4610 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16
= 0x1,
4611 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0
= 0x2,
4612 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE
= 0x3,
4613 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16
= 0x4,
4614 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0
= 0x5,
4615 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP
= 0x6,
4616 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS
= 0x7,
4617 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT
= 0x8,
4618 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT
= 0x9,
4619 MLX5_ACTION_IN_FIELD_OUT_IP_TTL
= 0xa,
4620 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT
= 0xb,
4621 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT
= 0xc,
4622 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96
= 0xd,
4623 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64
= 0xe,
4624 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32
= 0xf,
4625 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0
= 0x10,
4626 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96
= 0x11,
4627 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64
= 0x12,
4628 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32
= 0x13,
4629 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0
= 0x14,
4630 MLX5_ACTION_IN_FIELD_OUT_SIPV4
= 0x15,
4631 MLX5_ACTION_IN_FIELD_OUT_DIPV4
= 0x16,
4632 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT
= 0x47,
4635 struct mlx5_ifc_alloc_modify_header_context_out_bits
{
4637 u8 reserved_at_8
[0x18];
4641 u8 modify_header_id
[0x20];
4643 u8 reserved_at_60
[0x20];
4646 struct mlx5_ifc_alloc_modify_header_context_in_bits
{
4648 u8 reserved_at_10
[0x10];
4650 u8 reserved_at_20
[0x10];
4653 u8 reserved_at_40
[0x20];
4656 u8 reserved_at_68
[0x10];
4657 u8 num_of_actions
[0x8];
4659 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions
[0];
4662 struct mlx5_ifc_dealloc_modify_header_context_out_bits
{
4664 u8 reserved_at_8
[0x18];
4668 u8 reserved_at_40
[0x40];
4671 struct mlx5_ifc_dealloc_modify_header_context_in_bits
{
4673 u8 reserved_at_10
[0x10];
4675 u8 reserved_at_20
[0x10];
4678 u8 modify_header_id
[0x20];
4680 u8 reserved_at_60
[0x20];
4683 struct mlx5_ifc_query_dct_out_bits
{
4685 u8 reserved_at_8
[0x18];
4689 u8 reserved_at_40
[0x40];
4691 struct mlx5_ifc_dctc_bits dct_context_entry
;
4693 u8 reserved_at_280
[0x180];
4696 struct mlx5_ifc_query_dct_in_bits
{
4698 u8 reserved_at_10
[0x10];
4700 u8 reserved_at_20
[0x10];
4703 u8 reserved_at_40
[0x8];
4706 u8 reserved_at_60
[0x20];
4709 struct mlx5_ifc_query_cq_out_bits
{
4711 u8 reserved_at_8
[0x18];
4715 u8 reserved_at_40
[0x40];
4717 struct mlx5_ifc_cqc_bits cq_context
;
4719 u8 reserved_at_280
[0x600];
4724 struct mlx5_ifc_query_cq_in_bits
{
4726 u8 reserved_at_10
[0x10];
4728 u8 reserved_at_20
[0x10];
4731 u8 reserved_at_40
[0x8];
4734 u8 reserved_at_60
[0x20];
4737 struct mlx5_ifc_query_cong_status_out_bits
{
4739 u8 reserved_at_8
[0x18];
4743 u8 reserved_at_40
[0x20];
4747 u8 reserved_at_62
[0x1e];
4750 struct mlx5_ifc_query_cong_status_in_bits
{
4752 u8 reserved_at_10
[0x10];
4754 u8 reserved_at_20
[0x10];
4757 u8 reserved_at_40
[0x18];
4759 u8 cong_protocol
[0x4];
4761 u8 reserved_at_60
[0x20];
4764 struct mlx5_ifc_query_cong_statistics_out_bits
{
4766 u8 reserved_at_8
[0x18];
4770 u8 reserved_at_40
[0x40];
4772 u8 rp_cur_flows
[0x20];
4776 u8 rp_cnp_ignored_high
[0x20];
4778 u8 rp_cnp_ignored_low
[0x20];
4780 u8 rp_cnp_handled_high
[0x20];
4782 u8 rp_cnp_handled_low
[0x20];
4784 u8 reserved_at_140
[0x100];
4786 u8 time_stamp_high
[0x20];
4788 u8 time_stamp_low
[0x20];
4790 u8 accumulators_period
[0x20];
4792 u8 np_ecn_marked_roce_packets_high
[0x20];
4794 u8 np_ecn_marked_roce_packets_low
[0x20];
4796 u8 np_cnp_sent_high
[0x20];
4798 u8 np_cnp_sent_low
[0x20];
4800 u8 reserved_at_320
[0x560];
4803 struct mlx5_ifc_query_cong_statistics_in_bits
{
4805 u8 reserved_at_10
[0x10];
4807 u8 reserved_at_20
[0x10];
4811 u8 reserved_at_41
[0x1f];
4813 u8 reserved_at_60
[0x20];
4816 struct mlx5_ifc_query_cong_params_out_bits
{
4818 u8 reserved_at_8
[0x18];
4822 u8 reserved_at_40
[0x40];
4824 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
4827 struct mlx5_ifc_query_cong_params_in_bits
{
4829 u8 reserved_at_10
[0x10];
4831 u8 reserved_at_20
[0x10];
4834 u8 reserved_at_40
[0x1c];
4835 u8 cong_protocol
[0x4];
4837 u8 reserved_at_60
[0x20];
4840 struct mlx5_ifc_query_adapter_out_bits
{
4842 u8 reserved_at_8
[0x18];
4846 u8 reserved_at_40
[0x40];
4848 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct
;
4851 struct mlx5_ifc_query_adapter_in_bits
{
4853 u8 reserved_at_10
[0x10];
4855 u8 reserved_at_20
[0x10];
4858 u8 reserved_at_40
[0x40];
4861 struct mlx5_ifc_qp_2rst_out_bits
{
4863 u8 reserved_at_8
[0x18];
4867 u8 reserved_at_40
[0x40];
4870 struct mlx5_ifc_qp_2rst_in_bits
{
4872 u8 reserved_at_10
[0x10];
4874 u8 reserved_at_20
[0x10];
4877 u8 reserved_at_40
[0x8];
4880 u8 reserved_at_60
[0x20];
4883 struct mlx5_ifc_qp_2err_out_bits
{
4885 u8 reserved_at_8
[0x18];
4889 u8 reserved_at_40
[0x40];
4892 struct mlx5_ifc_qp_2err_in_bits
{
4894 u8 reserved_at_10
[0x10];
4896 u8 reserved_at_20
[0x10];
4899 u8 reserved_at_40
[0x8];
4902 u8 reserved_at_60
[0x20];
4905 struct mlx5_ifc_page_fault_resume_out_bits
{
4907 u8 reserved_at_8
[0x18];
4911 u8 reserved_at_40
[0x40];
4914 struct mlx5_ifc_page_fault_resume_in_bits
{
4916 u8 reserved_at_10
[0x10];
4918 u8 reserved_at_20
[0x10];
4922 u8 reserved_at_41
[0x4];
4923 u8 page_fault_type
[0x3];
4926 u8 reserved_at_60
[0x8];
4930 struct mlx5_ifc_nop_out_bits
{
4932 u8 reserved_at_8
[0x18];
4936 u8 reserved_at_40
[0x40];
4939 struct mlx5_ifc_nop_in_bits
{
4941 u8 reserved_at_10
[0x10];
4943 u8 reserved_at_20
[0x10];
4946 u8 reserved_at_40
[0x40];
4949 struct mlx5_ifc_modify_vport_state_out_bits
{
4951 u8 reserved_at_8
[0x18];
4955 u8 reserved_at_40
[0x40];
4958 struct mlx5_ifc_modify_vport_state_in_bits
{
4960 u8 reserved_at_10
[0x10];
4962 u8 reserved_at_20
[0x10];
4965 u8 other_vport
[0x1];
4966 u8 reserved_at_41
[0xf];
4967 u8 vport_number
[0x10];
4969 u8 reserved_at_60
[0x18];
4970 u8 admin_state
[0x4];
4971 u8 reserved_at_7c
[0x4];
4974 struct mlx5_ifc_modify_tis_out_bits
{
4976 u8 reserved_at_8
[0x18];
4980 u8 reserved_at_40
[0x40];
4983 struct mlx5_ifc_modify_tis_bitmask_bits
{
4984 u8 reserved_at_0
[0x20];
4986 u8 reserved_at_20
[0x1d];
4987 u8 lag_tx_port_affinity
[0x1];
4988 u8 strict_lag_tx_port_affinity
[0x1];
4992 struct mlx5_ifc_modify_tis_in_bits
{
4994 u8 reserved_at_10
[0x10];
4996 u8 reserved_at_20
[0x10];
4999 u8 reserved_at_40
[0x8];
5002 u8 reserved_at_60
[0x20];
5004 struct mlx5_ifc_modify_tis_bitmask_bits bitmask
;
5006 u8 reserved_at_c0
[0x40];
5008 struct mlx5_ifc_tisc_bits ctx
;
5011 struct mlx5_ifc_modify_tir_bitmask_bits
{
5012 u8 reserved_at_0
[0x20];
5014 u8 reserved_at_20
[0x1b];
5016 u8 reserved_at_3c
[0x1];
5018 u8 reserved_at_3e
[0x1];
5022 struct mlx5_ifc_modify_tir_out_bits
{
5024 u8 reserved_at_8
[0x18];
5028 u8 reserved_at_40
[0x40];
5031 struct mlx5_ifc_modify_tir_in_bits
{
5033 u8 reserved_at_10
[0x10];
5035 u8 reserved_at_20
[0x10];
5038 u8 reserved_at_40
[0x8];
5041 u8 reserved_at_60
[0x20];
5043 struct mlx5_ifc_modify_tir_bitmask_bits bitmask
;
5045 u8 reserved_at_c0
[0x40];
5047 struct mlx5_ifc_tirc_bits ctx
;
5050 struct mlx5_ifc_modify_sq_out_bits
{
5052 u8 reserved_at_8
[0x18];
5056 u8 reserved_at_40
[0x40];
5059 struct mlx5_ifc_modify_sq_in_bits
{
5061 u8 reserved_at_10
[0x10];
5063 u8 reserved_at_20
[0x10];
5067 u8 reserved_at_44
[0x4];
5070 u8 reserved_at_60
[0x20];
5072 u8 modify_bitmask
[0x40];
5074 u8 reserved_at_c0
[0x40];
5076 struct mlx5_ifc_sqc_bits ctx
;
5079 struct mlx5_ifc_modify_scheduling_element_out_bits
{
5081 u8 reserved_at_8
[0x18];
5085 u8 reserved_at_40
[0x1c0];
5089 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE
= 0x1,
5090 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW
= 0x2,
5093 struct mlx5_ifc_modify_scheduling_element_in_bits
{
5095 u8 reserved_at_10
[0x10];
5097 u8 reserved_at_20
[0x10];
5100 u8 scheduling_hierarchy
[0x8];
5101 u8 reserved_at_48
[0x18];
5103 u8 scheduling_element_id
[0x20];
5105 u8 reserved_at_80
[0x20];
5107 u8 modify_bitmask
[0x20];
5109 u8 reserved_at_c0
[0x40];
5111 struct mlx5_ifc_scheduling_context_bits scheduling_context
;
5113 u8 reserved_at_300
[0x100];
5116 struct mlx5_ifc_modify_rqt_out_bits
{
5118 u8 reserved_at_8
[0x18];
5122 u8 reserved_at_40
[0x40];
5125 struct mlx5_ifc_rqt_bitmask_bits
{
5126 u8 reserved_at_0
[0x20];
5128 u8 reserved_at_20
[0x1f];
5132 struct mlx5_ifc_modify_rqt_in_bits
{
5134 u8 reserved_at_10
[0x10];
5136 u8 reserved_at_20
[0x10];
5139 u8 reserved_at_40
[0x8];
5142 u8 reserved_at_60
[0x20];
5144 struct mlx5_ifc_rqt_bitmask_bits bitmask
;
5146 u8 reserved_at_c0
[0x40];
5148 struct mlx5_ifc_rqtc_bits ctx
;
5151 struct mlx5_ifc_modify_rq_out_bits
{
5153 u8 reserved_at_8
[0x18];
5157 u8 reserved_at_40
[0x40];
5161 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD
= 1ULL << 1,
5162 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS
= 1ULL << 2,
5163 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID
= 1ULL << 3,
5166 struct mlx5_ifc_modify_rq_in_bits
{
5168 u8 reserved_at_10
[0x10];
5170 u8 reserved_at_20
[0x10];
5174 u8 reserved_at_44
[0x4];
5177 u8 reserved_at_60
[0x20];
5179 u8 modify_bitmask
[0x40];
5181 u8 reserved_at_c0
[0x40];
5183 struct mlx5_ifc_rqc_bits ctx
;
5186 struct mlx5_ifc_modify_rmp_out_bits
{
5188 u8 reserved_at_8
[0x18];
5192 u8 reserved_at_40
[0x40];
5195 struct mlx5_ifc_rmp_bitmask_bits
{
5196 u8 reserved_at_0
[0x20];
5198 u8 reserved_at_20
[0x1f];
5202 struct mlx5_ifc_modify_rmp_in_bits
{
5204 u8 reserved_at_10
[0x10];
5206 u8 reserved_at_20
[0x10];
5210 u8 reserved_at_44
[0x4];
5213 u8 reserved_at_60
[0x20];
5215 struct mlx5_ifc_rmp_bitmask_bits bitmask
;
5217 u8 reserved_at_c0
[0x40];
5219 struct mlx5_ifc_rmpc_bits ctx
;
5222 struct mlx5_ifc_modify_nic_vport_context_out_bits
{
5224 u8 reserved_at_8
[0x18];
5228 u8 reserved_at_40
[0x40];
5231 struct mlx5_ifc_modify_nic_vport_field_select_bits
{
5232 u8 reserved_at_0
[0x16];
5237 u8 change_event
[0x1];
5239 u8 permanent_address
[0x1];
5240 u8 addresses_list
[0x1];
5242 u8 reserved_at_1f
[0x1];
5245 struct mlx5_ifc_modify_nic_vport_context_in_bits
{
5247 u8 reserved_at_10
[0x10];
5249 u8 reserved_at_20
[0x10];
5252 u8 other_vport
[0x1];
5253 u8 reserved_at_41
[0xf];
5254 u8 vport_number
[0x10];
5256 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select
;
5258 u8 reserved_at_80
[0x780];
5260 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
5263 struct mlx5_ifc_modify_hca_vport_context_out_bits
{
5265 u8 reserved_at_8
[0x18];
5269 u8 reserved_at_40
[0x40];
5272 struct mlx5_ifc_modify_hca_vport_context_in_bits
{
5274 u8 reserved_at_10
[0x10];
5276 u8 reserved_at_20
[0x10];
5279 u8 other_vport
[0x1];
5280 u8 reserved_at_41
[0xb];
5282 u8 vport_number
[0x10];
5284 u8 reserved_at_60
[0x20];
5286 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
5289 struct mlx5_ifc_modify_cq_out_bits
{
5291 u8 reserved_at_8
[0x18];
5295 u8 reserved_at_40
[0x40];
5299 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ
= 0x0,
5300 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ
= 0x1,
5303 struct mlx5_ifc_modify_cq_in_bits
{
5305 u8 reserved_at_10
[0x10];
5307 u8 reserved_at_20
[0x10];
5310 u8 reserved_at_40
[0x8];
5313 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select
;
5315 struct mlx5_ifc_cqc_bits cq_context
;
5317 u8 reserved_at_280
[0x600];
5322 struct mlx5_ifc_modify_cong_status_out_bits
{
5324 u8 reserved_at_8
[0x18];
5328 u8 reserved_at_40
[0x40];
5331 struct mlx5_ifc_modify_cong_status_in_bits
{
5333 u8 reserved_at_10
[0x10];
5335 u8 reserved_at_20
[0x10];
5338 u8 reserved_at_40
[0x18];
5340 u8 cong_protocol
[0x4];
5344 u8 reserved_at_62
[0x1e];
5347 struct mlx5_ifc_modify_cong_params_out_bits
{
5349 u8 reserved_at_8
[0x18];
5353 u8 reserved_at_40
[0x40];
5356 struct mlx5_ifc_modify_cong_params_in_bits
{
5358 u8 reserved_at_10
[0x10];
5360 u8 reserved_at_20
[0x10];
5363 u8 reserved_at_40
[0x1c];
5364 u8 cong_protocol
[0x4];
5366 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select
;
5368 u8 reserved_at_80
[0x80];
5370 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
5373 struct mlx5_ifc_manage_pages_out_bits
{
5375 u8 reserved_at_8
[0x18];
5379 u8 output_num_entries
[0x20];
5381 u8 reserved_at_60
[0x20];
5387 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL
= 0x0,
5388 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS
= 0x1,
5389 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES
= 0x2,
5392 struct mlx5_ifc_manage_pages_in_bits
{
5394 u8 reserved_at_10
[0x10];
5396 u8 reserved_at_20
[0x10];
5399 u8 reserved_at_40
[0x10];
5400 u8 function_id
[0x10];
5402 u8 input_num_entries
[0x20];
5407 struct mlx5_ifc_mad_ifc_out_bits
{
5409 u8 reserved_at_8
[0x18];
5413 u8 reserved_at_40
[0x40];
5415 u8 response_mad_packet
[256][0x8];
5418 struct mlx5_ifc_mad_ifc_in_bits
{
5420 u8 reserved_at_10
[0x10];
5422 u8 reserved_at_20
[0x10];
5425 u8 remote_lid
[0x10];
5426 u8 reserved_at_50
[0x8];
5429 u8 reserved_at_60
[0x20];
5434 struct mlx5_ifc_init_hca_out_bits
{
5436 u8 reserved_at_8
[0x18];
5440 u8 reserved_at_40
[0x40];
5443 struct mlx5_ifc_init_hca_in_bits
{
5445 u8 reserved_at_10
[0x10];
5447 u8 reserved_at_20
[0x10];
5450 u8 reserved_at_40
[0x40];
5453 struct mlx5_ifc_init2rtr_qp_out_bits
{
5455 u8 reserved_at_8
[0x18];
5459 u8 reserved_at_40
[0x40];
5462 struct mlx5_ifc_init2rtr_qp_in_bits
{
5464 u8 reserved_at_10
[0x10];
5466 u8 reserved_at_20
[0x10];
5469 u8 reserved_at_40
[0x8];
5472 u8 reserved_at_60
[0x20];
5474 u8 opt_param_mask
[0x20];
5476 u8 reserved_at_a0
[0x20];
5478 struct mlx5_ifc_qpc_bits qpc
;
5480 u8 reserved_at_800
[0x80];
5483 struct mlx5_ifc_init2init_qp_out_bits
{
5485 u8 reserved_at_8
[0x18];
5489 u8 reserved_at_40
[0x40];
5492 struct mlx5_ifc_init2init_qp_in_bits
{
5494 u8 reserved_at_10
[0x10];
5496 u8 reserved_at_20
[0x10];
5499 u8 reserved_at_40
[0x8];
5502 u8 reserved_at_60
[0x20];
5504 u8 opt_param_mask
[0x20];
5506 u8 reserved_at_a0
[0x20];
5508 struct mlx5_ifc_qpc_bits qpc
;
5510 u8 reserved_at_800
[0x80];
5513 struct mlx5_ifc_get_dropped_packet_log_out_bits
{
5515 u8 reserved_at_8
[0x18];
5519 u8 reserved_at_40
[0x40];
5521 u8 packet_headers_log
[128][0x8];
5523 u8 packet_syndrome
[64][0x8];
5526 struct mlx5_ifc_get_dropped_packet_log_in_bits
{
5528 u8 reserved_at_10
[0x10];
5530 u8 reserved_at_20
[0x10];
5533 u8 reserved_at_40
[0x40];
5536 struct mlx5_ifc_gen_eqe_in_bits
{
5538 u8 reserved_at_10
[0x10];
5540 u8 reserved_at_20
[0x10];
5543 u8 reserved_at_40
[0x18];
5546 u8 reserved_at_60
[0x20];
5551 struct mlx5_ifc_gen_eq_out_bits
{
5553 u8 reserved_at_8
[0x18];
5557 u8 reserved_at_40
[0x40];
5560 struct mlx5_ifc_enable_hca_out_bits
{
5562 u8 reserved_at_8
[0x18];
5566 u8 reserved_at_40
[0x20];
5569 struct mlx5_ifc_enable_hca_in_bits
{
5571 u8 reserved_at_10
[0x10];
5573 u8 reserved_at_20
[0x10];
5576 u8 reserved_at_40
[0x10];
5577 u8 function_id
[0x10];
5579 u8 reserved_at_60
[0x20];
5582 struct mlx5_ifc_drain_dct_out_bits
{
5584 u8 reserved_at_8
[0x18];
5588 u8 reserved_at_40
[0x40];
5591 struct mlx5_ifc_drain_dct_in_bits
{
5593 u8 reserved_at_10
[0x10];
5595 u8 reserved_at_20
[0x10];
5598 u8 reserved_at_40
[0x8];
5601 u8 reserved_at_60
[0x20];
5604 struct mlx5_ifc_disable_hca_out_bits
{
5606 u8 reserved_at_8
[0x18];
5610 u8 reserved_at_40
[0x20];
5613 struct mlx5_ifc_disable_hca_in_bits
{
5615 u8 reserved_at_10
[0x10];
5617 u8 reserved_at_20
[0x10];
5620 u8 reserved_at_40
[0x10];
5621 u8 function_id
[0x10];
5623 u8 reserved_at_60
[0x20];
5626 struct mlx5_ifc_detach_from_mcg_out_bits
{
5628 u8 reserved_at_8
[0x18];
5632 u8 reserved_at_40
[0x40];
5635 struct mlx5_ifc_detach_from_mcg_in_bits
{
5637 u8 reserved_at_10
[0x10];
5639 u8 reserved_at_20
[0x10];
5642 u8 reserved_at_40
[0x8];
5645 u8 reserved_at_60
[0x20];
5647 u8 multicast_gid
[16][0x8];
5650 struct mlx5_ifc_destroy_xrq_out_bits
{
5652 u8 reserved_at_8
[0x18];
5656 u8 reserved_at_40
[0x40];
5659 struct mlx5_ifc_destroy_xrq_in_bits
{
5661 u8 reserved_at_10
[0x10];
5663 u8 reserved_at_20
[0x10];
5666 u8 reserved_at_40
[0x8];
5669 u8 reserved_at_60
[0x20];
5672 struct mlx5_ifc_destroy_xrc_srq_out_bits
{
5674 u8 reserved_at_8
[0x18];
5678 u8 reserved_at_40
[0x40];
5681 struct mlx5_ifc_destroy_xrc_srq_in_bits
{
5683 u8 reserved_at_10
[0x10];
5685 u8 reserved_at_20
[0x10];
5688 u8 reserved_at_40
[0x8];
5691 u8 reserved_at_60
[0x20];
5694 struct mlx5_ifc_destroy_tis_out_bits
{
5696 u8 reserved_at_8
[0x18];
5700 u8 reserved_at_40
[0x40];
5703 struct mlx5_ifc_destroy_tis_in_bits
{
5705 u8 reserved_at_10
[0x10];
5707 u8 reserved_at_20
[0x10];
5710 u8 reserved_at_40
[0x8];
5713 u8 reserved_at_60
[0x20];
5716 struct mlx5_ifc_destroy_tir_out_bits
{
5718 u8 reserved_at_8
[0x18];
5722 u8 reserved_at_40
[0x40];
5725 struct mlx5_ifc_destroy_tir_in_bits
{
5727 u8 reserved_at_10
[0x10];
5729 u8 reserved_at_20
[0x10];
5732 u8 reserved_at_40
[0x8];
5735 u8 reserved_at_60
[0x20];
5738 struct mlx5_ifc_destroy_srq_out_bits
{
5740 u8 reserved_at_8
[0x18];
5744 u8 reserved_at_40
[0x40];
5747 struct mlx5_ifc_destroy_srq_in_bits
{
5749 u8 reserved_at_10
[0x10];
5751 u8 reserved_at_20
[0x10];
5754 u8 reserved_at_40
[0x8];
5757 u8 reserved_at_60
[0x20];
5760 struct mlx5_ifc_destroy_sq_out_bits
{
5762 u8 reserved_at_8
[0x18];
5766 u8 reserved_at_40
[0x40];
5769 struct mlx5_ifc_destroy_sq_in_bits
{
5771 u8 reserved_at_10
[0x10];
5773 u8 reserved_at_20
[0x10];
5776 u8 reserved_at_40
[0x8];
5779 u8 reserved_at_60
[0x20];
5782 struct mlx5_ifc_destroy_scheduling_element_out_bits
{
5784 u8 reserved_at_8
[0x18];
5788 u8 reserved_at_40
[0x1c0];
5791 struct mlx5_ifc_destroy_scheduling_element_in_bits
{
5793 u8 reserved_at_10
[0x10];
5795 u8 reserved_at_20
[0x10];
5798 u8 scheduling_hierarchy
[0x8];
5799 u8 reserved_at_48
[0x18];
5801 u8 scheduling_element_id
[0x20];
5803 u8 reserved_at_80
[0x180];
5806 struct mlx5_ifc_destroy_rqt_out_bits
{
5808 u8 reserved_at_8
[0x18];
5812 u8 reserved_at_40
[0x40];
5815 struct mlx5_ifc_destroy_rqt_in_bits
{
5817 u8 reserved_at_10
[0x10];
5819 u8 reserved_at_20
[0x10];
5822 u8 reserved_at_40
[0x8];
5825 u8 reserved_at_60
[0x20];
5828 struct mlx5_ifc_destroy_rq_out_bits
{
5830 u8 reserved_at_8
[0x18];
5834 u8 reserved_at_40
[0x40];
5837 struct mlx5_ifc_destroy_rq_in_bits
{
5839 u8 reserved_at_10
[0x10];
5841 u8 reserved_at_20
[0x10];
5844 u8 reserved_at_40
[0x8];
5847 u8 reserved_at_60
[0x20];
5850 struct mlx5_ifc_destroy_rmp_out_bits
{
5852 u8 reserved_at_8
[0x18];
5856 u8 reserved_at_40
[0x40];
5859 struct mlx5_ifc_destroy_rmp_in_bits
{
5861 u8 reserved_at_10
[0x10];
5863 u8 reserved_at_20
[0x10];
5866 u8 reserved_at_40
[0x8];
5869 u8 reserved_at_60
[0x20];
5872 struct mlx5_ifc_destroy_qp_out_bits
{
5874 u8 reserved_at_8
[0x18];
5878 u8 reserved_at_40
[0x40];
5881 struct mlx5_ifc_destroy_qp_in_bits
{
5883 u8 reserved_at_10
[0x10];
5885 u8 reserved_at_20
[0x10];
5888 u8 reserved_at_40
[0x8];
5891 u8 reserved_at_60
[0x20];
5894 struct mlx5_ifc_destroy_psv_out_bits
{
5896 u8 reserved_at_8
[0x18];
5900 u8 reserved_at_40
[0x40];
5903 struct mlx5_ifc_destroy_psv_in_bits
{
5905 u8 reserved_at_10
[0x10];
5907 u8 reserved_at_20
[0x10];
5910 u8 reserved_at_40
[0x8];
5913 u8 reserved_at_60
[0x20];
5916 struct mlx5_ifc_destroy_mkey_out_bits
{
5918 u8 reserved_at_8
[0x18];
5922 u8 reserved_at_40
[0x40];
5925 struct mlx5_ifc_destroy_mkey_in_bits
{
5927 u8 reserved_at_10
[0x10];
5929 u8 reserved_at_20
[0x10];
5932 u8 reserved_at_40
[0x8];
5933 u8 mkey_index
[0x18];
5935 u8 reserved_at_60
[0x20];
5938 struct mlx5_ifc_destroy_flow_table_out_bits
{
5940 u8 reserved_at_8
[0x18];
5944 u8 reserved_at_40
[0x40];
5947 struct mlx5_ifc_destroy_flow_table_in_bits
{
5949 u8 reserved_at_10
[0x10];
5951 u8 reserved_at_20
[0x10];
5954 u8 other_vport
[0x1];
5955 u8 reserved_at_41
[0xf];
5956 u8 vport_number
[0x10];
5958 u8 reserved_at_60
[0x20];
5961 u8 reserved_at_88
[0x18];
5963 u8 reserved_at_a0
[0x8];
5966 u8 reserved_at_c0
[0x140];
5969 struct mlx5_ifc_destroy_flow_group_out_bits
{
5971 u8 reserved_at_8
[0x18];
5975 u8 reserved_at_40
[0x40];
5978 struct mlx5_ifc_destroy_flow_group_in_bits
{
5980 u8 reserved_at_10
[0x10];
5982 u8 reserved_at_20
[0x10];
5985 u8 other_vport
[0x1];
5986 u8 reserved_at_41
[0xf];
5987 u8 vport_number
[0x10];
5989 u8 reserved_at_60
[0x20];
5992 u8 reserved_at_88
[0x18];
5994 u8 reserved_at_a0
[0x8];
5999 u8 reserved_at_e0
[0x120];
6002 struct mlx5_ifc_destroy_eq_out_bits
{
6004 u8 reserved_at_8
[0x18];
6008 u8 reserved_at_40
[0x40];
6011 struct mlx5_ifc_destroy_eq_in_bits
{
6013 u8 reserved_at_10
[0x10];
6015 u8 reserved_at_20
[0x10];
6018 u8 reserved_at_40
[0x18];
6021 u8 reserved_at_60
[0x20];
6024 struct mlx5_ifc_destroy_dct_out_bits
{
6026 u8 reserved_at_8
[0x18];
6030 u8 reserved_at_40
[0x40];
6033 struct mlx5_ifc_destroy_dct_in_bits
{
6035 u8 reserved_at_10
[0x10];
6037 u8 reserved_at_20
[0x10];
6040 u8 reserved_at_40
[0x8];
6043 u8 reserved_at_60
[0x20];
6046 struct mlx5_ifc_destroy_cq_out_bits
{
6048 u8 reserved_at_8
[0x18];
6052 u8 reserved_at_40
[0x40];
6055 struct mlx5_ifc_destroy_cq_in_bits
{
6057 u8 reserved_at_10
[0x10];
6059 u8 reserved_at_20
[0x10];
6062 u8 reserved_at_40
[0x8];
6065 u8 reserved_at_60
[0x20];
6068 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits
{
6070 u8 reserved_at_8
[0x18];
6074 u8 reserved_at_40
[0x40];
6077 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits
{
6079 u8 reserved_at_10
[0x10];
6081 u8 reserved_at_20
[0x10];
6084 u8 reserved_at_40
[0x20];
6086 u8 reserved_at_60
[0x10];
6087 u8 vxlan_udp_port
[0x10];
6090 struct mlx5_ifc_delete_l2_table_entry_out_bits
{
6092 u8 reserved_at_8
[0x18];
6096 u8 reserved_at_40
[0x40];
6099 struct mlx5_ifc_delete_l2_table_entry_in_bits
{
6101 u8 reserved_at_10
[0x10];
6103 u8 reserved_at_20
[0x10];
6106 u8 reserved_at_40
[0x60];
6108 u8 reserved_at_a0
[0x8];
6109 u8 table_index
[0x18];
6111 u8 reserved_at_c0
[0x140];
6114 struct mlx5_ifc_delete_fte_out_bits
{
6116 u8 reserved_at_8
[0x18];
6120 u8 reserved_at_40
[0x40];
6123 struct mlx5_ifc_delete_fte_in_bits
{
6125 u8 reserved_at_10
[0x10];
6127 u8 reserved_at_20
[0x10];
6130 u8 other_vport
[0x1];
6131 u8 reserved_at_41
[0xf];
6132 u8 vport_number
[0x10];
6134 u8 reserved_at_60
[0x20];
6137 u8 reserved_at_88
[0x18];
6139 u8 reserved_at_a0
[0x8];
6142 u8 reserved_at_c0
[0x40];
6144 u8 flow_index
[0x20];
6146 u8 reserved_at_120
[0xe0];
6149 struct mlx5_ifc_dealloc_xrcd_out_bits
{
6151 u8 reserved_at_8
[0x18];
6155 u8 reserved_at_40
[0x40];
6158 struct mlx5_ifc_dealloc_xrcd_in_bits
{
6160 u8 reserved_at_10
[0x10];
6162 u8 reserved_at_20
[0x10];
6165 u8 reserved_at_40
[0x8];
6168 u8 reserved_at_60
[0x20];
6171 struct mlx5_ifc_dealloc_uar_out_bits
{
6173 u8 reserved_at_8
[0x18];
6177 u8 reserved_at_40
[0x40];
6180 struct mlx5_ifc_dealloc_uar_in_bits
{
6182 u8 reserved_at_10
[0x10];
6184 u8 reserved_at_20
[0x10];
6187 u8 reserved_at_40
[0x8];
6190 u8 reserved_at_60
[0x20];
6193 struct mlx5_ifc_dealloc_transport_domain_out_bits
{
6195 u8 reserved_at_8
[0x18];
6199 u8 reserved_at_40
[0x40];
6202 struct mlx5_ifc_dealloc_transport_domain_in_bits
{
6204 u8 reserved_at_10
[0x10];
6206 u8 reserved_at_20
[0x10];
6209 u8 reserved_at_40
[0x8];
6210 u8 transport_domain
[0x18];
6212 u8 reserved_at_60
[0x20];
6215 struct mlx5_ifc_dealloc_q_counter_out_bits
{
6217 u8 reserved_at_8
[0x18];
6221 u8 reserved_at_40
[0x40];
6224 struct mlx5_ifc_dealloc_q_counter_in_bits
{
6226 u8 reserved_at_10
[0x10];
6228 u8 reserved_at_20
[0x10];
6231 u8 reserved_at_40
[0x18];
6232 u8 counter_set_id
[0x8];
6234 u8 reserved_at_60
[0x20];
6237 struct mlx5_ifc_dealloc_pd_out_bits
{
6239 u8 reserved_at_8
[0x18];
6243 u8 reserved_at_40
[0x40];
6246 struct mlx5_ifc_dealloc_pd_in_bits
{
6248 u8 reserved_at_10
[0x10];
6250 u8 reserved_at_20
[0x10];
6253 u8 reserved_at_40
[0x8];
6256 u8 reserved_at_60
[0x20];
6259 struct mlx5_ifc_dealloc_flow_counter_out_bits
{
6261 u8 reserved_at_8
[0x18];
6265 u8 reserved_at_40
[0x40];
6268 struct mlx5_ifc_dealloc_flow_counter_in_bits
{
6270 u8 reserved_at_10
[0x10];
6272 u8 reserved_at_20
[0x10];
6275 u8 reserved_at_40
[0x10];
6276 u8 flow_counter_id
[0x10];
6278 u8 reserved_at_60
[0x20];
6281 struct mlx5_ifc_create_xrq_out_bits
{
6283 u8 reserved_at_8
[0x18];
6287 u8 reserved_at_40
[0x8];
6290 u8 reserved_at_60
[0x20];
6293 struct mlx5_ifc_create_xrq_in_bits
{
6295 u8 reserved_at_10
[0x10];
6297 u8 reserved_at_20
[0x10];
6300 u8 reserved_at_40
[0x40];
6302 struct mlx5_ifc_xrqc_bits xrq_context
;
6305 struct mlx5_ifc_create_xrc_srq_out_bits
{
6307 u8 reserved_at_8
[0x18];
6311 u8 reserved_at_40
[0x8];
6314 u8 reserved_at_60
[0x20];
6317 struct mlx5_ifc_create_xrc_srq_in_bits
{
6319 u8 reserved_at_10
[0x10];
6321 u8 reserved_at_20
[0x10];
6324 u8 reserved_at_40
[0x40];
6326 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
6328 u8 reserved_at_280
[0x600];
6333 struct mlx5_ifc_create_tis_out_bits
{
6335 u8 reserved_at_8
[0x18];
6339 u8 reserved_at_40
[0x8];
6342 u8 reserved_at_60
[0x20];
6345 struct mlx5_ifc_create_tis_in_bits
{
6347 u8 reserved_at_10
[0x10];
6349 u8 reserved_at_20
[0x10];
6352 u8 reserved_at_40
[0xc0];
6354 struct mlx5_ifc_tisc_bits ctx
;
6357 struct mlx5_ifc_create_tir_out_bits
{
6359 u8 reserved_at_8
[0x18];
6363 u8 reserved_at_40
[0x8];
6366 u8 reserved_at_60
[0x20];
6369 struct mlx5_ifc_create_tir_in_bits
{
6371 u8 reserved_at_10
[0x10];
6373 u8 reserved_at_20
[0x10];
6376 u8 reserved_at_40
[0xc0];
6378 struct mlx5_ifc_tirc_bits ctx
;
6381 struct mlx5_ifc_create_srq_out_bits
{
6383 u8 reserved_at_8
[0x18];
6387 u8 reserved_at_40
[0x8];
6390 u8 reserved_at_60
[0x20];
6393 struct mlx5_ifc_create_srq_in_bits
{
6395 u8 reserved_at_10
[0x10];
6397 u8 reserved_at_20
[0x10];
6400 u8 reserved_at_40
[0x40];
6402 struct mlx5_ifc_srqc_bits srq_context_entry
;
6404 u8 reserved_at_280
[0x600];
6409 struct mlx5_ifc_create_sq_out_bits
{
6411 u8 reserved_at_8
[0x18];
6415 u8 reserved_at_40
[0x8];
6418 u8 reserved_at_60
[0x20];
6421 struct mlx5_ifc_create_sq_in_bits
{
6423 u8 reserved_at_10
[0x10];
6425 u8 reserved_at_20
[0x10];
6428 u8 reserved_at_40
[0xc0];
6430 struct mlx5_ifc_sqc_bits ctx
;
6433 struct mlx5_ifc_create_scheduling_element_out_bits
{
6435 u8 reserved_at_8
[0x18];
6439 u8 reserved_at_40
[0x40];
6441 u8 scheduling_element_id
[0x20];
6443 u8 reserved_at_a0
[0x160];
6446 struct mlx5_ifc_create_scheduling_element_in_bits
{
6448 u8 reserved_at_10
[0x10];
6450 u8 reserved_at_20
[0x10];
6453 u8 scheduling_hierarchy
[0x8];
6454 u8 reserved_at_48
[0x18];
6456 u8 reserved_at_60
[0xa0];
6458 struct mlx5_ifc_scheduling_context_bits scheduling_context
;
6460 u8 reserved_at_300
[0x100];
6463 struct mlx5_ifc_create_rqt_out_bits
{
6465 u8 reserved_at_8
[0x18];
6469 u8 reserved_at_40
[0x8];
6472 u8 reserved_at_60
[0x20];
6475 struct mlx5_ifc_create_rqt_in_bits
{
6477 u8 reserved_at_10
[0x10];
6479 u8 reserved_at_20
[0x10];
6482 u8 reserved_at_40
[0xc0];
6484 struct mlx5_ifc_rqtc_bits rqt_context
;
6487 struct mlx5_ifc_create_rq_out_bits
{
6489 u8 reserved_at_8
[0x18];
6493 u8 reserved_at_40
[0x8];
6496 u8 reserved_at_60
[0x20];
6499 struct mlx5_ifc_create_rq_in_bits
{
6501 u8 reserved_at_10
[0x10];
6503 u8 reserved_at_20
[0x10];
6506 u8 reserved_at_40
[0xc0];
6508 struct mlx5_ifc_rqc_bits ctx
;
6511 struct mlx5_ifc_create_rmp_out_bits
{
6513 u8 reserved_at_8
[0x18];
6517 u8 reserved_at_40
[0x8];
6520 u8 reserved_at_60
[0x20];
6523 struct mlx5_ifc_create_rmp_in_bits
{
6525 u8 reserved_at_10
[0x10];
6527 u8 reserved_at_20
[0x10];
6530 u8 reserved_at_40
[0xc0];
6532 struct mlx5_ifc_rmpc_bits ctx
;
6535 struct mlx5_ifc_create_qp_out_bits
{
6537 u8 reserved_at_8
[0x18];
6541 u8 reserved_at_40
[0x8];
6544 u8 reserved_at_60
[0x20];
6547 struct mlx5_ifc_create_qp_in_bits
{
6549 u8 reserved_at_10
[0x10];
6551 u8 reserved_at_20
[0x10];
6554 u8 reserved_at_40
[0x40];
6556 u8 opt_param_mask
[0x20];
6558 u8 reserved_at_a0
[0x20];
6560 struct mlx5_ifc_qpc_bits qpc
;
6562 u8 reserved_at_800
[0x80];
6567 struct mlx5_ifc_create_psv_out_bits
{
6569 u8 reserved_at_8
[0x18];
6573 u8 reserved_at_40
[0x40];
6575 u8 reserved_at_80
[0x8];
6576 u8 psv0_index
[0x18];
6578 u8 reserved_at_a0
[0x8];
6579 u8 psv1_index
[0x18];
6581 u8 reserved_at_c0
[0x8];
6582 u8 psv2_index
[0x18];
6584 u8 reserved_at_e0
[0x8];
6585 u8 psv3_index
[0x18];
6588 struct mlx5_ifc_create_psv_in_bits
{
6590 u8 reserved_at_10
[0x10];
6592 u8 reserved_at_20
[0x10];
6596 u8 reserved_at_44
[0x4];
6599 u8 reserved_at_60
[0x20];
6602 struct mlx5_ifc_create_mkey_out_bits
{
6604 u8 reserved_at_8
[0x18];
6608 u8 reserved_at_40
[0x8];
6609 u8 mkey_index
[0x18];
6611 u8 reserved_at_60
[0x20];
6614 struct mlx5_ifc_create_mkey_in_bits
{
6616 u8 reserved_at_10
[0x10];
6618 u8 reserved_at_20
[0x10];
6621 u8 reserved_at_40
[0x20];
6624 u8 reserved_at_61
[0x1f];
6626 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
6628 u8 reserved_at_280
[0x80];
6630 u8 translations_octword_actual_size
[0x20];
6632 u8 reserved_at_320
[0x560];
6634 u8 klm_pas_mtt
[0][0x20];
6637 struct mlx5_ifc_create_flow_table_out_bits
{
6639 u8 reserved_at_8
[0x18];
6643 u8 reserved_at_40
[0x8];
6646 u8 reserved_at_60
[0x20];
6649 struct mlx5_ifc_flow_table_context_bits
{
6652 u8 reserved_at_2
[0x2];
6653 u8 table_miss_action
[0x4];
6655 u8 reserved_at_10
[0x8];
6658 u8 reserved_at_20
[0x8];
6659 u8 table_miss_id
[0x18];
6661 u8 reserved_at_40
[0x8];
6662 u8 lag_master_next_table_id
[0x18];
6664 u8 reserved_at_60
[0xe0];
6667 struct mlx5_ifc_create_flow_table_in_bits
{
6669 u8 reserved_at_10
[0x10];
6671 u8 reserved_at_20
[0x10];
6674 u8 other_vport
[0x1];
6675 u8 reserved_at_41
[0xf];
6676 u8 vport_number
[0x10];
6678 u8 reserved_at_60
[0x20];
6681 u8 reserved_at_88
[0x18];
6683 u8 reserved_at_a0
[0x20];
6685 struct mlx5_ifc_flow_table_context_bits flow_table_context
;
6688 struct mlx5_ifc_create_flow_group_out_bits
{
6690 u8 reserved_at_8
[0x18];
6694 u8 reserved_at_40
[0x8];
6697 u8 reserved_at_60
[0x20];
6701 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
6702 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
6703 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
6706 struct mlx5_ifc_create_flow_group_in_bits
{
6708 u8 reserved_at_10
[0x10];
6710 u8 reserved_at_20
[0x10];
6713 u8 other_vport
[0x1];
6714 u8 reserved_at_41
[0xf];
6715 u8 vport_number
[0x10];
6717 u8 reserved_at_60
[0x20];
6720 u8 reserved_at_88
[0x18];
6722 u8 reserved_at_a0
[0x8];
6725 u8 reserved_at_c0
[0x20];
6727 u8 start_flow_index
[0x20];
6729 u8 reserved_at_100
[0x20];
6731 u8 end_flow_index
[0x20];
6733 u8 reserved_at_140
[0xa0];
6735 u8 reserved_at_1e0
[0x18];
6736 u8 match_criteria_enable
[0x8];
6738 struct mlx5_ifc_fte_match_param_bits match_criteria
;
6740 u8 reserved_at_1200
[0xe00];
6743 struct mlx5_ifc_create_eq_out_bits
{
6745 u8 reserved_at_8
[0x18];
6749 u8 reserved_at_40
[0x18];
6752 u8 reserved_at_60
[0x20];
6755 struct mlx5_ifc_create_eq_in_bits
{
6757 u8 reserved_at_10
[0x10];
6759 u8 reserved_at_20
[0x10];
6762 u8 reserved_at_40
[0x40];
6764 struct mlx5_ifc_eqc_bits eq_context_entry
;
6766 u8 reserved_at_280
[0x40];
6768 u8 event_bitmask
[0x40];
6770 u8 reserved_at_300
[0x580];
6775 struct mlx5_ifc_create_dct_out_bits
{
6777 u8 reserved_at_8
[0x18];
6781 u8 reserved_at_40
[0x8];
6784 u8 reserved_at_60
[0x20];
6787 struct mlx5_ifc_create_dct_in_bits
{
6789 u8 reserved_at_10
[0x10];
6791 u8 reserved_at_20
[0x10];
6794 u8 reserved_at_40
[0x40];
6796 struct mlx5_ifc_dctc_bits dct_context_entry
;
6798 u8 reserved_at_280
[0x180];
6801 struct mlx5_ifc_create_cq_out_bits
{
6803 u8 reserved_at_8
[0x18];
6807 u8 reserved_at_40
[0x8];
6810 u8 reserved_at_60
[0x20];
6813 struct mlx5_ifc_create_cq_in_bits
{
6815 u8 reserved_at_10
[0x10];
6817 u8 reserved_at_20
[0x10];
6820 u8 reserved_at_40
[0x40];
6822 struct mlx5_ifc_cqc_bits cq_context
;
6824 u8 reserved_at_280
[0x600];
6829 struct mlx5_ifc_config_int_moderation_out_bits
{
6831 u8 reserved_at_8
[0x18];
6835 u8 reserved_at_40
[0x4];
6837 u8 int_vector
[0x10];
6839 u8 reserved_at_60
[0x20];
6843 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE
= 0x0,
6844 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ
= 0x1,
6847 struct mlx5_ifc_config_int_moderation_in_bits
{
6849 u8 reserved_at_10
[0x10];
6851 u8 reserved_at_20
[0x10];
6854 u8 reserved_at_40
[0x4];
6856 u8 int_vector
[0x10];
6858 u8 reserved_at_60
[0x20];
6861 struct mlx5_ifc_attach_to_mcg_out_bits
{
6863 u8 reserved_at_8
[0x18];
6867 u8 reserved_at_40
[0x40];
6870 struct mlx5_ifc_attach_to_mcg_in_bits
{
6872 u8 reserved_at_10
[0x10];
6874 u8 reserved_at_20
[0x10];
6877 u8 reserved_at_40
[0x8];
6880 u8 reserved_at_60
[0x20];
6882 u8 multicast_gid
[16][0x8];
6885 struct mlx5_ifc_arm_xrq_out_bits
{
6887 u8 reserved_at_8
[0x18];
6891 u8 reserved_at_40
[0x40];
6894 struct mlx5_ifc_arm_xrq_in_bits
{
6896 u8 reserved_at_10
[0x10];
6898 u8 reserved_at_20
[0x10];
6901 u8 reserved_at_40
[0x8];
6904 u8 reserved_at_60
[0x10];
6908 struct mlx5_ifc_arm_xrc_srq_out_bits
{
6910 u8 reserved_at_8
[0x18];
6914 u8 reserved_at_40
[0x40];
6918 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ
= 0x1,
6921 struct mlx5_ifc_arm_xrc_srq_in_bits
{
6923 u8 reserved_at_10
[0x10];
6925 u8 reserved_at_20
[0x10];
6928 u8 reserved_at_40
[0x8];
6931 u8 reserved_at_60
[0x10];
6935 struct mlx5_ifc_arm_rq_out_bits
{
6937 u8 reserved_at_8
[0x18];
6941 u8 reserved_at_40
[0x40];
6945 MLX5_ARM_RQ_IN_OP_MOD_SRQ
= 0x1,
6946 MLX5_ARM_RQ_IN_OP_MOD_XRQ
= 0x2,
6949 struct mlx5_ifc_arm_rq_in_bits
{
6951 u8 reserved_at_10
[0x10];
6953 u8 reserved_at_20
[0x10];
6956 u8 reserved_at_40
[0x8];
6957 u8 srq_number
[0x18];
6959 u8 reserved_at_60
[0x10];
6963 struct mlx5_ifc_arm_dct_out_bits
{
6965 u8 reserved_at_8
[0x18];
6969 u8 reserved_at_40
[0x40];
6972 struct mlx5_ifc_arm_dct_in_bits
{
6974 u8 reserved_at_10
[0x10];
6976 u8 reserved_at_20
[0x10];
6979 u8 reserved_at_40
[0x8];
6980 u8 dct_number
[0x18];
6982 u8 reserved_at_60
[0x20];
6985 struct mlx5_ifc_alloc_xrcd_out_bits
{
6987 u8 reserved_at_8
[0x18];
6991 u8 reserved_at_40
[0x8];
6994 u8 reserved_at_60
[0x20];
6997 struct mlx5_ifc_alloc_xrcd_in_bits
{
6999 u8 reserved_at_10
[0x10];
7001 u8 reserved_at_20
[0x10];
7004 u8 reserved_at_40
[0x40];
7007 struct mlx5_ifc_alloc_uar_out_bits
{
7009 u8 reserved_at_8
[0x18];
7013 u8 reserved_at_40
[0x8];
7016 u8 reserved_at_60
[0x20];
7019 struct mlx5_ifc_alloc_uar_in_bits
{
7021 u8 reserved_at_10
[0x10];
7023 u8 reserved_at_20
[0x10];
7026 u8 reserved_at_40
[0x40];
7029 struct mlx5_ifc_alloc_transport_domain_out_bits
{
7031 u8 reserved_at_8
[0x18];
7035 u8 reserved_at_40
[0x8];
7036 u8 transport_domain
[0x18];
7038 u8 reserved_at_60
[0x20];
7041 struct mlx5_ifc_alloc_transport_domain_in_bits
{
7043 u8 reserved_at_10
[0x10];
7045 u8 reserved_at_20
[0x10];
7048 u8 reserved_at_40
[0x40];
7051 struct mlx5_ifc_alloc_q_counter_out_bits
{
7053 u8 reserved_at_8
[0x18];
7057 u8 reserved_at_40
[0x18];
7058 u8 counter_set_id
[0x8];
7060 u8 reserved_at_60
[0x20];
7063 struct mlx5_ifc_alloc_q_counter_in_bits
{
7065 u8 reserved_at_10
[0x10];
7067 u8 reserved_at_20
[0x10];
7070 u8 reserved_at_40
[0x40];
7073 struct mlx5_ifc_alloc_pd_out_bits
{
7075 u8 reserved_at_8
[0x18];
7079 u8 reserved_at_40
[0x8];
7082 u8 reserved_at_60
[0x20];
7085 struct mlx5_ifc_alloc_pd_in_bits
{
7087 u8 reserved_at_10
[0x10];
7089 u8 reserved_at_20
[0x10];
7092 u8 reserved_at_40
[0x40];
7095 struct mlx5_ifc_alloc_flow_counter_out_bits
{
7097 u8 reserved_at_8
[0x18];
7101 u8 reserved_at_40
[0x10];
7102 u8 flow_counter_id
[0x10];
7104 u8 reserved_at_60
[0x20];
7107 struct mlx5_ifc_alloc_flow_counter_in_bits
{
7109 u8 reserved_at_10
[0x10];
7111 u8 reserved_at_20
[0x10];
7114 u8 reserved_at_40
[0x40];
7117 struct mlx5_ifc_add_vxlan_udp_dport_out_bits
{
7119 u8 reserved_at_8
[0x18];
7123 u8 reserved_at_40
[0x40];
7126 struct mlx5_ifc_add_vxlan_udp_dport_in_bits
{
7128 u8 reserved_at_10
[0x10];
7130 u8 reserved_at_20
[0x10];
7133 u8 reserved_at_40
[0x20];
7135 u8 reserved_at_60
[0x10];
7136 u8 vxlan_udp_port
[0x10];
7139 struct mlx5_ifc_set_rate_limit_out_bits
{
7141 u8 reserved_at_8
[0x18];
7145 u8 reserved_at_40
[0x40];
7148 struct mlx5_ifc_set_rate_limit_in_bits
{
7150 u8 reserved_at_10
[0x10];
7152 u8 reserved_at_20
[0x10];
7155 u8 reserved_at_40
[0x10];
7156 u8 rate_limit_index
[0x10];
7158 u8 reserved_at_60
[0x20];
7160 u8 rate_limit
[0x20];
7163 struct mlx5_ifc_access_register_out_bits
{
7165 u8 reserved_at_8
[0x18];
7169 u8 reserved_at_40
[0x40];
7171 u8 register_data
[0][0x20];
7175 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE
= 0x0,
7176 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ
= 0x1,
7179 struct mlx5_ifc_access_register_in_bits
{
7181 u8 reserved_at_10
[0x10];
7183 u8 reserved_at_20
[0x10];
7186 u8 reserved_at_40
[0x10];
7187 u8 register_id
[0x10];
7191 u8 register_data
[0][0x20];
7194 struct mlx5_ifc_sltp_reg_bits
{
7199 u8 reserved_at_12
[0x2];
7201 u8 reserved_at_18
[0x8];
7203 u8 reserved_at_20
[0x20];
7205 u8 reserved_at_40
[0x7];
7211 u8 reserved_at_60
[0xc];
7212 u8 ob_preemp_mode
[0x4];
7216 u8 reserved_at_80
[0x20];
7219 struct mlx5_ifc_slrg_reg_bits
{
7224 u8 reserved_at_12
[0x2];
7226 u8 reserved_at_18
[0x8];
7228 u8 time_to_link_up
[0x10];
7229 u8 reserved_at_30
[0xc];
7230 u8 grade_lane_speed
[0x4];
7232 u8 grade_version
[0x8];
7235 u8 reserved_at_60
[0x4];
7236 u8 height_grade_type
[0x4];
7237 u8 height_grade
[0x18];
7242 u8 reserved_at_a0
[0x10];
7243 u8 height_sigma
[0x10];
7245 u8 reserved_at_c0
[0x20];
7247 u8 reserved_at_e0
[0x4];
7248 u8 phase_grade_type
[0x4];
7249 u8 phase_grade
[0x18];
7251 u8 reserved_at_100
[0x8];
7252 u8 phase_eo_pos
[0x8];
7253 u8 reserved_at_110
[0x8];
7254 u8 phase_eo_neg
[0x8];
7256 u8 ffe_set_tested
[0x10];
7257 u8 test_errors_per_lane
[0x10];
7260 struct mlx5_ifc_pvlc_reg_bits
{
7261 u8 reserved_at_0
[0x8];
7263 u8 reserved_at_10
[0x10];
7265 u8 reserved_at_20
[0x1c];
7268 u8 reserved_at_40
[0x1c];
7271 u8 reserved_at_60
[0x1c];
7272 u8 vl_operational
[0x4];
7275 struct mlx5_ifc_pude_reg_bits
{
7278 u8 reserved_at_10
[0x4];
7279 u8 admin_status
[0x4];
7280 u8 reserved_at_18
[0x4];
7281 u8 oper_status
[0x4];
7283 u8 reserved_at_20
[0x60];
7286 struct mlx5_ifc_ptys_reg_bits
{
7287 u8 reserved_at_0
[0x1];
7288 u8 an_disable_admin
[0x1];
7289 u8 an_disable_cap
[0x1];
7290 u8 reserved_at_3
[0x5];
7292 u8 reserved_at_10
[0xd];
7296 u8 reserved_at_24
[0x3c];
7298 u8 eth_proto_capability
[0x20];
7300 u8 ib_link_width_capability
[0x10];
7301 u8 ib_proto_capability
[0x10];
7303 u8 reserved_at_a0
[0x20];
7305 u8 eth_proto_admin
[0x20];
7307 u8 ib_link_width_admin
[0x10];
7308 u8 ib_proto_admin
[0x10];
7310 u8 reserved_at_100
[0x20];
7312 u8 eth_proto_oper
[0x20];
7314 u8 ib_link_width_oper
[0x10];
7315 u8 ib_proto_oper
[0x10];
7317 u8 reserved_at_160
[0x1c];
7318 u8 connector_type
[0x4];
7320 u8 eth_proto_lp_advertise
[0x20];
7322 u8 reserved_at_1a0
[0x60];
7325 struct mlx5_ifc_mlcr_reg_bits
{
7326 u8 reserved_at_0
[0x8];
7328 u8 reserved_at_10
[0x20];
7330 u8 beacon_duration
[0x10];
7331 u8 reserved_at_40
[0x10];
7333 u8 beacon_remain
[0x10];
7336 struct mlx5_ifc_ptas_reg_bits
{
7337 u8 reserved_at_0
[0x20];
7339 u8 algorithm_options
[0x10];
7340 u8 reserved_at_30
[0x4];
7341 u8 repetitions_mode
[0x4];
7342 u8 num_of_repetitions
[0x8];
7344 u8 grade_version
[0x8];
7345 u8 height_grade_type
[0x4];
7346 u8 phase_grade_type
[0x4];
7347 u8 height_grade_weight
[0x8];
7348 u8 phase_grade_weight
[0x8];
7350 u8 gisim_measure_bits
[0x10];
7351 u8 adaptive_tap_measure_bits
[0x10];
7353 u8 ber_bath_high_error_threshold
[0x10];
7354 u8 ber_bath_mid_error_threshold
[0x10];
7356 u8 ber_bath_low_error_threshold
[0x10];
7357 u8 one_ratio_high_threshold
[0x10];
7359 u8 one_ratio_high_mid_threshold
[0x10];
7360 u8 one_ratio_low_mid_threshold
[0x10];
7362 u8 one_ratio_low_threshold
[0x10];
7363 u8 ndeo_error_threshold
[0x10];
7365 u8 mixer_offset_step_size
[0x10];
7366 u8 reserved_at_110
[0x8];
7367 u8 mix90_phase_for_voltage_bath
[0x8];
7369 u8 mixer_offset_start
[0x10];
7370 u8 mixer_offset_end
[0x10];
7372 u8 reserved_at_140
[0x15];
7373 u8 ber_test_time
[0xb];
7376 struct mlx5_ifc_pspa_reg_bits
{
7380 u8 reserved_at_18
[0x8];
7382 u8 reserved_at_20
[0x20];
7385 struct mlx5_ifc_pqdr_reg_bits
{
7386 u8 reserved_at_0
[0x8];
7388 u8 reserved_at_10
[0x5];
7390 u8 reserved_at_18
[0x6];
7393 u8 reserved_at_20
[0x20];
7395 u8 reserved_at_40
[0x10];
7396 u8 min_threshold
[0x10];
7398 u8 reserved_at_60
[0x10];
7399 u8 max_threshold
[0x10];
7401 u8 reserved_at_80
[0x10];
7402 u8 mark_probability_denominator
[0x10];
7404 u8 reserved_at_a0
[0x60];
7407 struct mlx5_ifc_ppsc_reg_bits
{
7408 u8 reserved_at_0
[0x8];
7410 u8 reserved_at_10
[0x10];
7412 u8 reserved_at_20
[0x60];
7414 u8 reserved_at_80
[0x1c];
7417 u8 reserved_at_a0
[0x1c];
7418 u8 wrps_status
[0x4];
7420 u8 reserved_at_c0
[0x8];
7421 u8 up_threshold
[0x8];
7422 u8 reserved_at_d0
[0x8];
7423 u8 down_threshold
[0x8];
7425 u8 reserved_at_e0
[0x20];
7427 u8 reserved_at_100
[0x1c];
7430 u8 reserved_at_120
[0x1c];
7431 u8 srps_status
[0x4];
7433 u8 reserved_at_140
[0x40];
7436 struct mlx5_ifc_pplr_reg_bits
{
7437 u8 reserved_at_0
[0x8];
7439 u8 reserved_at_10
[0x10];
7441 u8 reserved_at_20
[0x8];
7443 u8 reserved_at_30
[0x8];
7447 struct mlx5_ifc_pplm_reg_bits
{
7448 u8 reserved_at_0
[0x8];
7450 u8 reserved_at_10
[0x10];
7452 u8 reserved_at_20
[0x20];
7454 u8 port_profile_mode
[0x8];
7455 u8 static_port_profile
[0x8];
7456 u8 active_port_profile
[0x8];
7457 u8 reserved_at_58
[0x8];
7459 u8 retransmission_active
[0x8];
7460 u8 fec_mode_active
[0x18];
7462 u8 reserved_at_80
[0x20];
7465 struct mlx5_ifc_ppcnt_reg_bits
{
7469 u8 reserved_at_12
[0x8];
7473 u8 reserved_at_21
[0x1c];
7476 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set
;
7479 struct mlx5_ifc_mpcnt_reg_bits
{
7480 u8 reserved_at_0
[0x8];
7482 u8 reserved_at_10
[0xa];
7486 u8 reserved_at_21
[0x1f];
7488 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set
;
7491 struct mlx5_ifc_ppad_reg_bits
{
7492 u8 reserved_at_0
[0x3];
7494 u8 reserved_at_4
[0x4];
7500 u8 reserved_at_40
[0x40];
7503 struct mlx5_ifc_pmtu_reg_bits
{
7504 u8 reserved_at_0
[0x8];
7506 u8 reserved_at_10
[0x10];
7509 u8 reserved_at_30
[0x10];
7512 u8 reserved_at_50
[0x10];
7515 u8 reserved_at_70
[0x10];
7518 struct mlx5_ifc_pmpr_reg_bits
{
7519 u8 reserved_at_0
[0x8];
7521 u8 reserved_at_10
[0x10];
7523 u8 reserved_at_20
[0x18];
7524 u8 attenuation_5g
[0x8];
7526 u8 reserved_at_40
[0x18];
7527 u8 attenuation_7g
[0x8];
7529 u8 reserved_at_60
[0x18];
7530 u8 attenuation_12g
[0x8];
7533 struct mlx5_ifc_pmpe_reg_bits
{
7534 u8 reserved_at_0
[0x8];
7536 u8 reserved_at_10
[0xc];
7537 u8 module_status
[0x4];
7539 u8 reserved_at_20
[0x60];
7542 struct mlx5_ifc_pmpc_reg_bits
{
7543 u8 module_state_updated
[32][0x8];
7546 struct mlx5_ifc_pmlpn_reg_bits
{
7547 u8 reserved_at_0
[0x4];
7548 u8 mlpn_status
[0x4];
7550 u8 reserved_at_10
[0x10];
7553 u8 reserved_at_21
[0x1f];
7556 struct mlx5_ifc_pmlp_reg_bits
{
7558 u8 reserved_at_1
[0x7];
7560 u8 reserved_at_10
[0x8];
7563 u8 lane0_module_mapping
[0x20];
7565 u8 lane1_module_mapping
[0x20];
7567 u8 lane2_module_mapping
[0x20];
7569 u8 lane3_module_mapping
[0x20];
7571 u8 reserved_at_a0
[0x160];
7574 struct mlx5_ifc_pmaos_reg_bits
{
7575 u8 reserved_at_0
[0x8];
7577 u8 reserved_at_10
[0x4];
7578 u8 admin_status
[0x4];
7579 u8 reserved_at_18
[0x4];
7580 u8 oper_status
[0x4];
7584 u8 reserved_at_22
[0x1c];
7587 u8 reserved_at_40
[0x40];
7590 struct mlx5_ifc_plpc_reg_bits
{
7591 u8 reserved_at_0
[0x4];
7593 u8 reserved_at_10
[0x4];
7595 u8 reserved_at_18
[0x8];
7597 u8 reserved_at_20
[0x10];
7598 u8 lane_speed
[0x10];
7600 u8 reserved_at_40
[0x17];
7602 u8 fec_mode_policy
[0x8];
7604 u8 retransmission_capability
[0x8];
7605 u8 fec_mode_capability
[0x18];
7607 u8 retransmission_support_admin
[0x8];
7608 u8 fec_mode_support_admin
[0x18];
7610 u8 retransmission_request_admin
[0x8];
7611 u8 fec_mode_request_admin
[0x18];
7613 u8 reserved_at_c0
[0x80];
7616 struct mlx5_ifc_plib_reg_bits
{
7617 u8 reserved_at_0
[0x8];
7619 u8 reserved_at_10
[0x8];
7622 u8 reserved_at_20
[0x60];
7625 struct mlx5_ifc_plbf_reg_bits
{
7626 u8 reserved_at_0
[0x8];
7628 u8 reserved_at_10
[0xd];
7631 u8 reserved_at_20
[0x20];
7634 struct mlx5_ifc_pipg_reg_bits
{
7635 u8 reserved_at_0
[0x8];
7637 u8 reserved_at_10
[0x10];
7640 u8 reserved_at_21
[0x19];
7642 u8 reserved_at_3e
[0x2];
7645 struct mlx5_ifc_pifr_reg_bits
{
7646 u8 reserved_at_0
[0x8];
7648 u8 reserved_at_10
[0x10];
7650 u8 reserved_at_20
[0xe0];
7652 u8 port_filter
[8][0x20];
7654 u8 port_filter_update_en
[8][0x20];
7657 struct mlx5_ifc_pfcc_reg_bits
{
7658 u8 reserved_at_0
[0x8];
7660 u8 reserved_at_10
[0x10];
7663 u8 reserved_at_24
[0x4];
7664 u8 prio_mask_tx
[0x8];
7665 u8 reserved_at_30
[0x8];
7666 u8 prio_mask_rx
[0x8];
7670 u8 reserved_at_42
[0x6];
7672 u8 reserved_at_50
[0x10];
7676 u8 reserved_at_62
[0x6];
7678 u8 reserved_at_70
[0x10];
7680 u8 reserved_at_80
[0x80];
7683 struct mlx5_ifc_pelc_reg_bits
{
7685 u8 reserved_at_4
[0x4];
7687 u8 reserved_at_10
[0x10];
7690 u8 op_capability
[0x8];
7696 u8 capability
[0x40];
7702 u8 reserved_at_140
[0x80];
7705 struct mlx5_ifc_peir_reg_bits
{
7706 u8 reserved_at_0
[0x8];
7708 u8 reserved_at_10
[0x10];
7710 u8 reserved_at_20
[0xc];
7711 u8 error_count
[0x4];
7712 u8 reserved_at_30
[0x10];
7714 u8 reserved_at_40
[0xc];
7716 u8 reserved_at_50
[0x8];
7720 struct mlx5_ifc_pcam_enhanced_features_bits
{
7721 u8 reserved_at_0
[0x7c];
7723 u8 ptys_connector_type
[0x1];
7724 u8 reserved_at_7d
[0x1];
7725 u8 ppcnt_discard_group
[0x1];
7726 u8 ppcnt_statistical_group
[0x1];
7729 struct mlx5_ifc_pcam_reg_bits
{
7730 u8 reserved_at_0
[0x8];
7731 u8 feature_group
[0x8];
7732 u8 reserved_at_10
[0x8];
7733 u8 access_reg_group
[0x8];
7735 u8 reserved_at_20
[0x20];
7738 u8 reserved_at_0
[0x80];
7739 } port_access_reg_cap_mask
;
7741 u8 reserved_at_c0
[0x80];
7744 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features
;
7745 u8 reserved_at_0
[0x80];
7748 u8 reserved_at_1c0
[0xc0];
7751 struct mlx5_ifc_mcam_enhanced_features_bits
{
7752 u8 reserved_at_0
[0x7d];
7754 u8 mtpps_enh_out_per_adj
[0x1];
7756 u8 pcie_performance_group
[0x1];
7759 struct mlx5_ifc_mcam_access_reg_bits
{
7760 u8 reserved_at_0
[0x1c];
7764 u8 reserved_at_1f
[0x1];
7766 u8 regs_95_to_64
[0x20];
7767 u8 regs_63_to_32
[0x20];
7768 u8 regs_31_to_0
[0x20];
7771 struct mlx5_ifc_mcam_reg_bits
{
7772 u8 reserved_at_0
[0x8];
7773 u8 feature_group
[0x8];
7774 u8 reserved_at_10
[0x8];
7775 u8 access_reg_group
[0x8];
7777 u8 reserved_at_20
[0x20];
7780 struct mlx5_ifc_mcam_access_reg_bits access_regs
;
7781 u8 reserved_at_0
[0x80];
7782 } mng_access_reg_cap_mask
;
7784 u8 reserved_at_c0
[0x80];
7787 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features
;
7788 u8 reserved_at_0
[0x80];
7789 } mng_feature_cap_mask
;
7791 u8 reserved_at_1c0
[0x80];
7794 struct mlx5_ifc_pcap_reg_bits
{
7795 u8 reserved_at_0
[0x8];
7797 u8 reserved_at_10
[0x10];
7799 u8 port_capability_mask
[4][0x20];
7802 struct mlx5_ifc_paos_reg_bits
{
7805 u8 reserved_at_10
[0x4];
7806 u8 admin_status
[0x4];
7807 u8 reserved_at_18
[0x4];
7808 u8 oper_status
[0x4];
7812 u8 reserved_at_22
[0x1c];
7815 u8 reserved_at_40
[0x40];
7818 struct mlx5_ifc_pamp_reg_bits
{
7819 u8 reserved_at_0
[0x8];
7820 u8 opamp_group
[0x8];
7821 u8 reserved_at_10
[0xc];
7822 u8 opamp_group_type
[0x4];
7824 u8 start_index
[0x10];
7825 u8 reserved_at_30
[0x4];
7826 u8 num_of_indices
[0xc];
7828 u8 index_data
[18][0x10];
7831 struct mlx5_ifc_pcmr_reg_bits
{
7832 u8 reserved_at_0
[0x8];
7834 u8 reserved_at_10
[0x2e];
7836 u8 reserved_at_3f
[0x1f];
7838 u8 reserved_at_5f
[0x1];
7841 struct mlx5_ifc_lane_2_module_mapping_bits
{
7842 u8 reserved_at_0
[0x6];
7844 u8 reserved_at_8
[0x6];
7846 u8 reserved_at_10
[0x8];
7850 struct mlx5_ifc_bufferx_reg_bits
{
7851 u8 reserved_at_0
[0x6];
7854 u8 reserved_at_8
[0xc];
7857 u8 xoff_threshold
[0x10];
7858 u8 xon_threshold
[0x10];
7861 struct mlx5_ifc_set_node_in_bits
{
7862 u8 node_description
[64][0x8];
7865 struct mlx5_ifc_register_power_settings_bits
{
7866 u8 reserved_at_0
[0x18];
7867 u8 power_settings_level
[0x8];
7869 u8 reserved_at_20
[0x60];
7872 struct mlx5_ifc_register_host_endianness_bits
{
7874 u8 reserved_at_1
[0x1f];
7876 u8 reserved_at_20
[0x60];
7879 struct mlx5_ifc_umr_pointer_desc_argument_bits
{
7880 u8 reserved_at_0
[0x20];
7884 u8 addressh_63_32
[0x20];
7886 u8 addressl_31_0
[0x20];
7889 struct mlx5_ifc_ud_adrs_vector_bits
{
7893 u8 reserved_at_41
[0x7];
7894 u8 destination_qp_dct
[0x18];
7896 u8 static_rate
[0x4];
7897 u8 sl_eth_prio
[0x4];
7900 u8 rlid_udp_sport
[0x10];
7902 u8 reserved_at_80
[0x20];
7904 u8 rmac_47_16
[0x20];
7910 u8 reserved_at_e0
[0x1];
7912 u8 reserved_at_e2
[0x2];
7913 u8 src_addr_index
[0x8];
7914 u8 flow_label
[0x14];
7916 u8 rgid_rip
[16][0x8];
7919 struct mlx5_ifc_pages_req_event_bits
{
7920 u8 reserved_at_0
[0x10];
7921 u8 function_id
[0x10];
7925 u8 reserved_at_40
[0xa0];
7928 struct mlx5_ifc_eqe_bits
{
7929 u8 reserved_at_0
[0x8];
7931 u8 reserved_at_10
[0x8];
7932 u8 event_sub_type
[0x8];
7934 u8 reserved_at_20
[0xe0];
7936 union mlx5_ifc_event_auto_bits event_data
;
7938 u8 reserved_at_1e0
[0x10];
7940 u8 reserved_at_1f8
[0x7];
7945 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT
= 0x7,
7948 struct mlx5_ifc_cmd_queue_entry_bits
{
7950 u8 reserved_at_8
[0x18];
7952 u8 input_length
[0x20];
7954 u8 input_mailbox_pointer_63_32
[0x20];
7956 u8 input_mailbox_pointer_31_9
[0x17];
7957 u8 reserved_at_77
[0x9];
7959 u8 command_input_inline_data
[16][0x8];
7961 u8 command_output_inline_data
[16][0x8];
7963 u8 output_mailbox_pointer_63_32
[0x20];
7965 u8 output_mailbox_pointer_31_9
[0x17];
7966 u8 reserved_at_1b7
[0x9];
7968 u8 output_length
[0x20];
7972 u8 reserved_at_1f0
[0x8];
7977 struct mlx5_ifc_cmd_out_bits
{
7979 u8 reserved_at_8
[0x18];
7983 u8 command_output
[0x20];
7986 struct mlx5_ifc_cmd_in_bits
{
7988 u8 reserved_at_10
[0x10];
7990 u8 reserved_at_20
[0x10];
7993 u8 command
[0][0x20];
7996 struct mlx5_ifc_cmd_if_box_bits
{
7997 u8 mailbox_data
[512][0x8];
7999 u8 reserved_at_1000
[0x180];
8001 u8 next_pointer_63_32
[0x20];
8003 u8 next_pointer_31_10
[0x16];
8004 u8 reserved_at_11b6
[0xa];
8006 u8 block_number
[0x20];
8008 u8 reserved_at_11e0
[0x8];
8010 u8 ctrl_signature
[0x8];
8014 struct mlx5_ifc_mtt_bits
{
8015 u8 ptag_63_32
[0x20];
8018 u8 reserved_at_38
[0x6];
8023 struct mlx5_ifc_query_wol_rol_out_bits
{
8025 u8 reserved_at_8
[0x18];
8029 u8 reserved_at_40
[0x10];
8033 u8 reserved_at_60
[0x20];
8036 struct mlx5_ifc_query_wol_rol_in_bits
{
8038 u8 reserved_at_10
[0x10];
8040 u8 reserved_at_20
[0x10];
8043 u8 reserved_at_40
[0x40];
8046 struct mlx5_ifc_set_wol_rol_out_bits
{
8048 u8 reserved_at_8
[0x18];
8052 u8 reserved_at_40
[0x40];
8055 struct mlx5_ifc_set_wol_rol_in_bits
{
8057 u8 reserved_at_10
[0x10];
8059 u8 reserved_at_20
[0x10];
8062 u8 rol_mode_valid
[0x1];
8063 u8 wol_mode_valid
[0x1];
8064 u8 reserved_at_42
[0xe];
8068 u8 reserved_at_60
[0x20];
8072 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER
= 0x0,
8073 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED
= 0x1,
8074 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC
= 0x2,
8078 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER
= 0x0,
8079 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED
= 0x1,
8080 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC
= 0x2,
8084 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR
= 0x1,
8085 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC
= 0x7,
8086 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR
= 0x8,
8087 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR
= 0x9,
8088 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR
= 0xa,
8089 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR
= 0xb,
8090 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN
= 0xc,
8091 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR
= 0xd,
8092 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV
= 0xe,
8093 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR
= 0xf,
8094 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR
= 0x10,
8097 struct mlx5_ifc_initial_seg_bits
{
8098 u8 fw_rev_minor
[0x10];
8099 u8 fw_rev_major
[0x10];
8101 u8 cmd_interface_rev
[0x10];
8102 u8 fw_rev_subminor
[0x10];
8104 u8 reserved_at_40
[0x40];
8106 u8 cmdq_phy_addr_63_32
[0x20];
8108 u8 cmdq_phy_addr_31_12
[0x14];
8109 u8 reserved_at_b4
[0x2];
8110 u8 nic_interface
[0x2];
8111 u8 log_cmdq_size
[0x4];
8112 u8 log_cmdq_stride
[0x4];
8114 u8 command_doorbell_vector
[0x20];
8116 u8 reserved_at_e0
[0xf00];
8118 u8 initializing
[0x1];
8119 u8 reserved_at_fe1
[0x4];
8120 u8 nic_interface_supported
[0x3];
8121 u8 reserved_at_fe8
[0x18];
8123 struct mlx5_ifc_health_buffer_bits health_buffer
;
8125 u8 no_dram_nic_offset
[0x20];
8127 u8 reserved_at_1220
[0x6e40];
8129 u8 reserved_at_8060
[0x1f];
8132 u8 health_syndrome
[0x8];
8133 u8 health_counter
[0x18];
8135 u8 reserved_at_80a0
[0x17fc0];
8138 struct mlx5_ifc_mtpps_reg_bits
{
8139 u8 reserved_at_0
[0xc];
8140 u8 cap_number_of_pps_pins
[0x4];
8141 u8 reserved_at_10
[0x4];
8142 u8 cap_max_num_of_pps_in_pins
[0x4];
8143 u8 reserved_at_18
[0x4];
8144 u8 cap_max_num_of_pps_out_pins
[0x4];
8146 u8 reserved_at_20
[0x24];
8147 u8 cap_pin_3_mode
[0x4];
8148 u8 reserved_at_48
[0x4];
8149 u8 cap_pin_2_mode
[0x4];
8150 u8 reserved_at_50
[0x4];
8151 u8 cap_pin_1_mode
[0x4];
8152 u8 reserved_at_58
[0x4];
8153 u8 cap_pin_0_mode
[0x4];
8155 u8 reserved_at_60
[0x4];
8156 u8 cap_pin_7_mode
[0x4];
8157 u8 reserved_at_68
[0x4];
8158 u8 cap_pin_6_mode
[0x4];
8159 u8 reserved_at_70
[0x4];
8160 u8 cap_pin_5_mode
[0x4];
8161 u8 reserved_at_78
[0x4];
8162 u8 cap_pin_4_mode
[0x4];
8164 u8 field_select
[0x20];
8165 u8 reserved_at_a0
[0x60];
8168 u8 reserved_at_101
[0xb];
8170 u8 reserved_at_110
[0x4];
8174 u8 reserved_at_120
[0x20];
8176 u8 time_stamp
[0x40];
8178 u8 out_pulse_duration
[0x10];
8179 u8 out_periodic_adjustment
[0x10];
8180 u8 enhanced_out_periodic_adjustment
[0x20];
8182 u8 reserved_at_1c0
[0x20];
8185 struct mlx5_ifc_mtppse_reg_bits
{
8186 u8 reserved_at_0
[0x18];
8189 u8 reserved_at_21
[0x1b];
8190 u8 event_generation_mode
[0x4];
8191 u8 reserved_at_40
[0x40];
8194 struct mlx5_ifc_mcqi_cap_bits
{
8195 u8 supported_info_bitmask
[0x20];
8197 u8 component_size
[0x20];
8199 u8 max_component_size
[0x20];
8201 u8 log_mcda_word_size
[0x4];
8202 u8 reserved_at_64
[0xc];
8203 u8 mcda_max_write_size
[0x10];
8206 u8 reserved_at_81
[0x1];
8207 u8 match_chip_id
[0x1];
8209 u8 check_user_timestamp
[0x1];
8210 u8 match_base_guid_mac
[0x1];
8211 u8 reserved_at_86
[0x1a];
8214 struct mlx5_ifc_mcqi_reg_bits
{
8215 u8 read_pending_component
[0x1];
8216 u8 reserved_at_1
[0xf];
8217 u8 component_index
[0x10];
8219 u8 reserved_at_20
[0x20];
8221 u8 reserved_at_40
[0x1b];
8228 u8 reserved_at_a0
[0x10];
8234 struct mlx5_ifc_mcc_reg_bits
{
8235 u8 reserved_at_0
[0x4];
8236 u8 time_elapsed_since_last_cmd
[0xc];
8237 u8 reserved_at_10
[0x8];
8238 u8 instruction
[0x8];
8240 u8 reserved_at_20
[0x10];
8241 u8 component_index
[0x10];
8243 u8 reserved_at_40
[0x8];
8244 u8 update_handle
[0x18];
8246 u8 handle_owner_type
[0x4];
8247 u8 handle_owner_host_id
[0x4];
8248 u8 reserved_at_68
[0x1];
8249 u8 control_progress
[0x7];
8251 u8 reserved_at_78
[0x4];
8252 u8 control_state
[0x4];
8254 u8 component_size
[0x20];
8256 u8 reserved_at_a0
[0x60];
8259 struct mlx5_ifc_mcda_reg_bits
{
8260 u8 reserved_at_0
[0x8];
8261 u8 update_handle
[0x18];
8265 u8 reserved_at_40
[0x10];
8268 u8 reserved_at_60
[0x20];
8273 union mlx5_ifc_ports_control_registers_document_bits
{
8274 struct mlx5_ifc_bufferx_reg_bits bufferx_reg
;
8275 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
8276 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
8277 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
8278 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
8279 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
8280 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
8281 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout
;
8282 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping
;
8283 struct mlx5_ifc_pamp_reg_bits pamp_reg
;
8284 struct mlx5_ifc_paos_reg_bits paos_reg
;
8285 struct mlx5_ifc_pcap_reg_bits pcap_reg
;
8286 struct mlx5_ifc_peir_reg_bits peir_reg
;
8287 struct mlx5_ifc_pelc_reg_bits pelc_reg
;
8288 struct mlx5_ifc_pfcc_reg_bits pfcc_reg
;
8289 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
8290 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
8291 struct mlx5_ifc_pifr_reg_bits pifr_reg
;
8292 struct mlx5_ifc_pipg_reg_bits pipg_reg
;
8293 struct mlx5_ifc_plbf_reg_bits plbf_reg
;
8294 struct mlx5_ifc_plib_reg_bits plib_reg
;
8295 struct mlx5_ifc_plpc_reg_bits plpc_reg
;
8296 struct mlx5_ifc_pmaos_reg_bits pmaos_reg
;
8297 struct mlx5_ifc_pmlp_reg_bits pmlp_reg
;
8298 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg
;
8299 struct mlx5_ifc_pmpc_reg_bits pmpc_reg
;
8300 struct mlx5_ifc_pmpe_reg_bits pmpe_reg
;
8301 struct mlx5_ifc_pmpr_reg_bits pmpr_reg
;
8302 struct mlx5_ifc_pmtu_reg_bits pmtu_reg
;
8303 struct mlx5_ifc_ppad_reg_bits ppad_reg
;
8304 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg
;
8305 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg
;
8306 struct mlx5_ifc_pplm_reg_bits pplm_reg
;
8307 struct mlx5_ifc_pplr_reg_bits pplr_reg
;
8308 struct mlx5_ifc_ppsc_reg_bits ppsc_reg
;
8309 struct mlx5_ifc_pqdr_reg_bits pqdr_reg
;
8310 struct mlx5_ifc_pspa_reg_bits pspa_reg
;
8311 struct mlx5_ifc_ptas_reg_bits ptas_reg
;
8312 struct mlx5_ifc_ptys_reg_bits ptys_reg
;
8313 struct mlx5_ifc_mlcr_reg_bits mlcr_reg
;
8314 struct mlx5_ifc_pude_reg_bits pude_reg
;
8315 struct mlx5_ifc_pvlc_reg_bits pvlc_reg
;
8316 struct mlx5_ifc_slrg_reg_bits slrg_reg
;
8317 struct mlx5_ifc_sltp_reg_bits sltp_reg
;
8318 struct mlx5_ifc_mtpps_reg_bits mtpps_reg
;
8319 struct mlx5_ifc_mtppse_reg_bits mtppse_reg
;
8320 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg
;
8321 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits
;
8322 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits
;
8323 struct mlx5_ifc_mcqi_reg_bits mcqi_reg
;
8324 struct mlx5_ifc_mcc_reg_bits mcc_reg
;
8325 struct mlx5_ifc_mcda_reg_bits mcda_reg
;
8326 u8 reserved_at_0
[0x60e0];
8329 union mlx5_ifc_debug_enhancements_document_bits
{
8330 struct mlx5_ifc_health_buffer_bits health_buffer
;
8331 u8 reserved_at_0
[0x200];
8334 union mlx5_ifc_uplink_pci_interface_document_bits
{
8335 struct mlx5_ifc_initial_seg_bits initial_seg
;
8336 u8 reserved_at_0
[0x20060];
8339 struct mlx5_ifc_set_flow_table_root_out_bits
{
8341 u8 reserved_at_8
[0x18];
8345 u8 reserved_at_40
[0x40];
8348 struct mlx5_ifc_set_flow_table_root_in_bits
{
8350 u8 reserved_at_10
[0x10];
8352 u8 reserved_at_20
[0x10];
8355 u8 other_vport
[0x1];
8356 u8 reserved_at_41
[0xf];
8357 u8 vport_number
[0x10];
8359 u8 reserved_at_60
[0x20];
8362 u8 reserved_at_88
[0x18];
8364 u8 reserved_at_a0
[0x8];
8367 u8 reserved_at_c0
[0x8];
8368 u8 underlay_qpn
[0x18];
8369 u8 reserved_at_e0
[0x120];
8373 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID
= (1UL << 0),
8374 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID
= (1UL << 15),
8377 struct mlx5_ifc_modify_flow_table_out_bits
{
8379 u8 reserved_at_8
[0x18];
8383 u8 reserved_at_40
[0x40];
8386 struct mlx5_ifc_modify_flow_table_in_bits
{
8388 u8 reserved_at_10
[0x10];
8390 u8 reserved_at_20
[0x10];
8393 u8 other_vport
[0x1];
8394 u8 reserved_at_41
[0xf];
8395 u8 vport_number
[0x10];
8397 u8 reserved_at_60
[0x10];
8398 u8 modify_field_select
[0x10];
8401 u8 reserved_at_88
[0x18];
8403 u8 reserved_at_a0
[0x8];
8406 struct mlx5_ifc_flow_table_context_bits flow_table_context
;
8409 struct mlx5_ifc_ets_tcn_config_reg_bits
{
8413 u8 reserved_at_3
[0x9];
8415 u8 reserved_at_10
[0x9];
8416 u8 bw_allocation
[0x7];
8418 u8 reserved_at_20
[0xc];
8419 u8 max_bw_units
[0x4];
8420 u8 reserved_at_30
[0x8];
8421 u8 max_bw_value
[0x8];
8424 struct mlx5_ifc_ets_global_config_reg_bits
{
8425 u8 reserved_at_0
[0x2];
8427 u8 reserved_at_3
[0x1d];
8429 u8 reserved_at_20
[0xc];
8430 u8 max_bw_units
[0x4];
8431 u8 reserved_at_30
[0x8];
8432 u8 max_bw_value
[0x8];
8435 struct mlx5_ifc_qetc_reg_bits
{
8436 u8 reserved_at_0
[0x8];
8437 u8 port_number
[0x8];
8438 u8 reserved_at_10
[0x30];
8440 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration
[0x8];
8441 struct mlx5_ifc_ets_global_config_reg_bits global_configuration
;
8444 struct mlx5_ifc_qtct_reg_bits
{
8445 u8 reserved_at_0
[0x8];
8446 u8 port_number
[0x8];
8447 u8 reserved_at_10
[0xd];
8450 u8 reserved_at_20
[0x1d];
8454 struct mlx5_ifc_mcia_reg_bits
{
8456 u8 reserved_at_1
[0x7];
8458 u8 reserved_at_10
[0x8];
8461 u8 i2c_device_address
[0x8];
8462 u8 page_number
[0x8];
8463 u8 device_address
[0x10];
8465 u8 reserved_at_40
[0x10];
8468 u8 reserved_at_60
[0x20];
8484 struct mlx5_ifc_dcbx_param_bits
{
8485 u8 dcbx_cee_cap
[0x1];
8486 u8 dcbx_ieee_cap
[0x1];
8487 u8 dcbx_standby_cap
[0x1];
8488 u8 reserved_at_0
[0x5];
8489 u8 port_number
[0x8];
8490 u8 reserved_at_10
[0xa];
8491 u8 max_application_table_size
[6];
8492 u8 reserved_at_20
[0x15];
8493 u8 version_oper
[0x3];
8494 u8 reserved_at_38
[5];
8495 u8 version_admin
[0x3];
8496 u8 willing_admin
[0x1];
8497 u8 reserved_at_41
[0x3];
8498 u8 pfc_cap_oper
[0x4];
8499 u8 reserved_at_48
[0x4];
8500 u8 pfc_cap_admin
[0x4];
8501 u8 reserved_at_50
[0x4];
8502 u8 num_of_tc_oper
[0x4];
8503 u8 reserved_at_58
[0x4];
8504 u8 num_of_tc_admin
[0x4];
8505 u8 remote_willing
[0x1];
8506 u8 reserved_at_61
[3];
8507 u8 remote_pfc_cap
[4];
8508 u8 reserved_at_68
[0x14];
8509 u8 remote_num_of_tc
[0x4];
8510 u8 reserved_at_80
[0x18];
8512 u8 reserved_at_a0
[0x160];
8515 struct mlx5_ifc_lagc_bits
{
8516 u8 reserved_at_0
[0x1d];
8519 u8 reserved_at_20
[0x14];
8520 u8 tx_remap_affinity_2
[0x4];
8521 u8 reserved_at_38
[0x4];
8522 u8 tx_remap_affinity_1
[0x4];
8525 struct mlx5_ifc_create_lag_out_bits
{
8527 u8 reserved_at_8
[0x18];
8531 u8 reserved_at_40
[0x40];
8534 struct mlx5_ifc_create_lag_in_bits
{
8536 u8 reserved_at_10
[0x10];
8538 u8 reserved_at_20
[0x10];
8541 struct mlx5_ifc_lagc_bits ctx
;
8544 struct mlx5_ifc_modify_lag_out_bits
{
8546 u8 reserved_at_8
[0x18];
8550 u8 reserved_at_40
[0x40];
8553 struct mlx5_ifc_modify_lag_in_bits
{
8555 u8 reserved_at_10
[0x10];
8557 u8 reserved_at_20
[0x10];
8560 u8 reserved_at_40
[0x20];
8561 u8 field_select
[0x20];
8563 struct mlx5_ifc_lagc_bits ctx
;
8566 struct mlx5_ifc_query_lag_out_bits
{
8568 u8 reserved_at_8
[0x18];
8572 u8 reserved_at_40
[0x40];
8574 struct mlx5_ifc_lagc_bits ctx
;
8577 struct mlx5_ifc_query_lag_in_bits
{
8579 u8 reserved_at_10
[0x10];
8581 u8 reserved_at_20
[0x10];
8584 u8 reserved_at_40
[0x40];
8587 struct mlx5_ifc_destroy_lag_out_bits
{
8589 u8 reserved_at_8
[0x18];
8593 u8 reserved_at_40
[0x40];
8596 struct mlx5_ifc_destroy_lag_in_bits
{
8598 u8 reserved_at_10
[0x10];
8600 u8 reserved_at_20
[0x10];
8603 u8 reserved_at_40
[0x40];
8606 struct mlx5_ifc_create_vport_lag_out_bits
{
8608 u8 reserved_at_8
[0x18];
8612 u8 reserved_at_40
[0x40];
8615 struct mlx5_ifc_create_vport_lag_in_bits
{
8617 u8 reserved_at_10
[0x10];
8619 u8 reserved_at_20
[0x10];
8622 u8 reserved_at_40
[0x40];
8625 struct mlx5_ifc_destroy_vport_lag_out_bits
{
8627 u8 reserved_at_8
[0x18];
8631 u8 reserved_at_40
[0x40];
8634 struct mlx5_ifc_destroy_vport_lag_in_bits
{
8636 u8 reserved_at_10
[0x10];
8638 u8 reserved_at_20
[0x10];
8641 u8 reserved_at_40
[0x40];
8644 #endif /* MLX5_IFC_H */