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Merge tag 'gvt-next-fixes-2019-12-02' of https://github.com/intel/gvt-linux into...
[mirror_ubuntu-hirsute-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
64 };
65
66 enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71 };
72
73 enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77 };
78
79 enum {
80 MLX5_SHARED_RESOURCE_UID = 0xffff,
81 };
82
83 enum {
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
85 };
86
87 enum {
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90 };
91
92 enum {
93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
94 MLX5_OBJ_TYPE_MKEY = 0xff01,
95 MLX5_OBJ_TYPE_QP = 0xff02,
96 MLX5_OBJ_TYPE_PSV = 0xff03,
97 MLX5_OBJ_TYPE_RMP = 0xff04,
98 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99 MLX5_OBJ_TYPE_RQ = 0xff06,
100 MLX5_OBJ_TYPE_SQ = 0xff07,
101 MLX5_OBJ_TYPE_TIR = 0xff08,
102 MLX5_OBJ_TYPE_TIS = 0xff09,
103 MLX5_OBJ_TYPE_DCT = 0xff0a,
104 MLX5_OBJ_TYPE_XRQ = 0xff0b,
105 MLX5_OBJ_TYPE_RQT = 0xff0e,
106 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107 MLX5_OBJ_TYPE_CQ = 0xff10,
108 };
109
110 enum {
111 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
112 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
113 MLX5_CMD_OP_INIT_HCA = 0x102,
114 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
115 MLX5_CMD_OP_ENABLE_HCA = 0x104,
116 MLX5_CMD_OP_DISABLE_HCA = 0x105,
117 MLX5_CMD_OP_QUERY_PAGES = 0x107,
118 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
119 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
120 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
121 MLX5_CMD_OP_SET_ISSI = 0x10b,
122 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
123 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
124 MLX5_CMD_OP_ALLOC_SF = 0x113,
125 MLX5_CMD_OP_DEALLOC_SF = 0x114,
126 MLX5_CMD_OP_CREATE_MKEY = 0x200,
127 MLX5_CMD_OP_QUERY_MKEY = 0x201,
128 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
129 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
130 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
131 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
132 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
133 MLX5_CMD_OP_CREATE_EQ = 0x301,
134 MLX5_CMD_OP_DESTROY_EQ = 0x302,
135 MLX5_CMD_OP_QUERY_EQ = 0x303,
136 MLX5_CMD_OP_GEN_EQE = 0x304,
137 MLX5_CMD_OP_CREATE_CQ = 0x400,
138 MLX5_CMD_OP_DESTROY_CQ = 0x401,
139 MLX5_CMD_OP_QUERY_CQ = 0x402,
140 MLX5_CMD_OP_MODIFY_CQ = 0x403,
141 MLX5_CMD_OP_CREATE_QP = 0x500,
142 MLX5_CMD_OP_DESTROY_QP = 0x501,
143 MLX5_CMD_OP_RST2INIT_QP = 0x502,
144 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
145 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
146 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
147 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
148 MLX5_CMD_OP_2ERR_QP = 0x507,
149 MLX5_CMD_OP_2RST_QP = 0x50a,
150 MLX5_CMD_OP_QUERY_QP = 0x50b,
151 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
152 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
153 MLX5_CMD_OP_CREATE_PSV = 0x600,
154 MLX5_CMD_OP_DESTROY_PSV = 0x601,
155 MLX5_CMD_OP_CREATE_SRQ = 0x700,
156 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
157 MLX5_CMD_OP_QUERY_SRQ = 0x702,
158 MLX5_CMD_OP_ARM_RQ = 0x703,
159 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
160 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
161 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
162 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
163 MLX5_CMD_OP_CREATE_DCT = 0x710,
164 MLX5_CMD_OP_DESTROY_DCT = 0x711,
165 MLX5_CMD_OP_DRAIN_DCT = 0x712,
166 MLX5_CMD_OP_QUERY_DCT = 0x713,
167 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
168 MLX5_CMD_OP_CREATE_XRQ = 0x717,
169 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
170 MLX5_CMD_OP_QUERY_XRQ = 0x719,
171 MLX5_CMD_OP_ARM_XRQ = 0x71a,
172 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
173 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
174 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
175 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
176 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
177 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
178 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
179 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
180 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
181 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
182 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
183 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
184 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
185 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
186 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
187 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
188 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
190 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
191 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
192 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
193 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
194 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
195 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
196 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
197 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
198 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
199 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
200 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
201 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
202 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
203 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
204 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
205 MLX5_CMD_OP_ALLOC_PD = 0x800,
206 MLX5_CMD_OP_DEALLOC_PD = 0x801,
207 MLX5_CMD_OP_ALLOC_UAR = 0x802,
208 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
209 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
210 MLX5_CMD_OP_ACCESS_REG = 0x805,
211 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
212 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
213 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
214 MLX5_CMD_OP_MAD_IFC = 0x50d,
215 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
216 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
217 MLX5_CMD_OP_NOP = 0x80d,
218 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
219 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
220 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
221 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
222 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
223 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
224 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
225 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
226 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
227 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
228 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
229 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
230 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
231 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
232 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
233 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
234 MLX5_CMD_OP_CREATE_LAG = 0x840,
235 MLX5_CMD_OP_MODIFY_LAG = 0x841,
236 MLX5_CMD_OP_QUERY_LAG = 0x842,
237 MLX5_CMD_OP_DESTROY_LAG = 0x843,
238 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
239 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
240 MLX5_CMD_OP_CREATE_TIR = 0x900,
241 MLX5_CMD_OP_MODIFY_TIR = 0x901,
242 MLX5_CMD_OP_DESTROY_TIR = 0x902,
243 MLX5_CMD_OP_QUERY_TIR = 0x903,
244 MLX5_CMD_OP_CREATE_SQ = 0x904,
245 MLX5_CMD_OP_MODIFY_SQ = 0x905,
246 MLX5_CMD_OP_DESTROY_SQ = 0x906,
247 MLX5_CMD_OP_QUERY_SQ = 0x907,
248 MLX5_CMD_OP_CREATE_RQ = 0x908,
249 MLX5_CMD_OP_MODIFY_RQ = 0x909,
250 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
251 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
252 MLX5_CMD_OP_QUERY_RQ = 0x90b,
253 MLX5_CMD_OP_CREATE_RMP = 0x90c,
254 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
255 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
256 MLX5_CMD_OP_QUERY_RMP = 0x90f,
257 MLX5_CMD_OP_CREATE_TIS = 0x912,
258 MLX5_CMD_OP_MODIFY_TIS = 0x913,
259 MLX5_CMD_OP_DESTROY_TIS = 0x914,
260 MLX5_CMD_OP_QUERY_TIS = 0x915,
261 MLX5_CMD_OP_CREATE_RQT = 0x916,
262 MLX5_CMD_OP_MODIFY_RQT = 0x917,
263 MLX5_CMD_OP_DESTROY_RQT = 0x918,
264 MLX5_CMD_OP_QUERY_RQT = 0x919,
265 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
266 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
267 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
268 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
269 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
270 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
271 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
272 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
273 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
274 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
275 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
276 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
277 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
278 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
279 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
280 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
281 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
285 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
286 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
287 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
288 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
289 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
290 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
291 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
292 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
293 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
294 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
295 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
296 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
297 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
298 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
299 MLX5_CMD_OP_MAX
300 };
301
302 /* Valid range for general commands that don't work over an object */
303 enum {
304 MLX5_CMD_OP_GENERAL_START = 0xb00,
305 MLX5_CMD_OP_GENERAL_END = 0xd00,
306 };
307
308 struct mlx5_ifc_flow_table_fields_supported_bits {
309 u8 outer_dmac[0x1];
310 u8 outer_smac[0x1];
311 u8 outer_ether_type[0x1];
312 u8 outer_ip_version[0x1];
313 u8 outer_first_prio[0x1];
314 u8 outer_first_cfi[0x1];
315 u8 outer_first_vid[0x1];
316 u8 outer_ipv4_ttl[0x1];
317 u8 outer_second_prio[0x1];
318 u8 outer_second_cfi[0x1];
319 u8 outer_second_vid[0x1];
320 u8 reserved_at_b[0x1];
321 u8 outer_sip[0x1];
322 u8 outer_dip[0x1];
323 u8 outer_frag[0x1];
324 u8 outer_ip_protocol[0x1];
325 u8 outer_ip_ecn[0x1];
326 u8 outer_ip_dscp[0x1];
327 u8 outer_udp_sport[0x1];
328 u8 outer_udp_dport[0x1];
329 u8 outer_tcp_sport[0x1];
330 u8 outer_tcp_dport[0x1];
331 u8 outer_tcp_flags[0x1];
332 u8 outer_gre_protocol[0x1];
333 u8 outer_gre_key[0x1];
334 u8 outer_vxlan_vni[0x1];
335 u8 outer_geneve_vni[0x1];
336 u8 outer_geneve_oam[0x1];
337 u8 outer_geneve_protocol_type[0x1];
338 u8 outer_geneve_opt_len[0x1];
339 u8 reserved_at_1e[0x1];
340 u8 source_eswitch_port[0x1];
341
342 u8 inner_dmac[0x1];
343 u8 inner_smac[0x1];
344 u8 inner_ether_type[0x1];
345 u8 inner_ip_version[0x1];
346 u8 inner_first_prio[0x1];
347 u8 inner_first_cfi[0x1];
348 u8 inner_first_vid[0x1];
349 u8 reserved_at_27[0x1];
350 u8 inner_second_prio[0x1];
351 u8 inner_second_cfi[0x1];
352 u8 inner_second_vid[0x1];
353 u8 reserved_at_2b[0x1];
354 u8 inner_sip[0x1];
355 u8 inner_dip[0x1];
356 u8 inner_frag[0x1];
357 u8 inner_ip_protocol[0x1];
358 u8 inner_ip_ecn[0x1];
359 u8 inner_ip_dscp[0x1];
360 u8 inner_udp_sport[0x1];
361 u8 inner_udp_dport[0x1];
362 u8 inner_tcp_sport[0x1];
363 u8 inner_tcp_dport[0x1];
364 u8 inner_tcp_flags[0x1];
365 u8 reserved_at_37[0x9];
366
367 u8 geneve_tlv_option_0_data[0x1];
368 u8 reserved_at_41[0x4];
369 u8 outer_first_mpls_over_udp[0x4];
370 u8 outer_first_mpls_over_gre[0x4];
371 u8 inner_first_mpls[0x4];
372 u8 outer_first_mpls[0x4];
373 u8 reserved_at_55[0x2];
374 u8 outer_esp_spi[0x1];
375 u8 reserved_at_58[0x2];
376 u8 bth_dst_qp[0x1];
377
378 u8 reserved_at_5b[0x25];
379 };
380
381 struct mlx5_ifc_flow_table_prop_layout_bits {
382 u8 ft_support[0x1];
383 u8 reserved_at_1[0x1];
384 u8 flow_counter[0x1];
385 u8 flow_modify_en[0x1];
386 u8 modify_root[0x1];
387 u8 identified_miss_table_mode[0x1];
388 u8 flow_table_modify[0x1];
389 u8 reformat[0x1];
390 u8 decap[0x1];
391 u8 reserved_at_9[0x1];
392 u8 pop_vlan[0x1];
393 u8 push_vlan[0x1];
394 u8 reserved_at_c[0x1];
395 u8 pop_vlan_2[0x1];
396 u8 push_vlan_2[0x1];
397 u8 reformat_and_vlan_action[0x1];
398 u8 reserved_at_10[0x1];
399 u8 sw_owner[0x1];
400 u8 reformat_l3_tunnel_to_l2[0x1];
401 u8 reformat_l2_to_l3_tunnel[0x1];
402 u8 reformat_and_modify_action[0x1];
403 u8 reserved_at_15[0x2];
404 u8 table_miss_action_domain[0x1];
405 u8 termination_table[0x1];
406 u8 reserved_at_19[0x7];
407 u8 reserved_at_20[0x2];
408 u8 log_max_ft_size[0x6];
409 u8 log_max_modify_header_context[0x8];
410 u8 max_modify_header_actions[0x8];
411 u8 max_ft_level[0x8];
412
413 u8 reserved_at_40[0x20];
414
415 u8 reserved_at_60[0x18];
416 u8 log_max_ft_num[0x8];
417
418 u8 reserved_at_80[0x18];
419 u8 log_max_destination[0x8];
420
421 u8 log_max_flow_counter[0x8];
422 u8 reserved_at_a8[0x10];
423 u8 log_max_flow[0x8];
424
425 u8 reserved_at_c0[0x40];
426
427 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
428
429 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
430 };
431
432 struct mlx5_ifc_odp_per_transport_service_cap_bits {
433 u8 send[0x1];
434 u8 receive[0x1];
435 u8 write[0x1];
436 u8 read[0x1];
437 u8 atomic[0x1];
438 u8 srq_receive[0x1];
439 u8 reserved_at_6[0x1a];
440 };
441
442 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
443 u8 smac_47_16[0x20];
444
445 u8 smac_15_0[0x10];
446 u8 ethertype[0x10];
447
448 u8 dmac_47_16[0x20];
449
450 u8 dmac_15_0[0x10];
451 u8 first_prio[0x3];
452 u8 first_cfi[0x1];
453 u8 first_vid[0xc];
454
455 u8 ip_protocol[0x8];
456 u8 ip_dscp[0x6];
457 u8 ip_ecn[0x2];
458 u8 cvlan_tag[0x1];
459 u8 svlan_tag[0x1];
460 u8 frag[0x1];
461 u8 ip_version[0x4];
462 u8 tcp_flags[0x9];
463
464 u8 tcp_sport[0x10];
465 u8 tcp_dport[0x10];
466
467 u8 reserved_at_c0[0x18];
468 u8 ttl_hoplimit[0x8];
469
470 u8 udp_sport[0x10];
471 u8 udp_dport[0x10];
472
473 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
474
475 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
476 };
477
478 struct mlx5_ifc_nvgre_key_bits {
479 u8 hi[0x18];
480 u8 lo[0x8];
481 };
482
483 union mlx5_ifc_gre_key_bits {
484 struct mlx5_ifc_nvgre_key_bits nvgre;
485 u8 key[0x20];
486 };
487
488 struct mlx5_ifc_fte_match_set_misc_bits {
489 u8 gre_c_present[0x1];
490 u8 reserved_at_1[0x1];
491 u8 gre_k_present[0x1];
492 u8 gre_s_present[0x1];
493 u8 source_vhca_port[0x4];
494 u8 source_sqn[0x18];
495
496 u8 source_eswitch_owner_vhca_id[0x10];
497 u8 source_port[0x10];
498
499 u8 outer_second_prio[0x3];
500 u8 outer_second_cfi[0x1];
501 u8 outer_second_vid[0xc];
502 u8 inner_second_prio[0x3];
503 u8 inner_second_cfi[0x1];
504 u8 inner_second_vid[0xc];
505
506 u8 outer_second_cvlan_tag[0x1];
507 u8 inner_second_cvlan_tag[0x1];
508 u8 outer_second_svlan_tag[0x1];
509 u8 inner_second_svlan_tag[0x1];
510 u8 reserved_at_64[0xc];
511 u8 gre_protocol[0x10];
512
513 union mlx5_ifc_gre_key_bits gre_key;
514
515 u8 vxlan_vni[0x18];
516 u8 reserved_at_b8[0x8];
517
518 u8 geneve_vni[0x18];
519 u8 reserved_at_d8[0x7];
520 u8 geneve_oam[0x1];
521
522 u8 reserved_at_e0[0xc];
523 u8 outer_ipv6_flow_label[0x14];
524
525 u8 reserved_at_100[0xc];
526 u8 inner_ipv6_flow_label[0x14];
527
528 u8 reserved_at_120[0xa];
529 u8 geneve_opt_len[0x6];
530 u8 geneve_protocol_type[0x10];
531
532 u8 reserved_at_140[0x8];
533 u8 bth_dst_qp[0x18];
534 u8 reserved_at_160[0x20];
535 u8 outer_esp_spi[0x20];
536 u8 reserved_at_1a0[0x60];
537 };
538
539 struct mlx5_ifc_fte_match_mpls_bits {
540 u8 mpls_label[0x14];
541 u8 mpls_exp[0x3];
542 u8 mpls_s_bos[0x1];
543 u8 mpls_ttl[0x8];
544 };
545
546 struct mlx5_ifc_fte_match_set_misc2_bits {
547 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
548
549 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
550
551 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
552
553 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
554
555 u8 metadata_reg_c_7[0x20];
556
557 u8 metadata_reg_c_6[0x20];
558
559 u8 metadata_reg_c_5[0x20];
560
561 u8 metadata_reg_c_4[0x20];
562
563 u8 metadata_reg_c_3[0x20];
564
565 u8 metadata_reg_c_2[0x20];
566
567 u8 metadata_reg_c_1[0x20];
568
569 u8 metadata_reg_c_0[0x20];
570
571 u8 metadata_reg_a[0x20];
572
573 u8 metadata_reg_b[0x20];
574
575 u8 reserved_at_1c0[0x40];
576 };
577
578 struct mlx5_ifc_fte_match_set_misc3_bits {
579 u8 inner_tcp_seq_num[0x20];
580
581 u8 outer_tcp_seq_num[0x20];
582
583 u8 inner_tcp_ack_num[0x20];
584
585 u8 outer_tcp_ack_num[0x20];
586
587 u8 reserved_at_80[0x8];
588 u8 outer_vxlan_gpe_vni[0x18];
589
590 u8 outer_vxlan_gpe_next_protocol[0x8];
591 u8 outer_vxlan_gpe_flags[0x8];
592 u8 reserved_at_b0[0x10];
593
594 u8 icmp_header_data[0x20];
595
596 u8 icmpv6_header_data[0x20];
597
598 u8 icmp_type[0x8];
599 u8 icmp_code[0x8];
600 u8 icmpv6_type[0x8];
601 u8 icmpv6_code[0x8];
602
603 u8 geneve_tlv_option_0_data[0x20];
604
605 u8 reserved_at_140[0xc0];
606 };
607
608 struct mlx5_ifc_cmd_pas_bits {
609 u8 pa_h[0x20];
610
611 u8 pa_l[0x14];
612 u8 reserved_at_34[0xc];
613 };
614
615 struct mlx5_ifc_uint64_bits {
616 u8 hi[0x20];
617
618 u8 lo[0x20];
619 };
620
621 enum {
622 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
623 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
624 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
625 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
626 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
627 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
628 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
629 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
630 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
631 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
632 };
633
634 struct mlx5_ifc_ads_bits {
635 u8 fl[0x1];
636 u8 free_ar[0x1];
637 u8 reserved_at_2[0xe];
638 u8 pkey_index[0x10];
639
640 u8 reserved_at_20[0x8];
641 u8 grh[0x1];
642 u8 mlid[0x7];
643 u8 rlid[0x10];
644
645 u8 ack_timeout[0x5];
646 u8 reserved_at_45[0x3];
647 u8 src_addr_index[0x8];
648 u8 reserved_at_50[0x4];
649 u8 stat_rate[0x4];
650 u8 hop_limit[0x8];
651
652 u8 reserved_at_60[0x4];
653 u8 tclass[0x8];
654 u8 flow_label[0x14];
655
656 u8 rgid_rip[16][0x8];
657
658 u8 reserved_at_100[0x4];
659 u8 f_dscp[0x1];
660 u8 f_ecn[0x1];
661 u8 reserved_at_106[0x1];
662 u8 f_eth_prio[0x1];
663 u8 ecn[0x2];
664 u8 dscp[0x6];
665 u8 udp_sport[0x10];
666
667 u8 dei_cfi[0x1];
668 u8 eth_prio[0x3];
669 u8 sl[0x4];
670 u8 vhca_port_num[0x8];
671 u8 rmac_47_32[0x10];
672
673 u8 rmac_31_0[0x20];
674 };
675
676 struct mlx5_ifc_flow_table_nic_cap_bits {
677 u8 nic_rx_multi_path_tirs[0x1];
678 u8 nic_rx_multi_path_tirs_fts[0x1];
679 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
680 u8 reserved_at_3[0x1d];
681 u8 encap_general_header[0x1];
682 u8 reserved_at_21[0xa];
683 u8 log_max_packet_reformat_context[0x5];
684 u8 reserved_at_30[0x6];
685 u8 max_encap_header_size[0xa];
686 u8 reserved_at_40[0x1c0];
687
688 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
689
690 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
691
692 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
693
694 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
695
696 u8 reserved_at_a00[0x200];
697
698 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
699
700 u8 reserved_at_e00[0x1200];
701
702 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
703
704 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
705
706 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
707
708 u8 reserved_at_20c0[0x5f40];
709 };
710
711 enum {
712 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
713 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
714 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
715 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
716 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
717 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
718 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
719 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
720 };
721
722 struct mlx5_ifc_flow_table_eswitch_cap_bits {
723 u8 fdb_to_vport_reg_c_id[0x8];
724 u8 reserved_at_8[0xf];
725 u8 flow_source[0x1];
726 u8 reserved_at_18[0x2];
727 u8 multi_fdb_encap[0x1];
728 u8 reserved_at_1b[0x1];
729 u8 fdb_multi_path_to_table[0x1];
730 u8 reserved_at_1d[0x3];
731
732 u8 reserved_at_20[0x1e0];
733
734 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
735
736 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
737
738 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
739
740 u8 reserved_at_800[0x1000];
741
742 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
743
744 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
745
746 u8 sw_steering_uplink_icm_address_rx[0x40];
747
748 u8 sw_steering_uplink_icm_address_tx[0x40];
749
750 u8 reserved_at_1900[0x6700];
751 };
752
753 enum {
754 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
755 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
756 };
757
758 struct mlx5_ifc_e_switch_cap_bits {
759 u8 vport_svlan_strip[0x1];
760 u8 vport_cvlan_strip[0x1];
761 u8 vport_svlan_insert[0x1];
762 u8 vport_cvlan_insert_if_not_exist[0x1];
763 u8 vport_cvlan_insert_overwrite[0x1];
764 u8 reserved_at_5[0x3];
765 u8 esw_uplink_ingress_acl[0x1];
766 u8 reserved_at_9[0x10];
767 u8 esw_functions_changed[0x1];
768 u8 reserved_at_1a[0x1];
769 u8 ecpf_vport_exists[0x1];
770 u8 counter_eswitch_affinity[0x1];
771 u8 merged_eswitch[0x1];
772 u8 nic_vport_node_guid_modify[0x1];
773 u8 nic_vport_port_guid_modify[0x1];
774
775 u8 vxlan_encap_decap[0x1];
776 u8 nvgre_encap_decap[0x1];
777 u8 reserved_at_22[0x1];
778 u8 log_max_fdb_encap_uplink[0x5];
779 u8 reserved_at_21[0x3];
780 u8 log_max_packet_reformat_context[0x5];
781 u8 reserved_2b[0x6];
782 u8 max_encap_header_size[0xa];
783
784 u8 reserved_at_40[0xb];
785 u8 log_max_esw_sf[0x5];
786 u8 esw_sf_base_id[0x10];
787
788 u8 reserved_at_60[0x7a0];
789
790 };
791
792 struct mlx5_ifc_qos_cap_bits {
793 u8 packet_pacing[0x1];
794 u8 esw_scheduling[0x1];
795 u8 esw_bw_share[0x1];
796 u8 esw_rate_limit[0x1];
797 u8 reserved_at_4[0x1];
798 u8 packet_pacing_burst_bound[0x1];
799 u8 packet_pacing_typical_size[0x1];
800 u8 reserved_at_7[0x19];
801
802 u8 reserved_at_20[0x20];
803
804 u8 packet_pacing_max_rate[0x20];
805
806 u8 packet_pacing_min_rate[0x20];
807
808 u8 reserved_at_80[0x10];
809 u8 packet_pacing_rate_table_size[0x10];
810
811 u8 esw_element_type[0x10];
812 u8 esw_tsar_type[0x10];
813
814 u8 reserved_at_c0[0x10];
815 u8 max_qos_para_vport[0x10];
816
817 u8 max_tsar_bw_share[0x20];
818
819 u8 reserved_at_100[0x700];
820 };
821
822 struct mlx5_ifc_debug_cap_bits {
823 u8 core_dump_general[0x1];
824 u8 core_dump_qp[0x1];
825 u8 reserved_at_2[0x1e];
826
827 u8 reserved_at_20[0x2];
828 u8 stall_detect[0x1];
829 u8 reserved_at_23[0x1d];
830
831 u8 reserved_at_40[0x7c0];
832 };
833
834 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
835 u8 csum_cap[0x1];
836 u8 vlan_cap[0x1];
837 u8 lro_cap[0x1];
838 u8 lro_psh_flag[0x1];
839 u8 lro_time_stamp[0x1];
840 u8 reserved_at_5[0x2];
841 u8 wqe_vlan_insert[0x1];
842 u8 self_lb_en_modifiable[0x1];
843 u8 reserved_at_9[0x2];
844 u8 max_lso_cap[0x5];
845 u8 multi_pkt_send_wqe[0x2];
846 u8 wqe_inline_mode[0x2];
847 u8 rss_ind_tbl_cap[0x4];
848 u8 reg_umr_sq[0x1];
849 u8 scatter_fcs[0x1];
850 u8 enhanced_multi_pkt_send_wqe[0x1];
851 u8 tunnel_lso_const_out_ip_id[0x1];
852 u8 reserved_at_1c[0x2];
853 u8 tunnel_stateless_gre[0x1];
854 u8 tunnel_stateless_vxlan[0x1];
855
856 u8 swp[0x1];
857 u8 swp_csum[0x1];
858 u8 swp_lso[0x1];
859 u8 cqe_checksum_full[0x1];
860 u8 reserved_at_24[0x5];
861 u8 tunnel_stateless_ip_over_ip[0x1];
862 u8 reserved_at_2a[0x6];
863 u8 max_vxlan_udp_ports[0x8];
864 u8 reserved_at_38[0x6];
865 u8 max_geneve_opt_len[0x1];
866 u8 tunnel_stateless_geneve_rx[0x1];
867
868 u8 reserved_at_40[0x10];
869 u8 lro_min_mss_size[0x10];
870
871 u8 reserved_at_60[0x120];
872
873 u8 lro_timer_supported_periods[4][0x20];
874
875 u8 reserved_at_200[0x600];
876 };
877
878 struct mlx5_ifc_roce_cap_bits {
879 u8 roce_apm[0x1];
880 u8 reserved_at_1[0x1f];
881
882 u8 reserved_at_20[0x60];
883
884 u8 reserved_at_80[0xc];
885 u8 l3_type[0x4];
886 u8 reserved_at_90[0x8];
887 u8 roce_version[0x8];
888
889 u8 reserved_at_a0[0x10];
890 u8 r_roce_dest_udp_port[0x10];
891
892 u8 r_roce_max_src_udp_port[0x10];
893 u8 r_roce_min_src_udp_port[0x10];
894
895 u8 reserved_at_e0[0x10];
896 u8 roce_address_table_size[0x10];
897
898 u8 reserved_at_100[0x700];
899 };
900
901 struct mlx5_ifc_sync_steering_in_bits {
902 u8 opcode[0x10];
903 u8 uid[0x10];
904
905 u8 reserved_at_20[0x10];
906 u8 op_mod[0x10];
907
908 u8 reserved_at_40[0xc0];
909 };
910
911 struct mlx5_ifc_sync_steering_out_bits {
912 u8 status[0x8];
913 u8 reserved_at_8[0x18];
914
915 u8 syndrome[0x20];
916
917 u8 reserved_at_40[0x40];
918 };
919
920 struct mlx5_ifc_device_mem_cap_bits {
921 u8 memic[0x1];
922 u8 reserved_at_1[0x1f];
923
924 u8 reserved_at_20[0xb];
925 u8 log_min_memic_alloc_size[0x5];
926 u8 reserved_at_30[0x8];
927 u8 log_max_memic_addr_alignment[0x8];
928
929 u8 memic_bar_start_addr[0x40];
930
931 u8 memic_bar_size[0x20];
932
933 u8 max_memic_size[0x20];
934
935 u8 steering_sw_icm_start_address[0x40];
936
937 u8 reserved_at_100[0x8];
938 u8 log_header_modify_sw_icm_size[0x8];
939 u8 reserved_at_110[0x2];
940 u8 log_sw_icm_alloc_granularity[0x6];
941 u8 log_steering_sw_icm_size[0x8];
942
943 u8 reserved_at_120[0x20];
944
945 u8 header_modify_sw_icm_start_address[0x40];
946
947 u8 reserved_at_180[0x680];
948 };
949
950 struct mlx5_ifc_device_event_cap_bits {
951 u8 user_affiliated_events[4][0x40];
952
953 u8 user_unaffiliated_events[4][0x40];
954 };
955
956 enum {
957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
960 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
961 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
962 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
963 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
964 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
965 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
966 };
967
968 enum {
969 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
970 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
971 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
972 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
973 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
974 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
975 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
976 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
977 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
978 };
979
980 struct mlx5_ifc_atomic_caps_bits {
981 u8 reserved_at_0[0x40];
982
983 u8 atomic_req_8B_endianness_mode[0x2];
984 u8 reserved_at_42[0x4];
985 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
986
987 u8 reserved_at_47[0x19];
988
989 u8 reserved_at_60[0x20];
990
991 u8 reserved_at_80[0x10];
992 u8 atomic_operations[0x10];
993
994 u8 reserved_at_a0[0x10];
995 u8 atomic_size_qp[0x10];
996
997 u8 reserved_at_c0[0x10];
998 u8 atomic_size_dc[0x10];
999
1000 u8 reserved_at_e0[0x720];
1001 };
1002
1003 struct mlx5_ifc_odp_cap_bits {
1004 u8 reserved_at_0[0x40];
1005
1006 u8 sig[0x1];
1007 u8 reserved_at_41[0x1f];
1008
1009 u8 reserved_at_60[0x20];
1010
1011 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1012
1013 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1014
1015 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1016
1017 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1018
1019 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1020
1021 u8 reserved_at_120[0x6E0];
1022 };
1023
1024 struct mlx5_ifc_calc_op {
1025 u8 reserved_at_0[0x10];
1026 u8 reserved_at_10[0x9];
1027 u8 op_swap_endianness[0x1];
1028 u8 op_min[0x1];
1029 u8 op_xor[0x1];
1030 u8 op_or[0x1];
1031 u8 op_and[0x1];
1032 u8 op_max[0x1];
1033 u8 op_add[0x1];
1034 };
1035
1036 struct mlx5_ifc_vector_calc_cap_bits {
1037 u8 calc_matrix[0x1];
1038 u8 reserved_at_1[0x1f];
1039 u8 reserved_at_20[0x8];
1040 u8 max_vec_count[0x8];
1041 u8 reserved_at_30[0xd];
1042 u8 max_chunk_size[0x3];
1043 struct mlx5_ifc_calc_op calc0;
1044 struct mlx5_ifc_calc_op calc1;
1045 struct mlx5_ifc_calc_op calc2;
1046 struct mlx5_ifc_calc_op calc3;
1047
1048 u8 reserved_at_c0[0x720];
1049 };
1050
1051 struct mlx5_ifc_tls_cap_bits {
1052 u8 tls_1_2_aes_gcm_128[0x1];
1053 u8 tls_1_3_aes_gcm_128[0x1];
1054 u8 tls_1_2_aes_gcm_256[0x1];
1055 u8 tls_1_3_aes_gcm_256[0x1];
1056 u8 reserved_at_4[0x1c];
1057
1058 u8 reserved_at_20[0x7e0];
1059 };
1060
1061 enum {
1062 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1063 MLX5_WQ_TYPE_CYCLIC = 0x1,
1064 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1065 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1066 };
1067
1068 enum {
1069 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1070 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1071 };
1072
1073 enum {
1074 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1075 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1076 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1077 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1078 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1079 };
1080
1081 enum {
1082 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1083 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1084 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1085 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1086 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1087 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1088 };
1089
1090 enum {
1091 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1092 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1093 };
1094
1095 enum {
1096 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1097 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1098 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1099 };
1100
1101 enum {
1102 MLX5_CAP_PORT_TYPE_IB = 0x0,
1103 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1104 };
1105
1106 enum {
1107 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1108 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1109 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1110 };
1111
1112 enum {
1113 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1114 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1115 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1116 };
1117
1118 enum {
1119 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1120 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1121 };
1122
1123 #define MLX5_FC_BULK_SIZE_FACTOR 128
1124
1125 enum mlx5_fc_bulk_alloc_bitmask {
1126 MLX5_FC_BULK_128 = (1 << 0),
1127 MLX5_FC_BULK_256 = (1 << 1),
1128 MLX5_FC_BULK_512 = (1 << 2),
1129 MLX5_FC_BULK_1024 = (1 << 3),
1130 MLX5_FC_BULK_2048 = (1 << 4),
1131 MLX5_FC_BULK_4096 = (1 << 5),
1132 MLX5_FC_BULK_8192 = (1 << 6),
1133 MLX5_FC_BULK_16384 = (1 << 7),
1134 };
1135
1136 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1137
1138 struct mlx5_ifc_cmd_hca_cap_bits {
1139 u8 reserved_at_0[0x30];
1140 u8 vhca_id[0x10];
1141
1142 u8 reserved_at_40[0x40];
1143
1144 u8 log_max_srq_sz[0x8];
1145 u8 log_max_qp_sz[0x8];
1146 u8 event_cap[0x1];
1147 u8 reserved_at_91[0x7];
1148 u8 prio_tag_required[0x1];
1149 u8 reserved_at_99[0x2];
1150 u8 log_max_qp[0x5];
1151
1152 u8 reserved_at_a0[0xb];
1153 u8 log_max_srq[0x5];
1154 u8 reserved_at_b0[0x10];
1155
1156 u8 reserved_at_c0[0x8];
1157 u8 log_max_cq_sz[0x8];
1158 u8 reserved_at_d0[0xb];
1159 u8 log_max_cq[0x5];
1160
1161 u8 log_max_eq_sz[0x8];
1162 u8 reserved_at_e8[0x2];
1163 u8 log_max_mkey[0x6];
1164 u8 reserved_at_f0[0x8];
1165 u8 dump_fill_mkey[0x1];
1166 u8 reserved_at_f9[0x2];
1167 u8 fast_teardown[0x1];
1168 u8 log_max_eq[0x4];
1169
1170 u8 max_indirection[0x8];
1171 u8 fixed_buffer_size[0x1];
1172 u8 log_max_mrw_sz[0x7];
1173 u8 force_teardown[0x1];
1174 u8 reserved_at_111[0x1];
1175 u8 log_max_bsf_list_size[0x6];
1176 u8 umr_extended_translation_offset[0x1];
1177 u8 null_mkey[0x1];
1178 u8 log_max_klm_list_size[0x6];
1179
1180 u8 reserved_at_120[0xa];
1181 u8 log_max_ra_req_dc[0x6];
1182 u8 reserved_at_130[0xa];
1183 u8 log_max_ra_res_dc[0x6];
1184
1185 u8 reserved_at_140[0xa];
1186 u8 log_max_ra_req_qp[0x6];
1187 u8 reserved_at_150[0xa];
1188 u8 log_max_ra_res_qp[0x6];
1189
1190 u8 end_pad[0x1];
1191 u8 cc_query_allowed[0x1];
1192 u8 cc_modify_allowed[0x1];
1193 u8 start_pad[0x1];
1194 u8 cache_line_128byte[0x1];
1195 u8 reserved_at_165[0x4];
1196 u8 rts2rts_qp_counters_set_id[0x1];
1197 u8 reserved_at_16a[0x2];
1198 u8 vnic_env_int_rq_oob[0x1];
1199 u8 sbcam_reg[0x1];
1200 u8 reserved_at_16e[0x1];
1201 u8 qcam_reg[0x1];
1202 u8 gid_table_size[0x10];
1203
1204 u8 out_of_seq_cnt[0x1];
1205 u8 vport_counters[0x1];
1206 u8 retransmission_q_counters[0x1];
1207 u8 debug[0x1];
1208 u8 modify_rq_counter_set_id[0x1];
1209 u8 rq_delay_drop[0x1];
1210 u8 max_qp_cnt[0xa];
1211 u8 pkey_table_size[0x10];
1212
1213 u8 vport_group_manager[0x1];
1214 u8 vhca_group_manager[0x1];
1215 u8 ib_virt[0x1];
1216 u8 eth_virt[0x1];
1217 u8 vnic_env_queue_counters[0x1];
1218 u8 ets[0x1];
1219 u8 nic_flow_table[0x1];
1220 u8 eswitch_manager[0x1];
1221 u8 device_memory[0x1];
1222 u8 mcam_reg[0x1];
1223 u8 pcam_reg[0x1];
1224 u8 local_ca_ack_delay[0x5];
1225 u8 port_module_event[0x1];
1226 u8 enhanced_error_q_counters[0x1];
1227 u8 ports_check[0x1];
1228 u8 reserved_at_1b3[0x1];
1229 u8 disable_link_up[0x1];
1230 u8 beacon_led[0x1];
1231 u8 port_type[0x2];
1232 u8 num_ports[0x8];
1233
1234 u8 reserved_at_1c0[0x1];
1235 u8 pps[0x1];
1236 u8 pps_modify[0x1];
1237 u8 log_max_msg[0x5];
1238 u8 reserved_at_1c8[0x4];
1239 u8 max_tc[0x4];
1240 u8 temp_warn_event[0x1];
1241 u8 dcbx[0x1];
1242 u8 general_notification_event[0x1];
1243 u8 reserved_at_1d3[0x2];
1244 u8 fpga[0x1];
1245 u8 rol_s[0x1];
1246 u8 rol_g[0x1];
1247 u8 reserved_at_1d8[0x1];
1248 u8 wol_s[0x1];
1249 u8 wol_g[0x1];
1250 u8 wol_a[0x1];
1251 u8 wol_b[0x1];
1252 u8 wol_m[0x1];
1253 u8 wol_u[0x1];
1254 u8 wol_p[0x1];
1255
1256 u8 stat_rate_support[0x10];
1257 u8 reserved_at_1f0[0xc];
1258 u8 cqe_version[0x4];
1259
1260 u8 compact_address_vector[0x1];
1261 u8 striding_rq[0x1];
1262 u8 reserved_at_202[0x1];
1263 u8 ipoib_enhanced_offloads[0x1];
1264 u8 ipoib_basic_offloads[0x1];
1265 u8 reserved_at_205[0x1];
1266 u8 repeated_block_disabled[0x1];
1267 u8 umr_modify_entity_size_disabled[0x1];
1268 u8 umr_modify_atomic_disabled[0x1];
1269 u8 umr_indirect_mkey_disabled[0x1];
1270 u8 umr_fence[0x2];
1271 u8 dc_req_scat_data_cqe[0x1];
1272 u8 reserved_at_20d[0x2];
1273 u8 drain_sigerr[0x1];
1274 u8 cmdif_checksum[0x2];
1275 u8 sigerr_cqe[0x1];
1276 u8 reserved_at_213[0x1];
1277 u8 wq_signature[0x1];
1278 u8 sctr_data_cqe[0x1];
1279 u8 reserved_at_216[0x1];
1280 u8 sho[0x1];
1281 u8 tph[0x1];
1282 u8 rf[0x1];
1283 u8 dct[0x1];
1284 u8 qos[0x1];
1285 u8 eth_net_offloads[0x1];
1286 u8 roce[0x1];
1287 u8 atomic[0x1];
1288 u8 reserved_at_21f[0x1];
1289
1290 u8 cq_oi[0x1];
1291 u8 cq_resize[0x1];
1292 u8 cq_moderation[0x1];
1293 u8 reserved_at_223[0x3];
1294 u8 cq_eq_remap[0x1];
1295 u8 pg[0x1];
1296 u8 block_lb_mc[0x1];
1297 u8 reserved_at_229[0x1];
1298 u8 scqe_break_moderation[0x1];
1299 u8 cq_period_start_from_cqe[0x1];
1300 u8 cd[0x1];
1301 u8 reserved_at_22d[0x1];
1302 u8 apm[0x1];
1303 u8 vector_calc[0x1];
1304 u8 umr_ptr_rlky[0x1];
1305 u8 imaicl[0x1];
1306 u8 qp_packet_based[0x1];
1307 u8 reserved_at_233[0x3];
1308 u8 qkv[0x1];
1309 u8 pkv[0x1];
1310 u8 set_deth_sqpn[0x1];
1311 u8 reserved_at_239[0x3];
1312 u8 xrc[0x1];
1313 u8 ud[0x1];
1314 u8 uc[0x1];
1315 u8 rc[0x1];
1316
1317 u8 uar_4k[0x1];
1318 u8 reserved_at_241[0x9];
1319 u8 uar_sz[0x6];
1320 u8 reserved_at_250[0x8];
1321 u8 log_pg_sz[0x8];
1322
1323 u8 bf[0x1];
1324 u8 driver_version[0x1];
1325 u8 pad_tx_eth_packet[0x1];
1326 u8 reserved_at_263[0x8];
1327 u8 log_bf_reg_size[0x5];
1328
1329 u8 reserved_at_270[0x8];
1330 u8 lag_tx_port_affinity[0x1];
1331 u8 reserved_at_279[0x2];
1332 u8 lag_master[0x1];
1333 u8 num_lag_ports[0x4];
1334
1335 u8 reserved_at_280[0x10];
1336 u8 max_wqe_sz_sq[0x10];
1337
1338 u8 reserved_at_2a0[0x10];
1339 u8 max_wqe_sz_rq[0x10];
1340
1341 u8 max_flow_counter_31_16[0x10];
1342 u8 max_wqe_sz_sq_dc[0x10];
1343
1344 u8 reserved_at_2e0[0x7];
1345 u8 max_qp_mcg[0x19];
1346
1347 u8 reserved_at_300[0x10];
1348 u8 flow_counter_bulk_alloc[0x8];
1349 u8 log_max_mcg[0x8];
1350
1351 u8 reserved_at_320[0x3];
1352 u8 log_max_transport_domain[0x5];
1353 u8 reserved_at_328[0x3];
1354 u8 log_max_pd[0x5];
1355 u8 reserved_at_330[0xb];
1356 u8 log_max_xrcd[0x5];
1357
1358 u8 nic_receive_steering_discard[0x1];
1359 u8 receive_discard_vport_down[0x1];
1360 u8 transmit_discard_vport_down[0x1];
1361 u8 reserved_at_343[0x5];
1362 u8 log_max_flow_counter_bulk[0x8];
1363 u8 max_flow_counter_15_0[0x10];
1364
1365
1366 u8 reserved_at_360[0x3];
1367 u8 log_max_rq[0x5];
1368 u8 reserved_at_368[0x3];
1369 u8 log_max_sq[0x5];
1370 u8 reserved_at_370[0x3];
1371 u8 log_max_tir[0x5];
1372 u8 reserved_at_378[0x3];
1373 u8 log_max_tis[0x5];
1374
1375 u8 basic_cyclic_rcv_wqe[0x1];
1376 u8 reserved_at_381[0x2];
1377 u8 log_max_rmp[0x5];
1378 u8 reserved_at_388[0x3];
1379 u8 log_max_rqt[0x5];
1380 u8 reserved_at_390[0x3];
1381 u8 log_max_rqt_size[0x5];
1382 u8 reserved_at_398[0x3];
1383 u8 log_max_tis_per_sq[0x5];
1384
1385 u8 ext_stride_num_range[0x1];
1386 u8 reserved_at_3a1[0x2];
1387 u8 log_max_stride_sz_rq[0x5];
1388 u8 reserved_at_3a8[0x3];
1389 u8 log_min_stride_sz_rq[0x5];
1390 u8 reserved_at_3b0[0x3];
1391 u8 log_max_stride_sz_sq[0x5];
1392 u8 reserved_at_3b8[0x3];
1393 u8 log_min_stride_sz_sq[0x5];
1394
1395 u8 hairpin[0x1];
1396 u8 reserved_at_3c1[0x2];
1397 u8 log_max_hairpin_queues[0x5];
1398 u8 reserved_at_3c8[0x3];
1399 u8 log_max_hairpin_wq_data_sz[0x5];
1400 u8 reserved_at_3d0[0x3];
1401 u8 log_max_hairpin_num_packets[0x5];
1402 u8 reserved_at_3d8[0x3];
1403 u8 log_max_wq_sz[0x5];
1404
1405 u8 nic_vport_change_event[0x1];
1406 u8 disable_local_lb_uc[0x1];
1407 u8 disable_local_lb_mc[0x1];
1408 u8 log_min_hairpin_wq_data_sz[0x5];
1409 u8 reserved_at_3e8[0x3];
1410 u8 log_max_vlan_list[0x5];
1411 u8 reserved_at_3f0[0x3];
1412 u8 log_max_current_mc_list[0x5];
1413 u8 reserved_at_3f8[0x3];
1414 u8 log_max_current_uc_list[0x5];
1415
1416 u8 general_obj_types[0x40];
1417
1418 u8 reserved_at_440[0x20];
1419
1420 u8 tls[0x1];
1421 u8 reserved_at_461[0x2];
1422 u8 log_max_uctx[0x5];
1423 u8 reserved_at_468[0x3];
1424 u8 log_max_umem[0x5];
1425 u8 max_num_eqs[0x10];
1426
1427 u8 reserved_at_480[0x3];
1428 u8 log_max_l2_table[0x5];
1429 u8 reserved_at_488[0x8];
1430 u8 log_uar_page_sz[0x10];
1431
1432 u8 reserved_at_4a0[0x20];
1433 u8 device_frequency_mhz[0x20];
1434 u8 device_frequency_khz[0x20];
1435
1436 u8 reserved_at_500[0x20];
1437 u8 num_of_uars_per_page[0x20];
1438
1439 u8 flex_parser_protocols[0x20];
1440
1441 u8 max_geneve_tlv_options[0x8];
1442 u8 reserved_at_568[0x3];
1443 u8 max_geneve_tlv_option_data_len[0x5];
1444 u8 reserved_at_570[0x10];
1445
1446 u8 reserved_at_580[0x33];
1447 u8 log_max_dek[0x5];
1448 u8 reserved_at_5b8[0x4];
1449 u8 mini_cqe_resp_stride_index[0x1];
1450 u8 cqe_128_always[0x1];
1451 u8 cqe_compression_128[0x1];
1452 u8 cqe_compression[0x1];
1453
1454 u8 cqe_compression_timeout[0x10];
1455 u8 cqe_compression_max_num[0x10];
1456
1457 u8 reserved_at_5e0[0x10];
1458 u8 tag_matching[0x1];
1459 u8 rndv_offload_rc[0x1];
1460 u8 rndv_offload_dc[0x1];
1461 u8 log_tag_matching_list_sz[0x5];
1462 u8 reserved_at_5f8[0x3];
1463 u8 log_max_xrq[0x5];
1464
1465 u8 affiliate_nic_vport_criteria[0x8];
1466 u8 native_port_num[0x8];
1467 u8 num_vhca_ports[0x8];
1468 u8 reserved_at_618[0x6];
1469 u8 sw_owner_id[0x1];
1470 u8 reserved_at_61f[0x1];
1471
1472 u8 max_num_of_monitor_counters[0x10];
1473 u8 num_ppcnt_monitor_counters[0x10];
1474
1475 u8 reserved_at_640[0x10];
1476 u8 num_q_monitor_counters[0x10];
1477
1478 u8 reserved_at_660[0x20];
1479
1480 u8 sf[0x1];
1481 u8 sf_set_partition[0x1];
1482 u8 reserved_at_682[0x1];
1483 u8 log_max_sf[0x5];
1484 u8 reserved_at_688[0x8];
1485 u8 log_min_sf_size[0x8];
1486 u8 max_num_sf_partitions[0x8];
1487
1488 u8 uctx_cap[0x20];
1489
1490 u8 reserved_at_6c0[0x4];
1491 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1492 u8 flex_parser_id_icmp_dw1[0x4];
1493 u8 flex_parser_id_icmp_dw0[0x4];
1494 u8 flex_parser_id_icmpv6_dw1[0x4];
1495 u8 flex_parser_id_icmpv6_dw0[0x4];
1496 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1497 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1498
1499 u8 reserved_at_6e0[0x10];
1500 u8 sf_base_id[0x10];
1501
1502 u8 reserved_at_700[0x80];
1503 u8 vhca_tunnel_commands[0x40];
1504 u8 reserved_at_7c0[0x40];
1505 };
1506
1507 enum mlx5_flow_destination_type {
1508 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1509 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1510 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1511
1512 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1513 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1514 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1515 };
1516
1517 enum mlx5_flow_table_miss_action {
1518 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1519 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1520 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1521 };
1522
1523 struct mlx5_ifc_dest_format_struct_bits {
1524 u8 destination_type[0x8];
1525 u8 destination_id[0x18];
1526
1527 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1528 u8 packet_reformat[0x1];
1529 u8 reserved_at_22[0xe];
1530 u8 destination_eswitch_owner_vhca_id[0x10];
1531 };
1532
1533 struct mlx5_ifc_flow_counter_list_bits {
1534 u8 flow_counter_id[0x20];
1535
1536 u8 reserved_at_20[0x20];
1537 };
1538
1539 struct mlx5_ifc_extended_dest_format_bits {
1540 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1541
1542 u8 packet_reformat_id[0x20];
1543
1544 u8 reserved_at_60[0x20];
1545 };
1546
1547 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1548 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1549 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1550 };
1551
1552 struct mlx5_ifc_fte_match_param_bits {
1553 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1554
1555 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1556
1557 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1558
1559 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1560
1561 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1562
1563 u8 reserved_at_a00[0x600];
1564 };
1565
1566 enum {
1567 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1568 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1569 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1570 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1571 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1572 };
1573
1574 struct mlx5_ifc_rx_hash_field_select_bits {
1575 u8 l3_prot_type[0x1];
1576 u8 l4_prot_type[0x1];
1577 u8 selected_fields[0x1e];
1578 };
1579
1580 enum {
1581 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1582 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1583 };
1584
1585 enum {
1586 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1587 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1588 };
1589
1590 struct mlx5_ifc_wq_bits {
1591 u8 wq_type[0x4];
1592 u8 wq_signature[0x1];
1593 u8 end_padding_mode[0x2];
1594 u8 cd_slave[0x1];
1595 u8 reserved_at_8[0x18];
1596
1597 u8 hds_skip_first_sge[0x1];
1598 u8 log2_hds_buf_size[0x3];
1599 u8 reserved_at_24[0x7];
1600 u8 page_offset[0x5];
1601 u8 lwm[0x10];
1602
1603 u8 reserved_at_40[0x8];
1604 u8 pd[0x18];
1605
1606 u8 reserved_at_60[0x8];
1607 u8 uar_page[0x18];
1608
1609 u8 dbr_addr[0x40];
1610
1611 u8 hw_counter[0x20];
1612
1613 u8 sw_counter[0x20];
1614
1615 u8 reserved_at_100[0xc];
1616 u8 log_wq_stride[0x4];
1617 u8 reserved_at_110[0x3];
1618 u8 log_wq_pg_sz[0x5];
1619 u8 reserved_at_118[0x3];
1620 u8 log_wq_sz[0x5];
1621
1622 u8 dbr_umem_valid[0x1];
1623 u8 wq_umem_valid[0x1];
1624 u8 reserved_at_122[0x1];
1625 u8 log_hairpin_num_packets[0x5];
1626 u8 reserved_at_128[0x3];
1627 u8 log_hairpin_data_sz[0x5];
1628
1629 u8 reserved_at_130[0x4];
1630 u8 log_wqe_num_of_strides[0x4];
1631 u8 two_byte_shift_en[0x1];
1632 u8 reserved_at_139[0x4];
1633 u8 log_wqe_stride_size[0x3];
1634
1635 u8 reserved_at_140[0x4c0];
1636
1637 struct mlx5_ifc_cmd_pas_bits pas[0];
1638 };
1639
1640 struct mlx5_ifc_rq_num_bits {
1641 u8 reserved_at_0[0x8];
1642 u8 rq_num[0x18];
1643 };
1644
1645 struct mlx5_ifc_mac_address_layout_bits {
1646 u8 reserved_at_0[0x10];
1647 u8 mac_addr_47_32[0x10];
1648
1649 u8 mac_addr_31_0[0x20];
1650 };
1651
1652 struct mlx5_ifc_vlan_layout_bits {
1653 u8 reserved_at_0[0x14];
1654 u8 vlan[0x0c];
1655
1656 u8 reserved_at_20[0x20];
1657 };
1658
1659 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1660 u8 reserved_at_0[0xa0];
1661
1662 u8 min_time_between_cnps[0x20];
1663
1664 u8 reserved_at_c0[0x12];
1665 u8 cnp_dscp[0x6];
1666 u8 reserved_at_d8[0x4];
1667 u8 cnp_prio_mode[0x1];
1668 u8 cnp_802p_prio[0x3];
1669
1670 u8 reserved_at_e0[0x720];
1671 };
1672
1673 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1674 u8 reserved_at_0[0x60];
1675
1676 u8 reserved_at_60[0x4];
1677 u8 clamp_tgt_rate[0x1];
1678 u8 reserved_at_65[0x3];
1679 u8 clamp_tgt_rate_after_time_inc[0x1];
1680 u8 reserved_at_69[0x17];
1681
1682 u8 reserved_at_80[0x20];
1683
1684 u8 rpg_time_reset[0x20];
1685
1686 u8 rpg_byte_reset[0x20];
1687
1688 u8 rpg_threshold[0x20];
1689
1690 u8 rpg_max_rate[0x20];
1691
1692 u8 rpg_ai_rate[0x20];
1693
1694 u8 rpg_hai_rate[0x20];
1695
1696 u8 rpg_gd[0x20];
1697
1698 u8 rpg_min_dec_fac[0x20];
1699
1700 u8 rpg_min_rate[0x20];
1701
1702 u8 reserved_at_1c0[0xe0];
1703
1704 u8 rate_to_set_on_first_cnp[0x20];
1705
1706 u8 dce_tcp_g[0x20];
1707
1708 u8 dce_tcp_rtt[0x20];
1709
1710 u8 rate_reduce_monitor_period[0x20];
1711
1712 u8 reserved_at_320[0x20];
1713
1714 u8 initial_alpha_value[0x20];
1715
1716 u8 reserved_at_360[0x4a0];
1717 };
1718
1719 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1720 u8 reserved_at_0[0x80];
1721
1722 u8 rppp_max_rps[0x20];
1723
1724 u8 rpg_time_reset[0x20];
1725
1726 u8 rpg_byte_reset[0x20];
1727
1728 u8 rpg_threshold[0x20];
1729
1730 u8 rpg_max_rate[0x20];
1731
1732 u8 rpg_ai_rate[0x20];
1733
1734 u8 rpg_hai_rate[0x20];
1735
1736 u8 rpg_gd[0x20];
1737
1738 u8 rpg_min_dec_fac[0x20];
1739
1740 u8 rpg_min_rate[0x20];
1741
1742 u8 reserved_at_1c0[0x640];
1743 };
1744
1745 enum {
1746 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1747 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1748 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1749 };
1750
1751 struct mlx5_ifc_resize_field_select_bits {
1752 u8 resize_field_select[0x20];
1753 };
1754
1755 enum {
1756 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1757 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1758 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1759 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1760 };
1761
1762 struct mlx5_ifc_modify_field_select_bits {
1763 u8 modify_field_select[0x20];
1764 };
1765
1766 struct mlx5_ifc_field_select_r_roce_np_bits {
1767 u8 field_select_r_roce_np[0x20];
1768 };
1769
1770 struct mlx5_ifc_field_select_r_roce_rp_bits {
1771 u8 field_select_r_roce_rp[0x20];
1772 };
1773
1774 enum {
1775 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1776 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1777 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1778 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1779 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1780 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1781 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1782 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1783 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1784 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1785 };
1786
1787 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1788 u8 field_select_8021qaurp[0x20];
1789 };
1790
1791 struct mlx5_ifc_phys_layer_cntrs_bits {
1792 u8 time_since_last_clear_high[0x20];
1793
1794 u8 time_since_last_clear_low[0x20];
1795
1796 u8 symbol_errors_high[0x20];
1797
1798 u8 symbol_errors_low[0x20];
1799
1800 u8 sync_headers_errors_high[0x20];
1801
1802 u8 sync_headers_errors_low[0x20];
1803
1804 u8 edpl_bip_errors_lane0_high[0x20];
1805
1806 u8 edpl_bip_errors_lane0_low[0x20];
1807
1808 u8 edpl_bip_errors_lane1_high[0x20];
1809
1810 u8 edpl_bip_errors_lane1_low[0x20];
1811
1812 u8 edpl_bip_errors_lane2_high[0x20];
1813
1814 u8 edpl_bip_errors_lane2_low[0x20];
1815
1816 u8 edpl_bip_errors_lane3_high[0x20];
1817
1818 u8 edpl_bip_errors_lane3_low[0x20];
1819
1820 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1821
1822 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1823
1824 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1825
1826 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1827
1828 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1829
1830 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1831
1832 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1833
1834 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1835
1836 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1837
1838 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1839
1840 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1841
1842 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1843
1844 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1845
1846 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1847
1848 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1849
1850 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1851
1852 u8 rs_fec_corrected_blocks_high[0x20];
1853
1854 u8 rs_fec_corrected_blocks_low[0x20];
1855
1856 u8 rs_fec_uncorrectable_blocks_high[0x20];
1857
1858 u8 rs_fec_uncorrectable_blocks_low[0x20];
1859
1860 u8 rs_fec_no_errors_blocks_high[0x20];
1861
1862 u8 rs_fec_no_errors_blocks_low[0x20];
1863
1864 u8 rs_fec_single_error_blocks_high[0x20];
1865
1866 u8 rs_fec_single_error_blocks_low[0x20];
1867
1868 u8 rs_fec_corrected_symbols_total_high[0x20];
1869
1870 u8 rs_fec_corrected_symbols_total_low[0x20];
1871
1872 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1873
1874 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1875
1876 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1877
1878 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1879
1880 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1881
1882 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1883
1884 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1885
1886 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1887
1888 u8 link_down_events[0x20];
1889
1890 u8 successful_recovery_events[0x20];
1891
1892 u8 reserved_at_640[0x180];
1893 };
1894
1895 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1896 u8 time_since_last_clear_high[0x20];
1897
1898 u8 time_since_last_clear_low[0x20];
1899
1900 u8 phy_received_bits_high[0x20];
1901
1902 u8 phy_received_bits_low[0x20];
1903
1904 u8 phy_symbol_errors_high[0x20];
1905
1906 u8 phy_symbol_errors_low[0x20];
1907
1908 u8 phy_corrected_bits_high[0x20];
1909
1910 u8 phy_corrected_bits_low[0x20];
1911
1912 u8 phy_corrected_bits_lane0_high[0x20];
1913
1914 u8 phy_corrected_bits_lane0_low[0x20];
1915
1916 u8 phy_corrected_bits_lane1_high[0x20];
1917
1918 u8 phy_corrected_bits_lane1_low[0x20];
1919
1920 u8 phy_corrected_bits_lane2_high[0x20];
1921
1922 u8 phy_corrected_bits_lane2_low[0x20];
1923
1924 u8 phy_corrected_bits_lane3_high[0x20];
1925
1926 u8 phy_corrected_bits_lane3_low[0x20];
1927
1928 u8 reserved_at_200[0x5c0];
1929 };
1930
1931 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1932 u8 symbol_error_counter[0x10];
1933
1934 u8 link_error_recovery_counter[0x8];
1935
1936 u8 link_downed_counter[0x8];
1937
1938 u8 port_rcv_errors[0x10];
1939
1940 u8 port_rcv_remote_physical_errors[0x10];
1941
1942 u8 port_rcv_switch_relay_errors[0x10];
1943
1944 u8 port_xmit_discards[0x10];
1945
1946 u8 port_xmit_constraint_errors[0x8];
1947
1948 u8 port_rcv_constraint_errors[0x8];
1949
1950 u8 reserved_at_70[0x8];
1951
1952 u8 link_overrun_errors[0x8];
1953
1954 u8 reserved_at_80[0x10];
1955
1956 u8 vl_15_dropped[0x10];
1957
1958 u8 reserved_at_a0[0x80];
1959
1960 u8 port_xmit_wait[0x20];
1961 };
1962
1963 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
1964 u8 transmit_queue_high[0x20];
1965
1966 u8 transmit_queue_low[0x20];
1967
1968 u8 no_buffer_discard_uc_high[0x20];
1969
1970 u8 no_buffer_discard_uc_low[0x20];
1971
1972 u8 reserved_at_80[0x740];
1973 };
1974
1975 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
1976 u8 wred_discard_high[0x20];
1977
1978 u8 wred_discard_low[0x20];
1979
1980 u8 ecn_marked_tc_high[0x20];
1981
1982 u8 ecn_marked_tc_low[0x20];
1983
1984 u8 reserved_at_80[0x740];
1985 };
1986
1987 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1988 u8 rx_octets_high[0x20];
1989
1990 u8 rx_octets_low[0x20];
1991
1992 u8 reserved_at_40[0xc0];
1993
1994 u8 rx_frames_high[0x20];
1995
1996 u8 rx_frames_low[0x20];
1997
1998 u8 tx_octets_high[0x20];
1999
2000 u8 tx_octets_low[0x20];
2001
2002 u8 reserved_at_180[0xc0];
2003
2004 u8 tx_frames_high[0x20];
2005
2006 u8 tx_frames_low[0x20];
2007
2008 u8 rx_pause_high[0x20];
2009
2010 u8 rx_pause_low[0x20];
2011
2012 u8 rx_pause_duration_high[0x20];
2013
2014 u8 rx_pause_duration_low[0x20];
2015
2016 u8 tx_pause_high[0x20];
2017
2018 u8 tx_pause_low[0x20];
2019
2020 u8 tx_pause_duration_high[0x20];
2021
2022 u8 tx_pause_duration_low[0x20];
2023
2024 u8 rx_pause_transition_high[0x20];
2025
2026 u8 rx_pause_transition_low[0x20];
2027
2028 u8 reserved_at_3c0[0x40];
2029
2030 u8 device_stall_minor_watermark_cnt_high[0x20];
2031
2032 u8 device_stall_minor_watermark_cnt_low[0x20];
2033
2034 u8 device_stall_critical_watermark_cnt_high[0x20];
2035
2036 u8 device_stall_critical_watermark_cnt_low[0x20];
2037
2038 u8 reserved_at_480[0x340];
2039 };
2040
2041 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2042 u8 port_transmit_wait_high[0x20];
2043
2044 u8 port_transmit_wait_low[0x20];
2045
2046 u8 reserved_at_40[0x100];
2047
2048 u8 rx_buffer_almost_full_high[0x20];
2049
2050 u8 rx_buffer_almost_full_low[0x20];
2051
2052 u8 rx_buffer_full_high[0x20];
2053
2054 u8 rx_buffer_full_low[0x20];
2055
2056 u8 rx_icrc_encapsulated_high[0x20];
2057
2058 u8 rx_icrc_encapsulated_low[0x20];
2059
2060 u8 reserved_at_200[0x5c0];
2061 };
2062
2063 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2064 u8 dot3stats_alignment_errors_high[0x20];
2065
2066 u8 dot3stats_alignment_errors_low[0x20];
2067
2068 u8 dot3stats_fcs_errors_high[0x20];
2069
2070 u8 dot3stats_fcs_errors_low[0x20];
2071
2072 u8 dot3stats_single_collision_frames_high[0x20];
2073
2074 u8 dot3stats_single_collision_frames_low[0x20];
2075
2076 u8 dot3stats_multiple_collision_frames_high[0x20];
2077
2078 u8 dot3stats_multiple_collision_frames_low[0x20];
2079
2080 u8 dot3stats_sqe_test_errors_high[0x20];
2081
2082 u8 dot3stats_sqe_test_errors_low[0x20];
2083
2084 u8 dot3stats_deferred_transmissions_high[0x20];
2085
2086 u8 dot3stats_deferred_transmissions_low[0x20];
2087
2088 u8 dot3stats_late_collisions_high[0x20];
2089
2090 u8 dot3stats_late_collisions_low[0x20];
2091
2092 u8 dot3stats_excessive_collisions_high[0x20];
2093
2094 u8 dot3stats_excessive_collisions_low[0x20];
2095
2096 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2097
2098 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2099
2100 u8 dot3stats_carrier_sense_errors_high[0x20];
2101
2102 u8 dot3stats_carrier_sense_errors_low[0x20];
2103
2104 u8 dot3stats_frame_too_longs_high[0x20];
2105
2106 u8 dot3stats_frame_too_longs_low[0x20];
2107
2108 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2109
2110 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2111
2112 u8 dot3stats_symbol_errors_high[0x20];
2113
2114 u8 dot3stats_symbol_errors_low[0x20];
2115
2116 u8 dot3control_in_unknown_opcodes_high[0x20];
2117
2118 u8 dot3control_in_unknown_opcodes_low[0x20];
2119
2120 u8 dot3in_pause_frames_high[0x20];
2121
2122 u8 dot3in_pause_frames_low[0x20];
2123
2124 u8 dot3out_pause_frames_high[0x20];
2125
2126 u8 dot3out_pause_frames_low[0x20];
2127
2128 u8 reserved_at_400[0x3c0];
2129 };
2130
2131 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2132 u8 ether_stats_drop_events_high[0x20];
2133
2134 u8 ether_stats_drop_events_low[0x20];
2135
2136 u8 ether_stats_octets_high[0x20];
2137
2138 u8 ether_stats_octets_low[0x20];
2139
2140 u8 ether_stats_pkts_high[0x20];
2141
2142 u8 ether_stats_pkts_low[0x20];
2143
2144 u8 ether_stats_broadcast_pkts_high[0x20];
2145
2146 u8 ether_stats_broadcast_pkts_low[0x20];
2147
2148 u8 ether_stats_multicast_pkts_high[0x20];
2149
2150 u8 ether_stats_multicast_pkts_low[0x20];
2151
2152 u8 ether_stats_crc_align_errors_high[0x20];
2153
2154 u8 ether_stats_crc_align_errors_low[0x20];
2155
2156 u8 ether_stats_undersize_pkts_high[0x20];
2157
2158 u8 ether_stats_undersize_pkts_low[0x20];
2159
2160 u8 ether_stats_oversize_pkts_high[0x20];
2161
2162 u8 ether_stats_oversize_pkts_low[0x20];
2163
2164 u8 ether_stats_fragments_high[0x20];
2165
2166 u8 ether_stats_fragments_low[0x20];
2167
2168 u8 ether_stats_jabbers_high[0x20];
2169
2170 u8 ether_stats_jabbers_low[0x20];
2171
2172 u8 ether_stats_collisions_high[0x20];
2173
2174 u8 ether_stats_collisions_low[0x20];
2175
2176 u8 ether_stats_pkts64octets_high[0x20];
2177
2178 u8 ether_stats_pkts64octets_low[0x20];
2179
2180 u8 ether_stats_pkts65to127octets_high[0x20];
2181
2182 u8 ether_stats_pkts65to127octets_low[0x20];
2183
2184 u8 ether_stats_pkts128to255octets_high[0x20];
2185
2186 u8 ether_stats_pkts128to255octets_low[0x20];
2187
2188 u8 ether_stats_pkts256to511octets_high[0x20];
2189
2190 u8 ether_stats_pkts256to511octets_low[0x20];
2191
2192 u8 ether_stats_pkts512to1023octets_high[0x20];
2193
2194 u8 ether_stats_pkts512to1023octets_low[0x20];
2195
2196 u8 ether_stats_pkts1024to1518octets_high[0x20];
2197
2198 u8 ether_stats_pkts1024to1518octets_low[0x20];
2199
2200 u8 ether_stats_pkts1519to2047octets_high[0x20];
2201
2202 u8 ether_stats_pkts1519to2047octets_low[0x20];
2203
2204 u8 ether_stats_pkts2048to4095octets_high[0x20];
2205
2206 u8 ether_stats_pkts2048to4095octets_low[0x20];
2207
2208 u8 ether_stats_pkts4096to8191octets_high[0x20];
2209
2210 u8 ether_stats_pkts4096to8191octets_low[0x20];
2211
2212 u8 ether_stats_pkts8192to10239octets_high[0x20];
2213
2214 u8 ether_stats_pkts8192to10239octets_low[0x20];
2215
2216 u8 reserved_at_540[0x280];
2217 };
2218
2219 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2220 u8 if_in_octets_high[0x20];
2221
2222 u8 if_in_octets_low[0x20];
2223
2224 u8 if_in_ucast_pkts_high[0x20];
2225
2226 u8 if_in_ucast_pkts_low[0x20];
2227
2228 u8 if_in_discards_high[0x20];
2229
2230 u8 if_in_discards_low[0x20];
2231
2232 u8 if_in_errors_high[0x20];
2233
2234 u8 if_in_errors_low[0x20];
2235
2236 u8 if_in_unknown_protos_high[0x20];
2237
2238 u8 if_in_unknown_protos_low[0x20];
2239
2240 u8 if_out_octets_high[0x20];
2241
2242 u8 if_out_octets_low[0x20];
2243
2244 u8 if_out_ucast_pkts_high[0x20];
2245
2246 u8 if_out_ucast_pkts_low[0x20];
2247
2248 u8 if_out_discards_high[0x20];
2249
2250 u8 if_out_discards_low[0x20];
2251
2252 u8 if_out_errors_high[0x20];
2253
2254 u8 if_out_errors_low[0x20];
2255
2256 u8 if_in_multicast_pkts_high[0x20];
2257
2258 u8 if_in_multicast_pkts_low[0x20];
2259
2260 u8 if_in_broadcast_pkts_high[0x20];
2261
2262 u8 if_in_broadcast_pkts_low[0x20];
2263
2264 u8 if_out_multicast_pkts_high[0x20];
2265
2266 u8 if_out_multicast_pkts_low[0x20];
2267
2268 u8 if_out_broadcast_pkts_high[0x20];
2269
2270 u8 if_out_broadcast_pkts_low[0x20];
2271
2272 u8 reserved_at_340[0x480];
2273 };
2274
2275 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2276 u8 a_frames_transmitted_ok_high[0x20];
2277
2278 u8 a_frames_transmitted_ok_low[0x20];
2279
2280 u8 a_frames_received_ok_high[0x20];
2281
2282 u8 a_frames_received_ok_low[0x20];
2283
2284 u8 a_frame_check_sequence_errors_high[0x20];
2285
2286 u8 a_frame_check_sequence_errors_low[0x20];
2287
2288 u8 a_alignment_errors_high[0x20];
2289
2290 u8 a_alignment_errors_low[0x20];
2291
2292 u8 a_octets_transmitted_ok_high[0x20];
2293
2294 u8 a_octets_transmitted_ok_low[0x20];
2295
2296 u8 a_octets_received_ok_high[0x20];
2297
2298 u8 a_octets_received_ok_low[0x20];
2299
2300 u8 a_multicast_frames_xmitted_ok_high[0x20];
2301
2302 u8 a_multicast_frames_xmitted_ok_low[0x20];
2303
2304 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2305
2306 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2307
2308 u8 a_multicast_frames_received_ok_high[0x20];
2309
2310 u8 a_multicast_frames_received_ok_low[0x20];
2311
2312 u8 a_broadcast_frames_received_ok_high[0x20];
2313
2314 u8 a_broadcast_frames_received_ok_low[0x20];
2315
2316 u8 a_in_range_length_errors_high[0x20];
2317
2318 u8 a_in_range_length_errors_low[0x20];
2319
2320 u8 a_out_of_range_length_field_high[0x20];
2321
2322 u8 a_out_of_range_length_field_low[0x20];
2323
2324 u8 a_frame_too_long_errors_high[0x20];
2325
2326 u8 a_frame_too_long_errors_low[0x20];
2327
2328 u8 a_symbol_error_during_carrier_high[0x20];
2329
2330 u8 a_symbol_error_during_carrier_low[0x20];
2331
2332 u8 a_mac_control_frames_transmitted_high[0x20];
2333
2334 u8 a_mac_control_frames_transmitted_low[0x20];
2335
2336 u8 a_mac_control_frames_received_high[0x20];
2337
2338 u8 a_mac_control_frames_received_low[0x20];
2339
2340 u8 a_unsupported_opcodes_received_high[0x20];
2341
2342 u8 a_unsupported_opcodes_received_low[0x20];
2343
2344 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2345
2346 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2347
2348 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2349
2350 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2351
2352 u8 reserved_at_4c0[0x300];
2353 };
2354
2355 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2356 u8 life_time_counter_high[0x20];
2357
2358 u8 life_time_counter_low[0x20];
2359
2360 u8 rx_errors[0x20];
2361
2362 u8 tx_errors[0x20];
2363
2364 u8 l0_to_recovery_eieos[0x20];
2365
2366 u8 l0_to_recovery_ts[0x20];
2367
2368 u8 l0_to_recovery_framing[0x20];
2369
2370 u8 l0_to_recovery_retrain[0x20];
2371
2372 u8 crc_error_dllp[0x20];
2373
2374 u8 crc_error_tlp[0x20];
2375
2376 u8 tx_overflow_buffer_pkt_high[0x20];
2377
2378 u8 tx_overflow_buffer_pkt_low[0x20];
2379
2380 u8 outbound_stalled_reads[0x20];
2381
2382 u8 outbound_stalled_writes[0x20];
2383
2384 u8 outbound_stalled_reads_events[0x20];
2385
2386 u8 outbound_stalled_writes_events[0x20];
2387
2388 u8 reserved_at_200[0x5c0];
2389 };
2390
2391 struct mlx5_ifc_cmd_inter_comp_event_bits {
2392 u8 command_completion_vector[0x20];
2393
2394 u8 reserved_at_20[0xc0];
2395 };
2396
2397 struct mlx5_ifc_stall_vl_event_bits {
2398 u8 reserved_at_0[0x18];
2399 u8 port_num[0x1];
2400 u8 reserved_at_19[0x3];
2401 u8 vl[0x4];
2402
2403 u8 reserved_at_20[0xa0];
2404 };
2405
2406 struct mlx5_ifc_db_bf_congestion_event_bits {
2407 u8 event_subtype[0x8];
2408 u8 reserved_at_8[0x8];
2409 u8 congestion_level[0x8];
2410 u8 reserved_at_18[0x8];
2411
2412 u8 reserved_at_20[0xa0];
2413 };
2414
2415 struct mlx5_ifc_gpio_event_bits {
2416 u8 reserved_at_0[0x60];
2417
2418 u8 gpio_event_hi[0x20];
2419
2420 u8 gpio_event_lo[0x20];
2421
2422 u8 reserved_at_a0[0x40];
2423 };
2424
2425 struct mlx5_ifc_port_state_change_event_bits {
2426 u8 reserved_at_0[0x40];
2427
2428 u8 port_num[0x4];
2429 u8 reserved_at_44[0x1c];
2430
2431 u8 reserved_at_60[0x80];
2432 };
2433
2434 struct mlx5_ifc_dropped_packet_logged_bits {
2435 u8 reserved_at_0[0xe0];
2436 };
2437
2438 enum {
2439 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2440 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2441 };
2442
2443 struct mlx5_ifc_cq_error_bits {
2444 u8 reserved_at_0[0x8];
2445 u8 cqn[0x18];
2446
2447 u8 reserved_at_20[0x20];
2448
2449 u8 reserved_at_40[0x18];
2450 u8 syndrome[0x8];
2451
2452 u8 reserved_at_60[0x80];
2453 };
2454
2455 struct mlx5_ifc_rdma_page_fault_event_bits {
2456 u8 bytes_committed[0x20];
2457
2458 u8 r_key[0x20];
2459
2460 u8 reserved_at_40[0x10];
2461 u8 packet_len[0x10];
2462
2463 u8 rdma_op_len[0x20];
2464
2465 u8 rdma_va[0x40];
2466
2467 u8 reserved_at_c0[0x5];
2468 u8 rdma[0x1];
2469 u8 write[0x1];
2470 u8 requestor[0x1];
2471 u8 qp_number[0x18];
2472 };
2473
2474 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2475 u8 bytes_committed[0x20];
2476
2477 u8 reserved_at_20[0x10];
2478 u8 wqe_index[0x10];
2479
2480 u8 reserved_at_40[0x10];
2481 u8 len[0x10];
2482
2483 u8 reserved_at_60[0x60];
2484
2485 u8 reserved_at_c0[0x5];
2486 u8 rdma[0x1];
2487 u8 write_read[0x1];
2488 u8 requestor[0x1];
2489 u8 qpn[0x18];
2490 };
2491
2492 struct mlx5_ifc_qp_events_bits {
2493 u8 reserved_at_0[0xa0];
2494
2495 u8 type[0x8];
2496 u8 reserved_at_a8[0x18];
2497
2498 u8 reserved_at_c0[0x8];
2499 u8 qpn_rqn_sqn[0x18];
2500 };
2501
2502 struct mlx5_ifc_dct_events_bits {
2503 u8 reserved_at_0[0xc0];
2504
2505 u8 reserved_at_c0[0x8];
2506 u8 dct_number[0x18];
2507 };
2508
2509 struct mlx5_ifc_comp_event_bits {
2510 u8 reserved_at_0[0xc0];
2511
2512 u8 reserved_at_c0[0x8];
2513 u8 cq_number[0x18];
2514 };
2515
2516 enum {
2517 MLX5_QPC_STATE_RST = 0x0,
2518 MLX5_QPC_STATE_INIT = 0x1,
2519 MLX5_QPC_STATE_RTR = 0x2,
2520 MLX5_QPC_STATE_RTS = 0x3,
2521 MLX5_QPC_STATE_SQER = 0x4,
2522 MLX5_QPC_STATE_ERR = 0x6,
2523 MLX5_QPC_STATE_SQD = 0x7,
2524 MLX5_QPC_STATE_SUSPENDED = 0x9,
2525 };
2526
2527 enum {
2528 MLX5_QPC_ST_RC = 0x0,
2529 MLX5_QPC_ST_UC = 0x1,
2530 MLX5_QPC_ST_UD = 0x2,
2531 MLX5_QPC_ST_XRC = 0x3,
2532 MLX5_QPC_ST_DCI = 0x5,
2533 MLX5_QPC_ST_QP0 = 0x7,
2534 MLX5_QPC_ST_QP1 = 0x8,
2535 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2536 MLX5_QPC_ST_REG_UMR = 0xc,
2537 };
2538
2539 enum {
2540 MLX5_QPC_PM_STATE_ARMED = 0x0,
2541 MLX5_QPC_PM_STATE_REARM = 0x1,
2542 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2543 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2544 };
2545
2546 enum {
2547 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2548 };
2549
2550 enum {
2551 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2552 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2553 };
2554
2555 enum {
2556 MLX5_QPC_MTU_256_BYTES = 0x1,
2557 MLX5_QPC_MTU_512_BYTES = 0x2,
2558 MLX5_QPC_MTU_1K_BYTES = 0x3,
2559 MLX5_QPC_MTU_2K_BYTES = 0x4,
2560 MLX5_QPC_MTU_4K_BYTES = 0x5,
2561 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2562 };
2563
2564 enum {
2565 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2566 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2567 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2568 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2569 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2570 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2571 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2572 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2573 };
2574
2575 enum {
2576 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2577 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2578 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2579 };
2580
2581 enum {
2582 MLX5_QPC_CS_RES_DISABLE = 0x0,
2583 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2584 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2585 };
2586
2587 struct mlx5_ifc_qpc_bits {
2588 u8 state[0x4];
2589 u8 lag_tx_port_affinity[0x4];
2590 u8 st[0x8];
2591 u8 reserved_at_10[0x3];
2592 u8 pm_state[0x2];
2593 u8 reserved_at_15[0x1];
2594 u8 req_e2e_credit_mode[0x2];
2595 u8 offload_type[0x4];
2596 u8 end_padding_mode[0x2];
2597 u8 reserved_at_1e[0x2];
2598
2599 u8 wq_signature[0x1];
2600 u8 block_lb_mc[0x1];
2601 u8 atomic_like_write_en[0x1];
2602 u8 latency_sensitive[0x1];
2603 u8 reserved_at_24[0x1];
2604 u8 drain_sigerr[0x1];
2605 u8 reserved_at_26[0x2];
2606 u8 pd[0x18];
2607
2608 u8 mtu[0x3];
2609 u8 log_msg_max[0x5];
2610 u8 reserved_at_48[0x1];
2611 u8 log_rq_size[0x4];
2612 u8 log_rq_stride[0x3];
2613 u8 no_sq[0x1];
2614 u8 log_sq_size[0x4];
2615 u8 reserved_at_55[0x6];
2616 u8 rlky[0x1];
2617 u8 ulp_stateless_offload_mode[0x4];
2618
2619 u8 counter_set_id[0x8];
2620 u8 uar_page[0x18];
2621
2622 u8 reserved_at_80[0x8];
2623 u8 user_index[0x18];
2624
2625 u8 reserved_at_a0[0x3];
2626 u8 log_page_size[0x5];
2627 u8 remote_qpn[0x18];
2628
2629 struct mlx5_ifc_ads_bits primary_address_path;
2630
2631 struct mlx5_ifc_ads_bits secondary_address_path;
2632
2633 u8 log_ack_req_freq[0x4];
2634 u8 reserved_at_384[0x4];
2635 u8 log_sra_max[0x3];
2636 u8 reserved_at_38b[0x2];
2637 u8 retry_count[0x3];
2638 u8 rnr_retry[0x3];
2639 u8 reserved_at_393[0x1];
2640 u8 fre[0x1];
2641 u8 cur_rnr_retry[0x3];
2642 u8 cur_retry_count[0x3];
2643 u8 reserved_at_39b[0x5];
2644
2645 u8 reserved_at_3a0[0x20];
2646
2647 u8 reserved_at_3c0[0x8];
2648 u8 next_send_psn[0x18];
2649
2650 u8 reserved_at_3e0[0x8];
2651 u8 cqn_snd[0x18];
2652
2653 u8 reserved_at_400[0x8];
2654 u8 deth_sqpn[0x18];
2655
2656 u8 reserved_at_420[0x20];
2657
2658 u8 reserved_at_440[0x8];
2659 u8 last_acked_psn[0x18];
2660
2661 u8 reserved_at_460[0x8];
2662 u8 ssn[0x18];
2663
2664 u8 reserved_at_480[0x8];
2665 u8 log_rra_max[0x3];
2666 u8 reserved_at_48b[0x1];
2667 u8 atomic_mode[0x4];
2668 u8 rre[0x1];
2669 u8 rwe[0x1];
2670 u8 rae[0x1];
2671 u8 reserved_at_493[0x1];
2672 u8 page_offset[0x6];
2673 u8 reserved_at_49a[0x3];
2674 u8 cd_slave_receive[0x1];
2675 u8 cd_slave_send[0x1];
2676 u8 cd_master[0x1];
2677
2678 u8 reserved_at_4a0[0x3];
2679 u8 min_rnr_nak[0x5];
2680 u8 next_rcv_psn[0x18];
2681
2682 u8 reserved_at_4c0[0x8];
2683 u8 xrcd[0x18];
2684
2685 u8 reserved_at_4e0[0x8];
2686 u8 cqn_rcv[0x18];
2687
2688 u8 dbr_addr[0x40];
2689
2690 u8 q_key[0x20];
2691
2692 u8 reserved_at_560[0x5];
2693 u8 rq_type[0x3];
2694 u8 srqn_rmpn_xrqn[0x18];
2695
2696 u8 reserved_at_580[0x8];
2697 u8 rmsn[0x18];
2698
2699 u8 hw_sq_wqebb_counter[0x10];
2700 u8 sw_sq_wqebb_counter[0x10];
2701
2702 u8 hw_rq_counter[0x20];
2703
2704 u8 sw_rq_counter[0x20];
2705
2706 u8 reserved_at_600[0x20];
2707
2708 u8 reserved_at_620[0xf];
2709 u8 cgs[0x1];
2710 u8 cs_req[0x8];
2711 u8 cs_res[0x8];
2712
2713 u8 dc_access_key[0x40];
2714
2715 u8 reserved_at_680[0x3];
2716 u8 dbr_umem_valid[0x1];
2717
2718 u8 reserved_at_684[0xbc];
2719 };
2720
2721 struct mlx5_ifc_roce_addr_layout_bits {
2722 u8 source_l3_address[16][0x8];
2723
2724 u8 reserved_at_80[0x3];
2725 u8 vlan_valid[0x1];
2726 u8 vlan_id[0xc];
2727 u8 source_mac_47_32[0x10];
2728
2729 u8 source_mac_31_0[0x20];
2730
2731 u8 reserved_at_c0[0x14];
2732 u8 roce_l3_type[0x4];
2733 u8 roce_version[0x8];
2734
2735 u8 reserved_at_e0[0x20];
2736 };
2737
2738 union mlx5_ifc_hca_cap_union_bits {
2739 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2740 struct mlx5_ifc_odp_cap_bits odp_cap;
2741 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2742 struct mlx5_ifc_roce_cap_bits roce_cap;
2743 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2744 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2745 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2746 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2747 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2748 struct mlx5_ifc_qos_cap_bits qos_cap;
2749 struct mlx5_ifc_debug_cap_bits debug_cap;
2750 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2751 struct mlx5_ifc_tls_cap_bits tls_cap;
2752 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2753 u8 reserved_at_0[0x8000];
2754 };
2755
2756 enum {
2757 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2758 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2759 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2760 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2761 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2762 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2763 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2764 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2765 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2766 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2767 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2768 };
2769
2770 enum {
2771 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
2772 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
2773 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
2774 };
2775
2776 struct mlx5_ifc_vlan_bits {
2777 u8 ethtype[0x10];
2778 u8 prio[0x3];
2779 u8 cfi[0x1];
2780 u8 vid[0xc];
2781 };
2782
2783 struct mlx5_ifc_flow_context_bits {
2784 struct mlx5_ifc_vlan_bits push_vlan;
2785
2786 u8 group_id[0x20];
2787
2788 u8 reserved_at_40[0x8];
2789 u8 flow_tag[0x18];
2790
2791 u8 reserved_at_60[0x10];
2792 u8 action[0x10];
2793
2794 u8 extended_destination[0x1];
2795 u8 reserved_at_81[0x1];
2796 u8 flow_source[0x2];
2797 u8 reserved_at_84[0x4];
2798 u8 destination_list_size[0x18];
2799
2800 u8 reserved_at_a0[0x8];
2801 u8 flow_counter_list_size[0x18];
2802
2803 u8 packet_reformat_id[0x20];
2804
2805 u8 modify_header_id[0x20];
2806
2807 struct mlx5_ifc_vlan_bits push_vlan_2;
2808
2809 u8 reserved_at_120[0xe0];
2810
2811 struct mlx5_ifc_fte_match_param_bits match_value;
2812
2813 u8 reserved_at_1200[0x600];
2814
2815 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2816 };
2817
2818 enum {
2819 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2820 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2821 };
2822
2823 struct mlx5_ifc_xrc_srqc_bits {
2824 u8 state[0x4];
2825 u8 log_xrc_srq_size[0x4];
2826 u8 reserved_at_8[0x18];
2827
2828 u8 wq_signature[0x1];
2829 u8 cont_srq[0x1];
2830 u8 reserved_at_22[0x1];
2831 u8 rlky[0x1];
2832 u8 basic_cyclic_rcv_wqe[0x1];
2833 u8 log_rq_stride[0x3];
2834 u8 xrcd[0x18];
2835
2836 u8 page_offset[0x6];
2837 u8 reserved_at_46[0x1];
2838 u8 dbr_umem_valid[0x1];
2839 u8 cqn[0x18];
2840
2841 u8 reserved_at_60[0x20];
2842
2843 u8 user_index_equal_xrc_srqn[0x1];
2844 u8 reserved_at_81[0x1];
2845 u8 log_page_size[0x6];
2846 u8 user_index[0x18];
2847
2848 u8 reserved_at_a0[0x20];
2849
2850 u8 reserved_at_c0[0x8];
2851 u8 pd[0x18];
2852
2853 u8 lwm[0x10];
2854 u8 wqe_cnt[0x10];
2855
2856 u8 reserved_at_100[0x40];
2857
2858 u8 db_record_addr_h[0x20];
2859
2860 u8 db_record_addr_l[0x1e];
2861 u8 reserved_at_17e[0x2];
2862
2863 u8 reserved_at_180[0x80];
2864 };
2865
2866 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2867 u8 counter_error_queues[0x20];
2868
2869 u8 total_error_queues[0x20];
2870
2871 u8 send_queue_priority_update_flow[0x20];
2872
2873 u8 reserved_at_60[0x20];
2874
2875 u8 nic_receive_steering_discard[0x40];
2876
2877 u8 receive_discard_vport_down[0x40];
2878
2879 u8 transmit_discard_vport_down[0x40];
2880
2881 u8 reserved_at_140[0xa0];
2882
2883 u8 internal_rq_out_of_buffer[0x20];
2884
2885 u8 reserved_at_200[0xe00];
2886 };
2887
2888 struct mlx5_ifc_traffic_counter_bits {
2889 u8 packets[0x40];
2890
2891 u8 octets[0x40];
2892 };
2893
2894 struct mlx5_ifc_tisc_bits {
2895 u8 strict_lag_tx_port_affinity[0x1];
2896 u8 tls_en[0x1];
2897 u8 reserved_at_2[0x2];
2898 u8 lag_tx_port_affinity[0x04];
2899
2900 u8 reserved_at_8[0x4];
2901 u8 prio[0x4];
2902 u8 reserved_at_10[0x10];
2903
2904 u8 reserved_at_20[0x100];
2905
2906 u8 reserved_at_120[0x8];
2907 u8 transport_domain[0x18];
2908
2909 u8 reserved_at_140[0x8];
2910 u8 underlay_qpn[0x18];
2911
2912 u8 reserved_at_160[0x8];
2913 u8 pd[0x18];
2914
2915 u8 reserved_at_180[0x380];
2916 };
2917
2918 enum {
2919 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2920 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2921 };
2922
2923 enum {
2924 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2925 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2926 };
2927
2928 enum {
2929 MLX5_RX_HASH_FN_NONE = 0x0,
2930 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2931 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2932 };
2933
2934 enum {
2935 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2936 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2937 };
2938
2939 struct mlx5_ifc_tirc_bits {
2940 u8 reserved_at_0[0x20];
2941
2942 u8 disp_type[0x4];
2943 u8 reserved_at_24[0x1c];
2944
2945 u8 reserved_at_40[0x40];
2946
2947 u8 reserved_at_80[0x4];
2948 u8 lro_timeout_period_usecs[0x10];
2949 u8 lro_enable_mask[0x4];
2950 u8 lro_max_ip_payload_size[0x8];
2951
2952 u8 reserved_at_a0[0x40];
2953
2954 u8 reserved_at_e0[0x8];
2955 u8 inline_rqn[0x18];
2956
2957 u8 rx_hash_symmetric[0x1];
2958 u8 reserved_at_101[0x1];
2959 u8 tunneled_offload_en[0x1];
2960 u8 reserved_at_103[0x5];
2961 u8 indirect_table[0x18];
2962
2963 u8 rx_hash_fn[0x4];
2964 u8 reserved_at_124[0x2];
2965 u8 self_lb_block[0x2];
2966 u8 transport_domain[0x18];
2967
2968 u8 rx_hash_toeplitz_key[10][0x20];
2969
2970 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2971
2972 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2973
2974 u8 reserved_at_2c0[0x4c0];
2975 };
2976
2977 enum {
2978 MLX5_SRQC_STATE_GOOD = 0x0,
2979 MLX5_SRQC_STATE_ERROR = 0x1,
2980 };
2981
2982 struct mlx5_ifc_srqc_bits {
2983 u8 state[0x4];
2984 u8 log_srq_size[0x4];
2985 u8 reserved_at_8[0x18];
2986
2987 u8 wq_signature[0x1];
2988 u8 cont_srq[0x1];
2989 u8 reserved_at_22[0x1];
2990 u8 rlky[0x1];
2991 u8 reserved_at_24[0x1];
2992 u8 log_rq_stride[0x3];
2993 u8 xrcd[0x18];
2994
2995 u8 page_offset[0x6];
2996 u8 reserved_at_46[0x2];
2997 u8 cqn[0x18];
2998
2999 u8 reserved_at_60[0x20];
3000
3001 u8 reserved_at_80[0x2];
3002 u8 log_page_size[0x6];
3003 u8 reserved_at_88[0x18];
3004
3005 u8 reserved_at_a0[0x20];
3006
3007 u8 reserved_at_c0[0x8];
3008 u8 pd[0x18];
3009
3010 u8 lwm[0x10];
3011 u8 wqe_cnt[0x10];
3012
3013 u8 reserved_at_100[0x40];
3014
3015 u8 dbr_addr[0x40];
3016
3017 u8 reserved_at_180[0x80];
3018 };
3019
3020 enum {
3021 MLX5_SQC_STATE_RST = 0x0,
3022 MLX5_SQC_STATE_RDY = 0x1,
3023 MLX5_SQC_STATE_ERR = 0x3,
3024 };
3025
3026 struct mlx5_ifc_sqc_bits {
3027 u8 rlky[0x1];
3028 u8 cd_master[0x1];
3029 u8 fre[0x1];
3030 u8 flush_in_error_en[0x1];
3031 u8 allow_multi_pkt_send_wqe[0x1];
3032 u8 min_wqe_inline_mode[0x3];
3033 u8 state[0x4];
3034 u8 reg_umr[0x1];
3035 u8 allow_swp[0x1];
3036 u8 hairpin[0x1];
3037 u8 reserved_at_f[0x11];
3038
3039 u8 reserved_at_20[0x8];
3040 u8 user_index[0x18];
3041
3042 u8 reserved_at_40[0x8];
3043 u8 cqn[0x18];
3044
3045 u8 reserved_at_60[0x8];
3046 u8 hairpin_peer_rq[0x18];
3047
3048 u8 reserved_at_80[0x10];
3049 u8 hairpin_peer_vhca[0x10];
3050
3051 u8 reserved_at_a0[0x50];
3052
3053 u8 packet_pacing_rate_limit_index[0x10];
3054 u8 tis_lst_sz[0x10];
3055 u8 reserved_at_110[0x10];
3056
3057 u8 reserved_at_120[0x40];
3058
3059 u8 reserved_at_160[0x8];
3060 u8 tis_num_0[0x18];
3061
3062 struct mlx5_ifc_wq_bits wq;
3063 };
3064
3065 enum {
3066 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3067 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3068 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3069 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3070 };
3071
3072 enum {
3073 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3074 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3075 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3076 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3077 };
3078
3079 struct mlx5_ifc_scheduling_context_bits {
3080 u8 element_type[0x8];
3081 u8 reserved_at_8[0x18];
3082
3083 u8 element_attributes[0x20];
3084
3085 u8 parent_element_id[0x20];
3086
3087 u8 reserved_at_60[0x40];
3088
3089 u8 bw_share[0x20];
3090
3091 u8 max_average_bw[0x20];
3092
3093 u8 reserved_at_e0[0x120];
3094 };
3095
3096 struct mlx5_ifc_rqtc_bits {
3097 u8 reserved_at_0[0xa0];
3098
3099 u8 reserved_at_a0[0x10];
3100 u8 rqt_max_size[0x10];
3101
3102 u8 reserved_at_c0[0x10];
3103 u8 rqt_actual_size[0x10];
3104
3105 u8 reserved_at_e0[0x6a0];
3106
3107 struct mlx5_ifc_rq_num_bits rq_num[0];
3108 };
3109
3110 enum {
3111 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3112 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3113 };
3114
3115 enum {
3116 MLX5_RQC_STATE_RST = 0x0,
3117 MLX5_RQC_STATE_RDY = 0x1,
3118 MLX5_RQC_STATE_ERR = 0x3,
3119 };
3120
3121 struct mlx5_ifc_rqc_bits {
3122 u8 rlky[0x1];
3123 u8 delay_drop_en[0x1];
3124 u8 scatter_fcs[0x1];
3125 u8 vsd[0x1];
3126 u8 mem_rq_type[0x4];
3127 u8 state[0x4];
3128 u8 reserved_at_c[0x1];
3129 u8 flush_in_error_en[0x1];
3130 u8 hairpin[0x1];
3131 u8 reserved_at_f[0x11];
3132
3133 u8 reserved_at_20[0x8];
3134 u8 user_index[0x18];
3135
3136 u8 reserved_at_40[0x8];
3137 u8 cqn[0x18];
3138
3139 u8 counter_set_id[0x8];
3140 u8 reserved_at_68[0x18];
3141
3142 u8 reserved_at_80[0x8];
3143 u8 rmpn[0x18];
3144
3145 u8 reserved_at_a0[0x8];
3146 u8 hairpin_peer_sq[0x18];
3147
3148 u8 reserved_at_c0[0x10];
3149 u8 hairpin_peer_vhca[0x10];
3150
3151 u8 reserved_at_e0[0xa0];
3152
3153 struct mlx5_ifc_wq_bits wq;
3154 };
3155
3156 enum {
3157 MLX5_RMPC_STATE_RDY = 0x1,
3158 MLX5_RMPC_STATE_ERR = 0x3,
3159 };
3160
3161 struct mlx5_ifc_rmpc_bits {
3162 u8 reserved_at_0[0x8];
3163 u8 state[0x4];
3164 u8 reserved_at_c[0x14];
3165
3166 u8 basic_cyclic_rcv_wqe[0x1];
3167 u8 reserved_at_21[0x1f];
3168
3169 u8 reserved_at_40[0x140];
3170
3171 struct mlx5_ifc_wq_bits wq;
3172 };
3173
3174 struct mlx5_ifc_nic_vport_context_bits {
3175 u8 reserved_at_0[0x5];
3176 u8 min_wqe_inline_mode[0x3];
3177 u8 reserved_at_8[0x15];
3178 u8 disable_mc_local_lb[0x1];
3179 u8 disable_uc_local_lb[0x1];
3180 u8 roce_en[0x1];
3181
3182 u8 arm_change_event[0x1];
3183 u8 reserved_at_21[0x1a];
3184 u8 event_on_mtu[0x1];
3185 u8 event_on_promisc_change[0x1];
3186 u8 event_on_vlan_change[0x1];
3187 u8 event_on_mc_address_change[0x1];
3188 u8 event_on_uc_address_change[0x1];
3189
3190 u8 reserved_at_40[0xc];
3191
3192 u8 affiliation_criteria[0x4];
3193 u8 affiliated_vhca_id[0x10];
3194
3195 u8 reserved_at_60[0xd0];
3196
3197 u8 mtu[0x10];
3198
3199 u8 system_image_guid[0x40];
3200 u8 port_guid[0x40];
3201 u8 node_guid[0x40];
3202
3203 u8 reserved_at_200[0x140];
3204 u8 qkey_violation_counter[0x10];
3205 u8 reserved_at_350[0x430];
3206
3207 u8 promisc_uc[0x1];
3208 u8 promisc_mc[0x1];
3209 u8 promisc_all[0x1];
3210 u8 reserved_at_783[0x2];
3211 u8 allowed_list_type[0x3];
3212 u8 reserved_at_788[0xc];
3213 u8 allowed_list_size[0xc];
3214
3215 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3216
3217 u8 reserved_at_7e0[0x20];
3218
3219 u8 current_uc_mac_address[0][0x40];
3220 };
3221
3222 enum {
3223 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3224 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3225 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3226 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3227 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3228 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3229 };
3230
3231 struct mlx5_ifc_mkc_bits {
3232 u8 reserved_at_0[0x1];
3233 u8 free[0x1];
3234 u8 reserved_at_2[0x1];
3235 u8 access_mode_4_2[0x3];
3236 u8 reserved_at_6[0x7];
3237 u8 relaxed_ordering_write[0x1];
3238 u8 reserved_at_e[0x1];
3239 u8 small_fence_on_rdma_read_response[0x1];
3240 u8 umr_en[0x1];
3241 u8 a[0x1];
3242 u8 rw[0x1];
3243 u8 rr[0x1];
3244 u8 lw[0x1];
3245 u8 lr[0x1];
3246 u8 access_mode_1_0[0x2];
3247 u8 reserved_at_18[0x8];
3248
3249 u8 qpn[0x18];
3250 u8 mkey_7_0[0x8];
3251
3252 u8 reserved_at_40[0x20];
3253
3254 u8 length64[0x1];
3255 u8 bsf_en[0x1];
3256 u8 sync_umr[0x1];
3257 u8 reserved_at_63[0x2];
3258 u8 expected_sigerr_count[0x1];
3259 u8 reserved_at_66[0x1];
3260 u8 en_rinval[0x1];
3261 u8 pd[0x18];
3262
3263 u8 start_addr[0x40];
3264
3265 u8 len[0x40];
3266
3267 u8 bsf_octword_size[0x20];
3268
3269 u8 reserved_at_120[0x80];
3270
3271 u8 translations_octword_size[0x20];
3272
3273 u8 reserved_at_1c0[0x1b];
3274 u8 log_page_size[0x5];
3275
3276 u8 reserved_at_1e0[0x20];
3277 };
3278
3279 struct mlx5_ifc_pkey_bits {
3280 u8 reserved_at_0[0x10];
3281 u8 pkey[0x10];
3282 };
3283
3284 struct mlx5_ifc_array128_auto_bits {
3285 u8 array128_auto[16][0x8];
3286 };
3287
3288 struct mlx5_ifc_hca_vport_context_bits {
3289 u8 field_select[0x20];
3290
3291 u8 reserved_at_20[0xe0];
3292
3293 u8 sm_virt_aware[0x1];
3294 u8 has_smi[0x1];
3295 u8 has_raw[0x1];
3296 u8 grh_required[0x1];
3297 u8 reserved_at_104[0xc];
3298 u8 port_physical_state[0x4];
3299 u8 vport_state_policy[0x4];
3300 u8 port_state[0x4];
3301 u8 vport_state[0x4];
3302
3303 u8 reserved_at_120[0x20];
3304
3305 u8 system_image_guid[0x40];
3306
3307 u8 port_guid[0x40];
3308
3309 u8 node_guid[0x40];
3310
3311 u8 cap_mask1[0x20];
3312
3313 u8 cap_mask1_field_select[0x20];
3314
3315 u8 cap_mask2[0x20];
3316
3317 u8 cap_mask2_field_select[0x20];
3318
3319 u8 reserved_at_280[0x80];
3320
3321 u8 lid[0x10];
3322 u8 reserved_at_310[0x4];
3323 u8 init_type_reply[0x4];
3324 u8 lmc[0x3];
3325 u8 subnet_timeout[0x5];
3326
3327 u8 sm_lid[0x10];
3328 u8 sm_sl[0x4];
3329 u8 reserved_at_334[0xc];
3330
3331 u8 qkey_violation_counter[0x10];
3332 u8 pkey_violation_counter[0x10];
3333
3334 u8 reserved_at_360[0xca0];
3335 };
3336
3337 struct mlx5_ifc_esw_vport_context_bits {
3338 u8 fdb_to_vport_reg_c[0x1];
3339 u8 reserved_at_1[0x2];
3340 u8 vport_svlan_strip[0x1];
3341 u8 vport_cvlan_strip[0x1];
3342 u8 vport_svlan_insert[0x1];
3343 u8 vport_cvlan_insert[0x2];
3344 u8 fdb_to_vport_reg_c_id[0x8];
3345 u8 reserved_at_10[0x10];
3346
3347 u8 reserved_at_20[0x20];
3348
3349 u8 svlan_cfi[0x1];
3350 u8 svlan_pcp[0x3];
3351 u8 svlan_id[0xc];
3352 u8 cvlan_cfi[0x1];
3353 u8 cvlan_pcp[0x3];
3354 u8 cvlan_id[0xc];
3355
3356 u8 reserved_at_60[0x720];
3357
3358 u8 sw_steering_vport_icm_address_rx[0x40];
3359
3360 u8 sw_steering_vport_icm_address_tx[0x40];
3361 };
3362
3363 enum {
3364 MLX5_EQC_STATUS_OK = 0x0,
3365 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3366 };
3367
3368 enum {
3369 MLX5_EQC_ST_ARMED = 0x9,
3370 MLX5_EQC_ST_FIRED = 0xa,
3371 };
3372
3373 struct mlx5_ifc_eqc_bits {
3374 u8 status[0x4];
3375 u8 reserved_at_4[0x9];
3376 u8 ec[0x1];
3377 u8 oi[0x1];
3378 u8 reserved_at_f[0x5];
3379 u8 st[0x4];
3380 u8 reserved_at_18[0x8];
3381
3382 u8 reserved_at_20[0x20];
3383
3384 u8 reserved_at_40[0x14];
3385 u8 page_offset[0x6];
3386 u8 reserved_at_5a[0x6];
3387
3388 u8 reserved_at_60[0x3];
3389 u8 log_eq_size[0x5];
3390 u8 uar_page[0x18];
3391
3392 u8 reserved_at_80[0x20];
3393
3394 u8 reserved_at_a0[0x18];
3395 u8 intr[0x8];
3396
3397 u8 reserved_at_c0[0x3];
3398 u8 log_page_size[0x5];
3399 u8 reserved_at_c8[0x18];
3400
3401 u8 reserved_at_e0[0x60];
3402
3403 u8 reserved_at_140[0x8];
3404 u8 consumer_counter[0x18];
3405
3406 u8 reserved_at_160[0x8];
3407 u8 producer_counter[0x18];
3408
3409 u8 reserved_at_180[0x80];
3410 };
3411
3412 enum {
3413 MLX5_DCTC_STATE_ACTIVE = 0x0,
3414 MLX5_DCTC_STATE_DRAINING = 0x1,
3415 MLX5_DCTC_STATE_DRAINED = 0x2,
3416 };
3417
3418 enum {
3419 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3420 MLX5_DCTC_CS_RES_NA = 0x1,
3421 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3422 };
3423
3424 enum {
3425 MLX5_DCTC_MTU_256_BYTES = 0x1,
3426 MLX5_DCTC_MTU_512_BYTES = 0x2,
3427 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3428 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3429 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3430 };
3431
3432 struct mlx5_ifc_dctc_bits {
3433 u8 reserved_at_0[0x4];
3434 u8 state[0x4];
3435 u8 reserved_at_8[0x18];
3436
3437 u8 reserved_at_20[0x8];
3438 u8 user_index[0x18];
3439
3440 u8 reserved_at_40[0x8];
3441 u8 cqn[0x18];
3442
3443 u8 counter_set_id[0x8];
3444 u8 atomic_mode[0x4];
3445 u8 rre[0x1];
3446 u8 rwe[0x1];
3447 u8 rae[0x1];
3448 u8 atomic_like_write_en[0x1];
3449 u8 latency_sensitive[0x1];
3450 u8 rlky[0x1];
3451 u8 free_ar[0x1];
3452 u8 reserved_at_73[0xd];
3453
3454 u8 reserved_at_80[0x8];
3455 u8 cs_res[0x8];
3456 u8 reserved_at_90[0x3];
3457 u8 min_rnr_nak[0x5];
3458 u8 reserved_at_98[0x8];
3459
3460 u8 reserved_at_a0[0x8];
3461 u8 srqn_xrqn[0x18];
3462
3463 u8 reserved_at_c0[0x8];
3464 u8 pd[0x18];
3465
3466 u8 tclass[0x8];
3467 u8 reserved_at_e8[0x4];
3468 u8 flow_label[0x14];
3469
3470 u8 dc_access_key[0x40];
3471
3472 u8 reserved_at_140[0x5];
3473 u8 mtu[0x3];
3474 u8 port[0x8];
3475 u8 pkey_index[0x10];
3476
3477 u8 reserved_at_160[0x8];
3478 u8 my_addr_index[0x8];
3479 u8 reserved_at_170[0x8];
3480 u8 hop_limit[0x8];
3481
3482 u8 dc_access_key_violation_count[0x20];
3483
3484 u8 reserved_at_1a0[0x14];
3485 u8 dei_cfi[0x1];
3486 u8 eth_prio[0x3];
3487 u8 ecn[0x2];
3488 u8 dscp[0x6];
3489
3490 u8 reserved_at_1c0[0x40];
3491 };
3492
3493 enum {
3494 MLX5_CQC_STATUS_OK = 0x0,
3495 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3496 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3497 };
3498
3499 enum {
3500 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3501 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3502 };
3503
3504 enum {
3505 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3506 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3507 MLX5_CQC_ST_FIRED = 0xa,
3508 };
3509
3510 enum {
3511 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3512 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3513 MLX5_CQ_PERIOD_NUM_MODES
3514 };
3515
3516 struct mlx5_ifc_cqc_bits {
3517 u8 status[0x4];
3518 u8 reserved_at_4[0x2];
3519 u8 dbr_umem_valid[0x1];
3520 u8 reserved_at_7[0x1];
3521 u8 cqe_sz[0x3];
3522 u8 cc[0x1];
3523 u8 reserved_at_c[0x1];
3524 u8 scqe_break_moderation_en[0x1];
3525 u8 oi[0x1];
3526 u8 cq_period_mode[0x2];
3527 u8 cqe_comp_en[0x1];
3528 u8 mini_cqe_res_format[0x2];
3529 u8 st[0x4];
3530 u8 reserved_at_18[0x8];
3531
3532 u8 reserved_at_20[0x20];
3533
3534 u8 reserved_at_40[0x14];
3535 u8 page_offset[0x6];
3536 u8 reserved_at_5a[0x6];
3537
3538 u8 reserved_at_60[0x3];
3539 u8 log_cq_size[0x5];
3540 u8 uar_page[0x18];
3541
3542 u8 reserved_at_80[0x4];
3543 u8 cq_period[0xc];
3544 u8 cq_max_count[0x10];
3545
3546 u8 reserved_at_a0[0x18];
3547 u8 c_eqn[0x8];
3548
3549 u8 reserved_at_c0[0x3];
3550 u8 log_page_size[0x5];
3551 u8 reserved_at_c8[0x18];
3552
3553 u8 reserved_at_e0[0x20];
3554
3555 u8 reserved_at_100[0x8];
3556 u8 last_notified_index[0x18];
3557
3558 u8 reserved_at_120[0x8];
3559 u8 last_solicit_index[0x18];
3560
3561 u8 reserved_at_140[0x8];
3562 u8 consumer_counter[0x18];
3563
3564 u8 reserved_at_160[0x8];
3565 u8 producer_counter[0x18];
3566
3567 u8 reserved_at_180[0x40];
3568
3569 u8 dbr_addr[0x40];
3570 };
3571
3572 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3573 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3574 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3575 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3576 u8 reserved_at_0[0x800];
3577 };
3578
3579 struct mlx5_ifc_query_adapter_param_block_bits {
3580 u8 reserved_at_0[0xc0];
3581
3582 u8 reserved_at_c0[0x8];
3583 u8 ieee_vendor_id[0x18];
3584
3585 u8 reserved_at_e0[0x10];
3586 u8 vsd_vendor_id[0x10];
3587
3588 u8 vsd[208][0x8];
3589
3590 u8 vsd_contd_psid[16][0x8];
3591 };
3592
3593 enum {
3594 MLX5_XRQC_STATE_GOOD = 0x0,
3595 MLX5_XRQC_STATE_ERROR = 0x1,
3596 };
3597
3598 enum {
3599 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3600 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3601 };
3602
3603 enum {
3604 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3605 };
3606
3607 struct mlx5_ifc_tag_matching_topology_context_bits {
3608 u8 log_matching_list_sz[0x4];
3609 u8 reserved_at_4[0xc];
3610 u8 append_next_index[0x10];
3611
3612 u8 sw_phase_cnt[0x10];
3613 u8 hw_phase_cnt[0x10];
3614
3615 u8 reserved_at_40[0x40];
3616 };
3617
3618 struct mlx5_ifc_xrqc_bits {
3619 u8 state[0x4];
3620 u8 rlkey[0x1];
3621 u8 reserved_at_5[0xf];
3622 u8 topology[0x4];
3623 u8 reserved_at_18[0x4];
3624 u8 offload[0x4];
3625
3626 u8 reserved_at_20[0x8];
3627 u8 user_index[0x18];
3628
3629 u8 reserved_at_40[0x8];
3630 u8 cqn[0x18];
3631
3632 u8 reserved_at_60[0xa0];
3633
3634 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3635
3636 u8 reserved_at_180[0x280];
3637
3638 struct mlx5_ifc_wq_bits wq;
3639 };
3640
3641 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3642 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3643 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3644 u8 reserved_at_0[0x20];
3645 };
3646
3647 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3648 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3649 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3650 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3651 u8 reserved_at_0[0x20];
3652 };
3653
3654 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3655 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3656 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3657 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3658 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3659 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3660 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3661 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3662 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3663 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3664 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3665 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3666 u8 reserved_at_0[0x7c0];
3667 };
3668
3669 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3670 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3671 u8 reserved_at_0[0x7c0];
3672 };
3673
3674 union mlx5_ifc_event_auto_bits {
3675 struct mlx5_ifc_comp_event_bits comp_event;
3676 struct mlx5_ifc_dct_events_bits dct_events;
3677 struct mlx5_ifc_qp_events_bits qp_events;
3678 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3679 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3680 struct mlx5_ifc_cq_error_bits cq_error;
3681 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3682 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3683 struct mlx5_ifc_gpio_event_bits gpio_event;
3684 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3685 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3686 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3687 u8 reserved_at_0[0xe0];
3688 };
3689
3690 struct mlx5_ifc_health_buffer_bits {
3691 u8 reserved_at_0[0x100];
3692
3693 u8 assert_existptr[0x20];
3694
3695 u8 assert_callra[0x20];
3696
3697 u8 reserved_at_140[0x40];
3698
3699 u8 fw_version[0x20];
3700
3701 u8 hw_id[0x20];
3702
3703 u8 reserved_at_1c0[0x20];
3704
3705 u8 irisc_index[0x8];
3706 u8 synd[0x8];
3707 u8 ext_synd[0x10];
3708 };
3709
3710 struct mlx5_ifc_register_loopback_control_bits {
3711 u8 no_lb[0x1];
3712 u8 reserved_at_1[0x7];
3713 u8 port[0x8];
3714 u8 reserved_at_10[0x10];
3715
3716 u8 reserved_at_20[0x60];
3717 };
3718
3719 struct mlx5_ifc_vport_tc_element_bits {
3720 u8 traffic_class[0x4];
3721 u8 reserved_at_4[0xc];
3722 u8 vport_number[0x10];
3723 };
3724
3725 struct mlx5_ifc_vport_element_bits {
3726 u8 reserved_at_0[0x10];
3727 u8 vport_number[0x10];
3728 };
3729
3730 enum {
3731 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3732 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3733 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3734 };
3735
3736 struct mlx5_ifc_tsar_element_bits {
3737 u8 reserved_at_0[0x8];
3738 u8 tsar_type[0x8];
3739 u8 reserved_at_10[0x10];
3740 };
3741
3742 enum {
3743 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3744 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3745 };
3746
3747 struct mlx5_ifc_teardown_hca_out_bits {
3748 u8 status[0x8];
3749 u8 reserved_at_8[0x18];
3750
3751 u8 syndrome[0x20];
3752
3753 u8 reserved_at_40[0x3f];
3754
3755 u8 state[0x1];
3756 };
3757
3758 enum {
3759 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3760 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3761 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3762 };
3763
3764 struct mlx5_ifc_teardown_hca_in_bits {
3765 u8 opcode[0x10];
3766 u8 reserved_at_10[0x10];
3767
3768 u8 reserved_at_20[0x10];
3769 u8 op_mod[0x10];
3770
3771 u8 reserved_at_40[0x10];
3772 u8 profile[0x10];
3773
3774 u8 reserved_at_60[0x20];
3775 };
3776
3777 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3778 u8 status[0x8];
3779 u8 reserved_at_8[0x18];
3780
3781 u8 syndrome[0x20];
3782
3783 u8 reserved_at_40[0x40];
3784 };
3785
3786 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3787 u8 opcode[0x10];
3788 u8 uid[0x10];
3789
3790 u8 reserved_at_20[0x10];
3791 u8 op_mod[0x10];
3792
3793 u8 reserved_at_40[0x8];
3794 u8 qpn[0x18];
3795
3796 u8 reserved_at_60[0x20];
3797
3798 u8 opt_param_mask[0x20];
3799
3800 u8 reserved_at_a0[0x20];
3801
3802 struct mlx5_ifc_qpc_bits qpc;
3803
3804 u8 reserved_at_800[0x80];
3805 };
3806
3807 struct mlx5_ifc_sqd2rts_qp_out_bits {
3808 u8 status[0x8];
3809 u8 reserved_at_8[0x18];
3810
3811 u8 syndrome[0x20];
3812
3813 u8 reserved_at_40[0x40];
3814 };
3815
3816 struct mlx5_ifc_sqd2rts_qp_in_bits {
3817 u8 opcode[0x10];
3818 u8 uid[0x10];
3819
3820 u8 reserved_at_20[0x10];
3821 u8 op_mod[0x10];
3822
3823 u8 reserved_at_40[0x8];
3824 u8 qpn[0x18];
3825
3826 u8 reserved_at_60[0x20];
3827
3828 u8 opt_param_mask[0x20];
3829
3830 u8 reserved_at_a0[0x20];
3831
3832 struct mlx5_ifc_qpc_bits qpc;
3833
3834 u8 reserved_at_800[0x80];
3835 };
3836
3837 struct mlx5_ifc_set_roce_address_out_bits {
3838 u8 status[0x8];
3839 u8 reserved_at_8[0x18];
3840
3841 u8 syndrome[0x20];
3842
3843 u8 reserved_at_40[0x40];
3844 };
3845
3846 struct mlx5_ifc_set_roce_address_in_bits {
3847 u8 opcode[0x10];
3848 u8 reserved_at_10[0x10];
3849
3850 u8 reserved_at_20[0x10];
3851 u8 op_mod[0x10];
3852
3853 u8 roce_address_index[0x10];
3854 u8 reserved_at_50[0xc];
3855 u8 vhca_port_num[0x4];
3856
3857 u8 reserved_at_60[0x20];
3858
3859 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3860 };
3861
3862 struct mlx5_ifc_set_mad_demux_out_bits {
3863 u8 status[0x8];
3864 u8 reserved_at_8[0x18];
3865
3866 u8 syndrome[0x20];
3867
3868 u8 reserved_at_40[0x40];
3869 };
3870
3871 enum {
3872 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3873 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3874 };
3875
3876 struct mlx5_ifc_set_mad_demux_in_bits {
3877 u8 opcode[0x10];
3878 u8 reserved_at_10[0x10];
3879
3880 u8 reserved_at_20[0x10];
3881 u8 op_mod[0x10];
3882
3883 u8 reserved_at_40[0x20];
3884
3885 u8 reserved_at_60[0x6];
3886 u8 demux_mode[0x2];
3887 u8 reserved_at_68[0x18];
3888 };
3889
3890 struct mlx5_ifc_set_l2_table_entry_out_bits {
3891 u8 status[0x8];
3892 u8 reserved_at_8[0x18];
3893
3894 u8 syndrome[0x20];
3895
3896 u8 reserved_at_40[0x40];
3897 };
3898
3899 struct mlx5_ifc_set_l2_table_entry_in_bits {
3900 u8 opcode[0x10];
3901 u8 reserved_at_10[0x10];
3902
3903 u8 reserved_at_20[0x10];
3904 u8 op_mod[0x10];
3905
3906 u8 reserved_at_40[0x60];
3907
3908 u8 reserved_at_a0[0x8];
3909 u8 table_index[0x18];
3910
3911 u8 reserved_at_c0[0x20];
3912
3913 u8 reserved_at_e0[0x13];
3914 u8 vlan_valid[0x1];
3915 u8 vlan[0xc];
3916
3917 struct mlx5_ifc_mac_address_layout_bits mac_address;
3918
3919 u8 reserved_at_140[0xc0];
3920 };
3921
3922 struct mlx5_ifc_set_issi_out_bits {
3923 u8 status[0x8];
3924 u8 reserved_at_8[0x18];
3925
3926 u8 syndrome[0x20];
3927
3928 u8 reserved_at_40[0x40];
3929 };
3930
3931 struct mlx5_ifc_set_issi_in_bits {
3932 u8 opcode[0x10];
3933 u8 reserved_at_10[0x10];
3934
3935 u8 reserved_at_20[0x10];
3936 u8 op_mod[0x10];
3937
3938 u8 reserved_at_40[0x10];
3939 u8 current_issi[0x10];
3940
3941 u8 reserved_at_60[0x20];
3942 };
3943
3944 struct mlx5_ifc_set_hca_cap_out_bits {
3945 u8 status[0x8];
3946 u8 reserved_at_8[0x18];
3947
3948 u8 syndrome[0x20];
3949
3950 u8 reserved_at_40[0x40];
3951 };
3952
3953 struct mlx5_ifc_set_hca_cap_in_bits {
3954 u8 opcode[0x10];
3955 u8 reserved_at_10[0x10];
3956
3957 u8 reserved_at_20[0x10];
3958 u8 op_mod[0x10];
3959
3960 u8 reserved_at_40[0x40];
3961
3962 union mlx5_ifc_hca_cap_union_bits capability;
3963 };
3964
3965 enum {
3966 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3967 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3968 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3969 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3970 };
3971
3972 struct mlx5_ifc_set_fte_out_bits {
3973 u8 status[0x8];
3974 u8 reserved_at_8[0x18];
3975
3976 u8 syndrome[0x20];
3977
3978 u8 reserved_at_40[0x40];
3979 };
3980
3981 struct mlx5_ifc_set_fte_in_bits {
3982 u8 opcode[0x10];
3983 u8 reserved_at_10[0x10];
3984
3985 u8 reserved_at_20[0x10];
3986 u8 op_mod[0x10];
3987
3988 u8 other_vport[0x1];
3989 u8 reserved_at_41[0xf];
3990 u8 vport_number[0x10];
3991
3992 u8 reserved_at_60[0x20];
3993
3994 u8 table_type[0x8];
3995 u8 reserved_at_88[0x18];
3996
3997 u8 reserved_at_a0[0x8];
3998 u8 table_id[0x18];
3999
4000 u8 reserved_at_c0[0x18];
4001 u8 modify_enable_mask[0x8];
4002
4003 u8 reserved_at_e0[0x20];
4004
4005 u8 flow_index[0x20];
4006
4007 u8 reserved_at_120[0xe0];
4008
4009 struct mlx5_ifc_flow_context_bits flow_context;
4010 };
4011
4012 struct mlx5_ifc_rts2rts_qp_out_bits {
4013 u8 status[0x8];
4014 u8 reserved_at_8[0x18];
4015
4016 u8 syndrome[0x20];
4017
4018 u8 reserved_at_40[0x40];
4019 };
4020
4021 struct mlx5_ifc_rts2rts_qp_in_bits {
4022 u8 opcode[0x10];
4023 u8 uid[0x10];
4024
4025 u8 reserved_at_20[0x10];
4026 u8 op_mod[0x10];
4027
4028 u8 reserved_at_40[0x8];
4029 u8 qpn[0x18];
4030
4031 u8 reserved_at_60[0x20];
4032
4033 u8 opt_param_mask[0x20];
4034
4035 u8 reserved_at_a0[0x20];
4036
4037 struct mlx5_ifc_qpc_bits qpc;
4038
4039 u8 reserved_at_800[0x80];
4040 };
4041
4042 struct mlx5_ifc_rtr2rts_qp_out_bits {
4043 u8 status[0x8];
4044 u8 reserved_at_8[0x18];
4045
4046 u8 syndrome[0x20];
4047
4048 u8 reserved_at_40[0x40];
4049 };
4050
4051 struct mlx5_ifc_rtr2rts_qp_in_bits {
4052 u8 opcode[0x10];
4053 u8 uid[0x10];
4054
4055 u8 reserved_at_20[0x10];
4056 u8 op_mod[0x10];
4057
4058 u8 reserved_at_40[0x8];
4059 u8 qpn[0x18];
4060
4061 u8 reserved_at_60[0x20];
4062
4063 u8 opt_param_mask[0x20];
4064
4065 u8 reserved_at_a0[0x20];
4066
4067 struct mlx5_ifc_qpc_bits qpc;
4068
4069 u8 reserved_at_800[0x80];
4070 };
4071
4072 struct mlx5_ifc_rst2init_qp_out_bits {
4073 u8 status[0x8];
4074 u8 reserved_at_8[0x18];
4075
4076 u8 syndrome[0x20];
4077
4078 u8 reserved_at_40[0x40];
4079 };
4080
4081 struct mlx5_ifc_rst2init_qp_in_bits {
4082 u8 opcode[0x10];
4083 u8 uid[0x10];
4084
4085 u8 reserved_at_20[0x10];
4086 u8 op_mod[0x10];
4087
4088 u8 reserved_at_40[0x8];
4089 u8 qpn[0x18];
4090
4091 u8 reserved_at_60[0x20];
4092
4093 u8 opt_param_mask[0x20];
4094
4095 u8 reserved_at_a0[0x20];
4096
4097 struct mlx5_ifc_qpc_bits qpc;
4098
4099 u8 reserved_at_800[0x80];
4100 };
4101
4102 struct mlx5_ifc_query_xrq_out_bits {
4103 u8 status[0x8];
4104 u8 reserved_at_8[0x18];
4105
4106 u8 syndrome[0x20];
4107
4108 u8 reserved_at_40[0x40];
4109
4110 struct mlx5_ifc_xrqc_bits xrq_context;
4111 };
4112
4113 struct mlx5_ifc_query_xrq_in_bits {
4114 u8 opcode[0x10];
4115 u8 reserved_at_10[0x10];
4116
4117 u8 reserved_at_20[0x10];
4118 u8 op_mod[0x10];
4119
4120 u8 reserved_at_40[0x8];
4121 u8 xrqn[0x18];
4122
4123 u8 reserved_at_60[0x20];
4124 };
4125
4126 struct mlx5_ifc_query_xrc_srq_out_bits {
4127 u8 status[0x8];
4128 u8 reserved_at_8[0x18];
4129
4130 u8 syndrome[0x20];
4131
4132 u8 reserved_at_40[0x40];
4133
4134 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4135
4136 u8 reserved_at_280[0x600];
4137
4138 u8 pas[0][0x40];
4139 };
4140
4141 struct mlx5_ifc_query_xrc_srq_in_bits {
4142 u8 opcode[0x10];
4143 u8 reserved_at_10[0x10];
4144
4145 u8 reserved_at_20[0x10];
4146 u8 op_mod[0x10];
4147
4148 u8 reserved_at_40[0x8];
4149 u8 xrc_srqn[0x18];
4150
4151 u8 reserved_at_60[0x20];
4152 };
4153
4154 enum {
4155 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4156 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4157 };
4158
4159 struct mlx5_ifc_query_vport_state_out_bits {
4160 u8 status[0x8];
4161 u8 reserved_at_8[0x18];
4162
4163 u8 syndrome[0x20];
4164
4165 u8 reserved_at_40[0x20];
4166
4167 u8 reserved_at_60[0x18];
4168 u8 admin_state[0x4];
4169 u8 state[0x4];
4170 };
4171
4172 enum {
4173 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4174 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4175 };
4176
4177 struct mlx5_ifc_arm_monitor_counter_in_bits {
4178 u8 opcode[0x10];
4179 u8 uid[0x10];
4180
4181 u8 reserved_at_20[0x10];
4182 u8 op_mod[0x10];
4183
4184 u8 reserved_at_40[0x20];
4185
4186 u8 reserved_at_60[0x20];
4187 };
4188
4189 struct mlx5_ifc_arm_monitor_counter_out_bits {
4190 u8 status[0x8];
4191 u8 reserved_at_8[0x18];
4192
4193 u8 syndrome[0x20];
4194
4195 u8 reserved_at_40[0x40];
4196 };
4197
4198 enum {
4199 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4200 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4201 };
4202
4203 enum mlx5_monitor_counter_ppcnt {
4204 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4205 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4206 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4207 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4208 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4209 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4210 };
4211
4212 enum {
4213 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4214 };
4215
4216 struct mlx5_ifc_monitor_counter_output_bits {
4217 u8 reserved_at_0[0x4];
4218 u8 type[0x4];
4219 u8 reserved_at_8[0x8];
4220 u8 counter[0x10];
4221
4222 u8 counter_group_id[0x20];
4223 };
4224
4225 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4226 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4227 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4228 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4229
4230 struct mlx5_ifc_set_monitor_counter_in_bits {
4231 u8 opcode[0x10];
4232 u8 uid[0x10];
4233
4234 u8 reserved_at_20[0x10];
4235 u8 op_mod[0x10];
4236
4237 u8 reserved_at_40[0x10];
4238 u8 num_of_counters[0x10];
4239
4240 u8 reserved_at_60[0x20];
4241
4242 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4243 };
4244
4245 struct mlx5_ifc_set_monitor_counter_out_bits {
4246 u8 status[0x8];
4247 u8 reserved_at_8[0x18];
4248
4249 u8 syndrome[0x20];
4250
4251 u8 reserved_at_40[0x40];
4252 };
4253
4254 struct mlx5_ifc_query_vport_state_in_bits {
4255 u8 opcode[0x10];
4256 u8 reserved_at_10[0x10];
4257
4258 u8 reserved_at_20[0x10];
4259 u8 op_mod[0x10];
4260
4261 u8 other_vport[0x1];
4262 u8 reserved_at_41[0xf];
4263 u8 vport_number[0x10];
4264
4265 u8 reserved_at_60[0x20];
4266 };
4267
4268 struct mlx5_ifc_query_vnic_env_out_bits {
4269 u8 status[0x8];
4270 u8 reserved_at_8[0x18];
4271
4272 u8 syndrome[0x20];
4273
4274 u8 reserved_at_40[0x40];
4275
4276 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4277 };
4278
4279 enum {
4280 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4281 };
4282
4283 struct mlx5_ifc_query_vnic_env_in_bits {
4284 u8 opcode[0x10];
4285 u8 reserved_at_10[0x10];
4286
4287 u8 reserved_at_20[0x10];
4288 u8 op_mod[0x10];
4289
4290 u8 other_vport[0x1];
4291 u8 reserved_at_41[0xf];
4292 u8 vport_number[0x10];
4293
4294 u8 reserved_at_60[0x20];
4295 };
4296
4297 struct mlx5_ifc_query_vport_counter_out_bits {
4298 u8 status[0x8];
4299 u8 reserved_at_8[0x18];
4300
4301 u8 syndrome[0x20];
4302
4303 u8 reserved_at_40[0x40];
4304
4305 struct mlx5_ifc_traffic_counter_bits received_errors;
4306
4307 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4308
4309 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4310
4311 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4312
4313 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4314
4315 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4316
4317 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4318
4319 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4320
4321 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4322
4323 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4324
4325 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4326
4327 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4328
4329 u8 reserved_at_680[0xa00];
4330 };
4331
4332 enum {
4333 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4334 };
4335
4336 struct mlx5_ifc_query_vport_counter_in_bits {
4337 u8 opcode[0x10];
4338 u8 reserved_at_10[0x10];
4339
4340 u8 reserved_at_20[0x10];
4341 u8 op_mod[0x10];
4342
4343 u8 other_vport[0x1];
4344 u8 reserved_at_41[0xb];
4345 u8 port_num[0x4];
4346 u8 vport_number[0x10];
4347
4348 u8 reserved_at_60[0x60];
4349
4350 u8 clear[0x1];
4351 u8 reserved_at_c1[0x1f];
4352
4353 u8 reserved_at_e0[0x20];
4354 };
4355
4356 struct mlx5_ifc_query_tis_out_bits {
4357 u8 status[0x8];
4358 u8 reserved_at_8[0x18];
4359
4360 u8 syndrome[0x20];
4361
4362 u8 reserved_at_40[0x40];
4363
4364 struct mlx5_ifc_tisc_bits tis_context;
4365 };
4366
4367 struct mlx5_ifc_query_tis_in_bits {
4368 u8 opcode[0x10];
4369 u8 reserved_at_10[0x10];
4370
4371 u8 reserved_at_20[0x10];
4372 u8 op_mod[0x10];
4373
4374 u8 reserved_at_40[0x8];
4375 u8 tisn[0x18];
4376
4377 u8 reserved_at_60[0x20];
4378 };
4379
4380 struct mlx5_ifc_query_tir_out_bits {
4381 u8 status[0x8];
4382 u8 reserved_at_8[0x18];
4383
4384 u8 syndrome[0x20];
4385
4386 u8 reserved_at_40[0xc0];
4387
4388 struct mlx5_ifc_tirc_bits tir_context;
4389 };
4390
4391 struct mlx5_ifc_query_tir_in_bits {
4392 u8 opcode[0x10];
4393 u8 reserved_at_10[0x10];
4394
4395 u8 reserved_at_20[0x10];
4396 u8 op_mod[0x10];
4397
4398 u8 reserved_at_40[0x8];
4399 u8 tirn[0x18];
4400
4401 u8 reserved_at_60[0x20];
4402 };
4403
4404 struct mlx5_ifc_query_srq_out_bits {
4405 u8 status[0x8];
4406 u8 reserved_at_8[0x18];
4407
4408 u8 syndrome[0x20];
4409
4410 u8 reserved_at_40[0x40];
4411
4412 struct mlx5_ifc_srqc_bits srq_context_entry;
4413
4414 u8 reserved_at_280[0x600];
4415
4416 u8 pas[0][0x40];
4417 };
4418
4419 struct mlx5_ifc_query_srq_in_bits {
4420 u8 opcode[0x10];
4421 u8 reserved_at_10[0x10];
4422
4423 u8 reserved_at_20[0x10];
4424 u8 op_mod[0x10];
4425
4426 u8 reserved_at_40[0x8];
4427 u8 srqn[0x18];
4428
4429 u8 reserved_at_60[0x20];
4430 };
4431
4432 struct mlx5_ifc_query_sq_out_bits {
4433 u8 status[0x8];
4434 u8 reserved_at_8[0x18];
4435
4436 u8 syndrome[0x20];
4437
4438 u8 reserved_at_40[0xc0];
4439
4440 struct mlx5_ifc_sqc_bits sq_context;
4441 };
4442
4443 struct mlx5_ifc_query_sq_in_bits {
4444 u8 opcode[0x10];
4445 u8 reserved_at_10[0x10];
4446
4447 u8 reserved_at_20[0x10];
4448 u8 op_mod[0x10];
4449
4450 u8 reserved_at_40[0x8];
4451 u8 sqn[0x18];
4452
4453 u8 reserved_at_60[0x20];
4454 };
4455
4456 struct mlx5_ifc_query_special_contexts_out_bits {
4457 u8 status[0x8];
4458 u8 reserved_at_8[0x18];
4459
4460 u8 syndrome[0x20];
4461
4462 u8 dump_fill_mkey[0x20];
4463
4464 u8 resd_lkey[0x20];
4465
4466 u8 null_mkey[0x20];
4467
4468 u8 reserved_at_a0[0x60];
4469 };
4470
4471 struct mlx5_ifc_query_special_contexts_in_bits {
4472 u8 opcode[0x10];
4473 u8 reserved_at_10[0x10];
4474
4475 u8 reserved_at_20[0x10];
4476 u8 op_mod[0x10];
4477
4478 u8 reserved_at_40[0x40];
4479 };
4480
4481 struct mlx5_ifc_query_scheduling_element_out_bits {
4482 u8 opcode[0x10];
4483 u8 reserved_at_10[0x10];
4484
4485 u8 reserved_at_20[0x10];
4486 u8 op_mod[0x10];
4487
4488 u8 reserved_at_40[0xc0];
4489
4490 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4491
4492 u8 reserved_at_300[0x100];
4493 };
4494
4495 enum {
4496 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4497 };
4498
4499 struct mlx5_ifc_query_scheduling_element_in_bits {
4500 u8 opcode[0x10];
4501 u8 reserved_at_10[0x10];
4502
4503 u8 reserved_at_20[0x10];
4504 u8 op_mod[0x10];
4505
4506 u8 scheduling_hierarchy[0x8];
4507 u8 reserved_at_48[0x18];
4508
4509 u8 scheduling_element_id[0x20];
4510
4511 u8 reserved_at_80[0x180];
4512 };
4513
4514 struct mlx5_ifc_query_rqt_out_bits {
4515 u8 status[0x8];
4516 u8 reserved_at_8[0x18];
4517
4518 u8 syndrome[0x20];
4519
4520 u8 reserved_at_40[0xc0];
4521
4522 struct mlx5_ifc_rqtc_bits rqt_context;
4523 };
4524
4525 struct mlx5_ifc_query_rqt_in_bits {
4526 u8 opcode[0x10];
4527 u8 reserved_at_10[0x10];
4528
4529 u8 reserved_at_20[0x10];
4530 u8 op_mod[0x10];
4531
4532 u8 reserved_at_40[0x8];
4533 u8 rqtn[0x18];
4534
4535 u8 reserved_at_60[0x20];
4536 };
4537
4538 struct mlx5_ifc_query_rq_out_bits {
4539 u8 status[0x8];
4540 u8 reserved_at_8[0x18];
4541
4542 u8 syndrome[0x20];
4543
4544 u8 reserved_at_40[0xc0];
4545
4546 struct mlx5_ifc_rqc_bits rq_context;
4547 };
4548
4549 struct mlx5_ifc_query_rq_in_bits {
4550 u8 opcode[0x10];
4551 u8 reserved_at_10[0x10];
4552
4553 u8 reserved_at_20[0x10];
4554 u8 op_mod[0x10];
4555
4556 u8 reserved_at_40[0x8];
4557 u8 rqn[0x18];
4558
4559 u8 reserved_at_60[0x20];
4560 };
4561
4562 struct mlx5_ifc_query_roce_address_out_bits {
4563 u8 status[0x8];
4564 u8 reserved_at_8[0x18];
4565
4566 u8 syndrome[0x20];
4567
4568 u8 reserved_at_40[0x40];
4569
4570 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4571 };
4572
4573 struct mlx5_ifc_query_roce_address_in_bits {
4574 u8 opcode[0x10];
4575 u8 reserved_at_10[0x10];
4576
4577 u8 reserved_at_20[0x10];
4578 u8 op_mod[0x10];
4579
4580 u8 roce_address_index[0x10];
4581 u8 reserved_at_50[0xc];
4582 u8 vhca_port_num[0x4];
4583
4584 u8 reserved_at_60[0x20];
4585 };
4586
4587 struct mlx5_ifc_query_rmp_out_bits {
4588 u8 status[0x8];
4589 u8 reserved_at_8[0x18];
4590
4591 u8 syndrome[0x20];
4592
4593 u8 reserved_at_40[0xc0];
4594
4595 struct mlx5_ifc_rmpc_bits rmp_context;
4596 };
4597
4598 struct mlx5_ifc_query_rmp_in_bits {
4599 u8 opcode[0x10];
4600 u8 reserved_at_10[0x10];
4601
4602 u8 reserved_at_20[0x10];
4603 u8 op_mod[0x10];
4604
4605 u8 reserved_at_40[0x8];
4606 u8 rmpn[0x18];
4607
4608 u8 reserved_at_60[0x20];
4609 };
4610
4611 struct mlx5_ifc_query_qp_out_bits {
4612 u8 status[0x8];
4613 u8 reserved_at_8[0x18];
4614
4615 u8 syndrome[0x20];
4616
4617 u8 reserved_at_40[0x40];
4618
4619 u8 opt_param_mask[0x20];
4620
4621 u8 reserved_at_a0[0x20];
4622
4623 struct mlx5_ifc_qpc_bits qpc;
4624
4625 u8 reserved_at_800[0x80];
4626
4627 u8 pas[0][0x40];
4628 };
4629
4630 struct mlx5_ifc_query_qp_in_bits {
4631 u8 opcode[0x10];
4632 u8 reserved_at_10[0x10];
4633
4634 u8 reserved_at_20[0x10];
4635 u8 op_mod[0x10];
4636
4637 u8 reserved_at_40[0x8];
4638 u8 qpn[0x18];
4639
4640 u8 reserved_at_60[0x20];
4641 };
4642
4643 struct mlx5_ifc_query_q_counter_out_bits {
4644 u8 status[0x8];
4645 u8 reserved_at_8[0x18];
4646
4647 u8 syndrome[0x20];
4648
4649 u8 reserved_at_40[0x40];
4650
4651 u8 rx_write_requests[0x20];
4652
4653 u8 reserved_at_a0[0x20];
4654
4655 u8 rx_read_requests[0x20];
4656
4657 u8 reserved_at_e0[0x20];
4658
4659 u8 rx_atomic_requests[0x20];
4660
4661 u8 reserved_at_120[0x20];
4662
4663 u8 rx_dct_connect[0x20];
4664
4665 u8 reserved_at_160[0x20];
4666
4667 u8 out_of_buffer[0x20];
4668
4669 u8 reserved_at_1a0[0x20];
4670
4671 u8 out_of_sequence[0x20];
4672
4673 u8 reserved_at_1e0[0x20];
4674
4675 u8 duplicate_request[0x20];
4676
4677 u8 reserved_at_220[0x20];
4678
4679 u8 rnr_nak_retry_err[0x20];
4680
4681 u8 reserved_at_260[0x20];
4682
4683 u8 packet_seq_err[0x20];
4684
4685 u8 reserved_at_2a0[0x20];
4686
4687 u8 implied_nak_seq_err[0x20];
4688
4689 u8 reserved_at_2e0[0x20];
4690
4691 u8 local_ack_timeout_err[0x20];
4692
4693 u8 reserved_at_320[0xa0];
4694
4695 u8 resp_local_length_error[0x20];
4696
4697 u8 req_local_length_error[0x20];
4698
4699 u8 resp_local_qp_error[0x20];
4700
4701 u8 local_operation_error[0x20];
4702
4703 u8 resp_local_protection[0x20];
4704
4705 u8 req_local_protection[0x20];
4706
4707 u8 resp_cqe_error[0x20];
4708
4709 u8 req_cqe_error[0x20];
4710
4711 u8 req_mw_binding[0x20];
4712
4713 u8 req_bad_response[0x20];
4714
4715 u8 req_remote_invalid_request[0x20];
4716
4717 u8 resp_remote_invalid_request[0x20];
4718
4719 u8 req_remote_access_errors[0x20];
4720
4721 u8 resp_remote_access_errors[0x20];
4722
4723 u8 req_remote_operation_errors[0x20];
4724
4725 u8 req_transport_retries_exceeded[0x20];
4726
4727 u8 cq_overflow[0x20];
4728
4729 u8 resp_cqe_flush_error[0x20];
4730
4731 u8 req_cqe_flush_error[0x20];
4732
4733 u8 reserved_at_620[0x1e0];
4734 };
4735
4736 struct mlx5_ifc_query_q_counter_in_bits {
4737 u8 opcode[0x10];
4738 u8 reserved_at_10[0x10];
4739
4740 u8 reserved_at_20[0x10];
4741 u8 op_mod[0x10];
4742
4743 u8 reserved_at_40[0x80];
4744
4745 u8 clear[0x1];
4746 u8 reserved_at_c1[0x1f];
4747
4748 u8 reserved_at_e0[0x18];
4749 u8 counter_set_id[0x8];
4750 };
4751
4752 struct mlx5_ifc_query_pages_out_bits {
4753 u8 status[0x8];
4754 u8 reserved_at_8[0x18];
4755
4756 u8 syndrome[0x20];
4757
4758 u8 embedded_cpu_function[0x1];
4759 u8 reserved_at_41[0xf];
4760 u8 function_id[0x10];
4761
4762 u8 num_pages[0x20];
4763 };
4764
4765 enum {
4766 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4767 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4768 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4769 };
4770
4771 struct mlx5_ifc_query_pages_in_bits {
4772 u8 opcode[0x10];
4773 u8 reserved_at_10[0x10];
4774
4775 u8 reserved_at_20[0x10];
4776 u8 op_mod[0x10];
4777
4778 u8 embedded_cpu_function[0x1];
4779 u8 reserved_at_41[0xf];
4780 u8 function_id[0x10];
4781
4782 u8 reserved_at_60[0x20];
4783 };
4784
4785 struct mlx5_ifc_query_nic_vport_context_out_bits {
4786 u8 status[0x8];
4787 u8 reserved_at_8[0x18];
4788
4789 u8 syndrome[0x20];
4790
4791 u8 reserved_at_40[0x40];
4792
4793 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4794 };
4795
4796 struct mlx5_ifc_query_nic_vport_context_in_bits {
4797 u8 opcode[0x10];
4798 u8 reserved_at_10[0x10];
4799
4800 u8 reserved_at_20[0x10];
4801 u8 op_mod[0x10];
4802
4803 u8 other_vport[0x1];
4804 u8 reserved_at_41[0xf];
4805 u8 vport_number[0x10];
4806
4807 u8 reserved_at_60[0x5];
4808 u8 allowed_list_type[0x3];
4809 u8 reserved_at_68[0x18];
4810 };
4811
4812 struct mlx5_ifc_query_mkey_out_bits {
4813 u8 status[0x8];
4814 u8 reserved_at_8[0x18];
4815
4816 u8 syndrome[0x20];
4817
4818 u8 reserved_at_40[0x40];
4819
4820 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4821
4822 u8 reserved_at_280[0x600];
4823
4824 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4825
4826 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4827 };
4828
4829 struct mlx5_ifc_query_mkey_in_bits {
4830 u8 opcode[0x10];
4831 u8 reserved_at_10[0x10];
4832
4833 u8 reserved_at_20[0x10];
4834 u8 op_mod[0x10];
4835
4836 u8 reserved_at_40[0x8];
4837 u8 mkey_index[0x18];
4838
4839 u8 pg_access[0x1];
4840 u8 reserved_at_61[0x1f];
4841 };
4842
4843 struct mlx5_ifc_query_mad_demux_out_bits {
4844 u8 status[0x8];
4845 u8 reserved_at_8[0x18];
4846
4847 u8 syndrome[0x20];
4848
4849 u8 reserved_at_40[0x40];
4850
4851 u8 mad_dumux_parameters_block[0x20];
4852 };
4853
4854 struct mlx5_ifc_query_mad_demux_in_bits {
4855 u8 opcode[0x10];
4856 u8 reserved_at_10[0x10];
4857
4858 u8 reserved_at_20[0x10];
4859 u8 op_mod[0x10];
4860
4861 u8 reserved_at_40[0x40];
4862 };
4863
4864 struct mlx5_ifc_query_l2_table_entry_out_bits {
4865 u8 status[0x8];
4866 u8 reserved_at_8[0x18];
4867
4868 u8 syndrome[0x20];
4869
4870 u8 reserved_at_40[0xa0];
4871
4872 u8 reserved_at_e0[0x13];
4873 u8 vlan_valid[0x1];
4874 u8 vlan[0xc];
4875
4876 struct mlx5_ifc_mac_address_layout_bits mac_address;
4877
4878 u8 reserved_at_140[0xc0];
4879 };
4880
4881 struct mlx5_ifc_query_l2_table_entry_in_bits {
4882 u8 opcode[0x10];
4883 u8 reserved_at_10[0x10];
4884
4885 u8 reserved_at_20[0x10];
4886 u8 op_mod[0x10];
4887
4888 u8 reserved_at_40[0x60];
4889
4890 u8 reserved_at_a0[0x8];
4891 u8 table_index[0x18];
4892
4893 u8 reserved_at_c0[0x140];
4894 };
4895
4896 struct mlx5_ifc_query_issi_out_bits {
4897 u8 status[0x8];
4898 u8 reserved_at_8[0x18];
4899
4900 u8 syndrome[0x20];
4901
4902 u8 reserved_at_40[0x10];
4903 u8 current_issi[0x10];
4904
4905 u8 reserved_at_60[0xa0];
4906
4907 u8 reserved_at_100[76][0x8];
4908 u8 supported_issi_dw0[0x20];
4909 };
4910
4911 struct mlx5_ifc_query_issi_in_bits {
4912 u8 opcode[0x10];
4913 u8 reserved_at_10[0x10];
4914
4915 u8 reserved_at_20[0x10];
4916 u8 op_mod[0x10];
4917
4918 u8 reserved_at_40[0x40];
4919 };
4920
4921 struct mlx5_ifc_set_driver_version_out_bits {
4922 u8 status[0x8];
4923 u8 reserved_0[0x18];
4924
4925 u8 syndrome[0x20];
4926 u8 reserved_1[0x40];
4927 };
4928
4929 struct mlx5_ifc_set_driver_version_in_bits {
4930 u8 opcode[0x10];
4931 u8 reserved_0[0x10];
4932
4933 u8 reserved_1[0x10];
4934 u8 op_mod[0x10];
4935
4936 u8 reserved_2[0x40];
4937 u8 driver_version[64][0x8];
4938 };
4939
4940 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4941 u8 status[0x8];
4942 u8 reserved_at_8[0x18];
4943
4944 u8 syndrome[0x20];
4945
4946 u8 reserved_at_40[0x40];
4947
4948 struct mlx5_ifc_pkey_bits pkey[0];
4949 };
4950
4951 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4952 u8 opcode[0x10];
4953 u8 reserved_at_10[0x10];
4954
4955 u8 reserved_at_20[0x10];
4956 u8 op_mod[0x10];
4957
4958 u8 other_vport[0x1];
4959 u8 reserved_at_41[0xb];
4960 u8 port_num[0x4];
4961 u8 vport_number[0x10];
4962
4963 u8 reserved_at_60[0x10];
4964 u8 pkey_index[0x10];
4965 };
4966
4967 enum {
4968 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4969 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4970 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4971 };
4972
4973 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4974 u8 status[0x8];
4975 u8 reserved_at_8[0x18];
4976
4977 u8 syndrome[0x20];
4978
4979 u8 reserved_at_40[0x20];
4980
4981 u8 gids_num[0x10];
4982 u8 reserved_at_70[0x10];
4983
4984 struct mlx5_ifc_array128_auto_bits gid[0];
4985 };
4986
4987 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4988 u8 opcode[0x10];
4989 u8 reserved_at_10[0x10];
4990
4991 u8 reserved_at_20[0x10];
4992 u8 op_mod[0x10];
4993
4994 u8 other_vport[0x1];
4995 u8 reserved_at_41[0xb];
4996 u8 port_num[0x4];
4997 u8 vport_number[0x10];
4998
4999 u8 reserved_at_60[0x10];
5000 u8 gid_index[0x10];
5001 };
5002
5003 struct mlx5_ifc_query_hca_vport_context_out_bits {
5004 u8 status[0x8];
5005 u8 reserved_at_8[0x18];
5006
5007 u8 syndrome[0x20];
5008
5009 u8 reserved_at_40[0x40];
5010
5011 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5012 };
5013
5014 struct mlx5_ifc_query_hca_vport_context_in_bits {
5015 u8 opcode[0x10];
5016 u8 reserved_at_10[0x10];
5017
5018 u8 reserved_at_20[0x10];
5019 u8 op_mod[0x10];
5020
5021 u8 other_vport[0x1];
5022 u8 reserved_at_41[0xb];
5023 u8 port_num[0x4];
5024 u8 vport_number[0x10];
5025
5026 u8 reserved_at_60[0x20];
5027 };
5028
5029 struct mlx5_ifc_query_hca_cap_out_bits {
5030 u8 status[0x8];
5031 u8 reserved_at_8[0x18];
5032
5033 u8 syndrome[0x20];
5034
5035 u8 reserved_at_40[0x40];
5036
5037 union mlx5_ifc_hca_cap_union_bits capability;
5038 };
5039
5040 struct mlx5_ifc_query_hca_cap_in_bits {
5041 u8 opcode[0x10];
5042 u8 reserved_at_10[0x10];
5043
5044 u8 reserved_at_20[0x10];
5045 u8 op_mod[0x10];
5046
5047 u8 other_function[0x1];
5048 u8 reserved_at_41[0xf];
5049 u8 function_id[0x10];
5050
5051 u8 reserved_at_60[0x20];
5052 };
5053
5054 struct mlx5_ifc_other_hca_cap_bits {
5055 u8 roce[0x1];
5056 u8 reserved_at_1[0x27f];
5057 };
5058
5059 struct mlx5_ifc_query_other_hca_cap_out_bits {
5060 u8 status[0x8];
5061 u8 reserved_at_8[0x18];
5062
5063 u8 syndrome[0x20];
5064
5065 u8 reserved_at_40[0x40];
5066
5067 struct mlx5_ifc_other_hca_cap_bits other_capability;
5068 };
5069
5070 struct mlx5_ifc_query_other_hca_cap_in_bits {
5071 u8 opcode[0x10];
5072 u8 reserved_at_10[0x10];
5073
5074 u8 reserved_at_20[0x10];
5075 u8 op_mod[0x10];
5076
5077 u8 reserved_at_40[0x10];
5078 u8 function_id[0x10];
5079
5080 u8 reserved_at_60[0x20];
5081 };
5082
5083 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5084 u8 status[0x8];
5085 u8 reserved_at_8[0x18];
5086
5087 u8 syndrome[0x20];
5088
5089 u8 reserved_at_40[0x40];
5090 };
5091
5092 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5093 u8 opcode[0x10];
5094 u8 reserved_at_10[0x10];
5095
5096 u8 reserved_at_20[0x10];
5097 u8 op_mod[0x10];
5098
5099 u8 reserved_at_40[0x10];
5100 u8 function_id[0x10];
5101 u8 field_select[0x20];
5102
5103 struct mlx5_ifc_other_hca_cap_bits other_capability;
5104 };
5105
5106 struct mlx5_ifc_flow_table_context_bits {
5107 u8 reformat_en[0x1];
5108 u8 decap_en[0x1];
5109 u8 sw_owner[0x1];
5110 u8 termination_table[0x1];
5111 u8 table_miss_action[0x4];
5112 u8 level[0x8];
5113 u8 reserved_at_10[0x8];
5114 u8 log_size[0x8];
5115
5116 u8 reserved_at_20[0x8];
5117 u8 table_miss_id[0x18];
5118
5119 u8 reserved_at_40[0x8];
5120 u8 lag_master_next_table_id[0x18];
5121
5122 u8 reserved_at_60[0x60];
5123
5124 u8 sw_owner_icm_root_1[0x40];
5125
5126 u8 sw_owner_icm_root_0[0x40];
5127
5128 };
5129
5130 struct mlx5_ifc_query_flow_table_out_bits {
5131 u8 status[0x8];
5132 u8 reserved_at_8[0x18];
5133
5134 u8 syndrome[0x20];
5135
5136 u8 reserved_at_40[0x80];
5137
5138 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5139 };
5140
5141 struct mlx5_ifc_query_flow_table_in_bits {
5142 u8 opcode[0x10];
5143 u8 reserved_at_10[0x10];
5144
5145 u8 reserved_at_20[0x10];
5146 u8 op_mod[0x10];
5147
5148 u8 reserved_at_40[0x40];
5149
5150 u8 table_type[0x8];
5151 u8 reserved_at_88[0x18];
5152
5153 u8 reserved_at_a0[0x8];
5154 u8 table_id[0x18];
5155
5156 u8 reserved_at_c0[0x140];
5157 };
5158
5159 struct mlx5_ifc_query_fte_out_bits {
5160 u8 status[0x8];
5161 u8 reserved_at_8[0x18];
5162
5163 u8 syndrome[0x20];
5164
5165 u8 reserved_at_40[0x1c0];
5166
5167 struct mlx5_ifc_flow_context_bits flow_context;
5168 };
5169
5170 struct mlx5_ifc_query_fte_in_bits {
5171 u8 opcode[0x10];
5172 u8 reserved_at_10[0x10];
5173
5174 u8 reserved_at_20[0x10];
5175 u8 op_mod[0x10];
5176
5177 u8 reserved_at_40[0x40];
5178
5179 u8 table_type[0x8];
5180 u8 reserved_at_88[0x18];
5181
5182 u8 reserved_at_a0[0x8];
5183 u8 table_id[0x18];
5184
5185 u8 reserved_at_c0[0x40];
5186
5187 u8 flow_index[0x20];
5188
5189 u8 reserved_at_120[0xe0];
5190 };
5191
5192 enum {
5193 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5194 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5195 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5196 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5197 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5198 };
5199
5200 struct mlx5_ifc_query_flow_group_out_bits {
5201 u8 status[0x8];
5202 u8 reserved_at_8[0x18];
5203
5204 u8 syndrome[0x20];
5205
5206 u8 reserved_at_40[0xa0];
5207
5208 u8 start_flow_index[0x20];
5209
5210 u8 reserved_at_100[0x20];
5211
5212 u8 end_flow_index[0x20];
5213
5214 u8 reserved_at_140[0xa0];
5215
5216 u8 reserved_at_1e0[0x18];
5217 u8 match_criteria_enable[0x8];
5218
5219 struct mlx5_ifc_fte_match_param_bits match_criteria;
5220
5221 u8 reserved_at_1200[0xe00];
5222 };
5223
5224 struct mlx5_ifc_query_flow_group_in_bits {
5225 u8 opcode[0x10];
5226 u8 reserved_at_10[0x10];
5227
5228 u8 reserved_at_20[0x10];
5229 u8 op_mod[0x10];
5230
5231 u8 reserved_at_40[0x40];
5232
5233 u8 table_type[0x8];
5234 u8 reserved_at_88[0x18];
5235
5236 u8 reserved_at_a0[0x8];
5237 u8 table_id[0x18];
5238
5239 u8 group_id[0x20];
5240
5241 u8 reserved_at_e0[0x120];
5242 };
5243
5244 struct mlx5_ifc_query_flow_counter_out_bits {
5245 u8 status[0x8];
5246 u8 reserved_at_8[0x18];
5247
5248 u8 syndrome[0x20];
5249
5250 u8 reserved_at_40[0x40];
5251
5252 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5253 };
5254
5255 struct mlx5_ifc_query_flow_counter_in_bits {
5256 u8 opcode[0x10];
5257 u8 reserved_at_10[0x10];
5258
5259 u8 reserved_at_20[0x10];
5260 u8 op_mod[0x10];
5261
5262 u8 reserved_at_40[0x80];
5263
5264 u8 clear[0x1];
5265 u8 reserved_at_c1[0xf];
5266 u8 num_of_counters[0x10];
5267
5268 u8 flow_counter_id[0x20];
5269 };
5270
5271 struct mlx5_ifc_query_esw_vport_context_out_bits {
5272 u8 status[0x8];
5273 u8 reserved_at_8[0x18];
5274
5275 u8 syndrome[0x20];
5276
5277 u8 reserved_at_40[0x40];
5278
5279 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5280 };
5281
5282 struct mlx5_ifc_query_esw_vport_context_in_bits {
5283 u8 opcode[0x10];
5284 u8 reserved_at_10[0x10];
5285
5286 u8 reserved_at_20[0x10];
5287 u8 op_mod[0x10];
5288
5289 u8 other_vport[0x1];
5290 u8 reserved_at_41[0xf];
5291 u8 vport_number[0x10];
5292
5293 u8 reserved_at_60[0x20];
5294 };
5295
5296 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5297 u8 status[0x8];
5298 u8 reserved_at_8[0x18];
5299
5300 u8 syndrome[0x20];
5301
5302 u8 reserved_at_40[0x40];
5303 };
5304
5305 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5306 u8 reserved_at_0[0x1b];
5307 u8 fdb_to_vport_reg_c_id[0x1];
5308 u8 vport_cvlan_insert[0x1];
5309 u8 vport_svlan_insert[0x1];
5310 u8 vport_cvlan_strip[0x1];
5311 u8 vport_svlan_strip[0x1];
5312 };
5313
5314 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5315 u8 opcode[0x10];
5316 u8 reserved_at_10[0x10];
5317
5318 u8 reserved_at_20[0x10];
5319 u8 op_mod[0x10];
5320
5321 u8 other_vport[0x1];
5322 u8 reserved_at_41[0xf];
5323 u8 vport_number[0x10];
5324
5325 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5326
5327 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5328 };
5329
5330 struct mlx5_ifc_query_eq_out_bits {
5331 u8 status[0x8];
5332 u8 reserved_at_8[0x18];
5333
5334 u8 syndrome[0x20];
5335
5336 u8 reserved_at_40[0x40];
5337
5338 struct mlx5_ifc_eqc_bits eq_context_entry;
5339
5340 u8 reserved_at_280[0x40];
5341
5342 u8 event_bitmask[0x40];
5343
5344 u8 reserved_at_300[0x580];
5345
5346 u8 pas[0][0x40];
5347 };
5348
5349 struct mlx5_ifc_query_eq_in_bits {
5350 u8 opcode[0x10];
5351 u8 reserved_at_10[0x10];
5352
5353 u8 reserved_at_20[0x10];
5354 u8 op_mod[0x10];
5355
5356 u8 reserved_at_40[0x18];
5357 u8 eq_number[0x8];
5358
5359 u8 reserved_at_60[0x20];
5360 };
5361
5362 struct mlx5_ifc_packet_reformat_context_in_bits {
5363 u8 reserved_at_0[0x5];
5364 u8 reformat_type[0x3];
5365 u8 reserved_at_8[0xe];
5366 u8 reformat_data_size[0xa];
5367
5368 u8 reserved_at_20[0x10];
5369 u8 reformat_data[2][0x8];
5370
5371 u8 more_reformat_data[0][0x8];
5372 };
5373
5374 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5375 u8 status[0x8];
5376 u8 reserved_at_8[0x18];
5377
5378 u8 syndrome[0x20];
5379
5380 u8 reserved_at_40[0xa0];
5381
5382 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5383 };
5384
5385 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5386 u8 opcode[0x10];
5387 u8 reserved_at_10[0x10];
5388
5389 u8 reserved_at_20[0x10];
5390 u8 op_mod[0x10];
5391
5392 u8 packet_reformat_id[0x20];
5393
5394 u8 reserved_at_60[0xa0];
5395 };
5396
5397 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5398 u8 status[0x8];
5399 u8 reserved_at_8[0x18];
5400
5401 u8 syndrome[0x20];
5402
5403 u8 packet_reformat_id[0x20];
5404
5405 u8 reserved_at_60[0x20];
5406 };
5407
5408 enum mlx5_reformat_ctx_type {
5409 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5410 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5411 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5412 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5413 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5414 };
5415
5416 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5417 u8 opcode[0x10];
5418 u8 reserved_at_10[0x10];
5419
5420 u8 reserved_at_20[0x10];
5421 u8 op_mod[0x10];
5422
5423 u8 reserved_at_40[0xa0];
5424
5425 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5426 };
5427
5428 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5429 u8 status[0x8];
5430 u8 reserved_at_8[0x18];
5431
5432 u8 syndrome[0x20];
5433
5434 u8 reserved_at_40[0x40];
5435 };
5436
5437 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5438 u8 opcode[0x10];
5439 u8 reserved_at_10[0x10];
5440
5441 u8 reserved_20[0x10];
5442 u8 op_mod[0x10];
5443
5444 u8 packet_reformat_id[0x20];
5445
5446 u8 reserved_60[0x20];
5447 };
5448
5449 struct mlx5_ifc_set_action_in_bits {
5450 u8 action_type[0x4];
5451 u8 field[0xc];
5452 u8 reserved_at_10[0x3];
5453 u8 offset[0x5];
5454 u8 reserved_at_18[0x3];
5455 u8 length[0x5];
5456
5457 u8 data[0x20];
5458 };
5459
5460 struct mlx5_ifc_add_action_in_bits {
5461 u8 action_type[0x4];
5462 u8 field[0xc];
5463 u8 reserved_at_10[0x10];
5464
5465 u8 data[0x20];
5466 };
5467
5468 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5469 struct mlx5_ifc_set_action_in_bits set_action_in;
5470 struct mlx5_ifc_add_action_in_bits add_action_in;
5471 u8 reserved_at_0[0x40];
5472 };
5473
5474 enum {
5475 MLX5_ACTION_TYPE_SET = 0x1,
5476 MLX5_ACTION_TYPE_ADD = 0x2,
5477 };
5478
5479 enum {
5480 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5481 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5482 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5483 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5484 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5485 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5486 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5487 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5488 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5489 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5490 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5491 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5492 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5493 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5494 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5495 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5496 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5497 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5498 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5499 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5500 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5501 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5502 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5503 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5504 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5505 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5506 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5507 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5508 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5509 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5510 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5511 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5512 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5513 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5514 };
5515
5516 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5517 u8 status[0x8];
5518 u8 reserved_at_8[0x18];
5519
5520 u8 syndrome[0x20];
5521
5522 u8 modify_header_id[0x20];
5523
5524 u8 reserved_at_60[0x20];
5525 };
5526
5527 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5528 u8 opcode[0x10];
5529 u8 reserved_at_10[0x10];
5530
5531 u8 reserved_at_20[0x10];
5532 u8 op_mod[0x10];
5533
5534 u8 reserved_at_40[0x20];
5535
5536 u8 table_type[0x8];
5537 u8 reserved_at_68[0x10];
5538 u8 num_of_actions[0x8];
5539
5540 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5541 };
5542
5543 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5544 u8 status[0x8];
5545 u8 reserved_at_8[0x18];
5546
5547 u8 syndrome[0x20];
5548
5549 u8 reserved_at_40[0x40];
5550 };
5551
5552 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5553 u8 opcode[0x10];
5554 u8 reserved_at_10[0x10];
5555
5556 u8 reserved_at_20[0x10];
5557 u8 op_mod[0x10];
5558
5559 u8 modify_header_id[0x20];
5560
5561 u8 reserved_at_60[0x20];
5562 };
5563
5564 struct mlx5_ifc_query_dct_out_bits {
5565 u8 status[0x8];
5566 u8 reserved_at_8[0x18];
5567
5568 u8 syndrome[0x20];
5569
5570 u8 reserved_at_40[0x40];
5571
5572 struct mlx5_ifc_dctc_bits dct_context_entry;
5573
5574 u8 reserved_at_280[0x180];
5575 };
5576
5577 struct mlx5_ifc_query_dct_in_bits {
5578 u8 opcode[0x10];
5579 u8 reserved_at_10[0x10];
5580
5581 u8 reserved_at_20[0x10];
5582 u8 op_mod[0x10];
5583
5584 u8 reserved_at_40[0x8];
5585 u8 dctn[0x18];
5586
5587 u8 reserved_at_60[0x20];
5588 };
5589
5590 struct mlx5_ifc_query_cq_out_bits {
5591 u8 status[0x8];
5592 u8 reserved_at_8[0x18];
5593
5594 u8 syndrome[0x20];
5595
5596 u8 reserved_at_40[0x40];
5597
5598 struct mlx5_ifc_cqc_bits cq_context;
5599
5600 u8 reserved_at_280[0x600];
5601
5602 u8 pas[0][0x40];
5603 };
5604
5605 struct mlx5_ifc_query_cq_in_bits {
5606 u8 opcode[0x10];
5607 u8 reserved_at_10[0x10];
5608
5609 u8 reserved_at_20[0x10];
5610 u8 op_mod[0x10];
5611
5612 u8 reserved_at_40[0x8];
5613 u8 cqn[0x18];
5614
5615 u8 reserved_at_60[0x20];
5616 };
5617
5618 struct mlx5_ifc_query_cong_status_out_bits {
5619 u8 status[0x8];
5620 u8 reserved_at_8[0x18];
5621
5622 u8 syndrome[0x20];
5623
5624 u8 reserved_at_40[0x20];
5625
5626 u8 enable[0x1];
5627 u8 tag_enable[0x1];
5628 u8 reserved_at_62[0x1e];
5629 };
5630
5631 struct mlx5_ifc_query_cong_status_in_bits {
5632 u8 opcode[0x10];
5633 u8 reserved_at_10[0x10];
5634
5635 u8 reserved_at_20[0x10];
5636 u8 op_mod[0x10];
5637
5638 u8 reserved_at_40[0x18];
5639 u8 priority[0x4];
5640 u8 cong_protocol[0x4];
5641
5642 u8 reserved_at_60[0x20];
5643 };
5644
5645 struct mlx5_ifc_query_cong_statistics_out_bits {
5646 u8 status[0x8];
5647 u8 reserved_at_8[0x18];
5648
5649 u8 syndrome[0x20];
5650
5651 u8 reserved_at_40[0x40];
5652
5653 u8 rp_cur_flows[0x20];
5654
5655 u8 sum_flows[0x20];
5656
5657 u8 rp_cnp_ignored_high[0x20];
5658
5659 u8 rp_cnp_ignored_low[0x20];
5660
5661 u8 rp_cnp_handled_high[0x20];
5662
5663 u8 rp_cnp_handled_low[0x20];
5664
5665 u8 reserved_at_140[0x100];
5666
5667 u8 time_stamp_high[0x20];
5668
5669 u8 time_stamp_low[0x20];
5670
5671 u8 accumulators_period[0x20];
5672
5673 u8 np_ecn_marked_roce_packets_high[0x20];
5674
5675 u8 np_ecn_marked_roce_packets_low[0x20];
5676
5677 u8 np_cnp_sent_high[0x20];
5678
5679 u8 np_cnp_sent_low[0x20];
5680
5681 u8 reserved_at_320[0x560];
5682 };
5683
5684 struct mlx5_ifc_query_cong_statistics_in_bits {
5685 u8 opcode[0x10];
5686 u8 reserved_at_10[0x10];
5687
5688 u8 reserved_at_20[0x10];
5689 u8 op_mod[0x10];
5690
5691 u8 clear[0x1];
5692 u8 reserved_at_41[0x1f];
5693
5694 u8 reserved_at_60[0x20];
5695 };
5696
5697 struct mlx5_ifc_query_cong_params_out_bits {
5698 u8 status[0x8];
5699 u8 reserved_at_8[0x18];
5700
5701 u8 syndrome[0x20];
5702
5703 u8 reserved_at_40[0x40];
5704
5705 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5706 };
5707
5708 struct mlx5_ifc_query_cong_params_in_bits {
5709 u8 opcode[0x10];
5710 u8 reserved_at_10[0x10];
5711
5712 u8 reserved_at_20[0x10];
5713 u8 op_mod[0x10];
5714
5715 u8 reserved_at_40[0x1c];
5716 u8 cong_protocol[0x4];
5717
5718 u8 reserved_at_60[0x20];
5719 };
5720
5721 struct mlx5_ifc_query_adapter_out_bits {
5722 u8 status[0x8];
5723 u8 reserved_at_8[0x18];
5724
5725 u8 syndrome[0x20];
5726
5727 u8 reserved_at_40[0x40];
5728
5729 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5730 };
5731
5732 struct mlx5_ifc_query_adapter_in_bits {
5733 u8 opcode[0x10];
5734 u8 reserved_at_10[0x10];
5735
5736 u8 reserved_at_20[0x10];
5737 u8 op_mod[0x10];
5738
5739 u8 reserved_at_40[0x40];
5740 };
5741
5742 struct mlx5_ifc_qp_2rst_out_bits {
5743 u8 status[0x8];
5744 u8 reserved_at_8[0x18];
5745
5746 u8 syndrome[0x20];
5747
5748 u8 reserved_at_40[0x40];
5749 };
5750
5751 struct mlx5_ifc_qp_2rst_in_bits {
5752 u8 opcode[0x10];
5753 u8 uid[0x10];
5754
5755 u8 reserved_at_20[0x10];
5756 u8 op_mod[0x10];
5757
5758 u8 reserved_at_40[0x8];
5759 u8 qpn[0x18];
5760
5761 u8 reserved_at_60[0x20];
5762 };
5763
5764 struct mlx5_ifc_qp_2err_out_bits {
5765 u8 status[0x8];
5766 u8 reserved_at_8[0x18];
5767
5768 u8 syndrome[0x20];
5769
5770 u8 reserved_at_40[0x40];
5771 };
5772
5773 struct mlx5_ifc_qp_2err_in_bits {
5774 u8 opcode[0x10];
5775 u8 uid[0x10];
5776
5777 u8 reserved_at_20[0x10];
5778 u8 op_mod[0x10];
5779
5780 u8 reserved_at_40[0x8];
5781 u8 qpn[0x18];
5782
5783 u8 reserved_at_60[0x20];
5784 };
5785
5786 struct mlx5_ifc_page_fault_resume_out_bits {
5787 u8 status[0x8];
5788 u8 reserved_at_8[0x18];
5789
5790 u8 syndrome[0x20];
5791
5792 u8 reserved_at_40[0x40];
5793 };
5794
5795 struct mlx5_ifc_page_fault_resume_in_bits {
5796 u8 opcode[0x10];
5797 u8 reserved_at_10[0x10];
5798
5799 u8 reserved_at_20[0x10];
5800 u8 op_mod[0x10];
5801
5802 u8 error[0x1];
5803 u8 reserved_at_41[0x4];
5804 u8 page_fault_type[0x3];
5805 u8 wq_number[0x18];
5806
5807 u8 reserved_at_60[0x8];
5808 u8 token[0x18];
5809 };
5810
5811 struct mlx5_ifc_nop_out_bits {
5812 u8 status[0x8];
5813 u8 reserved_at_8[0x18];
5814
5815 u8 syndrome[0x20];
5816
5817 u8 reserved_at_40[0x40];
5818 };
5819
5820 struct mlx5_ifc_nop_in_bits {
5821 u8 opcode[0x10];
5822 u8 reserved_at_10[0x10];
5823
5824 u8 reserved_at_20[0x10];
5825 u8 op_mod[0x10];
5826
5827 u8 reserved_at_40[0x40];
5828 };
5829
5830 struct mlx5_ifc_modify_vport_state_out_bits {
5831 u8 status[0x8];
5832 u8 reserved_at_8[0x18];
5833
5834 u8 syndrome[0x20];
5835
5836 u8 reserved_at_40[0x40];
5837 };
5838
5839 struct mlx5_ifc_modify_vport_state_in_bits {
5840 u8 opcode[0x10];
5841 u8 reserved_at_10[0x10];
5842
5843 u8 reserved_at_20[0x10];
5844 u8 op_mod[0x10];
5845
5846 u8 other_vport[0x1];
5847 u8 reserved_at_41[0xf];
5848 u8 vport_number[0x10];
5849
5850 u8 reserved_at_60[0x18];
5851 u8 admin_state[0x4];
5852 u8 reserved_at_7c[0x4];
5853 };
5854
5855 struct mlx5_ifc_modify_tis_out_bits {
5856 u8 status[0x8];
5857 u8 reserved_at_8[0x18];
5858
5859 u8 syndrome[0x20];
5860
5861 u8 reserved_at_40[0x40];
5862 };
5863
5864 struct mlx5_ifc_modify_tis_bitmask_bits {
5865 u8 reserved_at_0[0x20];
5866
5867 u8 reserved_at_20[0x1d];
5868 u8 lag_tx_port_affinity[0x1];
5869 u8 strict_lag_tx_port_affinity[0x1];
5870 u8 prio[0x1];
5871 };
5872
5873 struct mlx5_ifc_modify_tis_in_bits {
5874 u8 opcode[0x10];
5875 u8 uid[0x10];
5876
5877 u8 reserved_at_20[0x10];
5878 u8 op_mod[0x10];
5879
5880 u8 reserved_at_40[0x8];
5881 u8 tisn[0x18];
5882
5883 u8 reserved_at_60[0x20];
5884
5885 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5886
5887 u8 reserved_at_c0[0x40];
5888
5889 struct mlx5_ifc_tisc_bits ctx;
5890 };
5891
5892 struct mlx5_ifc_modify_tir_bitmask_bits {
5893 u8 reserved_at_0[0x20];
5894
5895 u8 reserved_at_20[0x1b];
5896 u8 self_lb_en[0x1];
5897 u8 reserved_at_3c[0x1];
5898 u8 hash[0x1];
5899 u8 reserved_at_3e[0x1];
5900 u8 lro[0x1];
5901 };
5902
5903 struct mlx5_ifc_modify_tir_out_bits {
5904 u8 status[0x8];
5905 u8 reserved_at_8[0x18];
5906
5907 u8 syndrome[0x20];
5908
5909 u8 reserved_at_40[0x40];
5910 };
5911
5912 struct mlx5_ifc_modify_tir_in_bits {
5913 u8 opcode[0x10];
5914 u8 uid[0x10];
5915
5916 u8 reserved_at_20[0x10];
5917 u8 op_mod[0x10];
5918
5919 u8 reserved_at_40[0x8];
5920 u8 tirn[0x18];
5921
5922 u8 reserved_at_60[0x20];
5923
5924 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5925
5926 u8 reserved_at_c0[0x40];
5927
5928 struct mlx5_ifc_tirc_bits ctx;
5929 };
5930
5931 struct mlx5_ifc_modify_sq_out_bits {
5932 u8 status[0x8];
5933 u8 reserved_at_8[0x18];
5934
5935 u8 syndrome[0x20];
5936
5937 u8 reserved_at_40[0x40];
5938 };
5939
5940 struct mlx5_ifc_modify_sq_in_bits {
5941 u8 opcode[0x10];
5942 u8 uid[0x10];
5943
5944 u8 reserved_at_20[0x10];
5945 u8 op_mod[0x10];
5946
5947 u8 sq_state[0x4];
5948 u8 reserved_at_44[0x4];
5949 u8 sqn[0x18];
5950
5951 u8 reserved_at_60[0x20];
5952
5953 u8 modify_bitmask[0x40];
5954
5955 u8 reserved_at_c0[0x40];
5956
5957 struct mlx5_ifc_sqc_bits ctx;
5958 };
5959
5960 struct mlx5_ifc_modify_scheduling_element_out_bits {
5961 u8 status[0x8];
5962 u8 reserved_at_8[0x18];
5963
5964 u8 syndrome[0x20];
5965
5966 u8 reserved_at_40[0x1c0];
5967 };
5968
5969 enum {
5970 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5971 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5972 };
5973
5974 struct mlx5_ifc_modify_scheduling_element_in_bits {
5975 u8 opcode[0x10];
5976 u8 reserved_at_10[0x10];
5977
5978 u8 reserved_at_20[0x10];
5979 u8 op_mod[0x10];
5980
5981 u8 scheduling_hierarchy[0x8];
5982 u8 reserved_at_48[0x18];
5983
5984 u8 scheduling_element_id[0x20];
5985
5986 u8 reserved_at_80[0x20];
5987
5988 u8 modify_bitmask[0x20];
5989
5990 u8 reserved_at_c0[0x40];
5991
5992 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5993
5994 u8 reserved_at_300[0x100];
5995 };
5996
5997 struct mlx5_ifc_modify_rqt_out_bits {
5998 u8 status[0x8];
5999 u8 reserved_at_8[0x18];
6000
6001 u8 syndrome[0x20];
6002
6003 u8 reserved_at_40[0x40];
6004 };
6005
6006 struct mlx5_ifc_rqt_bitmask_bits {
6007 u8 reserved_at_0[0x20];
6008
6009 u8 reserved_at_20[0x1f];
6010 u8 rqn_list[0x1];
6011 };
6012
6013 struct mlx5_ifc_modify_rqt_in_bits {
6014 u8 opcode[0x10];
6015 u8 uid[0x10];
6016
6017 u8 reserved_at_20[0x10];
6018 u8 op_mod[0x10];
6019
6020 u8 reserved_at_40[0x8];
6021 u8 rqtn[0x18];
6022
6023 u8 reserved_at_60[0x20];
6024
6025 struct mlx5_ifc_rqt_bitmask_bits bitmask;
6026
6027 u8 reserved_at_c0[0x40];
6028
6029 struct mlx5_ifc_rqtc_bits ctx;
6030 };
6031
6032 struct mlx5_ifc_modify_rq_out_bits {
6033 u8 status[0x8];
6034 u8 reserved_at_8[0x18];
6035
6036 u8 syndrome[0x20];
6037
6038 u8 reserved_at_40[0x40];
6039 };
6040
6041 enum {
6042 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6043 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6044 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6045 };
6046
6047 struct mlx5_ifc_modify_rq_in_bits {
6048 u8 opcode[0x10];
6049 u8 uid[0x10];
6050
6051 u8 reserved_at_20[0x10];
6052 u8 op_mod[0x10];
6053
6054 u8 rq_state[0x4];
6055 u8 reserved_at_44[0x4];
6056 u8 rqn[0x18];
6057
6058 u8 reserved_at_60[0x20];
6059
6060 u8 modify_bitmask[0x40];
6061
6062 u8 reserved_at_c0[0x40];
6063
6064 struct mlx5_ifc_rqc_bits ctx;
6065 };
6066
6067 struct mlx5_ifc_modify_rmp_out_bits {
6068 u8 status[0x8];
6069 u8 reserved_at_8[0x18];
6070
6071 u8 syndrome[0x20];
6072
6073 u8 reserved_at_40[0x40];
6074 };
6075
6076 struct mlx5_ifc_rmp_bitmask_bits {
6077 u8 reserved_at_0[0x20];
6078
6079 u8 reserved_at_20[0x1f];
6080 u8 lwm[0x1];
6081 };
6082
6083 struct mlx5_ifc_modify_rmp_in_bits {
6084 u8 opcode[0x10];
6085 u8 uid[0x10];
6086
6087 u8 reserved_at_20[0x10];
6088 u8 op_mod[0x10];
6089
6090 u8 rmp_state[0x4];
6091 u8 reserved_at_44[0x4];
6092 u8 rmpn[0x18];
6093
6094 u8 reserved_at_60[0x20];
6095
6096 struct mlx5_ifc_rmp_bitmask_bits bitmask;
6097
6098 u8 reserved_at_c0[0x40];
6099
6100 struct mlx5_ifc_rmpc_bits ctx;
6101 };
6102
6103 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6104 u8 status[0x8];
6105 u8 reserved_at_8[0x18];
6106
6107 u8 syndrome[0x20];
6108
6109 u8 reserved_at_40[0x40];
6110 };
6111
6112 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6113 u8 reserved_at_0[0x12];
6114 u8 affiliation[0x1];
6115 u8 reserved_at_13[0x1];
6116 u8 disable_uc_local_lb[0x1];
6117 u8 disable_mc_local_lb[0x1];
6118 u8 node_guid[0x1];
6119 u8 port_guid[0x1];
6120 u8 min_inline[0x1];
6121 u8 mtu[0x1];
6122 u8 change_event[0x1];
6123 u8 promisc[0x1];
6124 u8 permanent_address[0x1];
6125 u8 addresses_list[0x1];
6126 u8 roce_en[0x1];
6127 u8 reserved_at_1f[0x1];
6128 };
6129
6130 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6131 u8 opcode[0x10];
6132 u8 reserved_at_10[0x10];
6133
6134 u8 reserved_at_20[0x10];
6135 u8 op_mod[0x10];
6136
6137 u8 other_vport[0x1];
6138 u8 reserved_at_41[0xf];
6139 u8 vport_number[0x10];
6140
6141 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6142
6143 u8 reserved_at_80[0x780];
6144
6145 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6146 };
6147
6148 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6149 u8 status[0x8];
6150 u8 reserved_at_8[0x18];
6151
6152 u8 syndrome[0x20];
6153
6154 u8 reserved_at_40[0x40];
6155 };
6156
6157 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6158 u8 opcode[0x10];
6159 u8 reserved_at_10[0x10];
6160
6161 u8 reserved_at_20[0x10];
6162 u8 op_mod[0x10];
6163
6164 u8 other_vport[0x1];
6165 u8 reserved_at_41[0xb];
6166 u8 port_num[0x4];
6167 u8 vport_number[0x10];
6168
6169 u8 reserved_at_60[0x20];
6170
6171 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6172 };
6173
6174 struct mlx5_ifc_modify_cq_out_bits {
6175 u8 status[0x8];
6176 u8 reserved_at_8[0x18];
6177
6178 u8 syndrome[0x20];
6179
6180 u8 reserved_at_40[0x40];
6181 };
6182
6183 enum {
6184 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6185 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6186 };
6187
6188 struct mlx5_ifc_modify_cq_in_bits {
6189 u8 opcode[0x10];
6190 u8 uid[0x10];
6191
6192 u8 reserved_at_20[0x10];
6193 u8 op_mod[0x10];
6194
6195 u8 reserved_at_40[0x8];
6196 u8 cqn[0x18];
6197
6198 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6199
6200 struct mlx5_ifc_cqc_bits cq_context;
6201
6202 u8 reserved_at_280[0x60];
6203
6204 u8 cq_umem_valid[0x1];
6205 u8 reserved_at_2e1[0x1f];
6206
6207 u8 reserved_at_300[0x580];
6208
6209 u8 pas[0][0x40];
6210 };
6211
6212 struct mlx5_ifc_modify_cong_status_out_bits {
6213 u8 status[0x8];
6214 u8 reserved_at_8[0x18];
6215
6216 u8 syndrome[0x20];
6217
6218 u8 reserved_at_40[0x40];
6219 };
6220
6221 struct mlx5_ifc_modify_cong_status_in_bits {
6222 u8 opcode[0x10];
6223 u8 reserved_at_10[0x10];
6224
6225 u8 reserved_at_20[0x10];
6226 u8 op_mod[0x10];
6227
6228 u8 reserved_at_40[0x18];
6229 u8 priority[0x4];
6230 u8 cong_protocol[0x4];
6231
6232 u8 enable[0x1];
6233 u8 tag_enable[0x1];
6234 u8 reserved_at_62[0x1e];
6235 };
6236
6237 struct mlx5_ifc_modify_cong_params_out_bits {
6238 u8 status[0x8];
6239 u8 reserved_at_8[0x18];
6240
6241 u8 syndrome[0x20];
6242
6243 u8 reserved_at_40[0x40];
6244 };
6245
6246 struct mlx5_ifc_modify_cong_params_in_bits {
6247 u8 opcode[0x10];
6248 u8 reserved_at_10[0x10];
6249
6250 u8 reserved_at_20[0x10];
6251 u8 op_mod[0x10];
6252
6253 u8 reserved_at_40[0x1c];
6254 u8 cong_protocol[0x4];
6255
6256 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6257
6258 u8 reserved_at_80[0x80];
6259
6260 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6261 };
6262
6263 struct mlx5_ifc_manage_pages_out_bits {
6264 u8 status[0x8];
6265 u8 reserved_at_8[0x18];
6266
6267 u8 syndrome[0x20];
6268
6269 u8 output_num_entries[0x20];
6270
6271 u8 reserved_at_60[0x20];
6272
6273 u8 pas[0][0x40];
6274 };
6275
6276 enum {
6277 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6278 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6279 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6280 };
6281
6282 struct mlx5_ifc_manage_pages_in_bits {
6283 u8 opcode[0x10];
6284 u8 reserved_at_10[0x10];
6285
6286 u8 reserved_at_20[0x10];
6287 u8 op_mod[0x10];
6288
6289 u8 embedded_cpu_function[0x1];
6290 u8 reserved_at_41[0xf];
6291 u8 function_id[0x10];
6292
6293 u8 input_num_entries[0x20];
6294
6295 u8 pas[0][0x40];
6296 };
6297
6298 struct mlx5_ifc_mad_ifc_out_bits {
6299 u8 status[0x8];
6300 u8 reserved_at_8[0x18];
6301
6302 u8 syndrome[0x20];
6303
6304 u8 reserved_at_40[0x40];
6305
6306 u8 response_mad_packet[256][0x8];
6307 };
6308
6309 struct mlx5_ifc_mad_ifc_in_bits {
6310 u8 opcode[0x10];
6311 u8 reserved_at_10[0x10];
6312
6313 u8 reserved_at_20[0x10];
6314 u8 op_mod[0x10];
6315
6316 u8 remote_lid[0x10];
6317 u8 reserved_at_50[0x8];
6318 u8 port[0x8];
6319
6320 u8 reserved_at_60[0x20];
6321
6322 u8 mad[256][0x8];
6323 };
6324
6325 struct mlx5_ifc_init_hca_out_bits {
6326 u8 status[0x8];
6327 u8 reserved_at_8[0x18];
6328
6329 u8 syndrome[0x20];
6330
6331 u8 reserved_at_40[0x40];
6332 };
6333
6334 struct mlx5_ifc_init_hca_in_bits {
6335 u8 opcode[0x10];
6336 u8 reserved_at_10[0x10];
6337
6338 u8 reserved_at_20[0x10];
6339 u8 op_mod[0x10];
6340
6341 u8 reserved_at_40[0x40];
6342 u8 sw_owner_id[4][0x20];
6343 };
6344
6345 struct mlx5_ifc_init2rtr_qp_out_bits {
6346 u8 status[0x8];
6347 u8 reserved_at_8[0x18];
6348
6349 u8 syndrome[0x20];
6350
6351 u8 reserved_at_40[0x40];
6352 };
6353
6354 struct mlx5_ifc_init2rtr_qp_in_bits {
6355 u8 opcode[0x10];
6356 u8 uid[0x10];
6357
6358 u8 reserved_at_20[0x10];
6359 u8 op_mod[0x10];
6360
6361 u8 reserved_at_40[0x8];
6362 u8 qpn[0x18];
6363
6364 u8 reserved_at_60[0x20];
6365
6366 u8 opt_param_mask[0x20];
6367
6368 u8 reserved_at_a0[0x20];
6369
6370 struct mlx5_ifc_qpc_bits qpc;
6371
6372 u8 reserved_at_800[0x80];
6373 };
6374
6375 struct mlx5_ifc_init2init_qp_out_bits {
6376 u8 status[0x8];
6377 u8 reserved_at_8[0x18];
6378
6379 u8 syndrome[0x20];
6380
6381 u8 reserved_at_40[0x40];
6382 };
6383
6384 struct mlx5_ifc_init2init_qp_in_bits {
6385 u8 opcode[0x10];
6386 u8 uid[0x10];
6387
6388 u8 reserved_at_20[0x10];
6389 u8 op_mod[0x10];
6390
6391 u8 reserved_at_40[0x8];
6392 u8 qpn[0x18];
6393
6394 u8 reserved_at_60[0x20];
6395
6396 u8 opt_param_mask[0x20];
6397
6398 u8 reserved_at_a0[0x20];
6399
6400 struct mlx5_ifc_qpc_bits qpc;
6401
6402 u8 reserved_at_800[0x80];
6403 };
6404
6405 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6406 u8 status[0x8];
6407 u8 reserved_at_8[0x18];
6408
6409 u8 syndrome[0x20];
6410
6411 u8 reserved_at_40[0x40];
6412
6413 u8 packet_headers_log[128][0x8];
6414
6415 u8 packet_syndrome[64][0x8];
6416 };
6417
6418 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6419 u8 opcode[0x10];
6420 u8 reserved_at_10[0x10];
6421
6422 u8 reserved_at_20[0x10];
6423 u8 op_mod[0x10];
6424
6425 u8 reserved_at_40[0x40];
6426 };
6427
6428 struct mlx5_ifc_gen_eqe_in_bits {
6429 u8 opcode[0x10];
6430 u8 reserved_at_10[0x10];
6431
6432 u8 reserved_at_20[0x10];
6433 u8 op_mod[0x10];
6434
6435 u8 reserved_at_40[0x18];
6436 u8 eq_number[0x8];
6437
6438 u8 reserved_at_60[0x20];
6439
6440 u8 eqe[64][0x8];
6441 };
6442
6443 struct mlx5_ifc_gen_eq_out_bits {
6444 u8 status[0x8];
6445 u8 reserved_at_8[0x18];
6446
6447 u8 syndrome[0x20];
6448
6449 u8 reserved_at_40[0x40];
6450 };
6451
6452 struct mlx5_ifc_enable_hca_out_bits {
6453 u8 status[0x8];
6454 u8 reserved_at_8[0x18];
6455
6456 u8 syndrome[0x20];
6457
6458 u8 reserved_at_40[0x20];
6459 };
6460
6461 struct mlx5_ifc_enable_hca_in_bits {
6462 u8 opcode[0x10];
6463 u8 reserved_at_10[0x10];
6464
6465 u8 reserved_at_20[0x10];
6466 u8 op_mod[0x10];
6467
6468 u8 embedded_cpu_function[0x1];
6469 u8 reserved_at_41[0xf];
6470 u8 function_id[0x10];
6471
6472 u8 reserved_at_60[0x20];
6473 };
6474
6475 struct mlx5_ifc_drain_dct_out_bits {
6476 u8 status[0x8];
6477 u8 reserved_at_8[0x18];
6478
6479 u8 syndrome[0x20];
6480
6481 u8 reserved_at_40[0x40];
6482 };
6483
6484 struct mlx5_ifc_drain_dct_in_bits {
6485 u8 opcode[0x10];
6486 u8 uid[0x10];
6487
6488 u8 reserved_at_20[0x10];
6489 u8 op_mod[0x10];
6490
6491 u8 reserved_at_40[0x8];
6492 u8 dctn[0x18];
6493
6494 u8 reserved_at_60[0x20];
6495 };
6496
6497 struct mlx5_ifc_disable_hca_out_bits {
6498 u8 status[0x8];
6499 u8 reserved_at_8[0x18];
6500
6501 u8 syndrome[0x20];
6502
6503 u8 reserved_at_40[0x20];
6504 };
6505
6506 struct mlx5_ifc_disable_hca_in_bits {
6507 u8 opcode[0x10];
6508 u8 reserved_at_10[0x10];
6509
6510 u8 reserved_at_20[0x10];
6511 u8 op_mod[0x10];
6512
6513 u8 embedded_cpu_function[0x1];
6514 u8 reserved_at_41[0xf];
6515 u8 function_id[0x10];
6516
6517 u8 reserved_at_60[0x20];
6518 };
6519
6520 struct mlx5_ifc_detach_from_mcg_out_bits {
6521 u8 status[0x8];
6522 u8 reserved_at_8[0x18];
6523
6524 u8 syndrome[0x20];
6525
6526 u8 reserved_at_40[0x40];
6527 };
6528
6529 struct mlx5_ifc_detach_from_mcg_in_bits {
6530 u8 opcode[0x10];
6531 u8 uid[0x10];
6532
6533 u8 reserved_at_20[0x10];
6534 u8 op_mod[0x10];
6535
6536 u8 reserved_at_40[0x8];
6537 u8 qpn[0x18];
6538
6539 u8 reserved_at_60[0x20];
6540
6541 u8 multicast_gid[16][0x8];
6542 };
6543
6544 struct mlx5_ifc_destroy_xrq_out_bits {
6545 u8 status[0x8];
6546 u8 reserved_at_8[0x18];
6547
6548 u8 syndrome[0x20];
6549
6550 u8 reserved_at_40[0x40];
6551 };
6552
6553 struct mlx5_ifc_destroy_xrq_in_bits {
6554 u8 opcode[0x10];
6555 u8 uid[0x10];
6556
6557 u8 reserved_at_20[0x10];
6558 u8 op_mod[0x10];
6559
6560 u8 reserved_at_40[0x8];
6561 u8 xrqn[0x18];
6562
6563 u8 reserved_at_60[0x20];
6564 };
6565
6566 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6567 u8 status[0x8];
6568 u8 reserved_at_8[0x18];
6569
6570 u8 syndrome[0x20];
6571
6572 u8 reserved_at_40[0x40];
6573 };
6574
6575 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6576 u8 opcode[0x10];
6577 u8 uid[0x10];
6578
6579 u8 reserved_at_20[0x10];
6580 u8 op_mod[0x10];
6581
6582 u8 reserved_at_40[0x8];
6583 u8 xrc_srqn[0x18];
6584
6585 u8 reserved_at_60[0x20];
6586 };
6587
6588 struct mlx5_ifc_destroy_tis_out_bits {
6589 u8 status[0x8];
6590 u8 reserved_at_8[0x18];
6591
6592 u8 syndrome[0x20];
6593
6594 u8 reserved_at_40[0x40];
6595 };
6596
6597 struct mlx5_ifc_destroy_tis_in_bits {
6598 u8 opcode[0x10];
6599 u8 uid[0x10];
6600
6601 u8 reserved_at_20[0x10];
6602 u8 op_mod[0x10];
6603
6604 u8 reserved_at_40[0x8];
6605 u8 tisn[0x18];
6606
6607 u8 reserved_at_60[0x20];
6608 };
6609
6610 struct mlx5_ifc_destroy_tir_out_bits {
6611 u8 status[0x8];
6612 u8 reserved_at_8[0x18];
6613
6614 u8 syndrome[0x20];
6615
6616 u8 reserved_at_40[0x40];
6617 };
6618
6619 struct mlx5_ifc_destroy_tir_in_bits {
6620 u8 opcode[0x10];
6621 u8 uid[0x10];
6622
6623 u8 reserved_at_20[0x10];
6624 u8 op_mod[0x10];
6625
6626 u8 reserved_at_40[0x8];
6627 u8 tirn[0x18];
6628
6629 u8 reserved_at_60[0x20];
6630 };
6631
6632 struct mlx5_ifc_destroy_srq_out_bits {
6633 u8 status[0x8];
6634 u8 reserved_at_8[0x18];
6635
6636 u8 syndrome[0x20];
6637
6638 u8 reserved_at_40[0x40];
6639 };
6640
6641 struct mlx5_ifc_destroy_srq_in_bits {
6642 u8 opcode[0x10];
6643 u8 uid[0x10];
6644
6645 u8 reserved_at_20[0x10];
6646 u8 op_mod[0x10];
6647
6648 u8 reserved_at_40[0x8];
6649 u8 srqn[0x18];
6650
6651 u8 reserved_at_60[0x20];
6652 };
6653
6654 struct mlx5_ifc_destroy_sq_out_bits {
6655 u8 status[0x8];
6656 u8 reserved_at_8[0x18];
6657
6658 u8 syndrome[0x20];
6659
6660 u8 reserved_at_40[0x40];
6661 };
6662
6663 struct mlx5_ifc_destroy_sq_in_bits {
6664 u8 opcode[0x10];
6665 u8 uid[0x10];
6666
6667 u8 reserved_at_20[0x10];
6668 u8 op_mod[0x10];
6669
6670 u8 reserved_at_40[0x8];
6671 u8 sqn[0x18];
6672
6673 u8 reserved_at_60[0x20];
6674 };
6675
6676 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6677 u8 status[0x8];
6678 u8 reserved_at_8[0x18];
6679
6680 u8 syndrome[0x20];
6681
6682 u8 reserved_at_40[0x1c0];
6683 };
6684
6685 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6686 u8 opcode[0x10];
6687 u8 reserved_at_10[0x10];
6688
6689 u8 reserved_at_20[0x10];
6690 u8 op_mod[0x10];
6691
6692 u8 scheduling_hierarchy[0x8];
6693 u8 reserved_at_48[0x18];
6694
6695 u8 scheduling_element_id[0x20];
6696
6697 u8 reserved_at_80[0x180];
6698 };
6699
6700 struct mlx5_ifc_destroy_rqt_out_bits {
6701 u8 status[0x8];
6702 u8 reserved_at_8[0x18];
6703
6704 u8 syndrome[0x20];
6705
6706 u8 reserved_at_40[0x40];
6707 };
6708
6709 struct mlx5_ifc_destroy_rqt_in_bits {
6710 u8 opcode[0x10];
6711 u8 uid[0x10];
6712
6713 u8 reserved_at_20[0x10];
6714 u8 op_mod[0x10];
6715
6716 u8 reserved_at_40[0x8];
6717 u8 rqtn[0x18];
6718
6719 u8 reserved_at_60[0x20];
6720 };
6721
6722 struct mlx5_ifc_destroy_rq_out_bits {
6723 u8 status[0x8];
6724 u8 reserved_at_8[0x18];
6725
6726 u8 syndrome[0x20];
6727
6728 u8 reserved_at_40[0x40];
6729 };
6730
6731 struct mlx5_ifc_destroy_rq_in_bits {
6732 u8 opcode[0x10];
6733 u8 uid[0x10];
6734
6735 u8 reserved_at_20[0x10];
6736 u8 op_mod[0x10];
6737
6738 u8 reserved_at_40[0x8];
6739 u8 rqn[0x18];
6740
6741 u8 reserved_at_60[0x20];
6742 };
6743
6744 struct mlx5_ifc_set_delay_drop_params_in_bits {
6745 u8 opcode[0x10];
6746 u8 reserved_at_10[0x10];
6747
6748 u8 reserved_at_20[0x10];
6749 u8 op_mod[0x10];
6750
6751 u8 reserved_at_40[0x20];
6752
6753 u8 reserved_at_60[0x10];
6754 u8 delay_drop_timeout[0x10];
6755 };
6756
6757 struct mlx5_ifc_set_delay_drop_params_out_bits {
6758 u8 status[0x8];
6759 u8 reserved_at_8[0x18];
6760
6761 u8 syndrome[0x20];
6762
6763 u8 reserved_at_40[0x40];
6764 };
6765
6766 struct mlx5_ifc_destroy_rmp_out_bits {
6767 u8 status[0x8];
6768 u8 reserved_at_8[0x18];
6769
6770 u8 syndrome[0x20];
6771
6772 u8 reserved_at_40[0x40];
6773 };
6774
6775 struct mlx5_ifc_destroy_rmp_in_bits {
6776 u8 opcode[0x10];
6777 u8 uid[0x10];
6778
6779 u8 reserved_at_20[0x10];
6780 u8 op_mod[0x10];
6781
6782 u8 reserved_at_40[0x8];
6783 u8 rmpn[0x18];
6784
6785 u8 reserved_at_60[0x20];
6786 };
6787
6788 struct mlx5_ifc_destroy_qp_out_bits {
6789 u8 status[0x8];
6790 u8 reserved_at_8[0x18];
6791
6792 u8 syndrome[0x20];
6793
6794 u8 reserved_at_40[0x40];
6795 };
6796
6797 struct mlx5_ifc_destroy_qp_in_bits {
6798 u8 opcode[0x10];
6799 u8 uid[0x10];
6800
6801 u8 reserved_at_20[0x10];
6802 u8 op_mod[0x10];
6803
6804 u8 reserved_at_40[0x8];
6805 u8 qpn[0x18];
6806
6807 u8 reserved_at_60[0x20];
6808 };
6809
6810 struct mlx5_ifc_destroy_psv_out_bits {
6811 u8 status[0x8];
6812 u8 reserved_at_8[0x18];
6813
6814 u8 syndrome[0x20];
6815
6816 u8 reserved_at_40[0x40];
6817 };
6818
6819 struct mlx5_ifc_destroy_psv_in_bits {
6820 u8 opcode[0x10];
6821 u8 reserved_at_10[0x10];
6822
6823 u8 reserved_at_20[0x10];
6824 u8 op_mod[0x10];
6825
6826 u8 reserved_at_40[0x8];
6827 u8 psvn[0x18];
6828
6829 u8 reserved_at_60[0x20];
6830 };
6831
6832 struct mlx5_ifc_destroy_mkey_out_bits {
6833 u8 status[0x8];
6834 u8 reserved_at_8[0x18];
6835
6836 u8 syndrome[0x20];
6837
6838 u8 reserved_at_40[0x40];
6839 };
6840
6841 struct mlx5_ifc_destroy_mkey_in_bits {
6842 u8 opcode[0x10];
6843 u8 reserved_at_10[0x10];
6844
6845 u8 reserved_at_20[0x10];
6846 u8 op_mod[0x10];
6847
6848 u8 reserved_at_40[0x8];
6849 u8 mkey_index[0x18];
6850
6851 u8 reserved_at_60[0x20];
6852 };
6853
6854 struct mlx5_ifc_destroy_flow_table_out_bits {
6855 u8 status[0x8];
6856 u8 reserved_at_8[0x18];
6857
6858 u8 syndrome[0x20];
6859
6860 u8 reserved_at_40[0x40];
6861 };
6862
6863 struct mlx5_ifc_destroy_flow_table_in_bits {
6864 u8 opcode[0x10];
6865 u8 reserved_at_10[0x10];
6866
6867 u8 reserved_at_20[0x10];
6868 u8 op_mod[0x10];
6869
6870 u8 other_vport[0x1];
6871 u8 reserved_at_41[0xf];
6872 u8 vport_number[0x10];
6873
6874 u8 reserved_at_60[0x20];
6875
6876 u8 table_type[0x8];
6877 u8 reserved_at_88[0x18];
6878
6879 u8 reserved_at_a0[0x8];
6880 u8 table_id[0x18];
6881
6882 u8 reserved_at_c0[0x140];
6883 };
6884
6885 struct mlx5_ifc_destroy_flow_group_out_bits {
6886 u8 status[0x8];
6887 u8 reserved_at_8[0x18];
6888
6889 u8 syndrome[0x20];
6890
6891 u8 reserved_at_40[0x40];
6892 };
6893
6894 struct mlx5_ifc_destroy_flow_group_in_bits {
6895 u8 opcode[0x10];
6896 u8 reserved_at_10[0x10];
6897
6898 u8 reserved_at_20[0x10];
6899 u8 op_mod[0x10];
6900
6901 u8 other_vport[0x1];
6902 u8 reserved_at_41[0xf];
6903 u8 vport_number[0x10];
6904
6905 u8 reserved_at_60[0x20];
6906
6907 u8 table_type[0x8];
6908 u8 reserved_at_88[0x18];
6909
6910 u8 reserved_at_a0[0x8];
6911 u8 table_id[0x18];
6912
6913 u8 group_id[0x20];
6914
6915 u8 reserved_at_e0[0x120];
6916 };
6917
6918 struct mlx5_ifc_destroy_eq_out_bits {
6919 u8 status[0x8];
6920 u8 reserved_at_8[0x18];
6921
6922 u8 syndrome[0x20];
6923
6924 u8 reserved_at_40[0x40];
6925 };
6926
6927 struct mlx5_ifc_destroy_eq_in_bits {
6928 u8 opcode[0x10];
6929 u8 reserved_at_10[0x10];
6930
6931 u8 reserved_at_20[0x10];
6932 u8 op_mod[0x10];
6933
6934 u8 reserved_at_40[0x18];
6935 u8 eq_number[0x8];
6936
6937 u8 reserved_at_60[0x20];
6938 };
6939
6940 struct mlx5_ifc_destroy_dct_out_bits {
6941 u8 status[0x8];
6942 u8 reserved_at_8[0x18];
6943
6944 u8 syndrome[0x20];
6945
6946 u8 reserved_at_40[0x40];
6947 };
6948
6949 struct mlx5_ifc_destroy_dct_in_bits {
6950 u8 opcode[0x10];
6951 u8 uid[0x10];
6952
6953 u8 reserved_at_20[0x10];
6954 u8 op_mod[0x10];
6955
6956 u8 reserved_at_40[0x8];
6957 u8 dctn[0x18];
6958
6959 u8 reserved_at_60[0x20];
6960 };
6961
6962 struct mlx5_ifc_destroy_cq_out_bits {
6963 u8 status[0x8];
6964 u8 reserved_at_8[0x18];
6965
6966 u8 syndrome[0x20];
6967
6968 u8 reserved_at_40[0x40];
6969 };
6970
6971 struct mlx5_ifc_destroy_cq_in_bits {
6972 u8 opcode[0x10];
6973 u8 uid[0x10];
6974
6975 u8 reserved_at_20[0x10];
6976 u8 op_mod[0x10];
6977
6978 u8 reserved_at_40[0x8];
6979 u8 cqn[0x18];
6980
6981 u8 reserved_at_60[0x20];
6982 };
6983
6984 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6985 u8 status[0x8];
6986 u8 reserved_at_8[0x18];
6987
6988 u8 syndrome[0x20];
6989
6990 u8 reserved_at_40[0x40];
6991 };
6992
6993 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6994 u8 opcode[0x10];
6995 u8 reserved_at_10[0x10];
6996
6997 u8 reserved_at_20[0x10];
6998 u8 op_mod[0x10];
6999
7000 u8 reserved_at_40[0x20];
7001
7002 u8 reserved_at_60[0x10];
7003 u8 vxlan_udp_port[0x10];
7004 };
7005
7006 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7007 u8 status[0x8];
7008 u8 reserved_at_8[0x18];
7009
7010 u8 syndrome[0x20];
7011
7012 u8 reserved_at_40[0x40];
7013 };
7014
7015 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7016 u8 opcode[0x10];
7017 u8 reserved_at_10[0x10];
7018
7019 u8 reserved_at_20[0x10];
7020 u8 op_mod[0x10];
7021
7022 u8 reserved_at_40[0x60];
7023
7024 u8 reserved_at_a0[0x8];
7025 u8 table_index[0x18];
7026
7027 u8 reserved_at_c0[0x140];
7028 };
7029
7030 struct mlx5_ifc_delete_fte_out_bits {
7031 u8 status[0x8];
7032 u8 reserved_at_8[0x18];
7033
7034 u8 syndrome[0x20];
7035
7036 u8 reserved_at_40[0x40];
7037 };
7038
7039 struct mlx5_ifc_delete_fte_in_bits {
7040 u8 opcode[0x10];
7041 u8 reserved_at_10[0x10];
7042
7043 u8 reserved_at_20[0x10];
7044 u8 op_mod[0x10];
7045
7046 u8 other_vport[0x1];
7047 u8 reserved_at_41[0xf];
7048 u8 vport_number[0x10];
7049
7050 u8 reserved_at_60[0x20];
7051
7052 u8 table_type[0x8];
7053 u8 reserved_at_88[0x18];
7054
7055 u8 reserved_at_a0[0x8];
7056 u8 table_id[0x18];
7057
7058 u8 reserved_at_c0[0x40];
7059
7060 u8 flow_index[0x20];
7061
7062 u8 reserved_at_120[0xe0];
7063 };
7064
7065 struct mlx5_ifc_dealloc_xrcd_out_bits {
7066 u8 status[0x8];
7067 u8 reserved_at_8[0x18];
7068
7069 u8 syndrome[0x20];
7070
7071 u8 reserved_at_40[0x40];
7072 };
7073
7074 struct mlx5_ifc_dealloc_xrcd_in_bits {
7075 u8 opcode[0x10];
7076 u8 uid[0x10];
7077
7078 u8 reserved_at_20[0x10];
7079 u8 op_mod[0x10];
7080
7081 u8 reserved_at_40[0x8];
7082 u8 xrcd[0x18];
7083
7084 u8 reserved_at_60[0x20];
7085 };
7086
7087 struct mlx5_ifc_dealloc_uar_out_bits {
7088 u8 status[0x8];
7089 u8 reserved_at_8[0x18];
7090
7091 u8 syndrome[0x20];
7092
7093 u8 reserved_at_40[0x40];
7094 };
7095
7096 struct mlx5_ifc_dealloc_uar_in_bits {
7097 u8 opcode[0x10];
7098 u8 reserved_at_10[0x10];
7099
7100 u8 reserved_at_20[0x10];
7101 u8 op_mod[0x10];
7102
7103 u8 reserved_at_40[0x8];
7104 u8 uar[0x18];
7105
7106 u8 reserved_at_60[0x20];
7107 };
7108
7109 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7110 u8 status[0x8];
7111 u8 reserved_at_8[0x18];
7112
7113 u8 syndrome[0x20];
7114
7115 u8 reserved_at_40[0x40];
7116 };
7117
7118 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7119 u8 opcode[0x10];
7120 u8 uid[0x10];
7121
7122 u8 reserved_at_20[0x10];
7123 u8 op_mod[0x10];
7124
7125 u8 reserved_at_40[0x8];
7126 u8 transport_domain[0x18];
7127
7128 u8 reserved_at_60[0x20];
7129 };
7130
7131 struct mlx5_ifc_dealloc_q_counter_out_bits {
7132 u8 status[0x8];
7133 u8 reserved_at_8[0x18];
7134
7135 u8 syndrome[0x20];
7136
7137 u8 reserved_at_40[0x40];
7138 };
7139
7140 struct mlx5_ifc_dealloc_q_counter_in_bits {
7141 u8 opcode[0x10];
7142 u8 reserved_at_10[0x10];
7143
7144 u8 reserved_at_20[0x10];
7145 u8 op_mod[0x10];
7146
7147 u8 reserved_at_40[0x18];
7148 u8 counter_set_id[0x8];
7149
7150 u8 reserved_at_60[0x20];
7151 };
7152
7153 struct mlx5_ifc_dealloc_pd_out_bits {
7154 u8 status[0x8];
7155 u8 reserved_at_8[0x18];
7156
7157 u8 syndrome[0x20];
7158
7159 u8 reserved_at_40[0x40];
7160 };
7161
7162 struct mlx5_ifc_dealloc_pd_in_bits {
7163 u8 opcode[0x10];
7164 u8 uid[0x10];
7165
7166 u8 reserved_at_20[0x10];
7167 u8 op_mod[0x10];
7168
7169 u8 reserved_at_40[0x8];
7170 u8 pd[0x18];
7171
7172 u8 reserved_at_60[0x20];
7173 };
7174
7175 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7176 u8 status[0x8];
7177 u8 reserved_at_8[0x18];
7178
7179 u8 syndrome[0x20];
7180
7181 u8 reserved_at_40[0x40];
7182 };
7183
7184 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7185 u8 opcode[0x10];
7186 u8 reserved_at_10[0x10];
7187
7188 u8 reserved_at_20[0x10];
7189 u8 op_mod[0x10];
7190
7191 u8 flow_counter_id[0x20];
7192
7193 u8 reserved_at_60[0x20];
7194 };
7195
7196 struct mlx5_ifc_create_xrq_out_bits {
7197 u8 status[0x8];
7198 u8 reserved_at_8[0x18];
7199
7200 u8 syndrome[0x20];
7201
7202 u8 reserved_at_40[0x8];
7203 u8 xrqn[0x18];
7204
7205 u8 reserved_at_60[0x20];
7206 };
7207
7208 struct mlx5_ifc_create_xrq_in_bits {
7209 u8 opcode[0x10];
7210 u8 uid[0x10];
7211
7212 u8 reserved_at_20[0x10];
7213 u8 op_mod[0x10];
7214
7215 u8 reserved_at_40[0x40];
7216
7217 struct mlx5_ifc_xrqc_bits xrq_context;
7218 };
7219
7220 struct mlx5_ifc_create_xrc_srq_out_bits {
7221 u8 status[0x8];
7222 u8 reserved_at_8[0x18];
7223
7224 u8 syndrome[0x20];
7225
7226 u8 reserved_at_40[0x8];
7227 u8 xrc_srqn[0x18];
7228
7229 u8 reserved_at_60[0x20];
7230 };
7231
7232 struct mlx5_ifc_create_xrc_srq_in_bits {
7233 u8 opcode[0x10];
7234 u8 uid[0x10];
7235
7236 u8 reserved_at_20[0x10];
7237 u8 op_mod[0x10];
7238
7239 u8 reserved_at_40[0x40];
7240
7241 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7242
7243 u8 reserved_at_280[0x60];
7244
7245 u8 xrc_srq_umem_valid[0x1];
7246 u8 reserved_at_2e1[0x1f];
7247
7248 u8 reserved_at_300[0x580];
7249
7250 u8 pas[0][0x40];
7251 };
7252
7253 struct mlx5_ifc_create_tis_out_bits {
7254 u8 status[0x8];
7255 u8 reserved_at_8[0x18];
7256
7257 u8 syndrome[0x20];
7258
7259 u8 reserved_at_40[0x8];
7260 u8 tisn[0x18];
7261
7262 u8 reserved_at_60[0x20];
7263 };
7264
7265 struct mlx5_ifc_create_tis_in_bits {
7266 u8 opcode[0x10];
7267 u8 uid[0x10];
7268
7269 u8 reserved_at_20[0x10];
7270 u8 op_mod[0x10];
7271
7272 u8 reserved_at_40[0xc0];
7273
7274 struct mlx5_ifc_tisc_bits ctx;
7275 };
7276
7277 struct mlx5_ifc_create_tir_out_bits {
7278 u8 status[0x8];
7279 u8 icm_address_63_40[0x18];
7280
7281 u8 syndrome[0x20];
7282
7283 u8 icm_address_39_32[0x8];
7284 u8 tirn[0x18];
7285
7286 u8 icm_address_31_0[0x20];
7287 };
7288
7289 struct mlx5_ifc_create_tir_in_bits {
7290 u8 opcode[0x10];
7291 u8 uid[0x10];
7292
7293 u8 reserved_at_20[0x10];
7294 u8 op_mod[0x10];
7295
7296 u8 reserved_at_40[0xc0];
7297
7298 struct mlx5_ifc_tirc_bits ctx;
7299 };
7300
7301 struct mlx5_ifc_create_srq_out_bits {
7302 u8 status[0x8];
7303 u8 reserved_at_8[0x18];
7304
7305 u8 syndrome[0x20];
7306
7307 u8 reserved_at_40[0x8];
7308 u8 srqn[0x18];
7309
7310 u8 reserved_at_60[0x20];
7311 };
7312
7313 struct mlx5_ifc_create_srq_in_bits {
7314 u8 opcode[0x10];
7315 u8 uid[0x10];
7316
7317 u8 reserved_at_20[0x10];
7318 u8 op_mod[0x10];
7319
7320 u8 reserved_at_40[0x40];
7321
7322 struct mlx5_ifc_srqc_bits srq_context_entry;
7323
7324 u8 reserved_at_280[0x600];
7325
7326 u8 pas[0][0x40];
7327 };
7328
7329 struct mlx5_ifc_create_sq_out_bits {
7330 u8 status[0x8];
7331 u8 reserved_at_8[0x18];
7332
7333 u8 syndrome[0x20];
7334
7335 u8 reserved_at_40[0x8];
7336 u8 sqn[0x18];
7337
7338 u8 reserved_at_60[0x20];
7339 };
7340
7341 struct mlx5_ifc_create_sq_in_bits {
7342 u8 opcode[0x10];
7343 u8 uid[0x10];
7344
7345 u8 reserved_at_20[0x10];
7346 u8 op_mod[0x10];
7347
7348 u8 reserved_at_40[0xc0];
7349
7350 struct mlx5_ifc_sqc_bits ctx;
7351 };
7352
7353 struct mlx5_ifc_create_scheduling_element_out_bits {
7354 u8 status[0x8];
7355 u8 reserved_at_8[0x18];
7356
7357 u8 syndrome[0x20];
7358
7359 u8 reserved_at_40[0x40];
7360
7361 u8 scheduling_element_id[0x20];
7362
7363 u8 reserved_at_a0[0x160];
7364 };
7365
7366 struct mlx5_ifc_create_scheduling_element_in_bits {
7367 u8 opcode[0x10];
7368 u8 reserved_at_10[0x10];
7369
7370 u8 reserved_at_20[0x10];
7371 u8 op_mod[0x10];
7372
7373 u8 scheduling_hierarchy[0x8];
7374 u8 reserved_at_48[0x18];
7375
7376 u8 reserved_at_60[0xa0];
7377
7378 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7379
7380 u8 reserved_at_300[0x100];
7381 };
7382
7383 struct mlx5_ifc_create_rqt_out_bits {
7384 u8 status[0x8];
7385 u8 reserved_at_8[0x18];
7386
7387 u8 syndrome[0x20];
7388
7389 u8 reserved_at_40[0x8];
7390 u8 rqtn[0x18];
7391
7392 u8 reserved_at_60[0x20];
7393 };
7394
7395 struct mlx5_ifc_create_rqt_in_bits {
7396 u8 opcode[0x10];
7397 u8 uid[0x10];
7398
7399 u8 reserved_at_20[0x10];
7400 u8 op_mod[0x10];
7401
7402 u8 reserved_at_40[0xc0];
7403
7404 struct mlx5_ifc_rqtc_bits rqt_context;
7405 };
7406
7407 struct mlx5_ifc_create_rq_out_bits {
7408 u8 status[0x8];
7409 u8 reserved_at_8[0x18];
7410
7411 u8 syndrome[0x20];
7412
7413 u8 reserved_at_40[0x8];
7414 u8 rqn[0x18];
7415
7416 u8 reserved_at_60[0x20];
7417 };
7418
7419 struct mlx5_ifc_create_rq_in_bits {
7420 u8 opcode[0x10];
7421 u8 uid[0x10];
7422
7423 u8 reserved_at_20[0x10];
7424 u8 op_mod[0x10];
7425
7426 u8 reserved_at_40[0xc0];
7427
7428 struct mlx5_ifc_rqc_bits ctx;
7429 };
7430
7431 struct mlx5_ifc_create_rmp_out_bits {
7432 u8 status[0x8];
7433 u8 reserved_at_8[0x18];
7434
7435 u8 syndrome[0x20];
7436
7437 u8 reserved_at_40[0x8];
7438 u8 rmpn[0x18];
7439
7440 u8 reserved_at_60[0x20];
7441 };
7442
7443 struct mlx5_ifc_create_rmp_in_bits {
7444 u8 opcode[0x10];
7445 u8 uid[0x10];
7446
7447 u8 reserved_at_20[0x10];
7448 u8 op_mod[0x10];
7449
7450 u8 reserved_at_40[0xc0];
7451
7452 struct mlx5_ifc_rmpc_bits ctx;
7453 };
7454
7455 struct mlx5_ifc_create_qp_out_bits {
7456 u8 status[0x8];
7457 u8 reserved_at_8[0x18];
7458
7459 u8 syndrome[0x20];
7460
7461 u8 reserved_at_40[0x8];
7462 u8 qpn[0x18];
7463
7464 u8 reserved_at_60[0x20];
7465 };
7466
7467 struct mlx5_ifc_create_qp_in_bits {
7468 u8 opcode[0x10];
7469 u8 uid[0x10];
7470
7471 u8 reserved_at_20[0x10];
7472 u8 op_mod[0x10];
7473
7474 u8 reserved_at_40[0x40];
7475
7476 u8 opt_param_mask[0x20];
7477
7478 u8 reserved_at_a0[0x20];
7479
7480 struct mlx5_ifc_qpc_bits qpc;
7481
7482 u8 reserved_at_800[0x60];
7483
7484 u8 wq_umem_valid[0x1];
7485 u8 reserved_at_861[0x1f];
7486
7487 u8 pas[0][0x40];
7488 };
7489
7490 struct mlx5_ifc_create_psv_out_bits {
7491 u8 status[0x8];
7492 u8 reserved_at_8[0x18];
7493
7494 u8 syndrome[0x20];
7495
7496 u8 reserved_at_40[0x40];
7497
7498 u8 reserved_at_80[0x8];
7499 u8 psv0_index[0x18];
7500
7501 u8 reserved_at_a0[0x8];
7502 u8 psv1_index[0x18];
7503
7504 u8 reserved_at_c0[0x8];
7505 u8 psv2_index[0x18];
7506
7507 u8 reserved_at_e0[0x8];
7508 u8 psv3_index[0x18];
7509 };
7510
7511 struct mlx5_ifc_create_psv_in_bits {
7512 u8 opcode[0x10];
7513 u8 reserved_at_10[0x10];
7514
7515 u8 reserved_at_20[0x10];
7516 u8 op_mod[0x10];
7517
7518 u8 num_psv[0x4];
7519 u8 reserved_at_44[0x4];
7520 u8 pd[0x18];
7521
7522 u8 reserved_at_60[0x20];
7523 };
7524
7525 struct mlx5_ifc_create_mkey_out_bits {
7526 u8 status[0x8];
7527 u8 reserved_at_8[0x18];
7528
7529 u8 syndrome[0x20];
7530
7531 u8 reserved_at_40[0x8];
7532 u8 mkey_index[0x18];
7533
7534 u8 reserved_at_60[0x20];
7535 };
7536
7537 struct mlx5_ifc_create_mkey_in_bits {
7538 u8 opcode[0x10];
7539 u8 reserved_at_10[0x10];
7540
7541 u8 reserved_at_20[0x10];
7542 u8 op_mod[0x10];
7543
7544 u8 reserved_at_40[0x20];
7545
7546 u8 pg_access[0x1];
7547 u8 mkey_umem_valid[0x1];
7548 u8 reserved_at_62[0x1e];
7549
7550 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7551
7552 u8 reserved_at_280[0x80];
7553
7554 u8 translations_octword_actual_size[0x20];
7555
7556 u8 reserved_at_320[0x560];
7557
7558 u8 klm_pas_mtt[0][0x20];
7559 };
7560
7561 enum {
7562 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7563 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7564 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7565 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7566 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7567 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7568 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7569 };
7570
7571 struct mlx5_ifc_create_flow_table_out_bits {
7572 u8 status[0x8];
7573 u8 icm_address_63_40[0x18];
7574
7575 u8 syndrome[0x20];
7576
7577 u8 icm_address_39_32[0x8];
7578 u8 table_id[0x18];
7579
7580 u8 icm_address_31_0[0x20];
7581 };
7582
7583 struct mlx5_ifc_create_flow_table_in_bits {
7584 u8 opcode[0x10];
7585 u8 reserved_at_10[0x10];
7586
7587 u8 reserved_at_20[0x10];
7588 u8 op_mod[0x10];
7589
7590 u8 other_vport[0x1];
7591 u8 reserved_at_41[0xf];
7592 u8 vport_number[0x10];
7593
7594 u8 reserved_at_60[0x20];
7595
7596 u8 table_type[0x8];
7597 u8 reserved_at_88[0x18];
7598
7599 u8 reserved_at_a0[0x20];
7600
7601 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7602 };
7603
7604 struct mlx5_ifc_create_flow_group_out_bits {
7605 u8 status[0x8];
7606 u8 reserved_at_8[0x18];
7607
7608 u8 syndrome[0x20];
7609
7610 u8 reserved_at_40[0x8];
7611 u8 group_id[0x18];
7612
7613 u8 reserved_at_60[0x20];
7614 };
7615
7616 enum {
7617 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7618 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7619 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7620 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7621 };
7622
7623 struct mlx5_ifc_create_flow_group_in_bits {
7624 u8 opcode[0x10];
7625 u8 reserved_at_10[0x10];
7626
7627 u8 reserved_at_20[0x10];
7628 u8 op_mod[0x10];
7629
7630 u8 other_vport[0x1];
7631 u8 reserved_at_41[0xf];
7632 u8 vport_number[0x10];
7633
7634 u8 reserved_at_60[0x20];
7635
7636 u8 table_type[0x8];
7637 u8 reserved_at_88[0x18];
7638
7639 u8 reserved_at_a0[0x8];
7640 u8 table_id[0x18];
7641
7642 u8 source_eswitch_owner_vhca_id_valid[0x1];
7643
7644 u8 reserved_at_c1[0x1f];
7645
7646 u8 start_flow_index[0x20];
7647
7648 u8 reserved_at_100[0x20];
7649
7650 u8 end_flow_index[0x20];
7651
7652 u8 reserved_at_140[0xa0];
7653
7654 u8 reserved_at_1e0[0x18];
7655 u8 match_criteria_enable[0x8];
7656
7657 struct mlx5_ifc_fte_match_param_bits match_criteria;
7658
7659 u8 reserved_at_1200[0xe00];
7660 };
7661
7662 struct mlx5_ifc_create_eq_out_bits {
7663 u8 status[0x8];
7664 u8 reserved_at_8[0x18];
7665
7666 u8 syndrome[0x20];
7667
7668 u8 reserved_at_40[0x18];
7669 u8 eq_number[0x8];
7670
7671 u8 reserved_at_60[0x20];
7672 };
7673
7674 struct mlx5_ifc_create_eq_in_bits {
7675 u8 opcode[0x10];
7676 u8 uid[0x10];
7677
7678 u8 reserved_at_20[0x10];
7679 u8 op_mod[0x10];
7680
7681 u8 reserved_at_40[0x40];
7682
7683 struct mlx5_ifc_eqc_bits eq_context_entry;
7684
7685 u8 reserved_at_280[0x40];
7686
7687 u8 event_bitmask[4][0x40];
7688
7689 u8 reserved_at_3c0[0x4c0];
7690
7691 u8 pas[0][0x40];
7692 };
7693
7694 struct mlx5_ifc_create_dct_out_bits {
7695 u8 status[0x8];
7696 u8 reserved_at_8[0x18];
7697
7698 u8 syndrome[0x20];
7699
7700 u8 reserved_at_40[0x8];
7701 u8 dctn[0x18];
7702
7703 u8 reserved_at_60[0x20];
7704 };
7705
7706 struct mlx5_ifc_create_dct_in_bits {
7707 u8 opcode[0x10];
7708 u8 uid[0x10];
7709
7710 u8 reserved_at_20[0x10];
7711 u8 op_mod[0x10];
7712
7713 u8 reserved_at_40[0x40];
7714
7715 struct mlx5_ifc_dctc_bits dct_context_entry;
7716
7717 u8 reserved_at_280[0x180];
7718 };
7719
7720 struct mlx5_ifc_create_cq_out_bits {
7721 u8 status[0x8];
7722 u8 reserved_at_8[0x18];
7723
7724 u8 syndrome[0x20];
7725
7726 u8 reserved_at_40[0x8];
7727 u8 cqn[0x18];
7728
7729 u8 reserved_at_60[0x20];
7730 };
7731
7732 struct mlx5_ifc_create_cq_in_bits {
7733 u8 opcode[0x10];
7734 u8 uid[0x10];
7735
7736 u8 reserved_at_20[0x10];
7737 u8 op_mod[0x10];
7738
7739 u8 reserved_at_40[0x40];
7740
7741 struct mlx5_ifc_cqc_bits cq_context;
7742
7743 u8 reserved_at_280[0x60];
7744
7745 u8 cq_umem_valid[0x1];
7746 u8 reserved_at_2e1[0x59f];
7747
7748 u8 pas[0][0x40];
7749 };
7750
7751 struct mlx5_ifc_config_int_moderation_out_bits {
7752 u8 status[0x8];
7753 u8 reserved_at_8[0x18];
7754
7755 u8 syndrome[0x20];
7756
7757 u8 reserved_at_40[0x4];
7758 u8 min_delay[0xc];
7759 u8 int_vector[0x10];
7760
7761 u8 reserved_at_60[0x20];
7762 };
7763
7764 enum {
7765 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7766 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7767 };
7768
7769 struct mlx5_ifc_config_int_moderation_in_bits {
7770 u8 opcode[0x10];
7771 u8 reserved_at_10[0x10];
7772
7773 u8 reserved_at_20[0x10];
7774 u8 op_mod[0x10];
7775
7776 u8 reserved_at_40[0x4];
7777 u8 min_delay[0xc];
7778 u8 int_vector[0x10];
7779
7780 u8 reserved_at_60[0x20];
7781 };
7782
7783 struct mlx5_ifc_attach_to_mcg_out_bits {
7784 u8 status[0x8];
7785 u8 reserved_at_8[0x18];
7786
7787 u8 syndrome[0x20];
7788
7789 u8 reserved_at_40[0x40];
7790 };
7791
7792 struct mlx5_ifc_attach_to_mcg_in_bits {
7793 u8 opcode[0x10];
7794 u8 uid[0x10];
7795
7796 u8 reserved_at_20[0x10];
7797 u8 op_mod[0x10];
7798
7799 u8 reserved_at_40[0x8];
7800 u8 qpn[0x18];
7801
7802 u8 reserved_at_60[0x20];
7803
7804 u8 multicast_gid[16][0x8];
7805 };
7806
7807 struct mlx5_ifc_arm_xrq_out_bits {
7808 u8 status[0x8];
7809 u8 reserved_at_8[0x18];
7810
7811 u8 syndrome[0x20];
7812
7813 u8 reserved_at_40[0x40];
7814 };
7815
7816 struct mlx5_ifc_arm_xrq_in_bits {
7817 u8 opcode[0x10];
7818 u8 reserved_at_10[0x10];
7819
7820 u8 reserved_at_20[0x10];
7821 u8 op_mod[0x10];
7822
7823 u8 reserved_at_40[0x8];
7824 u8 xrqn[0x18];
7825
7826 u8 reserved_at_60[0x10];
7827 u8 lwm[0x10];
7828 };
7829
7830 struct mlx5_ifc_arm_xrc_srq_out_bits {
7831 u8 status[0x8];
7832 u8 reserved_at_8[0x18];
7833
7834 u8 syndrome[0x20];
7835
7836 u8 reserved_at_40[0x40];
7837 };
7838
7839 enum {
7840 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7841 };
7842
7843 struct mlx5_ifc_arm_xrc_srq_in_bits {
7844 u8 opcode[0x10];
7845 u8 uid[0x10];
7846
7847 u8 reserved_at_20[0x10];
7848 u8 op_mod[0x10];
7849
7850 u8 reserved_at_40[0x8];
7851 u8 xrc_srqn[0x18];
7852
7853 u8 reserved_at_60[0x10];
7854 u8 lwm[0x10];
7855 };
7856
7857 struct mlx5_ifc_arm_rq_out_bits {
7858 u8 status[0x8];
7859 u8 reserved_at_8[0x18];
7860
7861 u8 syndrome[0x20];
7862
7863 u8 reserved_at_40[0x40];
7864 };
7865
7866 enum {
7867 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7868 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7869 };
7870
7871 struct mlx5_ifc_arm_rq_in_bits {
7872 u8 opcode[0x10];
7873 u8 uid[0x10];
7874
7875 u8 reserved_at_20[0x10];
7876 u8 op_mod[0x10];
7877
7878 u8 reserved_at_40[0x8];
7879 u8 srq_number[0x18];
7880
7881 u8 reserved_at_60[0x10];
7882 u8 lwm[0x10];
7883 };
7884
7885 struct mlx5_ifc_arm_dct_out_bits {
7886 u8 status[0x8];
7887 u8 reserved_at_8[0x18];
7888
7889 u8 syndrome[0x20];
7890
7891 u8 reserved_at_40[0x40];
7892 };
7893
7894 struct mlx5_ifc_arm_dct_in_bits {
7895 u8 opcode[0x10];
7896 u8 reserved_at_10[0x10];
7897
7898 u8 reserved_at_20[0x10];
7899 u8 op_mod[0x10];
7900
7901 u8 reserved_at_40[0x8];
7902 u8 dct_number[0x18];
7903
7904 u8 reserved_at_60[0x20];
7905 };
7906
7907 struct mlx5_ifc_alloc_xrcd_out_bits {
7908 u8 status[0x8];
7909 u8 reserved_at_8[0x18];
7910
7911 u8 syndrome[0x20];
7912
7913 u8 reserved_at_40[0x8];
7914 u8 xrcd[0x18];
7915
7916 u8 reserved_at_60[0x20];
7917 };
7918
7919 struct mlx5_ifc_alloc_xrcd_in_bits {
7920 u8 opcode[0x10];
7921 u8 uid[0x10];
7922
7923 u8 reserved_at_20[0x10];
7924 u8 op_mod[0x10];
7925
7926 u8 reserved_at_40[0x40];
7927 };
7928
7929 struct mlx5_ifc_alloc_uar_out_bits {
7930 u8 status[0x8];
7931 u8 reserved_at_8[0x18];
7932
7933 u8 syndrome[0x20];
7934
7935 u8 reserved_at_40[0x8];
7936 u8 uar[0x18];
7937
7938 u8 reserved_at_60[0x20];
7939 };
7940
7941 struct mlx5_ifc_alloc_uar_in_bits {
7942 u8 opcode[0x10];
7943 u8 reserved_at_10[0x10];
7944
7945 u8 reserved_at_20[0x10];
7946 u8 op_mod[0x10];
7947
7948 u8 reserved_at_40[0x40];
7949 };
7950
7951 struct mlx5_ifc_alloc_transport_domain_out_bits {
7952 u8 status[0x8];
7953 u8 reserved_at_8[0x18];
7954
7955 u8 syndrome[0x20];
7956
7957 u8 reserved_at_40[0x8];
7958 u8 transport_domain[0x18];
7959
7960 u8 reserved_at_60[0x20];
7961 };
7962
7963 struct mlx5_ifc_alloc_transport_domain_in_bits {
7964 u8 opcode[0x10];
7965 u8 uid[0x10];
7966
7967 u8 reserved_at_20[0x10];
7968 u8 op_mod[0x10];
7969
7970 u8 reserved_at_40[0x40];
7971 };
7972
7973 struct mlx5_ifc_alloc_q_counter_out_bits {
7974 u8 status[0x8];
7975 u8 reserved_at_8[0x18];
7976
7977 u8 syndrome[0x20];
7978
7979 u8 reserved_at_40[0x18];
7980 u8 counter_set_id[0x8];
7981
7982 u8 reserved_at_60[0x20];
7983 };
7984
7985 struct mlx5_ifc_alloc_q_counter_in_bits {
7986 u8 opcode[0x10];
7987 u8 uid[0x10];
7988
7989 u8 reserved_at_20[0x10];
7990 u8 op_mod[0x10];
7991
7992 u8 reserved_at_40[0x40];
7993 };
7994
7995 struct mlx5_ifc_alloc_pd_out_bits {
7996 u8 status[0x8];
7997 u8 reserved_at_8[0x18];
7998
7999 u8 syndrome[0x20];
8000
8001 u8 reserved_at_40[0x8];
8002 u8 pd[0x18];
8003
8004 u8 reserved_at_60[0x20];
8005 };
8006
8007 struct mlx5_ifc_alloc_pd_in_bits {
8008 u8 opcode[0x10];
8009 u8 uid[0x10];
8010
8011 u8 reserved_at_20[0x10];
8012 u8 op_mod[0x10];
8013
8014 u8 reserved_at_40[0x40];
8015 };
8016
8017 struct mlx5_ifc_alloc_flow_counter_out_bits {
8018 u8 status[0x8];
8019 u8 reserved_at_8[0x18];
8020
8021 u8 syndrome[0x20];
8022
8023 u8 flow_counter_id[0x20];
8024
8025 u8 reserved_at_60[0x20];
8026 };
8027
8028 struct mlx5_ifc_alloc_flow_counter_in_bits {
8029 u8 opcode[0x10];
8030 u8 reserved_at_10[0x10];
8031
8032 u8 reserved_at_20[0x10];
8033 u8 op_mod[0x10];
8034
8035 u8 reserved_at_40[0x38];
8036 u8 flow_counter_bulk[0x8];
8037 };
8038
8039 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8040 u8 status[0x8];
8041 u8 reserved_at_8[0x18];
8042
8043 u8 syndrome[0x20];
8044
8045 u8 reserved_at_40[0x40];
8046 };
8047
8048 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8049 u8 opcode[0x10];
8050 u8 reserved_at_10[0x10];
8051
8052 u8 reserved_at_20[0x10];
8053 u8 op_mod[0x10];
8054
8055 u8 reserved_at_40[0x20];
8056
8057 u8 reserved_at_60[0x10];
8058 u8 vxlan_udp_port[0x10];
8059 };
8060
8061 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8062 u8 status[0x8];
8063 u8 reserved_at_8[0x18];
8064
8065 u8 syndrome[0x20];
8066
8067 u8 reserved_at_40[0x40];
8068 };
8069
8070 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8071 u8 opcode[0x10];
8072 u8 reserved_at_10[0x10];
8073
8074 u8 reserved_at_20[0x10];
8075 u8 op_mod[0x10];
8076
8077 u8 reserved_at_40[0x10];
8078 u8 rate_limit_index[0x10];
8079
8080 u8 reserved_at_60[0x20];
8081
8082 u8 rate_limit[0x20];
8083
8084 u8 burst_upper_bound[0x20];
8085
8086 u8 reserved_at_c0[0x10];
8087 u8 typical_packet_size[0x10];
8088
8089 u8 reserved_at_e0[0x120];
8090 };
8091
8092 struct mlx5_ifc_access_register_out_bits {
8093 u8 status[0x8];
8094 u8 reserved_at_8[0x18];
8095
8096 u8 syndrome[0x20];
8097
8098 u8 reserved_at_40[0x40];
8099
8100 u8 register_data[0][0x20];
8101 };
8102
8103 enum {
8104 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8105 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8106 };
8107
8108 struct mlx5_ifc_access_register_in_bits {
8109 u8 opcode[0x10];
8110 u8 reserved_at_10[0x10];
8111
8112 u8 reserved_at_20[0x10];
8113 u8 op_mod[0x10];
8114
8115 u8 reserved_at_40[0x10];
8116 u8 register_id[0x10];
8117
8118 u8 argument[0x20];
8119
8120 u8 register_data[0][0x20];
8121 };
8122
8123 struct mlx5_ifc_sltp_reg_bits {
8124 u8 status[0x4];
8125 u8 version[0x4];
8126 u8 local_port[0x8];
8127 u8 pnat[0x2];
8128 u8 reserved_at_12[0x2];
8129 u8 lane[0x4];
8130 u8 reserved_at_18[0x8];
8131
8132 u8 reserved_at_20[0x20];
8133
8134 u8 reserved_at_40[0x7];
8135 u8 polarity[0x1];
8136 u8 ob_tap0[0x8];
8137 u8 ob_tap1[0x8];
8138 u8 ob_tap2[0x8];
8139
8140 u8 reserved_at_60[0xc];
8141 u8 ob_preemp_mode[0x4];
8142 u8 ob_reg[0x8];
8143 u8 ob_bias[0x8];
8144
8145 u8 reserved_at_80[0x20];
8146 };
8147
8148 struct mlx5_ifc_slrg_reg_bits {
8149 u8 status[0x4];
8150 u8 version[0x4];
8151 u8 local_port[0x8];
8152 u8 pnat[0x2];
8153 u8 reserved_at_12[0x2];
8154 u8 lane[0x4];
8155 u8 reserved_at_18[0x8];
8156
8157 u8 time_to_link_up[0x10];
8158 u8 reserved_at_30[0xc];
8159 u8 grade_lane_speed[0x4];
8160
8161 u8 grade_version[0x8];
8162 u8 grade[0x18];
8163
8164 u8 reserved_at_60[0x4];
8165 u8 height_grade_type[0x4];
8166 u8 height_grade[0x18];
8167
8168 u8 height_dz[0x10];
8169 u8 height_dv[0x10];
8170
8171 u8 reserved_at_a0[0x10];
8172 u8 height_sigma[0x10];
8173
8174 u8 reserved_at_c0[0x20];
8175
8176 u8 reserved_at_e0[0x4];
8177 u8 phase_grade_type[0x4];
8178 u8 phase_grade[0x18];
8179
8180 u8 reserved_at_100[0x8];
8181 u8 phase_eo_pos[0x8];
8182 u8 reserved_at_110[0x8];
8183 u8 phase_eo_neg[0x8];
8184
8185 u8 ffe_set_tested[0x10];
8186 u8 test_errors_per_lane[0x10];
8187 };
8188
8189 struct mlx5_ifc_pvlc_reg_bits {
8190 u8 reserved_at_0[0x8];
8191 u8 local_port[0x8];
8192 u8 reserved_at_10[0x10];
8193
8194 u8 reserved_at_20[0x1c];
8195 u8 vl_hw_cap[0x4];
8196
8197 u8 reserved_at_40[0x1c];
8198 u8 vl_admin[0x4];
8199
8200 u8 reserved_at_60[0x1c];
8201 u8 vl_operational[0x4];
8202 };
8203
8204 struct mlx5_ifc_pude_reg_bits {
8205 u8 swid[0x8];
8206 u8 local_port[0x8];
8207 u8 reserved_at_10[0x4];
8208 u8 admin_status[0x4];
8209 u8 reserved_at_18[0x4];
8210 u8 oper_status[0x4];
8211
8212 u8 reserved_at_20[0x60];
8213 };
8214
8215 struct mlx5_ifc_ptys_reg_bits {
8216 u8 reserved_at_0[0x1];
8217 u8 an_disable_admin[0x1];
8218 u8 an_disable_cap[0x1];
8219 u8 reserved_at_3[0x5];
8220 u8 local_port[0x8];
8221 u8 reserved_at_10[0xd];
8222 u8 proto_mask[0x3];
8223
8224 u8 an_status[0x4];
8225 u8 reserved_at_24[0x1c];
8226
8227 u8 ext_eth_proto_capability[0x20];
8228
8229 u8 eth_proto_capability[0x20];
8230
8231 u8 ib_link_width_capability[0x10];
8232 u8 ib_proto_capability[0x10];
8233
8234 u8 ext_eth_proto_admin[0x20];
8235
8236 u8 eth_proto_admin[0x20];
8237
8238 u8 ib_link_width_admin[0x10];
8239 u8 ib_proto_admin[0x10];
8240
8241 u8 ext_eth_proto_oper[0x20];
8242
8243 u8 eth_proto_oper[0x20];
8244
8245 u8 ib_link_width_oper[0x10];
8246 u8 ib_proto_oper[0x10];
8247
8248 u8 reserved_at_160[0x1c];
8249 u8 connector_type[0x4];
8250
8251 u8 eth_proto_lp_advertise[0x20];
8252
8253 u8 reserved_at_1a0[0x60];
8254 };
8255
8256 struct mlx5_ifc_mlcr_reg_bits {
8257 u8 reserved_at_0[0x8];
8258 u8 local_port[0x8];
8259 u8 reserved_at_10[0x20];
8260
8261 u8 beacon_duration[0x10];
8262 u8 reserved_at_40[0x10];
8263
8264 u8 beacon_remain[0x10];
8265 };
8266
8267 struct mlx5_ifc_ptas_reg_bits {
8268 u8 reserved_at_0[0x20];
8269
8270 u8 algorithm_options[0x10];
8271 u8 reserved_at_30[0x4];
8272 u8 repetitions_mode[0x4];
8273 u8 num_of_repetitions[0x8];
8274
8275 u8 grade_version[0x8];
8276 u8 height_grade_type[0x4];
8277 u8 phase_grade_type[0x4];
8278 u8 height_grade_weight[0x8];
8279 u8 phase_grade_weight[0x8];
8280
8281 u8 gisim_measure_bits[0x10];
8282 u8 adaptive_tap_measure_bits[0x10];
8283
8284 u8 ber_bath_high_error_threshold[0x10];
8285 u8 ber_bath_mid_error_threshold[0x10];
8286
8287 u8 ber_bath_low_error_threshold[0x10];
8288 u8 one_ratio_high_threshold[0x10];
8289
8290 u8 one_ratio_high_mid_threshold[0x10];
8291 u8 one_ratio_low_mid_threshold[0x10];
8292
8293 u8 one_ratio_low_threshold[0x10];
8294 u8 ndeo_error_threshold[0x10];
8295
8296 u8 mixer_offset_step_size[0x10];
8297 u8 reserved_at_110[0x8];
8298 u8 mix90_phase_for_voltage_bath[0x8];
8299
8300 u8 mixer_offset_start[0x10];
8301 u8 mixer_offset_end[0x10];
8302
8303 u8 reserved_at_140[0x15];
8304 u8 ber_test_time[0xb];
8305 };
8306
8307 struct mlx5_ifc_pspa_reg_bits {
8308 u8 swid[0x8];
8309 u8 local_port[0x8];
8310 u8 sub_port[0x8];
8311 u8 reserved_at_18[0x8];
8312
8313 u8 reserved_at_20[0x20];
8314 };
8315
8316 struct mlx5_ifc_pqdr_reg_bits {
8317 u8 reserved_at_0[0x8];
8318 u8 local_port[0x8];
8319 u8 reserved_at_10[0x5];
8320 u8 prio[0x3];
8321 u8 reserved_at_18[0x6];
8322 u8 mode[0x2];
8323
8324 u8 reserved_at_20[0x20];
8325
8326 u8 reserved_at_40[0x10];
8327 u8 min_threshold[0x10];
8328
8329 u8 reserved_at_60[0x10];
8330 u8 max_threshold[0x10];
8331
8332 u8 reserved_at_80[0x10];
8333 u8 mark_probability_denominator[0x10];
8334
8335 u8 reserved_at_a0[0x60];
8336 };
8337
8338 struct mlx5_ifc_ppsc_reg_bits {
8339 u8 reserved_at_0[0x8];
8340 u8 local_port[0x8];
8341 u8 reserved_at_10[0x10];
8342
8343 u8 reserved_at_20[0x60];
8344
8345 u8 reserved_at_80[0x1c];
8346 u8 wrps_admin[0x4];
8347
8348 u8 reserved_at_a0[0x1c];
8349 u8 wrps_status[0x4];
8350
8351 u8 reserved_at_c0[0x8];
8352 u8 up_threshold[0x8];
8353 u8 reserved_at_d0[0x8];
8354 u8 down_threshold[0x8];
8355
8356 u8 reserved_at_e0[0x20];
8357
8358 u8 reserved_at_100[0x1c];
8359 u8 srps_admin[0x4];
8360
8361 u8 reserved_at_120[0x1c];
8362 u8 srps_status[0x4];
8363
8364 u8 reserved_at_140[0x40];
8365 };
8366
8367 struct mlx5_ifc_pplr_reg_bits {
8368 u8 reserved_at_0[0x8];
8369 u8 local_port[0x8];
8370 u8 reserved_at_10[0x10];
8371
8372 u8 reserved_at_20[0x8];
8373 u8 lb_cap[0x8];
8374 u8 reserved_at_30[0x8];
8375 u8 lb_en[0x8];
8376 };
8377
8378 struct mlx5_ifc_pplm_reg_bits {
8379 u8 reserved_at_0[0x8];
8380 u8 local_port[0x8];
8381 u8 reserved_at_10[0x10];
8382
8383 u8 reserved_at_20[0x20];
8384
8385 u8 port_profile_mode[0x8];
8386 u8 static_port_profile[0x8];
8387 u8 active_port_profile[0x8];
8388 u8 reserved_at_58[0x8];
8389
8390 u8 retransmission_active[0x8];
8391 u8 fec_mode_active[0x18];
8392
8393 u8 rs_fec_correction_bypass_cap[0x4];
8394 u8 reserved_at_84[0x8];
8395 u8 fec_override_cap_56g[0x4];
8396 u8 fec_override_cap_100g[0x4];
8397 u8 fec_override_cap_50g[0x4];
8398 u8 fec_override_cap_25g[0x4];
8399 u8 fec_override_cap_10g_40g[0x4];
8400
8401 u8 rs_fec_correction_bypass_admin[0x4];
8402 u8 reserved_at_a4[0x8];
8403 u8 fec_override_admin_56g[0x4];
8404 u8 fec_override_admin_100g[0x4];
8405 u8 fec_override_admin_50g[0x4];
8406 u8 fec_override_admin_25g[0x4];
8407 u8 fec_override_admin_10g_40g[0x4];
8408 };
8409
8410 struct mlx5_ifc_ppcnt_reg_bits {
8411 u8 swid[0x8];
8412 u8 local_port[0x8];
8413 u8 pnat[0x2];
8414 u8 reserved_at_12[0x8];
8415 u8 grp[0x6];
8416
8417 u8 clr[0x1];
8418 u8 reserved_at_21[0x1c];
8419 u8 prio_tc[0x3];
8420
8421 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8422 };
8423
8424 struct mlx5_ifc_mpein_reg_bits {
8425 u8 reserved_at_0[0x2];
8426 u8 depth[0x6];
8427 u8 pcie_index[0x8];
8428 u8 node[0x8];
8429 u8 reserved_at_18[0x8];
8430
8431 u8 capability_mask[0x20];
8432
8433 u8 reserved_at_40[0x8];
8434 u8 link_width_enabled[0x8];
8435 u8 link_speed_enabled[0x10];
8436
8437 u8 lane0_physical_position[0x8];
8438 u8 link_width_active[0x8];
8439 u8 link_speed_active[0x10];
8440
8441 u8 num_of_pfs[0x10];
8442 u8 num_of_vfs[0x10];
8443
8444 u8 bdf0[0x10];
8445 u8 reserved_at_b0[0x10];
8446
8447 u8 max_read_request_size[0x4];
8448 u8 max_payload_size[0x4];
8449 u8 reserved_at_c8[0x5];
8450 u8 pwr_status[0x3];
8451 u8 port_type[0x4];
8452 u8 reserved_at_d4[0xb];
8453 u8 lane_reversal[0x1];
8454
8455 u8 reserved_at_e0[0x14];
8456 u8 pci_power[0xc];
8457
8458 u8 reserved_at_100[0x20];
8459
8460 u8 device_status[0x10];
8461 u8 port_state[0x8];
8462 u8 reserved_at_138[0x8];
8463
8464 u8 reserved_at_140[0x10];
8465 u8 receiver_detect_result[0x10];
8466
8467 u8 reserved_at_160[0x20];
8468 };
8469
8470 struct mlx5_ifc_mpcnt_reg_bits {
8471 u8 reserved_at_0[0x8];
8472 u8 pcie_index[0x8];
8473 u8 reserved_at_10[0xa];
8474 u8 grp[0x6];
8475
8476 u8 clr[0x1];
8477 u8 reserved_at_21[0x1f];
8478
8479 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8480 };
8481
8482 struct mlx5_ifc_ppad_reg_bits {
8483 u8 reserved_at_0[0x3];
8484 u8 single_mac[0x1];
8485 u8 reserved_at_4[0x4];
8486 u8 local_port[0x8];
8487 u8 mac_47_32[0x10];
8488
8489 u8 mac_31_0[0x20];
8490
8491 u8 reserved_at_40[0x40];
8492 };
8493
8494 struct mlx5_ifc_pmtu_reg_bits {
8495 u8 reserved_at_0[0x8];
8496 u8 local_port[0x8];
8497 u8 reserved_at_10[0x10];
8498
8499 u8 max_mtu[0x10];
8500 u8 reserved_at_30[0x10];
8501
8502 u8 admin_mtu[0x10];
8503 u8 reserved_at_50[0x10];
8504
8505 u8 oper_mtu[0x10];
8506 u8 reserved_at_70[0x10];
8507 };
8508
8509 struct mlx5_ifc_pmpr_reg_bits {
8510 u8 reserved_at_0[0x8];
8511 u8 module[0x8];
8512 u8 reserved_at_10[0x10];
8513
8514 u8 reserved_at_20[0x18];
8515 u8 attenuation_5g[0x8];
8516
8517 u8 reserved_at_40[0x18];
8518 u8 attenuation_7g[0x8];
8519
8520 u8 reserved_at_60[0x18];
8521 u8 attenuation_12g[0x8];
8522 };
8523
8524 struct mlx5_ifc_pmpe_reg_bits {
8525 u8 reserved_at_0[0x8];
8526 u8 module[0x8];
8527 u8 reserved_at_10[0xc];
8528 u8 module_status[0x4];
8529
8530 u8 reserved_at_20[0x60];
8531 };
8532
8533 struct mlx5_ifc_pmpc_reg_bits {
8534 u8 module_state_updated[32][0x8];
8535 };
8536
8537 struct mlx5_ifc_pmlpn_reg_bits {
8538 u8 reserved_at_0[0x4];
8539 u8 mlpn_status[0x4];
8540 u8 local_port[0x8];
8541 u8 reserved_at_10[0x10];
8542
8543 u8 e[0x1];
8544 u8 reserved_at_21[0x1f];
8545 };
8546
8547 struct mlx5_ifc_pmlp_reg_bits {
8548 u8 rxtx[0x1];
8549 u8 reserved_at_1[0x7];
8550 u8 local_port[0x8];
8551 u8 reserved_at_10[0x8];
8552 u8 width[0x8];
8553
8554 u8 lane0_module_mapping[0x20];
8555
8556 u8 lane1_module_mapping[0x20];
8557
8558 u8 lane2_module_mapping[0x20];
8559
8560 u8 lane3_module_mapping[0x20];
8561
8562 u8 reserved_at_a0[0x160];
8563 };
8564
8565 struct mlx5_ifc_pmaos_reg_bits {
8566 u8 reserved_at_0[0x8];
8567 u8 module[0x8];
8568 u8 reserved_at_10[0x4];
8569 u8 admin_status[0x4];
8570 u8 reserved_at_18[0x4];
8571 u8 oper_status[0x4];
8572
8573 u8 ase[0x1];
8574 u8 ee[0x1];
8575 u8 reserved_at_22[0x1c];
8576 u8 e[0x2];
8577
8578 u8 reserved_at_40[0x40];
8579 };
8580
8581 struct mlx5_ifc_plpc_reg_bits {
8582 u8 reserved_at_0[0x4];
8583 u8 profile_id[0xc];
8584 u8 reserved_at_10[0x4];
8585 u8 proto_mask[0x4];
8586 u8 reserved_at_18[0x8];
8587
8588 u8 reserved_at_20[0x10];
8589 u8 lane_speed[0x10];
8590
8591 u8 reserved_at_40[0x17];
8592 u8 lpbf[0x1];
8593 u8 fec_mode_policy[0x8];
8594
8595 u8 retransmission_capability[0x8];
8596 u8 fec_mode_capability[0x18];
8597
8598 u8 retransmission_support_admin[0x8];
8599 u8 fec_mode_support_admin[0x18];
8600
8601 u8 retransmission_request_admin[0x8];
8602 u8 fec_mode_request_admin[0x18];
8603
8604 u8 reserved_at_c0[0x80];
8605 };
8606
8607 struct mlx5_ifc_plib_reg_bits {
8608 u8 reserved_at_0[0x8];
8609 u8 local_port[0x8];
8610 u8 reserved_at_10[0x8];
8611 u8 ib_port[0x8];
8612
8613 u8 reserved_at_20[0x60];
8614 };
8615
8616 struct mlx5_ifc_plbf_reg_bits {
8617 u8 reserved_at_0[0x8];
8618 u8 local_port[0x8];
8619 u8 reserved_at_10[0xd];
8620 u8 lbf_mode[0x3];
8621
8622 u8 reserved_at_20[0x20];
8623 };
8624
8625 struct mlx5_ifc_pipg_reg_bits {
8626 u8 reserved_at_0[0x8];
8627 u8 local_port[0x8];
8628 u8 reserved_at_10[0x10];
8629
8630 u8 dic[0x1];
8631 u8 reserved_at_21[0x19];
8632 u8 ipg[0x4];
8633 u8 reserved_at_3e[0x2];
8634 };
8635
8636 struct mlx5_ifc_pifr_reg_bits {
8637 u8 reserved_at_0[0x8];
8638 u8 local_port[0x8];
8639 u8 reserved_at_10[0x10];
8640
8641 u8 reserved_at_20[0xe0];
8642
8643 u8 port_filter[8][0x20];
8644
8645 u8 port_filter_update_en[8][0x20];
8646 };
8647
8648 struct mlx5_ifc_pfcc_reg_bits {
8649 u8 reserved_at_0[0x8];
8650 u8 local_port[0x8];
8651 u8 reserved_at_10[0xb];
8652 u8 ppan_mask_n[0x1];
8653 u8 minor_stall_mask[0x1];
8654 u8 critical_stall_mask[0x1];
8655 u8 reserved_at_1e[0x2];
8656
8657 u8 ppan[0x4];
8658 u8 reserved_at_24[0x4];
8659 u8 prio_mask_tx[0x8];
8660 u8 reserved_at_30[0x8];
8661 u8 prio_mask_rx[0x8];
8662
8663 u8 pptx[0x1];
8664 u8 aptx[0x1];
8665 u8 pptx_mask_n[0x1];
8666 u8 reserved_at_43[0x5];
8667 u8 pfctx[0x8];
8668 u8 reserved_at_50[0x10];
8669
8670 u8 pprx[0x1];
8671 u8 aprx[0x1];
8672 u8 pprx_mask_n[0x1];
8673 u8 reserved_at_63[0x5];
8674 u8 pfcrx[0x8];
8675 u8 reserved_at_70[0x10];
8676
8677 u8 device_stall_minor_watermark[0x10];
8678 u8 device_stall_critical_watermark[0x10];
8679
8680 u8 reserved_at_a0[0x60];
8681 };
8682
8683 struct mlx5_ifc_pelc_reg_bits {
8684 u8 op[0x4];
8685 u8 reserved_at_4[0x4];
8686 u8 local_port[0x8];
8687 u8 reserved_at_10[0x10];
8688
8689 u8 op_admin[0x8];
8690 u8 op_capability[0x8];
8691 u8 op_request[0x8];
8692 u8 op_active[0x8];
8693
8694 u8 admin[0x40];
8695
8696 u8 capability[0x40];
8697
8698 u8 request[0x40];
8699
8700 u8 active[0x40];
8701
8702 u8 reserved_at_140[0x80];
8703 };
8704
8705 struct mlx5_ifc_peir_reg_bits {
8706 u8 reserved_at_0[0x8];
8707 u8 local_port[0x8];
8708 u8 reserved_at_10[0x10];
8709
8710 u8 reserved_at_20[0xc];
8711 u8 error_count[0x4];
8712 u8 reserved_at_30[0x10];
8713
8714 u8 reserved_at_40[0xc];
8715 u8 lane[0x4];
8716 u8 reserved_at_50[0x8];
8717 u8 error_type[0x8];
8718 };
8719
8720 struct mlx5_ifc_mpegc_reg_bits {
8721 u8 reserved_at_0[0x30];
8722 u8 field_select[0x10];
8723
8724 u8 tx_overflow_sense[0x1];
8725 u8 mark_cqe[0x1];
8726 u8 mark_cnp[0x1];
8727 u8 reserved_at_43[0x1b];
8728 u8 tx_lossy_overflow_oper[0x2];
8729
8730 u8 reserved_at_60[0x100];
8731 };
8732
8733 struct mlx5_ifc_pcam_enhanced_features_bits {
8734 u8 reserved_at_0[0x6d];
8735 u8 rx_icrc_encapsulated_counter[0x1];
8736 u8 reserved_at_6e[0x4];
8737 u8 ptys_extended_ethernet[0x1];
8738 u8 reserved_at_73[0x3];
8739 u8 pfcc_mask[0x1];
8740 u8 reserved_at_77[0x3];
8741 u8 per_lane_error_counters[0x1];
8742 u8 rx_buffer_fullness_counters[0x1];
8743 u8 ptys_connector_type[0x1];
8744 u8 reserved_at_7d[0x1];
8745 u8 ppcnt_discard_group[0x1];
8746 u8 ppcnt_statistical_group[0x1];
8747 };
8748
8749 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8750 u8 port_access_reg_cap_mask_127_to_96[0x20];
8751 u8 port_access_reg_cap_mask_95_to_64[0x20];
8752
8753 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8754 u8 pplm[0x1];
8755 u8 port_access_reg_cap_mask_34_to_32[0x3];
8756
8757 u8 port_access_reg_cap_mask_31_to_13[0x13];
8758 u8 pbmc[0x1];
8759 u8 pptb[0x1];
8760 u8 port_access_reg_cap_mask_10_to_09[0x2];
8761 u8 ppcnt[0x1];
8762 u8 port_access_reg_cap_mask_07_to_00[0x8];
8763 };
8764
8765 struct mlx5_ifc_pcam_reg_bits {
8766 u8 reserved_at_0[0x8];
8767 u8 feature_group[0x8];
8768 u8 reserved_at_10[0x8];
8769 u8 access_reg_group[0x8];
8770
8771 u8 reserved_at_20[0x20];
8772
8773 union {
8774 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8775 u8 reserved_at_0[0x80];
8776 } port_access_reg_cap_mask;
8777
8778 u8 reserved_at_c0[0x80];
8779
8780 union {
8781 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8782 u8 reserved_at_0[0x80];
8783 } feature_cap_mask;
8784
8785 u8 reserved_at_1c0[0xc0];
8786 };
8787
8788 struct mlx5_ifc_mcam_enhanced_features_bits {
8789 u8 reserved_at_0[0x6e];
8790 u8 pci_status_and_power[0x1];
8791 u8 reserved_at_6f[0x5];
8792 u8 mark_tx_action_cnp[0x1];
8793 u8 mark_tx_action_cqe[0x1];
8794 u8 dynamic_tx_overflow[0x1];
8795 u8 reserved_at_77[0x4];
8796 u8 pcie_outbound_stalled[0x1];
8797 u8 tx_overflow_buffer_pkt[0x1];
8798 u8 mtpps_enh_out_per_adj[0x1];
8799 u8 mtpps_fs[0x1];
8800 u8 pcie_performance_group[0x1];
8801 };
8802
8803 struct mlx5_ifc_mcam_access_reg_bits {
8804 u8 reserved_at_0[0x1c];
8805 u8 mcda[0x1];
8806 u8 mcc[0x1];
8807 u8 mcqi[0x1];
8808 u8 mcqs[0x1];
8809
8810 u8 regs_95_to_87[0x9];
8811 u8 mpegc[0x1];
8812 u8 regs_85_to_68[0x12];
8813 u8 tracer_registers[0x4];
8814
8815 u8 regs_63_to_32[0x20];
8816 u8 regs_31_to_0[0x20];
8817 };
8818
8819 struct mlx5_ifc_mcam_reg_bits {
8820 u8 reserved_at_0[0x8];
8821 u8 feature_group[0x8];
8822 u8 reserved_at_10[0x8];
8823 u8 access_reg_group[0x8];
8824
8825 u8 reserved_at_20[0x20];
8826
8827 union {
8828 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8829 u8 reserved_at_0[0x80];
8830 } mng_access_reg_cap_mask;
8831
8832 u8 reserved_at_c0[0x80];
8833
8834 union {
8835 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8836 u8 reserved_at_0[0x80];
8837 } mng_feature_cap_mask;
8838
8839 u8 reserved_at_1c0[0x80];
8840 };
8841
8842 struct mlx5_ifc_qcam_access_reg_cap_mask {
8843 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8844 u8 qpdpm[0x1];
8845 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8846 u8 qdpm[0x1];
8847 u8 qpts[0x1];
8848 u8 qcap[0x1];
8849 u8 qcam_access_reg_cap_mask_0[0x1];
8850 };
8851
8852 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8853 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8854 u8 qpts_trust_both[0x1];
8855 };
8856
8857 struct mlx5_ifc_qcam_reg_bits {
8858 u8 reserved_at_0[0x8];
8859 u8 feature_group[0x8];
8860 u8 reserved_at_10[0x8];
8861 u8 access_reg_group[0x8];
8862 u8 reserved_at_20[0x20];
8863
8864 union {
8865 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8866 u8 reserved_at_0[0x80];
8867 } qos_access_reg_cap_mask;
8868
8869 u8 reserved_at_c0[0x80];
8870
8871 union {
8872 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8873 u8 reserved_at_0[0x80];
8874 } qos_feature_cap_mask;
8875
8876 u8 reserved_at_1c0[0x80];
8877 };
8878
8879 struct mlx5_ifc_core_dump_reg_bits {
8880 u8 reserved_at_0[0x18];
8881 u8 core_dump_type[0x8];
8882
8883 u8 reserved_at_20[0x30];
8884 u8 vhca_id[0x10];
8885
8886 u8 reserved_at_60[0x8];
8887 u8 qpn[0x18];
8888 u8 reserved_at_80[0x180];
8889 };
8890
8891 struct mlx5_ifc_pcap_reg_bits {
8892 u8 reserved_at_0[0x8];
8893 u8 local_port[0x8];
8894 u8 reserved_at_10[0x10];
8895
8896 u8 port_capability_mask[4][0x20];
8897 };
8898
8899 struct mlx5_ifc_paos_reg_bits {
8900 u8 swid[0x8];
8901 u8 local_port[0x8];
8902 u8 reserved_at_10[0x4];
8903 u8 admin_status[0x4];
8904 u8 reserved_at_18[0x4];
8905 u8 oper_status[0x4];
8906
8907 u8 ase[0x1];
8908 u8 ee[0x1];
8909 u8 reserved_at_22[0x1c];
8910 u8 e[0x2];
8911
8912 u8 reserved_at_40[0x40];
8913 };
8914
8915 struct mlx5_ifc_pamp_reg_bits {
8916 u8 reserved_at_0[0x8];
8917 u8 opamp_group[0x8];
8918 u8 reserved_at_10[0xc];
8919 u8 opamp_group_type[0x4];
8920
8921 u8 start_index[0x10];
8922 u8 reserved_at_30[0x4];
8923 u8 num_of_indices[0xc];
8924
8925 u8 index_data[18][0x10];
8926 };
8927
8928 struct mlx5_ifc_pcmr_reg_bits {
8929 u8 reserved_at_0[0x8];
8930 u8 local_port[0x8];
8931 u8 reserved_at_10[0x10];
8932 u8 entropy_force_cap[0x1];
8933 u8 entropy_calc_cap[0x1];
8934 u8 entropy_gre_calc_cap[0x1];
8935 u8 reserved_at_23[0x1b];
8936 u8 fcs_cap[0x1];
8937 u8 reserved_at_3f[0x1];
8938 u8 entropy_force[0x1];
8939 u8 entropy_calc[0x1];
8940 u8 entropy_gre_calc[0x1];
8941 u8 reserved_at_43[0x1b];
8942 u8 fcs_chk[0x1];
8943 u8 reserved_at_5f[0x1];
8944 };
8945
8946 struct mlx5_ifc_lane_2_module_mapping_bits {
8947 u8 reserved_at_0[0x6];
8948 u8 rx_lane[0x2];
8949 u8 reserved_at_8[0x6];
8950 u8 tx_lane[0x2];
8951 u8 reserved_at_10[0x8];
8952 u8 module[0x8];
8953 };
8954
8955 struct mlx5_ifc_bufferx_reg_bits {
8956 u8 reserved_at_0[0x6];
8957 u8 lossy[0x1];
8958 u8 epsb[0x1];
8959 u8 reserved_at_8[0xc];
8960 u8 size[0xc];
8961
8962 u8 xoff_threshold[0x10];
8963 u8 xon_threshold[0x10];
8964 };
8965
8966 struct mlx5_ifc_set_node_in_bits {
8967 u8 node_description[64][0x8];
8968 };
8969
8970 struct mlx5_ifc_register_power_settings_bits {
8971 u8 reserved_at_0[0x18];
8972 u8 power_settings_level[0x8];
8973
8974 u8 reserved_at_20[0x60];
8975 };
8976
8977 struct mlx5_ifc_register_host_endianness_bits {
8978 u8 he[0x1];
8979 u8 reserved_at_1[0x1f];
8980
8981 u8 reserved_at_20[0x60];
8982 };
8983
8984 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8985 u8 reserved_at_0[0x20];
8986
8987 u8 mkey[0x20];
8988
8989 u8 addressh_63_32[0x20];
8990
8991 u8 addressl_31_0[0x20];
8992 };
8993
8994 struct mlx5_ifc_ud_adrs_vector_bits {
8995 u8 dc_key[0x40];
8996
8997 u8 ext[0x1];
8998 u8 reserved_at_41[0x7];
8999 u8 destination_qp_dct[0x18];
9000
9001 u8 static_rate[0x4];
9002 u8 sl_eth_prio[0x4];
9003 u8 fl[0x1];
9004 u8 mlid[0x7];
9005 u8 rlid_udp_sport[0x10];
9006
9007 u8 reserved_at_80[0x20];
9008
9009 u8 rmac_47_16[0x20];
9010
9011 u8 rmac_15_0[0x10];
9012 u8 tclass[0x8];
9013 u8 hop_limit[0x8];
9014
9015 u8 reserved_at_e0[0x1];
9016 u8 grh[0x1];
9017 u8 reserved_at_e2[0x2];
9018 u8 src_addr_index[0x8];
9019 u8 flow_label[0x14];
9020
9021 u8 rgid_rip[16][0x8];
9022 };
9023
9024 struct mlx5_ifc_pages_req_event_bits {
9025 u8 reserved_at_0[0x10];
9026 u8 function_id[0x10];
9027
9028 u8 num_pages[0x20];
9029
9030 u8 reserved_at_40[0xa0];
9031 };
9032
9033 struct mlx5_ifc_eqe_bits {
9034 u8 reserved_at_0[0x8];
9035 u8 event_type[0x8];
9036 u8 reserved_at_10[0x8];
9037 u8 event_sub_type[0x8];
9038
9039 u8 reserved_at_20[0xe0];
9040
9041 union mlx5_ifc_event_auto_bits event_data;
9042
9043 u8 reserved_at_1e0[0x10];
9044 u8 signature[0x8];
9045 u8 reserved_at_1f8[0x7];
9046 u8 owner[0x1];
9047 };
9048
9049 enum {
9050 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9051 };
9052
9053 struct mlx5_ifc_cmd_queue_entry_bits {
9054 u8 type[0x8];
9055 u8 reserved_at_8[0x18];
9056
9057 u8 input_length[0x20];
9058
9059 u8 input_mailbox_pointer_63_32[0x20];
9060
9061 u8 input_mailbox_pointer_31_9[0x17];
9062 u8 reserved_at_77[0x9];
9063
9064 u8 command_input_inline_data[16][0x8];
9065
9066 u8 command_output_inline_data[16][0x8];
9067
9068 u8 output_mailbox_pointer_63_32[0x20];
9069
9070 u8 output_mailbox_pointer_31_9[0x17];
9071 u8 reserved_at_1b7[0x9];
9072
9073 u8 output_length[0x20];
9074
9075 u8 token[0x8];
9076 u8 signature[0x8];
9077 u8 reserved_at_1f0[0x8];
9078 u8 status[0x7];
9079 u8 ownership[0x1];
9080 };
9081
9082 struct mlx5_ifc_cmd_out_bits {
9083 u8 status[0x8];
9084 u8 reserved_at_8[0x18];
9085
9086 u8 syndrome[0x20];
9087
9088 u8 command_output[0x20];
9089 };
9090
9091 struct mlx5_ifc_cmd_in_bits {
9092 u8 opcode[0x10];
9093 u8 reserved_at_10[0x10];
9094
9095 u8 reserved_at_20[0x10];
9096 u8 op_mod[0x10];
9097
9098 u8 command[0][0x20];
9099 };
9100
9101 struct mlx5_ifc_cmd_if_box_bits {
9102 u8 mailbox_data[512][0x8];
9103
9104 u8 reserved_at_1000[0x180];
9105
9106 u8 next_pointer_63_32[0x20];
9107
9108 u8 next_pointer_31_10[0x16];
9109 u8 reserved_at_11b6[0xa];
9110
9111 u8 block_number[0x20];
9112
9113 u8 reserved_at_11e0[0x8];
9114 u8 token[0x8];
9115 u8 ctrl_signature[0x8];
9116 u8 signature[0x8];
9117 };
9118
9119 struct mlx5_ifc_mtt_bits {
9120 u8 ptag_63_32[0x20];
9121
9122 u8 ptag_31_8[0x18];
9123 u8 reserved_at_38[0x6];
9124 u8 wr_en[0x1];
9125 u8 rd_en[0x1];
9126 };
9127
9128 struct mlx5_ifc_query_wol_rol_out_bits {
9129 u8 status[0x8];
9130 u8 reserved_at_8[0x18];
9131
9132 u8 syndrome[0x20];
9133
9134 u8 reserved_at_40[0x10];
9135 u8 rol_mode[0x8];
9136 u8 wol_mode[0x8];
9137
9138 u8 reserved_at_60[0x20];
9139 };
9140
9141 struct mlx5_ifc_query_wol_rol_in_bits {
9142 u8 opcode[0x10];
9143 u8 reserved_at_10[0x10];
9144
9145 u8 reserved_at_20[0x10];
9146 u8 op_mod[0x10];
9147
9148 u8 reserved_at_40[0x40];
9149 };
9150
9151 struct mlx5_ifc_set_wol_rol_out_bits {
9152 u8 status[0x8];
9153 u8 reserved_at_8[0x18];
9154
9155 u8 syndrome[0x20];
9156
9157 u8 reserved_at_40[0x40];
9158 };
9159
9160 struct mlx5_ifc_set_wol_rol_in_bits {
9161 u8 opcode[0x10];
9162 u8 reserved_at_10[0x10];
9163
9164 u8 reserved_at_20[0x10];
9165 u8 op_mod[0x10];
9166
9167 u8 rol_mode_valid[0x1];
9168 u8 wol_mode_valid[0x1];
9169 u8 reserved_at_42[0xe];
9170 u8 rol_mode[0x8];
9171 u8 wol_mode[0x8];
9172
9173 u8 reserved_at_60[0x20];
9174 };
9175
9176 enum {
9177 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9178 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9179 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9180 };
9181
9182 enum {
9183 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9184 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9185 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9186 };
9187
9188 enum {
9189 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9190 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9191 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9192 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9193 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9194 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9195 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9196 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9197 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9198 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9199 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9200 };
9201
9202 struct mlx5_ifc_initial_seg_bits {
9203 u8 fw_rev_minor[0x10];
9204 u8 fw_rev_major[0x10];
9205
9206 u8 cmd_interface_rev[0x10];
9207 u8 fw_rev_subminor[0x10];
9208
9209 u8 reserved_at_40[0x40];
9210
9211 u8 cmdq_phy_addr_63_32[0x20];
9212
9213 u8 cmdq_phy_addr_31_12[0x14];
9214 u8 reserved_at_b4[0x2];
9215 u8 nic_interface[0x2];
9216 u8 log_cmdq_size[0x4];
9217 u8 log_cmdq_stride[0x4];
9218
9219 u8 command_doorbell_vector[0x20];
9220
9221 u8 reserved_at_e0[0xf00];
9222
9223 u8 initializing[0x1];
9224 u8 reserved_at_fe1[0x4];
9225 u8 nic_interface_supported[0x3];
9226 u8 embedded_cpu[0x1];
9227 u8 reserved_at_fe9[0x17];
9228
9229 struct mlx5_ifc_health_buffer_bits health_buffer;
9230
9231 u8 no_dram_nic_offset[0x20];
9232
9233 u8 reserved_at_1220[0x6e40];
9234
9235 u8 reserved_at_8060[0x1f];
9236 u8 clear_int[0x1];
9237
9238 u8 health_syndrome[0x8];
9239 u8 health_counter[0x18];
9240
9241 u8 reserved_at_80a0[0x17fc0];
9242 };
9243
9244 struct mlx5_ifc_mtpps_reg_bits {
9245 u8 reserved_at_0[0xc];
9246 u8 cap_number_of_pps_pins[0x4];
9247 u8 reserved_at_10[0x4];
9248 u8 cap_max_num_of_pps_in_pins[0x4];
9249 u8 reserved_at_18[0x4];
9250 u8 cap_max_num_of_pps_out_pins[0x4];
9251
9252 u8 reserved_at_20[0x24];
9253 u8 cap_pin_3_mode[0x4];
9254 u8 reserved_at_48[0x4];
9255 u8 cap_pin_2_mode[0x4];
9256 u8 reserved_at_50[0x4];
9257 u8 cap_pin_1_mode[0x4];
9258 u8 reserved_at_58[0x4];
9259 u8 cap_pin_0_mode[0x4];
9260
9261 u8 reserved_at_60[0x4];
9262 u8 cap_pin_7_mode[0x4];
9263 u8 reserved_at_68[0x4];
9264 u8 cap_pin_6_mode[0x4];
9265 u8 reserved_at_70[0x4];
9266 u8 cap_pin_5_mode[0x4];
9267 u8 reserved_at_78[0x4];
9268 u8 cap_pin_4_mode[0x4];
9269
9270 u8 field_select[0x20];
9271 u8 reserved_at_a0[0x60];
9272
9273 u8 enable[0x1];
9274 u8 reserved_at_101[0xb];
9275 u8 pattern[0x4];
9276 u8 reserved_at_110[0x4];
9277 u8 pin_mode[0x4];
9278 u8 pin[0x8];
9279
9280 u8 reserved_at_120[0x20];
9281
9282 u8 time_stamp[0x40];
9283
9284 u8 out_pulse_duration[0x10];
9285 u8 out_periodic_adjustment[0x10];
9286 u8 enhanced_out_periodic_adjustment[0x20];
9287
9288 u8 reserved_at_1c0[0x20];
9289 };
9290
9291 struct mlx5_ifc_mtppse_reg_bits {
9292 u8 reserved_at_0[0x18];
9293 u8 pin[0x8];
9294 u8 event_arm[0x1];
9295 u8 reserved_at_21[0x1b];
9296 u8 event_generation_mode[0x4];
9297 u8 reserved_at_40[0x40];
9298 };
9299
9300 struct mlx5_ifc_mcqs_reg_bits {
9301 u8 last_index_flag[0x1];
9302 u8 reserved_at_1[0x7];
9303 u8 fw_device[0x8];
9304 u8 component_index[0x10];
9305
9306 u8 reserved_at_20[0x10];
9307 u8 identifier[0x10];
9308
9309 u8 reserved_at_40[0x17];
9310 u8 component_status[0x5];
9311 u8 component_update_state[0x4];
9312
9313 u8 last_update_state_changer_type[0x4];
9314 u8 last_update_state_changer_host_id[0x4];
9315 u8 reserved_at_68[0x18];
9316 };
9317
9318 struct mlx5_ifc_mcqi_cap_bits {
9319 u8 supported_info_bitmask[0x20];
9320
9321 u8 component_size[0x20];
9322
9323 u8 max_component_size[0x20];
9324
9325 u8 log_mcda_word_size[0x4];
9326 u8 reserved_at_64[0xc];
9327 u8 mcda_max_write_size[0x10];
9328
9329 u8 rd_en[0x1];
9330 u8 reserved_at_81[0x1];
9331 u8 match_chip_id[0x1];
9332 u8 match_psid[0x1];
9333 u8 check_user_timestamp[0x1];
9334 u8 match_base_guid_mac[0x1];
9335 u8 reserved_at_86[0x1a];
9336 };
9337
9338 struct mlx5_ifc_mcqi_version_bits {
9339 u8 reserved_at_0[0x2];
9340 u8 build_time_valid[0x1];
9341 u8 user_defined_time_valid[0x1];
9342 u8 reserved_at_4[0x14];
9343 u8 version_string_length[0x8];
9344
9345 u8 version[0x20];
9346
9347 u8 build_time[0x40];
9348
9349 u8 user_defined_time[0x40];
9350
9351 u8 build_tool_version[0x20];
9352
9353 u8 reserved_at_e0[0x20];
9354
9355 u8 version_string[92][0x8];
9356 };
9357
9358 struct mlx5_ifc_mcqi_activation_method_bits {
9359 u8 pending_server_ac_power_cycle[0x1];
9360 u8 pending_server_dc_power_cycle[0x1];
9361 u8 pending_server_reboot[0x1];
9362 u8 pending_fw_reset[0x1];
9363 u8 auto_activate[0x1];
9364 u8 all_hosts_sync[0x1];
9365 u8 device_hw_reset[0x1];
9366 u8 reserved_at_7[0x19];
9367 };
9368
9369 union mlx5_ifc_mcqi_reg_data_bits {
9370 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9371 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9372 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9373 };
9374
9375 struct mlx5_ifc_mcqi_reg_bits {
9376 u8 read_pending_component[0x1];
9377 u8 reserved_at_1[0xf];
9378 u8 component_index[0x10];
9379
9380 u8 reserved_at_20[0x20];
9381
9382 u8 reserved_at_40[0x1b];
9383 u8 info_type[0x5];
9384
9385 u8 info_size[0x20];
9386
9387 u8 offset[0x20];
9388
9389 u8 reserved_at_a0[0x10];
9390 u8 data_size[0x10];
9391
9392 union mlx5_ifc_mcqi_reg_data_bits data[0];
9393 };
9394
9395 struct mlx5_ifc_mcc_reg_bits {
9396 u8 reserved_at_0[0x4];
9397 u8 time_elapsed_since_last_cmd[0xc];
9398 u8 reserved_at_10[0x8];
9399 u8 instruction[0x8];
9400
9401 u8 reserved_at_20[0x10];
9402 u8 component_index[0x10];
9403
9404 u8 reserved_at_40[0x8];
9405 u8 update_handle[0x18];
9406
9407 u8 handle_owner_type[0x4];
9408 u8 handle_owner_host_id[0x4];
9409 u8 reserved_at_68[0x1];
9410 u8 control_progress[0x7];
9411 u8 error_code[0x8];
9412 u8 reserved_at_78[0x4];
9413 u8 control_state[0x4];
9414
9415 u8 component_size[0x20];
9416
9417 u8 reserved_at_a0[0x60];
9418 };
9419
9420 struct mlx5_ifc_mcda_reg_bits {
9421 u8 reserved_at_0[0x8];
9422 u8 update_handle[0x18];
9423
9424 u8 offset[0x20];
9425
9426 u8 reserved_at_40[0x10];
9427 u8 size[0x10];
9428
9429 u8 reserved_at_60[0x20];
9430
9431 u8 data[0][0x20];
9432 };
9433
9434 union mlx5_ifc_ports_control_registers_document_bits {
9435 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9436 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9437 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9438 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9439 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9440 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9441 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9442 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9443 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9444 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9445 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9446 struct mlx5_ifc_paos_reg_bits paos_reg;
9447 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9448 struct mlx5_ifc_peir_reg_bits peir_reg;
9449 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9450 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9451 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9452 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9453 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9454 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9455 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9456 struct mlx5_ifc_plib_reg_bits plib_reg;
9457 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9458 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9459 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9460 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9461 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9462 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9463 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9464 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9465 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9466 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9467 struct mlx5_ifc_mpein_reg_bits mpein_reg;
9468 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9469 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9470 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9471 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9472 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9473 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9474 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9475 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9476 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9477 struct mlx5_ifc_pude_reg_bits pude_reg;
9478 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9479 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9480 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9481 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9482 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9483 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9484 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9485 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9486 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9487 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9488 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9489 u8 reserved_at_0[0x60e0];
9490 };
9491
9492 union mlx5_ifc_debug_enhancements_document_bits {
9493 struct mlx5_ifc_health_buffer_bits health_buffer;
9494 u8 reserved_at_0[0x200];
9495 };
9496
9497 union mlx5_ifc_uplink_pci_interface_document_bits {
9498 struct mlx5_ifc_initial_seg_bits initial_seg;
9499 u8 reserved_at_0[0x20060];
9500 };
9501
9502 struct mlx5_ifc_set_flow_table_root_out_bits {
9503 u8 status[0x8];
9504 u8 reserved_at_8[0x18];
9505
9506 u8 syndrome[0x20];
9507
9508 u8 reserved_at_40[0x40];
9509 };
9510
9511 struct mlx5_ifc_set_flow_table_root_in_bits {
9512 u8 opcode[0x10];
9513 u8 reserved_at_10[0x10];
9514
9515 u8 reserved_at_20[0x10];
9516 u8 op_mod[0x10];
9517
9518 u8 other_vport[0x1];
9519 u8 reserved_at_41[0xf];
9520 u8 vport_number[0x10];
9521
9522 u8 reserved_at_60[0x20];
9523
9524 u8 table_type[0x8];
9525 u8 reserved_at_88[0x18];
9526
9527 u8 reserved_at_a0[0x8];
9528 u8 table_id[0x18];
9529
9530 u8 reserved_at_c0[0x8];
9531 u8 underlay_qpn[0x18];
9532 u8 reserved_at_e0[0x120];
9533 };
9534
9535 enum {
9536 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9537 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9538 };
9539
9540 struct mlx5_ifc_modify_flow_table_out_bits {
9541 u8 status[0x8];
9542 u8 reserved_at_8[0x18];
9543
9544 u8 syndrome[0x20];
9545
9546 u8 reserved_at_40[0x40];
9547 };
9548
9549 struct mlx5_ifc_modify_flow_table_in_bits {
9550 u8 opcode[0x10];
9551 u8 reserved_at_10[0x10];
9552
9553 u8 reserved_at_20[0x10];
9554 u8 op_mod[0x10];
9555
9556 u8 other_vport[0x1];
9557 u8 reserved_at_41[0xf];
9558 u8 vport_number[0x10];
9559
9560 u8 reserved_at_60[0x10];
9561 u8 modify_field_select[0x10];
9562
9563 u8 table_type[0x8];
9564 u8 reserved_at_88[0x18];
9565
9566 u8 reserved_at_a0[0x8];
9567 u8 table_id[0x18];
9568
9569 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9570 };
9571
9572 struct mlx5_ifc_ets_tcn_config_reg_bits {
9573 u8 g[0x1];
9574 u8 b[0x1];
9575 u8 r[0x1];
9576 u8 reserved_at_3[0x9];
9577 u8 group[0x4];
9578 u8 reserved_at_10[0x9];
9579 u8 bw_allocation[0x7];
9580
9581 u8 reserved_at_20[0xc];
9582 u8 max_bw_units[0x4];
9583 u8 reserved_at_30[0x8];
9584 u8 max_bw_value[0x8];
9585 };
9586
9587 struct mlx5_ifc_ets_global_config_reg_bits {
9588 u8 reserved_at_0[0x2];
9589 u8 r[0x1];
9590 u8 reserved_at_3[0x1d];
9591
9592 u8 reserved_at_20[0xc];
9593 u8 max_bw_units[0x4];
9594 u8 reserved_at_30[0x8];
9595 u8 max_bw_value[0x8];
9596 };
9597
9598 struct mlx5_ifc_qetc_reg_bits {
9599 u8 reserved_at_0[0x8];
9600 u8 port_number[0x8];
9601 u8 reserved_at_10[0x30];
9602
9603 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9604 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9605 };
9606
9607 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9608 u8 e[0x1];
9609 u8 reserved_at_01[0x0b];
9610 u8 prio[0x04];
9611 };
9612
9613 struct mlx5_ifc_qpdpm_reg_bits {
9614 u8 reserved_at_0[0x8];
9615 u8 local_port[0x8];
9616 u8 reserved_at_10[0x10];
9617 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9618 };
9619
9620 struct mlx5_ifc_qpts_reg_bits {
9621 u8 reserved_at_0[0x8];
9622 u8 local_port[0x8];
9623 u8 reserved_at_10[0x2d];
9624 u8 trust_state[0x3];
9625 };
9626
9627 struct mlx5_ifc_pptb_reg_bits {
9628 u8 reserved_at_0[0x2];
9629 u8 mm[0x2];
9630 u8 reserved_at_4[0x4];
9631 u8 local_port[0x8];
9632 u8 reserved_at_10[0x6];
9633 u8 cm[0x1];
9634 u8 um[0x1];
9635 u8 pm[0x8];
9636
9637 u8 prio_x_buff[0x20];
9638
9639 u8 pm_msb[0x8];
9640 u8 reserved_at_48[0x10];
9641 u8 ctrl_buff[0x4];
9642 u8 untagged_buff[0x4];
9643 };
9644
9645 struct mlx5_ifc_pbmc_reg_bits {
9646 u8 reserved_at_0[0x8];
9647 u8 local_port[0x8];
9648 u8 reserved_at_10[0x10];
9649
9650 u8 xoff_timer_value[0x10];
9651 u8 xoff_refresh[0x10];
9652
9653 u8 reserved_at_40[0x9];
9654 u8 fullness_threshold[0x7];
9655 u8 port_buffer_size[0x10];
9656
9657 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9658
9659 u8 reserved_at_2e0[0x40];
9660 };
9661
9662 struct mlx5_ifc_qtct_reg_bits {
9663 u8 reserved_at_0[0x8];
9664 u8 port_number[0x8];
9665 u8 reserved_at_10[0xd];
9666 u8 prio[0x3];
9667
9668 u8 reserved_at_20[0x1d];
9669 u8 tclass[0x3];
9670 };
9671
9672 struct mlx5_ifc_mcia_reg_bits {
9673 u8 l[0x1];
9674 u8 reserved_at_1[0x7];
9675 u8 module[0x8];
9676 u8 reserved_at_10[0x8];
9677 u8 status[0x8];
9678
9679 u8 i2c_device_address[0x8];
9680 u8 page_number[0x8];
9681 u8 device_address[0x10];
9682
9683 u8 reserved_at_40[0x10];
9684 u8 size[0x10];
9685
9686 u8 reserved_at_60[0x20];
9687
9688 u8 dword_0[0x20];
9689 u8 dword_1[0x20];
9690 u8 dword_2[0x20];
9691 u8 dword_3[0x20];
9692 u8 dword_4[0x20];
9693 u8 dword_5[0x20];
9694 u8 dword_6[0x20];
9695 u8 dword_7[0x20];
9696 u8 dword_8[0x20];
9697 u8 dword_9[0x20];
9698 u8 dword_10[0x20];
9699 u8 dword_11[0x20];
9700 };
9701
9702 struct mlx5_ifc_dcbx_param_bits {
9703 u8 dcbx_cee_cap[0x1];
9704 u8 dcbx_ieee_cap[0x1];
9705 u8 dcbx_standby_cap[0x1];
9706 u8 reserved_at_3[0x5];
9707 u8 port_number[0x8];
9708 u8 reserved_at_10[0xa];
9709 u8 max_application_table_size[6];
9710 u8 reserved_at_20[0x15];
9711 u8 version_oper[0x3];
9712 u8 reserved_at_38[5];
9713 u8 version_admin[0x3];
9714 u8 willing_admin[0x1];
9715 u8 reserved_at_41[0x3];
9716 u8 pfc_cap_oper[0x4];
9717 u8 reserved_at_48[0x4];
9718 u8 pfc_cap_admin[0x4];
9719 u8 reserved_at_50[0x4];
9720 u8 num_of_tc_oper[0x4];
9721 u8 reserved_at_58[0x4];
9722 u8 num_of_tc_admin[0x4];
9723 u8 remote_willing[0x1];
9724 u8 reserved_at_61[3];
9725 u8 remote_pfc_cap[4];
9726 u8 reserved_at_68[0x14];
9727 u8 remote_num_of_tc[0x4];
9728 u8 reserved_at_80[0x18];
9729 u8 error[0x8];
9730 u8 reserved_at_a0[0x160];
9731 };
9732
9733 struct mlx5_ifc_lagc_bits {
9734 u8 reserved_at_0[0x1d];
9735 u8 lag_state[0x3];
9736
9737 u8 reserved_at_20[0x14];
9738 u8 tx_remap_affinity_2[0x4];
9739 u8 reserved_at_38[0x4];
9740 u8 tx_remap_affinity_1[0x4];
9741 };
9742
9743 struct mlx5_ifc_create_lag_out_bits {
9744 u8 status[0x8];
9745 u8 reserved_at_8[0x18];
9746
9747 u8 syndrome[0x20];
9748
9749 u8 reserved_at_40[0x40];
9750 };
9751
9752 struct mlx5_ifc_create_lag_in_bits {
9753 u8 opcode[0x10];
9754 u8 reserved_at_10[0x10];
9755
9756 u8 reserved_at_20[0x10];
9757 u8 op_mod[0x10];
9758
9759 struct mlx5_ifc_lagc_bits ctx;
9760 };
9761
9762 struct mlx5_ifc_modify_lag_out_bits {
9763 u8 status[0x8];
9764 u8 reserved_at_8[0x18];
9765
9766 u8 syndrome[0x20];
9767
9768 u8 reserved_at_40[0x40];
9769 };
9770
9771 struct mlx5_ifc_modify_lag_in_bits {
9772 u8 opcode[0x10];
9773 u8 reserved_at_10[0x10];
9774
9775 u8 reserved_at_20[0x10];
9776 u8 op_mod[0x10];
9777
9778 u8 reserved_at_40[0x20];
9779 u8 field_select[0x20];
9780
9781 struct mlx5_ifc_lagc_bits ctx;
9782 };
9783
9784 struct mlx5_ifc_query_lag_out_bits {
9785 u8 status[0x8];
9786 u8 reserved_at_8[0x18];
9787
9788 u8 syndrome[0x20];
9789
9790 struct mlx5_ifc_lagc_bits ctx;
9791 };
9792
9793 struct mlx5_ifc_query_lag_in_bits {
9794 u8 opcode[0x10];
9795 u8 reserved_at_10[0x10];
9796
9797 u8 reserved_at_20[0x10];
9798 u8 op_mod[0x10];
9799
9800 u8 reserved_at_40[0x40];
9801 };
9802
9803 struct mlx5_ifc_destroy_lag_out_bits {
9804 u8 status[0x8];
9805 u8 reserved_at_8[0x18];
9806
9807 u8 syndrome[0x20];
9808
9809 u8 reserved_at_40[0x40];
9810 };
9811
9812 struct mlx5_ifc_destroy_lag_in_bits {
9813 u8 opcode[0x10];
9814 u8 reserved_at_10[0x10];
9815
9816 u8 reserved_at_20[0x10];
9817 u8 op_mod[0x10];
9818
9819 u8 reserved_at_40[0x40];
9820 };
9821
9822 struct mlx5_ifc_create_vport_lag_out_bits {
9823 u8 status[0x8];
9824 u8 reserved_at_8[0x18];
9825
9826 u8 syndrome[0x20];
9827
9828 u8 reserved_at_40[0x40];
9829 };
9830
9831 struct mlx5_ifc_create_vport_lag_in_bits {
9832 u8 opcode[0x10];
9833 u8 reserved_at_10[0x10];
9834
9835 u8 reserved_at_20[0x10];
9836 u8 op_mod[0x10];
9837
9838 u8 reserved_at_40[0x40];
9839 };
9840
9841 struct mlx5_ifc_destroy_vport_lag_out_bits {
9842 u8 status[0x8];
9843 u8 reserved_at_8[0x18];
9844
9845 u8 syndrome[0x20];
9846
9847 u8 reserved_at_40[0x40];
9848 };
9849
9850 struct mlx5_ifc_destroy_vport_lag_in_bits {
9851 u8 opcode[0x10];
9852 u8 reserved_at_10[0x10];
9853
9854 u8 reserved_at_20[0x10];
9855 u8 op_mod[0x10];
9856
9857 u8 reserved_at_40[0x40];
9858 };
9859
9860 struct mlx5_ifc_alloc_memic_in_bits {
9861 u8 opcode[0x10];
9862 u8 reserved_at_10[0x10];
9863
9864 u8 reserved_at_20[0x10];
9865 u8 op_mod[0x10];
9866
9867 u8 reserved_at_30[0x20];
9868
9869 u8 reserved_at_40[0x18];
9870 u8 log_memic_addr_alignment[0x8];
9871
9872 u8 range_start_addr[0x40];
9873
9874 u8 range_size[0x20];
9875
9876 u8 memic_size[0x20];
9877 };
9878
9879 struct mlx5_ifc_alloc_memic_out_bits {
9880 u8 status[0x8];
9881 u8 reserved_at_8[0x18];
9882
9883 u8 syndrome[0x20];
9884
9885 u8 memic_start_addr[0x40];
9886 };
9887
9888 struct mlx5_ifc_dealloc_memic_in_bits {
9889 u8 opcode[0x10];
9890 u8 reserved_at_10[0x10];
9891
9892 u8 reserved_at_20[0x10];
9893 u8 op_mod[0x10];
9894
9895 u8 reserved_at_40[0x40];
9896
9897 u8 memic_start_addr[0x40];
9898
9899 u8 memic_size[0x20];
9900
9901 u8 reserved_at_e0[0x20];
9902 };
9903
9904 struct mlx5_ifc_dealloc_memic_out_bits {
9905 u8 status[0x8];
9906 u8 reserved_at_8[0x18];
9907
9908 u8 syndrome[0x20];
9909
9910 u8 reserved_at_40[0x40];
9911 };
9912
9913 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9914 u8 opcode[0x10];
9915 u8 uid[0x10];
9916
9917 u8 vhca_tunnel_id[0x10];
9918 u8 obj_type[0x10];
9919
9920 u8 obj_id[0x20];
9921
9922 u8 reserved_at_60[0x20];
9923 };
9924
9925 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9926 u8 status[0x8];
9927 u8 reserved_at_8[0x18];
9928
9929 u8 syndrome[0x20];
9930
9931 u8 obj_id[0x20];
9932
9933 u8 reserved_at_60[0x20];
9934 };
9935
9936 struct mlx5_ifc_umem_bits {
9937 u8 reserved_at_0[0x80];
9938
9939 u8 reserved_at_80[0x1b];
9940 u8 log_page_size[0x5];
9941
9942 u8 page_offset[0x20];
9943
9944 u8 num_of_mtt[0x40];
9945
9946 struct mlx5_ifc_mtt_bits mtt[0];
9947 };
9948
9949 struct mlx5_ifc_uctx_bits {
9950 u8 cap[0x20];
9951
9952 u8 reserved_at_20[0x160];
9953 };
9954
9955 struct mlx5_ifc_sw_icm_bits {
9956 u8 modify_field_select[0x40];
9957
9958 u8 reserved_at_40[0x18];
9959 u8 log_sw_icm_size[0x8];
9960
9961 u8 reserved_at_60[0x20];
9962
9963 u8 sw_icm_start_addr[0x40];
9964
9965 u8 reserved_at_c0[0x140];
9966 };
9967
9968 struct mlx5_ifc_geneve_tlv_option_bits {
9969 u8 modify_field_select[0x40];
9970
9971 u8 reserved_at_40[0x18];
9972 u8 geneve_option_fte_index[0x8];
9973
9974 u8 option_class[0x10];
9975 u8 option_type[0x8];
9976 u8 reserved_at_78[0x3];
9977 u8 option_data_length[0x5];
9978
9979 u8 reserved_at_80[0x180];
9980 };
9981
9982 struct mlx5_ifc_create_umem_in_bits {
9983 u8 opcode[0x10];
9984 u8 uid[0x10];
9985
9986 u8 reserved_at_20[0x10];
9987 u8 op_mod[0x10];
9988
9989 u8 reserved_at_40[0x40];
9990
9991 struct mlx5_ifc_umem_bits umem;
9992 };
9993
9994 struct mlx5_ifc_create_uctx_in_bits {
9995 u8 opcode[0x10];
9996 u8 reserved_at_10[0x10];
9997
9998 u8 reserved_at_20[0x10];
9999 u8 op_mod[0x10];
10000
10001 u8 reserved_at_40[0x40];
10002
10003 struct mlx5_ifc_uctx_bits uctx;
10004 };
10005
10006 struct mlx5_ifc_destroy_uctx_in_bits {
10007 u8 opcode[0x10];
10008 u8 reserved_at_10[0x10];
10009
10010 u8 reserved_at_20[0x10];
10011 u8 op_mod[0x10];
10012
10013 u8 reserved_at_40[0x10];
10014 u8 uid[0x10];
10015
10016 u8 reserved_at_60[0x20];
10017 };
10018
10019 struct mlx5_ifc_create_sw_icm_in_bits {
10020 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10021 struct mlx5_ifc_sw_icm_bits sw_icm;
10022 };
10023
10024 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10025 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10026 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
10027 };
10028
10029 struct mlx5_ifc_mtrc_string_db_param_bits {
10030 u8 string_db_base_address[0x20];
10031
10032 u8 reserved_at_20[0x8];
10033 u8 string_db_size[0x18];
10034 };
10035
10036 struct mlx5_ifc_mtrc_cap_bits {
10037 u8 trace_owner[0x1];
10038 u8 trace_to_memory[0x1];
10039 u8 reserved_at_2[0x4];
10040 u8 trc_ver[0x2];
10041 u8 reserved_at_8[0x14];
10042 u8 num_string_db[0x4];
10043
10044 u8 first_string_trace[0x8];
10045 u8 num_string_trace[0x8];
10046 u8 reserved_at_30[0x28];
10047
10048 u8 log_max_trace_buffer_size[0x8];
10049
10050 u8 reserved_at_60[0x20];
10051
10052 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10053
10054 u8 reserved_at_280[0x180];
10055 };
10056
10057 struct mlx5_ifc_mtrc_conf_bits {
10058 u8 reserved_at_0[0x1c];
10059 u8 trace_mode[0x4];
10060 u8 reserved_at_20[0x18];
10061 u8 log_trace_buffer_size[0x8];
10062 u8 trace_mkey[0x20];
10063 u8 reserved_at_60[0x3a0];
10064 };
10065
10066 struct mlx5_ifc_mtrc_stdb_bits {
10067 u8 string_db_index[0x4];
10068 u8 reserved_at_4[0x4];
10069 u8 read_size[0x18];
10070 u8 start_offset[0x20];
10071 u8 string_db_data[0];
10072 };
10073
10074 struct mlx5_ifc_mtrc_ctrl_bits {
10075 u8 trace_status[0x2];
10076 u8 reserved_at_2[0x2];
10077 u8 arm_event[0x1];
10078 u8 reserved_at_5[0xb];
10079 u8 modify_field_select[0x10];
10080 u8 reserved_at_20[0x2b];
10081 u8 current_timestamp52_32[0x15];
10082 u8 current_timestamp31_0[0x20];
10083 u8 reserved_at_80[0x180];
10084 };
10085
10086 struct mlx5_ifc_host_params_context_bits {
10087 u8 host_number[0x8];
10088 u8 reserved_at_8[0x7];
10089 u8 host_pf_disabled[0x1];
10090 u8 host_num_of_vfs[0x10];
10091
10092 u8 host_total_vfs[0x10];
10093 u8 host_pci_bus[0x10];
10094
10095 u8 reserved_at_40[0x10];
10096 u8 host_pci_device[0x10];
10097
10098 u8 reserved_at_60[0x10];
10099 u8 host_pci_function[0x10];
10100
10101 u8 reserved_at_80[0x180];
10102 };
10103
10104 struct mlx5_ifc_query_esw_functions_in_bits {
10105 u8 opcode[0x10];
10106 u8 reserved_at_10[0x10];
10107
10108 u8 reserved_at_20[0x10];
10109 u8 op_mod[0x10];
10110
10111 u8 reserved_at_40[0x40];
10112 };
10113
10114 struct mlx5_ifc_query_esw_functions_out_bits {
10115 u8 status[0x8];
10116 u8 reserved_at_8[0x18];
10117
10118 u8 syndrome[0x20];
10119
10120 u8 reserved_at_40[0x40];
10121
10122 struct mlx5_ifc_host_params_context_bits host_params_context;
10123
10124 u8 reserved_at_280[0x180];
10125 u8 host_sf_enable[0][0x40];
10126 };
10127
10128 struct mlx5_ifc_sf_partition_bits {
10129 u8 reserved_at_0[0x10];
10130 u8 log_num_sf[0x8];
10131 u8 log_sf_bar_size[0x8];
10132 };
10133
10134 struct mlx5_ifc_query_sf_partitions_out_bits {
10135 u8 status[0x8];
10136 u8 reserved_at_8[0x18];
10137
10138 u8 syndrome[0x20];
10139
10140 u8 reserved_at_40[0x18];
10141 u8 num_sf_partitions[0x8];
10142
10143 u8 reserved_at_60[0x20];
10144
10145 struct mlx5_ifc_sf_partition_bits sf_partition[0];
10146 };
10147
10148 struct mlx5_ifc_query_sf_partitions_in_bits {
10149 u8 opcode[0x10];
10150 u8 reserved_at_10[0x10];
10151
10152 u8 reserved_at_20[0x10];
10153 u8 op_mod[0x10];
10154
10155 u8 reserved_at_40[0x40];
10156 };
10157
10158 struct mlx5_ifc_dealloc_sf_out_bits {
10159 u8 status[0x8];
10160 u8 reserved_at_8[0x18];
10161
10162 u8 syndrome[0x20];
10163
10164 u8 reserved_at_40[0x40];
10165 };
10166
10167 struct mlx5_ifc_dealloc_sf_in_bits {
10168 u8 opcode[0x10];
10169 u8 reserved_at_10[0x10];
10170
10171 u8 reserved_at_20[0x10];
10172 u8 op_mod[0x10];
10173
10174 u8 reserved_at_40[0x10];
10175 u8 function_id[0x10];
10176
10177 u8 reserved_at_60[0x20];
10178 };
10179
10180 struct mlx5_ifc_alloc_sf_out_bits {
10181 u8 status[0x8];
10182 u8 reserved_at_8[0x18];
10183
10184 u8 syndrome[0x20];
10185
10186 u8 reserved_at_40[0x40];
10187 };
10188
10189 struct mlx5_ifc_alloc_sf_in_bits {
10190 u8 opcode[0x10];
10191 u8 reserved_at_10[0x10];
10192
10193 u8 reserved_at_20[0x10];
10194 u8 op_mod[0x10];
10195
10196 u8 reserved_at_40[0x10];
10197 u8 function_id[0x10];
10198
10199 u8 reserved_at_60[0x20];
10200 };
10201
10202 struct mlx5_ifc_affiliated_event_header_bits {
10203 u8 reserved_at_0[0x10];
10204 u8 obj_type[0x10];
10205
10206 u8 obj_id[0x20];
10207 };
10208
10209 enum {
10210 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10211 };
10212
10213 enum {
10214 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10215 };
10216
10217 struct mlx5_ifc_encryption_key_obj_bits {
10218 u8 modify_field_select[0x40];
10219
10220 u8 reserved_at_40[0x14];
10221 u8 key_size[0x4];
10222 u8 reserved_at_58[0x4];
10223 u8 key_type[0x4];
10224
10225 u8 reserved_at_60[0x8];
10226 u8 pd[0x18];
10227
10228 u8 reserved_at_80[0x180];
10229 u8 key[8][0x20];
10230
10231 u8 reserved_at_300[0x500];
10232 };
10233
10234 struct mlx5_ifc_create_encryption_key_in_bits {
10235 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10236 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10237 };
10238
10239 enum {
10240 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10241 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10242 };
10243
10244 enum {
10245 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10246 };
10247
10248 struct mlx5_ifc_tls_static_params_bits {
10249 u8 const_2[0x2];
10250 u8 tls_version[0x4];
10251 u8 const_1[0x2];
10252 u8 reserved_at_8[0x14];
10253 u8 encryption_standard[0x4];
10254
10255 u8 reserved_at_20[0x20];
10256
10257 u8 initial_record_number[0x40];
10258
10259 u8 resync_tcp_sn[0x20];
10260
10261 u8 gcm_iv[0x20];
10262
10263 u8 implicit_iv[0x40];
10264
10265 u8 reserved_at_100[0x8];
10266 u8 dek_index[0x18];
10267
10268 u8 reserved_at_120[0xe0];
10269 };
10270
10271 struct mlx5_ifc_tls_progress_params_bits {
10272 u8 reserved_at_0[0x8];
10273 u8 tisn[0x18];
10274
10275 u8 next_record_tcp_sn[0x20];
10276
10277 u8 hw_resync_tcp_sn[0x20];
10278
10279 u8 record_tracker_state[0x2];
10280 u8 auth_state[0x2];
10281 u8 reserved_at_64[0x4];
10282 u8 hw_offset_record_number[0x18];
10283 };
10284
10285 #endif /* MLX5_IFC_H */
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