include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 150         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 170         MLX5_CMD_OP_NOP                           = 0x80d,
 171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 203         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 204         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 205         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 206         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 207         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 208         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 209         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 210         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 211         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 212         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 213         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 214         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 215         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 216         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 217         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 218         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 219         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 220         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 221         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 222         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 223         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 224         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 225         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 226         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 227         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 228         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 229         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 230         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 231         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 232         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 233         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 234         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 235         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 236         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 237         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 238         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 239         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 240         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 241         MLX5_CMD_OP_MAX
 242 };
 243
 244 struct mlx5_ifc_flow_table_fields_supported_bits {
 245         u8         outer_dmac[0x1];
 246         u8         outer_smac[0x1];
 247         u8         outer_ether_type[0x1];
 248         u8         outer_ip_version[0x1];
 249         u8         outer_first_prio[0x1];
 250         u8         outer_first_cfi[0x1];
 251         u8         outer_first_vid[0x1];
 252         u8         outer_ipv4_ttl[0x1];
 253         u8         outer_second_prio[0x1];
 254         u8         outer_second_cfi[0x1];
 255         u8         outer_second_vid[0x1];
 256         u8         reserved_at_b[0x1];
 257         u8         outer_sip[0x1];
 258         u8         outer_dip[0x1];
 259         u8         outer_frag[0x1];
 260         u8         outer_ip_protocol[0x1];
 261         u8         outer_ip_ecn[0x1];
 262         u8         outer_ip_dscp[0x1];
 263         u8         outer_udp_sport[0x1];
 264         u8         outer_udp_dport[0x1];
 265         u8         outer_tcp_sport[0x1];
 266         u8         outer_tcp_dport[0x1];
 267         u8         outer_tcp_flags[0x1];
 268         u8         outer_gre_protocol[0x1];
 269         u8         outer_gre_key[0x1];
 270         u8         outer_vxlan_vni[0x1];
 271         u8         reserved_at_1a[0x5];
 272         u8         source_eswitch_port[0x1];
 273
 274         u8         inner_dmac[0x1];
 275         u8         inner_smac[0x1];
 276         u8         inner_ether_type[0x1];
 277         u8         inner_ip_version[0x1];
 278         u8         inner_first_prio[0x1];
 279         u8         inner_first_cfi[0x1];
 280         u8         inner_first_vid[0x1];
 281         u8         reserved_at_27[0x1];
 282         u8         inner_second_prio[0x1];
 283         u8         inner_second_cfi[0x1];
 284         u8         inner_second_vid[0x1];
 285         u8         reserved_at_2b[0x1];
 286         u8         inner_sip[0x1];
 287         u8         inner_dip[0x1];
 288         u8         inner_frag[0x1];
 289         u8         inner_ip_protocol[0x1];
 290         u8         inner_ip_ecn[0x1];
 291         u8         inner_ip_dscp[0x1];
 292         u8         inner_udp_sport[0x1];
 293         u8         inner_udp_dport[0x1];
 294         u8         inner_tcp_sport[0x1];
 295         u8         inner_tcp_dport[0x1];
 296         u8         inner_tcp_flags[0x1];
 297         u8         reserved_at_37[0x9];
 298         u8         reserved_at_40[0x1a];
 299         u8         bth_dst_qp[0x1];
 300
 301         u8         reserved_at_5b[0x25];
 302 };
 303
 304 struct mlx5_ifc_flow_table_prop_layout_bits {
 305         u8         ft_support[0x1];
 306         u8         reserved_at_1[0x1];
 307         u8         flow_counter[0x1];
 308         u8         flow_modify_en[0x1];
 309         u8         modify_root[0x1];
 310         u8         identified_miss_table_mode[0x1];
 311         u8         flow_table_modify[0x1];
 312         u8         encap[0x1];
 313         u8         decap[0x1];
 314         u8         reserved_at_9[0x17];
 315
 316         u8         reserved_at_20[0x2];
 317         u8         log_max_ft_size[0x6];
 318         u8         log_max_modify_header_context[0x8];
 319         u8         max_modify_header_actions[0x8];
 320         u8         max_ft_level[0x8];
 321
 322         u8         reserved_at_40[0x20];
 323
 324         u8         reserved_at_60[0x18];
 325         u8         log_max_ft_num[0x8];
 326
 327         u8         reserved_at_80[0x18];
 328         u8         log_max_destination[0x8];
 329
 330         u8         log_max_flow_counter[0x8];
 331         u8         reserved_at_a8[0x10];
 332         u8         log_max_flow[0x8];
 333
 334         u8         reserved_at_c0[0x40];
 335
 336         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 337
 338         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 339 };
 340
 341 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 342         u8         send[0x1];
 343         u8         receive[0x1];
 344         u8         write[0x1];
 345         u8         read[0x1];
 346         u8         atomic[0x1];
 347         u8         srq_receive[0x1];
 348         u8         reserved_at_6[0x1a];
 349 };
 350
 351 struct mlx5_ifc_ipv4_layout_bits {
 352         u8         reserved_at_0[0x60];
 353
 354         u8         ipv4[0x20];
 355 };
 356
 357 struct mlx5_ifc_ipv6_layout_bits {
 358         u8         ipv6[16][0x8];
 359 };
 360
 361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 362         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 363         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 364         u8         reserved_at_0[0x80];
 365 };
 366
 367 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 368         u8         smac_47_16[0x20];
 369
 370         u8         smac_15_0[0x10];
 371         u8         ethertype[0x10];
 372
 373         u8         dmac_47_16[0x20];
 374
 375         u8         dmac_15_0[0x10];
 376         u8         first_prio[0x3];
 377         u8         first_cfi[0x1];
 378         u8         first_vid[0xc];
 379
 380         u8         ip_protocol[0x8];
 381         u8         ip_dscp[0x6];
 382         u8         ip_ecn[0x2];
 383         u8         cvlan_tag[0x1];
 384         u8         svlan_tag[0x1];
 385         u8         frag[0x1];
 386         u8         ip_version[0x4];
 387         u8         tcp_flags[0x9];
 388
 389         u8         tcp_sport[0x10];
 390         u8         tcp_dport[0x10];
 391
 392         u8         reserved_at_c0[0x18];
 393         u8         ttl_hoplimit[0x8];
 394
 395         u8         udp_sport[0x10];
 396         u8         udp_dport[0x10];
 397
 398         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 399
 400         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 401 };
 402
 403 struct mlx5_ifc_fte_match_set_misc_bits {
 404         u8         reserved_at_0[0x8];
 405         u8         source_sqn[0x18];
 406
 407         u8         reserved_at_20[0x10];
 408         u8         source_port[0x10];
 409
 410         u8         outer_second_prio[0x3];
 411         u8         outer_second_cfi[0x1];
 412         u8         outer_second_vid[0xc];
 413         u8         inner_second_prio[0x3];
 414         u8         inner_second_cfi[0x1];
 415         u8         inner_second_vid[0xc];
 416
 417         u8         outer_second_cvlan_tag[0x1];
 418         u8         inner_second_cvlan_tag[0x1];
 419         u8         outer_second_svlan_tag[0x1];
 420         u8         inner_second_svlan_tag[0x1];
 421         u8         reserved_at_64[0xc];
 422         u8         gre_protocol[0x10];
 423
 424         u8         gre_key_h[0x18];
 425         u8         gre_key_l[0x8];
 426
 427         u8         vxlan_vni[0x18];
 428         u8         reserved_at_b8[0x8];
 429
 430         u8         reserved_at_c0[0x20];
 431
 432         u8         reserved_at_e0[0xc];
 433         u8         outer_ipv6_flow_label[0x14];
 434
 435         u8         reserved_at_100[0xc];
 436         u8         inner_ipv6_flow_label[0x14];
 437
 438         u8         reserved_at_120[0x28];
 439         u8         bth_dst_qp[0x18];
 440         u8         reserved_at_160[0xa0];
 441 };
 442
 443 struct mlx5_ifc_cmd_pas_bits {
 444         u8         pa_h[0x20];
 445
 446         u8         pa_l[0x14];
 447         u8         reserved_at_34[0xc];
 448 };
 449
 450 struct mlx5_ifc_uint64_bits {
 451         u8         hi[0x20];
 452
 453         u8         lo[0x20];
 454 };
 455
 456 enum {
 457         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 458         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 459         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 460         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 461         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 462         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 463         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 464         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 465         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 466         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 467 };
 468
 469 struct mlx5_ifc_ads_bits {
 470         u8         fl[0x1];
 471         u8         free_ar[0x1];
 472         u8         reserved_at_2[0xe];
 473         u8         pkey_index[0x10];
 474
 475         u8         reserved_at_20[0x8];
 476         u8         grh[0x1];
 477         u8         mlid[0x7];
 478         u8         rlid[0x10];
 479
 480         u8         ack_timeout[0x5];
 481         u8         reserved_at_45[0x3];
 482         u8         src_addr_index[0x8];
 483         u8         reserved_at_50[0x4];
 484         u8         stat_rate[0x4];
 485         u8         hop_limit[0x8];
 486
 487         u8         reserved_at_60[0x4];
 488         u8         tclass[0x8];
 489         u8         flow_label[0x14];
 490
 491         u8         rgid_rip[16][0x8];
 492
 493         u8         reserved_at_100[0x4];
 494         u8         f_dscp[0x1];
 495         u8         f_ecn[0x1];
 496         u8         reserved_at_106[0x1];
 497         u8         f_eth_prio[0x1];
 498         u8         ecn[0x2];
 499         u8         dscp[0x6];
 500         u8         udp_sport[0x10];
 501
 502         u8         dei_cfi[0x1];
 503         u8         eth_prio[0x3];
 504         u8         sl[0x4];
 505         u8         port[0x8];
 506         u8         rmac_47_32[0x10];
 507
 508         u8         rmac_31_0[0x20];
 509 };
 510
 511 struct mlx5_ifc_flow_table_nic_cap_bits {
 512         u8         nic_rx_multi_path_tirs[0x1];
 513         u8         nic_rx_multi_path_tirs_fts[0x1];
 514         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 515         u8         reserved_at_3[0x1fd];
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 518
 519         u8         reserved_at_400[0x200];
 520
 521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 522
 523         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 524
 525         u8         reserved_at_a00[0x200];
 526
 527         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 528
 529         u8         reserved_at_e00[0x7200];
 530 };
 531
 532 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 533         u8     reserved_at_0[0x200];
 534
 535         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 536
 537         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 538
 539         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 540
 541         u8      reserved_at_800[0x7800];
 542 };
 543
 544 struct mlx5_ifc_e_switch_cap_bits {
 545         u8         vport_svlan_strip[0x1];
 546         u8         vport_cvlan_strip[0x1];
 547         u8         vport_svlan_insert[0x1];
 548         u8         vport_cvlan_insert_if_not_exist[0x1];
 549         u8         vport_cvlan_insert_overwrite[0x1];
 550         u8         reserved_at_5[0x19];
 551         u8         nic_vport_node_guid_modify[0x1];
 552         u8         nic_vport_port_guid_modify[0x1];
 553
 554         u8         vxlan_encap_decap[0x1];
 555         u8         nvgre_encap_decap[0x1];
 556         u8         reserved_at_22[0x9];
 557         u8         log_max_encap_headers[0x5];
 558         u8         reserved_2b[0x6];
 559         u8         max_encap_header_size[0xa];
 560
 561         u8         reserved_40[0x7c0];
 562
 563 };
 564
 565 struct mlx5_ifc_qos_cap_bits {
 566         u8         packet_pacing[0x1];
 567         u8         esw_scheduling[0x1];
 568         u8         esw_bw_share[0x1];
 569         u8         esw_rate_limit[0x1];
 570         u8         reserved_at_4[0x1c];
 571
 572         u8         reserved_at_20[0x20];
 573
 574         u8         packet_pacing_max_rate[0x20];
 575
 576         u8         packet_pacing_min_rate[0x20];
 577
 578         u8         reserved_at_80[0x10];
 579         u8         packet_pacing_rate_table_size[0x10];
 580
 581         u8         esw_element_type[0x10];
 582         u8         esw_tsar_type[0x10];
 583
 584         u8         reserved_at_c0[0x10];
 585         u8         max_qos_para_vport[0x10];
 586
 587         u8         max_tsar_bw_share[0x20];
 588
 589         u8         reserved_at_100[0x700];
 590 };
 591
 592 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 593         u8         csum_cap[0x1];
 594         u8         vlan_cap[0x1];
 595         u8         lro_cap[0x1];
 596         u8         lro_psh_flag[0x1];
 597         u8         lro_time_stamp[0x1];
 598         u8         reserved_at_5[0x2];
 599         u8         wqe_vlan_insert[0x1];
 600         u8         self_lb_en_modifiable[0x1];
 601         u8         reserved_at_9[0x2];
 602         u8         max_lso_cap[0x5];
 603         u8         multi_pkt_send_wqe[0x2];
 604         u8         wqe_inline_mode[0x2];
 605         u8         rss_ind_tbl_cap[0x4];
 606         u8         reg_umr_sq[0x1];
 607         u8         scatter_fcs[0x1];
 608         u8         enhanced_multi_pkt_send_wqe[0x1];
 609         u8         tunnel_lso_const_out_ip_id[0x1];
 610         u8         reserved_at_1c[0x2];
 611         u8         tunnel_stateless_gre[0x1];
 612         u8         tunnel_stateless_vxlan[0x1];
 613
 614         u8         swp[0x1];
 615         u8         swp_csum[0x1];
 616         u8         swp_lso[0x1];
 617         u8         reserved_at_23[0x1b];
 618         u8         max_geneve_opt_len[0x1];
 619         u8         tunnel_stateless_geneve_rx[0x1];
 620
 621         u8         reserved_at_40[0x10];
 622         u8         lro_min_mss_size[0x10];
 623
 624         u8         reserved_at_60[0x120];
 625
 626         u8         lro_timer_supported_periods[4][0x20];
 627
 628         u8         reserved_at_200[0x600];
 629 };
 630
 631 struct mlx5_ifc_roce_cap_bits {
 632         u8         roce_apm[0x1];
 633         u8         reserved_at_1[0x1f];
 634
 635         u8         reserved_at_20[0x60];
 636
 637         u8         reserved_at_80[0xc];
 638         u8         l3_type[0x4];
 639         u8         reserved_at_90[0x8];
 640         u8         roce_version[0x8];
 641
 642         u8         reserved_at_a0[0x10];
 643         u8         r_roce_dest_udp_port[0x10];
 644
 645         u8         r_roce_max_src_udp_port[0x10];
 646         u8         r_roce_min_src_udp_port[0x10];
 647
 648         u8         reserved_at_e0[0x10];
 649         u8         roce_address_table_size[0x10];
 650
 651         u8         reserved_at_100[0x700];
 652 };
 653
 654 enum {
 655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 656         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 657         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 658         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 659         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 660         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 661         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 662         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 663         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 664 };
 665
 666 enum {
 667         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 668         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 669         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 670         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 671         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 672         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 673         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 674         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 675         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 676 };
 677
 678 struct mlx5_ifc_atomic_caps_bits {
 679         u8         reserved_at_0[0x40];
 680
 681         u8         atomic_req_8B_endianness_mode[0x2];
 682         u8         reserved_at_42[0x4];
 683         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 684
 685         u8         reserved_at_47[0x19];
 686
 687         u8         reserved_at_60[0x20];
 688
 689         u8         reserved_at_80[0x10];
 690         u8         atomic_operations[0x10];
 691
 692         u8         reserved_at_a0[0x10];
 693         u8         atomic_size_qp[0x10];
 694
 695         u8         reserved_at_c0[0x10];
 696         u8         atomic_size_dc[0x10];
 697
 698         u8         reserved_at_e0[0x720];
 699 };
 700
 701 struct mlx5_ifc_odp_cap_bits {
 702         u8         reserved_at_0[0x40];
 703
 704         u8         sig[0x1];
 705         u8         reserved_at_41[0x1f];
 706
 707         u8         reserved_at_60[0x20];
 708
 709         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 710
 711         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 712
 713         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 714
 715         u8         reserved_at_e0[0x720];
 716 };
 717
 718 struct mlx5_ifc_calc_op {
 719         u8        reserved_at_0[0x10];
 720         u8        reserved_at_10[0x9];
 721         u8        op_swap_endianness[0x1];
 722         u8        op_min[0x1];
 723         u8        op_xor[0x1];
 724         u8        op_or[0x1];
 725         u8        op_and[0x1];
 726         u8        op_max[0x1];
 727         u8        op_add[0x1];
 728 };
 729
 730 struct mlx5_ifc_vector_calc_cap_bits {
 731         u8         calc_matrix[0x1];
 732         u8         reserved_at_1[0x1f];
 733         u8         reserved_at_20[0x8];
 734         u8         max_vec_count[0x8];
 735         u8         reserved_at_30[0xd];
 736         u8         max_chunk_size[0x3];
 737         struct mlx5_ifc_calc_op calc0;
 738         struct mlx5_ifc_calc_op calc1;
 739         struct mlx5_ifc_calc_op calc2;
 740         struct mlx5_ifc_calc_op calc3;
 741
 742         u8         reserved_at_e0[0x720];
 743 };
 744
 745 enum {
 746         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 747         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 748         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 749         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 750 };
 751
 752 enum {
 753         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 754         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 755 };
 756
 757 enum {
 758         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 759         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 760         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 761         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 762         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 763 };
 764
 765 enum {
 766         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 767         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 768         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 769         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 770         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 771         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 772 };
 773
 774 enum {
 775         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 776         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 777 };
 778
 779 enum {
 780         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 781         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 782         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 783 };
 784
 785 enum {
 786         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 787         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 788 };
 789
 790 enum {
 791         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 792         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 793         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 794 };
 795
 796 struct mlx5_ifc_cmd_hca_cap_bits {
 797         u8         reserved_at_0[0x80];
 798
 799         u8         log_max_srq_sz[0x8];
 800         u8         log_max_qp_sz[0x8];
 801         u8         reserved_at_90[0xb];
 802         u8         log_max_qp[0x5];
 803
 804         u8         reserved_at_a0[0xb];
 805         u8         log_max_srq[0x5];
 806         u8         reserved_at_b0[0x10];
 807
 808         u8         reserved_at_c0[0x8];
 809         u8         log_max_cq_sz[0x8];
 810         u8         reserved_at_d0[0xb];
 811         u8         log_max_cq[0x5];
 812
 813         u8         log_max_eq_sz[0x8];
 814         u8         reserved_at_e8[0x2];
 815         u8         log_max_mkey[0x6];
 816         u8         reserved_at_f0[0xc];
 817         u8         log_max_eq[0x4];
 818
 819         u8         max_indirection[0x8];
 820         u8         fixed_buffer_size[0x1];
 821         u8         log_max_mrw_sz[0x7];
 822         u8         force_teardown[0x1];
 823         u8         reserved_at_111[0x1];
 824         u8         log_max_bsf_list_size[0x6];
 825         u8         umr_extended_translation_offset[0x1];
 826         u8         null_mkey[0x1];
 827         u8         log_max_klm_list_size[0x6];
 828
 829         u8         reserved_at_120[0xa];
 830         u8         log_max_ra_req_dc[0x6];
 831         u8         reserved_at_130[0xa];
 832         u8         log_max_ra_res_dc[0x6];
 833
 834         u8         reserved_at_140[0xa];
 835         u8         log_max_ra_req_qp[0x6];
 836         u8         reserved_at_150[0xa];
 837         u8         log_max_ra_res_qp[0x6];
 838
 839         u8         end_pad[0x1];
 840         u8         cc_query_allowed[0x1];
 841         u8         cc_modify_allowed[0x1];
 842         u8         start_pad[0x1];
 843         u8         cache_line_128byte[0x1];
 844         u8         reserved_at_165[0xa];
 845         u8         qcam_reg[0x1];
 846         u8         gid_table_size[0x10];
 847
 848         u8         out_of_seq_cnt[0x1];
 849         u8         vport_counters[0x1];
 850         u8         retransmission_q_counters[0x1];
 851         u8         reserved_at_183[0x1];
 852         u8         modify_rq_counter_set_id[0x1];
 853         u8         rq_delay_drop[0x1];
 854         u8         max_qp_cnt[0xa];
 855         u8         pkey_table_size[0x10];
 856
 857         u8         vport_group_manager[0x1];
 858         u8         vhca_group_manager[0x1];
 859         u8         ib_virt[0x1];
 860         u8         eth_virt[0x1];
 861         u8         reserved_at_1a4[0x1];
 862         u8         ets[0x1];
 863         u8         nic_flow_table[0x1];
 864         u8         eswitch_flow_table[0x1];
 865         u8         early_vf_enable[0x1];
 866         u8         mcam_reg[0x1];
 867         u8         pcam_reg[0x1];
 868         u8         local_ca_ack_delay[0x5];
 869         u8         port_module_event[0x1];
 870         u8         enhanced_error_q_counters[0x1];
 871         u8         ports_check[0x1];
 872         u8         reserved_at_1b3[0x1];
 873         u8         disable_link_up[0x1];
 874         u8         beacon_led[0x1];
 875         u8         port_type[0x2];
 876         u8         num_ports[0x8];
 877
 878         u8         reserved_at_1c0[0x1];
 879         u8         pps[0x1];
 880         u8         pps_modify[0x1];
 881         u8         log_max_msg[0x5];
 882         u8         reserved_at_1c8[0x4];
 883         u8         max_tc[0x4];
 884         u8         reserved_at_1d0[0x1];
 885         u8         dcbx[0x1];
 886         u8         general_notification_event[0x1];
 887         u8         reserved_at_1d3[0x2];
 888         u8         fpga[0x1];
 889         u8         rol_s[0x1];
 890         u8         rol_g[0x1];
 891         u8         reserved_at_1d8[0x1];
 892         u8         wol_s[0x1];
 893         u8         wol_g[0x1];
 894         u8         wol_a[0x1];
 895         u8         wol_b[0x1];
 896         u8         wol_m[0x1];
 897         u8         wol_u[0x1];
 898         u8         wol_p[0x1];
 899
 900         u8         stat_rate_support[0x10];
 901         u8         reserved_at_1f0[0xc];
 902         u8         cqe_version[0x4];
 903
 904         u8         compact_address_vector[0x1];
 905         u8         striding_rq[0x1];
 906         u8         reserved_at_202[0x1];
 907         u8         ipoib_enhanced_offloads[0x1];
 908         u8         ipoib_basic_offloads[0x1];
 909         u8         reserved_at_205[0x5];
 910         u8         umr_fence[0x2];
 911         u8         reserved_at_20c[0x3];
 912         u8         drain_sigerr[0x1];
 913         u8         cmdif_checksum[0x2];
 914         u8         sigerr_cqe[0x1];
 915         u8         reserved_at_213[0x1];
 916         u8         wq_signature[0x1];
 917         u8         sctr_data_cqe[0x1];
 918         u8         reserved_at_216[0x1];
 919         u8         sho[0x1];
 920         u8         tph[0x1];
 921         u8         rf[0x1];
 922         u8         dct[0x1];
 923         u8         qos[0x1];
 924         u8         eth_net_offloads[0x1];
 925         u8         roce[0x1];
 926         u8         atomic[0x1];
 927         u8         reserved_at_21f[0x1];
 928
 929         u8         cq_oi[0x1];
 930         u8         cq_resize[0x1];
 931         u8         cq_moderation[0x1];
 932         u8         reserved_at_223[0x3];
 933         u8         cq_eq_remap[0x1];
 934         u8         pg[0x1];
 935         u8         block_lb_mc[0x1];
 936         u8         reserved_at_229[0x1];
 937         u8         scqe_break_moderation[0x1];
 938         u8         cq_period_start_from_cqe[0x1];
 939         u8         cd[0x1];
 940         u8         reserved_at_22d[0x1];
 941         u8         apm[0x1];
 942         u8         vector_calc[0x1];
 943         u8         umr_ptr_rlky[0x1];
 944         u8         imaicl[0x1];
 945         u8         reserved_at_232[0x4];
 946         u8         qkv[0x1];
 947         u8         pkv[0x1];
 948         u8         set_deth_sqpn[0x1];
 949         u8         reserved_at_239[0x3];
 950         u8         xrc[0x1];
 951         u8         ud[0x1];
 952         u8         uc[0x1];
 953         u8         rc[0x1];
 954
 955         u8         uar_4k[0x1];
 956         u8         reserved_at_241[0x9];
 957         u8         uar_sz[0x6];
 958         u8         reserved_at_250[0x8];
 959         u8         log_pg_sz[0x8];
 960
 961         u8         bf[0x1];
 962         u8         driver_version[0x1];
 963         u8         pad_tx_eth_packet[0x1];
 964         u8         reserved_at_263[0x8];
 965         u8         log_bf_reg_size[0x5];
 966
 967         u8         reserved_at_270[0xb];
 968         u8         lag_master[0x1];
 969         u8         num_lag_ports[0x4];
 970
 971         u8         reserved_at_280[0x10];
 972         u8         max_wqe_sz_sq[0x10];
 973
 974         u8         reserved_at_2a0[0x10];
 975         u8         max_wqe_sz_rq[0x10];
 976
 977         u8         max_flow_counter_31_16[0x10];
 978         u8         max_wqe_sz_sq_dc[0x10];
 979
 980         u8         reserved_at_2e0[0x7];
 981         u8         max_qp_mcg[0x19];
 982
 983         u8         reserved_at_300[0x18];
 984         u8         log_max_mcg[0x8];
 985
 986         u8         reserved_at_320[0x3];
 987         u8         log_max_transport_domain[0x5];
 988         u8         reserved_at_328[0x3];
 989         u8         log_max_pd[0x5];
 990         u8         reserved_at_330[0xb];
 991         u8         log_max_xrcd[0x5];
 992
 993         u8         reserved_at_340[0x8];
 994         u8         log_max_flow_counter_bulk[0x8];
 995         u8         max_flow_counter_15_0[0x10];
 996
 997
 998         u8         reserved_at_360[0x3];
 999         u8         log_max_rq[0x5];
1000         u8         reserved_at_368[0x3];
1001         u8         log_max_sq[0x5];
1002         u8         reserved_at_370[0x3];
1003         u8         log_max_tir[0x5];
1004         u8         reserved_at_378[0x3];
1005         u8         log_max_tis[0x5];
1006
1007         u8         basic_cyclic_rcv_wqe[0x1];
1008         u8         reserved_at_381[0x2];
1009         u8         log_max_rmp[0x5];
1010         u8         reserved_at_388[0x3];
1011         u8         log_max_rqt[0x5];
1012         u8         reserved_at_390[0x3];
1013         u8         log_max_rqt_size[0x5];
1014         u8         reserved_at_398[0x3];
1015         u8         log_max_tis_per_sq[0x5];
1016
1017         u8         reserved_at_3a0[0x3];
1018         u8         log_max_stride_sz_rq[0x5];
1019         u8         reserved_at_3a8[0x3];
1020         u8         log_min_stride_sz_rq[0x5];
1021         u8         reserved_at_3b0[0x3];
1022         u8         log_max_stride_sz_sq[0x5];
1023         u8         reserved_at_3b8[0x3];
1024         u8         log_min_stride_sz_sq[0x5];
1025
1026         u8         reserved_at_3c0[0x1b];
1027         u8         log_max_wq_sz[0x5];
1028
1029         u8         nic_vport_change_event[0x1];
1030         u8         disable_local_lb[0x1];
1031         u8         reserved_at_3e2[0x9];
1032         u8         log_max_vlan_list[0x5];
1033         u8         reserved_at_3f0[0x3];
1034         u8         log_max_current_mc_list[0x5];
1035         u8         reserved_at_3f8[0x3];
1036         u8         log_max_current_uc_list[0x5];
1037
1038         u8         reserved_at_400[0x80];
1039
1040         u8         reserved_at_480[0x3];
1041         u8         log_max_l2_table[0x5];
1042         u8         reserved_at_488[0x8];
1043         u8         log_uar_page_sz[0x10];
1044
1045         u8         reserved_at_4a0[0x20];
1046         u8         device_frequency_mhz[0x20];
1047         u8         device_frequency_khz[0x20];
1048
1049         u8         reserved_at_500[0x20];
1050         u8         num_of_uars_per_page[0x20];
1051         u8         reserved_at_540[0x40];
1052
1053         u8         reserved_at_580[0x3d];
1054         u8         cqe_128_always[0x1];
1055         u8         cqe_compression_128[0x1];
1056         u8         cqe_compression[0x1];
1057
1058         u8         cqe_compression_timeout[0x10];
1059         u8         cqe_compression_max_num[0x10];
1060
1061         u8         reserved_at_5e0[0x10];
1062         u8         tag_matching[0x1];
1063         u8         rndv_offload_rc[0x1];
1064         u8         rndv_offload_dc[0x1];
1065         u8         log_tag_matching_list_sz[0x5];
1066         u8         reserved_at_5f8[0x3];
1067         u8         log_max_xrq[0x5];
1068
1069         u8         reserved_at_600[0x200];
1070 };
1071
1072 enum mlx5_flow_destination_type {
1073         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1074         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1075         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1076
1077         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1078 };
1079
1080 struct mlx5_ifc_dest_format_struct_bits {
1081         u8         destination_type[0x8];
1082         u8         destination_id[0x18];
1083
1084         u8         reserved_at_20[0x20];
1085 };
1086
1087 struct mlx5_ifc_flow_counter_list_bits {
1088         u8         flow_counter_id[0x20];
1089
1090         u8         reserved_at_20[0x20];
1091 };
1092
1093 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1094         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1095         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1096         u8         reserved_at_0[0x40];
1097 };
1098
1099 struct mlx5_ifc_fte_match_param_bits {
1100         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1101
1102         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1103
1104         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1105
1106         u8         reserved_at_600[0xa00];
1107 };
1108
1109 enum {
1110         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1111         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1112         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1113         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1114         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1115 };
1116
1117 struct mlx5_ifc_rx_hash_field_select_bits {
1118         u8         l3_prot_type[0x1];
1119         u8         l4_prot_type[0x1];
1120         u8         selected_fields[0x1e];
1121 };
1122
1123 enum {
1124         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1125         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1126 };
1127
1128 enum {
1129         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1130         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1131 };
1132
1133 struct mlx5_ifc_wq_bits {
1134         u8         wq_type[0x4];
1135         u8         wq_signature[0x1];
1136         u8         end_padding_mode[0x2];
1137         u8         cd_slave[0x1];
1138         u8         reserved_at_8[0x18];
1139
1140         u8         hds_skip_first_sge[0x1];
1141         u8         log2_hds_buf_size[0x3];
1142         u8         reserved_at_24[0x7];
1143         u8         page_offset[0x5];
1144         u8         lwm[0x10];
1145
1146         u8         reserved_at_40[0x8];
1147         u8         pd[0x18];
1148
1149         u8         reserved_at_60[0x8];
1150         u8         uar_page[0x18];
1151
1152         u8         dbr_addr[0x40];
1153
1154         u8         hw_counter[0x20];
1155
1156         u8         sw_counter[0x20];
1157
1158         u8         reserved_at_100[0xc];
1159         u8         log_wq_stride[0x4];
1160         u8         reserved_at_110[0x3];
1161         u8         log_wq_pg_sz[0x5];
1162         u8         reserved_at_118[0x3];
1163         u8         log_wq_sz[0x5];
1164
1165         u8         reserved_at_120[0x15];
1166         u8         log_wqe_num_of_strides[0x3];
1167         u8         two_byte_shift_en[0x1];
1168         u8         reserved_at_139[0x4];
1169         u8         log_wqe_stride_size[0x3];
1170
1171         u8         reserved_at_140[0x4c0];
1172
1173         struct mlx5_ifc_cmd_pas_bits pas[0];
1174 };
1175
1176 struct mlx5_ifc_rq_num_bits {
1177         u8         reserved_at_0[0x8];
1178         u8         rq_num[0x18];
1179 };
1180
1181 struct mlx5_ifc_mac_address_layout_bits {
1182         u8         reserved_at_0[0x10];
1183         u8         mac_addr_47_32[0x10];
1184
1185         u8         mac_addr_31_0[0x20];
1186 };
1187
1188 struct mlx5_ifc_vlan_layout_bits {
1189         u8         reserved_at_0[0x14];
1190         u8         vlan[0x0c];
1191
1192         u8         reserved_at_20[0x20];
1193 };
1194
1195 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1196         u8         reserved_at_0[0xa0];
1197
1198         u8         min_time_between_cnps[0x20];
1199
1200         u8         reserved_at_c0[0x12];
1201         u8         cnp_dscp[0x6];
1202         u8         reserved_at_d8[0x4];
1203         u8         cnp_prio_mode[0x1];
1204         u8         cnp_802p_prio[0x3];
1205
1206         u8         reserved_at_e0[0x720];
1207 };
1208
1209 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1210         u8         reserved_at_0[0x60];
1211
1212         u8         reserved_at_60[0x4];
1213         u8         clamp_tgt_rate[0x1];
1214         u8         reserved_at_65[0x3];
1215         u8         clamp_tgt_rate_after_time_inc[0x1];
1216         u8         reserved_at_69[0x17];
1217
1218         u8         reserved_at_80[0x20];
1219
1220         u8         rpg_time_reset[0x20];
1221
1222         u8         rpg_byte_reset[0x20];
1223
1224         u8         rpg_threshold[0x20];
1225
1226         u8         rpg_max_rate[0x20];
1227
1228         u8         rpg_ai_rate[0x20];
1229
1230         u8         rpg_hai_rate[0x20];
1231
1232         u8         rpg_gd[0x20];
1233
1234         u8         rpg_min_dec_fac[0x20];
1235
1236         u8         rpg_min_rate[0x20];
1237
1238         u8         reserved_at_1c0[0xe0];
1239
1240         u8         rate_to_set_on_first_cnp[0x20];
1241
1242         u8         dce_tcp_g[0x20];
1243
1244         u8         dce_tcp_rtt[0x20];
1245
1246         u8         rate_reduce_monitor_period[0x20];
1247
1248         u8         reserved_at_320[0x20];
1249
1250         u8         initial_alpha_value[0x20];
1251
1252         u8         reserved_at_360[0x4a0];
1253 };
1254
1255 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1256         u8         reserved_at_0[0x80];
1257
1258         u8         rppp_max_rps[0x20];
1259
1260         u8         rpg_time_reset[0x20];
1261
1262         u8         rpg_byte_reset[0x20];
1263
1264         u8         rpg_threshold[0x20];
1265
1266         u8         rpg_max_rate[0x20];
1267
1268         u8         rpg_ai_rate[0x20];
1269
1270         u8         rpg_hai_rate[0x20];
1271
1272         u8         rpg_gd[0x20];
1273
1274         u8         rpg_min_dec_fac[0x20];
1275
1276         u8         rpg_min_rate[0x20];
1277
1278         u8         reserved_at_1c0[0x640];
1279 };
1280
1281 enum {
1282         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1283         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1284         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1285 };
1286
1287 struct mlx5_ifc_resize_field_select_bits {
1288         u8         resize_field_select[0x20];
1289 };
1290
1291 enum {
1292         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1293         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1294         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1295         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1296 };
1297
1298 struct mlx5_ifc_modify_field_select_bits {
1299         u8         modify_field_select[0x20];
1300 };
1301
1302 struct mlx5_ifc_field_select_r_roce_np_bits {
1303         u8         field_select_r_roce_np[0x20];
1304 };
1305
1306 struct mlx5_ifc_field_select_r_roce_rp_bits {
1307         u8         field_select_r_roce_rp[0x20];
1308 };
1309
1310 enum {
1311         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1312         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1313         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1314         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1315         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1316         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1317         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1318         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1319         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1320         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1321 };
1322
1323 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1324         u8         field_select_8021qaurp[0x20];
1325 };
1326
1327 struct mlx5_ifc_phys_layer_cntrs_bits {
1328         u8         time_since_last_clear_high[0x20];
1329
1330         u8         time_since_last_clear_low[0x20];
1331
1332         u8         symbol_errors_high[0x20];
1333
1334         u8         symbol_errors_low[0x20];
1335
1336         u8         sync_headers_errors_high[0x20];
1337
1338         u8         sync_headers_errors_low[0x20];
1339
1340         u8         edpl_bip_errors_lane0_high[0x20];
1341
1342         u8         edpl_bip_errors_lane0_low[0x20];
1343
1344         u8         edpl_bip_errors_lane1_high[0x20];
1345
1346         u8         edpl_bip_errors_lane1_low[0x20];
1347
1348         u8         edpl_bip_errors_lane2_high[0x20];
1349
1350         u8         edpl_bip_errors_lane2_low[0x20];
1351
1352         u8         edpl_bip_errors_lane3_high[0x20];
1353
1354         u8         edpl_bip_errors_lane3_low[0x20];
1355
1356         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1357
1358         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1359
1360         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1361
1362         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1363
1364         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1365
1366         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1367
1368         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1369
1370         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1371
1372         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1373
1374         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1375
1376         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1377
1378         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1379
1380         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1381
1382         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1383
1384         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1385
1386         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1387
1388         u8         rs_fec_corrected_blocks_high[0x20];
1389
1390         u8         rs_fec_corrected_blocks_low[0x20];
1391
1392         u8         rs_fec_uncorrectable_blocks_high[0x20];
1393
1394         u8         rs_fec_uncorrectable_blocks_low[0x20];
1395
1396         u8         rs_fec_no_errors_blocks_high[0x20];
1397
1398         u8         rs_fec_no_errors_blocks_low[0x20];
1399
1400         u8         rs_fec_single_error_blocks_high[0x20];
1401
1402         u8         rs_fec_single_error_blocks_low[0x20];
1403
1404         u8         rs_fec_corrected_symbols_total_high[0x20];
1405
1406         u8         rs_fec_corrected_symbols_total_low[0x20];
1407
1408         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1409
1410         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1411
1412         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1413
1414         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1415
1416         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1417
1418         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1419
1420         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1421
1422         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1423
1424         u8         link_down_events[0x20];
1425
1426         u8         successful_recovery_events[0x20];
1427
1428         u8         reserved_at_640[0x180];
1429 };
1430
1431 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1432         u8         time_since_last_clear_high[0x20];
1433
1434         u8         time_since_last_clear_low[0x20];
1435
1436         u8         phy_received_bits_high[0x20];
1437
1438         u8         phy_received_bits_low[0x20];
1439
1440         u8         phy_symbol_errors_high[0x20];
1441
1442         u8         phy_symbol_errors_low[0x20];
1443
1444         u8         phy_corrected_bits_high[0x20];
1445
1446         u8         phy_corrected_bits_low[0x20];
1447
1448         u8         phy_corrected_bits_lane0_high[0x20];
1449
1450         u8         phy_corrected_bits_lane0_low[0x20];
1451
1452         u8         phy_corrected_bits_lane1_high[0x20];
1453
1454         u8         phy_corrected_bits_lane1_low[0x20];
1455
1456         u8         phy_corrected_bits_lane2_high[0x20];
1457
1458         u8         phy_corrected_bits_lane2_low[0x20];
1459
1460         u8         phy_corrected_bits_lane3_high[0x20];
1461
1462         u8         phy_corrected_bits_lane3_low[0x20];
1463
1464         u8         reserved_at_200[0x5c0];
1465 };
1466
1467 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1468         u8         symbol_error_counter[0x10];
1469
1470         u8         link_error_recovery_counter[0x8];
1471
1472         u8         link_downed_counter[0x8];
1473
1474         u8         port_rcv_errors[0x10];
1475
1476         u8         port_rcv_remote_physical_errors[0x10];
1477
1478         u8         port_rcv_switch_relay_errors[0x10];
1479
1480         u8         port_xmit_discards[0x10];
1481
1482         u8         port_xmit_constraint_errors[0x8];
1483
1484         u8         port_rcv_constraint_errors[0x8];
1485
1486         u8         reserved_at_70[0x8];
1487
1488         u8         link_overrun_errors[0x8];
1489
1490         u8         reserved_at_80[0x10];
1491
1492         u8         vl_15_dropped[0x10];
1493
1494         u8         reserved_at_a0[0x80];
1495
1496         u8         port_xmit_wait[0x20];
1497 };
1498
1499 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1500         u8         transmit_queue_high[0x20];
1501
1502         u8         transmit_queue_low[0x20];
1503
1504         u8         reserved_at_40[0x780];
1505 };
1506
1507 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1508         u8         rx_octets_high[0x20];
1509
1510         u8         rx_octets_low[0x20];
1511
1512         u8         reserved_at_40[0xc0];
1513
1514         u8         rx_frames_high[0x20];
1515
1516         u8         rx_frames_low[0x20];
1517
1518         u8         tx_octets_high[0x20];
1519
1520         u8         tx_octets_low[0x20];
1521
1522         u8         reserved_at_180[0xc0];
1523
1524         u8         tx_frames_high[0x20];
1525
1526         u8         tx_frames_low[0x20];
1527
1528         u8         rx_pause_high[0x20];
1529
1530         u8         rx_pause_low[0x20];
1531
1532         u8         rx_pause_duration_high[0x20];
1533
1534         u8         rx_pause_duration_low[0x20];
1535
1536         u8         tx_pause_high[0x20];
1537
1538         u8         tx_pause_low[0x20];
1539
1540         u8         tx_pause_duration_high[0x20];
1541
1542         u8         tx_pause_duration_low[0x20];
1543
1544         u8         rx_pause_transition_high[0x20];
1545
1546         u8         rx_pause_transition_low[0x20];
1547
1548         u8         reserved_at_3c0[0x400];
1549 };
1550
1551 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1552         u8         port_transmit_wait_high[0x20];
1553
1554         u8         port_transmit_wait_low[0x20];
1555
1556         u8         reserved_at_40[0x100];
1557
1558         u8         rx_buffer_almost_full_high[0x20];
1559
1560         u8         rx_buffer_almost_full_low[0x20];
1561
1562         u8         rx_buffer_full_high[0x20];
1563
1564         u8         rx_buffer_full_low[0x20];
1565
1566         u8         reserved_at_1c0[0x600];
1567 };
1568
1569 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1570         u8         dot3stats_alignment_errors_high[0x20];
1571
1572         u8         dot3stats_alignment_errors_low[0x20];
1573
1574         u8         dot3stats_fcs_errors_high[0x20];
1575
1576         u8         dot3stats_fcs_errors_low[0x20];
1577
1578         u8         dot3stats_single_collision_frames_high[0x20];
1579
1580         u8         dot3stats_single_collision_frames_low[0x20];
1581
1582         u8         dot3stats_multiple_collision_frames_high[0x20];
1583
1584         u8         dot3stats_multiple_collision_frames_low[0x20];
1585
1586         u8         dot3stats_sqe_test_errors_high[0x20];
1587
1588         u8         dot3stats_sqe_test_errors_low[0x20];
1589
1590         u8         dot3stats_deferred_transmissions_high[0x20];
1591
1592         u8         dot3stats_deferred_transmissions_low[0x20];
1593
1594         u8         dot3stats_late_collisions_high[0x20];
1595
1596         u8         dot3stats_late_collisions_low[0x20];
1597
1598         u8         dot3stats_excessive_collisions_high[0x20];
1599
1600         u8         dot3stats_excessive_collisions_low[0x20];
1601
1602         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1603
1604         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1605
1606         u8         dot3stats_carrier_sense_errors_high[0x20];
1607
1608         u8         dot3stats_carrier_sense_errors_low[0x20];
1609
1610         u8         dot3stats_frame_too_longs_high[0x20];
1611
1612         u8         dot3stats_frame_too_longs_low[0x20];
1613
1614         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1615
1616         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1617
1618         u8         dot3stats_symbol_errors_high[0x20];
1619
1620         u8         dot3stats_symbol_errors_low[0x20];
1621
1622         u8         dot3control_in_unknown_opcodes_high[0x20];
1623
1624         u8         dot3control_in_unknown_opcodes_low[0x20];
1625
1626         u8         dot3in_pause_frames_high[0x20];
1627
1628         u8         dot3in_pause_frames_low[0x20];
1629
1630         u8         dot3out_pause_frames_high[0x20];
1631
1632         u8         dot3out_pause_frames_low[0x20];
1633
1634         u8         reserved_at_400[0x3c0];
1635 };
1636
1637 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1638         u8         ether_stats_drop_events_high[0x20];
1639
1640         u8         ether_stats_drop_events_low[0x20];
1641
1642         u8         ether_stats_octets_high[0x20];
1643
1644         u8         ether_stats_octets_low[0x20];
1645
1646         u8         ether_stats_pkts_high[0x20];
1647
1648         u8         ether_stats_pkts_low[0x20];
1649
1650         u8         ether_stats_broadcast_pkts_high[0x20];
1651
1652         u8         ether_stats_broadcast_pkts_low[0x20];
1653
1654         u8         ether_stats_multicast_pkts_high[0x20];
1655
1656         u8         ether_stats_multicast_pkts_low[0x20];
1657
1658         u8         ether_stats_crc_align_errors_high[0x20];
1659
1660         u8         ether_stats_crc_align_errors_low[0x20];
1661
1662         u8         ether_stats_undersize_pkts_high[0x20];
1663
1664         u8         ether_stats_undersize_pkts_low[0x20];
1665
1666         u8         ether_stats_oversize_pkts_high[0x20];
1667
1668         u8         ether_stats_oversize_pkts_low[0x20];
1669
1670         u8         ether_stats_fragments_high[0x20];
1671
1672         u8         ether_stats_fragments_low[0x20];
1673
1674         u8         ether_stats_jabbers_high[0x20];
1675
1676         u8         ether_stats_jabbers_low[0x20];
1677
1678         u8         ether_stats_collisions_high[0x20];
1679
1680         u8         ether_stats_collisions_low[0x20];
1681
1682         u8         ether_stats_pkts64octets_high[0x20];
1683
1684         u8         ether_stats_pkts64octets_low[0x20];
1685
1686         u8         ether_stats_pkts65to127octets_high[0x20];
1687
1688         u8         ether_stats_pkts65to127octets_low[0x20];
1689
1690         u8         ether_stats_pkts128to255octets_high[0x20];
1691
1692         u8         ether_stats_pkts128to255octets_low[0x20];
1693
1694         u8         ether_stats_pkts256to511octets_high[0x20];
1695
1696         u8         ether_stats_pkts256to511octets_low[0x20];
1697
1698         u8         ether_stats_pkts512to1023octets_high[0x20];
1699
1700         u8         ether_stats_pkts512to1023octets_low[0x20];
1701
1702         u8         ether_stats_pkts1024to1518octets_high[0x20];
1703
1704         u8         ether_stats_pkts1024to1518octets_low[0x20];
1705
1706         u8         ether_stats_pkts1519to2047octets_high[0x20];
1707
1708         u8         ether_stats_pkts1519to2047octets_low[0x20];
1709
1710         u8         ether_stats_pkts2048to4095octets_high[0x20];
1711
1712         u8         ether_stats_pkts2048to4095octets_low[0x20];
1713
1714         u8         ether_stats_pkts4096to8191octets_high[0x20];
1715
1716         u8         ether_stats_pkts4096to8191octets_low[0x20];
1717
1718         u8         ether_stats_pkts8192to10239octets_high[0x20];
1719
1720         u8         ether_stats_pkts8192to10239octets_low[0x20];
1721
1722         u8         reserved_at_540[0x280];
1723 };
1724
1725 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1726         u8         if_in_octets_high[0x20];
1727
1728         u8         if_in_octets_low[0x20];
1729
1730         u8         if_in_ucast_pkts_high[0x20];
1731
1732         u8         if_in_ucast_pkts_low[0x20];
1733
1734         u8         if_in_discards_high[0x20];
1735
1736         u8         if_in_discards_low[0x20];
1737
1738         u8         if_in_errors_high[0x20];
1739
1740         u8         if_in_errors_low[0x20];
1741
1742         u8         if_in_unknown_protos_high[0x20];
1743
1744         u8         if_in_unknown_protos_low[0x20];
1745
1746         u8         if_out_octets_high[0x20];
1747
1748         u8         if_out_octets_low[0x20];
1749
1750         u8         if_out_ucast_pkts_high[0x20];
1751
1752         u8         if_out_ucast_pkts_low[0x20];
1753
1754         u8         if_out_discards_high[0x20];
1755
1756         u8         if_out_discards_low[0x20];
1757
1758         u8         if_out_errors_high[0x20];
1759
1760         u8         if_out_errors_low[0x20];
1761
1762         u8         if_in_multicast_pkts_high[0x20];
1763
1764         u8         if_in_multicast_pkts_low[0x20];
1765
1766         u8         if_in_broadcast_pkts_high[0x20];
1767
1768         u8         if_in_broadcast_pkts_low[0x20];
1769
1770         u8         if_out_multicast_pkts_high[0x20];
1771
1772         u8         if_out_multicast_pkts_low[0x20];
1773
1774         u8         if_out_broadcast_pkts_high[0x20];
1775
1776         u8         if_out_broadcast_pkts_low[0x20];
1777
1778         u8         reserved_at_340[0x480];
1779 };
1780
1781 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1782         u8         a_frames_transmitted_ok_high[0x20];
1783
1784         u8         a_frames_transmitted_ok_low[0x20];
1785
1786         u8         a_frames_received_ok_high[0x20];
1787
1788         u8         a_frames_received_ok_low[0x20];
1789
1790         u8         a_frame_check_sequence_errors_high[0x20];
1791
1792         u8         a_frame_check_sequence_errors_low[0x20];
1793
1794         u8         a_alignment_errors_high[0x20];
1795
1796         u8         a_alignment_errors_low[0x20];
1797
1798         u8         a_octets_transmitted_ok_high[0x20];
1799
1800         u8         a_octets_transmitted_ok_low[0x20];
1801
1802         u8         a_octets_received_ok_high[0x20];
1803
1804         u8         a_octets_received_ok_low[0x20];
1805
1806         u8         a_multicast_frames_xmitted_ok_high[0x20];
1807
1808         u8         a_multicast_frames_xmitted_ok_low[0x20];
1809
1810         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1811
1812         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1813
1814         u8         a_multicast_frames_received_ok_high[0x20];
1815
1816         u8         a_multicast_frames_received_ok_low[0x20];
1817
1818         u8         a_broadcast_frames_received_ok_high[0x20];
1819
1820         u8         a_broadcast_frames_received_ok_low[0x20];
1821
1822         u8         a_in_range_length_errors_high[0x20];
1823
1824         u8         a_in_range_length_errors_low[0x20];
1825
1826         u8         a_out_of_range_length_field_high[0x20];
1827
1828         u8         a_out_of_range_length_field_low[0x20];
1829
1830         u8         a_frame_too_long_errors_high[0x20];
1831
1832         u8         a_frame_too_long_errors_low[0x20];
1833
1834         u8         a_symbol_error_during_carrier_high[0x20];
1835
1836         u8         a_symbol_error_during_carrier_low[0x20];
1837
1838         u8         a_mac_control_frames_transmitted_high[0x20];
1839
1840         u8         a_mac_control_frames_transmitted_low[0x20];
1841
1842         u8         a_mac_control_frames_received_high[0x20];
1843
1844         u8         a_mac_control_frames_received_low[0x20];
1845
1846         u8         a_unsupported_opcodes_received_high[0x20];
1847
1848         u8         a_unsupported_opcodes_received_low[0x20];
1849
1850         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1851
1852         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1853
1854         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1855
1856         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1857
1858         u8         reserved_at_4c0[0x300];
1859 };
1860
1861 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1862         u8         life_time_counter_high[0x20];
1863
1864         u8         life_time_counter_low[0x20];
1865
1866         u8         rx_errors[0x20];
1867
1868         u8         tx_errors[0x20];
1869
1870         u8         l0_to_recovery_eieos[0x20];
1871
1872         u8         l0_to_recovery_ts[0x20];
1873
1874         u8         l0_to_recovery_framing[0x20];
1875
1876         u8         l0_to_recovery_retrain[0x20];
1877
1878         u8         crc_error_dllp[0x20];
1879
1880         u8         crc_error_tlp[0x20];
1881
1882         u8         tx_overflow_buffer_pkt_high[0x20];
1883
1884         u8         tx_overflow_buffer_pkt_low[0x20];
1885
1886         u8         outbound_stalled_reads[0x20];
1887
1888         u8         outbound_stalled_writes[0x20];
1889
1890         u8         outbound_stalled_reads_events[0x20];
1891
1892         u8         outbound_stalled_writes_events[0x20];
1893
1894         u8         reserved_at_200[0x5c0];
1895 };
1896
1897 struct mlx5_ifc_cmd_inter_comp_event_bits {
1898         u8         command_completion_vector[0x20];
1899
1900         u8         reserved_at_20[0xc0];
1901 };
1902
1903 struct mlx5_ifc_stall_vl_event_bits {
1904         u8         reserved_at_0[0x18];
1905         u8         port_num[0x1];
1906         u8         reserved_at_19[0x3];
1907         u8         vl[0x4];
1908
1909         u8         reserved_at_20[0xa0];
1910 };
1911
1912 struct mlx5_ifc_db_bf_congestion_event_bits {
1913         u8         event_subtype[0x8];
1914         u8         reserved_at_8[0x8];
1915         u8         congestion_level[0x8];
1916         u8         reserved_at_18[0x8];
1917
1918         u8         reserved_at_20[0xa0];
1919 };
1920
1921 struct mlx5_ifc_gpio_event_bits {
1922         u8         reserved_at_0[0x60];
1923
1924         u8         gpio_event_hi[0x20];
1925
1926         u8         gpio_event_lo[0x20];
1927
1928         u8         reserved_at_a0[0x40];
1929 };
1930
1931 struct mlx5_ifc_port_state_change_event_bits {
1932         u8         reserved_at_0[0x40];
1933
1934         u8         port_num[0x4];
1935         u8         reserved_at_44[0x1c];
1936
1937         u8         reserved_at_60[0x80];
1938 };
1939
1940 struct mlx5_ifc_dropped_packet_logged_bits {
1941         u8         reserved_at_0[0xe0];
1942 };
1943
1944 enum {
1945         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1946         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1947 };
1948
1949 struct mlx5_ifc_cq_error_bits {
1950         u8         reserved_at_0[0x8];
1951         u8         cqn[0x18];
1952
1953         u8         reserved_at_20[0x20];
1954
1955         u8         reserved_at_40[0x18];
1956         u8         syndrome[0x8];
1957
1958         u8         reserved_at_60[0x80];
1959 };
1960
1961 struct mlx5_ifc_rdma_page_fault_event_bits {
1962         u8         bytes_committed[0x20];
1963
1964         u8         r_key[0x20];
1965
1966         u8         reserved_at_40[0x10];
1967         u8         packet_len[0x10];
1968
1969         u8         rdma_op_len[0x20];
1970
1971         u8         rdma_va[0x40];
1972
1973         u8         reserved_at_c0[0x5];
1974         u8         rdma[0x1];
1975         u8         write[0x1];
1976         u8         requestor[0x1];
1977         u8         qp_number[0x18];
1978 };
1979
1980 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1981         u8         bytes_committed[0x20];
1982
1983         u8         reserved_at_20[0x10];
1984         u8         wqe_index[0x10];
1985
1986         u8         reserved_at_40[0x10];
1987         u8         len[0x10];
1988
1989         u8         reserved_at_60[0x60];
1990
1991         u8         reserved_at_c0[0x5];
1992         u8         rdma[0x1];
1993         u8         write_read[0x1];
1994         u8         requestor[0x1];
1995         u8         qpn[0x18];
1996 };
1997
1998 struct mlx5_ifc_qp_events_bits {
1999         u8         reserved_at_0[0xa0];
2000
2001         u8         type[0x8];
2002         u8         reserved_at_a8[0x18];
2003
2004         u8         reserved_at_c0[0x8];
2005         u8         qpn_rqn_sqn[0x18];
2006 };
2007
2008 struct mlx5_ifc_dct_events_bits {
2009         u8         reserved_at_0[0xc0];
2010
2011         u8         reserved_at_c0[0x8];
2012         u8         dct_number[0x18];
2013 };
2014
2015 struct mlx5_ifc_comp_event_bits {
2016         u8         reserved_at_0[0xc0];
2017
2018         u8         reserved_at_c0[0x8];
2019         u8         cq_number[0x18];
2020 };
2021
2022 enum {
2023         MLX5_QPC_STATE_RST        = 0x0,
2024         MLX5_QPC_STATE_INIT       = 0x1,
2025         MLX5_QPC_STATE_RTR        = 0x2,
2026         MLX5_QPC_STATE_RTS        = 0x3,
2027         MLX5_QPC_STATE_SQER       = 0x4,
2028         MLX5_QPC_STATE_ERR        = 0x6,
2029         MLX5_QPC_STATE_SQD        = 0x7,
2030         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2031 };
2032
2033 enum {
2034         MLX5_QPC_ST_RC            = 0x0,
2035         MLX5_QPC_ST_UC            = 0x1,
2036         MLX5_QPC_ST_UD            = 0x2,
2037         MLX5_QPC_ST_XRC           = 0x3,
2038         MLX5_QPC_ST_DCI           = 0x5,
2039         MLX5_QPC_ST_QP0           = 0x7,
2040         MLX5_QPC_ST_QP1           = 0x8,
2041         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2042         MLX5_QPC_ST_REG_UMR       = 0xc,
2043 };
2044
2045 enum {
2046         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2047         MLX5_QPC_PM_STATE_REARM     = 0x1,
2048         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2049         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2050 };
2051
2052 enum {
2053         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2054 };
2055
2056 enum {
2057         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2058         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2059 };
2060
2061 enum {
2062         MLX5_QPC_MTU_256_BYTES        = 0x1,
2063         MLX5_QPC_MTU_512_BYTES        = 0x2,
2064         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2065         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2066         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2067         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2068 };
2069
2070 enum {
2071         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2072         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2073         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2074         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2075         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2076         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2077         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2078         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2079 };
2080
2081 enum {
2082         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2083         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2084         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2085 };
2086
2087 enum {
2088         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2089         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2090         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2091 };
2092
2093 struct mlx5_ifc_qpc_bits {
2094         u8         state[0x4];
2095         u8         lag_tx_port_affinity[0x4];
2096         u8         st[0x8];
2097         u8         reserved_at_10[0x3];
2098         u8         pm_state[0x2];
2099         u8         reserved_at_15[0x3];
2100         u8         offload_type[0x4];
2101         u8         end_padding_mode[0x2];
2102         u8         reserved_at_1e[0x2];
2103
2104         u8         wq_signature[0x1];
2105         u8         block_lb_mc[0x1];
2106         u8         atomic_like_write_en[0x1];
2107         u8         latency_sensitive[0x1];
2108         u8         reserved_at_24[0x1];
2109         u8         drain_sigerr[0x1];
2110         u8         reserved_at_26[0x2];
2111         u8         pd[0x18];
2112
2113         u8         mtu[0x3];
2114         u8         log_msg_max[0x5];
2115         u8         reserved_at_48[0x1];
2116         u8         log_rq_size[0x4];
2117         u8         log_rq_stride[0x3];
2118         u8         no_sq[0x1];
2119         u8         log_sq_size[0x4];
2120         u8         reserved_at_55[0x6];
2121         u8         rlky[0x1];
2122         u8         ulp_stateless_offload_mode[0x4];
2123
2124         u8         counter_set_id[0x8];
2125         u8         uar_page[0x18];
2126
2127         u8         reserved_at_80[0x8];
2128         u8         user_index[0x18];
2129
2130         u8         reserved_at_a0[0x3];
2131         u8         log_page_size[0x5];
2132         u8         remote_qpn[0x18];
2133
2134         struct mlx5_ifc_ads_bits primary_address_path;
2135
2136         struct mlx5_ifc_ads_bits secondary_address_path;
2137
2138         u8         log_ack_req_freq[0x4];
2139         u8         reserved_at_384[0x4];
2140         u8         log_sra_max[0x3];
2141         u8         reserved_at_38b[0x2];
2142         u8         retry_count[0x3];
2143         u8         rnr_retry[0x3];
2144         u8         reserved_at_393[0x1];
2145         u8         fre[0x1];
2146         u8         cur_rnr_retry[0x3];
2147         u8         cur_retry_count[0x3];
2148         u8         reserved_at_39b[0x5];
2149
2150         u8         reserved_at_3a0[0x20];
2151
2152         u8         reserved_at_3c0[0x8];
2153         u8         next_send_psn[0x18];
2154
2155         u8         reserved_at_3e0[0x8];
2156         u8         cqn_snd[0x18];
2157
2158         u8         reserved_at_400[0x8];
2159         u8         deth_sqpn[0x18];
2160
2161         u8         reserved_at_420[0x20];
2162
2163         u8         reserved_at_440[0x8];
2164         u8         last_acked_psn[0x18];
2165
2166         u8         reserved_at_460[0x8];
2167         u8         ssn[0x18];
2168
2169         u8         reserved_at_480[0x8];
2170         u8         log_rra_max[0x3];
2171         u8         reserved_at_48b[0x1];
2172         u8         atomic_mode[0x4];
2173         u8         rre[0x1];
2174         u8         rwe[0x1];
2175         u8         rae[0x1];
2176         u8         reserved_at_493[0x1];
2177         u8         page_offset[0x6];
2178         u8         reserved_at_49a[0x3];
2179         u8         cd_slave_receive[0x1];
2180         u8         cd_slave_send[0x1];
2181         u8         cd_master[0x1];
2182
2183         u8         reserved_at_4a0[0x3];
2184         u8         min_rnr_nak[0x5];
2185         u8         next_rcv_psn[0x18];
2186
2187         u8         reserved_at_4c0[0x8];
2188         u8         xrcd[0x18];
2189
2190         u8         reserved_at_4e0[0x8];
2191         u8         cqn_rcv[0x18];
2192
2193         u8         dbr_addr[0x40];
2194
2195         u8         q_key[0x20];
2196
2197         u8         reserved_at_560[0x5];
2198         u8         rq_type[0x3];
2199         u8         srqn_rmpn_xrqn[0x18];
2200
2201         u8         reserved_at_580[0x8];
2202         u8         rmsn[0x18];
2203
2204         u8         hw_sq_wqebb_counter[0x10];
2205         u8         sw_sq_wqebb_counter[0x10];
2206
2207         u8         hw_rq_counter[0x20];
2208
2209         u8         sw_rq_counter[0x20];
2210
2211         u8         reserved_at_600[0x20];
2212
2213         u8         reserved_at_620[0xf];
2214         u8         cgs[0x1];
2215         u8         cs_req[0x8];
2216         u8         cs_res[0x8];
2217
2218         u8         dc_access_key[0x40];
2219
2220         u8         reserved_at_680[0xc0];
2221 };
2222
2223 struct mlx5_ifc_roce_addr_layout_bits {
2224         u8         source_l3_address[16][0x8];
2225
2226         u8         reserved_at_80[0x3];
2227         u8         vlan_valid[0x1];
2228         u8         vlan_id[0xc];
2229         u8         source_mac_47_32[0x10];
2230
2231         u8         source_mac_31_0[0x20];
2232
2233         u8         reserved_at_c0[0x14];
2234         u8         roce_l3_type[0x4];
2235         u8         roce_version[0x8];
2236
2237         u8         reserved_at_e0[0x20];
2238 };
2239
2240 union mlx5_ifc_hca_cap_union_bits {
2241         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2242         struct mlx5_ifc_odp_cap_bits odp_cap;
2243         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2244         struct mlx5_ifc_roce_cap_bits roce_cap;
2245         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2246         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2247         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2248         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2249         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2250         struct mlx5_ifc_qos_cap_bits qos_cap;
2251         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2252         u8         reserved_at_0[0x8000];
2253 };
2254
2255 enum {
2256         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2257         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2258         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2259         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2260         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2261         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2262         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2263 };
2264
2265 struct mlx5_ifc_flow_context_bits {
2266         u8         reserved_at_0[0x20];
2267
2268         u8         group_id[0x20];
2269
2270         u8         reserved_at_40[0x8];
2271         u8         flow_tag[0x18];
2272
2273         u8         reserved_at_60[0x10];
2274         u8         action[0x10];
2275
2276         u8         reserved_at_80[0x8];
2277         u8         destination_list_size[0x18];
2278
2279         u8         reserved_at_a0[0x8];
2280         u8         flow_counter_list_size[0x18];
2281
2282         u8         encap_id[0x20];
2283
2284         u8         modify_header_id[0x20];
2285
2286         u8         reserved_at_100[0x100];
2287
2288         struct mlx5_ifc_fte_match_param_bits match_value;
2289
2290         u8         reserved_at_1200[0x600];
2291
2292         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2293 };
2294
2295 enum {
2296         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2297         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2298 };
2299
2300 struct mlx5_ifc_xrc_srqc_bits {
2301         u8         state[0x4];
2302         u8         log_xrc_srq_size[0x4];
2303         u8         reserved_at_8[0x18];
2304
2305         u8         wq_signature[0x1];
2306         u8         cont_srq[0x1];
2307         u8         reserved_at_22[0x1];
2308         u8         rlky[0x1];
2309         u8         basic_cyclic_rcv_wqe[0x1];
2310         u8         log_rq_stride[0x3];
2311         u8         xrcd[0x18];
2312
2313         u8         page_offset[0x6];
2314         u8         reserved_at_46[0x2];
2315         u8         cqn[0x18];
2316
2317         u8         reserved_at_60[0x20];
2318
2319         u8         user_index_equal_xrc_srqn[0x1];
2320         u8         reserved_at_81[0x1];
2321         u8         log_page_size[0x6];
2322         u8         user_index[0x18];
2323
2324         u8         reserved_at_a0[0x20];
2325
2326         u8         reserved_at_c0[0x8];
2327         u8         pd[0x18];
2328
2329         u8         lwm[0x10];
2330         u8         wqe_cnt[0x10];
2331
2332         u8         reserved_at_100[0x40];
2333
2334         u8         db_record_addr_h[0x20];
2335
2336         u8         db_record_addr_l[0x1e];
2337         u8         reserved_at_17e[0x2];
2338
2339         u8         reserved_at_180[0x80];
2340 };
2341
2342 struct mlx5_ifc_traffic_counter_bits {
2343         u8         packets[0x40];
2344
2345         u8         octets[0x40];
2346 };
2347
2348 struct mlx5_ifc_tisc_bits {
2349         u8         strict_lag_tx_port_affinity[0x1];
2350         u8         reserved_at_1[0x3];
2351         u8         lag_tx_port_affinity[0x04];
2352
2353         u8         reserved_at_8[0x4];
2354         u8         prio[0x4];
2355         u8         reserved_at_10[0x10];
2356
2357         u8         reserved_at_20[0x100];
2358
2359         u8         reserved_at_120[0x8];
2360         u8         transport_domain[0x18];
2361
2362         u8         reserved_at_140[0x8];
2363         u8         underlay_qpn[0x18];
2364         u8         reserved_at_160[0x3a0];
2365 };
2366
2367 enum {
2368         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2369         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2370 };
2371
2372 enum {
2373         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2374         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2375 };
2376
2377 enum {
2378         MLX5_RX_HASH_FN_NONE           = 0x0,
2379         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2380         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2381 };
2382
2383 enum {
2384         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2385         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2386 };
2387
2388 struct mlx5_ifc_tirc_bits {
2389         u8         reserved_at_0[0x20];
2390
2391         u8         disp_type[0x4];
2392         u8         reserved_at_24[0x1c];
2393
2394         u8         reserved_at_40[0x40];
2395
2396         u8         reserved_at_80[0x4];
2397         u8         lro_timeout_period_usecs[0x10];
2398         u8         lro_enable_mask[0x4];
2399         u8         lro_max_ip_payload_size[0x8];
2400
2401         u8         reserved_at_a0[0x40];
2402
2403         u8         reserved_at_e0[0x8];
2404         u8         inline_rqn[0x18];
2405
2406         u8         rx_hash_symmetric[0x1];
2407         u8         reserved_at_101[0x1];
2408         u8         tunneled_offload_en[0x1];
2409         u8         reserved_at_103[0x5];
2410         u8         indirect_table[0x18];
2411
2412         u8         rx_hash_fn[0x4];
2413         u8         reserved_at_124[0x2];
2414         u8         self_lb_block[0x2];
2415         u8         transport_domain[0x18];
2416
2417         u8         rx_hash_toeplitz_key[10][0x20];
2418
2419         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2420
2421         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2422
2423         u8         reserved_at_2c0[0x4c0];
2424 };
2425
2426 enum {
2427         MLX5_SRQC_STATE_GOOD   = 0x0,
2428         MLX5_SRQC_STATE_ERROR  = 0x1,
2429 };
2430
2431 struct mlx5_ifc_srqc_bits {
2432         u8         state[0x4];
2433         u8         log_srq_size[0x4];
2434         u8         reserved_at_8[0x18];
2435
2436         u8         wq_signature[0x1];
2437         u8         cont_srq[0x1];
2438         u8         reserved_at_22[0x1];
2439         u8         rlky[0x1];
2440         u8         reserved_at_24[0x1];
2441         u8         log_rq_stride[0x3];
2442         u8         xrcd[0x18];
2443
2444         u8         page_offset[0x6];
2445         u8         reserved_at_46[0x2];
2446         u8         cqn[0x18];
2447
2448         u8         reserved_at_60[0x20];
2449
2450         u8         reserved_at_80[0x2];
2451         u8         log_page_size[0x6];
2452         u8         reserved_at_88[0x18];
2453
2454         u8         reserved_at_a0[0x20];
2455
2456         u8         reserved_at_c0[0x8];
2457         u8         pd[0x18];
2458
2459         u8         lwm[0x10];
2460         u8         wqe_cnt[0x10];
2461
2462         u8         reserved_at_100[0x40];
2463
2464         u8         dbr_addr[0x40];
2465
2466         u8         reserved_at_180[0x80];
2467 };
2468
2469 enum {
2470         MLX5_SQC_STATE_RST  = 0x0,
2471         MLX5_SQC_STATE_RDY  = 0x1,
2472         MLX5_SQC_STATE_ERR  = 0x3,
2473 };
2474
2475 struct mlx5_ifc_sqc_bits {
2476         u8         rlky[0x1];
2477         u8         cd_master[0x1];
2478         u8         fre[0x1];
2479         u8         flush_in_error_en[0x1];
2480         u8         allow_multi_pkt_send_wqe[0x1];
2481         u8         min_wqe_inline_mode[0x3];
2482         u8         state[0x4];
2483         u8         reg_umr[0x1];
2484         u8         allow_swp[0x1];
2485         u8         reserved_at_e[0x12];
2486
2487         u8         reserved_at_20[0x8];
2488         u8         user_index[0x18];
2489
2490         u8         reserved_at_40[0x8];
2491         u8         cqn[0x18];
2492
2493         u8         reserved_at_60[0x90];
2494
2495         u8         packet_pacing_rate_limit_index[0x10];
2496         u8         tis_lst_sz[0x10];
2497         u8         reserved_at_110[0x10];
2498
2499         u8         reserved_at_120[0x40];
2500
2501         u8         reserved_at_160[0x8];
2502         u8         tis_num_0[0x18];
2503
2504         struct mlx5_ifc_wq_bits wq;
2505 };
2506
2507 enum {
2508         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2509         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2510         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2511         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2512 };
2513
2514 struct mlx5_ifc_scheduling_context_bits {
2515         u8         element_type[0x8];
2516         u8         reserved_at_8[0x18];
2517
2518         u8         element_attributes[0x20];
2519
2520         u8         parent_element_id[0x20];
2521
2522         u8         reserved_at_60[0x40];
2523
2524         u8         bw_share[0x20];
2525
2526         u8         max_average_bw[0x20];
2527
2528         u8         reserved_at_e0[0x120];
2529 };
2530
2531 struct mlx5_ifc_rqtc_bits {
2532         u8         reserved_at_0[0xa0];
2533
2534         u8         reserved_at_a0[0x10];
2535         u8         rqt_max_size[0x10];
2536
2537         u8         reserved_at_c0[0x10];
2538         u8         rqt_actual_size[0x10];
2539
2540         u8         reserved_at_e0[0x6a0];
2541
2542         struct mlx5_ifc_rq_num_bits rq_num[0];
2543 };
2544
2545 enum {
2546         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2547         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2548 };
2549
2550 enum {
2551         MLX5_RQC_STATE_RST  = 0x0,
2552         MLX5_RQC_STATE_RDY  = 0x1,
2553         MLX5_RQC_STATE_ERR  = 0x3,
2554 };
2555
2556 struct mlx5_ifc_rqc_bits {
2557         u8         rlky[0x1];
2558         u8         delay_drop_en[0x1];
2559         u8         scatter_fcs[0x1];
2560         u8         vsd[0x1];
2561         u8         mem_rq_type[0x4];
2562         u8         state[0x4];
2563         u8         reserved_at_c[0x1];
2564         u8         flush_in_error_en[0x1];
2565         u8         reserved_at_e[0x12];
2566
2567         u8         reserved_at_20[0x8];
2568         u8         user_index[0x18];
2569
2570         u8         reserved_at_40[0x8];
2571         u8         cqn[0x18];
2572
2573         u8         counter_set_id[0x8];
2574         u8         reserved_at_68[0x18];
2575
2576         u8         reserved_at_80[0x8];
2577         u8         rmpn[0x18];
2578
2579         u8         reserved_at_a0[0xe0];
2580
2581         struct mlx5_ifc_wq_bits wq;
2582 };
2583
2584 enum {
2585         MLX5_RMPC_STATE_RDY  = 0x1,
2586         MLX5_RMPC_STATE_ERR  = 0x3,
2587 };
2588
2589 struct mlx5_ifc_rmpc_bits {
2590         u8         reserved_at_0[0x8];
2591         u8         state[0x4];
2592         u8         reserved_at_c[0x14];
2593
2594         u8         basic_cyclic_rcv_wqe[0x1];
2595         u8         reserved_at_21[0x1f];
2596
2597         u8         reserved_at_40[0x140];
2598
2599         struct mlx5_ifc_wq_bits wq;
2600 };
2601
2602 struct mlx5_ifc_nic_vport_context_bits {
2603         u8         reserved_at_0[0x5];
2604         u8         min_wqe_inline_mode[0x3];
2605         u8         reserved_at_8[0x15];
2606         u8         disable_mc_local_lb[0x1];
2607         u8         disable_uc_local_lb[0x1];
2608         u8         roce_en[0x1];
2609
2610         u8         arm_change_event[0x1];
2611         u8         reserved_at_21[0x1a];
2612         u8         event_on_mtu[0x1];
2613         u8         event_on_promisc_change[0x1];
2614         u8         event_on_vlan_change[0x1];
2615         u8         event_on_mc_address_change[0x1];
2616         u8         event_on_uc_address_change[0x1];
2617
2618         u8         reserved_at_40[0xf0];
2619
2620         u8         mtu[0x10];
2621
2622         u8         system_image_guid[0x40];
2623         u8         port_guid[0x40];
2624         u8         node_guid[0x40];
2625
2626         u8         reserved_at_200[0x140];
2627         u8         qkey_violation_counter[0x10];
2628         u8         reserved_at_350[0x430];
2629
2630         u8         promisc_uc[0x1];
2631         u8         promisc_mc[0x1];
2632         u8         promisc_all[0x1];
2633         u8         reserved_at_783[0x2];
2634         u8         allowed_list_type[0x3];
2635         u8         reserved_at_788[0xc];
2636         u8         allowed_list_size[0xc];
2637
2638         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2639
2640         u8         reserved_at_7e0[0x20];
2641
2642         u8         current_uc_mac_address[0][0x40];
2643 };
2644
2645 enum {
2646         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2647         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2648         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2649         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2650 };
2651
2652 struct mlx5_ifc_mkc_bits {
2653         u8         reserved_at_0[0x1];
2654         u8         free[0x1];
2655         u8         reserved_at_2[0xd];
2656         u8         small_fence_on_rdma_read_response[0x1];
2657         u8         umr_en[0x1];
2658         u8         a[0x1];
2659         u8         rw[0x1];
2660         u8         rr[0x1];
2661         u8         lw[0x1];
2662         u8         lr[0x1];
2663         u8         access_mode[0x2];
2664         u8         reserved_at_18[0x8];
2665
2666         u8         qpn[0x18];
2667         u8         mkey_7_0[0x8];
2668
2669         u8         reserved_at_40[0x20];
2670
2671         u8         length64[0x1];
2672         u8         bsf_en[0x1];
2673         u8         sync_umr[0x1];
2674         u8         reserved_at_63[0x2];
2675         u8         expected_sigerr_count[0x1];
2676         u8         reserved_at_66[0x1];
2677         u8         en_rinval[0x1];
2678         u8         pd[0x18];
2679
2680         u8         start_addr[0x40];
2681
2682         u8         len[0x40];
2683
2684         u8         bsf_octword_size[0x20];
2685
2686         u8         reserved_at_120[0x80];
2687
2688         u8         translations_octword_size[0x20];
2689
2690         u8         reserved_at_1c0[0x1b];
2691         u8         log_page_size[0x5];
2692
2693         u8         reserved_at_1e0[0x20];
2694 };
2695
2696 struct mlx5_ifc_pkey_bits {
2697         u8         reserved_at_0[0x10];
2698         u8         pkey[0x10];
2699 };
2700
2701 struct mlx5_ifc_array128_auto_bits {
2702         u8         array128_auto[16][0x8];
2703 };
2704
2705 struct mlx5_ifc_hca_vport_context_bits {
2706         u8         field_select[0x20];
2707
2708         u8         reserved_at_20[0xe0];
2709
2710         u8         sm_virt_aware[0x1];
2711         u8         has_smi[0x1];
2712         u8         has_raw[0x1];
2713         u8         grh_required[0x1];
2714         u8         reserved_at_104[0xc];
2715         u8         port_physical_state[0x4];
2716         u8         vport_state_policy[0x4];
2717         u8         port_state[0x4];
2718         u8         vport_state[0x4];
2719
2720         u8         reserved_at_120[0x20];
2721
2722         u8         system_image_guid[0x40];
2723
2724         u8         port_guid[0x40];
2725
2726         u8         node_guid[0x40];
2727
2728         u8         cap_mask1[0x20];
2729
2730         u8         cap_mask1_field_select[0x20];
2731
2732         u8         cap_mask2[0x20];
2733
2734         u8         cap_mask2_field_select[0x20];
2735
2736         u8         reserved_at_280[0x80];
2737
2738         u8         lid[0x10];
2739         u8         reserved_at_310[0x4];
2740         u8         init_type_reply[0x4];
2741         u8         lmc[0x3];
2742         u8         subnet_timeout[0x5];
2743
2744         u8         sm_lid[0x10];
2745         u8         sm_sl[0x4];
2746         u8         reserved_at_334[0xc];
2747
2748         u8         qkey_violation_counter[0x10];
2749         u8         pkey_violation_counter[0x10];
2750
2751         u8         reserved_at_360[0xca0];
2752 };
2753
2754 struct mlx5_ifc_esw_vport_context_bits {
2755         u8         reserved_at_0[0x3];
2756         u8         vport_svlan_strip[0x1];
2757         u8         vport_cvlan_strip[0x1];
2758         u8         vport_svlan_insert[0x1];
2759         u8         vport_cvlan_insert[0x2];
2760         u8         reserved_at_8[0x18];
2761
2762         u8         reserved_at_20[0x20];
2763
2764         u8         svlan_cfi[0x1];
2765         u8         svlan_pcp[0x3];
2766         u8         svlan_id[0xc];
2767         u8         cvlan_cfi[0x1];
2768         u8         cvlan_pcp[0x3];
2769         u8         cvlan_id[0xc];
2770
2771         u8         reserved_at_60[0x7a0];
2772 };
2773
2774 enum {
2775         MLX5_EQC_STATUS_OK                = 0x0,
2776         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2777 };
2778
2779 enum {
2780         MLX5_EQC_ST_ARMED  = 0x9,
2781         MLX5_EQC_ST_FIRED  = 0xa,
2782 };
2783
2784 struct mlx5_ifc_eqc_bits {
2785         u8         status[0x4];
2786         u8         reserved_at_4[0x9];
2787         u8         ec[0x1];
2788         u8         oi[0x1];
2789         u8         reserved_at_f[0x5];
2790         u8         st[0x4];
2791         u8         reserved_at_18[0x8];
2792
2793         u8         reserved_at_20[0x20];
2794
2795         u8         reserved_at_40[0x14];
2796         u8         page_offset[0x6];
2797         u8         reserved_at_5a[0x6];
2798
2799         u8         reserved_at_60[0x3];
2800         u8         log_eq_size[0x5];
2801         u8         uar_page[0x18];
2802
2803         u8         reserved_at_80[0x20];
2804
2805         u8         reserved_at_a0[0x18];
2806         u8         intr[0x8];
2807
2808         u8         reserved_at_c0[0x3];
2809         u8         log_page_size[0x5];
2810         u8         reserved_at_c8[0x18];
2811
2812         u8         reserved_at_e0[0x60];
2813
2814         u8         reserved_at_140[0x8];
2815         u8         consumer_counter[0x18];
2816
2817         u8         reserved_at_160[0x8];
2818         u8         producer_counter[0x18];
2819
2820         u8         reserved_at_180[0x80];
2821 };
2822
2823 enum {
2824         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2825         MLX5_DCTC_STATE_DRAINING  = 0x1,
2826         MLX5_DCTC_STATE_DRAINED   = 0x2,
2827 };
2828
2829 enum {
2830         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2831         MLX5_DCTC_CS_RES_NA         = 0x1,
2832         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2833 };
2834
2835 enum {
2836         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2837         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2838         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2839         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2840         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2841 };
2842
2843 struct mlx5_ifc_dctc_bits {
2844         u8         reserved_at_0[0x4];
2845         u8         state[0x4];
2846         u8         reserved_at_8[0x18];
2847
2848         u8         reserved_at_20[0x8];
2849         u8         user_index[0x18];
2850
2851         u8         reserved_at_40[0x8];
2852         u8         cqn[0x18];
2853
2854         u8         counter_set_id[0x8];
2855         u8         atomic_mode[0x4];
2856         u8         rre[0x1];
2857         u8         rwe[0x1];
2858         u8         rae[0x1];
2859         u8         atomic_like_write_en[0x1];
2860         u8         latency_sensitive[0x1];
2861         u8         rlky[0x1];
2862         u8         free_ar[0x1];
2863         u8         reserved_at_73[0xd];
2864
2865         u8         reserved_at_80[0x8];
2866         u8         cs_res[0x8];
2867         u8         reserved_at_90[0x3];
2868         u8         min_rnr_nak[0x5];
2869         u8         reserved_at_98[0x8];
2870
2871         u8         reserved_at_a0[0x8];
2872         u8         srqn_xrqn[0x18];
2873
2874         u8         reserved_at_c0[0x8];
2875         u8         pd[0x18];
2876
2877         u8         tclass[0x8];
2878         u8         reserved_at_e8[0x4];
2879         u8         flow_label[0x14];
2880
2881         u8         dc_access_key[0x40];
2882
2883         u8         reserved_at_140[0x5];
2884         u8         mtu[0x3];
2885         u8         port[0x8];
2886         u8         pkey_index[0x10];
2887
2888         u8         reserved_at_160[0x8];
2889         u8         my_addr_index[0x8];
2890         u8         reserved_at_170[0x8];
2891         u8         hop_limit[0x8];
2892
2893         u8         dc_access_key_violation_count[0x20];
2894
2895         u8         reserved_at_1a0[0x14];
2896         u8         dei_cfi[0x1];
2897         u8         eth_prio[0x3];
2898         u8         ecn[0x2];
2899         u8         dscp[0x6];
2900
2901         u8         reserved_at_1c0[0x40];
2902 };
2903
2904 enum {
2905         MLX5_CQC_STATUS_OK             = 0x0,
2906         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2907         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2908 };
2909
2910 enum {
2911         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2912         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2913 };
2914
2915 enum {
2916         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2917         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2918         MLX5_CQC_ST_FIRED                                 = 0xa,
2919 };
2920
2921 enum {
2922         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2923         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2924         MLX5_CQ_PERIOD_NUM_MODES
2925 };
2926
2927 struct mlx5_ifc_cqc_bits {
2928         u8         status[0x4];
2929         u8         reserved_at_4[0x4];
2930         u8         cqe_sz[0x3];
2931         u8         cc[0x1];
2932         u8         reserved_at_c[0x1];
2933         u8         scqe_break_moderation_en[0x1];
2934         u8         oi[0x1];
2935         u8         cq_period_mode[0x2];
2936         u8         cqe_comp_en[0x1];
2937         u8         mini_cqe_res_format[0x2];
2938         u8         st[0x4];
2939         u8         reserved_at_18[0x8];
2940
2941         u8         reserved_at_20[0x20];
2942
2943         u8         reserved_at_40[0x14];
2944         u8         page_offset[0x6];
2945         u8         reserved_at_5a[0x6];
2946
2947         u8         reserved_at_60[0x3];
2948         u8         log_cq_size[0x5];
2949         u8         uar_page[0x18];
2950
2951         u8         reserved_at_80[0x4];
2952         u8         cq_period[0xc];
2953         u8         cq_max_count[0x10];
2954
2955         u8         reserved_at_a0[0x18];
2956         u8         c_eqn[0x8];
2957
2958         u8         reserved_at_c0[0x3];
2959         u8         log_page_size[0x5];
2960         u8         reserved_at_c8[0x18];
2961
2962         u8         reserved_at_e0[0x20];
2963
2964         u8         reserved_at_100[0x8];
2965         u8         last_notified_index[0x18];
2966
2967         u8         reserved_at_120[0x8];
2968         u8         last_solicit_index[0x18];
2969
2970         u8         reserved_at_140[0x8];
2971         u8         consumer_counter[0x18];
2972
2973         u8         reserved_at_160[0x8];
2974         u8         producer_counter[0x18];
2975
2976         u8         reserved_at_180[0x40];
2977
2978         u8         dbr_addr[0x40];
2979 };
2980
2981 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2982         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2983         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2984         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2985         u8         reserved_at_0[0x800];
2986 };
2987
2988 struct mlx5_ifc_query_adapter_param_block_bits {
2989         u8         reserved_at_0[0xc0];
2990
2991         u8         reserved_at_c0[0x8];
2992         u8         ieee_vendor_id[0x18];
2993
2994         u8         reserved_at_e0[0x10];
2995         u8         vsd_vendor_id[0x10];
2996
2997         u8         vsd[208][0x8];
2998
2999         u8         vsd_contd_psid[16][0x8];
3000 };
3001
3002 enum {
3003         MLX5_XRQC_STATE_GOOD   = 0x0,
3004         MLX5_XRQC_STATE_ERROR  = 0x1,
3005 };
3006
3007 enum {
3008         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3009         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3010 };
3011
3012 enum {
3013         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3014 };
3015
3016 struct mlx5_ifc_tag_matching_topology_context_bits {
3017         u8         log_matching_list_sz[0x4];
3018         u8         reserved_at_4[0xc];
3019         u8         append_next_index[0x10];
3020
3021         u8         sw_phase_cnt[0x10];
3022         u8         hw_phase_cnt[0x10];
3023
3024         u8         reserved_at_40[0x40];
3025 };
3026
3027 struct mlx5_ifc_xrqc_bits {
3028         u8         state[0x4];
3029         u8         rlkey[0x1];
3030         u8         reserved_at_5[0xf];
3031         u8         topology[0x4];
3032         u8         reserved_at_18[0x4];
3033         u8         offload[0x4];
3034
3035         u8         reserved_at_20[0x8];
3036         u8         user_index[0x18];
3037
3038         u8         reserved_at_40[0x8];
3039         u8         cqn[0x18];
3040
3041         u8         reserved_at_60[0xa0];
3042
3043         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3044
3045         u8         reserved_at_180[0x280];
3046
3047         struct mlx5_ifc_wq_bits wq;
3048 };
3049
3050 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3051         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3052         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3053         u8         reserved_at_0[0x20];
3054 };
3055
3056 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3057         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3058         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3059         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3060         u8         reserved_at_0[0x20];
3061 };
3062
3063 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3064         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3065         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3066         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3067         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3068         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3069         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3070         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3071         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3072         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3073         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3074         u8         reserved_at_0[0x7c0];
3075 };
3076
3077 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3078         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3079         u8         reserved_at_0[0x7c0];
3080 };
3081
3082 union mlx5_ifc_event_auto_bits {
3083         struct mlx5_ifc_comp_event_bits comp_event;
3084         struct mlx5_ifc_dct_events_bits dct_events;
3085         struct mlx5_ifc_qp_events_bits qp_events;
3086         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3087         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3088         struct mlx5_ifc_cq_error_bits cq_error;
3089         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3090         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3091         struct mlx5_ifc_gpio_event_bits gpio_event;
3092         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3093         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3094         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3095         u8         reserved_at_0[0xe0];
3096 };
3097
3098 struct mlx5_ifc_health_buffer_bits {
3099         u8         reserved_at_0[0x100];
3100
3101         u8         assert_existptr[0x20];
3102
3103         u8         assert_callra[0x20];
3104
3105         u8         reserved_at_140[0x40];
3106
3107         u8         fw_version[0x20];
3108
3109         u8         hw_id[0x20];
3110
3111         u8         reserved_at_1c0[0x20];
3112
3113         u8         irisc_index[0x8];
3114         u8         synd[0x8];
3115         u8         ext_synd[0x10];
3116 };
3117
3118 struct mlx5_ifc_register_loopback_control_bits {
3119         u8         no_lb[0x1];
3120         u8         reserved_at_1[0x7];
3121         u8         port[0x8];
3122         u8         reserved_at_10[0x10];
3123
3124         u8         reserved_at_20[0x60];
3125 };
3126
3127 struct mlx5_ifc_vport_tc_element_bits {
3128         u8         traffic_class[0x4];
3129         u8         reserved_at_4[0xc];
3130         u8         vport_number[0x10];
3131 };
3132
3133 struct mlx5_ifc_vport_element_bits {
3134         u8         reserved_at_0[0x10];
3135         u8         vport_number[0x10];
3136 };
3137
3138 enum {
3139         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3140         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3141         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3142 };
3143
3144 struct mlx5_ifc_tsar_element_bits {
3145         u8         reserved_at_0[0x8];
3146         u8         tsar_type[0x8];
3147         u8         reserved_at_10[0x10];
3148 };
3149
3150 enum {
3151         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3152         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3153 };
3154
3155 struct mlx5_ifc_teardown_hca_out_bits {
3156         u8         status[0x8];
3157         u8         reserved_at_8[0x18];
3158
3159         u8         syndrome[0x20];
3160
3161         u8         reserved_at_40[0x3f];
3162
3163         u8         force_state[0x1];
3164 };
3165
3166 enum {
3167         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3168         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3169 };
3170
3171 struct mlx5_ifc_teardown_hca_in_bits {
3172         u8         opcode[0x10];
3173         u8         reserved_at_10[0x10];
3174
3175         u8         reserved_at_20[0x10];
3176         u8         op_mod[0x10];
3177
3178         u8         reserved_at_40[0x10];
3179         u8         profile[0x10];
3180
3181         u8         reserved_at_60[0x20];
3182 };
3183
3184 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3185         u8         status[0x8];
3186         u8         reserved_at_8[0x18];
3187
3188         u8         syndrome[0x20];
3189
3190         u8         reserved_at_40[0x40];
3191 };
3192
3193 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3194         u8         opcode[0x10];
3195         u8         reserved_at_10[0x10];
3196
3197         u8         reserved_at_20[0x10];
3198         u8         op_mod[0x10];
3199
3200         u8         reserved_at_40[0x8];
3201         u8         qpn[0x18];
3202
3203         u8         reserved_at_60[0x20];
3204
3205         u8         opt_param_mask[0x20];
3206
3207         u8         reserved_at_a0[0x20];
3208
3209         struct mlx5_ifc_qpc_bits qpc;
3210
3211         u8         reserved_at_800[0x80];
3212 };
3213
3214 struct mlx5_ifc_sqd2rts_qp_out_bits {
3215         u8         status[0x8];
3216         u8         reserved_at_8[0x18];
3217
3218         u8         syndrome[0x20];
3219
3220         u8         reserved_at_40[0x40];
3221 };
3222
3223 struct mlx5_ifc_sqd2rts_qp_in_bits {
3224         u8         opcode[0x10];
3225         u8         reserved_at_10[0x10];
3226
3227         u8         reserved_at_20[0x10];
3228         u8         op_mod[0x10];
3229
3230         u8         reserved_at_40[0x8];
3231         u8         qpn[0x18];
3232
3233         u8         reserved_at_60[0x20];
3234
3235         u8         opt_param_mask[0x20];
3236
3237         u8         reserved_at_a0[0x20];
3238
3239         struct mlx5_ifc_qpc_bits qpc;
3240
3241         u8         reserved_at_800[0x80];
3242 };
3243
3244 struct mlx5_ifc_set_roce_address_out_bits {
3245         u8         status[0x8];
3246         u8         reserved_at_8[0x18];
3247
3248         u8         syndrome[0x20];
3249
3250         u8         reserved_at_40[0x40];
3251 };
3252
3253 struct mlx5_ifc_set_roce_address_in_bits {
3254         u8         opcode[0x10];
3255         u8         reserved_at_10[0x10];
3256
3257         u8         reserved_at_20[0x10];
3258         u8         op_mod[0x10];
3259
3260         u8         roce_address_index[0x10];
3261         u8         reserved_at_50[0x10];
3262
3263         u8         reserved_at_60[0x20];
3264
3265         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3266 };
3267
3268 struct mlx5_ifc_set_mad_demux_out_bits {
3269         u8         status[0x8];
3270         u8         reserved_at_8[0x18];
3271
3272         u8         syndrome[0x20];
3273
3274         u8         reserved_at_40[0x40];
3275 };
3276
3277 enum {
3278         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3279         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3280 };
3281
3282 struct mlx5_ifc_set_mad_demux_in_bits {
3283         u8         opcode[0x10];
3284         u8         reserved_at_10[0x10];
3285
3286         u8         reserved_at_20[0x10];
3287         u8         op_mod[0x10];
3288
3289         u8         reserved_at_40[0x20];
3290
3291         u8         reserved_at_60[0x6];
3292         u8         demux_mode[0x2];
3293         u8         reserved_at_68[0x18];
3294 };
3295
3296 struct mlx5_ifc_set_l2_table_entry_out_bits {
3297         u8         status[0x8];
3298         u8         reserved_at_8[0x18];
3299
3300         u8         syndrome[0x20];
3301
3302         u8         reserved_at_40[0x40];
3303 };
3304
3305 struct mlx5_ifc_set_l2_table_entry_in_bits {
3306         u8         opcode[0x10];
3307         u8         reserved_at_10[0x10];
3308
3309         u8         reserved_at_20[0x10];
3310         u8         op_mod[0x10];
3311
3312         u8         reserved_at_40[0x60];
3313
3314         u8         reserved_at_a0[0x8];
3315         u8         table_index[0x18];
3316
3317         u8         reserved_at_c0[0x20];
3318
3319         u8         reserved_at_e0[0x13];
3320         u8         vlan_valid[0x1];
3321         u8         vlan[0xc];
3322
3323         struct mlx5_ifc_mac_address_layout_bits mac_address;
3324
3325         u8         reserved_at_140[0xc0];
3326 };
3327
3328 struct mlx5_ifc_set_issi_out_bits {
3329         u8         status[0x8];
3330         u8         reserved_at_8[0x18];
3331
3332         u8         syndrome[0x20];
3333
3334         u8         reserved_at_40[0x40];
3335 };
3336
3337 struct mlx5_ifc_set_issi_in_bits {
3338         u8         opcode[0x10];
3339         u8         reserved_at_10[0x10];
3340
3341         u8         reserved_at_20[0x10];
3342         u8         op_mod[0x10];
3343
3344         u8         reserved_at_40[0x10];
3345         u8         current_issi[0x10];
3346
3347         u8         reserved_at_60[0x20];
3348 };
3349
3350 struct mlx5_ifc_set_hca_cap_out_bits {
3351         u8         status[0x8];
3352         u8         reserved_at_8[0x18];
3353
3354         u8         syndrome[0x20];
3355
3356         u8         reserved_at_40[0x40];
3357 };
3358
3359 struct mlx5_ifc_set_hca_cap_in_bits {
3360         u8         opcode[0x10];
3361         u8         reserved_at_10[0x10];
3362
3363         u8         reserved_at_20[0x10];
3364         u8         op_mod[0x10];
3365
3366         u8         reserved_at_40[0x40];
3367
3368         union mlx5_ifc_hca_cap_union_bits capability;
3369 };
3370
3371 enum {
3372         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3373         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3374         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3375         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3376 };
3377
3378 struct mlx5_ifc_set_fte_out_bits {
3379         u8         status[0x8];
3380         u8         reserved_at_8[0x18];
3381
3382         u8         syndrome[0x20];
3383
3384         u8         reserved_at_40[0x40];
3385 };
3386
3387 struct mlx5_ifc_set_fte_in_bits {
3388         u8         opcode[0x10];
3389         u8         reserved_at_10[0x10];
3390
3391         u8         reserved_at_20[0x10];
3392         u8         op_mod[0x10];
3393
3394         u8         other_vport[0x1];
3395         u8         reserved_at_41[0xf];
3396         u8         vport_number[0x10];
3397
3398         u8         reserved_at_60[0x20];
3399
3400         u8         table_type[0x8];
3401         u8         reserved_at_88[0x18];
3402
3403         u8         reserved_at_a0[0x8];
3404         u8         table_id[0x18];
3405
3406         u8         reserved_at_c0[0x18];
3407         u8         modify_enable_mask[0x8];
3408
3409         u8         reserved_at_e0[0x20];
3410
3411         u8         flow_index[0x20];
3412
3413         u8         reserved_at_120[0xe0];
3414
3415         struct mlx5_ifc_flow_context_bits flow_context;
3416 };
3417
3418 struct mlx5_ifc_rts2rts_qp_out_bits {
3419         u8         status[0x8];
3420         u8         reserved_at_8[0x18];
3421
3422         u8         syndrome[0x20];
3423
3424         u8         reserved_at_40[0x40];
3425 };
3426
3427 struct mlx5_ifc_rts2rts_qp_in_bits {
3428         u8         opcode[0x10];
3429         u8         reserved_at_10[0x10];
3430
3431         u8         reserved_at_20[0x10];
3432         u8         op_mod[0x10];
3433
3434         u8         reserved_at_40[0x8];
3435         u8         qpn[0x18];
3436
3437         u8         reserved_at_60[0x20];
3438
3439         u8         opt_param_mask[0x20];
3440
3441         u8         reserved_at_a0[0x20];
3442
3443         struct mlx5_ifc_qpc_bits qpc;
3444
3445         u8         reserved_at_800[0x80];
3446 };
3447
3448 struct mlx5_ifc_rtr2rts_qp_out_bits {
3449         u8         status[0x8];
3450         u8         reserved_at_8[0x18];
3451
3452         u8         syndrome[0x20];
3453
3454         u8         reserved_at_40[0x40];
3455 };
3456
3457 struct mlx5_ifc_rtr2rts_qp_in_bits {
3458         u8         opcode[0x10];
3459         u8         reserved_at_10[0x10];
3460
3461         u8         reserved_at_20[0x10];
3462         u8         op_mod[0x10];
3463
3464         u8         reserved_at_40[0x8];
3465         u8         qpn[0x18];
3466
3467         u8         reserved_at_60[0x20];
3468
3469         u8         opt_param_mask[0x20];
3470
3471         u8         reserved_at_a0[0x20];
3472
3473         struct mlx5_ifc_qpc_bits qpc;
3474
3475         u8         reserved_at_800[0x80];
3476 };
3477
3478 struct mlx5_ifc_rst2init_qp_out_bits {
3479         u8         status[0x8];
3480         u8         reserved_at_8[0x18];
3481
3482         u8         syndrome[0x20];
3483
3484         u8         reserved_at_40[0x40];
3485 };
3486
3487 struct mlx5_ifc_rst2init_qp_in_bits {
3488         u8         opcode[0x10];
3489         u8         reserved_at_10[0x10];
3490
3491         u8         reserved_at_20[0x10];
3492         u8         op_mod[0x10];
3493
3494         u8         reserved_at_40[0x8];
3495         u8         qpn[0x18];
3496
3497         u8         reserved_at_60[0x20];
3498
3499         u8         opt_param_mask[0x20];
3500
3501         u8         reserved_at_a0[0x20];
3502
3503         struct mlx5_ifc_qpc_bits qpc;
3504
3505         u8         reserved_at_800[0x80];
3506 };
3507
3508 struct mlx5_ifc_query_xrq_out_bits {
3509         u8         status[0x8];
3510         u8         reserved_at_8[0x18];
3511
3512         u8         syndrome[0x20];
3513
3514         u8         reserved_at_40[0x40];
3515
3516         struct mlx5_ifc_xrqc_bits xrq_context;
3517 };
3518
3519 struct mlx5_ifc_query_xrq_in_bits {
3520         u8         opcode[0x10];
3521         u8         reserved_at_10[0x10];
3522
3523         u8         reserved_at_20[0x10];
3524         u8         op_mod[0x10];
3525
3526         u8         reserved_at_40[0x8];
3527         u8         xrqn[0x18];
3528
3529         u8         reserved_at_60[0x20];
3530 };
3531
3532 struct mlx5_ifc_query_xrc_srq_out_bits {
3533         u8         status[0x8];
3534         u8         reserved_at_8[0x18];
3535
3536         u8         syndrome[0x20];
3537
3538         u8         reserved_at_40[0x40];
3539
3540         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3541
3542         u8         reserved_at_280[0x600];
3543
3544         u8         pas[0][0x40];
3545 };
3546
3547 struct mlx5_ifc_query_xrc_srq_in_bits {
3548         u8         opcode[0x10];
3549         u8         reserved_at_10[0x10];
3550
3551         u8         reserved_at_20[0x10];
3552         u8         op_mod[0x10];
3553
3554         u8         reserved_at_40[0x8];
3555         u8         xrc_srqn[0x18];
3556
3557         u8         reserved_at_60[0x20];
3558 };
3559
3560 enum {
3561         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3562         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3563 };
3564
3565 struct mlx5_ifc_query_vport_state_out_bits {
3566         u8         status[0x8];
3567         u8         reserved_at_8[0x18];
3568
3569         u8         syndrome[0x20];
3570
3571         u8         reserved_at_40[0x20];
3572
3573         u8         reserved_at_60[0x18];
3574         u8         admin_state[0x4];
3575         u8         state[0x4];
3576 };
3577
3578 enum {
3579         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3580         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3581 };
3582
3583 struct mlx5_ifc_query_vport_state_in_bits {
3584         u8         opcode[0x10];
3585         u8         reserved_at_10[0x10];
3586
3587         u8         reserved_at_20[0x10];
3588         u8         op_mod[0x10];
3589
3590         u8         other_vport[0x1];
3591         u8         reserved_at_41[0xf];
3592         u8         vport_number[0x10];
3593
3594         u8         reserved_at_60[0x20];
3595 };
3596
3597 struct mlx5_ifc_query_vport_counter_out_bits {
3598         u8         status[0x8];
3599         u8         reserved_at_8[0x18];
3600
3601         u8         syndrome[0x20];
3602
3603         u8         reserved_at_40[0x40];
3604
3605         struct mlx5_ifc_traffic_counter_bits received_errors;
3606
3607         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3608
3609         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3610
3611         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3612
3613         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3614
3615         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3616
3617         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3618
3619         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3620
3621         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3622
3623         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3624
3625         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3626
3627         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3628
3629         u8         reserved_at_680[0xa00];
3630 };
3631
3632 enum {
3633         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3634 };
3635
3636 struct mlx5_ifc_query_vport_counter_in_bits {
3637         u8         opcode[0x10];
3638         u8         reserved_at_10[0x10];
3639
3640         u8         reserved_at_20[0x10];
3641         u8         op_mod[0x10];
3642
3643         u8         other_vport[0x1];
3644         u8         reserved_at_41[0xb];
3645         u8         port_num[0x4];
3646         u8         vport_number[0x10];
3647
3648         u8         reserved_at_60[0x60];
3649
3650         u8         clear[0x1];
3651         u8         reserved_at_c1[0x1f];
3652
3653         u8         reserved_at_e0[0x20];
3654 };
3655
3656 struct mlx5_ifc_query_tis_out_bits {
3657         u8         status[0x8];
3658         u8         reserved_at_8[0x18];
3659
3660         u8         syndrome[0x20];
3661
3662         u8         reserved_at_40[0x40];
3663
3664         struct mlx5_ifc_tisc_bits tis_context;
3665 };
3666
3667 struct mlx5_ifc_query_tis_in_bits {
3668         u8         opcode[0x10];
3669         u8         reserved_at_10[0x10];
3670
3671         u8         reserved_at_20[0x10];
3672         u8         op_mod[0x10];
3673
3674         u8         reserved_at_40[0x8];
3675         u8         tisn[0x18];
3676
3677         u8         reserved_at_60[0x20];
3678 };
3679
3680 struct mlx5_ifc_query_tir_out_bits {
3681         u8         status[0x8];
3682         u8         reserved_at_8[0x18];
3683
3684         u8         syndrome[0x20];
3685
3686         u8         reserved_at_40[0xc0];
3687
3688         struct mlx5_ifc_tirc_bits tir_context;
3689 };
3690
3691 struct mlx5_ifc_query_tir_in_bits {
3692         u8         opcode[0x10];
3693         u8         reserved_at_10[0x10];
3694
3695         u8         reserved_at_20[0x10];
3696         u8         op_mod[0x10];
3697
3698         u8         reserved_at_40[0x8];
3699         u8         tirn[0x18];
3700
3701         u8         reserved_at_60[0x20];
3702 };
3703
3704 struct mlx5_ifc_query_srq_out_bits {
3705         u8         status[0x8];
3706         u8         reserved_at_8[0x18];
3707
3708         u8         syndrome[0x20];
3709
3710         u8         reserved_at_40[0x40];
3711
3712         struct mlx5_ifc_srqc_bits srq_context_entry;
3713
3714         u8         reserved_at_280[0x600];
3715
3716         u8         pas[0][0x40];
3717 };
3718
3719 struct mlx5_ifc_query_srq_in_bits {
3720         u8         opcode[0x10];
3721         u8         reserved_at_10[0x10];
3722
3723         u8         reserved_at_20[0x10];
3724         u8         op_mod[0x10];
3725
3726         u8         reserved_at_40[0x8];
3727         u8         srqn[0x18];
3728
3729         u8         reserved_at_60[0x20];
3730 };
3731
3732 struct mlx5_ifc_query_sq_out_bits {
3733         u8         status[0x8];
3734         u8         reserved_at_8[0x18];
3735
3736         u8         syndrome[0x20];
3737
3738         u8         reserved_at_40[0xc0];
3739
3740         struct mlx5_ifc_sqc_bits sq_context;
3741 };
3742
3743 struct mlx5_ifc_query_sq_in_bits {
3744         u8         opcode[0x10];
3745         u8         reserved_at_10[0x10];
3746
3747         u8         reserved_at_20[0x10];
3748         u8         op_mod[0x10];
3749
3750         u8         reserved_at_40[0x8];
3751         u8         sqn[0x18];
3752
3753         u8         reserved_at_60[0x20];
3754 };
3755
3756 struct mlx5_ifc_query_special_contexts_out_bits {
3757         u8         status[0x8];
3758         u8         reserved_at_8[0x18];
3759
3760         u8         syndrome[0x20];
3761
3762         u8         dump_fill_mkey[0x20];
3763
3764         u8         resd_lkey[0x20];
3765
3766         u8         null_mkey[0x20];
3767
3768         u8         reserved_at_a0[0x60];
3769 };
3770
3771 struct mlx5_ifc_query_special_contexts_in_bits {
3772         u8         opcode[0x10];
3773         u8         reserved_at_10[0x10];
3774
3775         u8         reserved_at_20[0x10];
3776         u8         op_mod[0x10];
3777
3778         u8         reserved_at_40[0x40];
3779 };
3780
3781 struct mlx5_ifc_query_scheduling_element_out_bits {
3782         u8         opcode[0x10];
3783         u8         reserved_at_10[0x10];
3784
3785         u8         reserved_at_20[0x10];
3786         u8         op_mod[0x10];
3787
3788         u8         reserved_at_40[0xc0];
3789
3790         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3791
3792         u8         reserved_at_300[0x100];
3793 };
3794
3795 enum {
3796         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3797 };
3798
3799 struct mlx5_ifc_query_scheduling_element_in_bits {
3800         u8         opcode[0x10];
3801         u8         reserved_at_10[0x10];
3802
3803         u8         reserved_at_20[0x10];
3804         u8         op_mod[0x10];
3805
3806         u8         scheduling_hierarchy[0x8];
3807         u8         reserved_at_48[0x18];
3808
3809         u8         scheduling_element_id[0x20];
3810
3811         u8         reserved_at_80[0x180];
3812 };
3813
3814 struct mlx5_ifc_query_rqt_out_bits {
3815         u8         status[0x8];
3816         u8         reserved_at_8[0x18];
3817
3818         u8         syndrome[0x20];
3819
3820         u8         reserved_at_40[0xc0];
3821
3822         struct mlx5_ifc_rqtc_bits rqt_context;
3823 };
3824
3825 struct mlx5_ifc_query_rqt_in_bits {
3826         u8         opcode[0x10];
3827         u8         reserved_at_10[0x10];
3828
3829         u8         reserved_at_20[0x10];
3830         u8         op_mod[0x10];
3831
3832         u8         reserved_at_40[0x8];
3833         u8         rqtn[0x18];
3834
3835         u8         reserved_at_60[0x20];
3836 };
3837
3838 struct mlx5_ifc_query_rq_out_bits {
3839         u8         status[0x8];
3840         u8         reserved_at_8[0x18];
3841
3842         u8         syndrome[0x20];
3843
3844         u8         reserved_at_40[0xc0];
3845
3846         struct mlx5_ifc_rqc_bits rq_context;
3847 };
3848
3849 struct mlx5_ifc_query_rq_in_bits {
3850         u8         opcode[0x10];
3851         u8         reserved_at_10[0x10];
3852
3853         u8         reserved_at_20[0x10];
3854         u8         op_mod[0x10];
3855
3856         u8         reserved_at_40[0x8];
3857         u8         rqn[0x18];
3858
3859         u8         reserved_at_60[0x20];
3860 };
3861
3862 struct mlx5_ifc_query_roce_address_out_bits {
3863         u8         status[0x8];
3864         u8         reserved_at_8[0x18];
3865
3866         u8         syndrome[0x20];
3867
3868         u8         reserved_at_40[0x40];
3869
3870         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3871 };
3872
3873 struct mlx5_ifc_query_roce_address_in_bits {
3874         u8         opcode[0x10];
3875         u8         reserved_at_10[0x10];
3876
3877         u8         reserved_at_20[0x10];
3878         u8         op_mod[0x10];
3879
3880         u8         roce_address_index[0x10];
3881         u8         reserved_at_50[0x10];
3882
3883         u8         reserved_at_60[0x20];
3884 };
3885
3886 struct mlx5_ifc_query_rmp_out_bits {
3887         u8         status[0x8];
3888         u8         reserved_at_8[0x18];
3889
3890         u8         syndrome[0x20];
3891
3892         u8         reserved_at_40[0xc0];
3893
3894         struct mlx5_ifc_rmpc_bits rmp_context;
3895 };
3896
3897 struct mlx5_ifc_query_rmp_in_bits {
3898         u8         opcode[0x10];
3899         u8         reserved_at_10[0x10];
3900
3901         u8         reserved_at_20[0x10];
3902         u8         op_mod[0x10];
3903
3904         u8         reserved_at_40[0x8];
3905         u8         rmpn[0x18];
3906
3907         u8         reserved_at_60[0x20];
3908 };
3909
3910 struct mlx5_ifc_query_qp_out_bits {
3911         u8         status[0x8];
3912         u8         reserved_at_8[0x18];
3913
3914         u8         syndrome[0x20];
3915
3916         u8         reserved_at_40[0x40];
3917
3918         u8         opt_param_mask[0x20];
3919
3920         u8         reserved_at_a0[0x20];
3921
3922         struct mlx5_ifc_qpc_bits qpc;
3923
3924         u8         reserved_at_800[0x80];
3925
3926         u8         pas[0][0x40];
3927 };
3928
3929 struct mlx5_ifc_query_qp_in_bits {
3930         u8         opcode[0x10];
3931         u8         reserved_at_10[0x10];
3932
3933         u8         reserved_at_20[0x10];
3934         u8         op_mod[0x10];
3935
3936         u8         reserved_at_40[0x8];
3937         u8         qpn[0x18];
3938
3939         u8         reserved_at_60[0x20];
3940 };
3941
3942 struct mlx5_ifc_query_q_counter_out_bits {
3943         u8         status[0x8];
3944         u8         reserved_at_8[0x18];
3945
3946         u8         syndrome[0x20];
3947
3948         u8         reserved_at_40[0x40];
3949
3950         u8         rx_write_requests[0x20];
3951
3952         u8         reserved_at_a0[0x20];
3953
3954         u8         rx_read_requests[0x20];
3955
3956         u8         reserved_at_e0[0x20];
3957
3958         u8         rx_atomic_requests[0x20];
3959
3960         u8         reserved_at_120[0x20];
3961
3962         u8         rx_dct_connect[0x20];
3963
3964         u8         reserved_at_160[0x20];
3965
3966         u8         out_of_buffer[0x20];
3967
3968         u8         reserved_at_1a0[0x20];
3969
3970         u8         out_of_sequence[0x20];
3971
3972         u8         reserved_at_1e0[0x20];
3973
3974         u8         duplicate_request[0x20];
3975
3976         u8         reserved_at_220[0x20];
3977
3978         u8         rnr_nak_retry_err[0x20];
3979
3980         u8         reserved_at_260[0x20];
3981
3982         u8         packet_seq_err[0x20];
3983
3984         u8         reserved_at_2a0[0x20];
3985
3986         u8         implied_nak_seq_err[0x20];
3987
3988         u8         reserved_at_2e0[0x20];
3989
3990         u8         local_ack_timeout_err[0x20];
3991
3992         u8         reserved_at_320[0xa0];
3993
3994         u8         resp_local_length_error[0x20];
3995
3996         u8         req_local_length_error[0x20];
3997
3998         u8         resp_local_qp_error[0x20];
3999
4000         u8         local_operation_error[0x20];
4001
4002         u8         resp_local_protection[0x20];
4003
4004         u8         req_local_protection[0x20];
4005
4006         u8         resp_cqe_error[0x20];
4007
4008         u8         req_cqe_error[0x20];
4009
4010         u8         req_mw_binding[0x20];
4011
4012         u8         req_bad_response[0x20];
4013
4014         u8         req_remote_invalid_request[0x20];
4015
4016         u8         resp_remote_invalid_request[0x20];
4017
4018         u8         req_remote_access_errors[0x20];
4019
4020         u8         resp_remote_access_errors[0x20];
4021
4022         u8         req_remote_operation_errors[0x20];
4023
4024         u8         req_transport_retries_exceeded[0x20];
4025
4026         u8         cq_overflow[0x20];
4027
4028         u8         resp_cqe_flush_error[0x20];
4029
4030         u8         req_cqe_flush_error[0x20];
4031
4032         u8         reserved_at_620[0x1e0];
4033 };
4034
4035 struct mlx5_ifc_query_q_counter_in_bits {
4036         u8         opcode[0x10];
4037         u8         reserved_at_10[0x10];
4038
4039         u8         reserved_at_20[0x10];
4040         u8         op_mod[0x10];
4041
4042         u8         reserved_at_40[0x80];
4043
4044         u8         clear[0x1];
4045         u8         reserved_at_c1[0x1f];
4046
4047         u8         reserved_at_e0[0x18];
4048         u8         counter_set_id[0x8];
4049 };
4050
4051 struct mlx5_ifc_query_pages_out_bits {
4052         u8         status[0x8];
4053         u8         reserved_at_8[0x18];
4054
4055         u8         syndrome[0x20];
4056
4057         u8         reserved_at_40[0x10];
4058         u8         function_id[0x10];
4059
4060         u8         num_pages[0x20];
4061 };
4062
4063 enum {
4064         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4065         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4066         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4067 };
4068
4069 struct mlx5_ifc_query_pages_in_bits {
4070         u8         opcode[0x10];
4071         u8         reserved_at_10[0x10];
4072
4073         u8         reserved_at_20[0x10];
4074         u8         op_mod[0x10];
4075
4076         u8         reserved_at_40[0x10];
4077         u8         function_id[0x10];
4078
4079         u8         reserved_at_60[0x20];
4080 };
4081
4082 struct mlx5_ifc_query_nic_vport_context_out_bits {
4083         u8         status[0x8];
4084         u8         reserved_at_8[0x18];
4085
4086         u8         syndrome[0x20];
4087
4088         u8         reserved_at_40[0x40];
4089
4090         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4091 };
4092
4093 struct mlx5_ifc_query_nic_vport_context_in_bits {
4094         u8         opcode[0x10];
4095         u8         reserved_at_10[0x10];
4096
4097         u8         reserved_at_20[0x10];
4098         u8         op_mod[0x10];
4099
4100         u8         other_vport[0x1];
4101         u8         reserved_at_41[0xf];
4102         u8         vport_number[0x10];
4103
4104         u8         reserved_at_60[0x5];
4105         u8         allowed_list_type[0x3];
4106         u8         reserved_at_68[0x18];
4107 };
4108
4109 struct mlx5_ifc_query_mkey_out_bits {
4110         u8         status[0x8];
4111         u8         reserved_at_8[0x18];
4112
4113         u8         syndrome[0x20];
4114
4115         u8         reserved_at_40[0x40];
4116
4117         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4118
4119         u8         reserved_at_280[0x600];
4120
4121         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4122
4123         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4124 };
4125
4126 struct mlx5_ifc_query_mkey_in_bits {
4127         u8         opcode[0x10];
4128         u8         reserved_at_10[0x10];
4129
4130         u8         reserved_at_20[0x10];
4131         u8         op_mod[0x10];
4132
4133         u8         reserved_at_40[0x8];
4134         u8         mkey_index[0x18];
4135
4136         u8         pg_access[0x1];
4137         u8         reserved_at_61[0x1f];
4138 };
4139
4140 struct mlx5_ifc_query_mad_demux_out_bits {
4141         u8         status[0x8];
4142         u8         reserved_at_8[0x18];
4143
4144         u8         syndrome[0x20];
4145
4146         u8         reserved_at_40[0x40];
4147
4148         u8         mad_dumux_parameters_block[0x20];
4149 };
4150
4151 struct mlx5_ifc_query_mad_demux_in_bits {
4152         u8         opcode[0x10];
4153         u8         reserved_at_10[0x10];
4154
4155         u8         reserved_at_20[0x10];
4156         u8         op_mod[0x10];
4157
4158         u8         reserved_at_40[0x40];
4159 };
4160
4161 struct mlx5_ifc_query_l2_table_entry_out_bits {
4162         u8         status[0x8];
4163         u8         reserved_at_8[0x18];
4164
4165         u8         syndrome[0x20];
4166
4167         u8         reserved_at_40[0xa0];
4168
4169         u8         reserved_at_e0[0x13];
4170         u8         vlan_valid[0x1];
4171         u8         vlan[0xc];
4172
4173         struct mlx5_ifc_mac_address_layout_bits mac_address;
4174
4175         u8         reserved_at_140[0xc0];
4176 };
4177
4178 struct mlx5_ifc_query_l2_table_entry_in_bits {
4179         u8         opcode[0x10];
4180         u8         reserved_at_10[0x10];
4181
4182         u8         reserved_at_20[0x10];
4183         u8         op_mod[0x10];
4184
4185         u8         reserved_at_40[0x60];
4186
4187         u8         reserved_at_a0[0x8];
4188         u8         table_index[0x18];
4189
4190         u8         reserved_at_c0[0x140];
4191 };
4192
4193 struct mlx5_ifc_query_issi_out_bits {
4194         u8         status[0x8];
4195         u8         reserved_at_8[0x18];
4196
4197         u8         syndrome[0x20];
4198
4199         u8         reserved_at_40[0x10];
4200         u8         current_issi[0x10];
4201
4202         u8         reserved_at_60[0xa0];
4203
4204         u8         reserved_at_100[76][0x8];
4205         u8         supported_issi_dw0[0x20];
4206 };
4207
4208 struct mlx5_ifc_query_issi_in_bits {
4209         u8         opcode[0x10];
4210         u8         reserved_at_10[0x10];
4211
4212         u8         reserved_at_20[0x10];
4213         u8         op_mod[0x10];
4214
4215         u8         reserved_at_40[0x40];
4216 };
4217
4218 struct mlx5_ifc_set_driver_version_out_bits {
4219         u8         status[0x8];
4220         u8         reserved_0[0x18];
4221
4222         u8         syndrome[0x20];
4223         u8         reserved_1[0x40];
4224 };
4225
4226 struct mlx5_ifc_set_driver_version_in_bits {
4227         u8         opcode[0x10];
4228         u8         reserved_0[0x10];
4229
4230         u8         reserved_1[0x10];
4231         u8         op_mod[0x10];
4232
4233         u8         reserved_2[0x40];
4234         u8         driver_version[64][0x8];
4235 };
4236
4237 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4238         u8         status[0x8];
4239         u8         reserved_at_8[0x18];
4240
4241         u8         syndrome[0x20];
4242
4243         u8         reserved_at_40[0x40];
4244
4245         struct mlx5_ifc_pkey_bits pkey[0];
4246 };
4247
4248 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4249         u8         opcode[0x10];
4250         u8         reserved_at_10[0x10];
4251
4252         u8         reserved_at_20[0x10];
4253         u8         op_mod[0x10];
4254
4255         u8         other_vport[0x1];
4256         u8         reserved_at_41[0xb];
4257         u8         port_num[0x4];
4258         u8         vport_number[0x10];
4259
4260         u8         reserved_at_60[0x10];
4261         u8         pkey_index[0x10];
4262 };
4263
4264 enum {
4265         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4266         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4267         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4268 };
4269
4270 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4271         u8         status[0x8];
4272         u8         reserved_at_8[0x18];
4273
4274         u8         syndrome[0x20];
4275
4276         u8         reserved_at_40[0x20];
4277
4278         u8         gids_num[0x10];
4279         u8         reserved_at_70[0x10];
4280
4281         struct mlx5_ifc_array128_auto_bits gid[0];
4282 };
4283
4284 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4285         u8         opcode[0x10];
4286         u8         reserved_at_10[0x10];
4287
4288         u8         reserved_at_20[0x10];
4289         u8         op_mod[0x10];
4290
4291         u8         other_vport[0x1];
4292         u8         reserved_at_41[0xb];
4293         u8         port_num[0x4];
4294         u8         vport_number[0x10];
4295
4296         u8         reserved_at_60[0x10];
4297         u8         gid_index[0x10];
4298 };
4299
4300 struct mlx5_ifc_query_hca_vport_context_out_bits {
4301         u8         status[0x8];
4302         u8         reserved_at_8[0x18];
4303
4304         u8         syndrome[0x20];
4305
4306         u8         reserved_at_40[0x40];
4307
4308         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4309 };
4310
4311 struct mlx5_ifc_query_hca_vport_context_in_bits {
4312         u8         opcode[0x10];
4313         u8         reserved_at_10[0x10];
4314
4315         u8         reserved_at_20[0x10];
4316         u8         op_mod[0x10];
4317
4318         u8         other_vport[0x1];
4319         u8         reserved_at_41[0xb];
4320         u8         port_num[0x4];
4321         u8         vport_number[0x10];
4322
4323         u8         reserved_at_60[0x20];
4324 };
4325
4326 struct mlx5_ifc_query_hca_cap_out_bits {
4327         u8         status[0x8];
4328         u8         reserved_at_8[0x18];
4329
4330         u8         syndrome[0x20];
4331
4332         u8         reserved_at_40[0x40];
4333
4334         union mlx5_ifc_hca_cap_union_bits capability;
4335 };
4336
4337 struct mlx5_ifc_query_hca_cap_in_bits {
4338         u8         opcode[0x10];
4339         u8         reserved_at_10[0x10];
4340
4341         u8         reserved_at_20[0x10];
4342         u8         op_mod[0x10];
4343
4344         u8         reserved_at_40[0x40];
4345 };
4346
4347 struct mlx5_ifc_query_flow_table_out_bits {
4348         u8         status[0x8];
4349         u8         reserved_at_8[0x18];
4350
4351         u8         syndrome[0x20];
4352
4353         u8         reserved_at_40[0x80];
4354
4355         u8         reserved_at_c0[0x8];
4356         u8         level[0x8];
4357         u8         reserved_at_d0[0x8];
4358         u8         log_size[0x8];
4359
4360         u8         reserved_at_e0[0x120];
4361 };
4362
4363 struct mlx5_ifc_query_flow_table_in_bits {
4364         u8         opcode[0x10];
4365         u8         reserved_at_10[0x10];
4366
4367         u8         reserved_at_20[0x10];
4368         u8         op_mod[0x10];
4369
4370         u8         reserved_at_40[0x40];
4371
4372         u8         table_type[0x8];
4373         u8         reserved_at_88[0x18];
4374
4375         u8         reserved_at_a0[0x8];
4376         u8         table_id[0x18];
4377
4378         u8         reserved_at_c0[0x140];
4379 };
4380
4381 struct mlx5_ifc_query_fte_out_bits {
4382         u8         status[0x8];
4383         u8         reserved_at_8[0x18];
4384
4385         u8         syndrome[0x20];
4386
4387         u8         reserved_at_40[0x1c0];
4388
4389         struct mlx5_ifc_flow_context_bits flow_context;
4390 };
4391
4392 struct mlx5_ifc_query_fte_in_bits {
4393         u8         opcode[0x10];
4394         u8         reserved_at_10[0x10];
4395
4396         u8         reserved_at_20[0x10];
4397         u8         op_mod[0x10];
4398
4399         u8         reserved_at_40[0x40];
4400
4401         u8         table_type[0x8];
4402         u8         reserved_at_88[0x18];
4403
4404         u8         reserved_at_a0[0x8];
4405         u8         table_id[0x18];
4406
4407         u8         reserved_at_c0[0x40];
4408
4409         u8         flow_index[0x20];
4410
4411         u8         reserved_at_120[0xe0];
4412 };
4413
4414 enum {
4415         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4416         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4417         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4418 };
4419
4420 struct mlx5_ifc_query_flow_group_out_bits {
4421         u8         status[0x8];
4422         u8         reserved_at_8[0x18];
4423
4424         u8         syndrome[0x20];
4425
4426         u8         reserved_at_40[0xa0];
4427
4428         u8         start_flow_index[0x20];
4429
4430         u8         reserved_at_100[0x20];
4431
4432         u8         end_flow_index[0x20];
4433
4434         u8         reserved_at_140[0xa0];
4435
4436         u8         reserved_at_1e0[0x18];
4437         u8         match_criteria_enable[0x8];
4438
4439         struct mlx5_ifc_fte_match_param_bits match_criteria;
4440
4441         u8         reserved_at_1200[0xe00];
4442 };
4443
4444 struct mlx5_ifc_query_flow_group_in_bits {
4445         u8         opcode[0x10];
4446         u8         reserved_at_10[0x10];
4447
4448         u8         reserved_at_20[0x10];
4449         u8         op_mod[0x10];
4450
4451         u8         reserved_at_40[0x40];
4452
4453         u8         table_type[0x8];
4454         u8         reserved_at_88[0x18];
4455
4456         u8         reserved_at_a0[0x8];
4457         u8         table_id[0x18];
4458
4459         u8         group_id[0x20];
4460
4461         u8         reserved_at_e0[0x120];
4462 };
4463
4464 struct mlx5_ifc_query_flow_counter_out_bits {
4465         u8         status[0x8];
4466         u8         reserved_at_8[0x18];
4467
4468         u8         syndrome[0x20];
4469
4470         u8         reserved_at_40[0x40];
4471
4472         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4473 };
4474
4475 struct mlx5_ifc_query_flow_counter_in_bits {
4476         u8         opcode[0x10];
4477         u8         reserved_at_10[0x10];
4478
4479         u8         reserved_at_20[0x10];
4480         u8         op_mod[0x10];
4481
4482         u8         reserved_at_40[0x80];
4483
4484         u8         clear[0x1];
4485         u8         reserved_at_c1[0xf];
4486         u8         num_of_counters[0x10];
4487
4488         u8         flow_counter_id[0x20];
4489 };
4490
4491 struct mlx5_ifc_query_esw_vport_context_out_bits {
4492         u8         status[0x8];
4493         u8         reserved_at_8[0x18];
4494
4495         u8         syndrome[0x20];
4496
4497         u8         reserved_at_40[0x40];
4498
4499         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4500 };
4501
4502 struct mlx5_ifc_query_esw_vport_context_in_bits {
4503         u8         opcode[0x10];
4504         u8         reserved_at_10[0x10];
4505
4506         u8         reserved_at_20[0x10];
4507         u8         op_mod[0x10];
4508
4509         u8         other_vport[0x1];
4510         u8         reserved_at_41[0xf];
4511         u8         vport_number[0x10];
4512
4513         u8         reserved_at_60[0x20];
4514 };
4515
4516 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4517         u8         status[0x8];
4518         u8         reserved_at_8[0x18];
4519
4520         u8         syndrome[0x20];
4521
4522         u8         reserved_at_40[0x40];
4523 };
4524
4525 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4526         u8         reserved_at_0[0x1c];
4527         u8         vport_cvlan_insert[0x1];
4528         u8         vport_svlan_insert[0x1];
4529         u8         vport_cvlan_strip[0x1];
4530         u8         vport_svlan_strip[0x1];
4531 };
4532
4533 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4534         u8         opcode[0x10];
4535         u8         reserved_at_10[0x10];
4536
4537         u8         reserved_at_20[0x10];
4538         u8         op_mod[0x10];
4539
4540         u8         other_vport[0x1];
4541         u8         reserved_at_41[0xf];
4542         u8         vport_number[0x10];
4543
4544         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4545
4546         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4547 };
4548
4549 struct mlx5_ifc_query_eq_out_bits {
4550         u8         status[0x8];
4551         u8         reserved_at_8[0x18];
4552
4553         u8         syndrome[0x20];
4554
4555         u8         reserved_at_40[0x40];
4556
4557         struct mlx5_ifc_eqc_bits eq_context_entry;
4558
4559         u8         reserved_at_280[0x40];
4560
4561         u8         event_bitmask[0x40];
4562
4563         u8         reserved_at_300[0x580];
4564
4565         u8         pas[0][0x40];
4566 };
4567
4568 struct mlx5_ifc_query_eq_in_bits {
4569         u8         opcode[0x10];
4570         u8         reserved_at_10[0x10];
4571
4572         u8         reserved_at_20[0x10];
4573         u8         op_mod[0x10];
4574
4575         u8         reserved_at_40[0x18];
4576         u8         eq_number[0x8];
4577
4578         u8         reserved_at_60[0x20];
4579 };
4580
4581 struct mlx5_ifc_encap_header_in_bits {
4582         u8         reserved_at_0[0x5];
4583         u8         header_type[0x3];
4584         u8         reserved_at_8[0xe];
4585         u8         encap_header_size[0xa];
4586
4587         u8         reserved_at_20[0x10];
4588         u8         encap_header[2][0x8];
4589
4590         u8         more_encap_header[0][0x8];
4591 };
4592
4593 struct mlx5_ifc_query_encap_header_out_bits {
4594         u8         status[0x8];
4595         u8         reserved_at_8[0x18];
4596
4597         u8         syndrome[0x20];
4598
4599         u8         reserved_at_40[0xa0];
4600
4601         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4602 };
4603
4604 struct mlx5_ifc_query_encap_header_in_bits {
4605         u8         opcode[0x10];
4606         u8         reserved_at_10[0x10];
4607
4608         u8         reserved_at_20[0x10];
4609         u8         op_mod[0x10];
4610
4611         u8         encap_id[0x20];
4612
4613         u8         reserved_at_60[0xa0];
4614 };
4615
4616 struct mlx5_ifc_alloc_encap_header_out_bits {
4617         u8         status[0x8];
4618         u8         reserved_at_8[0x18];
4619
4620         u8         syndrome[0x20];
4621
4622         u8         encap_id[0x20];
4623
4624         u8         reserved_at_60[0x20];
4625 };
4626
4627 struct mlx5_ifc_alloc_encap_header_in_bits {
4628         u8         opcode[0x10];
4629         u8         reserved_at_10[0x10];
4630
4631         u8         reserved_at_20[0x10];
4632         u8         op_mod[0x10];
4633
4634         u8         reserved_at_40[0xa0];
4635
4636         struct mlx5_ifc_encap_header_in_bits encap_header;
4637 };
4638
4639 struct mlx5_ifc_dealloc_encap_header_out_bits {
4640         u8         status[0x8];
4641         u8         reserved_at_8[0x18];
4642
4643         u8         syndrome[0x20];
4644
4645         u8         reserved_at_40[0x40];
4646 };
4647
4648 struct mlx5_ifc_dealloc_encap_header_in_bits {
4649         u8         opcode[0x10];
4650         u8         reserved_at_10[0x10];
4651
4652         u8         reserved_20[0x10];
4653         u8         op_mod[0x10];
4654
4655         u8         encap_id[0x20];
4656
4657         u8         reserved_60[0x20];
4658 };
4659
4660 struct mlx5_ifc_set_action_in_bits {
4661         u8         action_type[0x4];
4662         u8         field[0xc];
4663         u8         reserved_at_10[0x3];
4664         u8         offset[0x5];
4665         u8         reserved_at_18[0x3];
4666         u8         length[0x5];
4667
4668         u8         data[0x20];
4669 };
4670
4671 struct mlx5_ifc_add_action_in_bits {
4672         u8         action_type[0x4];
4673         u8         field[0xc];
4674         u8         reserved_at_10[0x10];
4675
4676         u8         data[0x20];
4677 };
4678
4679 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4680         struct mlx5_ifc_set_action_in_bits set_action_in;
4681         struct mlx5_ifc_add_action_in_bits add_action_in;
4682         u8         reserved_at_0[0x40];
4683 };
4684
4685 enum {
4686         MLX5_ACTION_TYPE_SET   = 0x1,
4687         MLX5_ACTION_TYPE_ADD   = 0x2,
4688 };
4689
4690 enum {
4691         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4692         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4693         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4694         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4695         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4696         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4697         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4698         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4699         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4700         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4701         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4702         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4703         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4704         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4705         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4706         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4707         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4708         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4709         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4710         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4711         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4712         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4713         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4714 };
4715
4716 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4717         u8         status[0x8];
4718         u8         reserved_at_8[0x18];
4719
4720         u8         syndrome[0x20];
4721
4722         u8         modify_header_id[0x20];
4723
4724         u8         reserved_at_60[0x20];
4725 };
4726
4727 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4728         u8         opcode[0x10];
4729         u8         reserved_at_10[0x10];
4730
4731         u8         reserved_at_20[0x10];
4732         u8         op_mod[0x10];
4733
4734         u8         reserved_at_40[0x20];
4735
4736         u8         table_type[0x8];
4737         u8         reserved_at_68[0x10];
4738         u8         num_of_actions[0x8];
4739
4740         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4741 };
4742
4743 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4744         u8         status[0x8];
4745         u8         reserved_at_8[0x18];
4746
4747         u8         syndrome[0x20];
4748
4749         u8         reserved_at_40[0x40];
4750 };
4751
4752 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4753         u8         opcode[0x10];
4754         u8         reserved_at_10[0x10];
4755
4756         u8         reserved_at_20[0x10];
4757         u8         op_mod[0x10];
4758
4759         u8         modify_header_id[0x20];
4760
4761         u8         reserved_at_60[0x20];
4762 };
4763
4764 struct mlx5_ifc_query_dct_out_bits {
4765         u8         status[0x8];
4766         u8         reserved_at_8[0x18];
4767
4768         u8         syndrome[0x20];
4769
4770         u8         reserved_at_40[0x40];
4771
4772         struct mlx5_ifc_dctc_bits dct_context_entry;
4773
4774         u8         reserved_at_280[0x180];
4775 };
4776
4777 struct mlx5_ifc_query_dct_in_bits {
4778         u8         opcode[0x10];
4779         u8         reserved_at_10[0x10];
4780
4781         u8         reserved_at_20[0x10];
4782         u8         op_mod[0x10];
4783
4784         u8         reserved_at_40[0x8];
4785         u8         dctn[0x18];
4786
4787         u8         reserved_at_60[0x20];
4788 };
4789
4790 struct mlx5_ifc_query_cq_out_bits {
4791         u8         status[0x8];
4792         u8         reserved_at_8[0x18];
4793
4794         u8         syndrome[0x20];
4795
4796         u8         reserved_at_40[0x40];
4797
4798         struct mlx5_ifc_cqc_bits cq_context;
4799
4800         u8         reserved_at_280[0x600];
4801
4802         u8         pas[0][0x40];
4803 };
4804
4805 struct mlx5_ifc_query_cq_in_bits {
4806         u8         opcode[0x10];
4807         u8         reserved_at_10[0x10];
4808
4809         u8         reserved_at_20[0x10];
4810         u8         op_mod[0x10];
4811
4812         u8         reserved_at_40[0x8];
4813         u8         cqn[0x18];
4814
4815         u8         reserved_at_60[0x20];
4816 };
4817
4818 struct mlx5_ifc_query_cong_status_out_bits {
4819         u8         status[0x8];
4820         u8         reserved_at_8[0x18];
4821
4822         u8         syndrome[0x20];
4823
4824         u8         reserved_at_40[0x20];
4825
4826         u8         enable[0x1];
4827         u8         tag_enable[0x1];
4828         u8         reserved_at_62[0x1e];
4829 };
4830
4831 struct mlx5_ifc_query_cong_status_in_bits {
4832         u8         opcode[0x10];
4833         u8         reserved_at_10[0x10];
4834
4835         u8         reserved_at_20[0x10];
4836         u8         op_mod[0x10];
4837
4838         u8         reserved_at_40[0x18];
4839         u8         priority[0x4];
4840         u8         cong_protocol[0x4];
4841
4842         u8         reserved_at_60[0x20];
4843 };
4844
4845 struct mlx5_ifc_query_cong_statistics_out_bits {
4846         u8         status[0x8];
4847         u8         reserved_at_8[0x18];
4848
4849         u8         syndrome[0x20];
4850
4851         u8         reserved_at_40[0x40];
4852
4853         u8         rp_cur_flows[0x20];
4854
4855         u8         sum_flows[0x20];
4856
4857         u8         rp_cnp_ignored_high[0x20];
4858
4859         u8         rp_cnp_ignored_low[0x20];
4860
4861         u8         rp_cnp_handled_high[0x20];
4862
4863         u8         rp_cnp_handled_low[0x20];
4864
4865         u8         reserved_at_140[0x100];
4866
4867         u8         time_stamp_high[0x20];
4868
4869         u8         time_stamp_low[0x20];
4870
4871         u8         accumulators_period[0x20];
4872
4873         u8         np_ecn_marked_roce_packets_high[0x20];
4874
4875         u8         np_ecn_marked_roce_packets_low[0x20];
4876
4877         u8         np_cnp_sent_high[0x20];
4878
4879         u8         np_cnp_sent_low[0x20];
4880
4881         u8         reserved_at_320[0x560];
4882 };
4883
4884 struct mlx5_ifc_query_cong_statistics_in_bits {
4885         u8         opcode[0x10];
4886         u8         reserved_at_10[0x10];
4887
4888         u8         reserved_at_20[0x10];
4889         u8         op_mod[0x10];
4890
4891         u8         clear[0x1];
4892         u8         reserved_at_41[0x1f];
4893
4894         u8         reserved_at_60[0x20];
4895 };
4896
4897 struct mlx5_ifc_query_cong_params_out_bits {
4898         u8         status[0x8];
4899         u8         reserved_at_8[0x18];
4900
4901         u8         syndrome[0x20];
4902
4903         u8         reserved_at_40[0x40];
4904
4905         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4906 };
4907
4908 struct mlx5_ifc_query_cong_params_in_bits {
4909         u8         opcode[0x10];
4910         u8         reserved_at_10[0x10];
4911
4912         u8         reserved_at_20[0x10];
4913         u8         op_mod[0x10];
4914
4915         u8         reserved_at_40[0x1c];
4916         u8         cong_protocol[0x4];
4917
4918         u8         reserved_at_60[0x20];
4919 };
4920
4921 struct mlx5_ifc_query_adapter_out_bits {
4922         u8         status[0x8];
4923         u8         reserved_at_8[0x18];
4924
4925         u8         syndrome[0x20];
4926
4927         u8         reserved_at_40[0x40];
4928
4929         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4930 };
4931
4932 struct mlx5_ifc_query_adapter_in_bits {
4933         u8         opcode[0x10];
4934         u8         reserved_at_10[0x10];
4935
4936         u8         reserved_at_20[0x10];
4937         u8         op_mod[0x10];
4938
4939         u8         reserved_at_40[0x40];
4940 };
4941
4942 struct mlx5_ifc_qp_2rst_out_bits {
4943         u8         status[0x8];
4944         u8         reserved_at_8[0x18];
4945
4946         u8         syndrome[0x20];
4947
4948         u8         reserved_at_40[0x40];
4949 };
4950
4951 struct mlx5_ifc_qp_2rst_in_bits {
4952         u8         opcode[0x10];
4953         u8         reserved_at_10[0x10];
4954
4955         u8         reserved_at_20[0x10];
4956         u8         op_mod[0x10];
4957
4958         u8         reserved_at_40[0x8];
4959         u8         qpn[0x18];
4960
4961         u8         reserved_at_60[0x20];
4962 };
4963
4964 struct mlx5_ifc_qp_2err_out_bits {
4965         u8         status[0x8];
4966         u8         reserved_at_8[0x18];
4967
4968         u8         syndrome[0x20];
4969
4970         u8         reserved_at_40[0x40];
4971 };
4972
4973 struct mlx5_ifc_qp_2err_in_bits {
4974         u8         opcode[0x10];
4975         u8         reserved_at_10[0x10];
4976
4977         u8         reserved_at_20[0x10];
4978         u8         op_mod[0x10];
4979
4980         u8         reserved_at_40[0x8];
4981         u8         qpn[0x18];
4982
4983         u8         reserved_at_60[0x20];
4984 };
4985
4986 struct mlx5_ifc_page_fault_resume_out_bits {
4987         u8         status[0x8];
4988         u8         reserved_at_8[0x18];
4989
4990         u8         syndrome[0x20];
4991
4992         u8         reserved_at_40[0x40];
4993 };
4994
4995 struct mlx5_ifc_page_fault_resume_in_bits {
4996         u8         opcode[0x10];
4997         u8         reserved_at_10[0x10];
4998
4999         u8         reserved_at_20[0x10];
5000         u8         op_mod[0x10];
5001
5002         u8         error[0x1];
5003         u8         reserved_at_41[0x4];
5004         u8         page_fault_type[0x3];
5005         u8         wq_number[0x18];
5006
5007         u8         reserved_at_60[0x8];
5008         u8         token[0x18];
5009 };
5010
5011 struct mlx5_ifc_nop_out_bits {
5012         u8         status[0x8];
5013         u8         reserved_at_8[0x18];
5014
5015         u8         syndrome[0x20];
5016
5017         u8         reserved_at_40[0x40];
5018 };
5019
5020 struct mlx5_ifc_nop_in_bits {
5021         u8         opcode[0x10];
5022         u8         reserved_at_10[0x10];
5023
5024         u8         reserved_at_20[0x10];
5025         u8         op_mod[0x10];
5026
5027         u8         reserved_at_40[0x40];
5028 };
5029
5030 struct mlx5_ifc_modify_vport_state_out_bits {
5031         u8         status[0x8];
5032         u8         reserved_at_8[0x18];
5033
5034         u8         syndrome[0x20];
5035
5036         u8         reserved_at_40[0x40];
5037 };
5038
5039 struct mlx5_ifc_modify_vport_state_in_bits {
5040         u8         opcode[0x10];
5041         u8         reserved_at_10[0x10];
5042
5043         u8         reserved_at_20[0x10];
5044         u8         op_mod[0x10];
5045
5046         u8         other_vport[0x1];
5047         u8         reserved_at_41[0xf];
5048         u8         vport_number[0x10];
5049
5050         u8         reserved_at_60[0x18];
5051         u8         admin_state[0x4];
5052         u8         reserved_at_7c[0x4];
5053 };
5054
5055 struct mlx5_ifc_modify_tis_out_bits {
5056         u8         status[0x8];
5057         u8         reserved_at_8[0x18];
5058
5059         u8         syndrome[0x20];
5060
5061         u8         reserved_at_40[0x40];
5062 };
5063
5064 struct mlx5_ifc_modify_tis_bitmask_bits {
5065         u8         reserved_at_0[0x20];
5066
5067         u8         reserved_at_20[0x1d];
5068         u8         lag_tx_port_affinity[0x1];
5069         u8         strict_lag_tx_port_affinity[0x1];
5070         u8         prio[0x1];
5071 };
5072
5073 struct mlx5_ifc_modify_tis_in_bits {
5074         u8         opcode[0x10];
5075         u8         reserved_at_10[0x10];
5076
5077         u8         reserved_at_20[0x10];
5078         u8         op_mod[0x10];
5079
5080         u8         reserved_at_40[0x8];
5081         u8         tisn[0x18];
5082
5083         u8         reserved_at_60[0x20];
5084
5085         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5086
5087         u8         reserved_at_c0[0x40];
5088
5089         struct mlx5_ifc_tisc_bits ctx;
5090 };
5091
5092 struct mlx5_ifc_modify_tir_bitmask_bits {
5093         u8         reserved_at_0[0x20];
5094
5095         u8         reserved_at_20[0x1b];
5096         u8         self_lb_en[0x1];
5097         u8         reserved_at_3c[0x1];
5098         u8         hash[0x1];
5099         u8         reserved_at_3e[0x1];
5100         u8         lro[0x1];
5101 };
5102
5103 struct mlx5_ifc_modify_tir_out_bits {
5104         u8         status[0x8];
5105         u8         reserved_at_8[0x18];
5106
5107         u8         syndrome[0x20];
5108
5109         u8         reserved_at_40[0x40];
5110 };
5111
5112 struct mlx5_ifc_modify_tir_in_bits {
5113         u8         opcode[0x10];
5114         u8         reserved_at_10[0x10];
5115
5116         u8         reserved_at_20[0x10];
5117         u8         op_mod[0x10];
5118
5119         u8         reserved_at_40[0x8];
5120         u8         tirn[0x18];
5121
5122         u8         reserved_at_60[0x20];
5123
5124         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5125
5126         u8         reserved_at_c0[0x40];
5127
5128         struct mlx5_ifc_tirc_bits ctx;
5129 };
5130
5131 struct mlx5_ifc_modify_sq_out_bits {
5132         u8         status[0x8];
5133         u8         reserved_at_8[0x18];
5134
5135         u8         syndrome[0x20];
5136
5137         u8         reserved_at_40[0x40];
5138 };
5139
5140 struct mlx5_ifc_modify_sq_in_bits {
5141         u8         opcode[0x10];
5142         u8         reserved_at_10[0x10];
5143
5144         u8         reserved_at_20[0x10];
5145         u8         op_mod[0x10];
5146
5147         u8         sq_state[0x4];
5148         u8         reserved_at_44[0x4];
5149         u8         sqn[0x18];
5150
5151         u8         reserved_at_60[0x20];
5152
5153         u8         modify_bitmask[0x40];
5154
5155         u8         reserved_at_c0[0x40];
5156
5157         struct mlx5_ifc_sqc_bits ctx;
5158 };
5159
5160 struct mlx5_ifc_modify_scheduling_element_out_bits {
5161         u8         status[0x8];
5162         u8         reserved_at_8[0x18];
5163
5164         u8         syndrome[0x20];
5165
5166         u8         reserved_at_40[0x1c0];
5167 };
5168
5169 enum {
5170         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5171         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5172 };
5173
5174 struct mlx5_ifc_modify_scheduling_element_in_bits {
5175         u8         opcode[0x10];
5176         u8         reserved_at_10[0x10];
5177
5178         u8         reserved_at_20[0x10];
5179         u8         op_mod[0x10];
5180
5181         u8         scheduling_hierarchy[0x8];
5182         u8         reserved_at_48[0x18];
5183
5184         u8         scheduling_element_id[0x20];
5185
5186         u8         reserved_at_80[0x20];
5187
5188         u8         modify_bitmask[0x20];
5189
5190         u8         reserved_at_c0[0x40];
5191
5192         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5193
5194         u8         reserved_at_300[0x100];
5195 };
5196
5197 struct mlx5_ifc_modify_rqt_out_bits {
5198         u8         status[0x8];
5199         u8         reserved_at_8[0x18];
5200
5201         u8         syndrome[0x20];
5202
5203         u8         reserved_at_40[0x40];
5204 };
5205
5206 struct mlx5_ifc_rqt_bitmask_bits {
5207         u8         reserved_at_0[0x20];
5208
5209         u8         reserved_at_20[0x1f];
5210         u8         rqn_list[0x1];
5211 };
5212
5213 struct mlx5_ifc_modify_rqt_in_bits {
5214         u8         opcode[0x10];
5215         u8         reserved_at_10[0x10];
5216
5217         u8         reserved_at_20[0x10];
5218         u8         op_mod[0x10];
5219
5220         u8         reserved_at_40[0x8];
5221         u8         rqtn[0x18];
5222
5223         u8         reserved_at_60[0x20];
5224
5225         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5226
5227         u8         reserved_at_c0[0x40];
5228
5229         struct mlx5_ifc_rqtc_bits ctx;
5230 };
5231
5232 struct mlx5_ifc_modify_rq_out_bits {
5233         u8         status[0x8];
5234         u8         reserved_at_8[0x18];
5235
5236         u8         syndrome[0x20];
5237
5238         u8         reserved_at_40[0x40];
5239 };
5240
5241 enum {
5242         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5243         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5244         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5245 };
5246
5247 struct mlx5_ifc_modify_rq_in_bits {
5248         u8         opcode[0x10];
5249         u8         reserved_at_10[0x10];
5250
5251         u8         reserved_at_20[0x10];
5252         u8         op_mod[0x10];
5253
5254         u8         rq_state[0x4];
5255         u8         reserved_at_44[0x4];
5256         u8         rqn[0x18];
5257
5258         u8         reserved_at_60[0x20];
5259
5260         u8         modify_bitmask[0x40];
5261
5262         u8         reserved_at_c0[0x40];
5263
5264         struct mlx5_ifc_rqc_bits ctx;
5265 };
5266
5267 struct mlx5_ifc_modify_rmp_out_bits {
5268         u8         status[0x8];
5269         u8         reserved_at_8[0x18];
5270
5271         u8         syndrome[0x20];
5272
5273         u8         reserved_at_40[0x40];
5274 };
5275
5276 struct mlx5_ifc_rmp_bitmask_bits {
5277         u8         reserved_at_0[0x20];
5278
5279         u8         reserved_at_20[0x1f];
5280         u8         lwm[0x1];
5281 };
5282
5283 struct mlx5_ifc_modify_rmp_in_bits {
5284         u8         opcode[0x10];
5285         u8         reserved_at_10[0x10];
5286
5287         u8         reserved_at_20[0x10];
5288         u8         op_mod[0x10];
5289
5290         u8         rmp_state[0x4];
5291         u8         reserved_at_44[0x4];
5292         u8         rmpn[0x18];
5293
5294         u8         reserved_at_60[0x20];
5295
5296         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5297
5298         u8         reserved_at_c0[0x40];
5299
5300         struct mlx5_ifc_rmpc_bits ctx;
5301 };
5302
5303 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5304         u8         status[0x8];
5305         u8         reserved_at_8[0x18];
5306
5307         u8         syndrome[0x20];
5308
5309         u8         reserved_at_40[0x40];
5310 };
5311
5312 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5313         u8         reserved_at_0[0x14];
5314         u8         disable_uc_local_lb[0x1];
5315         u8         disable_mc_local_lb[0x1];
5316         u8         node_guid[0x1];
5317         u8         port_guid[0x1];
5318         u8         min_inline[0x1];
5319         u8         mtu[0x1];
5320         u8         change_event[0x1];
5321         u8         promisc[0x1];
5322         u8         permanent_address[0x1];
5323         u8         addresses_list[0x1];
5324         u8         roce_en[0x1];
5325         u8         reserved_at_1f[0x1];
5326 };
5327
5328 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5329         u8         opcode[0x10];
5330         u8         reserved_at_10[0x10];
5331
5332         u8         reserved_at_20[0x10];
5333         u8         op_mod[0x10];
5334
5335         u8         other_vport[0x1];
5336         u8         reserved_at_41[0xf];
5337         u8         vport_number[0x10];
5338
5339         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5340
5341         u8         reserved_at_80[0x780];
5342
5343         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5344 };
5345
5346 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5347         u8         status[0x8];
5348         u8         reserved_at_8[0x18];
5349
5350         u8         syndrome[0x20];
5351
5352         u8         reserved_at_40[0x40];
5353 };
5354
5355 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5356         u8         opcode[0x10];
5357         u8         reserved_at_10[0x10];
5358
5359         u8         reserved_at_20[0x10];
5360         u8         op_mod[0x10];
5361
5362         u8         other_vport[0x1];
5363         u8         reserved_at_41[0xb];
5364         u8         port_num[0x4];
5365         u8         vport_number[0x10];
5366
5367         u8         reserved_at_60[0x20];
5368
5369         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5370 };
5371
5372 struct mlx5_ifc_modify_cq_out_bits {
5373         u8         status[0x8];
5374         u8         reserved_at_8[0x18];
5375
5376         u8         syndrome[0x20];
5377
5378         u8         reserved_at_40[0x40];
5379 };
5380
5381 enum {
5382         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5383         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5384 };
5385
5386 struct mlx5_ifc_modify_cq_in_bits {
5387         u8         opcode[0x10];
5388         u8         reserved_at_10[0x10];
5389
5390         u8         reserved_at_20[0x10];
5391         u8         op_mod[0x10];
5392
5393         u8         reserved_at_40[0x8];
5394         u8         cqn[0x18];
5395
5396         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5397
5398         struct mlx5_ifc_cqc_bits cq_context;
5399
5400         u8         reserved_at_280[0x600];
5401
5402         u8         pas[0][0x40];
5403 };
5404
5405 struct mlx5_ifc_modify_cong_status_out_bits {
5406         u8         status[0x8];
5407         u8         reserved_at_8[0x18];
5408
5409         u8         syndrome[0x20];
5410
5411         u8         reserved_at_40[0x40];
5412 };
5413
5414 struct mlx5_ifc_modify_cong_status_in_bits {
5415         u8         opcode[0x10];
5416         u8         reserved_at_10[0x10];
5417
5418         u8         reserved_at_20[0x10];
5419         u8         op_mod[0x10];
5420
5421         u8         reserved_at_40[0x18];
5422         u8         priority[0x4];
5423         u8         cong_protocol[0x4];
5424
5425         u8         enable[0x1];
5426         u8         tag_enable[0x1];
5427         u8         reserved_at_62[0x1e];
5428 };
5429
5430 struct mlx5_ifc_modify_cong_params_out_bits {
5431         u8         status[0x8];
5432         u8         reserved_at_8[0x18];
5433
5434         u8         syndrome[0x20];
5435
5436         u8         reserved_at_40[0x40];
5437 };
5438
5439 struct mlx5_ifc_modify_cong_params_in_bits {
5440         u8         opcode[0x10];
5441         u8         reserved_at_10[0x10];
5442
5443         u8         reserved_at_20[0x10];
5444         u8         op_mod[0x10];
5445
5446         u8         reserved_at_40[0x1c];
5447         u8         cong_protocol[0x4];
5448
5449         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5450
5451         u8         reserved_at_80[0x80];
5452
5453         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5454 };
5455
5456 struct mlx5_ifc_manage_pages_out_bits {
5457         u8         status[0x8];
5458         u8         reserved_at_8[0x18];
5459
5460         u8         syndrome[0x20];
5461
5462         u8         output_num_entries[0x20];
5463
5464         u8         reserved_at_60[0x20];
5465
5466         u8         pas[0][0x40];
5467 };
5468
5469 enum {
5470         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5471         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5472         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5473 };
5474
5475 struct mlx5_ifc_manage_pages_in_bits {
5476         u8         opcode[0x10];
5477         u8         reserved_at_10[0x10];
5478
5479         u8         reserved_at_20[0x10];
5480         u8         op_mod[0x10];
5481
5482         u8         reserved_at_40[0x10];
5483         u8         function_id[0x10];
5484
5485         u8         input_num_entries[0x20];
5486
5487         u8         pas[0][0x40];
5488 };
5489
5490 struct mlx5_ifc_mad_ifc_out_bits {
5491         u8         status[0x8];
5492         u8         reserved_at_8[0x18];
5493
5494         u8         syndrome[0x20];
5495
5496         u8         reserved_at_40[0x40];
5497
5498         u8         response_mad_packet[256][0x8];
5499 };
5500
5501 struct mlx5_ifc_mad_ifc_in_bits {
5502         u8         opcode[0x10];
5503         u8         reserved_at_10[0x10];
5504
5505         u8         reserved_at_20[0x10];
5506         u8         op_mod[0x10];
5507
5508         u8         remote_lid[0x10];
5509         u8         reserved_at_50[0x8];
5510         u8         port[0x8];
5511
5512         u8         reserved_at_60[0x20];
5513
5514         u8         mad[256][0x8];
5515 };
5516
5517 struct mlx5_ifc_init_hca_out_bits {
5518         u8         status[0x8];
5519         u8         reserved_at_8[0x18];
5520
5521         u8         syndrome[0x20];
5522
5523         u8         reserved_at_40[0x40];
5524 };
5525
5526 struct mlx5_ifc_init_hca_in_bits {
5527         u8         opcode[0x10];
5528         u8         reserved_at_10[0x10];
5529
5530         u8         reserved_at_20[0x10];
5531         u8         op_mod[0x10];
5532
5533         u8         reserved_at_40[0x40];
5534 };
5535
5536 struct mlx5_ifc_init2rtr_qp_out_bits {
5537         u8         status[0x8];
5538         u8         reserved_at_8[0x18];
5539
5540         u8         syndrome[0x20];
5541
5542         u8         reserved_at_40[0x40];
5543 };
5544
5545 struct mlx5_ifc_init2rtr_qp_in_bits {
5546         u8         opcode[0x10];
5547         u8         reserved_at_10[0x10];
5548
5549         u8         reserved_at_20[0x10];
5550         u8         op_mod[0x10];
5551
5552         u8         reserved_at_40[0x8];
5553         u8         qpn[0x18];
5554
5555         u8         reserved_at_60[0x20];
5556
5557         u8         opt_param_mask[0x20];
5558
5559         u8         reserved_at_a0[0x20];
5560
5561         struct mlx5_ifc_qpc_bits qpc;
5562
5563         u8         reserved_at_800[0x80];
5564 };
5565
5566 struct mlx5_ifc_init2init_qp_out_bits {
5567         u8         status[0x8];
5568         u8         reserved_at_8[0x18];
5569
5570         u8         syndrome[0x20];
5571
5572         u8         reserved_at_40[0x40];
5573 };
5574
5575 struct mlx5_ifc_init2init_qp_in_bits {
5576         u8         opcode[0x10];
5577         u8         reserved_at_10[0x10];
5578
5579         u8         reserved_at_20[0x10];
5580         u8         op_mod[0x10];
5581
5582         u8         reserved_at_40[0x8];
5583         u8         qpn[0x18];
5584
5585         u8         reserved_at_60[0x20];
5586
5587         u8         opt_param_mask[0x20];
5588
5589         u8         reserved_at_a0[0x20];
5590
5591         struct mlx5_ifc_qpc_bits qpc;
5592
5593         u8         reserved_at_800[0x80];
5594 };
5595
5596 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5597         u8         status[0x8];
5598         u8         reserved_at_8[0x18];
5599
5600         u8         syndrome[0x20];
5601
5602         u8         reserved_at_40[0x40];
5603
5604         u8         packet_headers_log[128][0x8];
5605
5606         u8         packet_syndrome[64][0x8];
5607 };
5608
5609 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5610         u8         opcode[0x10];
5611         u8         reserved_at_10[0x10];
5612
5613         u8         reserved_at_20[0x10];
5614         u8         op_mod[0x10];
5615
5616         u8         reserved_at_40[0x40];
5617 };
5618
5619 struct mlx5_ifc_gen_eqe_in_bits {
5620         u8         opcode[0x10];
5621         u8         reserved_at_10[0x10];
5622
5623         u8         reserved_at_20[0x10];
5624         u8         op_mod[0x10];
5625
5626         u8         reserved_at_40[0x18];
5627         u8         eq_number[0x8];
5628
5629         u8         reserved_at_60[0x20];
5630
5631         u8         eqe[64][0x8];
5632 };
5633
5634 struct mlx5_ifc_gen_eq_out_bits {
5635         u8         status[0x8];
5636         u8         reserved_at_8[0x18];
5637
5638         u8         syndrome[0x20];
5639
5640         u8         reserved_at_40[0x40];
5641 };
5642
5643 struct mlx5_ifc_enable_hca_out_bits {
5644         u8         status[0x8];
5645         u8         reserved_at_8[0x18];
5646
5647         u8         syndrome[0x20];
5648
5649         u8         reserved_at_40[0x20];
5650 };
5651
5652 struct mlx5_ifc_enable_hca_in_bits {
5653         u8         opcode[0x10];
5654         u8         reserved_at_10[0x10];
5655
5656         u8         reserved_at_20[0x10];
5657         u8         op_mod[0x10];
5658
5659         u8         reserved_at_40[0x10];
5660         u8         function_id[0x10];
5661
5662         u8         reserved_at_60[0x20];
5663 };
5664
5665 struct mlx5_ifc_drain_dct_out_bits {
5666         u8         status[0x8];
5667         u8         reserved_at_8[0x18];
5668
5669         u8         syndrome[0x20];
5670
5671         u8         reserved_at_40[0x40];
5672 };
5673
5674 struct mlx5_ifc_drain_dct_in_bits {
5675         u8         opcode[0x10];
5676         u8         reserved_at_10[0x10];
5677
5678         u8         reserved_at_20[0x10];
5679         u8         op_mod[0x10];
5680
5681         u8         reserved_at_40[0x8];
5682         u8         dctn[0x18];
5683
5684         u8         reserved_at_60[0x20];
5685 };
5686
5687 struct mlx5_ifc_disable_hca_out_bits {
5688         u8         status[0x8];
5689         u8         reserved_at_8[0x18];
5690
5691         u8         syndrome[0x20];
5692
5693         u8         reserved_at_40[0x20];
5694 };
5695
5696 struct mlx5_ifc_disable_hca_in_bits {
5697         u8         opcode[0x10];
5698         u8         reserved_at_10[0x10];
5699
5700         u8         reserved_at_20[0x10];
5701         u8         op_mod[0x10];
5702
5703         u8         reserved_at_40[0x10];
5704         u8         function_id[0x10];
5705
5706         u8         reserved_at_60[0x20];
5707 };
5708
5709 struct mlx5_ifc_detach_from_mcg_out_bits {
5710         u8         status[0x8];
5711         u8         reserved_at_8[0x18];
5712
5713         u8         syndrome[0x20];
5714
5715         u8         reserved_at_40[0x40];
5716 };
5717
5718 struct mlx5_ifc_detach_from_mcg_in_bits {
5719         u8         opcode[0x10];
5720         u8         reserved_at_10[0x10];
5721
5722         u8         reserved_at_20[0x10];
5723         u8         op_mod[0x10];
5724
5725         u8         reserved_at_40[0x8];
5726         u8         qpn[0x18];
5727
5728         u8         reserved_at_60[0x20];
5729
5730         u8         multicast_gid[16][0x8];
5731 };
5732
5733 struct mlx5_ifc_destroy_xrq_out_bits {
5734         u8         status[0x8];
5735         u8         reserved_at_8[0x18];
5736
5737         u8         syndrome[0x20];
5738
5739         u8         reserved_at_40[0x40];
5740 };
5741
5742 struct mlx5_ifc_destroy_xrq_in_bits {
5743         u8         opcode[0x10];
5744         u8         reserved_at_10[0x10];
5745
5746         u8         reserved_at_20[0x10];
5747         u8         op_mod[0x10];
5748
5749         u8         reserved_at_40[0x8];
5750         u8         xrqn[0x18];
5751
5752         u8         reserved_at_60[0x20];
5753 };
5754
5755 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5756         u8         status[0x8];
5757         u8         reserved_at_8[0x18];
5758
5759         u8         syndrome[0x20];
5760
5761         u8         reserved_at_40[0x40];
5762 };
5763
5764 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5765         u8         opcode[0x10];
5766         u8         reserved_at_10[0x10];
5767
5768         u8         reserved_at_20[0x10];
5769         u8         op_mod[0x10];
5770
5771         u8         reserved_at_40[0x8];
5772         u8         xrc_srqn[0x18];
5773
5774         u8         reserved_at_60[0x20];
5775 };
5776
5777 struct mlx5_ifc_destroy_tis_out_bits {
5778         u8         status[0x8];
5779         u8         reserved_at_8[0x18];
5780
5781         u8         syndrome[0x20];
5782
5783         u8         reserved_at_40[0x40];
5784 };
5785
5786 struct mlx5_ifc_destroy_tis_in_bits {
5787         u8         opcode[0x10];
5788         u8         reserved_at_10[0x10];
5789
5790         u8         reserved_at_20[0x10];
5791         u8         op_mod[0x10];
5792
5793         u8         reserved_at_40[0x8];
5794         u8         tisn[0x18];
5795
5796         u8         reserved_at_60[0x20];
5797 };
5798
5799 struct mlx5_ifc_destroy_tir_out_bits {
5800         u8         status[0x8];
5801         u8         reserved_at_8[0x18];
5802
5803         u8         syndrome[0x20];
5804
5805         u8         reserved_at_40[0x40];
5806 };
5807
5808 struct mlx5_ifc_destroy_tir_in_bits {
5809         u8         opcode[0x10];
5810         u8         reserved_at_10[0x10];
5811
5812         u8         reserved_at_20[0x10];
5813         u8         op_mod[0x10];
5814
5815         u8         reserved_at_40[0x8];
5816         u8         tirn[0x18];
5817
5818         u8         reserved_at_60[0x20];
5819 };
5820
5821 struct mlx5_ifc_destroy_srq_out_bits {
5822         u8         status[0x8];
5823         u8         reserved_at_8[0x18];
5824
5825         u8         syndrome[0x20];
5826
5827         u8         reserved_at_40[0x40];
5828 };
5829
5830 struct mlx5_ifc_destroy_srq_in_bits {
5831         u8         opcode[0x10];
5832         u8         reserved_at_10[0x10];
5833
5834         u8         reserved_at_20[0x10];
5835         u8         op_mod[0x10];
5836
5837         u8         reserved_at_40[0x8];
5838         u8         srqn[0x18];
5839
5840         u8         reserved_at_60[0x20];
5841 };
5842
5843 struct mlx5_ifc_destroy_sq_out_bits {
5844         u8         status[0x8];
5845         u8         reserved_at_8[0x18];
5846
5847         u8         syndrome[0x20];
5848
5849         u8         reserved_at_40[0x40];
5850 };
5851
5852 struct mlx5_ifc_destroy_sq_in_bits {
5853         u8         opcode[0x10];
5854         u8         reserved_at_10[0x10];
5855
5856         u8         reserved_at_20[0x10];
5857         u8         op_mod[0x10];
5858
5859         u8         reserved_at_40[0x8];
5860         u8         sqn[0x18];
5861
5862         u8         reserved_at_60[0x20];
5863 };
5864
5865 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5866         u8         status[0x8];
5867         u8         reserved_at_8[0x18];
5868
5869         u8         syndrome[0x20];
5870
5871         u8         reserved_at_40[0x1c0];
5872 };
5873
5874 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5875         u8         opcode[0x10];
5876         u8         reserved_at_10[0x10];
5877
5878         u8         reserved_at_20[0x10];
5879         u8         op_mod[0x10];
5880
5881         u8         scheduling_hierarchy[0x8];
5882         u8         reserved_at_48[0x18];
5883
5884         u8         scheduling_element_id[0x20];
5885
5886         u8         reserved_at_80[0x180];
5887 };
5888
5889 struct mlx5_ifc_destroy_rqt_out_bits {
5890         u8         status[0x8];
5891         u8         reserved_at_8[0x18];
5892
5893         u8         syndrome[0x20];
5894
5895         u8         reserved_at_40[0x40];
5896 };
5897
5898 struct mlx5_ifc_destroy_rqt_in_bits {
5899         u8         opcode[0x10];
5900         u8         reserved_at_10[0x10];
5901
5902         u8         reserved_at_20[0x10];
5903         u8         op_mod[0x10];
5904
5905         u8         reserved_at_40[0x8];
5906         u8         rqtn[0x18];
5907
5908         u8         reserved_at_60[0x20];
5909 };
5910
5911 struct mlx5_ifc_destroy_rq_out_bits {
5912         u8         status[0x8];
5913         u8         reserved_at_8[0x18];
5914
5915         u8         syndrome[0x20];
5916
5917         u8         reserved_at_40[0x40];
5918 };
5919
5920 struct mlx5_ifc_destroy_rq_in_bits {
5921         u8         opcode[0x10];
5922         u8         reserved_at_10[0x10];
5923
5924         u8         reserved_at_20[0x10];
5925         u8         op_mod[0x10];
5926
5927         u8         reserved_at_40[0x8];
5928         u8         rqn[0x18];
5929
5930         u8         reserved_at_60[0x20];
5931 };
5932
5933 struct mlx5_ifc_set_delay_drop_params_in_bits {
5934         u8         opcode[0x10];
5935         u8         reserved_at_10[0x10];
5936
5937         u8         reserved_at_20[0x10];
5938         u8         op_mod[0x10];
5939
5940         u8         reserved_at_40[0x20];
5941
5942         u8         reserved_at_60[0x10];
5943         u8         delay_drop_timeout[0x10];
5944 };
5945
5946 struct mlx5_ifc_set_delay_drop_params_out_bits {
5947         u8         status[0x8];
5948         u8         reserved_at_8[0x18];
5949
5950         u8         syndrome[0x20];
5951
5952         u8         reserved_at_40[0x40];
5953 };
5954
5955 struct mlx5_ifc_destroy_rmp_out_bits {
5956         u8         status[0x8];
5957         u8         reserved_at_8[0x18];
5958
5959         u8         syndrome[0x20];
5960
5961         u8         reserved_at_40[0x40];
5962 };
5963
5964 struct mlx5_ifc_destroy_rmp_in_bits {
5965         u8         opcode[0x10];
5966         u8         reserved_at_10[0x10];
5967
5968         u8         reserved_at_20[0x10];
5969         u8         op_mod[0x10];
5970
5971         u8         reserved_at_40[0x8];
5972         u8         rmpn[0x18];
5973
5974         u8         reserved_at_60[0x20];
5975 };
5976
5977 struct mlx5_ifc_destroy_qp_out_bits {
5978         u8         status[0x8];
5979         u8         reserved_at_8[0x18];
5980
5981         u8         syndrome[0x20];
5982
5983         u8         reserved_at_40[0x40];
5984 };
5985
5986 struct mlx5_ifc_destroy_qp_in_bits {
5987         u8         opcode[0x10];
5988         u8         reserved_at_10[0x10];
5989
5990         u8         reserved_at_20[0x10];
5991         u8         op_mod[0x10];
5992
5993         u8         reserved_at_40[0x8];
5994         u8         qpn[0x18];
5995
5996         u8         reserved_at_60[0x20];
5997 };
5998
5999 struct mlx5_ifc_destroy_psv_out_bits {
6000         u8         status[0x8];
6001         u8         reserved_at_8[0x18];
6002
6003         u8         syndrome[0x20];
6004
6005         u8         reserved_at_40[0x40];
6006 };
6007
6008 struct mlx5_ifc_destroy_psv_in_bits {
6009         u8         opcode[0x10];
6010         u8         reserved_at_10[0x10];
6011
6012         u8         reserved_at_20[0x10];
6013         u8         op_mod[0x10];
6014
6015         u8         reserved_at_40[0x8];
6016         u8         psvn[0x18];
6017
6018         u8         reserved_at_60[0x20];
6019 };
6020
6021 struct mlx5_ifc_destroy_mkey_out_bits {
6022         u8         status[0x8];
6023         u8         reserved_at_8[0x18];
6024
6025         u8         syndrome[0x20];
6026
6027         u8         reserved_at_40[0x40];
6028 };
6029
6030 struct mlx5_ifc_destroy_mkey_in_bits {
6031         u8         opcode[0x10];
6032         u8         reserved_at_10[0x10];
6033
6034         u8         reserved_at_20[0x10];
6035         u8         op_mod[0x10];
6036
6037         u8         reserved_at_40[0x8];
6038         u8         mkey_index[0x18];
6039
6040         u8         reserved_at_60[0x20];
6041 };
6042
6043 struct mlx5_ifc_destroy_flow_table_out_bits {
6044         u8         status[0x8];
6045         u8         reserved_at_8[0x18];
6046
6047         u8         syndrome[0x20];
6048
6049         u8         reserved_at_40[0x40];
6050 };
6051
6052 struct mlx5_ifc_destroy_flow_table_in_bits {
6053         u8         opcode[0x10];
6054         u8         reserved_at_10[0x10];
6055
6056         u8         reserved_at_20[0x10];
6057         u8         op_mod[0x10];
6058
6059         u8         other_vport[0x1];
6060         u8         reserved_at_41[0xf];
6061         u8         vport_number[0x10];
6062
6063         u8         reserved_at_60[0x20];
6064
6065         u8         table_type[0x8];
6066         u8         reserved_at_88[0x18];
6067
6068         u8         reserved_at_a0[0x8];
6069         u8         table_id[0x18];
6070
6071         u8         reserved_at_c0[0x140];
6072 };
6073
6074 struct mlx5_ifc_destroy_flow_group_out_bits {
6075         u8         status[0x8];
6076         u8         reserved_at_8[0x18];
6077
6078         u8         syndrome[0x20];
6079
6080         u8         reserved_at_40[0x40];
6081 };
6082
6083 struct mlx5_ifc_destroy_flow_group_in_bits {
6084         u8         opcode[0x10];
6085         u8         reserved_at_10[0x10];
6086
6087         u8         reserved_at_20[0x10];
6088         u8         op_mod[0x10];
6089
6090         u8         other_vport[0x1];
6091         u8         reserved_at_41[0xf];
6092         u8         vport_number[0x10];
6093
6094         u8         reserved_at_60[0x20];
6095
6096         u8         table_type[0x8];
6097         u8         reserved_at_88[0x18];
6098
6099         u8         reserved_at_a0[0x8];
6100         u8         table_id[0x18];
6101
6102         u8         group_id[0x20];
6103
6104         u8         reserved_at_e0[0x120];
6105 };
6106
6107 struct mlx5_ifc_destroy_eq_out_bits {
6108         u8         status[0x8];
6109         u8         reserved_at_8[0x18];
6110
6111         u8         syndrome[0x20];
6112
6113         u8         reserved_at_40[0x40];
6114 };
6115
6116 struct mlx5_ifc_destroy_eq_in_bits {
6117         u8         opcode[0x10];
6118         u8         reserved_at_10[0x10];
6119
6120         u8         reserved_at_20[0x10];
6121         u8         op_mod[0x10];
6122
6123         u8         reserved_at_40[0x18];
6124         u8         eq_number[0x8];
6125
6126         u8         reserved_at_60[0x20];
6127 };
6128
6129 struct mlx5_ifc_destroy_dct_out_bits {
6130         u8         status[0x8];
6131         u8         reserved_at_8[0x18];
6132
6133         u8         syndrome[0x20];
6134
6135         u8         reserved_at_40[0x40];
6136 };
6137
6138 struct mlx5_ifc_destroy_dct_in_bits {
6139         u8         opcode[0x10];
6140         u8         reserved_at_10[0x10];
6141
6142         u8         reserved_at_20[0x10];
6143         u8         op_mod[0x10];
6144
6145         u8         reserved_at_40[0x8];
6146         u8         dctn[0x18];
6147
6148         u8         reserved_at_60[0x20];
6149 };
6150
6151 struct mlx5_ifc_destroy_cq_out_bits {
6152         u8         status[0x8];
6153         u8         reserved_at_8[0x18];
6154
6155         u8         syndrome[0x20];
6156
6157         u8         reserved_at_40[0x40];
6158 };
6159
6160 struct mlx5_ifc_destroy_cq_in_bits {
6161         u8         opcode[0x10];
6162         u8         reserved_at_10[0x10];
6163
6164         u8         reserved_at_20[0x10];
6165         u8         op_mod[0x10];
6166
6167         u8         reserved_at_40[0x8];
6168         u8         cqn[0x18];
6169
6170         u8         reserved_at_60[0x20];
6171 };
6172
6173 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6174         u8         status[0x8];
6175         u8         reserved_at_8[0x18];
6176
6177         u8         syndrome[0x20];
6178
6179         u8         reserved_at_40[0x40];
6180 };
6181
6182 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6183         u8         opcode[0x10];
6184         u8         reserved_at_10[0x10];
6185
6186         u8         reserved_at_20[0x10];
6187         u8         op_mod[0x10];
6188
6189         u8         reserved_at_40[0x20];
6190
6191         u8         reserved_at_60[0x10];
6192         u8         vxlan_udp_port[0x10];
6193 };
6194
6195 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6196         u8         status[0x8];
6197         u8         reserved_at_8[0x18];
6198
6199         u8         syndrome[0x20];
6200
6201         u8         reserved_at_40[0x40];
6202 };
6203
6204 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6205         u8         opcode[0x10];
6206         u8         reserved_at_10[0x10];
6207
6208         u8         reserved_at_20[0x10];
6209         u8         op_mod[0x10];
6210
6211         u8         reserved_at_40[0x60];
6212
6213         u8         reserved_at_a0[0x8];
6214         u8         table_index[0x18];
6215
6216         u8         reserved_at_c0[0x140];
6217 };
6218
6219 struct mlx5_ifc_delete_fte_out_bits {
6220         u8         status[0x8];
6221         u8         reserved_at_8[0x18];
6222
6223         u8         syndrome[0x20];
6224
6225         u8         reserved_at_40[0x40];
6226 };
6227
6228 struct mlx5_ifc_delete_fte_in_bits {
6229         u8         opcode[0x10];
6230         u8         reserved_at_10[0x10];
6231
6232         u8         reserved_at_20[0x10];
6233         u8         op_mod[0x10];
6234
6235         u8         other_vport[0x1];
6236         u8         reserved_at_41[0xf];
6237         u8         vport_number[0x10];
6238
6239         u8         reserved_at_60[0x20];
6240
6241         u8         table_type[0x8];
6242         u8         reserved_at_88[0x18];
6243
6244         u8         reserved_at_a0[0x8];
6245         u8         table_id[0x18];
6246
6247         u8         reserved_at_c0[0x40];
6248
6249         u8         flow_index[0x20];
6250
6251         u8         reserved_at_120[0xe0];
6252 };
6253
6254 struct mlx5_ifc_dealloc_xrcd_out_bits {
6255         u8         status[0x8];
6256         u8         reserved_at_8[0x18];
6257
6258         u8         syndrome[0x20];
6259
6260         u8         reserved_at_40[0x40];
6261 };
6262
6263 struct mlx5_ifc_dealloc_xrcd_in_bits {
6264         u8         opcode[0x10];
6265         u8         reserved_at_10[0x10];
6266
6267         u8         reserved_at_20[0x10];
6268         u8         op_mod[0x10];
6269
6270         u8         reserved_at_40[0x8];
6271         u8         xrcd[0x18];
6272
6273         u8         reserved_at_60[0x20];
6274 };
6275
6276 struct mlx5_ifc_dealloc_uar_out_bits {
6277         u8         status[0x8];
6278         u8         reserved_at_8[0x18];
6279
6280         u8         syndrome[0x20];
6281
6282         u8         reserved_at_40[0x40];
6283 };
6284
6285 struct mlx5_ifc_dealloc_uar_in_bits {
6286         u8         opcode[0x10];
6287         u8         reserved_at_10[0x10];
6288
6289         u8         reserved_at_20[0x10];
6290         u8         op_mod[0x10];
6291
6292         u8         reserved_at_40[0x8];
6293         u8         uar[0x18];
6294
6295         u8         reserved_at_60[0x20];
6296 };
6297
6298 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6299         u8         status[0x8];
6300         u8         reserved_at_8[0x18];
6301
6302         u8         syndrome[0x20];
6303
6304         u8         reserved_at_40[0x40];
6305 };
6306
6307 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6308         u8         opcode[0x10];
6309         u8         reserved_at_10[0x10];
6310
6311         u8         reserved_at_20[0x10];
6312         u8         op_mod[0x10];
6313
6314         u8         reserved_at_40[0x8];
6315         u8         transport_domain[0x18];
6316
6317         u8         reserved_at_60[0x20];
6318 };
6319
6320 struct mlx5_ifc_dealloc_q_counter_out_bits {
6321         u8         status[0x8];
6322         u8         reserved_at_8[0x18];
6323
6324         u8         syndrome[0x20];
6325
6326         u8         reserved_at_40[0x40];
6327 };
6328
6329 struct mlx5_ifc_dealloc_q_counter_in_bits {
6330         u8         opcode[0x10];
6331         u8         reserved_at_10[0x10];
6332
6333         u8         reserved_at_20[0x10];
6334         u8         op_mod[0x10];
6335
6336         u8         reserved_at_40[0x18];
6337         u8         counter_set_id[0x8];
6338
6339         u8         reserved_at_60[0x20];
6340 };
6341
6342 struct mlx5_ifc_dealloc_pd_out_bits {
6343         u8         status[0x8];
6344         u8         reserved_at_8[0x18];
6345
6346         u8         syndrome[0x20];
6347
6348         u8         reserved_at_40[0x40];
6349 };
6350
6351 struct mlx5_ifc_dealloc_pd_in_bits {
6352         u8         opcode[0x10];
6353         u8         reserved_at_10[0x10];
6354
6355         u8         reserved_at_20[0x10];
6356         u8         op_mod[0x10];
6357
6358         u8         reserved_at_40[0x8];
6359         u8         pd[0x18];
6360
6361         u8         reserved_at_60[0x20];
6362 };
6363
6364 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6365         u8         status[0x8];
6366         u8         reserved_at_8[0x18];
6367
6368         u8         syndrome[0x20];
6369
6370         u8         reserved_at_40[0x40];
6371 };
6372
6373 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6374         u8         opcode[0x10];
6375         u8         reserved_at_10[0x10];
6376
6377         u8         reserved_at_20[0x10];
6378         u8         op_mod[0x10];
6379
6380         u8         flow_counter_id[0x20];
6381
6382         u8         reserved_at_60[0x20];
6383 };
6384
6385 struct mlx5_ifc_create_xrq_out_bits {
6386         u8         status[0x8];
6387         u8         reserved_at_8[0x18];
6388
6389         u8         syndrome[0x20];
6390
6391         u8         reserved_at_40[0x8];
6392         u8         xrqn[0x18];
6393
6394         u8         reserved_at_60[0x20];
6395 };
6396
6397 struct mlx5_ifc_create_xrq_in_bits {
6398         u8         opcode[0x10];
6399         u8         reserved_at_10[0x10];
6400
6401         u8         reserved_at_20[0x10];
6402         u8         op_mod[0x10];
6403
6404         u8         reserved_at_40[0x40];
6405
6406         struct mlx5_ifc_xrqc_bits xrq_context;
6407 };
6408
6409 struct mlx5_ifc_create_xrc_srq_out_bits {
6410         u8         status[0x8];
6411         u8         reserved_at_8[0x18];
6412
6413         u8         syndrome[0x20];
6414
6415         u8         reserved_at_40[0x8];
6416         u8         xrc_srqn[0x18];
6417
6418         u8         reserved_at_60[0x20];
6419 };
6420
6421 struct mlx5_ifc_create_xrc_srq_in_bits {
6422         u8         opcode[0x10];
6423         u8         reserved_at_10[0x10];
6424
6425         u8         reserved_at_20[0x10];
6426         u8         op_mod[0x10];
6427
6428         u8         reserved_at_40[0x40];
6429
6430         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6431
6432         u8         reserved_at_280[0x600];
6433
6434         u8         pas[0][0x40];
6435 };
6436
6437 struct mlx5_ifc_create_tis_out_bits {
6438         u8         status[0x8];
6439         u8         reserved_at_8[0x18];
6440
6441         u8         syndrome[0x20];
6442
6443         u8         reserved_at_40[0x8];
6444         u8         tisn[0x18];
6445
6446         u8         reserved_at_60[0x20];
6447 };
6448
6449 struct mlx5_ifc_create_tis_in_bits {
6450         u8         opcode[0x10];
6451         u8         reserved_at_10[0x10];
6452
6453         u8         reserved_at_20[0x10];
6454         u8         op_mod[0x10];
6455
6456         u8         reserved_at_40[0xc0];
6457
6458         struct mlx5_ifc_tisc_bits ctx;
6459 };
6460
6461 struct mlx5_ifc_create_tir_out_bits {
6462         u8         status[0x8];
6463         u8         reserved_at_8[0x18];
6464
6465         u8         syndrome[0x20];
6466
6467         u8         reserved_at_40[0x8];
6468         u8         tirn[0x18];
6469
6470         u8         reserved_at_60[0x20];
6471 };
6472
6473 struct mlx5_ifc_create_tir_in_bits {
6474         u8         opcode[0x10];
6475         u8         reserved_at_10[0x10];
6476
6477         u8         reserved_at_20[0x10];
6478         u8         op_mod[0x10];
6479
6480         u8         reserved_at_40[0xc0];
6481
6482         struct mlx5_ifc_tirc_bits ctx;
6483 };
6484
6485 struct mlx5_ifc_create_srq_out_bits {
6486         u8         status[0x8];
6487         u8         reserved_at_8[0x18];
6488
6489         u8         syndrome[0x20];
6490
6491         u8         reserved_at_40[0x8];
6492         u8         srqn[0x18];
6493
6494         u8         reserved_at_60[0x20];
6495 };
6496
6497 struct mlx5_ifc_create_srq_in_bits {
6498         u8         opcode[0x10];
6499         u8         reserved_at_10[0x10];
6500
6501         u8         reserved_at_20[0x10];
6502         u8         op_mod[0x10];
6503
6504         u8         reserved_at_40[0x40];
6505
6506         struct mlx5_ifc_srqc_bits srq_context_entry;
6507
6508         u8         reserved_at_280[0x600];
6509
6510         u8         pas[0][0x40];
6511 };
6512
6513 struct mlx5_ifc_create_sq_out_bits {
6514         u8         status[0x8];
6515         u8         reserved_at_8[0x18];
6516
6517         u8         syndrome[0x20];
6518
6519         u8         reserved_at_40[0x8];
6520         u8         sqn[0x18];
6521
6522         u8         reserved_at_60[0x20];
6523 };
6524
6525 struct mlx5_ifc_create_sq_in_bits {
6526         u8         opcode[0x10];
6527         u8         reserved_at_10[0x10];
6528
6529         u8         reserved_at_20[0x10];
6530         u8         op_mod[0x10];
6531
6532         u8         reserved_at_40[0xc0];
6533
6534         struct mlx5_ifc_sqc_bits ctx;
6535 };
6536
6537 struct mlx5_ifc_create_scheduling_element_out_bits {
6538         u8         status[0x8];
6539         u8         reserved_at_8[0x18];
6540
6541         u8         syndrome[0x20];
6542
6543         u8         reserved_at_40[0x40];
6544
6545         u8         scheduling_element_id[0x20];
6546
6547         u8         reserved_at_a0[0x160];
6548 };
6549
6550 struct mlx5_ifc_create_scheduling_element_in_bits {
6551         u8         opcode[0x10];
6552         u8         reserved_at_10[0x10];
6553
6554         u8         reserved_at_20[0x10];
6555         u8         op_mod[0x10];
6556
6557         u8         scheduling_hierarchy[0x8];
6558         u8         reserved_at_48[0x18];
6559
6560         u8         reserved_at_60[0xa0];
6561
6562         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6563
6564         u8         reserved_at_300[0x100];
6565 };
6566
6567 struct mlx5_ifc_create_rqt_out_bits {
6568         u8         status[0x8];
6569         u8         reserved_at_8[0x18];
6570
6571         u8         syndrome[0x20];
6572
6573         u8         reserved_at_40[0x8];
6574         u8         rqtn[0x18];
6575
6576         u8         reserved_at_60[0x20];
6577 };
6578
6579 struct mlx5_ifc_create_rqt_in_bits {
6580         u8         opcode[0x10];
6581         u8         reserved_at_10[0x10];
6582
6583         u8         reserved_at_20[0x10];
6584         u8         op_mod[0x10];
6585
6586         u8         reserved_at_40[0xc0];
6587
6588         struct mlx5_ifc_rqtc_bits rqt_context;
6589 };
6590
6591 struct mlx5_ifc_create_rq_out_bits {
6592         u8         status[0x8];
6593         u8         reserved_at_8[0x18];
6594
6595         u8         syndrome[0x20];
6596
6597         u8         reserved_at_40[0x8];
6598         u8         rqn[0x18];
6599
6600         u8         reserved_at_60[0x20];
6601 };
6602
6603 struct mlx5_ifc_create_rq_in_bits {
6604         u8         opcode[0x10];
6605         u8         reserved_at_10[0x10];
6606
6607         u8         reserved_at_20[0x10];
6608         u8         op_mod[0x10];
6609
6610         u8         reserved_at_40[0xc0];
6611
6612         struct mlx5_ifc_rqc_bits ctx;
6613 };
6614
6615 struct mlx5_ifc_create_rmp_out_bits {
6616         u8         status[0x8];
6617         u8         reserved_at_8[0x18];
6618
6619         u8         syndrome[0x20];
6620
6621         u8         reserved_at_40[0x8];
6622         u8         rmpn[0x18];
6623
6624         u8         reserved_at_60[0x20];
6625 };
6626
6627 struct mlx5_ifc_create_rmp_in_bits {
6628         u8         opcode[0x10];
6629         u8         reserved_at_10[0x10];
6630
6631         u8         reserved_at_20[0x10];
6632         u8         op_mod[0x10];
6633
6634         u8         reserved_at_40[0xc0];
6635
6636         struct mlx5_ifc_rmpc_bits ctx;
6637 };
6638
6639 struct mlx5_ifc_create_qp_out_bits {
6640         u8         status[0x8];
6641         u8         reserved_at_8[0x18];
6642
6643         u8         syndrome[0x20];
6644
6645         u8         reserved_at_40[0x8];
6646         u8         qpn[0x18];
6647
6648         u8         reserved_at_60[0x20];
6649 };
6650
6651 struct mlx5_ifc_create_qp_in_bits {
6652         u8         opcode[0x10];
6653         u8         reserved_at_10[0x10];
6654
6655         u8         reserved_at_20[0x10];
6656         u8         op_mod[0x10];
6657
6658         u8         reserved_at_40[0x40];
6659
6660         u8         opt_param_mask[0x20];
6661
6662         u8         reserved_at_a0[0x20];
6663
6664         struct mlx5_ifc_qpc_bits qpc;
6665
6666         u8         reserved_at_800[0x80];
6667
6668         u8         pas[0][0x40];
6669 };
6670
6671 struct mlx5_ifc_create_psv_out_bits {
6672         u8         status[0x8];
6673         u8         reserved_at_8[0x18];
6674
6675         u8         syndrome[0x20];
6676
6677         u8         reserved_at_40[0x40];
6678
6679         u8         reserved_at_80[0x8];
6680         u8         psv0_index[0x18];
6681
6682         u8         reserved_at_a0[0x8];
6683         u8         psv1_index[0x18];
6684
6685         u8         reserved_at_c0[0x8];
6686         u8         psv2_index[0x18];
6687
6688         u8         reserved_at_e0[0x8];
6689         u8         psv3_index[0x18];
6690 };
6691
6692 struct mlx5_ifc_create_psv_in_bits {
6693         u8         opcode[0x10];
6694         u8         reserved_at_10[0x10];
6695
6696         u8         reserved_at_20[0x10];
6697         u8         op_mod[0x10];
6698
6699         u8         num_psv[0x4];
6700         u8         reserved_at_44[0x4];
6701         u8         pd[0x18];
6702
6703         u8         reserved_at_60[0x20];
6704 };
6705
6706 struct mlx5_ifc_create_mkey_out_bits {
6707         u8         status[0x8];
6708         u8         reserved_at_8[0x18];
6709
6710         u8         syndrome[0x20];
6711
6712         u8         reserved_at_40[0x8];
6713         u8         mkey_index[0x18];
6714
6715         u8         reserved_at_60[0x20];
6716 };
6717
6718 struct mlx5_ifc_create_mkey_in_bits {
6719         u8         opcode[0x10];
6720         u8         reserved_at_10[0x10];
6721
6722         u8         reserved_at_20[0x10];
6723         u8         op_mod[0x10];
6724
6725         u8         reserved_at_40[0x20];
6726
6727         u8         pg_access[0x1];
6728         u8         reserved_at_61[0x1f];
6729
6730         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6731
6732         u8         reserved_at_280[0x80];
6733
6734         u8         translations_octword_actual_size[0x20];
6735
6736         u8         reserved_at_320[0x560];
6737
6738         u8         klm_pas_mtt[0][0x20];
6739 };
6740
6741 struct mlx5_ifc_create_flow_table_out_bits {
6742         u8         status[0x8];
6743         u8         reserved_at_8[0x18];
6744
6745         u8         syndrome[0x20];
6746
6747         u8         reserved_at_40[0x8];
6748         u8         table_id[0x18];
6749
6750         u8         reserved_at_60[0x20];
6751 };
6752
6753 struct mlx5_ifc_flow_table_context_bits {
6754         u8         encap_en[0x1];
6755         u8         decap_en[0x1];
6756         u8         reserved_at_2[0x2];
6757         u8         table_miss_action[0x4];
6758         u8         level[0x8];
6759         u8         reserved_at_10[0x8];
6760         u8         log_size[0x8];
6761
6762         u8         reserved_at_20[0x8];
6763         u8         table_miss_id[0x18];
6764
6765         u8         reserved_at_40[0x8];
6766         u8         lag_master_next_table_id[0x18];
6767
6768         u8         reserved_at_60[0xe0];
6769 };
6770
6771 struct mlx5_ifc_create_flow_table_in_bits {
6772         u8         opcode[0x10];
6773         u8         reserved_at_10[0x10];
6774
6775         u8         reserved_at_20[0x10];
6776         u8         op_mod[0x10];
6777
6778         u8         other_vport[0x1];
6779         u8         reserved_at_41[0xf];
6780         u8         vport_number[0x10];
6781
6782         u8         reserved_at_60[0x20];
6783
6784         u8         table_type[0x8];
6785         u8         reserved_at_88[0x18];
6786
6787         u8         reserved_at_a0[0x20];
6788
6789         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6790 };
6791
6792 struct mlx5_ifc_create_flow_group_out_bits {
6793         u8         status[0x8];
6794         u8         reserved_at_8[0x18];
6795
6796         u8         syndrome[0x20];
6797
6798         u8         reserved_at_40[0x8];
6799         u8         group_id[0x18];
6800
6801         u8         reserved_at_60[0x20];
6802 };
6803
6804 enum {
6805         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6806         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6807         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6808 };
6809
6810 struct mlx5_ifc_create_flow_group_in_bits {
6811         u8         opcode[0x10];
6812         u8         reserved_at_10[0x10];
6813
6814         u8         reserved_at_20[0x10];
6815         u8         op_mod[0x10];
6816
6817         u8         other_vport[0x1];
6818         u8         reserved_at_41[0xf];
6819         u8         vport_number[0x10];
6820
6821         u8         reserved_at_60[0x20];
6822
6823         u8         table_type[0x8];
6824         u8         reserved_at_88[0x18];
6825
6826         u8         reserved_at_a0[0x8];
6827         u8         table_id[0x18];
6828
6829         u8         reserved_at_c0[0x20];
6830
6831         u8         start_flow_index[0x20];
6832
6833         u8         reserved_at_100[0x20];
6834
6835         u8         end_flow_index[0x20];
6836
6837         u8         reserved_at_140[0xa0];
6838
6839         u8         reserved_at_1e0[0x18];
6840         u8         match_criteria_enable[0x8];
6841
6842         struct mlx5_ifc_fte_match_param_bits match_criteria;
6843
6844         u8         reserved_at_1200[0xe00];
6845 };
6846
6847 struct mlx5_ifc_create_eq_out_bits {
6848         u8         status[0x8];
6849         u8         reserved_at_8[0x18];
6850
6851         u8         syndrome[0x20];
6852
6853         u8         reserved_at_40[0x18];
6854         u8         eq_number[0x8];
6855
6856         u8         reserved_at_60[0x20];
6857 };
6858
6859 struct mlx5_ifc_create_eq_in_bits {
6860         u8         opcode[0x10];
6861         u8         reserved_at_10[0x10];
6862
6863         u8         reserved_at_20[0x10];
6864         u8         op_mod[0x10];
6865
6866         u8         reserved_at_40[0x40];
6867
6868         struct mlx5_ifc_eqc_bits eq_context_entry;
6869
6870         u8         reserved_at_280[0x40];
6871
6872         u8         event_bitmask[0x40];
6873
6874         u8         reserved_at_300[0x580];
6875
6876         u8         pas[0][0x40];
6877 };
6878
6879 struct mlx5_ifc_create_dct_out_bits {
6880         u8         status[0x8];
6881         u8         reserved_at_8[0x18];
6882
6883         u8         syndrome[0x20];
6884
6885         u8         reserved_at_40[0x8];
6886         u8         dctn[0x18];
6887
6888         u8         reserved_at_60[0x20];
6889 };
6890
6891 struct mlx5_ifc_create_dct_in_bits {
6892         u8         opcode[0x10];
6893         u8         reserved_at_10[0x10];
6894
6895         u8         reserved_at_20[0x10];
6896         u8         op_mod[0x10];
6897
6898         u8         reserved_at_40[0x40];
6899
6900         struct mlx5_ifc_dctc_bits dct_context_entry;
6901
6902         u8         reserved_at_280[0x180];
6903 };
6904
6905 struct mlx5_ifc_create_cq_out_bits {
6906         u8         status[0x8];
6907         u8         reserved_at_8[0x18];
6908
6909         u8         syndrome[0x20];
6910
6911         u8         reserved_at_40[0x8];
6912         u8         cqn[0x18];
6913
6914         u8         reserved_at_60[0x20];
6915 };
6916
6917 struct mlx5_ifc_create_cq_in_bits {
6918         u8         opcode[0x10];
6919         u8         reserved_at_10[0x10];
6920
6921         u8         reserved_at_20[0x10];
6922         u8         op_mod[0x10];
6923
6924         u8         reserved_at_40[0x40];
6925
6926         struct mlx5_ifc_cqc_bits cq_context;
6927
6928         u8         reserved_at_280[0x600];
6929
6930         u8         pas[0][0x40];
6931 };
6932
6933 struct mlx5_ifc_config_int_moderation_out_bits {
6934         u8         status[0x8];
6935         u8         reserved_at_8[0x18];
6936
6937         u8         syndrome[0x20];
6938
6939         u8         reserved_at_40[0x4];
6940         u8         min_delay[0xc];
6941         u8         int_vector[0x10];
6942
6943         u8         reserved_at_60[0x20];
6944 };
6945
6946 enum {
6947         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6948         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6949 };
6950
6951 struct mlx5_ifc_config_int_moderation_in_bits {
6952         u8         opcode[0x10];
6953         u8         reserved_at_10[0x10];
6954
6955         u8         reserved_at_20[0x10];
6956         u8         op_mod[0x10];
6957
6958         u8         reserved_at_40[0x4];
6959         u8         min_delay[0xc];
6960         u8         int_vector[0x10];
6961
6962         u8         reserved_at_60[0x20];
6963 };
6964
6965 struct mlx5_ifc_attach_to_mcg_out_bits {
6966         u8         status[0x8];
6967         u8         reserved_at_8[0x18];
6968
6969         u8         syndrome[0x20];
6970
6971         u8         reserved_at_40[0x40];
6972 };
6973
6974 struct mlx5_ifc_attach_to_mcg_in_bits {
6975         u8         opcode[0x10];
6976         u8         reserved_at_10[0x10];
6977
6978         u8         reserved_at_20[0x10];
6979         u8         op_mod[0x10];
6980
6981         u8         reserved_at_40[0x8];
6982         u8         qpn[0x18];
6983
6984         u8         reserved_at_60[0x20];
6985
6986         u8         multicast_gid[16][0x8];
6987 };
6988
6989 struct mlx5_ifc_arm_xrq_out_bits {
6990         u8         status[0x8];
6991         u8         reserved_at_8[0x18];
6992
6993         u8         syndrome[0x20];
6994
6995         u8         reserved_at_40[0x40];
6996 };
6997
6998 struct mlx5_ifc_arm_xrq_in_bits {
6999         u8         opcode[0x10];
7000         u8         reserved_at_10[0x10];
7001
7002         u8         reserved_at_20[0x10];
7003         u8         op_mod[0x10];
7004
7005         u8         reserved_at_40[0x8];
7006         u8         xrqn[0x18];
7007
7008         u8         reserved_at_60[0x10];
7009         u8         lwm[0x10];
7010 };
7011
7012 struct mlx5_ifc_arm_xrc_srq_out_bits {
7013         u8         status[0x8];
7014         u8         reserved_at_8[0x18];
7015
7016         u8         syndrome[0x20];
7017
7018         u8         reserved_at_40[0x40];
7019 };
7020
7021 enum {
7022         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7023 };
7024
7025 struct mlx5_ifc_arm_xrc_srq_in_bits {
7026         u8         opcode[0x10];
7027         u8         reserved_at_10[0x10];
7028
7029         u8         reserved_at_20[0x10];
7030         u8         op_mod[0x10];
7031
7032         u8         reserved_at_40[0x8];
7033         u8         xrc_srqn[0x18];
7034
7035         u8         reserved_at_60[0x10];
7036         u8         lwm[0x10];
7037 };
7038
7039 struct mlx5_ifc_arm_rq_out_bits {
7040         u8         status[0x8];
7041         u8         reserved_at_8[0x18];
7042
7043         u8         syndrome[0x20];
7044
7045         u8         reserved_at_40[0x40];
7046 };
7047
7048 enum {
7049         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7050         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7051 };
7052
7053 struct mlx5_ifc_arm_rq_in_bits {
7054         u8         opcode[0x10];
7055         u8         reserved_at_10[0x10];
7056
7057         u8         reserved_at_20[0x10];
7058         u8         op_mod[0x10];
7059
7060         u8         reserved_at_40[0x8];
7061         u8         srq_number[0x18];
7062
7063         u8         reserved_at_60[0x10];
7064         u8         lwm[0x10];
7065 };
7066
7067 struct mlx5_ifc_arm_dct_out_bits {
7068         u8         status[0x8];
7069         u8         reserved_at_8[0x18];
7070
7071         u8         syndrome[0x20];
7072
7073         u8         reserved_at_40[0x40];
7074 };
7075
7076 struct mlx5_ifc_arm_dct_in_bits {
7077         u8         opcode[0x10];
7078         u8         reserved_at_10[0x10];
7079
7080         u8         reserved_at_20[0x10];
7081         u8         op_mod[0x10];
7082
7083         u8         reserved_at_40[0x8];
7084         u8         dct_number[0x18];
7085
7086         u8         reserved_at_60[0x20];
7087 };
7088
7089 struct mlx5_ifc_alloc_xrcd_out_bits {
7090         u8         status[0x8];
7091         u8         reserved_at_8[0x18];
7092
7093         u8         syndrome[0x20];
7094
7095         u8         reserved_at_40[0x8];
7096         u8         xrcd[0x18];
7097
7098         u8         reserved_at_60[0x20];
7099 };
7100
7101 struct mlx5_ifc_alloc_xrcd_in_bits {
7102         u8         opcode[0x10];
7103         u8         reserved_at_10[0x10];
7104
7105         u8         reserved_at_20[0x10];
7106         u8         op_mod[0x10];
7107
7108         u8         reserved_at_40[0x40];
7109 };
7110
7111 struct mlx5_ifc_alloc_uar_out_bits {
7112         u8         status[0x8];
7113         u8         reserved_at_8[0x18];
7114
7115         u8         syndrome[0x20];
7116
7117         u8         reserved_at_40[0x8];
7118         u8         uar[0x18];
7119
7120         u8         reserved_at_60[0x20];
7121 };
7122
7123 struct mlx5_ifc_alloc_uar_in_bits {
7124         u8         opcode[0x10];
7125         u8         reserved_at_10[0x10];
7126
7127         u8         reserved_at_20[0x10];
7128         u8         op_mod[0x10];
7129
7130         u8         reserved_at_40[0x40];
7131 };
7132
7133 struct mlx5_ifc_alloc_transport_domain_out_bits {
7134         u8         status[0x8];
7135         u8         reserved_at_8[0x18];
7136
7137         u8         syndrome[0x20];
7138
7139         u8         reserved_at_40[0x8];
7140         u8         transport_domain[0x18];
7141
7142         u8         reserved_at_60[0x20];
7143 };
7144
7145 struct mlx5_ifc_alloc_transport_domain_in_bits {
7146         u8         opcode[0x10];
7147         u8         reserved_at_10[0x10];
7148
7149         u8         reserved_at_20[0x10];
7150         u8         op_mod[0x10];
7151
7152         u8         reserved_at_40[0x40];
7153 };
7154
7155 struct mlx5_ifc_alloc_q_counter_out_bits {
7156         u8         status[0x8];
7157         u8         reserved_at_8[0x18];
7158
7159         u8         syndrome[0x20];
7160
7161         u8         reserved_at_40[0x18];
7162         u8         counter_set_id[0x8];
7163
7164         u8         reserved_at_60[0x20];
7165 };
7166
7167 struct mlx5_ifc_alloc_q_counter_in_bits {
7168         u8         opcode[0x10];
7169         u8         reserved_at_10[0x10];
7170
7171         u8         reserved_at_20[0x10];
7172         u8         op_mod[0x10];
7173
7174         u8         reserved_at_40[0x40];
7175 };
7176
7177 struct mlx5_ifc_alloc_pd_out_bits {
7178         u8         status[0x8];
7179         u8         reserved_at_8[0x18];
7180
7181         u8         syndrome[0x20];
7182
7183         u8         reserved_at_40[0x8];
7184         u8         pd[0x18];
7185
7186         u8         reserved_at_60[0x20];
7187 };
7188
7189 struct mlx5_ifc_alloc_pd_in_bits {
7190         u8         opcode[0x10];
7191         u8         reserved_at_10[0x10];
7192
7193         u8         reserved_at_20[0x10];
7194         u8         op_mod[0x10];
7195
7196         u8         reserved_at_40[0x40];
7197 };
7198
7199 struct mlx5_ifc_alloc_flow_counter_out_bits {
7200         u8         status[0x8];
7201         u8         reserved_at_8[0x18];
7202
7203         u8         syndrome[0x20];
7204
7205         u8         flow_counter_id[0x20];
7206
7207         u8         reserved_at_60[0x20];
7208 };
7209
7210 struct mlx5_ifc_alloc_flow_counter_in_bits {
7211         u8         opcode[0x10];
7212         u8         reserved_at_10[0x10];
7213
7214         u8         reserved_at_20[0x10];
7215         u8         op_mod[0x10];
7216
7217         u8         reserved_at_40[0x40];
7218 };
7219
7220 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7221         u8         status[0x8];
7222         u8         reserved_at_8[0x18];
7223
7224         u8         syndrome[0x20];
7225
7226         u8         reserved_at_40[0x40];
7227 };
7228
7229 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7230         u8         opcode[0x10];
7231         u8         reserved_at_10[0x10];
7232
7233         u8         reserved_at_20[0x10];
7234         u8         op_mod[0x10];
7235
7236         u8         reserved_at_40[0x20];
7237
7238         u8         reserved_at_60[0x10];
7239         u8         vxlan_udp_port[0x10];
7240 };
7241
7242 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7243         u8         status[0x8];
7244         u8         reserved_at_8[0x18];
7245
7246         u8         syndrome[0x20];
7247
7248         u8         reserved_at_40[0x40];
7249 };
7250
7251 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7252         u8         opcode[0x10];
7253         u8         reserved_at_10[0x10];
7254
7255         u8         reserved_at_20[0x10];
7256         u8         op_mod[0x10];
7257
7258         u8         reserved_at_40[0x10];
7259         u8         rate_limit_index[0x10];
7260
7261         u8         reserved_at_60[0x20];
7262
7263         u8         rate_limit[0x20];
7264
7265         u8         reserved_at_a0[0x160];
7266 };
7267
7268 struct mlx5_ifc_access_register_out_bits {
7269         u8         status[0x8];
7270         u8         reserved_at_8[0x18];
7271
7272         u8         syndrome[0x20];
7273
7274         u8         reserved_at_40[0x40];
7275
7276         u8         register_data[0][0x20];
7277 };
7278
7279 enum {
7280         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7281         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7282 };
7283
7284 struct mlx5_ifc_access_register_in_bits {
7285         u8         opcode[0x10];
7286         u8         reserved_at_10[0x10];
7287
7288         u8         reserved_at_20[0x10];
7289         u8         op_mod[0x10];
7290
7291         u8         reserved_at_40[0x10];
7292         u8         register_id[0x10];
7293
7294         u8         argument[0x20];
7295
7296         u8         register_data[0][0x20];
7297 };
7298
7299 struct mlx5_ifc_sltp_reg_bits {
7300         u8         status[0x4];
7301         u8         version[0x4];
7302         u8         local_port[0x8];
7303         u8         pnat[0x2];
7304         u8         reserved_at_12[0x2];
7305         u8         lane[0x4];
7306         u8         reserved_at_18[0x8];
7307
7308         u8         reserved_at_20[0x20];
7309
7310         u8         reserved_at_40[0x7];
7311         u8         polarity[0x1];
7312         u8         ob_tap0[0x8];
7313         u8         ob_tap1[0x8];
7314         u8         ob_tap2[0x8];
7315
7316         u8         reserved_at_60[0xc];
7317         u8         ob_preemp_mode[0x4];
7318         u8         ob_reg[0x8];
7319         u8         ob_bias[0x8];
7320
7321         u8         reserved_at_80[0x20];
7322 };
7323
7324 struct mlx5_ifc_slrg_reg_bits {
7325         u8         status[0x4];
7326         u8         version[0x4];
7327         u8         local_port[0x8];
7328         u8         pnat[0x2];
7329         u8         reserved_at_12[0x2];
7330         u8         lane[0x4];
7331         u8         reserved_at_18[0x8];
7332
7333         u8         time_to_link_up[0x10];
7334         u8         reserved_at_30[0xc];
7335         u8         grade_lane_speed[0x4];
7336
7337         u8         grade_version[0x8];
7338         u8         grade[0x18];
7339
7340         u8         reserved_at_60[0x4];
7341         u8         height_grade_type[0x4];
7342         u8         height_grade[0x18];
7343
7344         u8         height_dz[0x10];
7345         u8         height_dv[0x10];
7346
7347         u8         reserved_at_a0[0x10];
7348         u8         height_sigma[0x10];
7349
7350         u8         reserved_at_c0[0x20];
7351
7352         u8         reserved_at_e0[0x4];
7353         u8         phase_grade_type[0x4];
7354         u8         phase_grade[0x18];
7355
7356         u8         reserved_at_100[0x8];
7357         u8         phase_eo_pos[0x8];
7358         u8         reserved_at_110[0x8];
7359         u8         phase_eo_neg[0x8];
7360
7361         u8         ffe_set_tested[0x10];
7362         u8         test_errors_per_lane[0x10];
7363 };
7364
7365 struct mlx5_ifc_pvlc_reg_bits {
7366         u8         reserved_at_0[0x8];
7367         u8         local_port[0x8];
7368         u8         reserved_at_10[0x10];
7369
7370         u8         reserved_at_20[0x1c];
7371         u8         vl_hw_cap[0x4];
7372
7373         u8         reserved_at_40[0x1c];
7374         u8         vl_admin[0x4];
7375
7376         u8         reserved_at_60[0x1c];
7377         u8         vl_operational[0x4];
7378 };
7379
7380 struct mlx5_ifc_pude_reg_bits {
7381         u8         swid[0x8];
7382         u8         local_port[0x8];
7383         u8         reserved_at_10[0x4];
7384         u8         admin_status[0x4];
7385         u8         reserved_at_18[0x4];
7386         u8         oper_status[0x4];
7387
7388         u8         reserved_at_20[0x60];
7389 };
7390
7391 struct mlx5_ifc_ptys_reg_bits {
7392         u8         reserved_at_0[0x1];
7393         u8         an_disable_admin[0x1];
7394         u8         an_disable_cap[0x1];
7395         u8         reserved_at_3[0x5];
7396         u8         local_port[0x8];
7397         u8         reserved_at_10[0xd];
7398         u8         proto_mask[0x3];
7399
7400         u8         an_status[0x4];
7401         u8         reserved_at_24[0x3c];
7402
7403         u8         eth_proto_capability[0x20];
7404
7405         u8         ib_link_width_capability[0x10];
7406         u8         ib_proto_capability[0x10];
7407
7408         u8         reserved_at_a0[0x20];
7409
7410         u8         eth_proto_admin[0x20];
7411
7412         u8         ib_link_width_admin[0x10];
7413         u8         ib_proto_admin[0x10];
7414
7415         u8         reserved_at_100[0x20];
7416
7417         u8         eth_proto_oper[0x20];
7418
7419         u8         ib_link_width_oper[0x10];
7420         u8         ib_proto_oper[0x10];
7421
7422         u8         reserved_at_160[0x1c];
7423         u8         connector_type[0x4];
7424
7425         u8         eth_proto_lp_advertise[0x20];
7426
7427         u8         reserved_at_1a0[0x60];
7428 };
7429
7430 struct mlx5_ifc_mlcr_reg_bits {
7431         u8         reserved_at_0[0x8];
7432         u8         local_port[0x8];
7433         u8         reserved_at_10[0x20];
7434
7435         u8         beacon_duration[0x10];
7436         u8         reserved_at_40[0x10];
7437
7438         u8         beacon_remain[0x10];
7439 };
7440
7441 struct mlx5_ifc_ptas_reg_bits {
7442         u8         reserved_at_0[0x20];
7443
7444         u8         algorithm_options[0x10];
7445         u8         reserved_at_30[0x4];
7446         u8         repetitions_mode[0x4];
7447         u8         num_of_repetitions[0x8];
7448
7449         u8         grade_version[0x8];
7450         u8         height_grade_type[0x4];
7451         u8         phase_grade_type[0x4];
7452         u8         height_grade_weight[0x8];
7453         u8         phase_grade_weight[0x8];
7454
7455         u8         gisim_measure_bits[0x10];
7456         u8         adaptive_tap_measure_bits[0x10];
7457
7458         u8         ber_bath_high_error_threshold[0x10];
7459         u8         ber_bath_mid_error_threshold[0x10];
7460
7461         u8         ber_bath_low_error_threshold[0x10];
7462         u8         one_ratio_high_threshold[0x10];
7463
7464         u8         one_ratio_high_mid_threshold[0x10];
7465         u8         one_ratio_low_mid_threshold[0x10];
7466
7467         u8         one_ratio_low_threshold[0x10];
7468         u8         ndeo_error_threshold[0x10];
7469
7470         u8         mixer_offset_step_size[0x10];
7471         u8         reserved_at_110[0x8];
7472         u8         mix90_phase_for_voltage_bath[0x8];
7473
7474         u8         mixer_offset_start[0x10];
7475         u8         mixer_offset_end[0x10];
7476
7477         u8         reserved_at_140[0x15];
7478         u8         ber_test_time[0xb];
7479 };
7480
7481 struct mlx5_ifc_pspa_reg_bits {
7482         u8         swid[0x8];
7483         u8         local_port[0x8];
7484         u8         sub_port[0x8];
7485         u8         reserved_at_18[0x8];
7486
7487         u8         reserved_at_20[0x20];
7488 };
7489
7490 struct mlx5_ifc_pqdr_reg_bits {
7491         u8         reserved_at_0[0x8];
7492         u8         local_port[0x8];
7493         u8         reserved_at_10[0x5];
7494         u8         prio[0x3];
7495         u8         reserved_at_18[0x6];
7496         u8         mode[0x2];
7497
7498         u8         reserved_at_20[0x20];
7499
7500         u8         reserved_at_40[0x10];
7501         u8         min_threshold[0x10];
7502
7503         u8         reserved_at_60[0x10];
7504         u8         max_threshold[0x10];
7505
7506         u8         reserved_at_80[0x10];
7507         u8         mark_probability_denominator[0x10];
7508
7509         u8         reserved_at_a0[0x60];
7510 };
7511
7512 struct mlx5_ifc_ppsc_reg_bits {
7513         u8         reserved_at_0[0x8];
7514         u8         local_port[0x8];
7515         u8         reserved_at_10[0x10];
7516
7517         u8         reserved_at_20[0x60];
7518
7519         u8         reserved_at_80[0x1c];
7520         u8         wrps_admin[0x4];
7521
7522         u8         reserved_at_a0[0x1c];
7523         u8         wrps_status[0x4];
7524
7525         u8         reserved_at_c0[0x8];
7526         u8         up_threshold[0x8];
7527         u8         reserved_at_d0[0x8];
7528         u8         down_threshold[0x8];
7529
7530         u8         reserved_at_e0[0x20];
7531
7532         u8         reserved_at_100[0x1c];
7533         u8         srps_admin[0x4];
7534
7535         u8         reserved_at_120[0x1c];
7536         u8         srps_status[0x4];
7537
7538         u8         reserved_at_140[0x40];
7539 };
7540
7541 struct mlx5_ifc_pplr_reg_bits {
7542         u8         reserved_at_0[0x8];
7543         u8         local_port[0x8];
7544         u8         reserved_at_10[0x10];
7545
7546         u8         reserved_at_20[0x8];
7547         u8         lb_cap[0x8];
7548         u8         reserved_at_30[0x8];
7549         u8         lb_en[0x8];
7550 };
7551
7552 struct mlx5_ifc_pplm_reg_bits {
7553         u8         reserved_at_0[0x8];
7554         u8         local_port[0x8];
7555         u8         reserved_at_10[0x10];
7556
7557         u8         reserved_at_20[0x20];
7558
7559         u8         port_profile_mode[0x8];
7560         u8         static_port_profile[0x8];
7561         u8         active_port_profile[0x8];
7562         u8         reserved_at_58[0x8];
7563
7564         u8         retransmission_active[0x8];
7565         u8         fec_mode_active[0x18];
7566
7567         u8         reserved_at_80[0x20];
7568 };
7569
7570 struct mlx5_ifc_ppcnt_reg_bits {
7571         u8         swid[0x8];
7572         u8         local_port[0x8];
7573         u8         pnat[0x2];
7574         u8         reserved_at_12[0x8];
7575         u8         grp[0x6];
7576
7577         u8         clr[0x1];
7578         u8         reserved_at_21[0x1c];
7579         u8         prio_tc[0x3];
7580
7581         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7582 };
7583
7584 struct mlx5_ifc_mpcnt_reg_bits {
7585         u8         reserved_at_0[0x8];
7586         u8         pcie_index[0x8];
7587         u8         reserved_at_10[0xa];
7588         u8         grp[0x6];
7589
7590         u8         clr[0x1];
7591         u8         reserved_at_21[0x1f];
7592
7593         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7594 };
7595
7596 struct mlx5_ifc_ppad_reg_bits {
7597         u8         reserved_at_0[0x3];
7598         u8         single_mac[0x1];
7599         u8         reserved_at_4[0x4];
7600         u8         local_port[0x8];
7601         u8         mac_47_32[0x10];
7602
7603         u8         mac_31_0[0x20];
7604
7605         u8         reserved_at_40[0x40];
7606 };
7607
7608 struct mlx5_ifc_pmtu_reg_bits {
7609         u8         reserved_at_0[0x8];
7610         u8         local_port[0x8];
7611         u8         reserved_at_10[0x10];
7612
7613         u8         max_mtu[0x10];
7614         u8         reserved_at_30[0x10];
7615
7616         u8         admin_mtu[0x10];
7617         u8         reserved_at_50[0x10];
7618
7619         u8         oper_mtu[0x10];
7620         u8         reserved_at_70[0x10];
7621 };
7622
7623 struct mlx5_ifc_pmpr_reg_bits {
7624         u8         reserved_at_0[0x8];
7625         u8         module[0x8];
7626         u8         reserved_at_10[0x10];
7627
7628         u8         reserved_at_20[0x18];
7629         u8         attenuation_5g[0x8];
7630
7631         u8         reserved_at_40[0x18];
7632         u8         attenuation_7g[0x8];
7633
7634         u8         reserved_at_60[0x18];
7635         u8         attenuation_12g[0x8];
7636 };
7637
7638 struct mlx5_ifc_pmpe_reg_bits {
7639         u8         reserved_at_0[0x8];
7640         u8         module[0x8];
7641         u8         reserved_at_10[0xc];
7642         u8         module_status[0x4];
7643
7644         u8         reserved_at_20[0x60];
7645 };
7646
7647 struct mlx5_ifc_pmpc_reg_bits {
7648         u8         module_state_updated[32][0x8];
7649 };
7650
7651 struct mlx5_ifc_pmlpn_reg_bits {
7652         u8         reserved_at_0[0x4];
7653         u8         mlpn_status[0x4];
7654         u8         local_port[0x8];
7655         u8         reserved_at_10[0x10];
7656
7657         u8         e[0x1];
7658         u8         reserved_at_21[0x1f];
7659 };
7660
7661 struct mlx5_ifc_pmlp_reg_bits {
7662         u8         rxtx[0x1];
7663         u8         reserved_at_1[0x7];
7664         u8         local_port[0x8];
7665         u8         reserved_at_10[0x8];
7666         u8         width[0x8];
7667
7668         u8         lane0_module_mapping[0x20];
7669
7670         u8         lane1_module_mapping[0x20];
7671
7672         u8         lane2_module_mapping[0x20];
7673
7674         u8         lane3_module_mapping[0x20];
7675
7676         u8         reserved_at_a0[0x160];
7677 };
7678
7679 struct mlx5_ifc_pmaos_reg_bits {
7680         u8         reserved_at_0[0x8];
7681         u8         module[0x8];
7682         u8         reserved_at_10[0x4];
7683         u8         admin_status[0x4];
7684         u8         reserved_at_18[0x4];
7685         u8         oper_status[0x4];
7686
7687         u8         ase[0x1];
7688         u8         ee[0x1];
7689         u8         reserved_at_22[0x1c];
7690         u8         e[0x2];
7691
7692         u8         reserved_at_40[0x40];
7693 };
7694
7695 struct mlx5_ifc_plpc_reg_bits {
7696         u8         reserved_at_0[0x4];
7697         u8         profile_id[0xc];
7698         u8         reserved_at_10[0x4];
7699         u8         proto_mask[0x4];
7700         u8         reserved_at_18[0x8];
7701
7702         u8         reserved_at_20[0x10];
7703         u8         lane_speed[0x10];
7704
7705         u8         reserved_at_40[0x17];
7706         u8         lpbf[0x1];
7707         u8         fec_mode_policy[0x8];
7708
7709         u8         retransmission_capability[0x8];
7710         u8         fec_mode_capability[0x18];
7711
7712         u8         retransmission_support_admin[0x8];
7713         u8         fec_mode_support_admin[0x18];
7714
7715         u8         retransmission_request_admin[0x8];
7716         u8         fec_mode_request_admin[0x18];
7717
7718         u8         reserved_at_c0[0x80];
7719 };
7720
7721 struct mlx5_ifc_plib_reg_bits {
7722         u8         reserved_at_0[0x8];
7723         u8         local_port[0x8];
7724         u8         reserved_at_10[0x8];
7725         u8         ib_port[0x8];
7726
7727         u8         reserved_at_20[0x60];
7728 };
7729
7730 struct mlx5_ifc_plbf_reg_bits {
7731         u8         reserved_at_0[0x8];
7732         u8         local_port[0x8];
7733         u8         reserved_at_10[0xd];
7734         u8         lbf_mode[0x3];
7735
7736         u8         reserved_at_20[0x20];
7737 };
7738
7739 struct mlx5_ifc_pipg_reg_bits {
7740         u8         reserved_at_0[0x8];
7741         u8         local_port[0x8];
7742         u8         reserved_at_10[0x10];
7743
7744         u8         dic[0x1];
7745         u8         reserved_at_21[0x19];
7746         u8         ipg[0x4];
7747         u8         reserved_at_3e[0x2];
7748 };
7749
7750 struct mlx5_ifc_pifr_reg_bits {
7751         u8         reserved_at_0[0x8];
7752         u8         local_port[0x8];
7753         u8         reserved_at_10[0x10];
7754
7755         u8         reserved_at_20[0xe0];
7756
7757         u8         port_filter[8][0x20];
7758
7759         u8         port_filter_update_en[8][0x20];
7760 };
7761
7762 struct mlx5_ifc_pfcc_reg_bits {
7763         u8         reserved_at_0[0x8];
7764         u8         local_port[0x8];
7765         u8         reserved_at_10[0x10];
7766
7767         u8         ppan[0x4];
7768         u8         reserved_at_24[0x4];
7769         u8         prio_mask_tx[0x8];
7770         u8         reserved_at_30[0x8];
7771         u8         prio_mask_rx[0x8];
7772
7773         u8         pptx[0x1];
7774         u8         aptx[0x1];
7775         u8         reserved_at_42[0x6];
7776         u8         pfctx[0x8];
7777         u8         reserved_at_50[0x10];
7778
7779         u8         pprx[0x1];
7780         u8         aprx[0x1];
7781         u8         reserved_at_62[0x6];
7782         u8         pfcrx[0x8];
7783         u8         reserved_at_70[0x10];
7784
7785         u8         reserved_at_80[0x80];
7786 };
7787
7788 struct mlx5_ifc_pelc_reg_bits {
7789         u8         op[0x4];
7790         u8         reserved_at_4[0x4];
7791         u8         local_port[0x8];
7792         u8         reserved_at_10[0x10];
7793
7794         u8         op_admin[0x8];
7795         u8         op_capability[0x8];
7796         u8         op_request[0x8];
7797         u8         op_active[0x8];
7798
7799         u8         admin[0x40];
7800
7801         u8         capability[0x40];
7802
7803         u8         request[0x40];
7804
7805         u8         active[0x40];
7806
7807         u8         reserved_at_140[0x80];
7808 };
7809
7810 struct mlx5_ifc_peir_reg_bits {
7811         u8         reserved_at_0[0x8];
7812         u8         local_port[0x8];
7813         u8         reserved_at_10[0x10];
7814
7815         u8         reserved_at_20[0xc];
7816         u8         error_count[0x4];
7817         u8         reserved_at_30[0x10];
7818
7819         u8         reserved_at_40[0xc];
7820         u8         lane[0x4];
7821         u8         reserved_at_50[0x8];
7822         u8         error_type[0x8];
7823 };
7824
7825 struct mlx5_ifc_pcam_enhanced_features_bits {
7826         u8         reserved_at_0[0x7b];
7827
7828         u8         rx_buffer_fullness_counters[0x1];
7829         u8         ptys_connector_type[0x1];
7830         u8         reserved_at_7d[0x1];
7831         u8         ppcnt_discard_group[0x1];
7832         u8         ppcnt_statistical_group[0x1];
7833 };
7834
7835 struct mlx5_ifc_pcam_reg_bits {
7836         u8         reserved_at_0[0x8];
7837         u8         feature_group[0x8];
7838         u8         reserved_at_10[0x8];
7839         u8         access_reg_group[0x8];
7840
7841         u8         reserved_at_20[0x20];
7842
7843         union {
7844                 u8         reserved_at_0[0x80];
7845         } port_access_reg_cap_mask;
7846
7847         u8         reserved_at_c0[0x80];
7848
7849         union {
7850                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7851                 u8         reserved_at_0[0x80];
7852         } feature_cap_mask;
7853
7854         u8         reserved_at_1c0[0xc0];
7855 };
7856
7857 struct mlx5_ifc_mcam_enhanced_features_bits {
7858         u8         reserved_at_0[0x7b];
7859         u8         pcie_outbound_stalled[0x1];
7860         u8         tx_overflow_buffer_pkt[0x1];
7861         u8         mtpps_enh_out_per_adj[0x1];
7862         u8         mtpps_fs[0x1];
7863         u8         pcie_performance_group[0x1];
7864 };
7865
7866 struct mlx5_ifc_mcam_access_reg_bits {
7867         u8         reserved_at_0[0x1c];
7868         u8         mcda[0x1];
7869         u8         mcc[0x1];
7870         u8         mcqi[0x1];
7871         u8         reserved_at_1f[0x1];
7872
7873         u8         regs_95_to_64[0x20];
7874         u8         regs_63_to_32[0x20];
7875         u8         regs_31_to_0[0x20];
7876 };
7877
7878 struct mlx5_ifc_mcam_reg_bits {
7879         u8         reserved_at_0[0x8];
7880         u8         feature_group[0x8];
7881         u8         reserved_at_10[0x8];
7882         u8         access_reg_group[0x8];
7883
7884         u8         reserved_at_20[0x20];
7885
7886         union {
7887                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7888                 u8         reserved_at_0[0x80];
7889         } mng_access_reg_cap_mask;
7890
7891         u8         reserved_at_c0[0x80];
7892
7893         union {
7894                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7895                 u8         reserved_at_0[0x80];
7896         } mng_feature_cap_mask;
7897
7898         u8         reserved_at_1c0[0x80];
7899 };
7900
7901 struct mlx5_ifc_qcam_access_reg_cap_mask {
7902         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
7903         u8         qpdpm[0x1];
7904         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
7905         u8         qdpm[0x1];
7906         u8         qpts[0x1];
7907         u8         qcap[0x1];
7908         u8         qcam_access_reg_cap_mask_0[0x1];
7909 };
7910
7911 struct mlx5_ifc_qcam_qos_feature_cap_mask {
7912         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
7913         u8         qpts_trust_both[0x1];
7914 };
7915
7916 struct mlx5_ifc_qcam_reg_bits {
7917         u8         reserved_at_0[0x8];
7918         u8         feature_group[0x8];
7919         u8         reserved_at_10[0x8];
7920         u8         access_reg_group[0x8];
7921         u8         reserved_at_20[0x20];
7922
7923         union {
7924                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
7925                 u8  reserved_at_0[0x80];
7926         } qos_access_reg_cap_mask;
7927
7928         u8         reserved_at_c0[0x80];
7929
7930         union {
7931                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
7932                 u8  reserved_at_0[0x80];
7933         } qos_feature_cap_mask;
7934
7935         u8         reserved_at_1c0[0x80];
7936 };
7937
7938 struct mlx5_ifc_pcap_reg_bits {
7939         u8         reserved_at_0[0x8];
7940         u8         local_port[0x8];
7941         u8         reserved_at_10[0x10];
7942
7943         u8         port_capability_mask[4][0x20];
7944 };
7945
7946 struct mlx5_ifc_paos_reg_bits {
7947         u8         swid[0x8];
7948         u8         local_port[0x8];
7949         u8         reserved_at_10[0x4];
7950         u8         admin_status[0x4];
7951         u8         reserved_at_18[0x4];
7952         u8         oper_status[0x4];
7953
7954         u8         ase[0x1];
7955         u8         ee[0x1];
7956         u8         reserved_at_22[0x1c];
7957         u8         e[0x2];
7958
7959         u8         reserved_at_40[0x40];
7960 };
7961
7962 struct mlx5_ifc_pamp_reg_bits {
7963         u8         reserved_at_0[0x8];
7964         u8         opamp_group[0x8];
7965         u8         reserved_at_10[0xc];
7966         u8         opamp_group_type[0x4];
7967
7968         u8         start_index[0x10];
7969         u8         reserved_at_30[0x4];
7970         u8         num_of_indices[0xc];
7971
7972         u8         index_data[18][0x10];
7973 };
7974
7975 struct mlx5_ifc_pcmr_reg_bits {
7976         u8         reserved_at_0[0x8];
7977         u8         local_port[0x8];
7978         u8         reserved_at_10[0x2e];
7979         u8         fcs_cap[0x1];
7980         u8         reserved_at_3f[0x1f];
7981         u8         fcs_chk[0x1];
7982         u8         reserved_at_5f[0x1];
7983 };
7984
7985 struct mlx5_ifc_lane_2_module_mapping_bits {
7986         u8         reserved_at_0[0x6];
7987         u8         rx_lane[0x2];
7988         u8         reserved_at_8[0x6];
7989         u8         tx_lane[0x2];
7990         u8         reserved_at_10[0x8];
7991         u8         module[0x8];
7992 };
7993
7994 struct mlx5_ifc_bufferx_reg_bits {
7995         u8         reserved_at_0[0x6];
7996         u8         lossy[0x1];
7997         u8         epsb[0x1];
7998         u8         reserved_at_8[0xc];
7999         u8         size[0xc];
8000
8001         u8         xoff_threshold[0x10];
8002         u8         xon_threshold[0x10];
8003 };
8004
8005 struct mlx5_ifc_set_node_in_bits {
8006         u8         node_description[64][0x8];
8007 };
8008
8009 struct mlx5_ifc_register_power_settings_bits {
8010         u8         reserved_at_0[0x18];
8011         u8         power_settings_level[0x8];
8012
8013         u8         reserved_at_20[0x60];
8014 };
8015
8016 struct mlx5_ifc_register_host_endianness_bits {
8017         u8         he[0x1];
8018         u8         reserved_at_1[0x1f];
8019
8020         u8         reserved_at_20[0x60];
8021 };
8022
8023 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8024         u8         reserved_at_0[0x20];
8025
8026         u8         mkey[0x20];
8027
8028         u8         addressh_63_32[0x20];
8029
8030         u8         addressl_31_0[0x20];
8031 };
8032
8033 struct mlx5_ifc_ud_adrs_vector_bits {
8034         u8         dc_key[0x40];
8035
8036         u8         ext[0x1];
8037         u8         reserved_at_41[0x7];
8038         u8         destination_qp_dct[0x18];
8039
8040         u8         static_rate[0x4];
8041         u8         sl_eth_prio[0x4];
8042         u8         fl[0x1];
8043         u8         mlid[0x7];
8044         u8         rlid_udp_sport[0x10];
8045
8046         u8         reserved_at_80[0x20];
8047
8048         u8         rmac_47_16[0x20];
8049
8050         u8         rmac_15_0[0x10];
8051         u8         tclass[0x8];
8052         u8         hop_limit[0x8];
8053
8054         u8         reserved_at_e0[0x1];
8055         u8         grh[0x1];
8056         u8         reserved_at_e2[0x2];
8057         u8         src_addr_index[0x8];
8058         u8         flow_label[0x14];
8059
8060         u8         rgid_rip[16][0x8];
8061 };
8062
8063 struct mlx5_ifc_pages_req_event_bits {
8064         u8         reserved_at_0[0x10];
8065         u8         function_id[0x10];
8066
8067         u8         num_pages[0x20];
8068
8069         u8         reserved_at_40[0xa0];
8070 };
8071
8072 struct mlx5_ifc_eqe_bits {
8073         u8         reserved_at_0[0x8];
8074         u8         event_type[0x8];
8075         u8         reserved_at_10[0x8];
8076         u8         event_sub_type[0x8];
8077
8078         u8         reserved_at_20[0xe0];
8079
8080         union mlx5_ifc_event_auto_bits event_data;
8081
8082         u8         reserved_at_1e0[0x10];
8083         u8         signature[0x8];
8084         u8         reserved_at_1f8[0x7];
8085         u8         owner[0x1];
8086 };
8087
8088 enum {
8089         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8090 };
8091
8092 struct mlx5_ifc_cmd_queue_entry_bits {
8093         u8         type[0x8];
8094         u8         reserved_at_8[0x18];
8095
8096         u8         input_length[0x20];
8097
8098         u8         input_mailbox_pointer_63_32[0x20];
8099
8100         u8         input_mailbox_pointer_31_9[0x17];
8101         u8         reserved_at_77[0x9];
8102
8103         u8         command_input_inline_data[16][0x8];
8104
8105         u8         command_output_inline_data[16][0x8];
8106
8107         u8         output_mailbox_pointer_63_32[0x20];
8108
8109         u8         output_mailbox_pointer_31_9[0x17];
8110         u8         reserved_at_1b7[0x9];
8111
8112         u8         output_length[0x20];
8113
8114         u8         token[0x8];
8115         u8         signature[0x8];
8116         u8         reserved_at_1f0[0x8];
8117         u8         status[0x7];
8118         u8         ownership[0x1];
8119 };
8120
8121 struct mlx5_ifc_cmd_out_bits {
8122         u8         status[0x8];
8123         u8         reserved_at_8[0x18];
8124
8125         u8         syndrome[0x20];
8126
8127         u8         command_output[0x20];
8128 };
8129
8130 struct mlx5_ifc_cmd_in_bits {
8131         u8         opcode[0x10];
8132         u8         reserved_at_10[0x10];
8133
8134         u8         reserved_at_20[0x10];
8135         u8         op_mod[0x10];
8136
8137         u8         command[0][0x20];
8138 };
8139
8140 struct mlx5_ifc_cmd_if_box_bits {
8141         u8         mailbox_data[512][0x8];
8142
8143         u8         reserved_at_1000[0x180];
8144
8145         u8         next_pointer_63_32[0x20];
8146
8147         u8         next_pointer_31_10[0x16];
8148         u8         reserved_at_11b6[0xa];
8149
8150         u8         block_number[0x20];
8151
8152         u8         reserved_at_11e0[0x8];
8153         u8         token[0x8];
8154         u8         ctrl_signature[0x8];
8155         u8         signature[0x8];
8156 };
8157
8158 struct mlx5_ifc_mtt_bits {
8159         u8         ptag_63_32[0x20];
8160
8161         u8         ptag_31_8[0x18];
8162         u8         reserved_at_38[0x6];
8163         u8         wr_en[0x1];
8164         u8         rd_en[0x1];
8165 };
8166
8167 struct mlx5_ifc_query_wol_rol_out_bits {
8168         u8         status[0x8];
8169         u8         reserved_at_8[0x18];
8170
8171         u8         syndrome[0x20];
8172
8173         u8         reserved_at_40[0x10];
8174         u8         rol_mode[0x8];
8175         u8         wol_mode[0x8];
8176
8177         u8         reserved_at_60[0x20];
8178 };
8179
8180 struct mlx5_ifc_query_wol_rol_in_bits {
8181         u8         opcode[0x10];
8182         u8         reserved_at_10[0x10];
8183
8184         u8         reserved_at_20[0x10];
8185         u8         op_mod[0x10];
8186
8187         u8         reserved_at_40[0x40];
8188 };
8189
8190 struct mlx5_ifc_set_wol_rol_out_bits {
8191         u8         status[0x8];
8192         u8         reserved_at_8[0x18];
8193
8194         u8         syndrome[0x20];
8195
8196         u8         reserved_at_40[0x40];
8197 };
8198
8199 struct mlx5_ifc_set_wol_rol_in_bits {
8200         u8         opcode[0x10];
8201         u8         reserved_at_10[0x10];
8202
8203         u8         reserved_at_20[0x10];
8204         u8         op_mod[0x10];
8205
8206         u8         rol_mode_valid[0x1];
8207         u8         wol_mode_valid[0x1];
8208         u8         reserved_at_42[0xe];
8209         u8         rol_mode[0x8];
8210         u8         wol_mode[0x8];
8211
8212         u8         reserved_at_60[0x20];
8213 };
8214
8215 enum {
8216         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8217         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8218         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8219 };
8220
8221 enum {
8222         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8223         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8224         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8225 };
8226
8227 enum {
8228         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8229         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8230         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8231         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8232         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8233         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8234         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8235         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8236         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8237         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8238         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8239 };
8240
8241 struct mlx5_ifc_initial_seg_bits {
8242         u8         fw_rev_minor[0x10];
8243         u8         fw_rev_major[0x10];
8244
8245         u8         cmd_interface_rev[0x10];
8246         u8         fw_rev_subminor[0x10];
8247
8248         u8         reserved_at_40[0x40];
8249
8250         u8         cmdq_phy_addr_63_32[0x20];
8251
8252         u8         cmdq_phy_addr_31_12[0x14];
8253         u8         reserved_at_b4[0x2];
8254         u8         nic_interface[0x2];
8255         u8         log_cmdq_size[0x4];
8256         u8         log_cmdq_stride[0x4];
8257
8258         u8         command_doorbell_vector[0x20];
8259
8260         u8         reserved_at_e0[0xf00];
8261
8262         u8         initializing[0x1];
8263         u8         reserved_at_fe1[0x4];
8264         u8         nic_interface_supported[0x3];
8265         u8         reserved_at_fe8[0x18];
8266
8267         struct mlx5_ifc_health_buffer_bits health_buffer;
8268
8269         u8         no_dram_nic_offset[0x20];
8270
8271         u8         reserved_at_1220[0x6e40];
8272
8273         u8         reserved_at_8060[0x1f];
8274         u8         clear_int[0x1];
8275
8276         u8         health_syndrome[0x8];
8277         u8         health_counter[0x18];
8278
8279         u8         reserved_at_80a0[0x17fc0];
8280 };
8281
8282 struct mlx5_ifc_mtpps_reg_bits {
8283         u8         reserved_at_0[0xc];
8284         u8         cap_number_of_pps_pins[0x4];
8285         u8         reserved_at_10[0x4];
8286         u8         cap_max_num_of_pps_in_pins[0x4];
8287         u8         reserved_at_18[0x4];
8288         u8         cap_max_num_of_pps_out_pins[0x4];
8289
8290         u8         reserved_at_20[0x24];
8291         u8         cap_pin_3_mode[0x4];
8292         u8         reserved_at_48[0x4];
8293         u8         cap_pin_2_mode[0x4];
8294         u8         reserved_at_50[0x4];
8295         u8         cap_pin_1_mode[0x4];
8296         u8         reserved_at_58[0x4];
8297         u8         cap_pin_0_mode[0x4];
8298
8299         u8         reserved_at_60[0x4];
8300         u8         cap_pin_7_mode[0x4];
8301         u8         reserved_at_68[0x4];
8302         u8         cap_pin_6_mode[0x4];
8303         u8         reserved_at_70[0x4];
8304         u8         cap_pin_5_mode[0x4];
8305         u8         reserved_at_78[0x4];
8306         u8         cap_pin_4_mode[0x4];
8307
8308         u8         field_select[0x20];
8309         u8         reserved_at_a0[0x60];
8310
8311         u8         enable[0x1];
8312         u8         reserved_at_101[0xb];
8313         u8         pattern[0x4];
8314         u8         reserved_at_110[0x4];
8315         u8         pin_mode[0x4];
8316         u8         pin[0x8];
8317
8318         u8         reserved_at_120[0x20];
8319
8320         u8         time_stamp[0x40];
8321
8322         u8         out_pulse_duration[0x10];
8323         u8         out_periodic_adjustment[0x10];
8324         u8         enhanced_out_periodic_adjustment[0x20];
8325
8326         u8         reserved_at_1c0[0x20];
8327 };
8328
8329 struct mlx5_ifc_mtppse_reg_bits {
8330         u8         reserved_at_0[0x18];
8331         u8         pin[0x8];
8332         u8         event_arm[0x1];
8333         u8         reserved_at_21[0x1b];
8334         u8         event_generation_mode[0x4];
8335         u8         reserved_at_40[0x40];
8336 };
8337
8338 struct mlx5_ifc_mcqi_cap_bits {
8339         u8         supported_info_bitmask[0x20];
8340
8341         u8         component_size[0x20];
8342
8343         u8         max_component_size[0x20];
8344
8345         u8         log_mcda_word_size[0x4];
8346         u8         reserved_at_64[0xc];
8347         u8         mcda_max_write_size[0x10];
8348
8349         u8         rd_en[0x1];
8350         u8         reserved_at_81[0x1];
8351         u8         match_chip_id[0x1];
8352         u8         match_psid[0x1];
8353         u8         check_user_timestamp[0x1];
8354         u8         match_base_guid_mac[0x1];
8355         u8         reserved_at_86[0x1a];
8356 };
8357
8358 struct mlx5_ifc_mcqi_reg_bits {
8359         u8         read_pending_component[0x1];
8360         u8         reserved_at_1[0xf];
8361         u8         component_index[0x10];
8362
8363         u8         reserved_at_20[0x20];
8364
8365         u8         reserved_at_40[0x1b];
8366         u8         info_type[0x5];
8367
8368         u8         info_size[0x20];
8369
8370         u8         offset[0x20];
8371
8372         u8         reserved_at_a0[0x10];
8373         u8         data_size[0x10];
8374
8375         u8         data[0][0x20];
8376 };
8377
8378 struct mlx5_ifc_mcc_reg_bits {
8379         u8         reserved_at_0[0x4];
8380         u8         time_elapsed_since_last_cmd[0xc];
8381         u8         reserved_at_10[0x8];
8382         u8         instruction[0x8];
8383
8384         u8         reserved_at_20[0x10];
8385         u8         component_index[0x10];
8386
8387         u8         reserved_at_40[0x8];
8388         u8         update_handle[0x18];
8389
8390         u8         handle_owner_type[0x4];
8391         u8         handle_owner_host_id[0x4];
8392         u8         reserved_at_68[0x1];
8393         u8         control_progress[0x7];
8394         u8         error_code[0x8];
8395         u8         reserved_at_78[0x4];
8396         u8         control_state[0x4];
8397
8398         u8         component_size[0x20];
8399
8400         u8         reserved_at_a0[0x60];
8401 };
8402
8403 struct mlx5_ifc_mcda_reg_bits {
8404         u8         reserved_at_0[0x8];
8405         u8         update_handle[0x18];
8406
8407         u8         offset[0x20];
8408
8409         u8         reserved_at_40[0x10];
8410         u8         size[0x10];
8411
8412         u8         reserved_at_60[0x20];
8413
8414         u8         data[0][0x20];
8415 };
8416
8417 union mlx5_ifc_ports_control_registers_document_bits {
8418         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8419         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8420         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8421         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8422         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8423         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8424         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8425         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8426         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8427         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8428         struct mlx5_ifc_paos_reg_bits paos_reg;
8429         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8430         struct mlx5_ifc_peir_reg_bits peir_reg;
8431         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8432         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8433         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8434         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8435         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8436         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8437         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8438         struct mlx5_ifc_plib_reg_bits plib_reg;
8439         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8440         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8441         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8442         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8443         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8444         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8445         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8446         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8447         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8448         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8449         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8450         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8451         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8452         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8453         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8454         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8455         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8456         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8457         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8458         struct mlx5_ifc_pude_reg_bits pude_reg;
8459         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8460         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8461         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8462         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8463         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8464         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8465         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8466         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8467         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8468         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8469         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8470         u8         reserved_at_0[0x60e0];
8471 };
8472
8473 union mlx5_ifc_debug_enhancements_document_bits {
8474         struct mlx5_ifc_health_buffer_bits health_buffer;
8475         u8         reserved_at_0[0x200];
8476 };
8477
8478 union mlx5_ifc_uplink_pci_interface_document_bits {
8479         struct mlx5_ifc_initial_seg_bits initial_seg;
8480         u8         reserved_at_0[0x20060];
8481 };
8482
8483 struct mlx5_ifc_set_flow_table_root_out_bits {
8484         u8         status[0x8];
8485         u8         reserved_at_8[0x18];
8486
8487         u8         syndrome[0x20];
8488
8489         u8         reserved_at_40[0x40];
8490 };
8491
8492 struct mlx5_ifc_set_flow_table_root_in_bits {
8493         u8         opcode[0x10];
8494         u8         reserved_at_10[0x10];
8495
8496         u8         reserved_at_20[0x10];
8497         u8         op_mod[0x10];
8498
8499         u8         other_vport[0x1];
8500         u8         reserved_at_41[0xf];
8501         u8         vport_number[0x10];
8502
8503         u8         reserved_at_60[0x20];
8504
8505         u8         table_type[0x8];
8506         u8         reserved_at_88[0x18];
8507
8508         u8         reserved_at_a0[0x8];
8509         u8         table_id[0x18];
8510
8511         u8         reserved_at_c0[0x8];
8512         u8         underlay_qpn[0x18];
8513         u8         reserved_at_e0[0x120];
8514 };
8515
8516 enum {
8517         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8518         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8519 };
8520
8521 struct mlx5_ifc_modify_flow_table_out_bits {
8522         u8         status[0x8];
8523         u8         reserved_at_8[0x18];
8524
8525         u8         syndrome[0x20];
8526
8527         u8         reserved_at_40[0x40];
8528 };
8529
8530 struct mlx5_ifc_modify_flow_table_in_bits {
8531         u8         opcode[0x10];
8532         u8         reserved_at_10[0x10];
8533
8534         u8         reserved_at_20[0x10];
8535         u8         op_mod[0x10];
8536
8537         u8         other_vport[0x1];
8538         u8         reserved_at_41[0xf];
8539         u8         vport_number[0x10];
8540
8541         u8         reserved_at_60[0x10];
8542         u8         modify_field_select[0x10];
8543
8544         u8         table_type[0x8];
8545         u8         reserved_at_88[0x18];
8546
8547         u8         reserved_at_a0[0x8];
8548         u8         table_id[0x18];
8549
8550         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8551 };
8552
8553 struct mlx5_ifc_ets_tcn_config_reg_bits {
8554         u8         g[0x1];
8555         u8         b[0x1];
8556         u8         r[0x1];
8557         u8         reserved_at_3[0x9];
8558         u8         group[0x4];
8559         u8         reserved_at_10[0x9];
8560         u8         bw_allocation[0x7];
8561
8562         u8         reserved_at_20[0xc];
8563         u8         max_bw_units[0x4];
8564         u8         reserved_at_30[0x8];
8565         u8         max_bw_value[0x8];
8566 };
8567
8568 struct mlx5_ifc_ets_global_config_reg_bits {
8569         u8         reserved_at_0[0x2];
8570         u8         r[0x1];
8571         u8         reserved_at_3[0x1d];
8572
8573         u8         reserved_at_20[0xc];
8574         u8         max_bw_units[0x4];
8575         u8         reserved_at_30[0x8];
8576         u8         max_bw_value[0x8];
8577 };
8578
8579 struct mlx5_ifc_qetc_reg_bits {
8580         u8                                         reserved_at_0[0x8];
8581         u8                                         port_number[0x8];
8582         u8                                         reserved_at_10[0x30];
8583
8584         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8585         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8586 };
8587
8588 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8589         u8         e[0x1];
8590         u8         reserved_at_01[0x0b];
8591         u8         prio[0x04];
8592 };
8593
8594 struct mlx5_ifc_qpdpm_reg_bits {
8595         u8                                     reserved_at_0[0x8];
8596         u8                                     local_port[0x8];
8597         u8                                     reserved_at_10[0x10];
8598         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8599 };
8600
8601 struct mlx5_ifc_qpts_reg_bits {
8602         u8         reserved_at_0[0x8];
8603         u8         local_port[0x8];
8604         u8         reserved_at_10[0x2d];
8605         u8         trust_state[0x3];
8606 };
8607
8608 struct mlx5_ifc_qtct_reg_bits {
8609         u8         reserved_at_0[0x8];
8610         u8         port_number[0x8];
8611         u8         reserved_at_10[0xd];
8612         u8         prio[0x3];
8613
8614         u8         reserved_at_20[0x1d];
8615         u8         tclass[0x3];
8616 };
8617
8618 struct mlx5_ifc_mcia_reg_bits {
8619         u8         l[0x1];
8620         u8         reserved_at_1[0x7];
8621         u8         module[0x8];
8622         u8         reserved_at_10[0x8];
8623         u8         status[0x8];
8624
8625         u8         i2c_device_address[0x8];
8626         u8         page_number[0x8];
8627         u8         device_address[0x10];
8628
8629         u8         reserved_at_40[0x10];
8630         u8         size[0x10];
8631
8632         u8         reserved_at_60[0x20];
8633
8634         u8         dword_0[0x20];
8635         u8         dword_1[0x20];
8636         u8         dword_2[0x20];
8637         u8         dword_3[0x20];
8638         u8         dword_4[0x20];
8639         u8         dword_5[0x20];
8640         u8         dword_6[0x20];
8641         u8         dword_7[0x20];
8642         u8         dword_8[0x20];
8643         u8         dword_9[0x20];
8644         u8         dword_10[0x20];
8645         u8         dword_11[0x20];
8646 };
8647
8648 struct mlx5_ifc_dcbx_param_bits {
8649         u8         dcbx_cee_cap[0x1];
8650         u8         dcbx_ieee_cap[0x1];
8651         u8         dcbx_standby_cap[0x1];
8652         u8         reserved_at_0[0x5];
8653         u8         port_number[0x8];
8654         u8         reserved_at_10[0xa];
8655         u8         max_application_table_size[6];
8656         u8         reserved_at_20[0x15];
8657         u8         version_oper[0x3];
8658         u8         reserved_at_38[5];
8659         u8         version_admin[0x3];
8660         u8         willing_admin[0x1];
8661         u8         reserved_at_41[0x3];
8662         u8         pfc_cap_oper[0x4];
8663         u8         reserved_at_48[0x4];
8664         u8         pfc_cap_admin[0x4];
8665         u8         reserved_at_50[0x4];
8666         u8         num_of_tc_oper[0x4];
8667         u8         reserved_at_58[0x4];
8668         u8         num_of_tc_admin[0x4];
8669         u8         remote_willing[0x1];
8670         u8         reserved_at_61[3];
8671         u8         remote_pfc_cap[4];
8672         u8         reserved_at_68[0x14];
8673         u8         remote_num_of_tc[0x4];
8674         u8         reserved_at_80[0x18];
8675         u8         error[0x8];
8676         u8         reserved_at_a0[0x160];
8677 };
8678
8679 struct mlx5_ifc_lagc_bits {
8680         u8         reserved_at_0[0x1d];
8681         u8         lag_state[0x3];
8682
8683         u8         reserved_at_20[0x14];
8684         u8         tx_remap_affinity_2[0x4];
8685         u8         reserved_at_38[0x4];
8686         u8         tx_remap_affinity_1[0x4];
8687 };
8688
8689 struct mlx5_ifc_create_lag_out_bits {
8690         u8         status[0x8];
8691         u8         reserved_at_8[0x18];
8692
8693         u8         syndrome[0x20];
8694
8695         u8         reserved_at_40[0x40];
8696 };
8697
8698 struct mlx5_ifc_create_lag_in_bits {
8699         u8         opcode[0x10];
8700         u8         reserved_at_10[0x10];
8701
8702         u8         reserved_at_20[0x10];
8703         u8         op_mod[0x10];
8704
8705         struct mlx5_ifc_lagc_bits ctx;
8706 };
8707
8708 struct mlx5_ifc_modify_lag_out_bits {
8709         u8         status[0x8];
8710         u8         reserved_at_8[0x18];
8711
8712         u8         syndrome[0x20];
8713
8714         u8         reserved_at_40[0x40];
8715 };
8716
8717 struct mlx5_ifc_modify_lag_in_bits {
8718         u8         opcode[0x10];
8719         u8         reserved_at_10[0x10];
8720
8721         u8         reserved_at_20[0x10];
8722         u8         op_mod[0x10];
8723
8724         u8         reserved_at_40[0x20];
8725         u8         field_select[0x20];
8726
8727         struct mlx5_ifc_lagc_bits ctx;
8728 };
8729
8730 struct mlx5_ifc_query_lag_out_bits {
8731         u8         status[0x8];
8732         u8         reserved_at_8[0x18];
8733
8734         u8         syndrome[0x20];
8735
8736         u8         reserved_at_40[0x40];
8737
8738         struct mlx5_ifc_lagc_bits ctx;
8739 };
8740
8741 struct mlx5_ifc_query_lag_in_bits {
8742         u8         opcode[0x10];
8743         u8         reserved_at_10[0x10];
8744
8745         u8         reserved_at_20[0x10];
8746         u8         op_mod[0x10];
8747
8748         u8         reserved_at_40[0x40];
8749 };
8750
8751 struct mlx5_ifc_destroy_lag_out_bits {
8752         u8         status[0x8];
8753         u8         reserved_at_8[0x18];
8754
8755         u8         syndrome[0x20];
8756
8757         u8         reserved_at_40[0x40];
8758 };
8759
8760 struct mlx5_ifc_destroy_lag_in_bits {
8761         u8         opcode[0x10];
8762         u8         reserved_at_10[0x10];
8763
8764         u8         reserved_at_20[0x10];
8765         u8         op_mod[0x10];
8766
8767         u8         reserved_at_40[0x40];
8768 };
8769
8770 struct mlx5_ifc_create_vport_lag_out_bits {
8771         u8         status[0x8];
8772         u8         reserved_at_8[0x18];
8773
8774         u8         syndrome[0x20];
8775
8776         u8         reserved_at_40[0x40];
8777 };
8778
8779 struct mlx5_ifc_create_vport_lag_in_bits {
8780         u8         opcode[0x10];
8781         u8         reserved_at_10[0x10];
8782
8783         u8         reserved_at_20[0x10];
8784         u8         op_mod[0x10];
8785
8786         u8         reserved_at_40[0x40];
8787 };
8788
8789 struct mlx5_ifc_destroy_vport_lag_out_bits {
8790         u8         status[0x8];
8791         u8         reserved_at_8[0x18];
8792
8793         u8         syndrome[0x20];
8794
8795         u8         reserved_at_40[0x40];
8796 };
8797
8798 struct mlx5_ifc_destroy_vport_lag_in_bits {
8799         u8         opcode[0x10];
8800         u8         reserved_at_10[0x10];
8801
8802         u8         reserved_at_20[0x10];
8803         u8         op_mod[0x10];
8804
8805         u8         reserved_at_40[0x40];
8806 };
8807
8808 #endif /* MLX5_IFC_H */