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UBUNTU: Ubuntu-5.11.0-22.23
[mirror_ubuntu-hirsute-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 #include "mlx5_ifc_fpga.h"
36
37 enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
64 };
65
66 enum {
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
71 };
72
73 enum {
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
78 };
79
80 enum {
81 MLX5_SHARED_RESOURCE_UID = 0xffff,
82 };
83
84 enum {
85 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
86 };
87
88 enum {
89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
92 };
93
94 enum {
95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
97 MLX5_OBJ_TYPE_MKEY = 0xff01,
98 MLX5_OBJ_TYPE_QP = 0xff02,
99 MLX5_OBJ_TYPE_PSV = 0xff03,
100 MLX5_OBJ_TYPE_RMP = 0xff04,
101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
102 MLX5_OBJ_TYPE_RQ = 0xff06,
103 MLX5_OBJ_TYPE_SQ = 0xff07,
104 MLX5_OBJ_TYPE_TIR = 0xff08,
105 MLX5_OBJ_TYPE_TIS = 0xff09,
106 MLX5_OBJ_TYPE_DCT = 0xff0a,
107 MLX5_OBJ_TYPE_XRQ = 0xff0b,
108 MLX5_OBJ_TYPE_RQT = 0xff0e,
109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
110 MLX5_OBJ_TYPE_CQ = 0xff10,
111 };
112
113 enum {
114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
116 MLX5_CMD_OP_INIT_HCA = 0x102,
117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
118 MLX5_CMD_OP_ENABLE_HCA = 0x104,
119 MLX5_CMD_OP_DISABLE_HCA = 0x105,
120 MLX5_CMD_OP_QUERY_PAGES = 0x107,
121 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
122 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
123 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
124 MLX5_CMD_OP_SET_ISSI = 0x10b,
125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
127 MLX5_CMD_OP_ALLOC_SF = 0x113,
128 MLX5_CMD_OP_DEALLOC_SF = 0x114,
129 MLX5_CMD_OP_CREATE_MKEY = 0x200,
130 MLX5_CMD_OP_QUERY_MKEY = 0x201,
131 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
136 MLX5_CMD_OP_CREATE_EQ = 0x301,
137 MLX5_CMD_OP_DESTROY_EQ = 0x302,
138 MLX5_CMD_OP_QUERY_EQ = 0x303,
139 MLX5_CMD_OP_GEN_EQE = 0x304,
140 MLX5_CMD_OP_CREATE_CQ = 0x400,
141 MLX5_CMD_OP_DESTROY_CQ = 0x401,
142 MLX5_CMD_OP_QUERY_CQ = 0x402,
143 MLX5_CMD_OP_MODIFY_CQ = 0x403,
144 MLX5_CMD_OP_CREATE_QP = 0x500,
145 MLX5_CMD_OP_DESTROY_QP = 0x501,
146 MLX5_CMD_OP_RST2INIT_QP = 0x502,
147 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
148 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
149 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
151 MLX5_CMD_OP_2ERR_QP = 0x507,
152 MLX5_CMD_OP_2RST_QP = 0x50a,
153 MLX5_CMD_OP_QUERY_QP = 0x50b,
154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
156 MLX5_CMD_OP_CREATE_PSV = 0x600,
157 MLX5_CMD_OP_DESTROY_PSV = 0x601,
158 MLX5_CMD_OP_CREATE_SRQ = 0x700,
159 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
160 MLX5_CMD_OP_QUERY_SRQ = 0x702,
161 MLX5_CMD_OP_ARM_RQ = 0x703,
162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
166 MLX5_CMD_OP_CREATE_DCT = 0x710,
167 MLX5_CMD_OP_DESTROY_DCT = 0x711,
168 MLX5_CMD_OP_DRAIN_DCT = 0x712,
169 MLX5_CMD_OP_QUERY_DCT = 0x713,
170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
171 MLX5_CMD_OP_CREATE_XRQ = 0x717,
172 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
173 MLX5_CMD_OP_QUERY_XRQ = 0x719,
174 MLX5_CMD_OP_ARM_XRQ = 0x71a,
175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
208 MLX5_CMD_OP_ALLOC_PD = 0x800,
209 MLX5_CMD_OP_DEALLOC_PD = 0x801,
210 MLX5_CMD_OP_ALLOC_UAR = 0x802,
211 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
213 MLX5_CMD_OP_ACCESS_REG = 0x805,
214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
217 MLX5_CMD_OP_MAD_IFC = 0x50d,
218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
220 MLX5_CMD_OP_NOP = 0x80d,
221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
235 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
237 MLX5_CMD_OP_CREATE_LAG = 0x840,
238 MLX5_CMD_OP_MODIFY_LAG = 0x841,
239 MLX5_CMD_OP_QUERY_LAG = 0x842,
240 MLX5_CMD_OP_DESTROY_LAG = 0x843,
241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
243 MLX5_CMD_OP_CREATE_TIR = 0x900,
244 MLX5_CMD_OP_MODIFY_TIR = 0x901,
245 MLX5_CMD_OP_DESTROY_TIR = 0x902,
246 MLX5_CMD_OP_QUERY_TIR = 0x903,
247 MLX5_CMD_OP_CREATE_SQ = 0x904,
248 MLX5_CMD_OP_MODIFY_SQ = 0x905,
249 MLX5_CMD_OP_DESTROY_SQ = 0x906,
250 MLX5_CMD_OP_QUERY_SQ = 0x907,
251 MLX5_CMD_OP_CREATE_RQ = 0x908,
252 MLX5_CMD_OP_MODIFY_RQ = 0x909,
253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
254 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
255 MLX5_CMD_OP_QUERY_RQ = 0x90b,
256 MLX5_CMD_OP_CREATE_RMP = 0x90c,
257 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
258 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
259 MLX5_CMD_OP_QUERY_RMP = 0x90f,
260 MLX5_CMD_OP_CREATE_TIS = 0x912,
261 MLX5_CMD_OP_MODIFY_TIS = 0x913,
262 MLX5_CMD_OP_DESTROY_TIS = 0x914,
263 MLX5_CMD_OP_QUERY_TIS = 0x915,
264 MLX5_CMD_OP_CREATE_RQT = 0x916,
265 MLX5_CMD_OP_MODIFY_RQT = 0x917,
266 MLX5_CMD_OP_DESTROY_RQT = 0x918,
267 MLX5_CMD_OP_QUERY_RQT = 0x919,
268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
297 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
299 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
301 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
304 MLX5_CMD_OP_MAX
305 };
306
307 /* Valid range for general commands that don't work over an object */
308 enum {
309 MLX5_CMD_OP_GENERAL_START = 0xb00,
310 MLX5_CMD_OP_GENERAL_END = 0xd00,
311 };
312
313 struct mlx5_ifc_flow_table_fields_supported_bits {
314 u8 outer_dmac[0x1];
315 u8 outer_smac[0x1];
316 u8 outer_ether_type[0x1];
317 u8 outer_ip_version[0x1];
318 u8 outer_first_prio[0x1];
319 u8 outer_first_cfi[0x1];
320 u8 outer_first_vid[0x1];
321 u8 outer_ipv4_ttl[0x1];
322 u8 outer_second_prio[0x1];
323 u8 outer_second_cfi[0x1];
324 u8 outer_second_vid[0x1];
325 u8 reserved_at_b[0x1];
326 u8 outer_sip[0x1];
327 u8 outer_dip[0x1];
328 u8 outer_frag[0x1];
329 u8 outer_ip_protocol[0x1];
330 u8 outer_ip_ecn[0x1];
331 u8 outer_ip_dscp[0x1];
332 u8 outer_udp_sport[0x1];
333 u8 outer_udp_dport[0x1];
334 u8 outer_tcp_sport[0x1];
335 u8 outer_tcp_dport[0x1];
336 u8 outer_tcp_flags[0x1];
337 u8 outer_gre_protocol[0x1];
338 u8 outer_gre_key[0x1];
339 u8 outer_vxlan_vni[0x1];
340 u8 outer_geneve_vni[0x1];
341 u8 outer_geneve_oam[0x1];
342 u8 outer_geneve_protocol_type[0x1];
343 u8 outer_geneve_opt_len[0x1];
344 u8 reserved_at_1e[0x1];
345 u8 source_eswitch_port[0x1];
346
347 u8 inner_dmac[0x1];
348 u8 inner_smac[0x1];
349 u8 inner_ether_type[0x1];
350 u8 inner_ip_version[0x1];
351 u8 inner_first_prio[0x1];
352 u8 inner_first_cfi[0x1];
353 u8 inner_first_vid[0x1];
354 u8 reserved_at_27[0x1];
355 u8 inner_second_prio[0x1];
356 u8 inner_second_cfi[0x1];
357 u8 inner_second_vid[0x1];
358 u8 reserved_at_2b[0x1];
359 u8 inner_sip[0x1];
360 u8 inner_dip[0x1];
361 u8 inner_frag[0x1];
362 u8 inner_ip_protocol[0x1];
363 u8 inner_ip_ecn[0x1];
364 u8 inner_ip_dscp[0x1];
365 u8 inner_udp_sport[0x1];
366 u8 inner_udp_dport[0x1];
367 u8 inner_tcp_sport[0x1];
368 u8 inner_tcp_dport[0x1];
369 u8 inner_tcp_flags[0x1];
370 u8 reserved_at_37[0x9];
371
372 u8 geneve_tlv_option_0_data[0x1];
373 u8 reserved_at_41[0x4];
374 u8 outer_first_mpls_over_udp[0x4];
375 u8 outer_first_mpls_over_gre[0x4];
376 u8 inner_first_mpls[0x4];
377 u8 outer_first_mpls[0x4];
378 u8 reserved_at_55[0x2];
379 u8 outer_esp_spi[0x1];
380 u8 reserved_at_58[0x2];
381 u8 bth_dst_qp[0x1];
382 u8 reserved_at_5b[0x5];
383
384 u8 reserved_at_60[0x18];
385 u8 metadata_reg_c_7[0x1];
386 u8 metadata_reg_c_6[0x1];
387 u8 metadata_reg_c_5[0x1];
388 u8 metadata_reg_c_4[0x1];
389 u8 metadata_reg_c_3[0x1];
390 u8 metadata_reg_c_2[0x1];
391 u8 metadata_reg_c_1[0x1];
392 u8 metadata_reg_c_0[0x1];
393 };
394
395 struct mlx5_ifc_flow_table_prop_layout_bits {
396 u8 ft_support[0x1];
397 u8 reserved_at_1[0x1];
398 u8 flow_counter[0x1];
399 u8 flow_modify_en[0x1];
400 u8 modify_root[0x1];
401 u8 identified_miss_table_mode[0x1];
402 u8 flow_table_modify[0x1];
403 u8 reformat[0x1];
404 u8 decap[0x1];
405 u8 reserved_at_9[0x1];
406 u8 pop_vlan[0x1];
407 u8 push_vlan[0x1];
408 u8 reserved_at_c[0x1];
409 u8 pop_vlan_2[0x1];
410 u8 push_vlan_2[0x1];
411 u8 reformat_and_vlan_action[0x1];
412 u8 reserved_at_10[0x1];
413 u8 sw_owner[0x1];
414 u8 reformat_l3_tunnel_to_l2[0x1];
415 u8 reformat_l2_to_l3_tunnel[0x1];
416 u8 reformat_and_modify_action[0x1];
417 u8 ignore_flow_level[0x1];
418 u8 reserved_at_16[0x1];
419 u8 table_miss_action_domain[0x1];
420 u8 termination_table[0x1];
421 u8 reformat_and_fwd_to_table[0x1];
422 u8 reserved_at_1a[0x2];
423 u8 ipsec_encrypt[0x1];
424 u8 ipsec_decrypt[0x1];
425 u8 sw_owner_v2[0x1];
426 u8 reserved_at_1f[0x1];
427
428 u8 termination_table_raw_traffic[0x1];
429 u8 reserved_at_21[0x1];
430 u8 log_max_ft_size[0x6];
431 u8 log_max_modify_header_context[0x8];
432 u8 max_modify_header_actions[0x8];
433 u8 max_ft_level[0x8];
434
435 u8 reserved_at_40[0x20];
436
437 u8 reserved_at_60[0x18];
438 u8 log_max_ft_num[0x8];
439
440 u8 reserved_at_80[0x10];
441 u8 log_max_flow_counter[0x8];
442 u8 log_max_destination[0x8];
443
444 u8 reserved_at_a0[0x18];
445 u8 log_max_flow[0x8];
446
447 u8 reserved_at_c0[0x40];
448
449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
450
451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
452 };
453
454 struct mlx5_ifc_odp_per_transport_service_cap_bits {
455 u8 send[0x1];
456 u8 receive[0x1];
457 u8 write[0x1];
458 u8 read[0x1];
459 u8 atomic[0x1];
460 u8 srq_receive[0x1];
461 u8 reserved_at_6[0x1a];
462 };
463
464 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
465 u8 smac_47_16[0x20];
466
467 u8 smac_15_0[0x10];
468 u8 ethertype[0x10];
469
470 u8 dmac_47_16[0x20];
471
472 u8 dmac_15_0[0x10];
473 u8 first_prio[0x3];
474 u8 first_cfi[0x1];
475 u8 first_vid[0xc];
476
477 u8 ip_protocol[0x8];
478 u8 ip_dscp[0x6];
479 u8 ip_ecn[0x2];
480 u8 cvlan_tag[0x1];
481 u8 svlan_tag[0x1];
482 u8 frag[0x1];
483 u8 ip_version[0x4];
484 u8 tcp_flags[0x9];
485
486 u8 tcp_sport[0x10];
487 u8 tcp_dport[0x10];
488
489 u8 reserved_at_c0[0x18];
490 u8 ttl_hoplimit[0x8];
491
492 u8 udp_sport[0x10];
493 u8 udp_dport[0x10];
494
495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
496
497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
498 };
499
500 struct mlx5_ifc_nvgre_key_bits {
501 u8 hi[0x18];
502 u8 lo[0x8];
503 };
504
505 union mlx5_ifc_gre_key_bits {
506 struct mlx5_ifc_nvgre_key_bits nvgre;
507 u8 key[0x20];
508 };
509
510 struct mlx5_ifc_fte_match_set_misc_bits {
511 u8 gre_c_present[0x1];
512 u8 reserved_at_1[0x1];
513 u8 gre_k_present[0x1];
514 u8 gre_s_present[0x1];
515 u8 source_vhca_port[0x4];
516 u8 source_sqn[0x18];
517
518 u8 source_eswitch_owner_vhca_id[0x10];
519 u8 source_port[0x10];
520
521 u8 outer_second_prio[0x3];
522 u8 outer_second_cfi[0x1];
523 u8 outer_second_vid[0xc];
524 u8 inner_second_prio[0x3];
525 u8 inner_second_cfi[0x1];
526 u8 inner_second_vid[0xc];
527
528 u8 outer_second_cvlan_tag[0x1];
529 u8 inner_second_cvlan_tag[0x1];
530 u8 outer_second_svlan_tag[0x1];
531 u8 inner_second_svlan_tag[0x1];
532 u8 reserved_at_64[0xc];
533 u8 gre_protocol[0x10];
534
535 union mlx5_ifc_gre_key_bits gre_key;
536
537 u8 vxlan_vni[0x18];
538 u8 reserved_at_b8[0x8];
539
540 u8 geneve_vni[0x18];
541 u8 reserved_at_d8[0x7];
542 u8 geneve_oam[0x1];
543
544 u8 reserved_at_e0[0xc];
545 u8 outer_ipv6_flow_label[0x14];
546
547 u8 reserved_at_100[0xc];
548 u8 inner_ipv6_flow_label[0x14];
549
550 u8 reserved_at_120[0xa];
551 u8 geneve_opt_len[0x6];
552 u8 geneve_protocol_type[0x10];
553
554 u8 reserved_at_140[0x8];
555 u8 bth_dst_qp[0x18];
556 u8 reserved_at_160[0x20];
557 u8 outer_esp_spi[0x20];
558 u8 reserved_at_1a0[0x60];
559 };
560
561 struct mlx5_ifc_fte_match_mpls_bits {
562 u8 mpls_label[0x14];
563 u8 mpls_exp[0x3];
564 u8 mpls_s_bos[0x1];
565 u8 mpls_ttl[0x8];
566 };
567
568 struct mlx5_ifc_fte_match_set_misc2_bits {
569 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
570
571 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
572
573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
574
575 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
576
577 u8 metadata_reg_c_7[0x20];
578
579 u8 metadata_reg_c_6[0x20];
580
581 u8 metadata_reg_c_5[0x20];
582
583 u8 metadata_reg_c_4[0x20];
584
585 u8 metadata_reg_c_3[0x20];
586
587 u8 metadata_reg_c_2[0x20];
588
589 u8 metadata_reg_c_1[0x20];
590
591 u8 metadata_reg_c_0[0x20];
592
593 u8 metadata_reg_a[0x20];
594
595 u8 reserved_at_1a0[0x60];
596 };
597
598 struct mlx5_ifc_fte_match_set_misc3_bits {
599 u8 inner_tcp_seq_num[0x20];
600
601 u8 outer_tcp_seq_num[0x20];
602
603 u8 inner_tcp_ack_num[0x20];
604
605 u8 outer_tcp_ack_num[0x20];
606
607 u8 reserved_at_80[0x8];
608 u8 outer_vxlan_gpe_vni[0x18];
609
610 u8 outer_vxlan_gpe_next_protocol[0x8];
611 u8 outer_vxlan_gpe_flags[0x8];
612 u8 reserved_at_b0[0x10];
613
614 u8 icmp_header_data[0x20];
615
616 u8 icmpv6_header_data[0x20];
617
618 u8 icmp_type[0x8];
619 u8 icmp_code[0x8];
620 u8 icmpv6_type[0x8];
621 u8 icmpv6_code[0x8];
622
623 u8 geneve_tlv_option_0_data[0x20];
624
625 u8 reserved_at_140[0xc0];
626 };
627
628 struct mlx5_ifc_fte_match_set_misc4_bits {
629 u8 prog_sample_field_value_0[0x20];
630
631 u8 prog_sample_field_id_0[0x20];
632
633 u8 prog_sample_field_value_1[0x20];
634
635 u8 prog_sample_field_id_1[0x20];
636
637 u8 prog_sample_field_value_2[0x20];
638
639 u8 prog_sample_field_id_2[0x20];
640
641 u8 prog_sample_field_value_3[0x20];
642
643 u8 prog_sample_field_id_3[0x20];
644
645 u8 reserved_at_100[0x100];
646 };
647
648 struct mlx5_ifc_cmd_pas_bits {
649 u8 pa_h[0x20];
650
651 u8 pa_l[0x14];
652 u8 reserved_at_34[0xc];
653 };
654
655 struct mlx5_ifc_uint64_bits {
656 u8 hi[0x20];
657
658 u8 lo[0x20];
659 };
660
661 enum {
662 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
663 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
664 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
665 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
666 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
667 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
668 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
669 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
670 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
671 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
672 };
673
674 struct mlx5_ifc_ads_bits {
675 u8 fl[0x1];
676 u8 free_ar[0x1];
677 u8 reserved_at_2[0xe];
678 u8 pkey_index[0x10];
679
680 u8 reserved_at_20[0x8];
681 u8 grh[0x1];
682 u8 mlid[0x7];
683 u8 rlid[0x10];
684
685 u8 ack_timeout[0x5];
686 u8 reserved_at_45[0x3];
687 u8 src_addr_index[0x8];
688 u8 reserved_at_50[0x4];
689 u8 stat_rate[0x4];
690 u8 hop_limit[0x8];
691
692 u8 reserved_at_60[0x4];
693 u8 tclass[0x8];
694 u8 flow_label[0x14];
695
696 u8 rgid_rip[16][0x8];
697
698 u8 reserved_at_100[0x4];
699 u8 f_dscp[0x1];
700 u8 f_ecn[0x1];
701 u8 reserved_at_106[0x1];
702 u8 f_eth_prio[0x1];
703 u8 ecn[0x2];
704 u8 dscp[0x6];
705 u8 udp_sport[0x10];
706
707 u8 dei_cfi[0x1];
708 u8 eth_prio[0x3];
709 u8 sl[0x4];
710 u8 vhca_port_num[0x8];
711 u8 rmac_47_32[0x10];
712
713 u8 rmac_31_0[0x20];
714 };
715
716 struct mlx5_ifc_flow_table_nic_cap_bits {
717 u8 nic_rx_multi_path_tirs[0x1];
718 u8 nic_rx_multi_path_tirs_fts[0x1];
719 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
720 u8 reserved_at_3[0x4];
721 u8 sw_owner_reformat_supported[0x1];
722 u8 reserved_at_8[0x18];
723
724 u8 encap_general_header[0x1];
725 u8 reserved_at_21[0xa];
726 u8 log_max_packet_reformat_context[0x5];
727 u8 reserved_at_30[0x6];
728 u8 max_encap_header_size[0xa];
729 u8 reserved_at_40[0x1c0];
730
731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
732
733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
734
735 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
736
737 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
738
739 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
740
741 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
742
743 u8 reserved_at_e00[0x1200];
744
745 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
746
747 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
748
749 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
750
751 u8 reserved_at_20c0[0x5f40];
752 };
753
754 enum {
755 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
756 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
757 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
758 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
759 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
760 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
761 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
762 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
763 };
764
765 struct mlx5_ifc_flow_table_eswitch_cap_bits {
766 u8 fdb_to_vport_reg_c_id[0x8];
767 u8 reserved_at_8[0xd];
768 u8 fdb_modify_header_fwd_to_table[0x1];
769 u8 reserved_at_16[0x1];
770 u8 flow_source[0x1];
771 u8 reserved_at_18[0x2];
772 u8 multi_fdb_encap[0x1];
773 u8 egress_acl_forward_to_vport[0x1];
774 u8 fdb_multi_path_to_table[0x1];
775 u8 reserved_at_1d[0x3];
776
777 u8 reserved_at_20[0x1e0];
778
779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
780
781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
782
783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
784
785 u8 reserved_at_800[0x1000];
786
787 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
788
789 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
790
791 u8 sw_steering_uplink_icm_address_rx[0x40];
792
793 u8 sw_steering_uplink_icm_address_tx[0x40];
794
795 u8 reserved_at_1900[0x6700];
796 };
797
798 enum {
799 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
800 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
801 };
802
803 struct mlx5_ifc_e_switch_cap_bits {
804 u8 vport_svlan_strip[0x1];
805 u8 vport_cvlan_strip[0x1];
806 u8 vport_svlan_insert[0x1];
807 u8 vport_cvlan_insert_if_not_exist[0x1];
808 u8 vport_cvlan_insert_overwrite[0x1];
809 u8 reserved_at_5[0x3];
810 u8 esw_uplink_ingress_acl[0x1];
811 u8 reserved_at_9[0x10];
812 u8 esw_functions_changed[0x1];
813 u8 reserved_at_1a[0x1];
814 u8 ecpf_vport_exists[0x1];
815 u8 counter_eswitch_affinity[0x1];
816 u8 merged_eswitch[0x1];
817 u8 nic_vport_node_guid_modify[0x1];
818 u8 nic_vport_port_guid_modify[0x1];
819
820 u8 vxlan_encap_decap[0x1];
821 u8 nvgre_encap_decap[0x1];
822 u8 reserved_at_22[0x1];
823 u8 log_max_fdb_encap_uplink[0x5];
824 u8 reserved_at_21[0x3];
825 u8 log_max_packet_reformat_context[0x5];
826 u8 reserved_2b[0x6];
827 u8 max_encap_header_size[0xa];
828
829 u8 reserved_at_40[0xb];
830 u8 log_max_esw_sf[0x5];
831 u8 esw_sf_base_id[0x10];
832
833 u8 reserved_at_60[0x7a0];
834
835 };
836
837 struct mlx5_ifc_qos_cap_bits {
838 u8 packet_pacing[0x1];
839 u8 esw_scheduling[0x1];
840 u8 esw_bw_share[0x1];
841 u8 esw_rate_limit[0x1];
842 u8 reserved_at_4[0x1];
843 u8 packet_pacing_burst_bound[0x1];
844 u8 packet_pacing_typical_size[0x1];
845 u8 reserved_at_7[0x4];
846 u8 packet_pacing_uid[0x1];
847 u8 reserved_at_c[0x14];
848
849 u8 reserved_at_20[0x20];
850
851 u8 packet_pacing_max_rate[0x20];
852
853 u8 packet_pacing_min_rate[0x20];
854
855 u8 reserved_at_80[0x10];
856 u8 packet_pacing_rate_table_size[0x10];
857
858 u8 esw_element_type[0x10];
859 u8 esw_tsar_type[0x10];
860
861 u8 reserved_at_c0[0x10];
862 u8 max_qos_para_vport[0x10];
863
864 u8 max_tsar_bw_share[0x20];
865
866 u8 reserved_at_100[0x700];
867 };
868
869 struct mlx5_ifc_debug_cap_bits {
870 u8 core_dump_general[0x1];
871 u8 core_dump_qp[0x1];
872 u8 reserved_at_2[0x7];
873 u8 resource_dump[0x1];
874 u8 reserved_at_a[0x16];
875
876 u8 reserved_at_20[0x2];
877 u8 stall_detect[0x1];
878 u8 reserved_at_23[0x1d];
879
880 u8 reserved_at_40[0x7c0];
881 };
882
883 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
884 u8 csum_cap[0x1];
885 u8 vlan_cap[0x1];
886 u8 lro_cap[0x1];
887 u8 lro_psh_flag[0x1];
888 u8 lro_time_stamp[0x1];
889 u8 reserved_at_5[0x2];
890 u8 wqe_vlan_insert[0x1];
891 u8 self_lb_en_modifiable[0x1];
892 u8 reserved_at_9[0x2];
893 u8 max_lso_cap[0x5];
894 u8 multi_pkt_send_wqe[0x2];
895 u8 wqe_inline_mode[0x2];
896 u8 rss_ind_tbl_cap[0x4];
897 u8 reg_umr_sq[0x1];
898 u8 scatter_fcs[0x1];
899 u8 enhanced_multi_pkt_send_wqe[0x1];
900 u8 tunnel_lso_const_out_ip_id[0x1];
901 u8 reserved_at_1c[0x2];
902 u8 tunnel_stateless_gre[0x1];
903 u8 tunnel_stateless_vxlan[0x1];
904
905 u8 swp[0x1];
906 u8 swp_csum[0x1];
907 u8 swp_lso[0x1];
908 u8 cqe_checksum_full[0x1];
909 u8 tunnel_stateless_geneve_tx[0x1];
910 u8 tunnel_stateless_mpls_over_udp[0x1];
911 u8 tunnel_stateless_mpls_over_gre[0x1];
912 u8 tunnel_stateless_vxlan_gpe[0x1];
913 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
914 u8 tunnel_stateless_ip_over_ip[0x1];
915 u8 insert_trailer[0x1];
916 u8 reserved_at_2b[0x1];
917 u8 tunnel_stateless_ip_over_ip_rx[0x1];
918 u8 tunnel_stateless_ip_over_ip_tx[0x1];
919 u8 reserved_at_2e[0x2];
920 u8 max_vxlan_udp_ports[0x8];
921 u8 reserved_at_38[0x6];
922 u8 max_geneve_opt_len[0x1];
923 u8 tunnel_stateless_geneve_rx[0x1];
924
925 u8 reserved_at_40[0x10];
926 u8 lro_min_mss_size[0x10];
927
928 u8 reserved_at_60[0x120];
929
930 u8 lro_timer_supported_periods[4][0x20];
931
932 u8 reserved_at_200[0x600];
933 };
934
935 struct mlx5_ifc_roce_cap_bits {
936 u8 roce_apm[0x1];
937 u8 reserved_at_1[0x3];
938 u8 sw_r_roce_src_udp_port[0x1];
939 u8 reserved_at_5[0x1b];
940
941 u8 reserved_at_20[0x60];
942
943 u8 reserved_at_80[0xc];
944 u8 l3_type[0x4];
945 u8 reserved_at_90[0x8];
946 u8 roce_version[0x8];
947
948 u8 reserved_at_a0[0x10];
949 u8 r_roce_dest_udp_port[0x10];
950
951 u8 r_roce_max_src_udp_port[0x10];
952 u8 r_roce_min_src_udp_port[0x10];
953
954 u8 reserved_at_e0[0x10];
955 u8 roce_address_table_size[0x10];
956
957 u8 reserved_at_100[0x700];
958 };
959
960 struct mlx5_ifc_sync_steering_in_bits {
961 u8 opcode[0x10];
962 u8 uid[0x10];
963
964 u8 reserved_at_20[0x10];
965 u8 op_mod[0x10];
966
967 u8 reserved_at_40[0xc0];
968 };
969
970 struct mlx5_ifc_sync_steering_out_bits {
971 u8 status[0x8];
972 u8 reserved_at_8[0x18];
973
974 u8 syndrome[0x20];
975
976 u8 reserved_at_40[0x40];
977 };
978
979 struct mlx5_ifc_device_mem_cap_bits {
980 u8 memic[0x1];
981 u8 reserved_at_1[0x1f];
982
983 u8 reserved_at_20[0xb];
984 u8 log_min_memic_alloc_size[0x5];
985 u8 reserved_at_30[0x8];
986 u8 log_max_memic_addr_alignment[0x8];
987
988 u8 memic_bar_start_addr[0x40];
989
990 u8 memic_bar_size[0x20];
991
992 u8 max_memic_size[0x20];
993
994 u8 steering_sw_icm_start_address[0x40];
995
996 u8 reserved_at_100[0x8];
997 u8 log_header_modify_sw_icm_size[0x8];
998 u8 reserved_at_110[0x2];
999 u8 log_sw_icm_alloc_granularity[0x6];
1000 u8 log_steering_sw_icm_size[0x8];
1001
1002 u8 reserved_at_120[0x20];
1003
1004 u8 header_modify_sw_icm_start_address[0x40];
1005
1006 u8 reserved_at_180[0x680];
1007 };
1008
1009 struct mlx5_ifc_device_event_cap_bits {
1010 u8 user_affiliated_events[4][0x40];
1011
1012 u8 user_unaffiliated_events[4][0x40];
1013 };
1014
1015 struct mlx5_ifc_virtio_emulation_cap_bits {
1016 u8 desc_tunnel_offload_type[0x1];
1017 u8 eth_frame_offload_type[0x1];
1018 u8 virtio_version_1_0[0x1];
1019 u8 device_features_bits_mask[0xd];
1020 u8 event_mode[0x8];
1021 u8 virtio_queue_type[0x8];
1022
1023 u8 max_tunnel_desc[0x10];
1024 u8 reserved_at_30[0x3];
1025 u8 log_doorbell_stride[0x5];
1026 u8 reserved_at_38[0x3];
1027 u8 log_doorbell_bar_size[0x5];
1028
1029 u8 doorbell_bar_offset[0x40];
1030
1031 u8 max_emulated_devices[0x8];
1032 u8 max_num_virtio_queues[0x18];
1033
1034 u8 reserved_at_a0[0x60];
1035
1036 u8 umem_1_buffer_param_a[0x20];
1037
1038 u8 umem_1_buffer_param_b[0x20];
1039
1040 u8 umem_2_buffer_param_a[0x20];
1041
1042 u8 umem_2_buffer_param_b[0x20];
1043
1044 u8 umem_3_buffer_param_a[0x20];
1045
1046 u8 umem_3_buffer_param_b[0x20];
1047
1048 u8 reserved_at_1c0[0x640];
1049 };
1050
1051 enum {
1052 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1053 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1054 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1055 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1056 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1057 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1058 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1059 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1060 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1061 };
1062
1063 enum {
1064 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1065 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1066 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1067 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1068 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1069 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1070 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1071 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1072 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1073 };
1074
1075 struct mlx5_ifc_atomic_caps_bits {
1076 u8 reserved_at_0[0x40];
1077
1078 u8 atomic_req_8B_endianness_mode[0x2];
1079 u8 reserved_at_42[0x4];
1080 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1081
1082 u8 reserved_at_47[0x19];
1083
1084 u8 reserved_at_60[0x20];
1085
1086 u8 reserved_at_80[0x10];
1087 u8 atomic_operations[0x10];
1088
1089 u8 reserved_at_a0[0x10];
1090 u8 atomic_size_qp[0x10];
1091
1092 u8 reserved_at_c0[0x10];
1093 u8 atomic_size_dc[0x10];
1094
1095 u8 reserved_at_e0[0x720];
1096 };
1097
1098 struct mlx5_ifc_odp_cap_bits {
1099 u8 reserved_at_0[0x40];
1100
1101 u8 sig[0x1];
1102 u8 reserved_at_41[0x1f];
1103
1104 u8 reserved_at_60[0x20];
1105
1106 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1107
1108 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1109
1110 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1111
1112 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1113
1114 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1115
1116 u8 reserved_at_120[0x6E0];
1117 };
1118
1119 struct mlx5_ifc_calc_op {
1120 u8 reserved_at_0[0x10];
1121 u8 reserved_at_10[0x9];
1122 u8 op_swap_endianness[0x1];
1123 u8 op_min[0x1];
1124 u8 op_xor[0x1];
1125 u8 op_or[0x1];
1126 u8 op_and[0x1];
1127 u8 op_max[0x1];
1128 u8 op_add[0x1];
1129 };
1130
1131 struct mlx5_ifc_vector_calc_cap_bits {
1132 u8 calc_matrix[0x1];
1133 u8 reserved_at_1[0x1f];
1134 u8 reserved_at_20[0x8];
1135 u8 max_vec_count[0x8];
1136 u8 reserved_at_30[0xd];
1137 u8 max_chunk_size[0x3];
1138 struct mlx5_ifc_calc_op calc0;
1139 struct mlx5_ifc_calc_op calc1;
1140 struct mlx5_ifc_calc_op calc2;
1141 struct mlx5_ifc_calc_op calc3;
1142
1143 u8 reserved_at_c0[0x720];
1144 };
1145
1146 struct mlx5_ifc_tls_cap_bits {
1147 u8 tls_1_2_aes_gcm_128[0x1];
1148 u8 tls_1_3_aes_gcm_128[0x1];
1149 u8 tls_1_2_aes_gcm_256[0x1];
1150 u8 tls_1_3_aes_gcm_256[0x1];
1151 u8 reserved_at_4[0x1c];
1152
1153 u8 reserved_at_20[0x7e0];
1154 };
1155
1156 struct mlx5_ifc_ipsec_cap_bits {
1157 u8 ipsec_full_offload[0x1];
1158 u8 ipsec_crypto_offload[0x1];
1159 u8 ipsec_esn[0x1];
1160 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1161 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1162 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1163 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1164 u8 reserved_at_7[0x4];
1165 u8 log_max_ipsec_offload[0x5];
1166 u8 reserved_at_10[0x10];
1167
1168 u8 min_log_ipsec_full_replay_window[0x8];
1169 u8 max_log_ipsec_full_replay_window[0x8];
1170 u8 reserved_at_30[0x7d0];
1171 };
1172
1173 enum {
1174 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1175 MLX5_WQ_TYPE_CYCLIC = 0x1,
1176 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1177 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1178 };
1179
1180 enum {
1181 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1182 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1183 };
1184
1185 enum {
1186 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1187 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1188 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1189 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1190 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1191 };
1192
1193 enum {
1194 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1195 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1196 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1197 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1198 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1199 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1200 };
1201
1202 enum {
1203 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1204 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1205 };
1206
1207 enum {
1208 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1209 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1210 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1211 };
1212
1213 enum {
1214 MLX5_CAP_PORT_TYPE_IB = 0x0,
1215 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1216 };
1217
1218 enum {
1219 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1220 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1221 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1222 };
1223
1224 enum {
1225 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1226 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1227 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1228 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1229 };
1230
1231 enum {
1232 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1233 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1234 };
1235
1236 #define MLX5_FC_BULK_SIZE_FACTOR 128
1237
1238 enum mlx5_fc_bulk_alloc_bitmask {
1239 MLX5_FC_BULK_128 = (1 << 0),
1240 MLX5_FC_BULK_256 = (1 << 1),
1241 MLX5_FC_BULK_512 = (1 << 2),
1242 MLX5_FC_BULK_1024 = (1 << 3),
1243 MLX5_FC_BULK_2048 = (1 << 4),
1244 MLX5_FC_BULK_4096 = (1 << 5),
1245 MLX5_FC_BULK_8192 = (1 << 6),
1246 MLX5_FC_BULK_16384 = (1 << 7),
1247 };
1248
1249 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1250
1251 enum {
1252 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1253 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1254 };
1255
1256 struct mlx5_ifc_cmd_hca_cap_bits {
1257 u8 reserved_at_0[0x1f];
1258 u8 vhca_resource_manager[0x1];
1259
1260 u8 reserved_at_20[0x3];
1261 u8 event_on_vhca_state_teardown_request[0x1];
1262 u8 event_on_vhca_state_in_use[0x1];
1263 u8 event_on_vhca_state_active[0x1];
1264 u8 event_on_vhca_state_allocated[0x1];
1265 u8 event_on_vhca_state_invalid[0x1];
1266 u8 reserved_at_28[0x8];
1267 u8 vhca_id[0x10];
1268
1269 u8 reserved_at_40[0x40];
1270
1271 u8 log_max_srq_sz[0x8];
1272 u8 log_max_qp_sz[0x8];
1273 u8 event_cap[0x1];
1274 u8 reserved_at_91[0x7];
1275 u8 prio_tag_required[0x1];
1276 u8 reserved_at_99[0x2];
1277 u8 log_max_qp[0x5];
1278
1279 u8 reserved_at_a0[0x3];
1280 u8 ece_support[0x1];
1281 u8 reserved_at_a4[0x7];
1282 u8 log_max_srq[0x5];
1283 u8 reserved_at_b0[0x1];
1284 u8 uplink_follow[0x1];
1285 u8 ts_cqe_to_dest_cqn[0x1];
1286 u8 reserved_at_b3[0xd];
1287
1288 u8 max_sgl_for_optimized_performance[0x8];
1289 u8 log_max_cq_sz[0x8];
1290 u8 relaxed_ordering_write_umr[0x1];
1291 u8 relaxed_ordering_read_umr[0x1];
1292 u8 reserved_at_d2[0x7];
1293 u8 virtio_net_device_emualtion_manager[0x1];
1294 u8 virtio_blk_device_emualtion_manager[0x1];
1295 u8 log_max_cq[0x5];
1296
1297 u8 log_max_eq_sz[0x8];
1298 u8 relaxed_ordering_write[0x1];
1299 u8 relaxed_ordering_read[0x1];
1300 u8 log_max_mkey[0x6];
1301 u8 reserved_at_f0[0x8];
1302 u8 dump_fill_mkey[0x1];
1303 u8 reserved_at_f9[0x2];
1304 u8 fast_teardown[0x1];
1305 u8 log_max_eq[0x4];
1306
1307 u8 max_indirection[0x8];
1308 u8 fixed_buffer_size[0x1];
1309 u8 log_max_mrw_sz[0x7];
1310 u8 force_teardown[0x1];
1311 u8 reserved_at_111[0x1];
1312 u8 log_max_bsf_list_size[0x6];
1313 u8 umr_extended_translation_offset[0x1];
1314 u8 null_mkey[0x1];
1315 u8 log_max_klm_list_size[0x6];
1316
1317 u8 reserved_at_120[0xa];
1318 u8 log_max_ra_req_dc[0x6];
1319 u8 reserved_at_130[0xa];
1320 u8 log_max_ra_res_dc[0x6];
1321
1322 u8 reserved_at_140[0x6];
1323 u8 release_all_pages[0x1];
1324 u8 reserved_at_147[0x2];
1325 u8 roce_accl[0x1];
1326 u8 log_max_ra_req_qp[0x6];
1327 u8 reserved_at_150[0xa];
1328 u8 log_max_ra_res_qp[0x6];
1329
1330 u8 end_pad[0x1];
1331 u8 cc_query_allowed[0x1];
1332 u8 cc_modify_allowed[0x1];
1333 u8 start_pad[0x1];
1334 u8 cache_line_128byte[0x1];
1335 u8 reserved_at_165[0x4];
1336 u8 rts2rts_qp_counters_set_id[0x1];
1337 u8 reserved_at_16a[0x2];
1338 u8 vnic_env_int_rq_oob[0x1];
1339 u8 sbcam_reg[0x1];
1340 u8 reserved_at_16e[0x1];
1341 u8 qcam_reg[0x1];
1342 u8 gid_table_size[0x10];
1343
1344 u8 out_of_seq_cnt[0x1];
1345 u8 vport_counters[0x1];
1346 u8 retransmission_q_counters[0x1];
1347 u8 debug[0x1];
1348 u8 modify_rq_counter_set_id[0x1];
1349 u8 rq_delay_drop[0x1];
1350 u8 max_qp_cnt[0xa];
1351 u8 pkey_table_size[0x10];
1352
1353 u8 vport_group_manager[0x1];
1354 u8 vhca_group_manager[0x1];
1355 u8 ib_virt[0x1];
1356 u8 eth_virt[0x1];
1357 u8 vnic_env_queue_counters[0x1];
1358 u8 ets[0x1];
1359 u8 nic_flow_table[0x1];
1360 u8 eswitch_manager[0x1];
1361 u8 device_memory[0x1];
1362 u8 mcam_reg[0x1];
1363 u8 pcam_reg[0x1];
1364 u8 local_ca_ack_delay[0x5];
1365 u8 port_module_event[0x1];
1366 u8 enhanced_error_q_counters[0x1];
1367 u8 ports_check[0x1];
1368 u8 reserved_at_1b3[0x1];
1369 u8 disable_link_up[0x1];
1370 u8 beacon_led[0x1];
1371 u8 port_type[0x2];
1372 u8 num_ports[0x8];
1373
1374 u8 reserved_at_1c0[0x1];
1375 u8 pps[0x1];
1376 u8 pps_modify[0x1];
1377 u8 log_max_msg[0x5];
1378 u8 reserved_at_1c8[0x4];
1379 u8 max_tc[0x4];
1380 u8 temp_warn_event[0x1];
1381 u8 dcbx[0x1];
1382 u8 general_notification_event[0x1];
1383 u8 reserved_at_1d3[0x2];
1384 u8 fpga[0x1];
1385 u8 rol_s[0x1];
1386 u8 rol_g[0x1];
1387 u8 reserved_at_1d8[0x1];
1388 u8 wol_s[0x1];
1389 u8 wol_g[0x1];
1390 u8 wol_a[0x1];
1391 u8 wol_b[0x1];
1392 u8 wol_m[0x1];
1393 u8 wol_u[0x1];
1394 u8 wol_p[0x1];
1395
1396 u8 stat_rate_support[0x10];
1397 u8 reserved_at_1f0[0x1];
1398 u8 pci_sync_for_fw_update_event[0x1];
1399 u8 reserved_at_1f2[0x6];
1400 u8 init2_lag_tx_port_affinity[0x1];
1401 u8 reserved_at_1fa[0x3];
1402 u8 cqe_version[0x4];
1403
1404 u8 compact_address_vector[0x1];
1405 u8 striding_rq[0x1];
1406 u8 reserved_at_202[0x1];
1407 u8 ipoib_enhanced_offloads[0x1];
1408 u8 ipoib_basic_offloads[0x1];
1409 u8 reserved_at_205[0x1];
1410 u8 repeated_block_disabled[0x1];
1411 u8 umr_modify_entity_size_disabled[0x1];
1412 u8 umr_modify_atomic_disabled[0x1];
1413 u8 umr_indirect_mkey_disabled[0x1];
1414 u8 umr_fence[0x2];
1415 u8 dc_req_scat_data_cqe[0x1];
1416 u8 reserved_at_20d[0x2];
1417 u8 drain_sigerr[0x1];
1418 u8 cmdif_checksum[0x2];
1419 u8 sigerr_cqe[0x1];
1420 u8 reserved_at_213[0x1];
1421 u8 wq_signature[0x1];
1422 u8 sctr_data_cqe[0x1];
1423 u8 reserved_at_216[0x1];
1424 u8 sho[0x1];
1425 u8 tph[0x1];
1426 u8 rf[0x1];
1427 u8 dct[0x1];
1428 u8 qos[0x1];
1429 u8 eth_net_offloads[0x1];
1430 u8 roce[0x1];
1431 u8 atomic[0x1];
1432 u8 reserved_at_21f[0x1];
1433
1434 u8 cq_oi[0x1];
1435 u8 cq_resize[0x1];
1436 u8 cq_moderation[0x1];
1437 u8 reserved_at_223[0x3];
1438 u8 cq_eq_remap[0x1];
1439 u8 pg[0x1];
1440 u8 block_lb_mc[0x1];
1441 u8 reserved_at_229[0x1];
1442 u8 scqe_break_moderation[0x1];
1443 u8 cq_period_start_from_cqe[0x1];
1444 u8 cd[0x1];
1445 u8 reserved_at_22d[0x1];
1446 u8 apm[0x1];
1447 u8 vector_calc[0x1];
1448 u8 umr_ptr_rlky[0x1];
1449 u8 imaicl[0x1];
1450 u8 qp_packet_based[0x1];
1451 u8 reserved_at_233[0x3];
1452 u8 qkv[0x1];
1453 u8 pkv[0x1];
1454 u8 set_deth_sqpn[0x1];
1455 u8 reserved_at_239[0x3];
1456 u8 xrc[0x1];
1457 u8 ud[0x1];
1458 u8 uc[0x1];
1459 u8 rc[0x1];
1460
1461 u8 uar_4k[0x1];
1462 u8 reserved_at_241[0x9];
1463 u8 uar_sz[0x6];
1464 u8 reserved_at_250[0x8];
1465 u8 log_pg_sz[0x8];
1466
1467 u8 bf[0x1];
1468 u8 driver_version[0x1];
1469 u8 pad_tx_eth_packet[0x1];
1470 u8 reserved_at_263[0x3];
1471 u8 mkey_by_name[0x1];
1472 u8 reserved_at_267[0x4];
1473
1474 u8 log_bf_reg_size[0x5];
1475
1476 u8 reserved_at_270[0x6];
1477 u8 lag_dct[0x2];
1478 u8 lag_tx_port_affinity[0x1];
1479 u8 reserved_at_279[0x2];
1480 u8 lag_master[0x1];
1481 u8 num_lag_ports[0x4];
1482
1483 u8 reserved_at_280[0x10];
1484 u8 max_wqe_sz_sq[0x10];
1485
1486 u8 reserved_at_2a0[0x10];
1487 u8 max_wqe_sz_rq[0x10];
1488
1489 u8 max_flow_counter_31_16[0x10];
1490 u8 max_wqe_sz_sq_dc[0x10];
1491
1492 u8 reserved_at_2e0[0x7];
1493 u8 max_qp_mcg[0x19];
1494
1495 u8 reserved_at_300[0x10];
1496 u8 flow_counter_bulk_alloc[0x8];
1497 u8 log_max_mcg[0x8];
1498
1499 u8 reserved_at_320[0x3];
1500 u8 log_max_transport_domain[0x5];
1501 u8 reserved_at_328[0x3];
1502 u8 log_max_pd[0x5];
1503 u8 reserved_at_330[0xb];
1504 u8 log_max_xrcd[0x5];
1505
1506 u8 nic_receive_steering_discard[0x1];
1507 u8 receive_discard_vport_down[0x1];
1508 u8 transmit_discard_vport_down[0x1];
1509 u8 reserved_at_343[0x5];
1510 u8 log_max_flow_counter_bulk[0x8];
1511 u8 max_flow_counter_15_0[0x10];
1512
1513
1514 u8 reserved_at_360[0x3];
1515 u8 log_max_rq[0x5];
1516 u8 reserved_at_368[0x3];
1517 u8 log_max_sq[0x5];
1518 u8 reserved_at_370[0x3];
1519 u8 log_max_tir[0x5];
1520 u8 reserved_at_378[0x3];
1521 u8 log_max_tis[0x5];
1522
1523 u8 basic_cyclic_rcv_wqe[0x1];
1524 u8 reserved_at_381[0x2];
1525 u8 log_max_rmp[0x5];
1526 u8 reserved_at_388[0x3];
1527 u8 log_max_rqt[0x5];
1528 u8 reserved_at_390[0x3];
1529 u8 log_max_rqt_size[0x5];
1530 u8 reserved_at_398[0x3];
1531 u8 log_max_tis_per_sq[0x5];
1532
1533 u8 ext_stride_num_range[0x1];
1534 u8 reserved_at_3a1[0x2];
1535 u8 log_max_stride_sz_rq[0x5];
1536 u8 reserved_at_3a8[0x3];
1537 u8 log_min_stride_sz_rq[0x5];
1538 u8 reserved_at_3b0[0x3];
1539 u8 log_max_stride_sz_sq[0x5];
1540 u8 reserved_at_3b8[0x3];
1541 u8 log_min_stride_sz_sq[0x5];
1542
1543 u8 hairpin[0x1];
1544 u8 reserved_at_3c1[0x2];
1545 u8 log_max_hairpin_queues[0x5];
1546 u8 reserved_at_3c8[0x3];
1547 u8 log_max_hairpin_wq_data_sz[0x5];
1548 u8 reserved_at_3d0[0x3];
1549 u8 log_max_hairpin_num_packets[0x5];
1550 u8 reserved_at_3d8[0x3];
1551 u8 log_max_wq_sz[0x5];
1552
1553 u8 nic_vport_change_event[0x1];
1554 u8 disable_local_lb_uc[0x1];
1555 u8 disable_local_lb_mc[0x1];
1556 u8 log_min_hairpin_wq_data_sz[0x5];
1557 u8 reserved_at_3e8[0x2];
1558 u8 vhca_state[0x1];
1559 u8 log_max_vlan_list[0x5];
1560 u8 reserved_at_3f0[0x3];
1561 u8 log_max_current_mc_list[0x5];
1562 u8 reserved_at_3f8[0x3];
1563 u8 log_max_current_uc_list[0x5];
1564
1565 u8 general_obj_types[0x40];
1566
1567 u8 reserved_at_440[0x4];
1568 u8 steering_format_version[0x4];
1569 u8 create_qp_start_hint[0x18];
1570
1571 u8 reserved_at_460[0x3];
1572 u8 log_max_uctx[0x5];
1573 u8 reserved_at_468[0x2];
1574 u8 ipsec_offload[0x1];
1575 u8 log_max_umem[0x5];
1576 u8 max_num_eqs[0x10];
1577
1578 u8 reserved_at_480[0x1];
1579 u8 tls_tx[0x1];
1580 u8 tls_rx[0x1];
1581 u8 log_max_l2_table[0x5];
1582 u8 reserved_at_488[0x8];
1583 u8 log_uar_page_sz[0x10];
1584
1585 u8 reserved_at_4a0[0x20];
1586 u8 device_frequency_mhz[0x20];
1587 u8 device_frequency_khz[0x20];
1588
1589 u8 reserved_at_500[0x20];
1590 u8 num_of_uars_per_page[0x20];
1591
1592 u8 flex_parser_protocols[0x20];
1593
1594 u8 max_geneve_tlv_options[0x8];
1595 u8 reserved_at_568[0x3];
1596 u8 max_geneve_tlv_option_data_len[0x5];
1597 u8 reserved_at_570[0x10];
1598
1599 u8 reserved_at_580[0x33];
1600 u8 log_max_dek[0x5];
1601 u8 reserved_at_5b8[0x4];
1602 u8 mini_cqe_resp_stride_index[0x1];
1603 u8 cqe_128_always[0x1];
1604 u8 cqe_compression_128[0x1];
1605 u8 cqe_compression[0x1];
1606
1607 u8 cqe_compression_timeout[0x10];
1608 u8 cqe_compression_max_num[0x10];
1609
1610 u8 reserved_at_5e0[0x10];
1611 u8 tag_matching[0x1];
1612 u8 rndv_offload_rc[0x1];
1613 u8 rndv_offload_dc[0x1];
1614 u8 log_tag_matching_list_sz[0x5];
1615 u8 reserved_at_5f8[0x3];
1616 u8 log_max_xrq[0x5];
1617
1618 u8 affiliate_nic_vport_criteria[0x8];
1619 u8 native_port_num[0x8];
1620 u8 num_vhca_ports[0x8];
1621 u8 reserved_at_618[0x6];
1622 u8 sw_owner_id[0x1];
1623 u8 reserved_at_61f[0x1];
1624
1625 u8 max_num_of_monitor_counters[0x10];
1626 u8 num_ppcnt_monitor_counters[0x10];
1627
1628 u8 max_num_sf[0x10];
1629 u8 num_q_monitor_counters[0x10];
1630
1631 u8 reserved_at_660[0x20];
1632
1633 u8 sf[0x1];
1634 u8 sf_set_partition[0x1];
1635 u8 reserved_at_682[0x1];
1636 u8 log_max_sf[0x5];
1637 u8 reserved_at_688[0x8];
1638 u8 log_min_sf_size[0x8];
1639 u8 max_num_sf_partitions[0x8];
1640
1641 u8 uctx_cap[0x20];
1642
1643 u8 reserved_at_6c0[0x4];
1644 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1645 u8 flex_parser_id_icmp_dw1[0x4];
1646 u8 flex_parser_id_icmp_dw0[0x4];
1647 u8 flex_parser_id_icmpv6_dw1[0x4];
1648 u8 flex_parser_id_icmpv6_dw0[0x4];
1649 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1650 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1651
1652 u8 reserved_at_6e0[0x10];
1653 u8 sf_base_id[0x10];
1654
1655 u8 reserved_at_700[0x80];
1656 u8 vhca_tunnel_commands[0x40];
1657 u8 reserved_at_7c0[0x40];
1658 };
1659
1660 enum mlx5_flow_destination_type {
1661 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1662 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1663 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1664 MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1665
1666 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1667 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1668 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1669 };
1670
1671 enum mlx5_flow_table_miss_action {
1672 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1673 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1674 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1675 };
1676
1677 struct mlx5_ifc_dest_format_struct_bits {
1678 u8 destination_type[0x8];
1679 u8 destination_id[0x18];
1680
1681 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1682 u8 packet_reformat[0x1];
1683 u8 reserved_at_22[0xe];
1684 u8 destination_eswitch_owner_vhca_id[0x10];
1685 };
1686
1687 struct mlx5_ifc_flow_counter_list_bits {
1688 u8 flow_counter_id[0x20];
1689
1690 u8 reserved_at_20[0x20];
1691 };
1692
1693 struct mlx5_ifc_extended_dest_format_bits {
1694 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1695
1696 u8 packet_reformat_id[0x20];
1697
1698 u8 reserved_at_60[0x20];
1699 };
1700
1701 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1702 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1703 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1704 };
1705
1706 struct mlx5_ifc_fte_match_param_bits {
1707 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1708
1709 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1710
1711 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1712
1713 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1714
1715 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1716
1717 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1718
1719 u8 reserved_at_c00[0x400];
1720 };
1721
1722 enum {
1723 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1724 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1725 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1726 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1727 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1728 };
1729
1730 struct mlx5_ifc_rx_hash_field_select_bits {
1731 u8 l3_prot_type[0x1];
1732 u8 l4_prot_type[0x1];
1733 u8 selected_fields[0x1e];
1734 };
1735
1736 enum {
1737 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1738 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1739 };
1740
1741 enum {
1742 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1743 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1744 };
1745
1746 struct mlx5_ifc_wq_bits {
1747 u8 wq_type[0x4];
1748 u8 wq_signature[0x1];
1749 u8 end_padding_mode[0x2];
1750 u8 cd_slave[0x1];
1751 u8 reserved_at_8[0x18];
1752
1753 u8 hds_skip_first_sge[0x1];
1754 u8 log2_hds_buf_size[0x3];
1755 u8 reserved_at_24[0x7];
1756 u8 page_offset[0x5];
1757 u8 lwm[0x10];
1758
1759 u8 reserved_at_40[0x8];
1760 u8 pd[0x18];
1761
1762 u8 reserved_at_60[0x8];
1763 u8 uar_page[0x18];
1764
1765 u8 dbr_addr[0x40];
1766
1767 u8 hw_counter[0x20];
1768
1769 u8 sw_counter[0x20];
1770
1771 u8 reserved_at_100[0xc];
1772 u8 log_wq_stride[0x4];
1773 u8 reserved_at_110[0x3];
1774 u8 log_wq_pg_sz[0x5];
1775 u8 reserved_at_118[0x3];
1776 u8 log_wq_sz[0x5];
1777
1778 u8 dbr_umem_valid[0x1];
1779 u8 wq_umem_valid[0x1];
1780 u8 reserved_at_122[0x1];
1781 u8 log_hairpin_num_packets[0x5];
1782 u8 reserved_at_128[0x3];
1783 u8 log_hairpin_data_sz[0x5];
1784
1785 u8 reserved_at_130[0x4];
1786 u8 log_wqe_num_of_strides[0x4];
1787 u8 two_byte_shift_en[0x1];
1788 u8 reserved_at_139[0x4];
1789 u8 log_wqe_stride_size[0x3];
1790
1791 u8 reserved_at_140[0x4c0];
1792
1793 struct mlx5_ifc_cmd_pas_bits pas[];
1794 };
1795
1796 struct mlx5_ifc_rq_num_bits {
1797 u8 reserved_at_0[0x8];
1798 u8 rq_num[0x18];
1799 };
1800
1801 struct mlx5_ifc_mac_address_layout_bits {
1802 u8 reserved_at_0[0x10];
1803 u8 mac_addr_47_32[0x10];
1804
1805 u8 mac_addr_31_0[0x20];
1806 };
1807
1808 struct mlx5_ifc_vlan_layout_bits {
1809 u8 reserved_at_0[0x14];
1810 u8 vlan[0x0c];
1811
1812 u8 reserved_at_20[0x20];
1813 };
1814
1815 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1816 u8 reserved_at_0[0xa0];
1817
1818 u8 min_time_between_cnps[0x20];
1819
1820 u8 reserved_at_c0[0x12];
1821 u8 cnp_dscp[0x6];
1822 u8 reserved_at_d8[0x4];
1823 u8 cnp_prio_mode[0x1];
1824 u8 cnp_802p_prio[0x3];
1825
1826 u8 reserved_at_e0[0x720];
1827 };
1828
1829 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1830 u8 reserved_at_0[0x60];
1831
1832 u8 reserved_at_60[0x4];
1833 u8 clamp_tgt_rate[0x1];
1834 u8 reserved_at_65[0x3];
1835 u8 clamp_tgt_rate_after_time_inc[0x1];
1836 u8 reserved_at_69[0x17];
1837
1838 u8 reserved_at_80[0x20];
1839
1840 u8 rpg_time_reset[0x20];
1841
1842 u8 rpg_byte_reset[0x20];
1843
1844 u8 rpg_threshold[0x20];
1845
1846 u8 rpg_max_rate[0x20];
1847
1848 u8 rpg_ai_rate[0x20];
1849
1850 u8 rpg_hai_rate[0x20];
1851
1852 u8 rpg_gd[0x20];
1853
1854 u8 rpg_min_dec_fac[0x20];
1855
1856 u8 rpg_min_rate[0x20];
1857
1858 u8 reserved_at_1c0[0xe0];
1859
1860 u8 rate_to_set_on_first_cnp[0x20];
1861
1862 u8 dce_tcp_g[0x20];
1863
1864 u8 dce_tcp_rtt[0x20];
1865
1866 u8 rate_reduce_monitor_period[0x20];
1867
1868 u8 reserved_at_320[0x20];
1869
1870 u8 initial_alpha_value[0x20];
1871
1872 u8 reserved_at_360[0x4a0];
1873 };
1874
1875 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1876 u8 reserved_at_0[0x80];
1877
1878 u8 rppp_max_rps[0x20];
1879
1880 u8 rpg_time_reset[0x20];
1881
1882 u8 rpg_byte_reset[0x20];
1883
1884 u8 rpg_threshold[0x20];
1885
1886 u8 rpg_max_rate[0x20];
1887
1888 u8 rpg_ai_rate[0x20];
1889
1890 u8 rpg_hai_rate[0x20];
1891
1892 u8 rpg_gd[0x20];
1893
1894 u8 rpg_min_dec_fac[0x20];
1895
1896 u8 rpg_min_rate[0x20];
1897
1898 u8 reserved_at_1c0[0x640];
1899 };
1900
1901 enum {
1902 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1903 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1904 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1905 };
1906
1907 struct mlx5_ifc_resize_field_select_bits {
1908 u8 resize_field_select[0x20];
1909 };
1910
1911 struct mlx5_ifc_resource_dump_bits {
1912 u8 more_dump[0x1];
1913 u8 inline_dump[0x1];
1914 u8 reserved_at_2[0xa];
1915 u8 seq_num[0x4];
1916 u8 segment_type[0x10];
1917
1918 u8 reserved_at_20[0x10];
1919 u8 vhca_id[0x10];
1920
1921 u8 index1[0x20];
1922
1923 u8 index2[0x20];
1924
1925 u8 num_of_obj1[0x10];
1926 u8 num_of_obj2[0x10];
1927
1928 u8 reserved_at_a0[0x20];
1929
1930 u8 device_opaque[0x40];
1931
1932 u8 mkey[0x20];
1933
1934 u8 size[0x20];
1935
1936 u8 address[0x40];
1937
1938 u8 inline_data[52][0x20];
1939 };
1940
1941 struct mlx5_ifc_resource_dump_menu_record_bits {
1942 u8 reserved_at_0[0x4];
1943 u8 num_of_obj2_supports_active[0x1];
1944 u8 num_of_obj2_supports_all[0x1];
1945 u8 must_have_num_of_obj2[0x1];
1946 u8 support_num_of_obj2[0x1];
1947 u8 num_of_obj1_supports_active[0x1];
1948 u8 num_of_obj1_supports_all[0x1];
1949 u8 must_have_num_of_obj1[0x1];
1950 u8 support_num_of_obj1[0x1];
1951 u8 must_have_index2[0x1];
1952 u8 support_index2[0x1];
1953 u8 must_have_index1[0x1];
1954 u8 support_index1[0x1];
1955 u8 segment_type[0x10];
1956
1957 u8 segment_name[4][0x20];
1958
1959 u8 index1_name[4][0x20];
1960
1961 u8 index2_name[4][0x20];
1962 };
1963
1964 struct mlx5_ifc_resource_dump_segment_header_bits {
1965 u8 length_dw[0x10];
1966 u8 segment_type[0x10];
1967 };
1968
1969 struct mlx5_ifc_resource_dump_command_segment_bits {
1970 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1971
1972 u8 segment_called[0x10];
1973 u8 vhca_id[0x10];
1974
1975 u8 index1[0x20];
1976
1977 u8 index2[0x20];
1978
1979 u8 num_of_obj1[0x10];
1980 u8 num_of_obj2[0x10];
1981 };
1982
1983 struct mlx5_ifc_resource_dump_error_segment_bits {
1984 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1985
1986 u8 reserved_at_20[0x10];
1987 u8 syndrome_id[0x10];
1988
1989 u8 reserved_at_40[0x40];
1990
1991 u8 error[8][0x20];
1992 };
1993
1994 struct mlx5_ifc_resource_dump_info_segment_bits {
1995 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1996
1997 u8 reserved_at_20[0x18];
1998 u8 dump_version[0x8];
1999
2000 u8 hw_version[0x20];
2001
2002 u8 fw_version[0x20];
2003 };
2004
2005 struct mlx5_ifc_resource_dump_menu_segment_bits {
2006 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2007
2008 u8 reserved_at_20[0x10];
2009 u8 num_of_records[0x10];
2010
2011 struct mlx5_ifc_resource_dump_menu_record_bits record[];
2012 };
2013
2014 struct mlx5_ifc_resource_dump_resource_segment_bits {
2015 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2016
2017 u8 reserved_at_20[0x20];
2018
2019 u8 index1[0x20];
2020
2021 u8 index2[0x20];
2022
2023 u8 payload[][0x20];
2024 };
2025
2026 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2027 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2028 };
2029
2030 struct mlx5_ifc_menu_resource_dump_response_bits {
2031 struct mlx5_ifc_resource_dump_info_segment_bits info;
2032 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2033 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2034 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2035 };
2036
2037 enum {
2038 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2039 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2040 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2041 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2042 };
2043
2044 struct mlx5_ifc_modify_field_select_bits {
2045 u8 modify_field_select[0x20];
2046 };
2047
2048 struct mlx5_ifc_field_select_r_roce_np_bits {
2049 u8 field_select_r_roce_np[0x20];
2050 };
2051
2052 struct mlx5_ifc_field_select_r_roce_rp_bits {
2053 u8 field_select_r_roce_rp[0x20];
2054 };
2055
2056 enum {
2057 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2058 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2059 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2060 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2061 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2062 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2063 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2064 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2065 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2066 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2067 };
2068
2069 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2070 u8 field_select_8021qaurp[0x20];
2071 };
2072
2073 struct mlx5_ifc_phys_layer_cntrs_bits {
2074 u8 time_since_last_clear_high[0x20];
2075
2076 u8 time_since_last_clear_low[0x20];
2077
2078 u8 symbol_errors_high[0x20];
2079
2080 u8 symbol_errors_low[0x20];
2081
2082 u8 sync_headers_errors_high[0x20];
2083
2084 u8 sync_headers_errors_low[0x20];
2085
2086 u8 edpl_bip_errors_lane0_high[0x20];
2087
2088 u8 edpl_bip_errors_lane0_low[0x20];
2089
2090 u8 edpl_bip_errors_lane1_high[0x20];
2091
2092 u8 edpl_bip_errors_lane1_low[0x20];
2093
2094 u8 edpl_bip_errors_lane2_high[0x20];
2095
2096 u8 edpl_bip_errors_lane2_low[0x20];
2097
2098 u8 edpl_bip_errors_lane3_high[0x20];
2099
2100 u8 edpl_bip_errors_lane3_low[0x20];
2101
2102 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2103
2104 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2105
2106 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2107
2108 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2109
2110 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2111
2112 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2113
2114 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2115
2116 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2117
2118 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2119
2120 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2121
2122 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2123
2124 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2125
2126 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2127
2128 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2129
2130 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2131
2132 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2133
2134 u8 rs_fec_corrected_blocks_high[0x20];
2135
2136 u8 rs_fec_corrected_blocks_low[0x20];
2137
2138 u8 rs_fec_uncorrectable_blocks_high[0x20];
2139
2140 u8 rs_fec_uncorrectable_blocks_low[0x20];
2141
2142 u8 rs_fec_no_errors_blocks_high[0x20];
2143
2144 u8 rs_fec_no_errors_blocks_low[0x20];
2145
2146 u8 rs_fec_single_error_blocks_high[0x20];
2147
2148 u8 rs_fec_single_error_blocks_low[0x20];
2149
2150 u8 rs_fec_corrected_symbols_total_high[0x20];
2151
2152 u8 rs_fec_corrected_symbols_total_low[0x20];
2153
2154 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2155
2156 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2157
2158 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2159
2160 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2161
2162 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2163
2164 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2165
2166 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2167
2168 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2169
2170 u8 link_down_events[0x20];
2171
2172 u8 successful_recovery_events[0x20];
2173
2174 u8 reserved_at_640[0x180];
2175 };
2176
2177 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2178 u8 time_since_last_clear_high[0x20];
2179
2180 u8 time_since_last_clear_low[0x20];
2181
2182 u8 phy_received_bits_high[0x20];
2183
2184 u8 phy_received_bits_low[0x20];
2185
2186 u8 phy_symbol_errors_high[0x20];
2187
2188 u8 phy_symbol_errors_low[0x20];
2189
2190 u8 phy_corrected_bits_high[0x20];
2191
2192 u8 phy_corrected_bits_low[0x20];
2193
2194 u8 phy_corrected_bits_lane0_high[0x20];
2195
2196 u8 phy_corrected_bits_lane0_low[0x20];
2197
2198 u8 phy_corrected_bits_lane1_high[0x20];
2199
2200 u8 phy_corrected_bits_lane1_low[0x20];
2201
2202 u8 phy_corrected_bits_lane2_high[0x20];
2203
2204 u8 phy_corrected_bits_lane2_low[0x20];
2205
2206 u8 phy_corrected_bits_lane3_high[0x20];
2207
2208 u8 phy_corrected_bits_lane3_low[0x20];
2209
2210 u8 reserved_at_200[0x5c0];
2211 };
2212
2213 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2214 u8 symbol_error_counter[0x10];
2215
2216 u8 link_error_recovery_counter[0x8];
2217
2218 u8 link_downed_counter[0x8];
2219
2220 u8 port_rcv_errors[0x10];
2221
2222 u8 port_rcv_remote_physical_errors[0x10];
2223
2224 u8 port_rcv_switch_relay_errors[0x10];
2225
2226 u8 port_xmit_discards[0x10];
2227
2228 u8 port_xmit_constraint_errors[0x8];
2229
2230 u8 port_rcv_constraint_errors[0x8];
2231
2232 u8 reserved_at_70[0x8];
2233
2234 u8 link_overrun_errors[0x8];
2235
2236 u8 reserved_at_80[0x10];
2237
2238 u8 vl_15_dropped[0x10];
2239
2240 u8 reserved_at_a0[0x80];
2241
2242 u8 port_xmit_wait[0x20];
2243 };
2244
2245 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2246 u8 transmit_queue_high[0x20];
2247
2248 u8 transmit_queue_low[0x20];
2249
2250 u8 no_buffer_discard_uc_high[0x20];
2251
2252 u8 no_buffer_discard_uc_low[0x20];
2253
2254 u8 reserved_at_80[0x740];
2255 };
2256
2257 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2258 u8 wred_discard_high[0x20];
2259
2260 u8 wred_discard_low[0x20];
2261
2262 u8 ecn_marked_tc_high[0x20];
2263
2264 u8 ecn_marked_tc_low[0x20];
2265
2266 u8 reserved_at_80[0x740];
2267 };
2268
2269 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2270 u8 rx_octets_high[0x20];
2271
2272 u8 rx_octets_low[0x20];
2273
2274 u8 reserved_at_40[0xc0];
2275
2276 u8 rx_frames_high[0x20];
2277
2278 u8 rx_frames_low[0x20];
2279
2280 u8 tx_octets_high[0x20];
2281
2282 u8 tx_octets_low[0x20];
2283
2284 u8 reserved_at_180[0xc0];
2285
2286 u8 tx_frames_high[0x20];
2287
2288 u8 tx_frames_low[0x20];
2289
2290 u8 rx_pause_high[0x20];
2291
2292 u8 rx_pause_low[0x20];
2293
2294 u8 rx_pause_duration_high[0x20];
2295
2296 u8 rx_pause_duration_low[0x20];
2297
2298 u8 tx_pause_high[0x20];
2299
2300 u8 tx_pause_low[0x20];
2301
2302 u8 tx_pause_duration_high[0x20];
2303
2304 u8 tx_pause_duration_low[0x20];
2305
2306 u8 rx_pause_transition_high[0x20];
2307
2308 u8 rx_pause_transition_low[0x20];
2309
2310 u8 rx_discards_high[0x20];
2311
2312 u8 rx_discards_low[0x20];
2313
2314 u8 device_stall_minor_watermark_cnt_high[0x20];
2315
2316 u8 device_stall_minor_watermark_cnt_low[0x20];
2317
2318 u8 device_stall_critical_watermark_cnt_high[0x20];
2319
2320 u8 device_stall_critical_watermark_cnt_low[0x20];
2321
2322 u8 reserved_at_480[0x340];
2323 };
2324
2325 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2326 u8 port_transmit_wait_high[0x20];
2327
2328 u8 port_transmit_wait_low[0x20];
2329
2330 u8 reserved_at_40[0x100];
2331
2332 u8 rx_buffer_almost_full_high[0x20];
2333
2334 u8 rx_buffer_almost_full_low[0x20];
2335
2336 u8 rx_buffer_full_high[0x20];
2337
2338 u8 rx_buffer_full_low[0x20];
2339
2340 u8 rx_icrc_encapsulated_high[0x20];
2341
2342 u8 rx_icrc_encapsulated_low[0x20];
2343
2344 u8 reserved_at_200[0x5c0];
2345 };
2346
2347 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2348 u8 dot3stats_alignment_errors_high[0x20];
2349
2350 u8 dot3stats_alignment_errors_low[0x20];
2351
2352 u8 dot3stats_fcs_errors_high[0x20];
2353
2354 u8 dot3stats_fcs_errors_low[0x20];
2355
2356 u8 dot3stats_single_collision_frames_high[0x20];
2357
2358 u8 dot3stats_single_collision_frames_low[0x20];
2359
2360 u8 dot3stats_multiple_collision_frames_high[0x20];
2361
2362 u8 dot3stats_multiple_collision_frames_low[0x20];
2363
2364 u8 dot3stats_sqe_test_errors_high[0x20];
2365
2366 u8 dot3stats_sqe_test_errors_low[0x20];
2367
2368 u8 dot3stats_deferred_transmissions_high[0x20];
2369
2370 u8 dot3stats_deferred_transmissions_low[0x20];
2371
2372 u8 dot3stats_late_collisions_high[0x20];
2373
2374 u8 dot3stats_late_collisions_low[0x20];
2375
2376 u8 dot3stats_excessive_collisions_high[0x20];
2377
2378 u8 dot3stats_excessive_collisions_low[0x20];
2379
2380 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2381
2382 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2383
2384 u8 dot3stats_carrier_sense_errors_high[0x20];
2385
2386 u8 dot3stats_carrier_sense_errors_low[0x20];
2387
2388 u8 dot3stats_frame_too_longs_high[0x20];
2389
2390 u8 dot3stats_frame_too_longs_low[0x20];
2391
2392 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2393
2394 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2395
2396 u8 dot3stats_symbol_errors_high[0x20];
2397
2398 u8 dot3stats_symbol_errors_low[0x20];
2399
2400 u8 dot3control_in_unknown_opcodes_high[0x20];
2401
2402 u8 dot3control_in_unknown_opcodes_low[0x20];
2403
2404 u8 dot3in_pause_frames_high[0x20];
2405
2406 u8 dot3in_pause_frames_low[0x20];
2407
2408 u8 dot3out_pause_frames_high[0x20];
2409
2410 u8 dot3out_pause_frames_low[0x20];
2411
2412 u8 reserved_at_400[0x3c0];
2413 };
2414
2415 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2416 u8 ether_stats_drop_events_high[0x20];
2417
2418 u8 ether_stats_drop_events_low[0x20];
2419
2420 u8 ether_stats_octets_high[0x20];
2421
2422 u8 ether_stats_octets_low[0x20];
2423
2424 u8 ether_stats_pkts_high[0x20];
2425
2426 u8 ether_stats_pkts_low[0x20];
2427
2428 u8 ether_stats_broadcast_pkts_high[0x20];
2429
2430 u8 ether_stats_broadcast_pkts_low[0x20];
2431
2432 u8 ether_stats_multicast_pkts_high[0x20];
2433
2434 u8 ether_stats_multicast_pkts_low[0x20];
2435
2436 u8 ether_stats_crc_align_errors_high[0x20];
2437
2438 u8 ether_stats_crc_align_errors_low[0x20];
2439
2440 u8 ether_stats_undersize_pkts_high[0x20];
2441
2442 u8 ether_stats_undersize_pkts_low[0x20];
2443
2444 u8 ether_stats_oversize_pkts_high[0x20];
2445
2446 u8 ether_stats_oversize_pkts_low[0x20];
2447
2448 u8 ether_stats_fragments_high[0x20];
2449
2450 u8 ether_stats_fragments_low[0x20];
2451
2452 u8 ether_stats_jabbers_high[0x20];
2453
2454 u8 ether_stats_jabbers_low[0x20];
2455
2456 u8 ether_stats_collisions_high[0x20];
2457
2458 u8 ether_stats_collisions_low[0x20];
2459
2460 u8 ether_stats_pkts64octets_high[0x20];
2461
2462 u8 ether_stats_pkts64octets_low[0x20];
2463
2464 u8 ether_stats_pkts65to127octets_high[0x20];
2465
2466 u8 ether_stats_pkts65to127octets_low[0x20];
2467
2468 u8 ether_stats_pkts128to255octets_high[0x20];
2469
2470 u8 ether_stats_pkts128to255octets_low[0x20];
2471
2472 u8 ether_stats_pkts256to511octets_high[0x20];
2473
2474 u8 ether_stats_pkts256to511octets_low[0x20];
2475
2476 u8 ether_stats_pkts512to1023octets_high[0x20];
2477
2478 u8 ether_stats_pkts512to1023octets_low[0x20];
2479
2480 u8 ether_stats_pkts1024to1518octets_high[0x20];
2481
2482 u8 ether_stats_pkts1024to1518octets_low[0x20];
2483
2484 u8 ether_stats_pkts1519to2047octets_high[0x20];
2485
2486 u8 ether_stats_pkts1519to2047octets_low[0x20];
2487
2488 u8 ether_stats_pkts2048to4095octets_high[0x20];
2489
2490 u8 ether_stats_pkts2048to4095octets_low[0x20];
2491
2492 u8 ether_stats_pkts4096to8191octets_high[0x20];
2493
2494 u8 ether_stats_pkts4096to8191octets_low[0x20];
2495
2496 u8 ether_stats_pkts8192to10239octets_high[0x20];
2497
2498 u8 ether_stats_pkts8192to10239octets_low[0x20];
2499
2500 u8 reserved_at_540[0x280];
2501 };
2502
2503 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2504 u8 if_in_octets_high[0x20];
2505
2506 u8 if_in_octets_low[0x20];
2507
2508 u8 if_in_ucast_pkts_high[0x20];
2509
2510 u8 if_in_ucast_pkts_low[0x20];
2511
2512 u8 if_in_discards_high[0x20];
2513
2514 u8 if_in_discards_low[0x20];
2515
2516 u8 if_in_errors_high[0x20];
2517
2518 u8 if_in_errors_low[0x20];
2519
2520 u8 if_in_unknown_protos_high[0x20];
2521
2522 u8 if_in_unknown_protos_low[0x20];
2523
2524 u8 if_out_octets_high[0x20];
2525
2526 u8 if_out_octets_low[0x20];
2527
2528 u8 if_out_ucast_pkts_high[0x20];
2529
2530 u8 if_out_ucast_pkts_low[0x20];
2531
2532 u8 if_out_discards_high[0x20];
2533
2534 u8 if_out_discards_low[0x20];
2535
2536 u8 if_out_errors_high[0x20];
2537
2538 u8 if_out_errors_low[0x20];
2539
2540 u8 if_in_multicast_pkts_high[0x20];
2541
2542 u8 if_in_multicast_pkts_low[0x20];
2543
2544 u8 if_in_broadcast_pkts_high[0x20];
2545
2546 u8 if_in_broadcast_pkts_low[0x20];
2547
2548 u8 if_out_multicast_pkts_high[0x20];
2549
2550 u8 if_out_multicast_pkts_low[0x20];
2551
2552 u8 if_out_broadcast_pkts_high[0x20];
2553
2554 u8 if_out_broadcast_pkts_low[0x20];
2555
2556 u8 reserved_at_340[0x480];
2557 };
2558
2559 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2560 u8 a_frames_transmitted_ok_high[0x20];
2561
2562 u8 a_frames_transmitted_ok_low[0x20];
2563
2564 u8 a_frames_received_ok_high[0x20];
2565
2566 u8 a_frames_received_ok_low[0x20];
2567
2568 u8 a_frame_check_sequence_errors_high[0x20];
2569
2570 u8 a_frame_check_sequence_errors_low[0x20];
2571
2572 u8 a_alignment_errors_high[0x20];
2573
2574 u8 a_alignment_errors_low[0x20];
2575
2576 u8 a_octets_transmitted_ok_high[0x20];
2577
2578 u8 a_octets_transmitted_ok_low[0x20];
2579
2580 u8 a_octets_received_ok_high[0x20];
2581
2582 u8 a_octets_received_ok_low[0x20];
2583
2584 u8 a_multicast_frames_xmitted_ok_high[0x20];
2585
2586 u8 a_multicast_frames_xmitted_ok_low[0x20];
2587
2588 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2589
2590 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2591
2592 u8 a_multicast_frames_received_ok_high[0x20];
2593
2594 u8 a_multicast_frames_received_ok_low[0x20];
2595
2596 u8 a_broadcast_frames_received_ok_high[0x20];
2597
2598 u8 a_broadcast_frames_received_ok_low[0x20];
2599
2600 u8 a_in_range_length_errors_high[0x20];
2601
2602 u8 a_in_range_length_errors_low[0x20];
2603
2604 u8 a_out_of_range_length_field_high[0x20];
2605
2606 u8 a_out_of_range_length_field_low[0x20];
2607
2608 u8 a_frame_too_long_errors_high[0x20];
2609
2610 u8 a_frame_too_long_errors_low[0x20];
2611
2612 u8 a_symbol_error_during_carrier_high[0x20];
2613
2614 u8 a_symbol_error_during_carrier_low[0x20];
2615
2616 u8 a_mac_control_frames_transmitted_high[0x20];
2617
2618 u8 a_mac_control_frames_transmitted_low[0x20];
2619
2620 u8 a_mac_control_frames_received_high[0x20];
2621
2622 u8 a_mac_control_frames_received_low[0x20];
2623
2624 u8 a_unsupported_opcodes_received_high[0x20];
2625
2626 u8 a_unsupported_opcodes_received_low[0x20];
2627
2628 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2629
2630 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2631
2632 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2633
2634 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2635
2636 u8 reserved_at_4c0[0x300];
2637 };
2638
2639 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2640 u8 life_time_counter_high[0x20];
2641
2642 u8 life_time_counter_low[0x20];
2643
2644 u8 rx_errors[0x20];
2645
2646 u8 tx_errors[0x20];
2647
2648 u8 l0_to_recovery_eieos[0x20];
2649
2650 u8 l0_to_recovery_ts[0x20];
2651
2652 u8 l0_to_recovery_framing[0x20];
2653
2654 u8 l0_to_recovery_retrain[0x20];
2655
2656 u8 crc_error_dllp[0x20];
2657
2658 u8 crc_error_tlp[0x20];
2659
2660 u8 tx_overflow_buffer_pkt_high[0x20];
2661
2662 u8 tx_overflow_buffer_pkt_low[0x20];
2663
2664 u8 outbound_stalled_reads[0x20];
2665
2666 u8 outbound_stalled_writes[0x20];
2667
2668 u8 outbound_stalled_reads_events[0x20];
2669
2670 u8 outbound_stalled_writes_events[0x20];
2671
2672 u8 reserved_at_200[0x5c0];
2673 };
2674
2675 struct mlx5_ifc_cmd_inter_comp_event_bits {
2676 u8 command_completion_vector[0x20];
2677
2678 u8 reserved_at_20[0xc0];
2679 };
2680
2681 struct mlx5_ifc_stall_vl_event_bits {
2682 u8 reserved_at_0[0x18];
2683 u8 port_num[0x1];
2684 u8 reserved_at_19[0x3];
2685 u8 vl[0x4];
2686
2687 u8 reserved_at_20[0xa0];
2688 };
2689
2690 struct mlx5_ifc_db_bf_congestion_event_bits {
2691 u8 event_subtype[0x8];
2692 u8 reserved_at_8[0x8];
2693 u8 congestion_level[0x8];
2694 u8 reserved_at_18[0x8];
2695
2696 u8 reserved_at_20[0xa0];
2697 };
2698
2699 struct mlx5_ifc_gpio_event_bits {
2700 u8 reserved_at_0[0x60];
2701
2702 u8 gpio_event_hi[0x20];
2703
2704 u8 gpio_event_lo[0x20];
2705
2706 u8 reserved_at_a0[0x40];
2707 };
2708
2709 struct mlx5_ifc_port_state_change_event_bits {
2710 u8 reserved_at_0[0x40];
2711
2712 u8 port_num[0x4];
2713 u8 reserved_at_44[0x1c];
2714
2715 u8 reserved_at_60[0x80];
2716 };
2717
2718 struct mlx5_ifc_dropped_packet_logged_bits {
2719 u8 reserved_at_0[0xe0];
2720 };
2721
2722 enum {
2723 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2724 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2725 };
2726
2727 struct mlx5_ifc_cq_error_bits {
2728 u8 reserved_at_0[0x8];
2729 u8 cqn[0x18];
2730
2731 u8 reserved_at_20[0x20];
2732
2733 u8 reserved_at_40[0x18];
2734 u8 syndrome[0x8];
2735
2736 u8 reserved_at_60[0x80];
2737 };
2738
2739 struct mlx5_ifc_rdma_page_fault_event_bits {
2740 u8 bytes_committed[0x20];
2741
2742 u8 r_key[0x20];
2743
2744 u8 reserved_at_40[0x10];
2745 u8 packet_len[0x10];
2746
2747 u8 rdma_op_len[0x20];
2748
2749 u8 rdma_va[0x40];
2750
2751 u8 reserved_at_c0[0x5];
2752 u8 rdma[0x1];
2753 u8 write[0x1];
2754 u8 requestor[0x1];
2755 u8 qp_number[0x18];
2756 };
2757
2758 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2759 u8 bytes_committed[0x20];
2760
2761 u8 reserved_at_20[0x10];
2762 u8 wqe_index[0x10];
2763
2764 u8 reserved_at_40[0x10];
2765 u8 len[0x10];
2766
2767 u8 reserved_at_60[0x60];
2768
2769 u8 reserved_at_c0[0x5];
2770 u8 rdma[0x1];
2771 u8 write_read[0x1];
2772 u8 requestor[0x1];
2773 u8 qpn[0x18];
2774 };
2775
2776 struct mlx5_ifc_qp_events_bits {
2777 u8 reserved_at_0[0xa0];
2778
2779 u8 type[0x8];
2780 u8 reserved_at_a8[0x18];
2781
2782 u8 reserved_at_c0[0x8];
2783 u8 qpn_rqn_sqn[0x18];
2784 };
2785
2786 struct mlx5_ifc_dct_events_bits {
2787 u8 reserved_at_0[0xc0];
2788
2789 u8 reserved_at_c0[0x8];
2790 u8 dct_number[0x18];
2791 };
2792
2793 struct mlx5_ifc_comp_event_bits {
2794 u8 reserved_at_0[0xc0];
2795
2796 u8 reserved_at_c0[0x8];
2797 u8 cq_number[0x18];
2798 };
2799
2800 enum {
2801 MLX5_QPC_STATE_RST = 0x0,
2802 MLX5_QPC_STATE_INIT = 0x1,
2803 MLX5_QPC_STATE_RTR = 0x2,
2804 MLX5_QPC_STATE_RTS = 0x3,
2805 MLX5_QPC_STATE_SQER = 0x4,
2806 MLX5_QPC_STATE_ERR = 0x6,
2807 MLX5_QPC_STATE_SQD = 0x7,
2808 MLX5_QPC_STATE_SUSPENDED = 0x9,
2809 };
2810
2811 enum {
2812 MLX5_QPC_ST_RC = 0x0,
2813 MLX5_QPC_ST_UC = 0x1,
2814 MLX5_QPC_ST_UD = 0x2,
2815 MLX5_QPC_ST_XRC = 0x3,
2816 MLX5_QPC_ST_DCI = 0x5,
2817 MLX5_QPC_ST_QP0 = 0x7,
2818 MLX5_QPC_ST_QP1 = 0x8,
2819 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2820 MLX5_QPC_ST_REG_UMR = 0xc,
2821 };
2822
2823 enum {
2824 MLX5_QPC_PM_STATE_ARMED = 0x0,
2825 MLX5_QPC_PM_STATE_REARM = 0x1,
2826 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2827 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2828 };
2829
2830 enum {
2831 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2832 };
2833
2834 enum {
2835 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2836 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2837 };
2838
2839 enum {
2840 MLX5_QPC_MTU_256_BYTES = 0x1,
2841 MLX5_QPC_MTU_512_BYTES = 0x2,
2842 MLX5_QPC_MTU_1K_BYTES = 0x3,
2843 MLX5_QPC_MTU_2K_BYTES = 0x4,
2844 MLX5_QPC_MTU_4K_BYTES = 0x5,
2845 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2846 };
2847
2848 enum {
2849 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2850 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2851 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2852 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2853 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2854 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2855 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2856 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2857 };
2858
2859 enum {
2860 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2861 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2862 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2863 };
2864
2865 enum {
2866 MLX5_QPC_CS_RES_DISABLE = 0x0,
2867 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2868 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2869 };
2870
2871 struct mlx5_ifc_qpc_bits {
2872 u8 state[0x4];
2873 u8 lag_tx_port_affinity[0x4];
2874 u8 st[0x8];
2875 u8 reserved_at_10[0x3];
2876 u8 pm_state[0x2];
2877 u8 reserved_at_15[0x1];
2878 u8 req_e2e_credit_mode[0x2];
2879 u8 offload_type[0x4];
2880 u8 end_padding_mode[0x2];
2881 u8 reserved_at_1e[0x2];
2882
2883 u8 wq_signature[0x1];
2884 u8 block_lb_mc[0x1];
2885 u8 atomic_like_write_en[0x1];
2886 u8 latency_sensitive[0x1];
2887 u8 reserved_at_24[0x1];
2888 u8 drain_sigerr[0x1];
2889 u8 reserved_at_26[0x2];
2890 u8 pd[0x18];
2891
2892 u8 mtu[0x3];
2893 u8 log_msg_max[0x5];
2894 u8 reserved_at_48[0x1];
2895 u8 log_rq_size[0x4];
2896 u8 log_rq_stride[0x3];
2897 u8 no_sq[0x1];
2898 u8 log_sq_size[0x4];
2899 u8 reserved_at_55[0x6];
2900 u8 rlky[0x1];
2901 u8 ulp_stateless_offload_mode[0x4];
2902
2903 u8 counter_set_id[0x8];
2904 u8 uar_page[0x18];
2905
2906 u8 reserved_at_80[0x8];
2907 u8 user_index[0x18];
2908
2909 u8 reserved_at_a0[0x3];
2910 u8 log_page_size[0x5];
2911 u8 remote_qpn[0x18];
2912
2913 struct mlx5_ifc_ads_bits primary_address_path;
2914
2915 struct mlx5_ifc_ads_bits secondary_address_path;
2916
2917 u8 log_ack_req_freq[0x4];
2918 u8 reserved_at_384[0x4];
2919 u8 log_sra_max[0x3];
2920 u8 reserved_at_38b[0x2];
2921 u8 retry_count[0x3];
2922 u8 rnr_retry[0x3];
2923 u8 reserved_at_393[0x1];
2924 u8 fre[0x1];
2925 u8 cur_rnr_retry[0x3];
2926 u8 cur_retry_count[0x3];
2927 u8 reserved_at_39b[0x5];
2928
2929 u8 reserved_at_3a0[0x20];
2930
2931 u8 reserved_at_3c0[0x8];
2932 u8 next_send_psn[0x18];
2933
2934 u8 reserved_at_3e0[0x8];
2935 u8 cqn_snd[0x18];
2936
2937 u8 reserved_at_400[0x8];
2938 u8 deth_sqpn[0x18];
2939
2940 u8 reserved_at_420[0x20];
2941
2942 u8 reserved_at_440[0x8];
2943 u8 last_acked_psn[0x18];
2944
2945 u8 reserved_at_460[0x8];
2946 u8 ssn[0x18];
2947
2948 u8 reserved_at_480[0x8];
2949 u8 log_rra_max[0x3];
2950 u8 reserved_at_48b[0x1];
2951 u8 atomic_mode[0x4];
2952 u8 rre[0x1];
2953 u8 rwe[0x1];
2954 u8 rae[0x1];
2955 u8 reserved_at_493[0x1];
2956 u8 page_offset[0x6];
2957 u8 reserved_at_49a[0x3];
2958 u8 cd_slave_receive[0x1];
2959 u8 cd_slave_send[0x1];
2960 u8 cd_master[0x1];
2961
2962 u8 reserved_at_4a0[0x3];
2963 u8 min_rnr_nak[0x5];
2964 u8 next_rcv_psn[0x18];
2965
2966 u8 reserved_at_4c0[0x8];
2967 u8 xrcd[0x18];
2968
2969 u8 reserved_at_4e0[0x8];
2970 u8 cqn_rcv[0x18];
2971
2972 u8 dbr_addr[0x40];
2973
2974 u8 q_key[0x20];
2975
2976 u8 reserved_at_560[0x5];
2977 u8 rq_type[0x3];
2978 u8 srqn_rmpn_xrqn[0x18];
2979
2980 u8 reserved_at_580[0x8];
2981 u8 rmsn[0x18];
2982
2983 u8 hw_sq_wqebb_counter[0x10];
2984 u8 sw_sq_wqebb_counter[0x10];
2985
2986 u8 hw_rq_counter[0x20];
2987
2988 u8 sw_rq_counter[0x20];
2989
2990 u8 reserved_at_600[0x20];
2991
2992 u8 reserved_at_620[0xf];
2993 u8 cgs[0x1];
2994 u8 cs_req[0x8];
2995 u8 cs_res[0x8];
2996
2997 u8 dc_access_key[0x40];
2998
2999 u8 reserved_at_680[0x3];
3000 u8 dbr_umem_valid[0x1];
3001
3002 u8 reserved_at_684[0xbc];
3003 };
3004
3005 struct mlx5_ifc_roce_addr_layout_bits {
3006 u8 source_l3_address[16][0x8];
3007
3008 u8 reserved_at_80[0x3];
3009 u8 vlan_valid[0x1];
3010 u8 vlan_id[0xc];
3011 u8 source_mac_47_32[0x10];
3012
3013 u8 source_mac_31_0[0x20];
3014
3015 u8 reserved_at_c0[0x14];
3016 u8 roce_l3_type[0x4];
3017 u8 roce_version[0x8];
3018
3019 u8 reserved_at_e0[0x20];
3020 };
3021
3022 union mlx5_ifc_hca_cap_union_bits {
3023 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3024 struct mlx5_ifc_odp_cap_bits odp_cap;
3025 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3026 struct mlx5_ifc_roce_cap_bits roce_cap;
3027 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3028 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3029 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3030 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3031 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3032 struct mlx5_ifc_qos_cap_bits qos_cap;
3033 struct mlx5_ifc_debug_cap_bits debug_cap;
3034 struct mlx5_ifc_fpga_cap_bits fpga_cap;
3035 struct mlx5_ifc_tls_cap_bits tls_cap;
3036 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3037 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3038 u8 reserved_at_0[0x8000];
3039 };
3040
3041 enum {
3042 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3043 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3044 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3045 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3046 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3047 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3048 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3049 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3050 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3051 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3052 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3053 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3054 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3055 };
3056
3057 enum {
3058 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3059 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3060 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3061 };
3062
3063 struct mlx5_ifc_vlan_bits {
3064 u8 ethtype[0x10];
3065 u8 prio[0x3];
3066 u8 cfi[0x1];
3067 u8 vid[0xc];
3068 };
3069
3070 struct mlx5_ifc_flow_context_bits {
3071 struct mlx5_ifc_vlan_bits push_vlan;
3072
3073 u8 group_id[0x20];
3074
3075 u8 reserved_at_40[0x8];
3076 u8 flow_tag[0x18];
3077
3078 u8 reserved_at_60[0x10];
3079 u8 action[0x10];
3080
3081 u8 extended_destination[0x1];
3082 u8 reserved_at_81[0x1];
3083 u8 flow_source[0x2];
3084 u8 reserved_at_84[0x4];
3085 u8 destination_list_size[0x18];
3086
3087 u8 reserved_at_a0[0x8];
3088 u8 flow_counter_list_size[0x18];
3089
3090 u8 packet_reformat_id[0x20];
3091
3092 u8 modify_header_id[0x20];
3093
3094 struct mlx5_ifc_vlan_bits push_vlan_2;
3095
3096 u8 ipsec_obj_id[0x20];
3097 u8 reserved_at_140[0xc0];
3098
3099 struct mlx5_ifc_fte_match_param_bits match_value;
3100
3101 u8 reserved_at_1200[0x600];
3102
3103 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3104 };
3105
3106 enum {
3107 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3108 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3109 };
3110
3111 struct mlx5_ifc_xrc_srqc_bits {
3112 u8 state[0x4];
3113 u8 log_xrc_srq_size[0x4];
3114 u8 reserved_at_8[0x18];
3115
3116 u8 wq_signature[0x1];
3117 u8 cont_srq[0x1];
3118 u8 reserved_at_22[0x1];
3119 u8 rlky[0x1];
3120 u8 basic_cyclic_rcv_wqe[0x1];
3121 u8 log_rq_stride[0x3];
3122 u8 xrcd[0x18];
3123
3124 u8 page_offset[0x6];
3125 u8 reserved_at_46[0x1];
3126 u8 dbr_umem_valid[0x1];
3127 u8 cqn[0x18];
3128
3129 u8 reserved_at_60[0x20];
3130
3131 u8 user_index_equal_xrc_srqn[0x1];
3132 u8 reserved_at_81[0x1];
3133 u8 log_page_size[0x6];
3134 u8 user_index[0x18];
3135
3136 u8 reserved_at_a0[0x20];
3137
3138 u8 reserved_at_c0[0x8];
3139 u8 pd[0x18];
3140
3141 u8 lwm[0x10];
3142 u8 wqe_cnt[0x10];
3143
3144 u8 reserved_at_100[0x40];
3145
3146 u8 db_record_addr_h[0x20];
3147
3148 u8 db_record_addr_l[0x1e];
3149 u8 reserved_at_17e[0x2];
3150
3151 u8 reserved_at_180[0x80];
3152 };
3153
3154 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3155 u8 counter_error_queues[0x20];
3156
3157 u8 total_error_queues[0x20];
3158
3159 u8 send_queue_priority_update_flow[0x20];
3160
3161 u8 reserved_at_60[0x20];
3162
3163 u8 nic_receive_steering_discard[0x40];
3164
3165 u8 receive_discard_vport_down[0x40];
3166
3167 u8 transmit_discard_vport_down[0x40];
3168
3169 u8 reserved_at_140[0xa0];
3170
3171 u8 internal_rq_out_of_buffer[0x20];
3172
3173 u8 reserved_at_200[0xe00];
3174 };
3175
3176 struct mlx5_ifc_traffic_counter_bits {
3177 u8 packets[0x40];
3178
3179 u8 octets[0x40];
3180 };
3181
3182 struct mlx5_ifc_tisc_bits {
3183 u8 strict_lag_tx_port_affinity[0x1];
3184 u8 tls_en[0x1];
3185 u8 reserved_at_2[0x2];
3186 u8 lag_tx_port_affinity[0x04];
3187
3188 u8 reserved_at_8[0x4];
3189 u8 prio[0x4];
3190 u8 reserved_at_10[0x10];
3191
3192 u8 reserved_at_20[0x100];
3193
3194 u8 reserved_at_120[0x8];
3195 u8 transport_domain[0x18];
3196
3197 u8 reserved_at_140[0x8];
3198 u8 underlay_qpn[0x18];
3199
3200 u8 reserved_at_160[0x8];
3201 u8 pd[0x18];
3202
3203 u8 reserved_at_180[0x380];
3204 };
3205
3206 enum {
3207 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3208 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3209 };
3210
3211 enum {
3212 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
3213 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
3214 };
3215
3216 enum {
3217 MLX5_RX_HASH_FN_NONE = 0x0,
3218 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3219 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3220 };
3221
3222 enum {
3223 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3224 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3225 };
3226
3227 struct mlx5_ifc_tirc_bits {
3228 u8 reserved_at_0[0x20];
3229
3230 u8 disp_type[0x4];
3231 u8 tls_en[0x1];
3232 u8 reserved_at_25[0x1b];
3233
3234 u8 reserved_at_40[0x40];
3235
3236 u8 reserved_at_80[0x4];
3237 u8 lro_timeout_period_usecs[0x10];
3238 u8 lro_enable_mask[0x4];
3239 u8 lro_max_ip_payload_size[0x8];
3240
3241 u8 reserved_at_a0[0x40];
3242
3243 u8 reserved_at_e0[0x8];
3244 u8 inline_rqn[0x18];
3245
3246 u8 rx_hash_symmetric[0x1];
3247 u8 reserved_at_101[0x1];
3248 u8 tunneled_offload_en[0x1];
3249 u8 reserved_at_103[0x5];
3250 u8 indirect_table[0x18];
3251
3252 u8 rx_hash_fn[0x4];
3253 u8 reserved_at_124[0x2];
3254 u8 self_lb_block[0x2];
3255 u8 transport_domain[0x18];
3256
3257 u8 rx_hash_toeplitz_key[10][0x20];
3258
3259 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3260
3261 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3262
3263 u8 reserved_at_2c0[0x4c0];
3264 };
3265
3266 enum {
3267 MLX5_SRQC_STATE_GOOD = 0x0,
3268 MLX5_SRQC_STATE_ERROR = 0x1,
3269 };
3270
3271 struct mlx5_ifc_srqc_bits {
3272 u8 state[0x4];
3273 u8 log_srq_size[0x4];
3274 u8 reserved_at_8[0x18];
3275
3276 u8 wq_signature[0x1];
3277 u8 cont_srq[0x1];
3278 u8 reserved_at_22[0x1];
3279 u8 rlky[0x1];
3280 u8 reserved_at_24[0x1];
3281 u8 log_rq_stride[0x3];
3282 u8 xrcd[0x18];
3283
3284 u8 page_offset[0x6];
3285 u8 reserved_at_46[0x2];
3286 u8 cqn[0x18];
3287
3288 u8 reserved_at_60[0x20];
3289
3290 u8 reserved_at_80[0x2];
3291 u8 log_page_size[0x6];
3292 u8 reserved_at_88[0x18];
3293
3294 u8 reserved_at_a0[0x20];
3295
3296 u8 reserved_at_c0[0x8];
3297 u8 pd[0x18];
3298
3299 u8 lwm[0x10];
3300 u8 wqe_cnt[0x10];
3301
3302 u8 reserved_at_100[0x40];
3303
3304 u8 dbr_addr[0x40];
3305
3306 u8 reserved_at_180[0x80];
3307 };
3308
3309 enum {
3310 MLX5_SQC_STATE_RST = 0x0,
3311 MLX5_SQC_STATE_RDY = 0x1,
3312 MLX5_SQC_STATE_ERR = 0x3,
3313 };
3314
3315 struct mlx5_ifc_sqc_bits {
3316 u8 rlky[0x1];
3317 u8 cd_master[0x1];
3318 u8 fre[0x1];
3319 u8 flush_in_error_en[0x1];
3320 u8 allow_multi_pkt_send_wqe[0x1];
3321 u8 min_wqe_inline_mode[0x3];
3322 u8 state[0x4];
3323 u8 reg_umr[0x1];
3324 u8 allow_swp[0x1];
3325 u8 hairpin[0x1];
3326 u8 reserved_at_f[0x11];
3327
3328 u8 reserved_at_20[0x8];
3329 u8 user_index[0x18];
3330
3331 u8 reserved_at_40[0x8];
3332 u8 cqn[0x18];
3333
3334 u8 reserved_at_60[0x8];
3335 u8 hairpin_peer_rq[0x18];
3336
3337 u8 reserved_at_80[0x10];
3338 u8 hairpin_peer_vhca[0x10];
3339
3340 u8 reserved_at_a0[0x20];
3341
3342 u8 reserved_at_c0[0x8];
3343 u8 ts_cqe_to_dest_cqn[0x18];
3344
3345 u8 reserved_at_e0[0x10];
3346 u8 packet_pacing_rate_limit_index[0x10];
3347 u8 tis_lst_sz[0x10];
3348 u8 reserved_at_110[0x10];
3349
3350 u8 reserved_at_120[0x40];
3351
3352 u8 reserved_at_160[0x8];
3353 u8 tis_num_0[0x18];
3354
3355 struct mlx5_ifc_wq_bits wq;
3356 };
3357
3358 enum {
3359 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3360 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3361 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3362 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3363 };
3364
3365 enum {
3366 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3367 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3368 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3369 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3370 };
3371
3372 struct mlx5_ifc_scheduling_context_bits {
3373 u8 element_type[0x8];
3374 u8 reserved_at_8[0x18];
3375
3376 u8 element_attributes[0x20];
3377
3378 u8 parent_element_id[0x20];
3379
3380 u8 reserved_at_60[0x40];
3381
3382 u8 bw_share[0x20];
3383
3384 u8 max_average_bw[0x20];
3385
3386 u8 reserved_at_e0[0x120];
3387 };
3388
3389 struct mlx5_ifc_rqtc_bits {
3390 u8 reserved_at_0[0xa0];
3391
3392 u8 reserved_at_a0[0x5];
3393 u8 list_q_type[0x3];
3394 u8 reserved_at_a8[0x8];
3395 u8 rqt_max_size[0x10];
3396
3397 u8 rq_vhca_id_format[0x1];
3398 u8 reserved_at_c1[0xf];
3399 u8 rqt_actual_size[0x10];
3400
3401 u8 reserved_at_e0[0x6a0];
3402
3403 struct mlx5_ifc_rq_num_bits rq_num[];
3404 };
3405
3406 enum {
3407 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3408 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3409 };
3410
3411 enum {
3412 MLX5_RQC_STATE_RST = 0x0,
3413 MLX5_RQC_STATE_RDY = 0x1,
3414 MLX5_RQC_STATE_ERR = 0x3,
3415 };
3416
3417 struct mlx5_ifc_rqc_bits {
3418 u8 rlky[0x1];
3419 u8 delay_drop_en[0x1];
3420 u8 scatter_fcs[0x1];
3421 u8 vsd[0x1];
3422 u8 mem_rq_type[0x4];
3423 u8 state[0x4];
3424 u8 reserved_at_c[0x1];
3425 u8 flush_in_error_en[0x1];
3426 u8 hairpin[0x1];
3427 u8 reserved_at_f[0x11];
3428
3429 u8 reserved_at_20[0x8];
3430 u8 user_index[0x18];
3431
3432 u8 reserved_at_40[0x8];
3433 u8 cqn[0x18];
3434
3435 u8 counter_set_id[0x8];
3436 u8 reserved_at_68[0x18];
3437
3438 u8 reserved_at_80[0x8];
3439 u8 rmpn[0x18];
3440
3441 u8 reserved_at_a0[0x8];
3442 u8 hairpin_peer_sq[0x18];
3443
3444 u8 reserved_at_c0[0x10];
3445 u8 hairpin_peer_vhca[0x10];
3446
3447 u8 reserved_at_e0[0xa0];
3448
3449 struct mlx5_ifc_wq_bits wq;
3450 };
3451
3452 enum {
3453 MLX5_RMPC_STATE_RDY = 0x1,
3454 MLX5_RMPC_STATE_ERR = 0x3,
3455 };
3456
3457 struct mlx5_ifc_rmpc_bits {
3458 u8 reserved_at_0[0x8];
3459 u8 state[0x4];
3460 u8 reserved_at_c[0x14];
3461
3462 u8 basic_cyclic_rcv_wqe[0x1];
3463 u8 reserved_at_21[0x1f];
3464
3465 u8 reserved_at_40[0x140];
3466
3467 struct mlx5_ifc_wq_bits wq;
3468 };
3469
3470 struct mlx5_ifc_nic_vport_context_bits {
3471 u8 reserved_at_0[0x5];
3472 u8 min_wqe_inline_mode[0x3];
3473 u8 reserved_at_8[0x15];
3474 u8 disable_mc_local_lb[0x1];
3475 u8 disable_uc_local_lb[0x1];
3476 u8 roce_en[0x1];
3477
3478 u8 arm_change_event[0x1];
3479 u8 reserved_at_21[0x1a];
3480 u8 event_on_mtu[0x1];
3481 u8 event_on_promisc_change[0x1];
3482 u8 event_on_vlan_change[0x1];
3483 u8 event_on_mc_address_change[0x1];
3484 u8 event_on_uc_address_change[0x1];
3485
3486 u8 reserved_at_40[0xc];
3487
3488 u8 affiliation_criteria[0x4];
3489 u8 affiliated_vhca_id[0x10];
3490
3491 u8 reserved_at_60[0xd0];
3492
3493 u8 mtu[0x10];
3494
3495 u8 system_image_guid[0x40];
3496 u8 port_guid[0x40];
3497 u8 node_guid[0x40];
3498
3499 u8 reserved_at_200[0x140];
3500 u8 qkey_violation_counter[0x10];
3501 u8 reserved_at_350[0x430];
3502
3503 u8 promisc_uc[0x1];
3504 u8 promisc_mc[0x1];
3505 u8 promisc_all[0x1];
3506 u8 reserved_at_783[0x2];
3507 u8 allowed_list_type[0x3];
3508 u8 reserved_at_788[0xc];
3509 u8 allowed_list_size[0xc];
3510
3511 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3512
3513 u8 reserved_at_7e0[0x20];
3514
3515 u8 current_uc_mac_address[][0x40];
3516 };
3517
3518 enum {
3519 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3520 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3521 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3522 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3523 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3524 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3525 };
3526
3527 struct mlx5_ifc_mkc_bits {
3528 u8 reserved_at_0[0x1];
3529 u8 free[0x1];
3530 u8 reserved_at_2[0x1];
3531 u8 access_mode_4_2[0x3];
3532 u8 reserved_at_6[0x7];
3533 u8 relaxed_ordering_write[0x1];
3534 u8 reserved_at_e[0x1];
3535 u8 small_fence_on_rdma_read_response[0x1];
3536 u8 umr_en[0x1];
3537 u8 a[0x1];
3538 u8 rw[0x1];
3539 u8 rr[0x1];
3540 u8 lw[0x1];
3541 u8 lr[0x1];
3542 u8 access_mode_1_0[0x2];
3543 u8 reserved_at_18[0x8];
3544
3545 u8 qpn[0x18];
3546 u8 mkey_7_0[0x8];
3547
3548 u8 reserved_at_40[0x20];
3549
3550 u8 length64[0x1];
3551 u8 bsf_en[0x1];
3552 u8 sync_umr[0x1];
3553 u8 reserved_at_63[0x2];
3554 u8 expected_sigerr_count[0x1];
3555 u8 reserved_at_66[0x1];
3556 u8 en_rinval[0x1];
3557 u8 pd[0x18];
3558
3559 u8 start_addr[0x40];
3560
3561 u8 len[0x40];
3562
3563 u8 bsf_octword_size[0x20];
3564
3565 u8 reserved_at_120[0x80];
3566
3567 u8 translations_octword_size[0x20];
3568
3569 u8 reserved_at_1c0[0x19];
3570 u8 relaxed_ordering_read[0x1];
3571 u8 reserved_at_1d9[0x1];
3572 u8 log_page_size[0x5];
3573
3574 u8 reserved_at_1e0[0x20];
3575 };
3576
3577 struct mlx5_ifc_pkey_bits {
3578 u8 reserved_at_0[0x10];
3579 u8 pkey[0x10];
3580 };
3581
3582 struct mlx5_ifc_array128_auto_bits {
3583 u8 array128_auto[16][0x8];
3584 };
3585
3586 struct mlx5_ifc_hca_vport_context_bits {
3587 u8 field_select[0x20];
3588
3589 u8 reserved_at_20[0xe0];
3590
3591 u8 sm_virt_aware[0x1];
3592 u8 has_smi[0x1];
3593 u8 has_raw[0x1];
3594 u8 grh_required[0x1];
3595 u8 reserved_at_104[0xc];
3596 u8 port_physical_state[0x4];
3597 u8 vport_state_policy[0x4];
3598 u8 port_state[0x4];
3599 u8 vport_state[0x4];
3600
3601 u8 reserved_at_120[0x20];
3602
3603 u8 system_image_guid[0x40];
3604
3605 u8 port_guid[0x40];
3606
3607 u8 node_guid[0x40];
3608
3609 u8 cap_mask1[0x20];
3610
3611 u8 cap_mask1_field_select[0x20];
3612
3613 u8 cap_mask2[0x20];
3614
3615 u8 cap_mask2_field_select[0x20];
3616
3617 u8 reserved_at_280[0x80];
3618
3619 u8 lid[0x10];
3620 u8 reserved_at_310[0x4];
3621 u8 init_type_reply[0x4];
3622 u8 lmc[0x3];
3623 u8 subnet_timeout[0x5];
3624
3625 u8 sm_lid[0x10];
3626 u8 sm_sl[0x4];
3627 u8 reserved_at_334[0xc];
3628
3629 u8 qkey_violation_counter[0x10];
3630 u8 pkey_violation_counter[0x10];
3631
3632 u8 reserved_at_360[0xca0];
3633 };
3634
3635 struct mlx5_ifc_esw_vport_context_bits {
3636 u8 fdb_to_vport_reg_c[0x1];
3637 u8 reserved_at_1[0x2];
3638 u8 vport_svlan_strip[0x1];
3639 u8 vport_cvlan_strip[0x1];
3640 u8 vport_svlan_insert[0x1];
3641 u8 vport_cvlan_insert[0x2];
3642 u8 fdb_to_vport_reg_c_id[0x8];
3643 u8 reserved_at_10[0x10];
3644
3645 u8 reserved_at_20[0x20];
3646
3647 u8 svlan_cfi[0x1];
3648 u8 svlan_pcp[0x3];
3649 u8 svlan_id[0xc];
3650 u8 cvlan_cfi[0x1];
3651 u8 cvlan_pcp[0x3];
3652 u8 cvlan_id[0xc];
3653
3654 u8 reserved_at_60[0x720];
3655
3656 u8 sw_steering_vport_icm_address_rx[0x40];
3657
3658 u8 sw_steering_vport_icm_address_tx[0x40];
3659 };
3660
3661 enum {
3662 MLX5_EQC_STATUS_OK = 0x0,
3663 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3664 };
3665
3666 enum {
3667 MLX5_EQC_ST_ARMED = 0x9,
3668 MLX5_EQC_ST_FIRED = 0xa,
3669 };
3670
3671 struct mlx5_ifc_eqc_bits {
3672 u8 status[0x4];
3673 u8 reserved_at_4[0x9];
3674 u8 ec[0x1];
3675 u8 oi[0x1];
3676 u8 reserved_at_f[0x5];
3677 u8 st[0x4];
3678 u8 reserved_at_18[0x8];
3679
3680 u8 reserved_at_20[0x20];
3681
3682 u8 reserved_at_40[0x14];
3683 u8 page_offset[0x6];
3684 u8 reserved_at_5a[0x6];
3685
3686 u8 reserved_at_60[0x3];
3687 u8 log_eq_size[0x5];
3688 u8 uar_page[0x18];
3689
3690 u8 reserved_at_80[0x20];
3691
3692 u8 reserved_at_a0[0x18];
3693 u8 intr[0x8];
3694
3695 u8 reserved_at_c0[0x3];
3696 u8 log_page_size[0x5];
3697 u8 reserved_at_c8[0x18];
3698
3699 u8 reserved_at_e0[0x60];
3700
3701 u8 reserved_at_140[0x8];
3702 u8 consumer_counter[0x18];
3703
3704 u8 reserved_at_160[0x8];
3705 u8 producer_counter[0x18];
3706
3707 u8 reserved_at_180[0x80];
3708 };
3709
3710 enum {
3711 MLX5_DCTC_STATE_ACTIVE = 0x0,
3712 MLX5_DCTC_STATE_DRAINING = 0x1,
3713 MLX5_DCTC_STATE_DRAINED = 0x2,
3714 };
3715
3716 enum {
3717 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3718 MLX5_DCTC_CS_RES_NA = 0x1,
3719 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3720 };
3721
3722 enum {
3723 MLX5_DCTC_MTU_256_BYTES = 0x1,
3724 MLX5_DCTC_MTU_512_BYTES = 0x2,
3725 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3726 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3727 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3728 };
3729
3730 struct mlx5_ifc_dctc_bits {
3731 u8 reserved_at_0[0x4];
3732 u8 state[0x4];
3733 u8 reserved_at_8[0x18];
3734
3735 u8 reserved_at_20[0x8];
3736 u8 user_index[0x18];
3737
3738 u8 reserved_at_40[0x8];
3739 u8 cqn[0x18];
3740
3741 u8 counter_set_id[0x8];
3742 u8 atomic_mode[0x4];
3743 u8 rre[0x1];
3744 u8 rwe[0x1];
3745 u8 rae[0x1];
3746 u8 atomic_like_write_en[0x1];
3747 u8 latency_sensitive[0x1];
3748 u8 rlky[0x1];
3749 u8 free_ar[0x1];
3750 u8 reserved_at_73[0xd];
3751
3752 u8 reserved_at_80[0x8];
3753 u8 cs_res[0x8];
3754 u8 reserved_at_90[0x3];
3755 u8 min_rnr_nak[0x5];
3756 u8 reserved_at_98[0x8];
3757
3758 u8 reserved_at_a0[0x8];
3759 u8 srqn_xrqn[0x18];
3760
3761 u8 reserved_at_c0[0x8];
3762 u8 pd[0x18];
3763
3764 u8 tclass[0x8];
3765 u8 reserved_at_e8[0x4];
3766 u8 flow_label[0x14];
3767
3768 u8 dc_access_key[0x40];
3769
3770 u8 reserved_at_140[0x5];
3771 u8 mtu[0x3];
3772 u8 port[0x8];
3773 u8 pkey_index[0x10];
3774
3775 u8 reserved_at_160[0x8];
3776 u8 my_addr_index[0x8];
3777 u8 reserved_at_170[0x8];
3778 u8 hop_limit[0x8];
3779
3780 u8 dc_access_key_violation_count[0x20];
3781
3782 u8 reserved_at_1a0[0x14];
3783 u8 dei_cfi[0x1];
3784 u8 eth_prio[0x3];
3785 u8 ecn[0x2];
3786 u8 dscp[0x6];
3787
3788 u8 reserved_at_1c0[0x20];
3789 u8 ece[0x20];
3790 };
3791
3792 enum {
3793 MLX5_CQC_STATUS_OK = 0x0,
3794 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3795 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3796 };
3797
3798 enum {
3799 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3800 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3801 };
3802
3803 enum {
3804 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3805 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3806 MLX5_CQC_ST_FIRED = 0xa,
3807 };
3808
3809 enum {
3810 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3811 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3812 MLX5_CQ_PERIOD_NUM_MODES
3813 };
3814
3815 struct mlx5_ifc_cqc_bits {
3816 u8 status[0x4];
3817 u8 reserved_at_4[0x2];
3818 u8 dbr_umem_valid[0x1];
3819 u8 reserved_at_7[0x1];
3820 u8 cqe_sz[0x3];
3821 u8 cc[0x1];
3822 u8 reserved_at_c[0x1];
3823 u8 scqe_break_moderation_en[0x1];
3824 u8 oi[0x1];
3825 u8 cq_period_mode[0x2];
3826 u8 cqe_comp_en[0x1];
3827 u8 mini_cqe_res_format[0x2];
3828 u8 st[0x4];
3829 u8 reserved_at_18[0x8];
3830
3831 u8 reserved_at_20[0x20];
3832
3833 u8 reserved_at_40[0x14];
3834 u8 page_offset[0x6];
3835 u8 reserved_at_5a[0x6];
3836
3837 u8 reserved_at_60[0x3];
3838 u8 log_cq_size[0x5];
3839 u8 uar_page[0x18];
3840
3841 u8 reserved_at_80[0x4];
3842 u8 cq_period[0xc];
3843 u8 cq_max_count[0x10];
3844
3845 u8 reserved_at_a0[0x18];
3846 u8 c_eqn[0x8];
3847
3848 u8 reserved_at_c0[0x3];
3849 u8 log_page_size[0x5];
3850 u8 reserved_at_c8[0x18];
3851
3852 u8 reserved_at_e0[0x20];
3853
3854 u8 reserved_at_100[0x8];
3855 u8 last_notified_index[0x18];
3856
3857 u8 reserved_at_120[0x8];
3858 u8 last_solicit_index[0x18];
3859
3860 u8 reserved_at_140[0x8];
3861 u8 consumer_counter[0x18];
3862
3863 u8 reserved_at_160[0x8];
3864 u8 producer_counter[0x18];
3865
3866 u8 reserved_at_180[0x40];
3867
3868 u8 dbr_addr[0x40];
3869 };
3870
3871 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3872 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3873 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3874 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3875 u8 reserved_at_0[0x800];
3876 };
3877
3878 struct mlx5_ifc_query_adapter_param_block_bits {
3879 u8 reserved_at_0[0xc0];
3880
3881 u8 reserved_at_c0[0x8];
3882 u8 ieee_vendor_id[0x18];
3883
3884 u8 reserved_at_e0[0x10];
3885 u8 vsd_vendor_id[0x10];
3886
3887 u8 vsd[208][0x8];
3888
3889 u8 vsd_contd_psid[16][0x8];
3890 };
3891
3892 enum {
3893 MLX5_XRQC_STATE_GOOD = 0x0,
3894 MLX5_XRQC_STATE_ERROR = 0x1,
3895 };
3896
3897 enum {
3898 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3899 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3900 };
3901
3902 enum {
3903 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3904 };
3905
3906 struct mlx5_ifc_tag_matching_topology_context_bits {
3907 u8 log_matching_list_sz[0x4];
3908 u8 reserved_at_4[0xc];
3909 u8 append_next_index[0x10];
3910
3911 u8 sw_phase_cnt[0x10];
3912 u8 hw_phase_cnt[0x10];
3913
3914 u8 reserved_at_40[0x40];
3915 };
3916
3917 struct mlx5_ifc_xrqc_bits {
3918 u8 state[0x4];
3919 u8 rlkey[0x1];
3920 u8 reserved_at_5[0xf];
3921 u8 topology[0x4];
3922 u8 reserved_at_18[0x4];
3923 u8 offload[0x4];
3924
3925 u8 reserved_at_20[0x8];
3926 u8 user_index[0x18];
3927
3928 u8 reserved_at_40[0x8];
3929 u8 cqn[0x18];
3930
3931 u8 reserved_at_60[0xa0];
3932
3933 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3934
3935 u8 reserved_at_180[0x280];
3936
3937 struct mlx5_ifc_wq_bits wq;
3938 };
3939
3940 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3941 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3942 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3943 u8 reserved_at_0[0x20];
3944 };
3945
3946 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3947 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3948 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3949 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3950 u8 reserved_at_0[0x20];
3951 };
3952
3953 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3954 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3955 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3956 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3957 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3958 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3959 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3960 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3961 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3962 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3963 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3964 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3965 u8 reserved_at_0[0x7c0];
3966 };
3967
3968 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3969 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3970 u8 reserved_at_0[0x7c0];
3971 };
3972
3973 union mlx5_ifc_event_auto_bits {
3974 struct mlx5_ifc_comp_event_bits comp_event;
3975 struct mlx5_ifc_dct_events_bits dct_events;
3976 struct mlx5_ifc_qp_events_bits qp_events;
3977 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3978 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3979 struct mlx5_ifc_cq_error_bits cq_error;
3980 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3981 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3982 struct mlx5_ifc_gpio_event_bits gpio_event;
3983 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3984 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3985 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3986 u8 reserved_at_0[0xe0];
3987 };
3988
3989 struct mlx5_ifc_health_buffer_bits {
3990 u8 reserved_at_0[0x100];
3991
3992 u8 assert_existptr[0x20];
3993
3994 u8 assert_callra[0x20];
3995
3996 u8 reserved_at_140[0x40];
3997
3998 u8 fw_version[0x20];
3999
4000 u8 hw_id[0x20];
4001
4002 u8 reserved_at_1c0[0x20];
4003
4004 u8 irisc_index[0x8];
4005 u8 synd[0x8];
4006 u8 ext_synd[0x10];
4007 };
4008
4009 struct mlx5_ifc_register_loopback_control_bits {
4010 u8 no_lb[0x1];
4011 u8 reserved_at_1[0x7];
4012 u8 port[0x8];
4013 u8 reserved_at_10[0x10];
4014
4015 u8 reserved_at_20[0x60];
4016 };
4017
4018 struct mlx5_ifc_vport_tc_element_bits {
4019 u8 traffic_class[0x4];
4020 u8 reserved_at_4[0xc];
4021 u8 vport_number[0x10];
4022 };
4023
4024 struct mlx5_ifc_vport_element_bits {
4025 u8 reserved_at_0[0x10];
4026 u8 vport_number[0x10];
4027 };
4028
4029 enum {
4030 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4031 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4032 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4033 };
4034
4035 struct mlx5_ifc_tsar_element_bits {
4036 u8 reserved_at_0[0x8];
4037 u8 tsar_type[0x8];
4038 u8 reserved_at_10[0x10];
4039 };
4040
4041 enum {
4042 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4043 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4044 };
4045
4046 struct mlx5_ifc_teardown_hca_out_bits {
4047 u8 status[0x8];
4048 u8 reserved_at_8[0x18];
4049
4050 u8 syndrome[0x20];
4051
4052 u8 reserved_at_40[0x3f];
4053
4054 u8 state[0x1];
4055 };
4056
4057 enum {
4058 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4059 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4060 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4061 };
4062
4063 struct mlx5_ifc_teardown_hca_in_bits {
4064 u8 opcode[0x10];
4065 u8 reserved_at_10[0x10];
4066
4067 u8 reserved_at_20[0x10];
4068 u8 op_mod[0x10];
4069
4070 u8 reserved_at_40[0x10];
4071 u8 profile[0x10];
4072
4073 u8 reserved_at_60[0x20];
4074 };
4075
4076 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4077 u8 status[0x8];
4078 u8 reserved_at_8[0x18];
4079
4080 u8 syndrome[0x20];
4081
4082 u8 reserved_at_40[0x40];
4083 };
4084
4085 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4086 u8 opcode[0x10];
4087 u8 uid[0x10];
4088
4089 u8 reserved_at_20[0x10];
4090 u8 op_mod[0x10];
4091
4092 u8 reserved_at_40[0x8];
4093 u8 qpn[0x18];
4094
4095 u8 reserved_at_60[0x20];
4096
4097 u8 opt_param_mask[0x20];
4098
4099 u8 reserved_at_a0[0x20];
4100
4101 struct mlx5_ifc_qpc_bits qpc;
4102
4103 u8 reserved_at_800[0x80];
4104 };
4105
4106 struct mlx5_ifc_sqd2rts_qp_out_bits {
4107 u8 status[0x8];
4108 u8 reserved_at_8[0x18];
4109
4110 u8 syndrome[0x20];
4111
4112 u8 reserved_at_40[0x40];
4113 };
4114
4115 struct mlx5_ifc_sqd2rts_qp_in_bits {
4116 u8 opcode[0x10];
4117 u8 uid[0x10];
4118
4119 u8 reserved_at_20[0x10];
4120 u8 op_mod[0x10];
4121
4122 u8 reserved_at_40[0x8];
4123 u8 qpn[0x18];
4124
4125 u8 reserved_at_60[0x20];
4126
4127 u8 opt_param_mask[0x20];
4128
4129 u8 reserved_at_a0[0x20];
4130
4131 struct mlx5_ifc_qpc_bits qpc;
4132
4133 u8 reserved_at_800[0x80];
4134 };
4135
4136 struct mlx5_ifc_set_roce_address_out_bits {
4137 u8 status[0x8];
4138 u8 reserved_at_8[0x18];
4139
4140 u8 syndrome[0x20];
4141
4142 u8 reserved_at_40[0x40];
4143 };
4144
4145 struct mlx5_ifc_set_roce_address_in_bits {
4146 u8 opcode[0x10];
4147 u8 reserved_at_10[0x10];
4148
4149 u8 reserved_at_20[0x10];
4150 u8 op_mod[0x10];
4151
4152 u8 roce_address_index[0x10];
4153 u8 reserved_at_50[0xc];
4154 u8 vhca_port_num[0x4];
4155
4156 u8 reserved_at_60[0x20];
4157
4158 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4159 };
4160
4161 struct mlx5_ifc_set_mad_demux_out_bits {
4162 u8 status[0x8];
4163 u8 reserved_at_8[0x18];
4164
4165 u8 syndrome[0x20];
4166
4167 u8 reserved_at_40[0x40];
4168 };
4169
4170 enum {
4171 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4172 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4173 };
4174
4175 struct mlx5_ifc_set_mad_demux_in_bits {
4176 u8 opcode[0x10];
4177 u8 reserved_at_10[0x10];
4178
4179 u8 reserved_at_20[0x10];
4180 u8 op_mod[0x10];
4181
4182 u8 reserved_at_40[0x20];
4183
4184 u8 reserved_at_60[0x6];
4185 u8 demux_mode[0x2];
4186 u8 reserved_at_68[0x18];
4187 };
4188
4189 struct mlx5_ifc_set_l2_table_entry_out_bits {
4190 u8 status[0x8];
4191 u8 reserved_at_8[0x18];
4192
4193 u8 syndrome[0x20];
4194
4195 u8 reserved_at_40[0x40];
4196 };
4197
4198 struct mlx5_ifc_set_l2_table_entry_in_bits {
4199 u8 opcode[0x10];
4200 u8 reserved_at_10[0x10];
4201
4202 u8 reserved_at_20[0x10];
4203 u8 op_mod[0x10];
4204
4205 u8 reserved_at_40[0x60];
4206
4207 u8 reserved_at_a0[0x8];
4208 u8 table_index[0x18];
4209
4210 u8 reserved_at_c0[0x20];
4211
4212 u8 reserved_at_e0[0x13];
4213 u8 vlan_valid[0x1];
4214 u8 vlan[0xc];
4215
4216 struct mlx5_ifc_mac_address_layout_bits mac_address;
4217
4218 u8 reserved_at_140[0xc0];
4219 };
4220
4221 struct mlx5_ifc_set_issi_out_bits {
4222 u8 status[0x8];
4223 u8 reserved_at_8[0x18];
4224
4225 u8 syndrome[0x20];
4226
4227 u8 reserved_at_40[0x40];
4228 };
4229
4230 struct mlx5_ifc_set_issi_in_bits {
4231 u8 opcode[0x10];
4232 u8 reserved_at_10[0x10];
4233
4234 u8 reserved_at_20[0x10];
4235 u8 op_mod[0x10];
4236
4237 u8 reserved_at_40[0x10];
4238 u8 current_issi[0x10];
4239
4240 u8 reserved_at_60[0x20];
4241 };
4242
4243 struct mlx5_ifc_set_hca_cap_out_bits {
4244 u8 status[0x8];
4245 u8 reserved_at_8[0x18];
4246
4247 u8 syndrome[0x20];
4248
4249 u8 reserved_at_40[0x40];
4250 };
4251
4252 struct mlx5_ifc_set_hca_cap_in_bits {
4253 u8 opcode[0x10];
4254 u8 reserved_at_10[0x10];
4255
4256 u8 reserved_at_20[0x10];
4257 u8 op_mod[0x10];
4258
4259 u8 other_function[0x1];
4260 u8 reserved_at_41[0xf];
4261 u8 function_id[0x10];
4262
4263 u8 reserved_at_60[0x20];
4264
4265 union mlx5_ifc_hca_cap_union_bits capability;
4266 };
4267
4268 enum {
4269 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4270 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4271 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4272 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4273 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4274 };
4275
4276 struct mlx5_ifc_set_fte_out_bits {
4277 u8 status[0x8];
4278 u8 reserved_at_8[0x18];
4279
4280 u8 syndrome[0x20];
4281
4282 u8 reserved_at_40[0x40];
4283 };
4284
4285 struct mlx5_ifc_set_fte_in_bits {
4286 u8 opcode[0x10];
4287 u8 reserved_at_10[0x10];
4288
4289 u8 reserved_at_20[0x10];
4290 u8 op_mod[0x10];
4291
4292 u8 other_vport[0x1];
4293 u8 reserved_at_41[0xf];
4294 u8 vport_number[0x10];
4295
4296 u8 reserved_at_60[0x20];
4297
4298 u8 table_type[0x8];
4299 u8 reserved_at_88[0x18];
4300
4301 u8 reserved_at_a0[0x8];
4302 u8 table_id[0x18];
4303
4304 u8 ignore_flow_level[0x1];
4305 u8 reserved_at_c1[0x17];
4306 u8 modify_enable_mask[0x8];
4307
4308 u8 reserved_at_e0[0x20];
4309
4310 u8 flow_index[0x20];
4311
4312 u8 reserved_at_120[0xe0];
4313
4314 struct mlx5_ifc_flow_context_bits flow_context;
4315 };
4316
4317 struct mlx5_ifc_rts2rts_qp_out_bits {
4318 u8 status[0x8];
4319 u8 reserved_at_8[0x18];
4320
4321 u8 syndrome[0x20];
4322
4323 u8 reserved_at_40[0x20];
4324 u8 ece[0x20];
4325 };
4326
4327 struct mlx5_ifc_rts2rts_qp_in_bits {
4328 u8 opcode[0x10];
4329 u8 uid[0x10];
4330
4331 u8 reserved_at_20[0x10];
4332 u8 op_mod[0x10];
4333
4334 u8 reserved_at_40[0x8];
4335 u8 qpn[0x18];
4336
4337 u8 reserved_at_60[0x20];
4338
4339 u8 opt_param_mask[0x20];
4340
4341 u8 ece[0x20];
4342
4343 struct mlx5_ifc_qpc_bits qpc;
4344
4345 u8 reserved_at_800[0x80];
4346 };
4347
4348 struct mlx5_ifc_rtr2rts_qp_out_bits {
4349 u8 status[0x8];
4350 u8 reserved_at_8[0x18];
4351
4352 u8 syndrome[0x20];
4353
4354 u8 reserved_at_40[0x20];
4355 u8 ece[0x20];
4356 };
4357
4358 struct mlx5_ifc_rtr2rts_qp_in_bits {
4359 u8 opcode[0x10];
4360 u8 uid[0x10];
4361
4362 u8 reserved_at_20[0x10];
4363 u8 op_mod[0x10];
4364
4365 u8 reserved_at_40[0x8];
4366 u8 qpn[0x18];
4367
4368 u8 reserved_at_60[0x20];
4369
4370 u8 opt_param_mask[0x20];
4371
4372 u8 ece[0x20];
4373
4374 struct mlx5_ifc_qpc_bits qpc;
4375
4376 u8 reserved_at_800[0x80];
4377 };
4378
4379 struct mlx5_ifc_rst2init_qp_out_bits {
4380 u8 status[0x8];
4381 u8 reserved_at_8[0x18];
4382
4383 u8 syndrome[0x20];
4384
4385 u8 reserved_at_40[0x20];
4386 u8 ece[0x20];
4387 };
4388
4389 struct mlx5_ifc_rst2init_qp_in_bits {
4390 u8 opcode[0x10];
4391 u8 uid[0x10];
4392
4393 u8 reserved_at_20[0x10];
4394 u8 op_mod[0x10];
4395
4396 u8 reserved_at_40[0x8];
4397 u8 qpn[0x18];
4398
4399 u8 reserved_at_60[0x20];
4400
4401 u8 opt_param_mask[0x20];
4402
4403 u8 ece[0x20];
4404
4405 struct mlx5_ifc_qpc_bits qpc;
4406
4407 u8 reserved_at_800[0x80];
4408 };
4409
4410 struct mlx5_ifc_query_xrq_out_bits {
4411 u8 status[0x8];
4412 u8 reserved_at_8[0x18];
4413
4414 u8 syndrome[0x20];
4415
4416 u8 reserved_at_40[0x40];
4417
4418 struct mlx5_ifc_xrqc_bits xrq_context;
4419 };
4420
4421 struct mlx5_ifc_query_xrq_in_bits {
4422 u8 opcode[0x10];
4423 u8 reserved_at_10[0x10];
4424
4425 u8 reserved_at_20[0x10];
4426 u8 op_mod[0x10];
4427
4428 u8 reserved_at_40[0x8];
4429 u8 xrqn[0x18];
4430
4431 u8 reserved_at_60[0x20];
4432 };
4433
4434 struct mlx5_ifc_query_xrc_srq_out_bits {
4435 u8 status[0x8];
4436 u8 reserved_at_8[0x18];
4437
4438 u8 syndrome[0x20];
4439
4440 u8 reserved_at_40[0x40];
4441
4442 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4443
4444 u8 reserved_at_280[0x600];
4445
4446 u8 pas[][0x40];
4447 };
4448
4449 struct mlx5_ifc_query_xrc_srq_in_bits {
4450 u8 opcode[0x10];
4451 u8 reserved_at_10[0x10];
4452
4453 u8 reserved_at_20[0x10];
4454 u8 op_mod[0x10];
4455
4456 u8 reserved_at_40[0x8];
4457 u8 xrc_srqn[0x18];
4458
4459 u8 reserved_at_60[0x20];
4460 };
4461
4462 enum {
4463 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4464 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4465 };
4466
4467 struct mlx5_ifc_query_vport_state_out_bits {
4468 u8 status[0x8];
4469 u8 reserved_at_8[0x18];
4470
4471 u8 syndrome[0x20];
4472
4473 u8 reserved_at_40[0x20];
4474
4475 u8 reserved_at_60[0x18];
4476 u8 admin_state[0x4];
4477 u8 state[0x4];
4478 };
4479
4480 enum {
4481 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4482 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4483 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
4484 };
4485
4486 struct mlx5_ifc_arm_monitor_counter_in_bits {
4487 u8 opcode[0x10];
4488 u8 uid[0x10];
4489
4490 u8 reserved_at_20[0x10];
4491 u8 op_mod[0x10];
4492
4493 u8 reserved_at_40[0x20];
4494
4495 u8 reserved_at_60[0x20];
4496 };
4497
4498 struct mlx5_ifc_arm_monitor_counter_out_bits {
4499 u8 status[0x8];
4500 u8 reserved_at_8[0x18];
4501
4502 u8 syndrome[0x20];
4503
4504 u8 reserved_at_40[0x40];
4505 };
4506
4507 enum {
4508 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4509 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4510 };
4511
4512 enum mlx5_monitor_counter_ppcnt {
4513 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4514 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4515 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4516 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4517 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4518 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4519 };
4520
4521 enum {
4522 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4523 };
4524
4525 struct mlx5_ifc_monitor_counter_output_bits {
4526 u8 reserved_at_0[0x4];
4527 u8 type[0x4];
4528 u8 reserved_at_8[0x8];
4529 u8 counter[0x10];
4530
4531 u8 counter_group_id[0x20];
4532 };
4533
4534 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4535 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4536 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4537 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4538
4539 struct mlx5_ifc_set_monitor_counter_in_bits {
4540 u8 opcode[0x10];
4541 u8 uid[0x10];
4542
4543 u8 reserved_at_20[0x10];
4544 u8 op_mod[0x10];
4545
4546 u8 reserved_at_40[0x10];
4547 u8 num_of_counters[0x10];
4548
4549 u8 reserved_at_60[0x20];
4550
4551 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4552 };
4553
4554 struct mlx5_ifc_set_monitor_counter_out_bits {
4555 u8 status[0x8];
4556 u8 reserved_at_8[0x18];
4557
4558 u8 syndrome[0x20];
4559
4560 u8 reserved_at_40[0x40];
4561 };
4562
4563 struct mlx5_ifc_query_vport_state_in_bits {
4564 u8 opcode[0x10];
4565 u8 reserved_at_10[0x10];
4566
4567 u8 reserved_at_20[0x10];
4568 u8 op_mod[0x10];
4569
4570 u8 other_vport[0x1];
4571 u8 reserved_at_41[0xf];
4572 u8 vport_number[0x10];
4573
4574 u8 reserved_at_60[0x20];
4575 };
4576
4577 struct mlx5_ifc_query_vnic_env_out_bits {
4578 u8 status[0x8];
4579 u8 reserved_at_8[0x18];
4580
4581 u8 syndrome[0x20];
4582
4583 u8 reserved_at_40[0x40];
4584
4585 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4586 };
4587
4588 enum {
4589 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4590 };
4591
4592 struct mlx5_ifc_query_vnic_env_in_bits {
4593 u8 opcode[0x10];
4594 u8 reserved_at_10[0x10];
4595
4596 u8 reserved_at_20[0x10];
4597 u8 op_mod[0x10];
4598
4599 u8 other_vport[0x1];
4600 u8 reserved_at_41[0xf];
4601 u8 vport_number[0x10];
4602
4603 u8 reserved_at_60[0x20];
4604 };
4605
4606 struct mlx5_ifc_query_vport_counter_out_bits {
4607 u8 status[0x8];
4608 u8 reserved_at_8[0x18];
4609
4610 u8 syndrome[0x20];
4611
4612 u8 reserved_at_40[0x40];
4613
4614 struct mlx5_ifc_traffic_counter_bits received_errors;
4615
4616 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4617
4618 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4619
4620 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4621
4622 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4623
4624 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4625
4626 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4627
4628 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4629
4630 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4631
4632 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4633
4634 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4635
4636 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4637
4638 u8 reserved_at_680[0xa00];
4639 };
4640
4641 enum {
4642 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4643 };
4644
4645 struct mlx5_ifc_query_vport_counter_in_bits {
4646 u8 opcode[0x10];
4647 u8 reserved_at_10[0x10];
4648
4649 u8 reserved_at_20[0x10];
4650 u8 op_mod[0x10];
4651
4652 u8 other_vport[0x1];
4653 u8 reserved_at_41[0xb];
4654 u8 port_num[0x4];
4655 u8 vport_number[0x10];
4656
4657 u8 reserved_at_60[0x60];
4658
4659 u8 clear[0x1];
4660 u8 reserved_at_c1[0x1f];
4661
4662 u8 reserved_at_e0[0x20];
4663 };
4664
4665 struct mlx5_ifc_query_tis_out_bits {
4666 u8 status[0x8];
4667 u8 reserved_at_8[0x18];
4668
4669 u8 syndrome[0x20];
4670
4671 u8 reserved_at_40[0x40];
4672
4673 struct mlx5_ifc_tisc_bits tis_context;
4674 };
4675
4676 struct mlx5_ifc_query_tis_in_bits {
4677 u8 opcode[0x10];
4678 u8 reserved_at_10[0x10];
4679
4680 u8 reserved_at_20[0x10];
4681 u8 op_mod[0x10];
4682
4683 u8 reserved_at_40[0x8];
4684 u8 tisn[0x18];
4685
4686 u8 reserved_at_60[0x20];
4687 };
4688
4689 struct mlx5_ifc_query_tir_out_bits {
4690 u8 status[0x8];
4691 u8 reserved_at_8[0x18];
4692
4693 u8 syndrome[0x20];
4694
4695 u8 reserved_at_40[0xc0];
4696
4697 struct mlx5_ifc_tirc_bits tir_context;
4698 };
4699
4700 struct mlx5_ifc_query_tir_in_bits {
4701 u8 opcode[0x10];
4702 u8 reserved_at_10[0x10];
4703
4704 u8 reserved_at_20[0x10];
4705 u8 op_mod[0x10];
4706
4707 u8 reserved_at_40[0x8];
4708 u8 tirn[0x18];
4709
4710 u8 reserved_at_60[0x20];
4711 };
4712
4713 struct mlx5_ifc_query_srq_out_bits {
4714 u8 status[0x8];
4715 u8 reserved_at_8[0x18];
4716
4717 u8 syndrome[0x20];
4718
4719 u8 reserved_at_40[0x40];
4720
4721 struct mlx5_ifc_srqc_bits srq_context_entry;
4722
4723 u8 reserved_at_280[0x600];
4724
4725 u8 pas[][0x40];
4726 };
4727
4728 struct mlx5_ifc_query_srq_in_bits {
4729 u8 opcode[0x10];
4730 u8 reserved_at_10[0x10];
4731
4732 u8 reserved_at_20[0x10];
4733 u8 op_mod[0x10];
4734
4735 u8 reserved_at_40[0x8];
4736 u8 srqn[0x18];
4737
4738 u8 reserved_at_60[0x20];
4739 };
4740
4741 struct mlx5_ifc_query_sq_out_bits {
4742 u8 status[0x8];
4743 u8 reserved_at_8[0x18];
4744
4745 u8 syndrome[0x20];
4746
4747 u8 reserved_at_40[0xc0];
4748
4749 struct mlx5_ifc_sqc_bits sq_context;
4750 };
4751
4752 struct mlx5_ifc_query_sq_in_bits {
4753 u8 opcode[0x10];
4754 u8 reserved_at_10[0x10];
4755
4756 u8 reserved_at_20[0x10];
4757 u8 op_mod[0x10];
4758
4759 u8 reserved_at_40[0x8];
4760 u8 sqn[0x18];
4761
4762 u8 reserved_at_60[0x20];
4763 };
4764
4765 struct mlx5_ifc_query_special_contexts_out_bits {
4766 u8 status[0x8];
4767 u8 reserved_at_8[0x18];
4768
4769 u8 syndrome[0x20];
4770
4771 u8 dump_fill_mkey[0x20];
4772
4773 u8 resd_lkey[0x20];
4774
4775 u8 null_mkey[0x20];
4776
4777 u8 reserved_at_a0[0x60];
4778 };
4779
4780 struct mlx5_ifc_query_special_contexts_in_bits {
4781 u8 opcode[0x10];
4782 u8 reserved_at_10[0x10];
4783
4784 u8 reserved_at_20[0x10];
4785 u8 op_mod[0x10];
4786
4787 u8 reserved_at_40[0x40];
4788 };
4789
4790 struct mlx5_ifc_query_scheduling_element_out_bits {
4791 u8 opcode[0x10];
4792 u8 reserved_at_10[0x10];
4793
4794 u8 reserved_at_20[0x10];
4795 u8 op_mod[0x10];
4796
4797 u8 reserved_at_40[0xc0];
4798
4799 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4800
4801 u8 reserved_at_300[0x100];
4802 };
4803
4804 enum {
4805 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4806 };
4807
4808 struct mlx5_ifc_query_scheduling_element_in_bits {
4809 u8 opcode[0x10];
4810 u8 reserved_at_10[0x10];
4811
4812 u8 reserved_at_20[0x10];
4813 u8 op_mod[0x10];
4814
4815 u8 scheduling_hierarchy[0x8];
4816 u8 reserved_at_48[0x18];
4817
4818 u8 scheduling_element_id[0x20];
4819
4820 u8 reserved_at_80[0x180];
4821 };
4822
4823 struct mlx5_ifc_query_rqt_out_bits {
4824 u8 status[0x8];
4825 u8 reserved_at_8[0x18];
4826
4827 u8 syndrome[0x20];
4828
4829 u8 reserved_at_40[0xc0];
4830
4831 struct mlx5_ifc_rqtc_bits rqt_context;
4832 };
4833
4834 struct mlx5_ifc_query_rqt_in_bits {
4835 u8 opcode[0x10];
4836 u8 reserved_at_10[0x10];
4837
4838 u8 reserved_at_20[0x10];
4839 u8 op_mod[0x10];
4840
4841 u8 reserved_at_40[0x8];
4842 u8 rqtn[0x18];
4843
4844 u8 reserved_at_60[0x20];
4845 };
4846
4847 struct mlx5_ifc_query_rq_out_bits {
4848 u8 status[0x8];
4849 u8 reserved_at_8[0x18];
4850
4851 u8 syndrome[0x20];
4852
4853 u8 reserved_at_40[0xc0];
4854
4855 struct mlx5_ifc_rqc_bits rq_context;
4856 };
4857
4858 struct mlx5_ifc_query_rq_in_bits {
4859 u8 opcode[0x10];
4860 u8 reserved_at_10[0x10];
4861
4862 u8 reserved_at_20[0x10];
4863 u8 op_mod[0x10];
4864
4865 u8 reserved_at_40[0x8];
4866 u8 rqn[0x18];
4867
4868 u8 reserved_at_60[0x20];
4869 };
4870
4871 struct mlx5_ifc_query_roce_address_out_bits {
4872 u8 status[0x8];
4873 u8 reserved_at_8[0x18];
4874
4875 u8 syndrome[0x20];
4876
4877 u8 reserved_at_40[0x40];
4878
4879 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4880 };
4881
4882 struct mlx5_ifc_query_roce_address_in_bits {
4883 u8 opcode[0x10];
4884 u8 reserved_at_10[0x10];
4885
4886 u8 reserved_at_20[0x10];
4887 u8 op_mod[0x10];
4888
4889 u8 roce_address_index[0x10];
4890 u8 reserved_at_50[0xc];
4891 u8 vhca_port_num[0x4];
4892
4893 u8 reserved_at_60[0x20];
4894 };
4895
4896 struct mlx5_ifc_query_rmp_out_bits {
4897 u8 status[0x8];
4898 u8 reserved_at_8[0x18];
4899
4900 u8 syndrome[0x20];
4901
4902 u8 reserved_at_40[0xc0];
4903
4904 struct mlx5_ifc_rmpc_bits rmp_context;
4905 };
4906
4907 struct mlx5_ifc_query_rmp_in_bits {
4908 u8 opcode[0x10];
4909 u8 reserved_at_10[0x10];
4910
4911 u8 reserved_at_20[0x10];
4912 u8 op_mod[0x10];
4913
4914 u8 reserved_at_40[0x8];
4915 u8 rmpn[0x18];
4916
4917 u8 reserved_at_60[0x20];
4918 };
4919
4920 struct mlx5_ifc_query_qp_out_bits {
4921 u8 status[0x8];
4922 u8 reserved_at_8[0x18];
4923
4924 u8 syndrome[0x20];
4925
4926 u8 reserved_at_40[0x20];
4927 u8 ece[0x20];
4928
4929 u8 opt_param_mask[0x20];
4930
4931 u8 reserved_at_a0[0x20];
4932
4933 struct mlx5_ifc_qpc_bits qpc;
4934
4935 u8 reserved_at_800[0x80];
4936
4937 u8 pas[][0x40];
4938 };
4939
4940 struct mlx5_ifc_query_qp_in_bits {
4941 u8 opcode[0x10];
4942 u8 reserved_at_10[0x10];
4943
4944 u8 reserved_at_20[0x10];
4945 u8 op_mod[0x10];
4946
4947 u8 reserved_at_40[0x8];
4948 u8 qpn[0x18];
4949
4950 u8 reserved_at_60[0x20];
4951 };
4952
4953 struct mlx5_ifc_query_q_counter_out_bits {
4954 u8 status[0x8];
4955 u8 reserved_at_8[0x18];
4956
4957 u8 syndrome[0x20];
4958
4959 u8 reserved_at_40[0x40];
4960
4961 u8 rx_write_requests[0x20];
4962
4963 u8 reserved_at_a0[0x20];
4964
4965 u8 rx_read_requests[0x20];
4966
4967 u8 reserved_at_e0[0x20];
4968
4969 u8 rx_atomic_requests[0x20];
4970
4971 u8 reserved_at_120[0x20];
4972
4973 u8 rx_dct_connect[0x20];
4974
4975 u8 reserved_at_160[0x20];
4976
4977 u8 out_of_buffer[0x20];
4978
4979 u8 reserved_at_1a0[0x20];
4980
4981 u8 out_of_sequence[0x20];
4982
4983 u8 reserved_at_1e0[0x20];
4984
4985 u8 duplicate_request[0x20];
4986
4987 u8 reserved_at_220[0x20];
4988
4989 u8 rnr_nak_retry_err[0x20];
4990
4991 u8 reserved_at_260[0x20];
4992
4993 u8 packet_seq_err[0x20];
4994
4995 u8 reserved_at_2a0[0x20];
4996
4997 u8 implied_nak_seq_err[0x20];
4998
4999 u8 reserved_at_2e0[0x20];
5000
5001 u8 local_ack_timeout_err[0x20];
5002
5003 u8 reserved_at_320[0xa0];
5004
5005 u8 resp_local_length_error[0x20];
5006
5007 u8 req_local_length_error[0x20];
5008
5009 u8 resp_local_qp_error[0x20];
5010
5011 u8 local_operation_error[0x20];
5012
5013 u8 resp_local_protection[0x20];
5014
5015 u8 req_local_protection[0x20];
5016
5017 u8 resp_cqe_error[0x20];
5018
5019 u8 req_cqe_error[0x20];
5020
5021 u8 req_mw_binding[0x20];
5022
5023 u8 req_bad_response[0x20];
5024
5025 u8 req_remote_invalid_request[0x20];
5026
5027 u8 resp_remote_invalid_request[0x20];
5028
5029 u8 req_remote_access_errors[0x20];
5030
5031 u8 resp_remote_access_errors[0x20];
5032
5033 u8 req_remote_operation_errors[0x20];
5034
5035 u8 req_transport_retries_exceeded[0x20];
5036
5037 u8 cq_overflow[0x20];
5038
5039 u8 resp_cqe_flush_error[0x20];
5040
5041 u8 req_cqe_flush_error[0x20];
5042
5043 u8 reserved_at_620[0x20];
5044
5045 u8 roce_adp_retrans[0x20];
5046
5047 u8 roce_adp_retrans_to[0x20];
5048
5049 u8 roce_slow_restart[0x20];
5050
5051 u8 roce_slow_restart_cnps[0x20];
5052
5053 u8 roce_slow_restart_trans[0x20];
5054
5055 u8 reserved_at_6e0[0x120];
5056 };
5057
5058 struct mlx5_ifc_query_q_counter_in_bits {
5059 u8 opcode[0x10];
5060 u8 reserved_at_10[0x10];
5061
5062 u8 reserved_at_20[0x10];
5063 u8 op_mod[0x10];
5064
5065 u8 reserved_at_40[0x80];
5066
5067 u8 clear[0x1];
5068 u8 reserved_at_c1[0x1f];
5069
5070 u8 reserved_at_e0[0x18];
5071 u8 counter_set_id[0x8];
5072 };
5073
5074 struct mlx5_ifc_query_pages_out_bits {
5075 u8 status[0x8];
5076 u8 reserved_at_8[0x18];
5077
5078 u8 syndrome[0x20];
5079
5080 u8 embedded_cpu_function[0x1];
5081 u8 reserved_at_41[0xf];
5082 u8 function_id[0x10];
5083
5084 u8 num_pages[0x20];
5085 };
5086
5087 enum {
5088 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5089 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5090 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5091 };
5092
5093 struct mlx5_ifc_query_pages_in_bits {
5094 u8 opcode[0x10];
5095 u8 reserved_at_10[0x10];
5096
5097 u8 reserved_at_20[0x10];
5098 u8 op_mod[0x10];
5099
5100 u8 embedded_cpu_function[0x1];
5101 u8 reserved_at_41[0xf];
5102 u8 function_id[0x10];
5103
5104 u8 reserved_at_60[0x20];
5105 };
5106
5107 struct mlx5_ifc_query_nic_vport_context_out_bits {
5108 u8 status[0x8];
5109 u8 reserved_at_8[0x18];
5110
5111 u8 syndrome[0x20];
5112
5113 u8 reserved_at_40[0x40];
5114
5115 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5116 };
5117
5118 struct mlx5_ifc_query_nic_vport_context_in_bits {
5119 u8 opcode[0x10];
5120 u8 reserved_at_10[0x10];
5121
5122 u8 reserved_at_20[0x10];
5123 u8 op_mod[0x10];
5124
5125 u8 other_vport[0x1];
5126 u8 reserved_at_41[0xf];
5127 u8 vport_number[0x10];
5128
5129 u8 reserved_at_60[0x5];
5130 u8 allowed_list_type[0x3];
5131 u8 reserved_at_68[0x18];
5132 };
5133
5134 struct mlx5_ifc_query_mkey_out_bits {
5135 u8 status[0x8];
5136 u8 reserved_at_8[0x18];
5137
5138 u8 syndrome[0x20];
5139
5140 u8 reserved_at_40[0x40];
5141
5142 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5143
5144 u8 reserved_at_280[0x600];
5145
5146 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5147
5148 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5149 };
5150
5151 struct mlx5_ifc_query_mkey_in_bits {
5152 u8 opcode[0x10];
5153 u8 reserved_at_10[0x10];
5154
5155 u8 reserved_at_20[0x10];
5156 u8 op_mod[0x10];
5157
5158 u8 reserved_at_40[0x8];
5159 u8 mkey_index[0x18];
5160
5161 u8 pg_access[0x1];
5162 u8 reserved_at_61[0x1f];
5163 };
5164
5165 struct mlx5_ifc_query_mad_demux_out_bits {
5166 u8 status[0x8];
5167 u8 reserved_at_8[0x18];
5168
5169 u8 syndrome[0x20];
5170
5171 u8 reserved_at_40[0x40];
5172
5173 u8 mad_dumux_parameters_block[0x20];
5174 };
5175
5176 struct mlx5_ifc_query_mad_demux_in_bits {
5177 u8 opcode[0x10];
5178 u8 reserved_at_10[0x10];
5179
5180 u8 reserved_at_20[0x10];
5181 u8 op_mod[0x10];
5182
5183 u8 reserved_at_40[0x40];
5184 };
5185
5186 struct mlx5_ifc_query_l2_table_entry_out_bits {
5187 u8 status[0x8];
5188 u8 reserved_at_8[0x18];
5189
5190 u8 syndrome[0x20];
5191
5192 u8 reserved_at_40[0xa0];
5193
5194 u8 reserved_at_e0[0x13];
5195 u8 vlan_valid[0x1];
5196 u8 vlan[0xc];
5197
5198 struct mlx5_ifc_mac_address_layout_bits mac_address;
5199
5200 u8 reserved_at_140[0xc0];
5201 };
5202
5203 struct mlx5_ifc_query_l2_table_entry_in_bits {
5204 u8 opcode[0x10];
5205 u8 reserved_at_10[0x10];
5206
5207 u8 reserved_at_20[0x10];
5208 u8 op_mod[0x10];
5209
5210 u8 reserved_at_40[0x60];
5211
5212 u8 reserved_at_a0[0x8];
5213 u8 table_index[0x18];
5214
5215 u8 reserved_at_c0[0x140];
5216 };
5217
5218 struct mlx5_ifc_query_issi_out_bits {
5219 u8 status[0x8];
5220 u8 reserved_at_8[0x18];
5221
5222 u8 syndrome[0x20];
5223
5224 u8 reserved_at_40[0x10];
5225 u8 current_issi[0x10];
5226
5227 u8 reserved_at_60[0xa0];
5228
5229 u8 reserved_at_100[76][0x8];
5230 u8 supported_issi_dw0[0x20];
5231 };
5232
5233 struct mlx5_ifc_query_issi_in_bits {
5234 u8 opcode[0x10];
5235 u8 reserved_at_10[0x10];
5236
5237 u8 reserved_at_20[0x10];
5238 u8 op_mod[0x10];
5239
5240 u8 reserved_at_40[0x40];
5241 };
5242
5243 struct mlx5_ifc_set_driver_version_out_bits {
5244 u8 status[0x8];
5245 u8 reserved_0[0x18];
5246
5247 u8 syndrome[0x20];
5248 u8 reserved_1[0x40];
5249 };
5250
5251 struct mlx5_ifc_set_driver_version_in_bits {
5252 u8 opcode[0x10];
5253 u8 reserved_0[0x10];
5254
5255 u8 reserved_1[0x10];
5256 u8 op_mod[0x10];
5257
5258 u8 reserved_2[0x40];
5259 u8 driver_version[64][0x8];
5260 };
5261
5262 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5263 u8 status[0x8];
5264 u8 reserved_at_8[0x18];
5265
5266 u8 syndrome[0x20];
5267
5268 u8 reserved_at_40[0x40];
5269
5270 struct mlx5_ifc_pkey_bits pkey[];
5271 };
5272
5273 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5274 u8 opcode[0x10];
5275 u8 reserved_at_10[0x10];
5276
5277 u8 reserved_at_20[0x10];
5278 u8 op_mod[0x10];
5279
5280 u8 other_vport[0x1];
5281 u8 reserved_at_41[0xb];
5282 u8 port_num[0x4];
5283 u8 vport_number[0x10];
5284
5285 u8 reserved_at_60[0x10];
5286 u8 pkey_index[0x10];
5287 };
5288
5289 enum {
5290 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5291 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5292 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5293 };
5294
5295 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5296 u8 status[0x8];
5297 u8 reserved_at_8[0x18];
5298
5299 u8 syndrome[0x20];
5300
5301 u8 reserved_at_40[0x20];
5302
5303 u8 gids_num[0x10];
5304 u8 reserved_at_70[0x10];
5305
5306 struct mlx5_ifc_array128_auto_bits gid[];
5307 };
5308
5309 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5310 u8 opcode[0x10];
5311 u8 reserved_at_10[0x10];
5312
5313 u8 reserved_at_20[0x10];
5314 u8 op_mod[0x10];
5315
5316 u8 other_vport[0x1];
5317 u8 reserved_at_41[0xb];
5318 u8 port_num[0x4];
5319 u8 vport_number[0x10];
5320
5321 u8 reserved_at_60[0x10];
5322 u8 gid_index[0x10];
5323 };
5324
5325 struct mlx5_ifc_query_hca_vport_context_out_bits {
5326 u8 status[0x8];
5327 u8 reserved_at_8[0x18];
5328
5329 u8 syndrome[0x20];
5330
5331 u8 reserved_at_40[0x40];
5332
5333 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5334 };
5335
5336 struct mlx5_ifc_query_hca_vport_context_in_bits {
5337 u8 opcode[0x10];
5338 u8 reserved_at_10[0x10];
5339
5340 u8 reserved_at_20[0x10];
5341 u8 op_mod[0x10];
5342
5343 u8 other_vport[0x1];
5344 u8 reserved_at_41[0xb];
5345 u8 port_num[0x4];
5346 u8 vport_number[0x10];
5347
5348 u8 reserved_at_60[0x20];
5349 };
5350
5351 struct mlx5_ifc_query_hca_cap_out_bits {
5352 u8 status[0x8];
5353 u8 reserved_at_8[0x18];
5354
5355 u8 syndrome[0x20];
5356
5357 u8 reserved_at_40[0x40];
5358
5359 union mlx5_ifc_hca_cap_union_bits capability;
5360 };
5361
5362 struct mlx5_ifc_query_hca_cap_in_bits {
5363 u8 opcode[0x10];
5364 u8 reserved_at_10[0x10];
5365
5366 u8 reserved_at_20[0x10];
5367 u8 op_mod[0x10];
5368
5369 u8 other_function[0x1];
5370 u8 reserved_at_41[0xf];
5371 u8 function_id[0x10];
5372
5373 u8 reserved_at_60[0x20];
5374 };
5375
5376 struct mlx5_ifc_other_hca_cap_bits {
5377 u8 roce[0x1];
5378 u8 reserved_at_1[0x27f];
5379 };
5380
5381 struct mlx5_ifc_query_other_hca_cap_out_bits {
5382 u8 status[0x8];
5383 u8 reserved_at_8[0x18];
5384
5385 u8 syndrome[0x20];
5386
5387 u8 reserved_at_40[0x40];
5388
5389 struct mlx5_ifc_other_hca_cap_bits other_capability;
5390 };
5391
5392 struct mlx5_ifc_query_other_hca_cap_in_bits {
5393 u8 opcode[0x10];
5394 u8 reserved_at_10[0x10];
5395
5396 u8 reserved_at_20[0x10];
5397 u8 op_mod[0x10];
5398
5399 u8 reserved_at_40[0x10];
5400 u8 function_id[0x10];
5401
5402 u8 reserved_at_60[0x20];
5403 };
5404
5405 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5406 u8 status[0x8];
5407 u8 reserved_at_8[0x18];
5408
5409 u8 syndrome[0x20];
5410
5411 u8 reserved_at_40[0x40];
5412 };
5413
5414 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5415 u8 opcode[0x10];
5416 u8 reserved_at_10[0x10];
5417
5418 u8 reserved_at_20[0x10];
5419 u8 op_mod[0x10];
5420
5421 u8 reserved_at_40[0x10];
5422 u8 function_id[0x10];
5423 u8 field_select[0x20];
5424
5425 struct mlx5_ifc_other_hca_cap_bits other_capability;
5426 };
5427
5428 struct mlx5_ifc_flow_table_context_bits {
5429 u8 reformat_en[0x1];
5430 u8 decap_en[0x1];
5431 u8 sw_owner[0x1];
5432 u8 termination_table[0x1];
5433 u8 table_miss_action[0x4];
5434 u8 level[0x8];
5435 u8 reserved_at_10[0x8];
5436 u8 log_size[0x8];
5437
5438 u8 reserved_at_20[0x8];
5439 u8 table_miss_id[0x18];
5440
5441 u8 reserved_at_40[0x8];
5442 u8 lag_master_next_table_id[0x18];
5443
5444 u8 reserved_at_60[0x60];
5445
5446 u8 sw_owner_icm_root_1[0x40];
5447
5448 u8 sw_owner_icm_root_0[0x40];
5449
5450 };
5451
5452 struct mlx5_ifc_query_flow_table_out_bits {
5453 u8 status[0x8];
5454 u8 reserved_at_8[0x18];
5455
5456 u8 syndrome[0x20];
5457
5458 u8 reserved_at_40[0x80];
5459
5460 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5461 };
5462
5463 struct mlx5_ifc_query_flow_table_in_bits {
5464 u8 opcode[0x10];
5465 u8 reserved_at_10[0x10];
5466
5467 u8 reserved_at_20[0x10];
5468 u8 op_mod[0x10];
5469
5470 u8 reserved_at_40[0x40];
5471
5472 u8 table_type[0x8];
5473 u8 reserved_at_88[0x18];
5474
5475 u8 reserved_at_a0[0x8];
5476 u8 table_id[0x18];
5477
5478 u8 reserved_at_c0[0x140];
5479 };
5480
5481 struct mlx5_ifc_query_fte_out_bits {
5482 u8 status[0x8];
5483 u8 reserved_at_8[0x18];
5484
5485 u8 syndrome[0x20];
5486
5487 u8 reserved_at_40[0x1c0];
5488
5489 struct mlx5_ifc_flow_context_bits flow_context;
5490 };
5491
5492 struct mlx5_ifc_query_fte_in_bits {
5493 u8 opcode[0x10];
5494 u8 reserved_at_10[0x10];
5495
5496 u8 reserved_at_20[0x10];
5497 u8 op_mod[0x10];
5498
5499 u8 reserved_at_40[0x40];
5500
5501 u8 table_type[0x8];
5502 u8 reserved_at_88[0x18];
5503
5504 u8 reserved_at_a0[0x8];
5505 u8 table_id[0x18];
5506
5507 u8 reserved_at_c0[0x40];
5508
5509 u8 flow_index[0x20];
5510
5511 u8 reserved_at_120[0xe0];
5512 };
5513
5514 enum {
5515 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5516 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5517 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5518 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5519 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5520 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
5521 };
5522
5523 struct mlx5_ifc_query_flow_group_out_bits {
5524 u8 status[0x8];
5525 u8 reserved_at_8[0x18];
5526
5527 u8 syndrome[0x20];
5528
5529 u8 reserved_at_40[0xa0];
5530
5531 u8 start_flow_index[0x20];
5532
5533 u8 reserved_at_100[0x20];
5534
5535 u8 end_flow_index[0x20];
5536
5537 u8 reserved_at_140[0xa0];
5538
5539 u8 reserved_at_1e0[0x18];
5540 u8 match_criteria_enable[0x8];
5541
5542 struct mlx5_ifc_fte_match_param_bits match_criteria;
5543
5544 u8 reserved_at_1200[0xe00];
5545 };
5546
5547 struct mlx5_ifc_query_flow_group_in_bits {
5548 u8 opcode[0x10];
5549 u8 reserved_at_10[0x10];
5550
5551 u8 reserved_at_20[0x10];
5552 u8 op_mod[0x10];
5553
5554 u8 reserved_at_40[0x40];
5555
5556 u8 table_type[0x8];
5557 u8 reserved_at_88[0x18];
5558
5559 u8 reserved_at_a0[0x8];
5560 u8 table_id[0x18];
5561
5562 u8 group_id[0x20];
5563
5564 u8 reserved_at_e0[0x120];
5565 };
5566
5567 struct mlx5_ifc_query_flow_counter_out_bits {
5568 u8 status[0x8];
5569 u8 reserved_at_8[0x18];
5570
5571 u8 syndrome[0x20];
5572
5573 u8 reserved_at_40[0x40];
5574
5575 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5576 };
5577
5578 struct mlx5_ifc_query_flow_counter_in_bits {
5579 u8 opcode[0x10];
5580 u8 reserved_at_10[0x10];
5581
5582 u8 reserved_at_20[0x10];
5583 u8 op_mod[0x10];
5584
5585 u8 reserved_at_40[0x80];
5586
5587 u8 clear[0x1];
5588 u8 reserved_at_c1[0xf];
5589 u8 num_of_counters[0x10];
5590
5591 u8 flow_counter_id[0x20];
5592 };
5593
5594 struct mlx5_ifc_query_esw_vport_context_out_bits {
5595 u8 status[0x8];
5596 u8 reserved_at_8[0x18];
5597
5598 u8 syndrome[0x20];
5599
5600 u8 reserved_at_40[0x40];
5601
5602 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5603 };
5604
5605 struct mlx5_ifc_query_esw_vport_context_in_bits {
5606 u8 opcode[0x10];
5607 u8 reserved_at_10[0x10];
5608
5609 u8 reserved_at_20[0x10];
5610 u8 op_mod[0x10];
5611
5612 u8 other_vport[0x1];
5613 u8 reserved_at_41[0xf];
5614 u8 vport_number[0x10];
5615
5616 u8 reserved_at_60[0x20];
5617 };
5618
5619 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5620 u8 status[0x8];
5621 u8 reserved_at_8[0x18];
5622
5623 u8 syndrome[0x20];
5624
5625 u8 reserved_at_40[0x40];
5626 };
5627
5628 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5629 u8 reserved_at_0[0x1b];
5630 u8 fdb_to_vport_reg_c_id[0x1];
5631 u8 vport_cvlan_insert[0x1];
5632 u8 vport_svlan_insert[0x1];
5633 u8 vport_cvlan_strip[0x1];
5634 u8 vport_svlan_strip[0x1];
5635 };
5636
5637 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5638 u8 opcode[0x10];
5639 u8 reserved_at_10[0x10];
5640
5641 u8 reserved_at_20[0x10];
5642 u8 op_mod[0x10];
5643
5644 u8 other_vport[0x1];
5645 u8 reserved_at_41[0xf];
5646 u8 vport_number[0x10];
5647
5648 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5649
5650 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5651 };
5652
5653 struct mlx5_ifc_query_eq_out_bits {
5654 u8 status[0x8];
5655 u8 reserved_at_8[0x18];
5656
5657 u8 syndrome[0x20];
5658
5659 u8 reserved_at_40[0x40];
5660
5661 struct mlx5_ifc_eqc_bits eq_context_entry;
5662
5663 u8 reserved_at_280[0x40];
5664
5665 u8 event_bitmask[0x40];
5666
5667 u8 reserved_at_300[0x580];
5668
5669 u8 pas[][0x40];
5670 };
5671
5672 struct mlx5_ifc_query_eq_in_bits {
5673 u8 opcode[0x10];
5674 u8 reserved_at_10[0x10];
5675
5676 u8 reserved_at_20[0x10];
5677 u8 op_mod[0x10];
5678
5679 u8 reserved_at_40[0x18];
5680 u8 eq_number[0x8];
5681
5682 u8 reserved_at_60[0x20];
5683 };
5684
5685 struct mlx5_ifc_packet_reformat_context_in_bits {
5686 u8 reserved_at_0[0x5];
5687 u8 reformat_type[0x3];
5688 u8 reserved_at_8[0xe];
5689 u8 reformat_data_size[0xa];
5690
5691 u8 reserved_at_20[0x10];
5692 u8 reformat_data[2][0x8];
5693
5694 u8 more_reformat_data[][0x8];
5695 };
5696
5697 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5698 u8 status[0x8];
5699 u8 reserved_at_8[0x18];
5700
5701 u8 syndrome[0x20];
5702
5703 u8 reserved_at_40[0xa0];
5704
5705 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5706 };
5707
5708 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5709 u8 opcode[0x10];
5710 u8 reserved_at_10[0x10];
5711
5712 u8 reserved_at_20[0x10];
5713 u8 op_mod[0x10];
5714
5715 u8 packet_reformat_id[0x20];
5716
5717 u8 reserved_at_60[0xa0];
5718 };
5719
5720 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5721 u8 status[0x8];
5722 u8 reserved_at_8[0x18];
5723
5724 u8 syndrome[0x20];
5725
5726 u8 packet_reformat_id[0x20];
5727
5728 u8 reserved_at_60[0x20];
5729 };
5730
5731 enum mlx5_reformat_ctx_type {
5732 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5733 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5734 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5735 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5736 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5737 };
5738
5739 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5740 u8 opcode[0x10];
5741 u8 reserved_at_10[0x10];
5742
5743 u8 reserved_at_20[0x10];
5744 u8 op_mod[0x10];
5745
5746 u8 reserved_at_40[0xa0];
5747
5748 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5749 };
5750
5751 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5752 u8 status[0x8];
5753 u8 reserved_at_8[0x18];
5754
5755 u8 syndrome[0x20];
5756
5757 u8 reserved_at_40[0x40];
5758 };
5759
5760 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5761 u8 opcode[0x10];
5762 u8 reserved_at_10[0x10];
5763
5764 u8 reserved_20[0x10];
5765 u8 op_mod[0x10];
5766
5767 u8 packet_reformat_id[0x20];
5768
5769 u8 reserved_60[0x20];
5770 };
5771
5772 struct mlx5_ifc_set_action_in_bits {
5773 u8 action_type[0x4];
5774 u8 field[0xc];
5775 u8 reserved_at_10[0x3];
5776 u8 offset[0x5];
5777 u8 reserved_at_18[0x3];
5778 u8 length[0x5];
5779
5780 u8 data[0x20];
5781 };
5782
5783 struct mlx5_ifc_add_action_in_bits {
5784 u8 action_type[0x4];
5785 u8 field[0xc];
5786 u8 reserved_at_10[0x10];
5787
5788 u8 data[0x20];
5789 };
5790
5791 struct mlx5_ifc_copy_action_in_bits {
5792 u8 action_type[0x4];
5793 u8 src_field[0xc];
5794 u8 reserved_at_10[0x3];
5795 u8 src_offset[0x5];
5796 u8 reserved_at_18[0x3];
5797 u8 length[0x5];
5798
5799 u8 reserved_at_20[0x4];
5800 u8 dst_field[0xc];
5801 u8 reserved_at_30[0x3];
5802 u8 dst_offset[0x5];
5803 u8 reserved_at_38[0x8];
5804 };
5805
5806 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5807 struct mlx5_ifc_set_action_in_bits set_action_in;
5808 struct mlx5_ifc_add_action_in_bits add_action_in;
5809 struct mlx5_ifc_copy_action_in_bits copy_action_in;
5810 u8 reserved_at_0[0x40];
5811 };
5812
5813 enum {
5814 MLX5_ACTION_TYPE_SET = 0x1,
5815 MLX5_ACTION_TYPE_ADD = 0x2,
5816 MLX5_ACTION_TYPE_COPY = 0x3,
5817 };
5818
5819 enum {
5820 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5821 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5822 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5823 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5824 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5825 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5826 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5827 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5828 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5829 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5830 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5831 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5832 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5833 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5834 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5835 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5836 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5837 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5838 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5839 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5840 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5841 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5842 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5843 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5844 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5845 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5846 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5847 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5848 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5849 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5850 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5851 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5852 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5853 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
5854 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5855 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5856 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
5857 };
5858
5859 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5860 u8 status[0x8];
5861 u8 reserved_at_8[0x18];
5862
5863 u8 syndrome[0x20];
5864
5865 u8 modify_header_id[0x20];
5866
5867 u8 reserved_at_60[0x20];
5868 };
5869
5870 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5871 u8 opcode[0x10];
5872 u8 reserved_at_10[0x10];
5873
5874 u8 reserved_at_20[0x10];
5875 u8 op_mod[0x10];
5876
5877 u8 reserved_at_40[0x20];
5878
5879 u8 table_type[0x8];
5880 u8 reserved_at_68[0x10];
5881 u8 num_of_actions[0x8];
5882
5883 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
5884 };
5885
5886 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5887 u8 status[0x8];
5888 u8 reserved_at_8[0x18];
5889
5890 u8 syndrome[0x20];
5891
5892 u8 reserved_at_40[0x40];
5893 };
5894
5895 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5896 u8 opcode[0x10];
5897 u8 reserved_at_10[0x10];
5898
5899 u8 reserved_at_20[0x10];
5900 u8 op_mod[0x10];
5901
5902 u8 modify_header_id[0x20];
5903
5904 u8 reserved_at_60[0x20];
5905 };
5906
5907 struct mlx5_ifc_query_dct_out_bits {
5908 u8 status[0x8];
5909 u8 reserved_at_8[0x18];
5910
5911 u8 syndrome[0x20];
5912
5913 u8 reserved_at_40[0x40];
5914
5915 struct mlx5_ifc_dctc_bits dct_context_entry;
5916
5917 u8 reserved_at_280[0x180];
5918 };
5919
5920 struct mlx5_ifc_query_dct_in_bits {
5921 u8 opcode[0x10];
5922 u8 reserved_at_10[0x10];
5923
5924 u8 reserved_at_20[0x10];
5925 u8 op_mod[0x10];
5926
5927 u8 reserved_at_40[0x8];
5928 u8 dctn[0x18];
5929
5930 u8 reserved_at_60[0x20];
5931 };
5932
5933 struct mlx5_ifc_query_cq_out_bits {
5934 u8 status[0x8];
5935 u8 reserved_at_8[0x18];
5936
5937 u8 syndrome[0x20];
5938
5939 u8 reserved_at_40[0x40];
5940
5941 struct mlx5_ifc_cqc_bits cq_context;
5942
5943 u8 reserved_at_280[0x600];
5944
5945 u8 pas[][0x40];
5946 };
5947
5948 struct mlx5_ifc_query_cq_in_bits {
5949 u8 opcode[0x10];
5950 u8 reserved_at_10[0x10];
5951
5952 u8 reserved_at_20[0x10];
5953 u8 op_mod[0x10];
5954
5955 u8 reserved_at_40[0x8];
5956 u8 cqn[0x18];
5957
5958 u8 reserved_at_60[0x20];
5959 };
5960
5961 struct mlx5_ifc_query_cong_status_out_bits {
5962 u8 status[0x8];
5963 u8 reserved_at_8[0x18];
5964
5965 u8 syndrome[0x20];
5966
5967 u8 reserved_at_40[0x20];
5968
5969 u8 enable[0x1];
5970 u8 tag_enable[0x1];
5971 u8 reserved_at_62[0x1e];
5972 };
5973
5974 struct mlx5_ifc_query_cong_status_in_bits {
5975 u8 opcode[0x10];
5976 u8 reserved_at_10[0x10];
5977
5978 u8 reserved_at_20[0x10];
5979 u8 op_mod[0x10];
5980
5981 u8 reserved_at_40[0x18];
5982 u8 priority[0x4];
5983 u8 cong_protocol[0x4];
5984
5985 u8 reserved_at_60[0x20];
5986 };
5987
5988 struct mlx5_ifc_query_cong_statistics_out_bits {
5989 u8 status[0x8];
5990 u8 reserved_at_8[0x18];
5991
5992 u8 syndrome[0x20];
5993
5994 u8 reserved_at_40[0x40];
5995
5996 u8 rp_cur_flows[0x20];
5997
5998 u8 sum_flows[0x20];
5999
6000 u8 rp_cnp_ignored_high[0x20];
6001
6002 u8 rp_cnp_ignored_low[0x20];
6003
6004 u8 rp_cnp_handled_high[0x20];
6005
6006 u8 rp_cnp_handled_low[0x20];
6007
6008 u8 reserved_at_140[0x100];
6009
6010 u8 time_stamp_high[0x20];
6011
6012 u8 time_stamp_low[0x20];
6013
6014 u8 accumulators_period[0x20];
6015
6016 u8 np_ecn_marked_roce_packets_high[0x20];
6017
6018 u8 np_ecn_marked_roce_packets_low[0x20];
6019
6020 u8 np_cnp_sent_high[0x20];
6021
6022 u8 np_cnp_sent_low[0x20];
6023
6024 u8 reserved_at_320[0x560];
6025 };
6026
6027 struct mlx5_ifc_query_cong_statistics_in_bits {
6028 u8 opcode[0x10];
6029 u8 reserved_at_10[0x10];
6030
6031 u8 reserved_at_20[0x10];
6032 u8 op_mod[0x10];
6033
6034 u8 clear[0x1];
6035 u8 reserved_at_41[0x1f];
6036
6037 u8 reserved_at_60[0x20];
6038 };
6039
6040 struct mlx5_ifc_query_cong_params_out_bits {
6041 u8 status[0x8];
6042 u8 reserved_at_8[0x18];
6043
6044 u8 syndrome[0x20];
6045
6046 u8 reserved_at_40[0x40];
6047
6048 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6049 };
6050
6051 struct mlx5_ifc_query_cong_params_in_bits {
6052 u8 opcode[0x10];
6053 u8 reserved_at_10[0x10];
6054
6055 u8 reserved_at_20[0x10];
6056 u8 op_mod[0x10];
6057
6058 u8 reserved_at_40[0x1c];
6059 u8 cong_protocol[0x4];
6060
6061 u8 reserved_at_60[0x20];
6062 };
6063
6064 struct mlx5_ifc_query_adapter_out_bits {
6065 u8 status[0x8];
6066 u8 reserved_at_8[0x18];
6067
6068 u8 syndrome[0x20];
6069
6070 u8 reserved_at_40[0x40];
6071
6072 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6073 };
6074
6075 struct mlx5_ifc_query_adapter_in_bits {
6076 u8 opcode[0x10];
6077 u8 reserved_at_10[0x10];
6078
6079 u8 reserved_at_20[0x10];
6080 u8 op_mod[0x10];
6081
6082 u8 reserved_at_40[0x40];
6083 };
6084
6085 struct mlx5_ifc_qp_2rst_out_bits {
6086 u8 status[0x8];
6087 u8 reserved_at_8[0x18];
6088
6089 u8 syndrome[0x20];
6090
6091 u8 reserved_at_40[0x40];
6092 };
6093
6094 struct mlx5_ifc_qp_2rst_in_bits {
6095 u8 opcode[0x10];
6096 u8 uid[0x10];
6097
6098 u8 reserved_at_20[0x10];
6099 u8 op_mod[0x10];
6100
6101 u8 reserved_at_40[0x8];
6102 u8 qpn[0x18];
6103
6104 u8 reserved_at_60[0x20];
6105 };
6106
6107 struct mlx5_ifc_qp_2err_out_bits {
6108 u8 status[0x8];
6109 u8 reserved_at_8[0x18];
6110
6111 u8 syndrome[0x20];
6112
6113 u8 reserved_at_40[0x40];
6114 };
6115
6116 struct mlx5_ifc_qp_2err_in_bits {
6117 u8 opcode[0x10];
6118 u8 uid[0x10];
6119
6120 u8 reserved_at_20[0x10];
6121 u8 op_mod[0x10];
6122
6123 u8 reserved_at_40[0x8];
6124 u8 qpn[0x18];
6125
6126 u8 reserved_at_60[0x20];
6127 };
6128
6129 struct mlx5_ifc_page_fault_resume_out_bits {
6130 u8 status[0x8];
6131 u8 reserved_at_8[0x18];
6132
6133 u8 syndrome[0x20];
6134
6135 u8 reserved_at_40[0x40];
6136 };
6137
6138 struct mlx5_ifc_page_fault_resume_in_bits {
6139 u8 opcode[0x10];
6140 u8 reserved_at_10[0x10];
6141
6142 u8 reserved_at_20[0x10];
6143 u8 op_mod[0x10];
6144
6145 u8 error[0x1];
6146 u8 reserved_at_41[0x4];
6147 u8 page_fault_type[0x3];
6148 u8 wq_number[0x18];
6149
6150 u8 reserved_at_60[0x8];
6151 u8 token[0x18];
6152 };
6153
6154 struct mlx5_ifc_nop_out_bits {
6155 u8 status[0x8];
6156 u8 reserved_at_8[0x18];
6157
6158 u8 syndrome[0x20];
6159
6160 u8 reserved_at_40[0x40];
6161 };
6162
6163 struct mlx5_ifc_nop_in_bits {
6164 u8 opcode[0x10];
6165 u8 reserved_at_10[0x10];
6166
6167 u8 reserved_at_20[0x10];
6168 u8 op_mod[0x10];
6169
6170 u8 reserved_at_40[0x40];
6171 };
6172
6173 struct mlx5_ifc_modify_vport_state_out_bits {
6174 u8 status[0x8];
6175 u8 reserved_at_8[0x18];
6176
6177 u8 syndrome[0x20];
6178
6179 u8 reserved_at_40[0x40];
6180 };
6181
6182 struct mlx5_ifc_modify_vport_state_in_bits {
6183 u8 opcode[0x10];
6184 u8 reserved_at_10[0x10];
6185
6186 u8 reserved_at_20[0x10];
6187 u8 op_mod[0x10];
6188
6189 u8 other_vport[0x1];
6190 u8 reserved_at_41[0xf];
6191 u8 vport_number[0x10];
6192
6193 u8 reserved_at_60[0x18];
6194 u8 admin_state[0x4];
6195 u8 reserved_at_7c[0x4];
6196 };
6197
6198 struct mlx5_ifc_modify_tis_out_bits {
6199 u8 status[0x8];
6200 u8 reserved_at_8[0x18];
6201
6202 u8 syndrome[0x20];
6203
6204 u8 reserved_at_40[0x40];
6205 };
6206
6207 struct mlx5_ifc_modify_tis_bitmask_bits {
6208 u8 reserved_at_0[0x20];
6209
6210 u8 reserved_at_20[0x1d];
6211 u8 lag_tx_port_affinity[0x1];
6212 u8 strict_lag_tx_port_affinity[0x1];
6213 u8 prio[0x1];
6214 };
6215
6216 struct mlx5_ifc_modify_tis_in_bits {
6217 u8 opcode[0x10];
6218 u8 uid[0x10];
6219
6220 u8 reserved_at_20[0x10];
6221 u8 op_mod[0x10];
6222
6223 u8 reserved_at_40[0x8];
6224 u8 tisn[0x18];
6225
6226 u8 reserved_at_60[0x20];
6227
6228 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6229
6230 u8 reserved_at_c0[0x40];
6231
6232 struct mlx5_ifc_tisc_bits ctx;
6233 };
6234
6235 struct mlx5_ifc_modify_tir_bitmask_bits {
6236 u8 reserved_at_0[0x20];
6237
6238 u8 reserved_at_20[0x1b];
6239 u8 self_lb_en[0x1];
6240 u8 reserved_at_3c[0x1];
6241 u8 hash[0x1];
6242 u8 reserved_at_3e[0x1];
6243 u8 lro[0x1];
6244 };
6245
6246 struct mlx5_ifc_modify_tir_out_bits {
6247 u8 status[0x8];
6248 u8 reserved_at_8[0x18];
6249
6250 u8 syndrome[0x20];
6251
6252 u8 reserved_at_40[0x40];
6253 };
6254
6255 struct mlx5_ifc_modify_tir_in_bits {
6256 u8 opcode[0x10];
6257 u8 uid[0x10];
6258
6259 u8 reserved_at_20[0x10];
6260 u8 op_mod[0x10];
6261
6262 u8 reserved_at_40[0x8];
6263 u8 tirn[0x18];
6264
6265 u8 reserved_at_60[0x20];
6266
6267 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6268
6269 u8 reserved_at_c0[0x40];
6270
6271 struct mlx5_ifc_tirc_bits ctx;
6272 };
6273
6274 struct mlx5_ifc_modify_sq_out_bits {
6275 u8 status[0x8];
6276 u8 reserved_at_8[0x18];
6277
6278 u8 syndrome[0x20];
6279
6280 u8 reserved_at_40[0x40];
6281 };
6282
6283 struct mlx5_ifc_modify_sq_in_bits {
6284 u8 opcode[0x10];
6285 u8 uid[0x10];
6286
6287 u8 reserved_at_20[0x10];
6288 u8 op_mod[0x10];
6289
6290 u8 sq_state[0x4];
6291 u8 reserved_at_44[0x4];
6292 u8 sqn[0x18];
6293
6294 u8 reserved_at_60[0x20];
6295
6296 u8 modify_bitmask[0x40];
6297
6298 u8 reserved_at_c0[0x40];
6299
6300 struct mlx5_ifc_sqc_bits ctx;
6301 };
6302
6303 struct mlx5_ifc_modify_scheduling_element_out_bits {
6304 u8 status[0x8];
6305 u8 reserved_at_8[0x18];
6306
6307 u8 syndrome[0x20];
6308
6309 u8 reserved_at_40[0x1c0];
6310 };
6311
6312 enum {
6313 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6314 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6315 };
6316
6317 struct mlx5_ifc_modify_scheduling_element_in_bits {
6318 u8 opcode[0x10];
6319 u8 reserved_at_10[0x10];
6320
6321 u8 reserved_at_20[0x10];
6322 u8 op_mod[0x10];
6323
6324 u8 scheduling_hierarchy[0x8];
6325 u8 reserved_at_48[0x18];
6326
6327 u8 scheduling_element_id[0x20];
6328
6329 u8 reserved_at_80[0x20];
6330
6331 u8 modify_bitmask[0x20];
6332
6333 u8 reserved_at_c0[0x40];
6334
6335 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6336
6337 u8 reserved_at_300[0x100];
6338 };
6339
6340 struct mlx5_ifc_modify_rqt_out_bits {
6341 u8 status[0x8];
6342 u8 reserved_at_8[0x18];
6343
6344 u8 syndrome[0x20];
6345
6346 u8 reserved_at_40[0x40];
6347 };
6348
6349 struct mlx5_ifc_rqt_bitmask_bits {
6350 u8 reserved_at_0[0x20];
6351
6352 u8 reserved_at_20[0x1f];
6353 u8 rqn_list[0x1];
6354 };
6355
6356 struct mlx5_ifc_modify_rqt_in_bits {
6357 u8 opcode[0x10];
6358 u8 uid[0x10];
6359
6360 u8 reserved_at_20[0x10];
6361 u8 op_mod[0x10];
6362
6363 u8 reserved_at_40[0x8];
6364 u8 rqtn[0x18];
6365
6366 u8 reserved_at_60[0x20];
6367
6368 struct mlx5_ifc_rqt_bitmask_bits bitmask;
6369
6370 u8 reserved_at_c0[0x40];
6371
6372 struct mlx5_ifc_rqtc_bits ctx;
6373 };
6374
6375 struct mlx5_ifc_modify_rq_out_bits {
6376 u8 status[0x8];
6377 u8 reserved_at_8[0x18];
6378
6379 u8 syndrome[0x20];
6380
6381 u8 reserved_at_40[0x40];
6382 };
6383
6384 enum {
6385 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6386 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6387 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6388 };
6389
6390 struct mlx5_ifc_modify_rq_in_bits {
6391 u8 opcode[0x10];
6392 u8 uid[0x10];
6393
6394 u8 reserved_at_20[0x10];
6395 u8 op_mod[0x10];
6396
6397 u8 rq_state[0x4];
6398 u8 reserved_at_44[0x4];
6399 u8 rqn[0x18];
6400
6401 u8 reserved_at_60[0x20];
6402
6403 u8 modify_bitmask[0x40];
6404
6405 u8 reserved_at_c0[0x40];
6406
6407 struct mlx5_ifc_rqc_bits ctx;
6408 };
6409
6410 struct mlx5_ifc_modify_rmp_out_bits {
6411 u8 status[0x8];
6412 u8 reserved_at_8[0x18];
6413
6414 u8 syndrome[0x20];
6415
6416 u8 reserved_at_40[0x40];
6417 };
6418
6419 struct mlx5_ifc_rmp_bitmask_bits {
6420 u8 reserved_at_0[0x20];
6421
6422 u8 reserved_at_20[0x1f];
6423 u8 lwm[0x1];
6424 };
6425
6426 struct mlx5_ifc_modify_rmp_in_bits {
6427 u8 opcode[0x10];
6428 u8 uid[0x10];
6429
6430 u8 reserved_at_20[0x10];
6431 u8 op_mod[0x10];
6432
6433 u8 rmp_state[0x4];
6434 u8 reserved_at_44[0x4];
6435 u8 rmpn[0x18];
6436
6437 u8 reserved_at_60[0x20];
6438
6439 struct mlx5_ifc_rmp_bitmask_bits bitmask;
6440
6441 u8 reserved_at_c0[0x40];
6442
6443 struct mlx5_ifc_rmpc_bits ctx;
6444 };
6445
6446 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6447 u8 status[0x8];
6448 u8 reserved_at_8[0x18];
6449
6450 u8 syndrome[0x20];
6451
6452 u8 reserved_at_40[0x40];
6453 };
6454
6455 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6456 u8 reserved_at_0[0x12];
6457 u8 affiliation[0x1];
6458 u8 reserved_at_13[0x1];
6459 u8 disable_uc_local_lb[0x1];
6460 u8 disable_mc_local_lb[0x1];
6461 u8 node_guid[0x1];
6462 u8 port_guid[0x1];
6463 u8 min_inline[0x1];
6464 u8 mtu[0x1];
6465 u8 change_event[0x1];
6466 u8 promisc[0x1];
6467 u8 permanent_address[0x1];
6468 u8 addresses_list[0x1];
6469 u8 roce_en[0x1];
6470 u8 reserved_at_1f[0x1];
6471 };
6472
6473 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6474 u8 opcode[0x10];
6475 u8 reserved_at_10[0x10];
6476
6477 u8 reserved_at_20[0x10];
6478 u8 op_mod[0x10];
6479
6480 u8 other_vport[0x1];
6481 u8 reserved_at_41[0xf];
6482 u8 vport_number[0x10];
6483
6484 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6485
6486 u8 reserved_at_80[0x780];
6487
6488 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6489 };
6490
6491 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6492 u8 status[0x8];
6493 u8 reserved_at_8[0x18];
6494
6495 u8 syndrome[0x20];
6496
6497 u8 reserved_at_40[0x40];
6498 };
6499
6500 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6501 u8 opcode[0x10];
6502 u8 reserved_at_10[0x10];
6503
6504 u8 reserved_at_20[0x10];
6505 u8 op_mod[0x10];
6506
6507 u8 other_vport[0x1];
6508 u8 reserved_at_41[0xb];
6509 u8 port_num[0x4];
6510 u8 vport_number[0x10];
6511
6512 u8 reserved_at_60[0x20];
6513
6514 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6515 };
6516
6517 struct mlx5_ifc_modify_cq_out_bits {
6518 u8 status[0x8];
6519 u8 reserved_at_8[0x18];
6520
6521 u8 syndrome[0x20];
6522
6523 u8 reserved_at_40[0x40];
6524 };
6525
6526 enum {
6527 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6528 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6529 };
6530
6531 struct mlx5_ifc_modify_cq_in_bits {
6532 u8 opcode[0x10];
6533 u8 uid[0x10];
6534
6535 u8 reserved_at_20[0x10];
6536 u8 op_mod[0x10];
6537
6538 u8 reserved_at_40[0x8];
6539 u8 cqn[0x18];
6540
6541 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6542
6543 struct mlx5_ifc_cqc_bits cq_context;
6544
6545 u8 reserved_at_280[0x60];
6546
6547 u8 cq_umem_valid[0x1];
6548 u8 reserved_at_2e1[0x1f];
6549
6550 u8 reserved_at_300[0x580];
6551
6552 u8 pas[][0x40];
6553 };
6554
6555 struct mlx5_ifc_modify_cong_status_out_bits {
6556 u8 status[0x8];
6557 u8 reserved_at_8[0x18];
6558
6559 u8 syndrome[0x20];
6560
6561 u8 reserved_at_40[0x40];
6562 };
6563
6564 struct mlx5_ifc_modify_cong_status_in_bits {
6565 u8 opcode[0x10];
6566 u8 reserved_at_10[0x10];
6567
6568 u8 reserved_at_20[0x10];
6569 u8 op_mod[0x10];
6570
6571 u8 reserved_at_40[0x18];
6572 u8 priority[0x4];
6573 u8 cong_protocol[0x4];
6574
6575 u8 enable[0x1];
6576 u8 tag_enable[0x1];
6577 u8 reserved_at_62[0x1e];
6578 };
6579
6580 struct mlx5_ifc_modify_cong_params_out_bits {
6581 u8 status[0x8];
6582 u8 reserved_at_8[0x18];
6583
6584 u8 syndrome[0x20];
6585
6586 u8 reserved_at_40[0x40];
6587 };
6588
6589 struct mlx5_ifc_modify_cong_params_in_bits {
6590 u8 opcode[0x10];
6591 u8 reserved_at_10[0x10];
6592
6593 u8 reserved_at_20[0x10];
6594 u8 op_mod[0x10];
6595
6596 u8 reserved_at_40[0x1c];
6597 u8 cong_protocol[0x4];
6598
6599 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6600
6601 u8 reserved_at_80[0x80];
6602
6603 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6604 };
6605
6606 struct mlx5_ifc_manage_pages_out_bits {
6607 u8 status[0x8];
6608 u8 reserved_at_8[0x18];
6609
6610 u8 syndrome[0x20];
6611
6612 u8 output_num_entries[0x20];
6613
6614 u8 reserved_at_60[0x20];
6615
6616 u8 pas[][0x40];
6617 };
6618
6619 enum {
6620 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6621 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6622 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6623 };
6624
6625 struct mlx5_ifc_manage_pages_in_bits {
6626 u8 opcode[0x10];
6627 u8 reserved_at_10[0x10];
6628
6629 u8 reserved_at_20[0x10];
6630 u8 op_mod[0x10];
6631
6632 u8 embedded_cpu_function[0x1];
6633 u8 reserved_at_41[0xf];
6634 u8 function_id[0x10];
6635
6636 u8 input_num_entries[0x20];
6637
6638 u8 pas[][0x40];
6639 };
6640
6641 struct mlx5_ifc_mad_ifc_out_bits {
6642 u8 status[0x8];
6643 u8 reserved_at_8[0x18];
6644
6645 u8 syndrome[0x20];
6646
6647 u8 reserved_at_40[0x40];
6648
6649 u8 response_mad_packet[256][0x8];
6650 };
6651
6652 struct mlx5_ifc_mad_ifc_in_bits {
6653 u8 opcode[0x10];
6654 u8 reserved_at_10[0x10];
6655
6656 u8 reserved_at_20[0x10];
6657 u8 op_mod[0x10];
6658
6659 u8 remote_lid[0x10];
6660 u8 reserved_at_50[0x8];
6661 u8 port[0x8];
6662
6663 u8 reserved_at_60[0x20];
6664
6665 u8 mad[256][0x8];
6666 };
6667
6668 struct mlx5_ifc_init_hca_out_bits {
6669 u8 status[0x8];
6670 u8 reserved_at_8[0x18];
6671
6672 u8 syndrome[0x20];
6673
6674 u8 reserved_at_40[0x40];
6675 };
6676
6677 struct mlx5_ifc_init_hca_in_bits {
6678 u8 opcode[0x10];
6679 u8 reserved_at_10[0x10];
6680
6681 u8 reserved_at_20[0x10];
6682 u8 op_mod[0x10];
6683
6684 u8 reserved_at_40[0x40];
6685 u8 sw_owner_id[4][0x20];
6686 };
6687
6688 struct mlx5_ifc_init2rtr_qp_out_bits {
6689 u8 status[0x8];
6690 u8 reserved_at_8[0x18];
6691
6692 u8 syndrome[0x20];
6693
6694 u8 reserved_at_40[0x20];
6695 u8 ece[0x20];
6696 };
6697
6698 struct mlx5_ifc_init2rtr_qp_in_bits {
6699 u8 opcode[0x10];
6700 u8 uid[0x10];
6701
6702 u8 reserved_at_20[0x10];
6703 u8 op_mod[0x10];
6704
6705 u8 reserved_at_40[0x8];
6706 u8 qpn[0x18];
6707
6708 u8 reserved_at_60[0x20];
6709
6710 u8 opt_param_mask[0x20];
6711
6712 u8 ece[0x20];
6713
6714 struct mlx5_ifc_qpc_bits qpc;
6715
6716 u8 reserved_at_800[0x80];
6717 };
6718
6719 struct mlx5_ifc_init2init_qp_out_bits {
6720 u8 status[0x8];
6721 u8 reserved_at_8[0x18];
6722
6723 u8 syndrome[0x20];
6724
6725 u8 reserved_at_40[0x20];
6726 u8 ece[0x20];
6727 };
6728
6729 struct mlx5_ifc_init2init_qp_in_bits {
6730 u8 opcode[0x10];
6731 u8 uid[0x10];
6732
6733 u8 reserved_at_20[0x10];
6734 u8 op_mod[0x10];
6735
6736 u8 reserved_at_40[0x8];
6737 u8 qpn[0x18];
6738
6739 u8 reserved_at_60[0x20];
6740
6741 u8 opt_param_mask[0x20];
6742
6743 u8 ece[0x20];
6744
6745 struct mlx5_ifc_qpc_bits qpc;
6746
6747 u8 reserved_at_800[0x80];
6748 };
6749
6750 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6751 u8 status[0x8];
6752 u8 reserved_at_8[0x18];
6753
6754 u8 syndrome[0x20];
6755
6756 u8 reserved_at_40[0x40];
6757
6758 u8 packet_headers_log[128][0x8];
6759
6760 u8 packet_syndrome[64][0x8];
6761 };
6762
6763 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6764 u8 opcode[0x10];
6765 u8 reserved_at_10[0x10];
6766
6767 u8 reserved_at_20[0x10];
6768 u8 op_mod[0x10];
6769
6770 u8 reserved_at_40[0x40];
6771 };
6772
6773 struct mlx5_ifc_gen_eqe_in_bits {
6774 u8 opcode[0x10];
6775 u8 reserved_at_10[0x10];
6776
6777 u8 reserved_at_20[0x10];
6778 u8 op_mod[0x10];
6779
6780 u8 reserved_at_40[0x18];
6781 u8 eq_number[0x8];
6782
6783 u8 reserved_at_60[0x20];
6784
6785 u8 eqe[64][0x8];
6786 };
6787
6788 struct mlx5_ifc_gen_eq_out_bits {
6789 u8 status[0x8];
6790 u8 reserved_at_8[0x18];
6791
6792 u8 syndrome[0x20];
6793
6794 u8 reserved_at_40[0x40];
6795 };
6796
6797 struct mlx5_ifc_enable_hca_out_bits {
6798 u8 status[0x8];
6799 u8 reserved_at_8[0x18];
6800
6801 u8 syndrome[0x20];
6802
6803 u8 reserved_at_40[0x20];
6804 };
6805
6806 struct mlx5_ifc_enable_hca_in_bits {
6807 u8 opcode[0x10];
6808 u8 reserved_at_10[0x10];
6809
6810 u8 reserved_at_20[0x10];
6811 u8 op_mod[0x10];
6812
6813 u8 embedded_cpu_function[0x1];
6814 u8 reserved_at_41[0xf];
6815 u8 function_id[0x10];
6816
6817 u8 reserved_at_60[0x20];
6818 };
6819
6820 struct mlx5_ifc_drain_dct_out_bits {
6821 u8 status[0x8];
6822 u8 reserved_at_8[0x18];
6823
6824 u8 syndrome[0x20];
6825
6826 u8 reserved_at_40[0x40];
6827 };
6828
6829 struct mlx5_ifc_drain_dct_in_bits {
6830 u8 opcode[0x10];
6831 u8 uid[0x10];
6832
6833 u8 reserved_at_20[0x10];
6834 u8 op_mod[0x10];
6835
6836 u8 reserved_at_40[0x8];
6837 u8 dctn[0x18];
6838
6839 u8 reserved_at_60[0x20];
6840 };
6841
6842 struct mlx5_ifc_disable_hca_out_bits {
6843 u8 status[0x8];
6844 u8 reserved_at_8[0x18];
6845
6846 u8 syndrome[0x20];
6847
6848 u8 reserved_at_40[0x20];
6849 };
6850
6851 struct mlx5_ifc_disable_hca_in_bits {
6852 u8 opcode[0x10];
6853 u8 reserved_at_10[0x10];
6854
6855 u8 reserved_at_20[0x10];
6856 u8 op_mod[0x10];
6857
6858 u8 embedded_cpu_function[0x1];
6859 u8 reserved_at_41[0xf];
6860 u8 function_id[0x10];
6861
6862 u8 reserved_at_60[0x20];
6863 };
6864
6865 struct mlx5_ifc_detach_from_mcg_out_bits {
6866 u8 status[0x8];
6867 u8 reserved_at_8[0x18];
6868
6869 u8 syndrome[0x20];
6870
6871 u8 reserved_at_40[0x40];
6872 };
6873
6874 struct mlx5_ifc_detach_from_mcg_in_bits {
6875 u8 opcode[0x10];
6876 u8 uid[0x10];
6877
6878 u8 reserved_at_20[0x10];
6879 u8 op_mod[0x10];
6880
6881 u8 reserved_at_40[0x8];
6882 u8 qpn[0x18];
6883
6884 u8 reserved_at_60[0x20];
6885
6886 u8 multicast_gid[16][0x8];
6887 };
6888
6889 struct mlx5_ifc_destroy_xrq_out_bits {
6890 u8 status[0x8];
6891 u8 reserved_at_8[0x18];
6892
6893 u8 syndrome[0x20];
6894
6895 u8 reserved_at_40[0x40];
6896 };
6897
6898 struct mlx5_ifc_destroy_xrq_in_bits {
6899 u8 opcode[0x10];
6900 u8 uid[0x10];
6901
6902 u8 reserved_at_20[0x10];
6903 u8 op_mod[0x10];
6904
6905 u8 reserved_at_40[0x8];
6906 u8 xrqn[0x18];
6907
6908 u8 reserved_at_60[0x20];
6909 };
6910
6911 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6912 u8 status[0x8];
6913 u8 reserved_at_8[0x18];
6914
6915 u8 syndrome[0x20];
6916
6917 u8 reserved_at_40[0x40];
6918 };
6919
6920 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6921 u8 opcode[0x10];
6922 u8 uid[0x10];
6923
6924 u8 reserved_at_20[0x10];
6925 u8 op_mod[0x10];
6926
6927 u8 reserved_at_40[0x8];
6928 u8 xrc_srqn[0x18];
6929
6930 u8 reserved_at_60[0x20];
6931 };
6932
6933 struct mlx5_ifc_destroy_tis_out_bits {
6934 u8 status[0x8];
6935 u8 reserved_at_8[0x18];
6936
6937 u8 syndrome[0x20];
6938
6939 u8 reserved_at_40[0x40];
6940 };
6941
6942 struct mlx5_ifc_destroy_tis_in_bits {
6943 u8 opcode[0x10];
6944 u8 uid[0x10];
6945
6946 u8 reserved_at_20[0x10];
6947 u8 op_mod[0x10];
6948
6949 u8 reserved_at_40[0x8];
6950 u8 tisn[0x18];
6951
6952 u8 reserved_at_60[0x20];
6953 };
6954
6955 struct mlx5_ifc_destroy_tir_out_bits {
6956 u8 status[0x8];
6957 u8 reserved_at_8[0x18];
6958
6959 u8 syndrome[0x20];
6960
6961 u8 reserved_at_40[0x40];
6962 };
6963
6964 struct mlx5_ifc_destroy_tir_in_bits {
6965 u8 opcode[0x10];
6966 u8 uid[0x10];
6967
6968 u8 reserved_at_20[0x10];
6969 u8 op_mod[0x10];
6970
6971 u8 reserved_at_40[0x8];
6972 u8 tirn[0x18];
6973
6974 u8 reserved_at_60[0x20];
6975 };
6976
6977 struct mlx5_ifc_destroy_srq_out_bits {
6978 u8 status[0x8];
6979 u8 reserved_at_8[0x18];
6980
6981 u8 syndrome[0x20];
6982
6983 u8 reserved_at_40[0x40];
6984 };
6985
6986 struct mlx5_ifc_destroy_srq_in_bits {
6987 u8 opcode[0x10];
6988 u8 uid[0x10];
6989
6990 u8 reserved_at_20[0x10];
6991 u8 op_mod[0x10];
6992
6993 u8 reserved_at_40[0x8];
6994 u8 srqn[0x18];
6995
6996 u8 reserved_at_60[0x20];
6997 };
6998
6999 struct mlx5_ifc_destroy_sq_out_bits {
7000 u8 status[0x8];
7001 u8 reserved_at_8[0x18];
7002
7003 u8 syndrome[0x20];
7004
7005 u8 reserved_at_40[0x40];
7006 };
7007
7008 struct mlx5_ifc_destroy_sq_in_bits {
7009 u8 opcode[0x10];
7010 u8 uid[0x10];
7011
7012 u8 reserved_at_20[0x10];
7013 u8 op_mod[0x10];
7014
7015 u8 reserved_at_40[0x8];
7016 u8 sqn[0x18];
7017
7018 u8 reserved_at_60[0x20];
7019 };
7020
7021 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7022 u8 status[0x8];
7023 u8 reserved_at_8[0x18];
7024
7025 u8 syndrome[0x20];
7026
7027 u8 reserved_at_40[0x1c0];
7028 };
7029
7030 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7031 u8 opcode[0x10];
7032 u8 reserved_at_10[0x10];
7033
7034 u8 reserved_at_20[0x10];
7035 u8 op_mod[0x10];
7036
7037 u8 scheduling_hierarchy[0x8];
7038 u8 reserved_at_48[0x18];
7039
7040 u8 scheduling_element_id[0x20];
7041
7042 u8 reserved_at_80[0x180];
7043 };
7044
7045 struct mlx5_ifc_destroy_rqt_out_bits {
7046 u8 status[0x8];
7047 u8 reserved_at_8[0x18];
7048
7049 u8 syndrome[0x20];
7050
7051 u8 reserved_at_40[0x40];
7052 };
7053
7054 struct mlx5_ifc_destroy_rqt_in_bits {
7055 u8 opcode[0x10];
7056 u8 uid[0x10];
7057
7058 u8 reserved_at_20[0x10];
7059 u8 op_mod[0x10];
7060
7061 u8 reserved_at_40[0x8];
7062 u8 rqtn[0x18];
7063
7064 u8 reserved_at_60[0x20];
7065 };
7066
7067 struct mlx5_ifc_destroy_rq_out_bits {
7068 u8 status[0x8];
7069 u8 reserved_at_8[0x18];
7070
7071 u8 syndrome[0x20];
7072
7073 u8 reserved_at_40[0x40];
7074 };
7075
7076 struct mlx5_ifc_destroy_rq_in_bits {
7077 u8 opcode[0x10];
7078 u8 uid[0x10];
7079
7080 u8 reserved_at_20[0x10];
7081 u8 op_mod[0x10];
7082
7083 u8 reserved_at_40[0x8];
7084 u8 rqn[0x18];
7085
7086 u8 reserved_at_60[0x20];
7087 };
7088
7089 struct mlx5_ifc_set_delay_drop_params_in_bits {
7090 u8 opcode[0x10];
7091 u8 reserved_at_10[0x10];
7092
7093 u8 reserved_at_20[0x10];
7094 u8 op_mod[0x10];
7095
7096 u8 reserved_at_40[0x20];
7097
7098 u8 reserved_at_60[0x10];
7099 u8 delay_drop_timeout[0x10];
7100 };
7101
7102 struct mlx5_ifc_set_delay_drop_params_out_bits {
7103 u8 status[0x8];
7104 u8 reserved_at_8[0x18];
7105
7106 u8 syndrome[0x20];
7107
7108 u8 reserved_at_40[0x40];
7109 };
7110
7111 struct mlx5_ifc_destroy_rmp_out_bits {
7112 u8 status[0x8];
7113 u8 reserved_at_8[0x18];
7114
7115 u8 syndrome[0x20];
7116
7117 u8 reserved_at_40[0x40];
7118 };
7119
7120 struct mlx5_ifc_destroy_rmp_in_bits {
7121 u8 opcode[0x10];
7122 u8 uid[0x10];
7123
7124 u8 reserved_at_20[0x10];
7125 u8 op_mod[0x10];
7126
7127 u8 reserved_at_40[0x8];
7128 u8 rmpn[0x18];
7129
7130 u8 reserved_at_60[0x20];
7131 };
7132
7133 struct mlx5_ifc_destroy_qp_out_bits {
7134 u8 status[0x8];
7135 u8 reserved_at_8[0x18];
7136
7137 u8 syndrome[0x20];
7138
7139 u8 reserved_at_40[0x40];
7140 };
7141
7142 struct mlx5_ifc_destroy_qp_in_bits {
7143 u8 opcode[0x10];
7144 u8 uid[0x10];
7145
7146 u8 reserved_at_20[0x10];
7147 u8 op_mod[0x10];
7148
7149 u8 reserved_at_40[0x8];
7150 u8 qpn[0x18];
7151
7152 u8 reserved_at_60[0x20];
7153 };
7154
7155 struct mlx5_ifc_destroy_psv_out_bits {
7156 u8 status[0x8];
7157 u8 reserved_at_8[0x18];
7158
7159 u8 syndrome[0x20];
7160
7161 u8 reserved_at_40[0x40];
7162 };
7163
7164 struct mlx5_ifc_destroy_psv_in_bits {
7165 u8 opcode[0x10];
7166 u8 reserved_at_10[0x10];
7167
7168 u8 reserved_at_20[0x10];
7169 u8 op_mod[0x10];
7170
7171 u8 reserved_at_40[0x8];
7172 u8 psvn[0x18];
7173
7174 u8 reserved_at_60[0x20];
7175 };
7176
7177 struct mlx5_ifc_destroy_mkey_out_bits {
7178 u8 status[0x8];
7179 u8 reserved_at_8[0x18];
7180
7181 u8 syndrome[0x20];
7182
7183 u8 reserved_at_40[0x40];
7184 };
7185
7186 struct mlx5_ifc_destroy_mkey_in_bits {
7187 u8 opcode[0x10];
7188 u8 uid[0x10];
7189
7190 u8 reserved_at_20[0x10];
7191 u8 op_mod[0x10];
7192
7193 u8 reserved_at_40[0x8];
7194 u8 mkey_index[0x18];
7195
7196 u8 reserved_at_60[0x20];
7197 };
7198
7199 struct mlx5_ifc_destroy_flow_table_out_bits {
7200 u8 status[0x8];
7201 u8 reserved_at_8[0x18];
7202
7203 u8 syndrome[0x20];
7204
7205 u8 reserved_at_40[0x40];
7206 };
7207
7208 struct mlx5_ifc_destroy_flow_table_in_bits {
7209 u8 opcode[0x10];
7210 u8 reserved_at_10[0x10];
7211
7212 u8 reserved_at_20[0x10];
7213 u8 op_mod[0x10];
7214
7215 u8 other_vport[0x1];
7216 u8 reserved_at_41[0xf];
7217 u8 vport_number[0x10];
7218
7219 u8 reserved_at_60[0x20];
7220
7221 u8 table_type[0x8];
7222 u8 reserved_at_88[0x18];
7223
7224 u8 reserved_at_a0[0x8];
7225 u8 table_id[0x18];
7226
7227 u8 reserved_at_c0[0x140];
7228 };
7229
7230 struct mlx5_ifc_destroy_flow_group_out_bits {
7231 u8 status[0x8];
7232 u8 reserved_at_8[0x18];
7233
7234 u8 syndrome[0x20];
7235
7236 u8 reserved_at_40[0x40];
7237 };
7238
7239 struct mlx5_ifc_destroy_flow_group_in_bits {
7240 u8 opcode[0x10];
7241 u8 reserved_at_10[0x10];
7242
7243 u8 reserved_at_20[0x10];
7244 u8 op_mod[0x10];
7245
7246 u8 other_vport[0x1];
7247 u8 reserved_at_41[0xf];
7248 u8 vport_number[0x10];
7249
7250 u8 reserved_at_60[0x20];
7251
7252 u8 table_type[0x8];
7253 u8 reserved_at_88[0x18];
7254
7255 u8 reserved_at_a0[0x8];
7256 u8 table_id[0x18];
7257
7258 u8 group_id[0x20];
7259
7260 u8 reserved_at_e0[0x120];
7261 };
7262
7263 struct mlx5_ifc_destroy_eq_out_bits {
7264 u8 status[0x8];
7265 u8 reserved_at_8[0x18];
7266
7267 u8 syndrome[0x20];
7268
7269 u8 reserved_at_40[0x40];
7270 };
7271
7272 struct mlx5_ifc_destroy_eq_in_bits {
7273 u8 opcode[0x10];
7274 u8 reserved_at_10[0x10];
7275
7276 u8 reserved_at_20[0x10];
7277 u8 op_mod[0x10];
7278
7279 u8 reserved_at_40[0x18];
7280 u8 eq_number[0x8];
7281
7282 u8 reserved_at_60[0x20];
7283 };
7284
7285 struct mlx5_ifc_destroy_dct_out_bits {
7286 u8 status[0x8];
7287 u8 reserved_at_8[0x18];
7288
7289 u8 syndrome[0x20];
7290
7291 u8 reserved_at_40[0x40];
7292 };
7293
7294 struct mlx5_ifc_destroy_dct_in_bits {
7295 u8 opcode[0x10];
7296 u8 uid[0x10];
7297
7298 u8 reserved_at_20[0x10];
7299 u8 op_mod[0x10];
7300
7301 u8 reserved_at_40[0x8];
7302 u8 dctn[0x18];
7303
7304 u8 reserved_at_60[0x20];
7305 };
7306
7307 struct mlx5_ifc_destroy_cq_out_bits {
7308 u8 status[0x8];
7309 u8 reserved_at_8[0x18];
7310
7311 u8 syndrome[0x20];
7312
7313 u8 reserved_at_40[0x40];
7314 };
7315
7316 struct mlx5_ifc_destroy_cq_in_bits {
7317 u8 opcode[0x10];
7318 u8 uid[0x10];
7319
7320 u8 reserved_at_20[0x10];
7321 u8 op_mod[0x10];
7322
7323 u8 reserved_at_40[0x8];
7324 u8 cqn[0x18];
7325
7326 u8 reserved_at_60[0x20];
7327 };
7328
7329 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7330 u8 status[0x8];
7331 u8 reserved_at_8[0x18];
7332
7333 u8 syndrome[0x20];
7334
7335 u8 reserved_at_40[0x40];
7336 };
7337
7338 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7339 u8 opcode[0x10];
7340 u8 reserved_at_10[0x10];
7341
7342 u8 reserved_at_20[0x10];
7343 u8 op_mod[0x10];
7344
7345 u8 reserved_at_40[0x20];
7346
7347 u8 reserved_at_60[0x10];
7348 u8 vxlan_udp_port[0x10];
7349 };
7350
7351 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7352 u8 status[0x8];
7353 u8 reserved_at_8[0x18];
7354
7355 u8 syndrome[0x20];
7356
7357 u8 reserved_at_40[0x40];
7358 };
7359
7360 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7361 u8 opcode[0x10];
7362 u8 reserved_at_10[0x10];
7363
7364 u8 reserved_at_20[0x10];
7365 u8 op_mod[0x10];
7366
7367 u8 reserved_at_40[0x60];
7368
7369 u8 reserved_at_a0[0x8];
7370 u8 table_index[0x18];
7371
7372 u8 reserved_at_c0[0x140];
7373 };
7374
7375 struct mlx5_ifc_delete_fte_out_bits {
7376 u8 status[0x8];
7377 u8 reserved_at_8[0x18];
7378
7379 u8 syndrome[0x20];
7380
7381 u8 reserved_at_40[0x40];
7382 };
7383
7384 struct mlx5_ifc_delete_fte_in_bits {
7385 u8 opcode[0x10];
7386 u8 reserved_at_10[0x10];
7387
7388 u8 reserved_at_20[0x10];
7389 u8 op_mod[0x10];
7390
7391 u8 other_vport[0x1];
7392 u8 reserved_at_41[0xf];
7393 u8 vport_number[0x10];
7394
7395 u8 reserved_at_60[0x20];
7396
7397 u8 table_type[0x8];
7398 u8 reserved_at_88[0x18];
7399
7400 u8 reserved_at_a0[0x8];
7401 u8 table_id[0x18];
7402
7403 u8 reserved_at_c0[0x40];
7404
7405 u8 flow_index[0x20];
7406
7407 u8 reserved_at_120[0xe0];
7408 };
7409
7410 struct mlx5_ifc_dealloc_xrcd_out_bits {
7411 u8 status[0x8];
7412 u8 reserved_at_8[0x18];
7413
7414 u8 syndrome[0x20];
7415
7416 u8 reserved_at_40[0x40];
7417 };
7418
7419 struct mlx5_ifc_dealloc_xrcd_in_bits {
7420 u8 opcode[0x10];
7421 u8 uid[0x10];
7422
7423 u8 reserved_at_20[0x10];
7424 u8 op_mod[0x10];
7425
7426 u8 reserved_at_40[0x8];
7427 u8 xrcd[0x18];
7428
7429 u8 reserved_at_60[0x20];
7430 };
7431
7432 struct mlx5_ifc_dealloc_uar_out_bits {
7433 u8 status[0x8];
7434 u8 reserved_at_8[0x18];
7435
7436 u8 syndrome[0x20];
7437
7438 u8 reserved_at_40[0x40];
7439 };
7440
7441 struct mlx5_ifc_dealloc_uar_in_bits {
7442 u8 opcode[0x10];
7443 u8 reserved_at_10[0x10];
7444
7445 u8 reserved_at_20[0x10];
7446 u8 op_mod[0x10];
7447
7448 u8 reserved_at_40[0x8];
7449 u8 uar[0x18];
7450
7451 u8 reserved_at_60[0x20];
7452 };
7453
7454 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7455 u8 status[0x8];
7456 u8 reserved_at_8[0x18];
7457
7458 u8 syndrome[0x20];
7459
7460 u8 reserved_at_40[0x40];
7461 };
7462
7463 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7464 u8 opcode[0x10];
7465 u8 uid[0x10];
7466
7467 u8 reserved_at_20[0x10];
7468 u8 op_mod[0x10];
7469
7470 u8 reserved_at_40[0x8];
7471 u8 transport_domain[0x18];
7472
7473 u8 reserved_at_60[0x20];
7474 };
7475
7476 struct mlx5_ifc_dealloc_q_counter_out_bits {
7477 u8 status[0x8];
7478 u8 reserved_at_8[0x18];
7479
7480 u8 syndrome[0x20];
7481
7482 u8 reserved_at_40[0x40];
7483 };
7484
7485 struct mlx5_ifc_dealloc_q_counter_in_bits {
7486 u8 opcode[0x10];
7487 u8 reserved_at_10[0x10];
7488
7489 u8 reserved_at_20[0x10];
7490 u8 op_mod[0x10];
7491
7492 u8 reserved_at_40[0x18];
7493 u8 counter_set_id[0x8];
7494
7495 u8 reserved_at_60[0x20];
7496 };
7497
7498 struct mlx5_ifc_dealloc_pd_out_bits {
7499 u8 status[0x8];
7500 u8 reserved_at_8[0x18];
7501
7502 u8 syndrome[0x20];
7503
7504 u8 reserved_at_40[0x40];
7505 };
7506
7507 struct mlx5_ifc_dealloc_pd_in_bits {
7508 u8 opcode[0x10];
7509 u8 uid[0x10];
7510
7511 u8 reserved_at_20[0x10];
7512 u8 op_mod[0x10];
7513
7514 u8 reserved_at_40[0x8];
7515 u8 pd[0x18];
7516
7517 u8 reserved_at_60[0x20];
7518 };
7519
7520 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7521 u8 status[0x8];
7522 u8 reserved_at_8[0x18];
7523
7524 u8 syndrome[0x20];
7525
7526 u8 reserved_at_40[0x40];
7527 };
7528
7529 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7530 u8 opcode[0x10];
7531 u8 reserved_at_10[0x10];
7532
7533 u8 reserved_at_20[0x10];
7534 u8 op_mod[0x10];
7535
7536 u8 flow_counter_id[0x20];
7537
7538 u8 reserved_at_60[0x20];
7539 };
7540
7541 struct mlx5_ifc_create_xrq_out_bits {
7542 u8 status[0x8];
7543 u8 reserved_at_8[0x18];
7544
7545 u8 syndrome[0x20];
7546
7547 u8 reserved_at_40[0x8];
7548 u8 xrqn[0x18];
7549
7550 u8 reserved_at_60[0x20];
7551 };
7552
7553 struct mlx5_ifc_create_xrq_in_bits {
7554 u8 opcode[0x10];
7555 u8 uid[0x10];
7556
7557 u8 reserved_at_20[0x10];
7558 u8 op_mod[0x10];
7559
7560 u8 reserved_at_40[0x40];
7561
7562 struct mlx5_ifc_xrqc_bits xrq_context;
7563 };
7564
7565 struct mlx5_ifc_create_xrc_srq_out_bits {
7566 u8 status[0x8];
7567 u8 reserved_at_8[0x18];
7568
7569 u8 syndrome[0x20];
7570
7571 u8 reserved_at_40[0x8];
7572 u8 xrc_srqn[0x18];
7573
7574 u8 reserved_at_60[0x20];
7575 };
7576
7577 struct mlx5_ifc_create_xrc_srq_in_bits {
7578 u8 opcode[0x10];
7579 u8 uid[0x10];
7580
7581 u8 reserved_at_20[0x10];
7582 u8 op_mod[0x10];
7583
7584 u8 reserved_at_40[0x40];
7585
7586 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7587
7588 u8 reserved_at_280[0x60];
7589
7590 u8 xrc_srq_umem_valid[0x1];
7591 u8 reserved_at_2e1[0x1f];
7592
7593 u8 reserved_at_300[0x580];
7594
7595 u8 pas[][0x40];
7596 };
7597
7598 struct mlx5_ifc_create_tis_out_bits {
7599 u8 status[0x8];
7600 u8 reserved_at_8[0x18];
7601
7602 u8 syndrome[0x20];
7603
7604 u8 reserved_at_40[0x8];
7605 u8 tisn[0x18];
7606
7607 u8 reserved_at_60[0x20];
7608 };
7609
7610 struct mlx5_ifc_create_tis_in_bits {
7611 u8 opcode[0x10];
7612 u8 uid[0x10];
7613
7614 u8 reserved_at_20[0x10];
7615 u8 op_mod[0x10];
7616
7617 u8 reserved_at_40[0xc0];
7618
7619 struct mlx5_ifc_tisc_bits ctx;
7620 };
7621
7622 struct mlx5_ifc_create_tir_out_bits {
7623 u8 status[0x8];
7624 u8 icm_address_63_40[0x18];
7625
7626 u8 syndrome[0x20];
7627
7628 u8 icm_address_39_32[0x8];
7629 u8 tirn[0x18];
7630
7631 u8 icm_address_31_0[0x20];
7632 };
7633
7634 struct mlx5_ifc_create_tir_in_bits {
7635 u8 opcode[0x10];
7636 u8 uid[0x10];
7637
7638 u8 reserved_at_20[0x10];
7639 u8 op_mod[0x10];
7640
7641 u8 reserved_at_40[0xc0];
7642
7643 struct mlx5_ifc_tirc_bits ctx;
7644 };
7645
7646 struct mlx5_ifc_create_srq_out_bits {
7647 u8 status[0x8];
7648 u8 reserved_at_8[0x18];
7649
7650 u8 syndrome[0x20];
7651
7652 u8 reserved_at_40[0x8];
7653 u8 srqn[0x18];
7654
7655 u8 reserved_at_60[0x20];
7656 };
7657
7658 struct mlx5_ifc_create_srq_in_bits {
7659 u8 opcode[0x10];
7660 u8 uid[0x10];
7661
7662 u8 reserved_at_20[0x10];
7663 u8 op_mod[0x10];
7664
7665 u8 reserved_at_40[0x40];
7666
7667 struct mlx5_ifc_srqc_bits srq_context_entry;
7668
7669 u8 reserved_at_280[0x600];
7670
7671 u8 pas[][0x40];
7672 };
7673
7674 struct mlx5_ifc_create_sq_out_bits {
7675 u8 status[0x8];
7676 u8 reserved_at_8[0x18];
7677
7678 u8 syndrome[0x20];
7679
7680 u8 reserved_at_40[0x8];
7681 u8 sqn[0x18];
7682
7683 u8 reserved_at_60[0x20];
7684 };
7685
7686 struct mlx5_ifc_create_sq_in_bits {
7687 u8 opcode[0x10];
7688 u8 uid[0x10];
7689
7690 u8 reserved_at_20[0x10];
7691 u8 op_mod[0x10];
7692
7693 u8 reserved_at_40[0xc0];
7694
7695 struct mlx5_ifc_sqc_bits ctx;
7696 };
7697
7698 struct mlx5_ifc_create_scheduling_element_out_bits {
7699 u8 status[0x8];
7700 u8 reserved_at_8[0x18];
7701
7702 u8 syndrome[0x20];
7703
7704 u8 reserved_at_40[0x40];
7705
7706 u8 scheduling_element_id[0x20];
7707
7708 u8 reserved_at_a0[0x160];
7709 };
7710
7711 struct mlx5_ifc_create_scheduling_element_in_bits {
7712 u8 opcode[0x10];
7713 u8 reserved_at_10[0x10];
7714
7715 u8 reserved_at_20[0x10];
7716 u8 op_mod[0x10];
7717
7718 u8 scheduling_hierarchy[0x8];
7719 u8 reserved_at_48[0x18];
7720
7721 u8 reserved_at_60[0xa0];
7722
7723 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7724
7725 u8 reserved_at_300[0x100];
7726 };
7727
7728 struct mlx5_ifc_create_rqt_out_bits {
7729 u8 status[0x8];
7730 u8 reserved_at_8[0x18];
7731
7732 u8 syndrome[0x20];
7733
7734 u8 reserved_at_40[0x8];
7735 u8 rqtn[0x18];
7736
7737 u8 reserved_at_60[0x20];
7738 };
7739
7740 struct mlx5_ifc_create_rqt_in_bits {
7741 u8 opcode[0x10];
7742 u8 uid[0x10];
7743
7744 u8 reserved_at_20[0x10];
7745 u8 op_mod[0x10];
7746
7747 u8 reserved_at_40[0xc0];
7748
7749 struct mlx5_ifc_rqtc_bits rqt_context;
7750 };
7751
7752 struct mlx5_ifc_create_rq_out_bits {
7753 u8 status[0x8];
7754 u8 reserved_at_8[0x18];
7755
7756 u8 syndrome[0x20];
7757
7758 u8 reserved_at_40[0x8];
7759 u8 rqn[0x18];
7760
7761 u8 reserved_at_60[0x20];
7762 };
7763
7764 struct mlx5_ifc_create_rq_in_bits {
7765 u8 opcode[0x10];
7766 u8 uid[0x10];
7767
7768 u8 reserved_at_20[0x10];
7769 u8 op_mod[0x10];
7770
7771 u8 reserved_at_40[0xc0];
7772
7773 struct mlx5_ifc_rqc_bits ctx;
7774 };
7775
7776 struct mlx5_ifc_create_rmp_out_bits {
7777 u8 status[0x8];
7778 u8 reserved_at_8[0x18];
7779
7780 u8 syndrome[0x20];
7781
7782 u8 reserved_at_40[0x8];
7783 u8 rmpn[0x18];
7784
7785 u8 reserved_at_60[0x20];
7786 };
7787
7788 struct mlx5_ifc_create_rmp_in_bits {
7789 u8 opcode[0x10];
7790 u8 uid[0x10];
7791
7792 u8 reserved_at_20[0x10];
7793 u8 op_mod[0x10];
7794
7795 u8 reserved_at_40[0xc0];
7796
7797 struct mlx5_ifc_rmpc_bits ctx;
7798 };
7799
7800 struct mlx5_ifc_create_qp_out_bits {
7801 u8 status[0x8];
7802 u8 reserved_at_8[0x18];
7803
7804 u8 syndrome[0x20];
7805
7806 u8 reserved_at_40[0x8];
7807 u8 qpn[0x18];
7808
7809 u8 ece[0x20];
7810 };
7811
7812 struct mlx5_ifc_create_qp_in_bits {
7813 u8 opcode[0x10];
7814 u8 uid[0x10];
7815
7816 u8 reserved_at_20[0x10];
7817 u8 op_mod[0x10];
7818
7819 u8 reserved_at_40[0x8];
7820 u8 input_qpn[0x18];
7821
7822 u8 reserved_at_60[0x20];
7823 u8 opt_param_mask[0x20];
7824
7825 u8 ece[0x20];
7826
7827 struct mlx5_ifc_qpc_bits qpc;
7828
7829 u8 reserved_at_800[0x60];
7830
7831 u8 wq_umem_valid[0x1];
7832 u8 reserved_at_861[0x1f];
7833
7834 u8 pas[][0x40];
7835 };
7836
7837 struct mlx5_ifc_create_psv_out_bits {
7838 u8 status[0x8];
7839 u8 reserved_at_8[0x18];
7840
7841 u8 syndrome[0x20];
7842
7843 u8 reserved_at_40[0x40];
7844
7845 u8 reserved_at_80[0x8];
7846 u8 psv0_index[0x18];
7847
7848 u8 reserved_at_a0[0x8];
7849 u8 psv1_index[0x18];
7850
7851 u8 reserved_at_c0[0x8];
7852 u8 psv2_index[0x18];
7853
7854 u8 reserved_at_e0[0x8];
7855 u8 psv3_index[0x18];
7856 };
7857
7858 struct mlx5_ifc_create_psv_in_bits {
7859 u8 opcode[0x10];
7860 u8 reserved_at_10[0x10];
7861
7862 u8 reserved_at_20[0x10];
7863 u8 op_mod[0x10];
7864
7865 u8 num_psv[0x4];
7866 u8 reserved_at_44[0x4];
7867 u8 pd[0x18];
7868
7869 u8 reserved_at_60[0x20];
7870 };
7871
7872 struct mlx5_ifc_create_mkey_out_bits {
7873 u8 status[0x8];
7874 u8 reserved_at_8[0x18];
7875
7876 u8 syndrome[0x20];
7877
7878 u8 reserved_at_40[0x8];
7879 u8 mkey_index[0x18];
7880
7881 u8 reserved_at_60[0x20];
7882 };
7883
7884 struct mlx5_ifc_create_mkey_in_bits {
7885 u8 opcode[0x10];
7886 u8 uid[0x10];
7887
7888 u8 reserved_at_20[0x10];
7889 u8 op_mod[0x10];
7890
7891 u8 reserved_at_40[0x20];
7892
7893 u8 pg_access[0x1];
7894 u8 mkey_umem_valid[0x1];
7895 u8 reserved_at_62[0x1e];
7896
7897 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7898
7899 u8 reserved_at_280[0x80];
7900
7901 u8 translations_octword_actual_size[0x20];
7902
7903 u8 reserved_at_320[0x560];
7904
7905 u8 klm_pas_mtt[][0x20];
7906 };
7907
7908 enum {
7909 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7910 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7911 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7912 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7913 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7914 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7915 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7916 };
7917
7918 struct mlx5_ifc_create_flow_table_out_bits {
7919 u8 status[0x8];
7920 u8 icm_address_63_40[0x18];
7921
7922 u8 syndrome[0x20];
7923
7924 u8 icm_address_39_32[0x8];
7925 u8 table_id[0x18];
7926
7927 u8 icm_address_31_0[0x20];
7928 };
7929
7930 struct mlx5_ifc_create_flow_table_in_bits {
7931 u8 opcode[0x10];
7932 u8 reserved_at_10[0x10];
7933
7934 u8 reserved_at_20[0x10];
7935 u8 op_mod[0x10];
7936
7937 u8 other_vport[0x1];
7938 u8 reserved_at_41[0xf];
7939 u8 vport_number[0x10];
7940
7941 u8 reserved_at_60[0x20];
7942
7943 u8 table_type[0x8];
7944 u8 reserved_at_88[0x18];
7945
7946 u8 reserved_at_a0[0x20];
7947
7948 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7949 };
7950
7951 struct mlx5_ifc_create_flow_group_out_bits {
7952 u8 status[0x8];
7953 u8 reserved_at_8[0x18];
7954
7955 u8 syndrome[0x20];
7956
7957 u8 reserved_at_40[0x8];
7958 u8 group_id[0x18];
7959
7960 u8 reserved_at_60[0x20];
7961 };
7962
7963 enum {
7964 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7965 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7966 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7967 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7968 };
7969
7970 struct mlx5_ifc_create_flow_group_in_bits {
7971 u8 opcode[0x10];
7972 u8 reserved_at_10[0x10];
7973
7974 u8 reserved_at_20[0x10];
7975 u8 op_mod[0x10];
7976
7977 u8 other_vport[0x1];
7978 u8 reserved_at_41[0xf];
7979 u8 vport_number[0x10];
7980
7981 u8 reserved_at_60[0x20];
7982
7983 u8 table_type[0x8];
7984 u8 reserved_at_88[0x18];
7985
7986 u8 reserved_at_a0[0x8];
7987 u8 table_id[0x18];
7988
7989 u8 source_eswitch_owner_vhca_id_valid[0x1];
7990
7991 u8 reserved_at_c1[0x1f];
7992
7993 u8 start_flow_index[0x20];
7994
7995 u8 reserved_at_100[0x20];
7996
7997 u8 end_flow_index[0x20];
7998
7999 u8 reserved_at_140[0xa0];
8000
8001 u8 reserved_at_1e0[0x18];
8002 u8 match_criteria_enable[0x8];
8003
8004 struct mlx5_ifc_fte_match_param_bits match_criteria;
8005
8006 u8 reserved_at_1200[0xe00];
8007 };
8008
8009 struct mlx5_ifc_create_eq_out_bits {
8010 u8 status[0x8];
8011 u8 reserved_at_8[0x18];
8012
8013 u8 syndrome[0x20];
8014
8015 u8 reserved_at_40[0x18];
8016 u8 eq_number[0x8];
8017
8018 u8 reserved_at_60[0x20];
8019 };
8020
8021 struct mlx5_ifc_create_eq_in_bits {
8022 u8 opcode[0x10];
8023 u8 uid[0x10];
8024
8025 u8 reserved_at_20[0x10];
8026 u8 op_mod[0x10];
8027
8028 u8 reserved_at_40[0x40];
8029
8030 struct mlx5_ifc_eqc_bits eq_context_entry;
8031
8032 u8 reserved_at_280[0x40];
8033
8034 u8 event_bitmask[4][0x40];
8035
8036 u8 reserved_at_3c0[0x4c0];
8037
8038 u8 pas[][0x40];
8039 };
8040
8041 struct mlx5_ifc_create_dct_out_bits {
8042 u8 status[0x8];
8043 u8 reserved_at_8[0x18];
8044
8045 u8 syndrome[0x20];
8046
8047 u8 reserved_at_40[0x8];
8048 u8 dctn[0x18];
8049
8050 u8 ece[0x20];
8051 };
8052
8053 struct mlx5_ifc_create_dct_in_bits {
8054 u8 opcode[0x10];
8055 u8 uid[0x10];
8056
8057 u8 reserved_at_20[0x10];
8058 u8 op_mod[0x10];
8059
8060 u8 reserved_at_40[0x40];
8061
8062 struct mlx5_ifc_dctc_bits dct_context_entry;
8063
8064 u8 reserved_at_280[0x180];
8065 };
8066
8067 struct mlx5_ifc_create_cq_out_bits {
8068 u8 status[0x8];
8069 u8 reserved_at_8[0x18];
8070
8071 u8 syndrome[0x20];
8072
8073 u8 reserved_at_40[0x8];
8074 u8 cqn[0x18];
8075
8076 u8 reserved_at_60[0x20];
8077 };
8078
8079 struct mlx5_ifc_create_cq_in_bits {
8080 u8 opcode[0x10];
8081 u8 uid[0x10];
8082
8083 u8 reserved_at_20[0x10];
8084 u8 op_mod[0x10];
8085
8086 u8 reserved_at_40[0x40];
8087
8088 struct mlx5_ifc_cqc_bits cq_context;
8089
8090 u8 reserved_at_280[0x60];
8091
8092 u8 cq_umem_valid[0x1];
8093 u8 reserved_at_2e1[0x59f];
8094
8095 u8 pas[][0x40];
8096 };
8097
8098 struct mlx5_ifc_config_int_moderation_out_bits {
8099 u8 status[0x8];
8100 u8 reserved_at_8[0x18];
8101
8102 u8 syndrome[0x20];
8103
8104 u8 reserved_at_40[0x4];
8105 u8 min_delay[0xc];
8106 u8 int_vector[0x10];
8107
8108 u8 reserved_at_60[0x20];
8109 };
8110
8111 enum {
8112 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8113 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8114 };
8115
8116 struct mlx5_ifc_config_int_moderation_in_bits {
8117 u8 opcode[0x10];
8118 u8 reserved_at_10[0x10];
8119
8120 u8 reserved_at_20[0x10];
8121 u8 op_mod[0x10];
8122
8123 u8 reserved_at_40[0x4];
8124 u8 min_delay[0xc];
8125 u8 int_vector[0x10];
8126
8127 u8 reserved_at_60[0x20];
8128 };
8129
8130 struct mlx5_ifc_attach_to_mcg_out_bits {
8131 u8 status[0x8];
8132 u8 reserved_at_8[0x18];
8133
8134 u8 syndrome[0x20];
8135
8136 u8 reserved_at_40[0x40];
8137 };
8138
8139 struct mlx5_ifc_attach_to_mcg_in_bits {
8140 u8 opcode[0x10];
8141 u8 uid[0x10];
8142
8143 u8 reserved_at_20[0x10];
8144 u8 op_mod[0x10];
8145
8146 u8 reserved_at_40[0x8];
8147 u8 qpn[0x18];
8148
8149 u8 reserved_at_60[0x20];
8150
8151 u8 multicast_gid[16][0x8];
8152 };
8153
8154 struct mlx5_ifc_arm_xrq_out_bits {
8155 u8 status[0x8];
8156 u8 reserved_at_8[0x18];
8157
8158 u8 syndrome[0x20];
8159
8160 u8 reserved_at_40[0x40];
8161 };
8162
8163 struct mlx5_ifc_arm_xrq_in_bits {
8164 u8 opcode[0x10];
8165 u8 reserved_at_10[0x10];
8166
8167 u8 reserved_at_20[0x10];
8168 u8 op_mod[0x10];
8169
8170 u8 reserved_at_40[0x8];
8171 u8 xrqn[0x18];
8172
8173 u8 reserved_at_60[0x10];
8174 u8 lwm[0x10];
8175 };
8176
8177 struct mlx5_ifc_arm_xrc_srq_out_bits {
8178 u8 status[0x8];
8179 u8 reserved_at_8[0x18];
8180
8181 u8 syndrome[0x20];
8182
8183 u8 reserved_at_40[0x40];
8184 };
8185
8186 enum {
8187 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8188 };
8189
8190 struct mlx5_ifc_arm_xrc_srq_in_bits {
8191 u8 opcode[0x10];
8192 u8 uid[0x10];
8193
8194 u8 reserved_at_20[0x10];
8195 u8 op_mod[0x10];
8196
8197 u8 reserved_at_40[0x8];
8198 u8 xrc_srqn[0x18];
8199
8200 u8 reserved_at_60[0x10];
8201 u8 lwm[0x10];
8202 };
8203
8204 struct mlx5_ifc_arm_rq_out_bits {
8205 u8 status[0x8];
8206 u8 reserved_at_8[0x18];
8207
8208 u8 syndrome[0x20];
8209
8210 u8 reserved_at_40[0x40];
8211 };
8212
8213 enum {
8214 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8215 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8216 };
8217
8218 struct mlx5_ifc_arm_rq_in_bits {
8219 u8 opcode[0x10];
8220 u8 uid[0x10];
8221
8222 u8 reserved_at_20[0x10];
8223 u8 op_mod[0x10];
8224
8225 u8 reserved_at_40[0x8];
8226 u8 srq_number[0x18];
8227
8228 u8 reserved_at_60[0x10];
8229 u8 lwm[0x10];
8230 };
8231
8232 struct mlx5_ifc_arm_dct_out_bits {
8233 u8 status[0x8];
8234 u8 reserved_at_8[0x18];
8235
8236 u8 syndrome[0x20];
8237
8238 u8 reserved_at_40[0x40];
8239 };
8240
8241 struct mlx5_ifc_arm_dct_in_bits {
8242 u8 opcode[0x10];
8243 u8 reserved_at_10[0x10];
8244
8245 u8 reserved_at_20[0x10];
8246 u8 op_mod[0x10];
8247
8248 u8 reserved_at_40[0x8];
8249 u8 dct_number[0x18];
8250
8251 u8 reserved_at_60[0x20];
8252 };
8253
8254 struct mlx5_ifc_alloc_xrcd_out_bits {
8255 u8 status[0x8];
8256 u8 reserved_at_8[0x18];
8257
8258 u8 syndrome[0x20];
8259
8260 u8 reserved_at_40[0x8];
8261 u8 xrcd[0x18];
8262
8263 u8 reserved_at_60[0x20];
8264 };
8265
8266 struct mlx5_ifc_alloc_xrcd_in_bits {
8267 u8 opcode[0x10];
8268 u8 uid[0x10];
8269
8270 u8 reserved_at_20[0x10];
8271 u8 op_mod[0x10];
8272
8273 u8 reserved_at_40[0x40];
8274 };
8275
8276 struct mlx5_ifc_alloc_uar_out_bits {
8277 u8 status[0x8];
8278 u8 reserved_at_8[0x18];
8279
8280 u8 syndrome[0x20];
8281
8282 u8 reserved_at_40[0x8];
8283 u8 uar[0x18];
8284
8285 u8 reserved_at_60[0x20];
8286 };
8287
8288 struct mlx5_ifc_alloc_uar_in_bits {
8289 u8 opcode[0x10];
8290 u8 reserved_at_10[0x10];
8291
8292 u8 reserved_at_20[0x10];
8293 u8 op_mod[0x10];
8294
8295 u8 reserved_at_40[0x40];
8296 };
8297
8298 struct mlx5_ifc_alloc_transport_domain_out_bits {
8299 u8 status[0x8];
8300 u8 reserved_at_8[0x18];
8301
8302 u8 syndrome[0x20];
8303
8304 u8 reserved_at_40[0x8];
8305 u8 transport_domain[0x18];
8306
8307 u8 reserved_at_60[0x20];
8308 };
8309
8310 struct mlx5_ifc_alloc_transport_domain_in_bits {
8311 u8 opcode[0x10];
8312 u8 uid[0x10];
8313
8314 u8 reserved_at_20[0x10];
8315 u8 op_mod[0x10];
8316
8317 u8 reserved_at_40[0x40];
8318 };
8319
8320 struct mlx5_ifc_alloc_q_counter_out_bits {
8321 u8 status[0x8];
8322 u8 reserved_at_8[0x18];
8323
8324 u8 syndrome[0x20];
8325
8326 u8 reserved_at_40[0x18];
8327 u8 counter_set_id[0x8];
8328
8329 u8 reserved_at_60[0x20];
8330 };
8331
8332 struct mlx5_ifc_alloc_q_counter_in_bits {
8333 u8 opcode[0x10];
8334 u8 uid[0x10];
8335
8336 u8 reserved_at_20[0x10];
8337 u8 op_mod[0x10];
8338
8339 u8 reserved_at_40[0x40];
8340 };
8341
8342 struct mlx5_ifc_alloc_pd_out_bits {
8343 u8 status[0x8];
8344 u8 reserved_at_8[0x18];
8345
8346 u8 syndrome[0x20];
8347
8348 u8 reserved_at_40[0x8];
8349 u8 pd[0x18];
8350
8351 u8 reserved_at_60[0x20];
8352 };
8353
8354 struct mlx5_ifc_alloc_pd_in_bits {
8355 u8 opcode[0x10];
8356 u8 uid[0x10];
8357
8358 u8 reserved_at_20[0x10];
8359 u8 op_mod[0x10];
8360
8361 u8 reserved_at_40[0x40];
8362 };
8363
8364 struct mlx5_ifc_alloc_flow_counter_out_bits {
8365 u8 status[0x8];
8366 u8 reserved_at_8[0x18];
8367
8368 u8 syndrome[0x20];
8369
8370 u8 flow_counter_id[0x20];
8371
8372 u8 reserved_at_60[0x20];
8373 };
8374
8375 struct mlx5_ifc_alloc_flow_counter_in_bits {
8376 u8 opcode[0x10];
8377 u8 reserved_at_10[0x10];
8378
8379 u8 reserved_at_20[0x10];
8380 u8 op_mod[0x10];
8381
8382 u8 reserved_at_40[0x38];
8383 u8 flow_counter_bulk[0x8];
8384 };
8385
8386 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8387 u8 status[0x8];
8388 u8 reserved_at_8[0x18];
8389
8390 u8 syndrome[0x20];
8391
8392 u8 reserved_at_40[0x40];
8393 };
8394
8395 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8396 u8 opcode[0x10];
8397 u8 reserved_at_10[0x10];
8398
8399 u8 reserved_at_20[0x10];
8400 u8 op_mod[0x10];
8401
8402 u8 reserved_at_40[0x20];
8403
8404 u8 reserved_at_60[0x10];
8405 u8 vxlan_udp_port[0x10];
8406 };
8407
8408 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8409 u8 status[0x8];
8410 u8 reserved_at_8[0x18];
8411
8412 u8 syndrome[0x20];
8413
8414 u8 reserved_at_40[0x40];
8415 };
8416
8417 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8418 u8 rate_limit[0x20];
8419
8420 u8 burst_upper_bound[0x20];
8421
8422 u8 reserved_at_40[0x10];
8423 u8 typical_packet_size[0x10];
8424
8425 u8 reserved_at_60[0x120];
8426 };
8427
8428 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8429 u8 opcode[0x10];
8430 u8 uid[0x10];
8431
8432 u8 reserved_at_20[0x10];
8433 u8 op_mod[0x10];
8434
8435 u8 reserved_at_40[0x10];
8436 u8 rate_limit_index[0x10];
8437
8438 u8 reserved_at_60[0x20];
8439
8440 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8441 };
8442
8443 struct mlx5_ifc_access_register_out_bits {
8444 u8 status[0x8];
8445 u8 reserved_at_8[0x18];
8446
8447 u8 syndrome[0x20];
8448
8449 u8 reserved_at_40[0x40];
8450
8451 u8 register_data[][0x20];
8452 };
8453
8454 enum {
8455 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8456 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8457 };
8458
8459 struct mlx5_ifc_access_register_in_bits {
8460 u8 opcode[0x10];
8461 u8 reserved_at_10[0x10];
8462
8463 u8 reserved_at_20[0x10];
8464 u8 op_mod[0x10];
8465
8466 u8 reserved_at_40[0x10];
8467 u8 register_id[0x10];
8468
8469 u8 argument[0x20];
8470
8471 u8 register_data[][0x20];
8472 };
8473
8474 struct mlx5_ifc_sltp_reg_bits {
8475 u8 status[0x4];
8476 u8 version[0x4];
8477 u8 local_port[0x8];
8478 u8 pnat[0x2];
8479 u8 reserved_at_12[0x2];
8480 u8 lane[0x4];
8481 u8 reserved_at_18[0x8];
8482
8483 u8 reserved_at_20[0x20];
8484
8485 u8 reserved_at_40[0x7];
8486 u8 polarity[0x1];
8487 u8 ob_tap0[0x8];
8488 u8 ob_tap1[0x8];
8489 u8 ob_tap2[0x8];
8490
8491 u8 reserved_at_60[0xc];
8492 u8 ob_preemp_mode[0x4];
8493 u8 ob_reg[0x8];
8494 u8 ob_bias[0x8];
8495
8496 u8 reserved_at_80[0x20];
8497 };
8498
8499 struct mlx5_ifc_slrg_reg_bits {
8500 u8 status[0x4];
8501 u8 version[0x4];
8502 u8 local_port[0x8];
8503 u8 pnat[0x2];
8504 u8 reserved_at_12[0x2];
8505 u8 lane[0x4];
8506 u8 reserved_at_18[0x8];
8507
8508 u8 time_to_link_up[0x10];
8509 u8 reserved_at_30[0xc];
8510 u8 grade_lane_speed[0x4];
8511
8512 u8 grade_version[0x8];
8513 u8 grade[0x18];
8514
8515 u8 reserved_at_60[0x4];
8516 u8 height_grade_type[0x4];
8517 u8 height_grade[0x18];
8518
8519 u8 height_dz[0x10];
8520 u8 height_dv[0x10];
8521
8522 u8 reserved_at_a0[0x10];
8523 u8 height_sigma[0x10];
8524
8525 u8 reserved_at_c0[0x20];
8526
8527 u8 reserved_at_e0[0x4];
8528 u8 phase_grade_type[0x4];
8529 u8 phase_grade[0x18];
8530
8531 u8 reserved_at_100[0x8];
8532 u8 phase_eo_pos[0x8];
8533 u8 reserved_at_110[0x8];
8534 u8 phase_eo_neg[0x8];
8535
8536 u8 ffe_set_tested[0x10];
8537 u8 test_errors_per_lane[0x10];
8538 };
8539
8540 struct mlx5_ifc_pvlc_reg_bits {
8541 u8 reserved_at_0[0x8];
8542 u8 local_port[0x8];
8543 u8 reserved_at_10[0x10];
8544
8545 u8 reserved_at_20[0x1c];
8546 u8 vl_hw_cap[0x4];
8547
8548 u8 reserved_at_40[0x1c];
8549 u8 vl_admin[0x4];
8550
8551 u8 reserved_at_60[0x1c];
8552 u8 vl_operational[0x4];
8553 };
8554
8555 struct mlx5_ifc_pude_reg_bits {
8556 u8 swid[0x8];
8557 u8 local_port[0x8];
8558 u8 reserved_at_10[0x4];
8559 u8 admin_status[0x4];
8560 u8 reserved_at_18[0x4];
8561 u8 oper_status[0x4];
8562
8563 u8 reserved_at_20[0x60];
8564 };
8565
8566 struct mlx5_ifc_ptys_reg_bits {
8567 u8 reserved_at_0[0x1];
8568 u8 an_disable_admin[0x1];
8569 u8 an_disable_cap[0x1];
8570 u8 reserved_at_3[0x5];
8571 u8 local_port[0x8];
8572 u8 reserved_at_10[0xd];
8573 u8 proto_mask[0x3];
8574
8575 u8 an_status[0x4];
8576 u8 reserved_at_24[0xc];
8577 u8 data_rate_oper[0x10];
8578
8579 u8 ext_eth_proto_capability[0x20];
8580
8581 u8 eth_proto_capability[0x20];
8582
8583 u8 ib_link_width_capability[0x10];
8584 u8 ib_proto_capability[0x10];
8585
8586 u8 ext_eth_proto_admin[0x20];
8587
8588 u8 eth_proto_admin[0x20];
8589
8590 u8 ib_link_width_admin[0x10];
8591 u8 ib_proto_admin[0x10];
8592
8593 u8 ext_eth_proto_oper[0x20];
8594
8595 u8 eth_proto_oper[0x20];
8596
8597 u8 ib_link_width_oper[0x10];
8598 u8 ib_proto_oper[0x10];
8599
8600 u8 reserved_at_160[0x1c];
8601 u8 connector_type[0x4];
8602
8603 u8 eth_proto_lp_advertise[0x20];
8604
8605 u8 reserved_at_1a0[0x60];
8606 };
8607
8608 struct mlx5_ifc_mlcr_reg_bits {
8609 u8 reserved_at_0[0x8];
8610 u8 local_port[0x8];
8611 u8 reserved_at_10[0x20];
8612
8613 u8 beacon_duration[0x10];
8614 u8 reserved_at_40[0x10];
8615
8616 u8 beacon_remain[0x10];
8617 };
8618
8619 struct mlx5_ifc_ptas_reg_bits {
8620 u8 reserved_at_0[0x20];
8621
8622 u8 algorithm_options[0x10];
8623 u8 reserved_at_30[0x4];
8624 u8 repetitions_mode[0x4];
8625 u8 num_of_repetitions[0x8];
8626
8627 u8 grade_version[0x8];
8628 u8 height_grade_type[0x4];
8629 u8 phase_grade_type[0x4];
8630 u8 height_grade_weight[0x8];
8631 u8 phase_grade_weight[0x8];
8632
8633 u8 gisim_measure_bits[0x10];
8634 u8 adaptive_tap_measure_bits[0x10];
8635
8636 u8 ber_bath_high_error_threshold[0x10];
8637 u8 ber_bath_mid_error_threshold[0x10];
8638
8639 u8 ber_bath_low_error_threshold[0x10];
8640 u8 one_ratio_high_threshold[0x10];
8641
8642 u8 one_ratio_high_mid_threshold[0x10];
8643 u8 one_ratio_low_mid_threshold[0x10];
8644
8645 u8 one_ratio_low_threshold[0x10];
8646 u8 ndeo_error_threshold[0x10];
8647
8648 u8 mixer_offset_step_size[0x10];
8649 u8 reserved_at_110[0x8];
8650 u8 mix90_phase_for_voltage_bath[0x8];
8651
8652 u8 mixer_offset_start[0x10];
8653 u8 mixer_offset_end[0x10];
8654
8655 u8 reserved_at_140[0x15];
8656 u8 ber_test_time[0xb];
8657 };
8658
8659 struct mlx5_ifc_pspa_reg_bits {
8660 u8 swid[0x8];
8661 u8 local_port[0x8];
8662 u8 sub_port[0x8];
8663 u8 reserved_at_18[0x8];
8664
8665 u8 reserved_at_20[0x20];
8666 };
8667
8668 struct mlx5_ifc_pqdr_reg_bits {
8669 u8 reserved_at_0[0x8];
8670 u8 local_port[0x8];
8671 u8 reserved_at_10[0x5];
8672 u8 prio[0x3];
8673 u8 reserved_at_18[0x6];
8674 u8 mode[0x2];
8675
8676 u8 reserved_at_20[0x20];
8677
8678 u8 reserved_at_40[0x10];
8679 u8 min_threshold[0x10];
8680
8681 u8 reserved_at_60[0x10];
8682 u8 max_threshold[0x10];
8683
8684 u8 reserved_at_80[0x10];
8685 u8 mark_probability_denominator[0x10];
8686
8687 u8 reserved_at_a0[0x60];
8688 };
8689
8690 struct mlx5_ifc_ppsc_reg_bits {
8691 u8 reserved_at_0[0x8];
8692 u8 local_port[0x8];
8693 u8 reserved_at_10[0x10];
8694
8695 u8 reserved_at_20[0x60];
8696
8697 u8 reserved_at_80[0x1c];
8698 u8 wrps_admin[0x4];
8699
8700 u8 reserved_at_a0[0x1c];
8701 u8 wrps_status[0x4];
8702
8703 u8 reserved_at_c0[0x8];
8704 u8 up_threshold[0x8];
8705 u8 reserved_at_d0[0x8];
8706 u8 down_threshold[0x8];
8707
8708 u8 reserved_at_e0[0x20];
8709
8710 u8 reserved_at_100[0x1c];
8711 u8 srps_admin[0x4];
8712
8713 u8 reserved_at_120[0x1c];
8714 u8 srps_status[0x4];
8715
8716 u8 reserved_at_140[0x40];
8717 };
8718
8719 struct mlx5_ifc_pplr_reg_bits {
8720 u8 reserved_at_0[0x8];
8721 u8 local_port[0x8];
8722 u8 reserved_at_10[0x10];
8723
8724 u8 reserved_at_20[0x8];
8725 u8 lb_cap[0x8];
8726 u8 reserved_at_30[0x8];
8727 u8 lb_en[0x8];
8728 };
8729
8730 struct mlx5_ifc_pplm_reg_bits {
8731 u8 reserved_at_0[0x8];
8732 u8 local_port[0x8];
8733 u8 reserved_at_10[0x10];
8734
8735 u8 reserved_at_20[0x20];
8736
8737 u8 port_profile_mode[0x8];
8738 u8 static_port_profile[0x8];
8739 u8 active_port_profile[0x8];
8740 u8 reserved_at_58[0x8];
8741
8742 u8 retransmission_active[0x8];
8743 u8 fec_mode_active[0x18];
8744
8745 u8 rs_fec_correction_bypass_cap[0x4];
8746 u8 reserved_at_84[0x8];
8747 u8 fec_override_cap_56g[0x4];
8748 u8 fec_override_cap_100g[0x4];
8749 u8 fec_override_cap_50g[0x4];
8750 u8 fec_override_cap_25g[0x4];
8751 u8 fec_override_cap_10g_40g[0x4];
8752
8753 u8 rs_fec_correction_bypass_admin[0x4];
8754 u8 reserved_at_a4[0x8];
8755 u8 fec_override_admin_56g[0x4];
8756 u8 fec_override_admin_100g[0x4];
8757 u8 fec_override_admin_50g[0x4];
8758 u8 fec_override_admin_25g[0x4];
8759 u8 fec_override_admin_10g_40g[0x4];
8760
8761 u8 fec_override_cap_400g_8x[0x10];
8762 u8 fec_override_cap_200g_4x[0x10];
8763
8764 u8 fec_override_cap_100g_2x[0x10];
8765 u8 fec_override_cap_50g_1x[0x10];
8766
8767 u8 fec_override_admin_400g_8x[0x10];
8768 u8 fec_override_admin_200g_4x[0x10];
8769
8770 u8 fec_override_admin_100g_2x[0x10];
8771 u8 fec_override_admin_50g_1x[0x10];
8772
8773 u8 reserved_at_140[0x140];
8774 };
8775
8776 struct mlx5_ifc_ppcnt_reg_bits {
8777 u8 swid[0x8];
8778 u8 local_port[0x8];
8779 u8 pnat[0x2];
8780 u8 reserved_at_12[0x8];
8781 u8 grp[0x6];
8782
8783 u8 clr[0x1];
8784 u8 reserved_at_21[0x1c];
8785 u8 prio_tc[0x3];
8786
8787 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8788 };
8789
8790 struct mlx5_ifc_mpein_reg_bits {
8791 u8 reserved_at_0[0x2];
8792 u8 depth[0x6];
8793 u8 pcie_index[0x8];
8794 u8 node[0x8];
8795 u8 reserved_at_18[0x8];
8796
8797 u8 capability_mask[0x20];
8798
8799 u8 reserved_at_40[0x8];
8800 u8 link_width_enabled[0x8];
8801 u8 link_speed_enabled[0x10];
8802
8803 u8 lane0_physical_position[0x8];
8804 u8 link_width_active[0x8];
8805 u8 link_speed_active[0x10];
8806
8807 u8 num_of_pfs[0x10];
8808 u8 num_of_vfs[0x10];
8809
8810 u8 bdf0[0x10];
8811 u8 reserved_at_b0[0x10];
8812
8813 u8 max_read_request_size[0x4];
8814 u8 max_payload_size[0x4];
8815 u8 reserved_at_c8[0x5];
8816 u8 pwr_status[0x3];
8817 u8 port_type[0x4];
8818 u8 reserved_at_d4[0xb];
8819 u8 lane_reversal[0x1];
8820
8821 u8 reserved_at_e0[0x14];
8822 u8 pci_power[0xc];
8823
8824 u8 reserved_at_100[0x20];
8825
8826 u8 device_status[0x10];
8827 u8 port_state[0x8];
8828 u8 reserved_at_138[0x8];
8829
8830 u8 reserved_at_140[0x10];
8831 u8 receiver_detect_result[0x10];
8832
8833 u8 reserved_at_160[0x20];
8834 };
8835
8836 struct mlx5_ifc_mpcnt_reg_bits {
8837 u8 reserved_at_0[0x8];
8838 u8 pcie_index[0x8];
8839 u8 reserved_at_10[0xa];
8840 u8 grp[0x6];
8841
8842 u8 clr[0x1];
8843 u8 reserved_at_21[0x1f];
8844
8845 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8846 };
8847
8848 struct mlx5_ifc_ppad_reg_bits {
8849 u8 reserved_at_0[0x3];
8850 u8 single_mac[0x1];
8851 u8 reserved_at_4[0x4];
8852 u8 local_port[0x8];
8853 u8 mac_47_32[0x10];
8854
8855 u8 mac_31_0[0x20];
8856
8857 u8 reserved_at_40[0x40];
8858 };
8859
8860 struct mlx5_ifc_pmtu_reg_bits {
8861 u8 reserved_at_0[0x8];
8862 u8 local_port[0x8];
8863 u8 reserved_at_10[0x10];
8864
8865 u8 max_mtu[0x10];
8866 u8 reserved_at_30[0x10];
8867
8868 u8 admin_mtu[0x10];
8869 u8 reserved_at_50[0x10];
8870
8871 u8 oper_mtu[0x10];
8872 u8 reserved_at_70[0x10];
8873 };
8874
8875 struct mlx5_ifc_pmpr_reg_bits {
8876 u8 reserved_at_0[0x8];
8877 u8 module[0x8];
8878 u8 reserved_at_10[0x10];
8879
8880 u8 reserved_at_20[0x18];
8881 u8 attenuation_5g[0x8];
8882
8883 u8 reserved_at_40[0x18];
8884 u8 attenuation_7g[0x8];
8885
8886 u8 reserved_at_60[0x18];
8887 u8 attenuation_12g[0x8];
8888 };
8889
8890 struct mlx5_ifc_pmpe_reg_bits {
8891 u8 reserved_at_0[0x8];
8892 u8 module[0x8];
8893 u8 reserved_at_10[0xc];
8894 u8 module_status[0x4];
8895
8896 u8 reserved_at_20[0x60];
8897 };
8898
8899 struct mlx5_ifc_pmpc_reg_bits {
8900 u8 module_state_updated[32][0x8];
8901 };
8902
8903 struct mlx5_ifc_pmlpn_reg_bits {
8904 u8 reserved_at_0[0x4];
8905 u8 mlpn_status[0x4];
8906 u8 local_port[0x8];
8907 u8 reserved_at_10[0x10];
8908
8909 u8 e[0x1];
8910 u8 reserved_at_21[0x1f];
8911 };
8912
8913 struct mlx5_ifc_pmlp_reg_bits {
8914 u8 rxtx[0x1];
8915 u8 reserved_at_1[0x7];
8916 u8 local_port[0x8];
8917 u8 reserved_at_10[0x8];
8918 u8 width[0x8];
8919
8920 u8 lane0_module_mapping[0x20];
8921
8922 u8 lane1_module_mapping[0x20];
8923
8924 u8 lane2_module_mapping[0x20];
8925
8926 u8 lane3_module_mapping[0x20];
8927
8928 u8 reserved_at_a0[0x160];
8929 };
8930
8931 struct mlx5_ifc_pmaos_reg_bits {
8932 u8 reserved_at_0[0x8];
8933 u8 module[0x8];
8934 u8 reserved_at_10[0x4];
8935 u8 admin_status[0x4];
8936 u8 reserved_at_18[0x4];
8937 u8 oper_status[0x4];
8938
8939 u8 ase[0x1];
8940 u8 ee[0x1];
8941 u8 reserved_at_22[0x1c];
8942 u8 e[0x2];
8943
8944 u8 reserved_at_40[0x40];
8945 };
8946
8947 struct mlx5_ifc_plpc_reg_bits {
8948 u8 reserved_at_0[0x4];
8949 u8 profile_id[0xc];
8950 u8 reserved_at_10[0x4];
8951 u8 proto_mask[0x4];
8952 u8 reserved_at_18[0x8];
8953
8954 u8 reserved_at_20[0x10];
8955 u8 lane_speed[0x10];
8956
8957 u8 reserved_at_40[0x17];
8958 u8 lpbf[0x1];
8959 u8 fec_mode_policy[0x8];
8960
8961 u8 retransmission_capability[0x8];
8962 u8 fec_mode_capability[0x18];
8963
8964 u8 retransmission_support_admin[0x8];
8965 u8 fec_mode_support_admin[0x18];
8966
8967 u8 retransmission_request_admin[0x8];
8968 u8 fec_mode_request_admin[0x18];
8969
8970 u8 reserved_at_c0[0x80];
8971 };
8972
8973 struct mlx5_ifc_plib_reg_bits {
8974 u8 reserved_at_0[0x8];
8975 u8 local_port[0x8];
8976 u8 reserved_at_10[0x8];
8977 u8 ib_port[0x8];
8978
8979 u8 reserved_at_20[0x60];
8980 };
8981
8982 struct mlx5_ifc_plbf_reg_bits {
8983 u8 reserved_at_0[0x8];
8984 u8 local_port[0x8];
8985 u8 reserved_at_10[0xd];
8986 u8 lbf_mode[0x3];
8987
8988 u8 reserved_at_20[0x20];
8989 };
8990
8991 struct mlx5_ifc_pipg_reg_bits {
8992 u8 reserved_at_0[0x8];
8993 u8 local_port[0x8];
8994 u8 reserved_at_10[0x10];
8995
8996 u8 dic[0x1];
8997 u8 reserved_at_21[0x19];
8998 u8 ipg[0x4];
8999 u8 reserved_at_3e[0x2];
9000 };
9001
9002 struct mlx5_ifc_pifr_reg_bits {
9003 u8 reserved_at_0[0x8];
9004 u8 local_port[0x8];
9005 u8 reserved_at_10[0x10];
9006
9007 u8 reserved_at_20[0xe0];
9008
9009 u8 port_filter[8][0x20];
9010
9011 u8 port_filter_update_en[8][0x20];
9012 };
9013
9014 struct mlx5_ifc_pfcc_reg_bits {
9015 u8 reserved_at_0[0x8];
9016 u8 local_port[0x8];
9017 u8 reserved_at_10[0xb];
9018 u8 ppan_mask_n[0x1];
9019 u8 minor_stall_mask[0x1];
9020 u8 critical_stall_mask[0x1];
9021 u8 reserved_at_1e[0x2];
9022
9023 u8 ppan[0x4];
9024 u8 reserved_at_24[0x4];
9025 u8 prio_mask_tx[0x8];
9026 u8 reserved_at_30[0x8];
9027 u8 prio_mask_rx[0x8];
9028
9029 u8 pptx[0x1];
9030 u8 aptx[0x1];
9031 u8 pptx_mask_n[0x1];
9032 u8 reserved_at_43[0x5];
9033 u8 pfctx[0x8];
9034 u8 reserved_at_50[0x10];
9035
9036 u8 pprx[0x1];
9037 u8 aprx[0x1];
9038 u8 pprx_mask_n[0x1];
9039 u8 reserved_at_63[0x5];
9040 u8 pfcrx[0x8];
9041 u8 reserved_at_70[0x10];
9042
9043 u8 device_stall_minor_watermark[0x10];
9044 u8 device_stall_critical_watermark[0x10];
9045
9046 u8 reserved_at_a0[0x60];
9047 };
9048
9049 struct mlx5_ifc_pelc_reg_bits {
9050 u8 op[0x4];
9051 u8 reserved_at_4[0x4];
9052 u8 local_port[0x8];
9053 u8 reserved_at_10[0x10];
9054
9055 u8 op_admin[0x8];
9056 u8 op_capability[0x8];
9057 u8 op_request[0x8];
9058 u8 op_active[0x8];
9059
9060 u8 admin[0x40];
9061
9062 u8 capability[0x40];
9063
9064 u8 request[0x40];
9065
9066 u8 active[0x40];
9067
9068 u8 reserved_at_140[0x80];
9069 };
9070
9071 struct mlx5_ifc_peir_reg_bits {
9072 u8 reserved_at_0[0x8];
9073 u8 local_port[0x8];
9074 u8 reserved_at_10[0x10];
9075
9076 u8 reserved_at_20[0xc];
9077 u8 error_count[0x4];
9078 u8 reserved_at_30[0x10];
9079
9080 u8 reserved_at_40[0xc];
9081 u8 lane[0x4];
9082 u8 reserved_at_50[0x8];
9083 u8 error_type[0x8];
9084 };
9085
9086 struct mlx5_ifc_mpegc_reg_bits {
9087 u8 reserved_at_0[0x30];
9088 u8 field_select[0x10];
9089
9090 u8 tx_overflow_sense[0x1];
9091 u8 mark_cqe[0x1];
9092 u8 mark_cnp[0x1];
9093 u8 reserved_at_43[0x1b];
9094 u8 tx_lossy_overflow_oper[0x2];
9095
9096 u8 reserved_at_60[0x100];
9097 };
9098
9099 struct mlx5_ifc_pcam_enhanced_features_bits {
9100 u8 reserved_at_0[0x68];
9101 u8 fec_50G_per_lane_in_pplm[0x1];
9102 u8 reserved_at_69[0x4];
9103 u8 rx_icrc_encapsulated_counter[0x1];
9104 u8 reserved_at_6e[0x4];
9105 u8 ptys_extended_ethernet[0x1];
9106 u8 reserved_at_73[0x3];
9107 u8 pfcc_mask[0x1];
9108 u8 reserved_at_77[0x3];
9109 u8 per_lane_error_counters[0x1];
9110 u8 rx_buffer_fullness_counters[0x1];
9111 u8 ptys_connector_type[0x1];
9112 u8 reserved_at_7d[0x1];
9113 u8 ppcnt_discard_group[0x1];
9114 u8 ppcnt_statistical_group[0x1];
9115 };
9116
9117 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9118 u8 port_access_reg_cap_mask_127_to_96[0x20];
9119 u8 port_access_reg_cap_mask_95_to_64[0x20];
9120
9121 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9122 u8 pplm[0x1];
9123 u8 port_access_reg_cap_mask_34_to_32[0x3];
9124
9125 u8 port_access_reg_cap_mask_31_to_13[0x13];
9126 u8 pbmc[0x1];
9127 u8 pptb[0x1];
9128 u8 port_access_reg_cap_mask_10_to_09[0x2];
9129 u8 ppcnt[0x1];
9130 u8 port_access_reg_cap_mask_07_to_00[0x8];
9131 };
9132
9133 struct mlx5_ifc_pcam_reg_bits {
9134 u8 reserved_at_0[0x8];
9135 u8 feature_group[0x8];
9136 u8 reserved_at_10[0x8];
9137 u8 access_reg_group[0x8];
9138
9139 u8 reserved_at_20[0x20];
9140
9141 union {
9142 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9143 u8 reserved_at_0[0x80];
9144 } port_access_reg_cap_mask;
9145
9146 u8 reserved_at_c0[0x80];
9147
9148 union {
9149 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9150 u8 reserved_at_0[0x80];
9151 } feature_cap_mask;
9152
9153 u8 reserved_at_1c0[0xc0];
9154 };
9155
9156 struct mlx5_ifc_mcam_enhanced_features_bits {
9157 u8 reserved_at_0[0x6e];
9158 u8 pci_status_and_power[0x1];
9159 u8 reserved_at_6f[0x5];
9160 u8 mark_tx_action_cnp[0x1];
9161 u8 mark_tx_action_cqe[0x1];
9162 u8 dynamic_tx_overflow[0x1];
9163 u8 reserved_at_77[0x4];
9164 u8 pcie_outbound_stalled[0x1];
9165 u8 tx_overflow_buffer_pkt[0x1];
9166 u8 mtpps_enh_out_per_adj[0x1];
9167 u8 mtpps_fs[0x1];
9168 u8 pcie_performance_group[0x1];
9169 };
9170
9171 struct mlx5_ifc_mcam_access_reg_bits {
9172 u8 reserved_at_0[0x1c];
9173 u8 mcda[0x1];
9174 u8 mcc[0x1];
9175 u8 mcqi[0x1];
9176 u8 mcqs[0x1];
9177
9178 u8 regs_95_to_87[0x9];
9179 u8 mpegc[0x1];
9180 u8 regs_85_to_68[0x12];
9181 u8 tracer_registers[0x4];
9182
9183 u8 regs_63_to_32[0x20];
9184 u8 regs_31_to_0[0x20];
9185 };
9186
9187 struct mlx5_ifc_mcam_access_reg_bits1 {
9188 u8 regs_127_to_96[0x20];
9189
9190 u8 regs_95_to_64[0x20];
9191
9192 u8 regs_63_to_32[0x20];
9193
9194 u8 regs_31_to_0[0x20];
9195 };
9196
9197 struct mlx5_ifc_mcam_access_reg_bits2 {
9198 u8 regs_127_to_99[0x1d];
9199 u8 mirc[0x1];
9200 u8 regs_97_to_96[0x2];
9201
9202 u8 regs_95_to_64[0x20];
9203
9204 u8 regs_63_to_32[0x20];
9205
9206 u8 regs_31_to_0[0x20];
9207 };
9208
9209 struct mlx5_ifc_mcam_reg_bits {
9210 u8 reserved_at_0[0x8];
9211 u8 feature_group[0x8];
9212 u8 reserved_at_10[0x8];
9213 u8 access_reg_group[0x8];
9214
9215 u8 reserved_at_20[0x20];
9216
9217 union {
9218 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9219 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9220 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9221 u8 reserved_at_0[0x80];
9222 } mng_access_reg_cap_mask;
9223
9224 u8 reserved_at_c0[0x80];
9225
9226 union {
9227 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9228 u8 reserved_at_0[0x80];
9229 } mng_feature_cap_mask;
9230
9231 u8 reserved_at_1c0[0x80];
9232 };
9233
9234 struct mlx5_ifc_qcam_access_reg_cap_mask {
9235 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9236 u8 qpdpm[0x1];
9237 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9238 u8 qdpm[0x1];
9239 u8 qpts[0x1];
9240 u8 qcap[0x1];
9241 u8 qcam_access_reg_cap_mask_0[0x1];
9242 };
9243
9244 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9245 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9246 u8 qpts_trust_both[0x1];
9247 };
9248
9249 struct mlx5_ifc_qcam_reg_bits {
9250 u8 reserved_at_0[0x8];
9251 u8 feature_group[0x8];
9252 u8 reserved_at_10[0x8];
9253 u8 access_reg_group[0x8];
9254 u8 reserved_at_20[0x20];
9255
9256 union {
9257 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9258 u8 reserved_at_0[0x80];
9259 } qos_access_reg_cap_mask;
9260
9261 u8 reserved_at_c0[0x80];
9262
9263 union {
9264 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9265 u8 reserved_at_0[0x80];
9266 } qos_feature_cap_mask;
9267
9268 u8 reserved_at_1c0[0x80];
9269 };
9270
9271 struct mlx5_ifc_core_dump_reg_bits {
9272 u8 reserved_at_0[0x18];
9273 u8 core_dump_type[0x8];
9274
9275 u8 reserved_at_20[0x30];
9276 u8 vhca_id[0x10];
9277
9278 u8 reserved_at_60[0x8];
9279 u8 qpn[0x18];
9280 u8 reserved_at_80[0x180];
9281 };
9282
9283 struct mlx5_ifc_pcap_reg_bits {
9284 u8 reserved_at_0[0x8];
9285 u8 local_port[0x8];
9286 u8 reserved_at_10[0x10];
9287
9288 u8 port_capability_mask[4][0x20];
9289 };
9290
9291 struct mlx5_ifc_paos_reg_bits {
9292 u8 swid[0x8];
9293 u8 local_port[0x8];
9294 u8 reserved_at_10[0x4];
9295 u8 admin_status[0x4];
9296 u8 reserved_at_18[0x4];
9297 u8 oper_status[0x4];
9298
9299 u8 ase[0x1];
9300 u8 ee[0x1];
9301 u8 reserved_at_22[0x1c];
9302 u8 e[0x2];
9303
9304 u8 reserved_at_40[0x40];
9305 };
9306
9307 struct mlx5_ifc_pamp_reg_bits {
9308 u8 reserved_at_0[0x8];
9309 u8 opamp_group[0x8];
9310 u8 reserved_at_10[0xc];
9311 u8 opamp_group_type[0x4];
9312
9313 u8 start_index[0x10];
9314 u8 reserved_at_30[0x4];
9315 u8 num_of_indices[0xc];
9316
9317 u8 index_data[18][0x10];
9318 };
9319
9320 struct mlx5_ifc_pcmr_reg_bits {
9321 u8 reserved_at_0[0x8];
9322 u8 local_port[0x8];
9323 u8 reserved_at_10[0x10];
9324 u8 entropy_force_cap[0x1];
9325 u8 entropy_calc_cap[0x1];
9326 u8 entropy_gre_calc_cap[0x1];
9327 u8 reserved_at_23[0x1b];
9328 u8 fcs_cap[0x1];
9329 u8 reserved_at_3f[0x1];
9330 u8 entropy_force[0x1];
9331 u8 entropy_calc[0x1];
9332 u8 entropy_gre_calc[0x1];
9333 u8 reserved_at_43[0x1b];
9334 u8 fcs_chk[0x1];
9335 u8 reserved_at_5f[0x1];
9336 };
9337
9338 struct mlx5_ifc_lane_2_module_mapping_bits {
9339 u8 reserved_at_0[0x6];
9340 u8 rx_lane[0x2];
9341 u8 reserved_at_8[0x6];
9342 u8 tx_lane[0x2];
9343 u8 reserved_at_10[0x8];
9344 u8 module[0x8];
9345 };
9346
9347 struct mlx5_ifc_bufferx_reg_bits {
9348 u8 reserved_at_0[0x6];
9349 u8 lossy[0x1];
9350 u8 epsb[0x1];
9351 u8 reserved_at_8[0xc];
9352 u8 size[0xc];
9353
9354 u8 xoff_threshold[0x10];
9355 u8 xon_threshold[0x10];
9356 };
9357
9358 struct mlx5_ifc_set_node_in_bits {
9359 u8 node_description[64][0x8];
9360 };
9361
9362 struct mlx5_ifc_register_power_settings_bits {
9363 u8 reserved_at_0[0x18];
9364 u8 power_settings_level[0x8];
9365
9366 u8 reserved_at_20[0x60];
9367 };
9368
9369 struct mlx5_ifc_register_host_endianness_bits {
9370 u8 he[0x1];
9371 u8 reserved_at_1[0x1f];
9372
9373 u8 reserved_at_20[0x60];
9374 };
9375
9376 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9377 u8 reserved_at_0[0x20];
9378
9379 u8 mkey[0x20];
9380
9381 u8 addressh_63_32[0x20];
9382
9383 u8 addressl_31_0[0x20];
9384 };
9385
9386 struct mlx5_ifc_ud_adrs_vector_bits {
9387 u8 dc_key[0x40];
9388
9389 u8 ext[0x1];
9390 u8 reserved_at_41[0x7];
9391 u8 destination_qp_dct[0x18];
9392
9393 u8 static_rate[0x4];
9394 u8 sl_eth_prio[0x4];
9395 u8 fl[0x1];
9396 u8 mlid[0x7];
9397 u8 rlid_udp_sport[0x10];
9398
9399 u8 reserved_at_80[0x20];
9400
9401 u8 rmac_47_16[0x20];
9402
9403 u8 rmac_15_0[0x10];
9404 u8 tclass[0x8];
9405 u8 hop_limit[0x8];
9406
9407 u8 reserved_at_e0[0x1];
9408 u8 grh[0x1];
9409 u8 reserved_at_e2[0x2];
9410 u8 src_addr_index[0x8];
9411 u8 flow_label[0x14];
9412
9413 u8 rgid_rip[16][0x8];
9414 };
9415
9416 struct mlx5_ifc_pages_req_event_bits {
9417 u8 reserved_at_0[0x10];
9418 u8 function_id[0x10];
9419
9420 u8 num_pages[0x20];
9421
9422 u8 reserved_at_40[0xa0];
9423 };
9424
9425 struct mlx5_ifc_eqe_bits {
9426 u8 reserved_at_0[0x8];
9427 u8 event_type[0x8];
9428 u8 reserved_at_10[0x8];
9429 u8 event_sub_type[0x8];
9430
9431 u8 reserved_at_20[0xe0];
9432
9433 union mlx5_ifc_event_auto_bits event_data;
9434
9435 u8 reserved_at_1e0[0x10];
9436 u8 signature[0x8];
9437 u8 reserved_at_1f8[0x7];
9438 u8 owner[0x1];
9439 };
9440
9441 enum {
9442 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9443 };
9444
9445 struct mlx5_ifc_cmd_queue_entry_bits {
9446 u8 type[0x8];
9447 u8 reserved_at_8[0x18];
9448
9449 u8 input_length[0x20];
9450
9451 u8 input_mailbox_pointer_63_32[0x20];
9452
9453 u8 input_mailbox_pointer_31_9[0x17];
9454 u8 reserved_at_77[0x9];
9455
9456 u8 command_input_inline_data[16][0x8];
9457
9458 u8 command_output_inline_data[16][0x8];
9459
9460 u8 output_mailbox_pointer_63_32[0x20];
9461
9462 u8 output_mailbox_pointer_31_9[0x17];
9463 u8 reserved_at_1b7[0x9];
9464
9465 u8 output_length[0x20];
9466
9467 u8 token[0x8];
9468 u8 signature[0x8];
9469 u8 reserved_at_1f0[0x8];
9470 u8 status[0x7];
9471 u8 ownership[0x1];
9472 };
9473
9474 struct mlx5_ifc_cmd_out_bits {
9475 u8 status[0x8];
9476 u8 reserved_at_8[0x18];
9477
9478 u8 syndrome[0x20];
9479
9480 u8 command_output[0x20];
9481 };
9482
9483 struct mlx5_ifc_cmd_in_bits {
9484 u8 opcode[0x10];
9485 u8 reserved_at_10[0x10];
9486
9487 u8 reserved_at_20[0x10];
9488 u8 op_mod[0x10];
9489
9490 u8 command[][0x20];
9491 };
9492
9493 struct mlx5_ifc_cmd_if_box_bits {
9494 u8 mailbox_data[512][0x8];
9495
9496 u8 reserved_at_1000[0x180];
9497
9498 u8 next_pointer_63_32[0x20];
9499
9500 u8 next_pointer_31_10[0x16];
9501 u8 reserved_at_11b6[0xa];
9502
9503 u8 block_number[0x20];
9504
9505 u8 reserved_at_11e0[0x8];
9506 u8 token[0x8];
9507 u8 ctrl_signature[0x8];
9508 u8 signature[0x8];
9509 };
9510
9511 struct mlx5_ifc_mtt_bits {
9512 u8 ptag_63_32[0x20];
9513
9514 u8 ptag_31_8[0x18];
9515 u8 reserved_at_38[0x6];
9516 u8 wr_en[0x1];
9517 u8 rd_en[0x1];
9518 };
9519
9520 struct mlx5_ifc_query_wol_rol_out_bits {
9521 u8 status[0x8];
9522 u8 reserved_at_8[0x18];
9523
9524 u8 syndrome[0x20];
9525
9526 u8 reserved_at_40[0x10];
9527 u8 rol_mode[0x8];
9528 u8 wol_mode[0x8];
9529
9530 u8 reserved_at_60[0x20];
9531 };
9532
9533 struct mlx5_ifc_query_wol_rol_in_bits {
9534 u8 opcode[0x10];
9535 u8 reserved_at_10[0x10];
9536
9537 u8 reserved_at_20[0x10];
9538 u8 op_mod[0x10];
9539
9540 u8 reserved_at_40[0x40];
9541 };
9542
9543 struct mlx5_ifc_set_wol_rol_out_bits {
9544 u8 status[0x8];
9545 u8 reserved_at_8[0x18];
9546
9547 u8 syndrome[0x20];
9548
9549 u8 reserved_at_40[0x40];
9550 };
9551
9552 struct mlx5_ifc_set_wol_rol_in_bits {
9553 u8 opcode[0x10];
9554 u8 reserved_at_10[0x10];
9555
9556 u8 reserved_at_20[0x10];
9557 u8 op_mod[0x10];
9558
9559 u8 rol_mode_valid[0x1];
9560 u8 wol_mode_valid[0x1];
9561 u8 reserved_at_42[0xe];
9562 u8 rol_mode[0x8];
9563 u8 wol_mode[0x8];
9564
9565 u8 reserved_at_60[0x20];
9566 };
9567
9568 enum {
9569 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9570 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9571 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9572 };
9573
9574 enum {
9575 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9576 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9577 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9578 };
9579
9580 enum {
9581 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9582 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9583 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9584 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9585 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9586 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9587 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9588 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9589 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9590 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9591 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9592 };
9593
9594 struct mlx5_ifc_initial_seg_bits {
9595 u8 fw_rev_minor[0x10];
9596 u8 fw_rev_major[0x10];
9597
9598 u8 cmd_interface_rev[0x10];
9599 u8 fw_rev_subminor[0x10];
9600
9601 u8 reserved_at_40[0x40];
9602
9603 u8 cmdq_phy_addr_63_32[0x20];
9604
9605 u8 cmdq_phy_addr_31_12[0x14];
9606 u8 reserved_at_b4[0x2];
9607 u8 nic_interface[0x2];
9608 u8 log_cmdq_size[0x4];
9609 u8 log_cmdq_stride[0x4];
9610
9611 u8 command_doorbell_vector[0x20];
9612
9613 u8 reserved_at_e0[0xf00];
9614
9615 u8 initializing[0x1];
9616 u8 reserved_at_fe1[0x4];
9617 u8 nic_interface_supported[0x3];
9618 u8 embedded_cpu[0x1];
9619 u8 reserved_at_fe9[0x17];
9620
9621 struct mlx5_ifc_health_buffer_bits health_buffer;
9622
9623 u8 no_dram_nic_offset[0x20];
9624
9625 u8 reserved_at_1220[0x6e40];
9626
9627 u8 reserved_at_8060[0x1f];
9628 u8 clear_int[0x1];
9629
9630 u8 health_syndrome[0x8];
9631 u8 health_counter[0x18];
9632
9633 u8 reserved_at_80a0[0x17fc0];
9634 };
9635
9636 struct mlx5_ifc_mtpps_reg_bits {
9637 u8 reserved_at_0[0xc];
9638 u8 cap_number_of_pps_pins[0x4];
9639 u8 reserved_at_10[0x4];
9640 u8 cap_max_num_of_pps_in_pins[0x4];
9641 u8 reserved_at_18[0x4];
9642 u8 cap_max_num_of_pps_out_pins[0x4];
9643
9644 u8 reserved_at_20[0x24];
9645 u8 cap_pin_3_mode[0x4];
9646 u8 reserved_at_48[0x4];
9647 u8 cap_pin_2_mode[0x4];
9648 u8 reserved_at_50[0x4];
9649 u8 cap_pin_1_mode[0x4];
9650 u8 reserved_at_58[0x4];
9651 u8 cap_pin_0_mode[0x4];
9652
9653 u8 reserved_at_60[0x4];
9654 u8 cap_pin_7_mode[0x4];
9655 u8 reserved_at_68[0x4];
9656 u8 cap_pin_6_mode[0x4];
9657 u8 reserved_at_70[0x4];
9658 u8 cap_pin_5_mode[0x4];
9659 u8 reserved_at_78[0x4];
9660 u8 cap_pin_4_mode[0x4];
9661
9662 u8 field_select[0x20];
9663 u8 reserved_at_a0[0x60];
9664
9665 u8 enable[0x1];
9666 u8 reserved_at_101[0xb];
9667 u8 pattern[0x4];
9668 u8 reserved_at_110[0x4];
9669 u8 pin_mode[0x4];
9670 u8 pin[0x8];
9671
9672 u8 reserved_at_120[0x20];
9673
9674 u8 time_stamp[0x40];
9675
9676 u8 out_pulse_duration[0x10];
9677 u8 out_periodic_adjustment[0x10];
9678 u8 enhanced_out_periodic_adjustment[0x20];
9679
9680 u8 reserved_at_1c0[0x20];
9681 };
9682
9683 struct mlx5_ifc_mtppse_reg_bits {
9684 u8 reserved_at_0[0x18];
9685 u8 pin[0x8];
9686 u8 event_arm[0x1];
9687 u8 reserved_at_21[0x1b];
9688 u8 event_generation_mode[0x4];
9689 u8 reserved_at_40[0x40];
9690 };
9691
9692 struct mlx5_ifc_mcqs_reg_bits {
9693 u8 last_index_flag[0x1];
9694 u8 reserved_at_1[0x7];
9695 u8 fw_device[0x8];
9696 u8 component_index[0x10];
9697
9698 u8 reserved_at_20[0x10];
9699 u8 identifier[0x10];
9700
9701 u8 reserved_at_40[0x17];
9702 u8 component_status[0x5];
9703 u8 component_update_state[0x4];
9704
9705 u8 last_update_state_changer_type[0x4];
9706 u8 last_update_state_changer_host_id[0x4];
9707 u8 reserved_at_68[0x18];
9708 };
9709
9710 struct mlx5_ifc_mcqi_cap_bits {
9711 u8 supported_info_bitmask[0x20];
9712
9713 u8 component_size[0x20];
9714
9715 u8 max_component_size[0x20];
9716
9717 u8 log_mcda_word_size[0x4];
9718 u8 reserved_at_64[0xc];
9719 u8 mcda_max_write_size[0x10];
9720
9721 u8 rd_en[0x1];
9722 u8 reserved_at_81[0x1];
9723 u8 match_chip_id[0x1];
9724 u8 match_psid[0x1];
9725 u8 check_user_timestamp[0x1];
9726 u8 match_base_guid_mac[0x1];
9727 u8 reserved_at_86[0x1a];
9728 };
9729
9730 struct mlx5_ifc_mcqi_version_bits {
9731 u8 reserved_at_0[0x2];
9732 u8 build_time_valid[0x1];
9733 u8 user_defined_time_valid[0x1];
9734 u8 reserved_at_4[0x14];
9735 u8 version_string_length[0x8];
9736
9737 u8 version[0x20];
9738
9739 u8 build_time[0x40];
9740
9741 u8 user_defined_time[0x40];
9742
9743 u8 build_tool_version[0x20];
9744
9745 u8 reserved_at_e0[0x20];
9746
9747 u8 version_string[92][0x8];
9748 };
9749
9750 struct mlx5_ifc_mcqi_activation_method_bits {
9751 u8 pending_server_ac_power_cycle[0x1];
9752 u8 pending_server_dc_power_cycle[0x1];
9753 u8 pending_server_reboot[0x1];
9754 u8 pending_fw_reset[0x1];
9755 u8 auto_activate[0x1];
9756 u8 all_hosts_sync[0x1];
9757 u8 device_hw_reset[0x1];
9758 u8 reserved_at_7[0x19];
9759 };
9760
9761 union mlx5_ifc_mcqi_reg_data_bits {
9762 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9763 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9764 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9765 };
9766
9767 struct mlx5_ifc_mcqi_reg_bits {
9768 u8 read_pending_component[0x1];
9769 u8 reserved_at_1[0xf];
9770 u8 component_index[0x10];
9771
9772 u8 reserved_at_20[0x20];
9773
9774 u8 reserved_at_40[0x1b];
9775 u8 info_type[0x5];
9776
9777 u8 info_size[0x20];
9778
9779 u8 offset[0x20];
9780
9781 u8 reserved_at_a0[0x10];
9782 u8 data_size[0x10];
9783
9784 union mlx5_ifc_mcqi_reg_data_bits data[];
9785 };
9786
9787 struct mlx5_ifc_mcc_reg_bits {
9788 u8 reserved_at_0[0x4];
9789 u8 time_elapsed_since_last_cmd[0xc];
9790 u8 reserved_at_10[0x8];
9791 u8 instruction[0x8];
9792
9793 u8 reserved_at_20[0x10];
9794 u8 component_index[0x10];
9795
9796 u8 reserved_at_40[0x8];
9797 u8 update_handle[0x18];
9798
9799 u8 handle_owner_type[0x4];
9800 u8 handle_owner_host_id[0x4];
9801 u8 reserved_at_68[0x1];
9802 u8 control_progress[0x7];
9803 u8 error_code[0x8];
9804 u8 reserved_at_78[0x4];
9805 u8 control_state[0x4];
9806
9807 u8 component_size[0x20];
9808
9809 u8 reserved_at_a0[0x60];
9810 };
9811
9812 struct mlx5_ifc_mcda_reg_bits {
9813 u8 reserved_at_0[0x8];
9814 u8 update_handle[0x18];
9815
9816 u8 offset[0x20];
9817
9818 u8 reserved_at_40[0x10];
9819 u8 size[0x10];
9820
9821 u8 reserved_at_60[0x20];
9822
9823 u8 data[][0x20];
9824 };
9825
9826 enum {
9827 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9828 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9829 };
9830
9831 enum {
9832 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9833 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9834 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9835 };
9836
9837 struct mlx5_ifc_mfrl_reg_bits {
9838 u8 reserved_at_0[0x20];
9839
9840 u8 reserved_at_20[0x2];
9841 u8 pci_sync_for_fw_update_start[0x1];
9842 u8 pci_sync_for_fw_update_resp[0x2];
9843 u8 rst_type_sel[0x3];
9844 u8 reserved_at_28[0x8];
9845 u8 reset_type[0x8];
9846 u8 reset_level[0x8];
9847 };
9848
9849 struct mlx5_ifc_mirc_reg_bits {
9850 u8 reserved_at_0[0x18];
9851 u8 status_code[0x8];
9852
9853 u8 reserved_at_20[0x20];
9854 };
9855
9856 union mlx5_ifc_ports_control_registers_document_bits {
9857 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9858 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9859 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9860 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9861 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9862 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9863 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9864 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9865 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9866 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9867 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9868 struct mlx5_ifc_paos_reg_bits paos_reg;
9869 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9870 struct mlx5_ifc_peir_reg_bits peir_reg;
9871 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9872 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9873 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9874 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9875 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9876 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9877 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9878 struct mlx5_ifc_plib_reg_bits plib_reg;
9879 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9880 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9881 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9882 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9883 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9884 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9885 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9886 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9887 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9888 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9889 struct mlx5_ifc_mpein_reg_bits mpein_reg;
9890 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9891 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9892 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9893 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9894 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9895 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9896 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9897 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9898 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9899 struct mlx5_ifc_pude_reg_bits pude_reg;
9900 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9901 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9902 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9903 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9904 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9905 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9906 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9907 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9908 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9909 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9910 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9911 struct mlx5_ifc_mirc_reg_bits mirc_reg;
9912 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
9913 u8 reserved_at_0[0x60e0];
9914 };
9915
9916 union mlx5_ifc_debug_enhancements_document_bits {
9917 struct mlx5_ifc_health_buffer_bits health_buffer;
9918 u8 reserved_at_0[0x200];
9919 };
9920
9921 union mlx5_ifc_uplink_pci_interface_document_bits {
9922 struct mlx5_ifc_initial_seg_bits initial_seg;
9923 u8 reserved_at_0[0x20060];
9924 };
9925
9926 struct mlx5_ifc_set_flow_table_root_out_bits {
9927 u8 status[0x8];
9928 u8 reserved_at_8[0x18];
9929
9930 u8 syndrome[0x20];
9931
9932 u8 reserved_at_40[0x40];
9933 };
9934
9935 struct mlx5_ifc_set_flow_table_root_in_bits {
9936 u8 opcode[0x10];
9937 u8 reserved_at_10[0x10];
9938
9939 u8 reserved_at_20[0x10];
9940 u8 op_mod[0x10];
9941
9942 u8 other_vport[0x1];
9943 u8 reserved_at_41[0xf];
9944 u8 vport_number[0x10];
9945
9946 u8 reserved_at_60[0x20];
9947
9948 u8 table_type[0x8];
9949 u8 reserved_at_88[0x18];
9950
9951 u8 reserved_at_a0[0x8];
9952 u8 table_id[0x18];
9953
9954 u8 reserved_at_c0[0x8];
9955 u8 underlay_qpn[0x18];
9956 u8 reserved_at_e0[0x120];
9957 };
9958
9959 enum {
9960 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9961 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9962 };
9963
9964 struct mlx5_ifc_modify_flow_table_out_bits {
9965 u8 status[0x8];
9966 u8 reserved_at_8[0x18];
9967
9968 u8 syndrome[0x20];
9969
9970 u8 reserved_at_40[0x40];
9971 };
9972
9973 struct mlx5_ifc_modify_flow_table_in_bits {
9974 u8 opcode[0x10];
9975 u8 reserved_at_10[0x10];
9976
9977 u8 reserved_at_20[0x10];
9978 u8 op_mod[0x10];
9979
9980 u8 other_vport[0x1];
9981 u8 reserved_at_41[0xf];
9982 u8 vport_number[0x10];
9983
9984 u8 reserved_at_60[0x10];
9985 u8 modify_field_select[0x10];
9986
9987 u8 table_type[0x8];
9988 u8 reserved_at_88[0x18];
9989
9990 u8 reserved_at_a0[0x8];
9991 u8 table_id[0x18];
9992
9993 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9994 };
9995
9996 struct mlx5_ifc_ets_tcn_config_reg_bits {
9997 u8 g[0x1];
9998 u8 b[0x1];
9999 u8 r[0x1];
10000 u8 reserved_at_3[0x9];
10001 u8 group[0x4];
10002 u8 reserved_at_10[0x9];
10003 u8 bw_allocation[0x7];
10004
10005 u8 reserved_at_20[0xc];
10006 u8 max_bw_units[0x4];
10007 u8 reserved_at_30[0x8];
10008 u8 max_bw_value[0x8];
10009 };
10010
10011 struct mlx5_ifc_ets_global_config_reg_bits {
10012 u8 reserved_at_0[0x2];
10013 u8 r[0x1];
10014 u8 reserved_at_3[0x1d];
10015
10016 u8 reserved_at_20[0xc];
10017 u8 max_bw_units[0x4];
10018 u8 reserved_at_30[0x8];
10019 u8 max_bw_value[0x8];
10020 };
10021
10022 struct mlx5_ifc_qetc_reg_bits {
10023 u8 reserved_at_0[0x8];
10024 u8 port_number[0x8];
10025 u8 reserved_at_10[0x30];
10026
10027 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10028 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10029 };
10030
10031 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10032 u8 e[0x1];
10033 u8 reserved_at_01[0x0b];
10034 u8 prio[0x04];
10035 };
10036
10037 struct mlx5_ifc_qpdpm_reg_bits {
10038 u8 reserved_at_0[0x8];
10039 u8 local_port[0x8];
10040 u8 reserved_at_10[0x10];
10041 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10042 };
10043
10044 struct mlx5_ifc_qpts_reg_bits {
10045 u8 reserved_at_0[0x8];
10046 u8 local_port[0x8];
10047 u8 reserved_at_10[0x2d];
10048 u8 trust_state[0x3];
10049 };
10050
10051 struct mlx5_ifc_pptb_reg_bits {
10052 u8 reserved_at_0[0x2];
10053 u8 mm[0x2];
10054 u8 reserved_at_4[0x4];
10055 u8 local_port[0x8];
10056 u8 reserved_at_10[0x6];
10057 u8 cm[0x1];
10058 u8 um[0x1];
10059 u8 pm[0x8];
10060
10061 u8 prio_x_buff[0x20];
10062
10063 u8 pm_msb[0x8];
10064 u8 reserved_at_48[0x10];
10065 u8 ctrl_buff[0x4];
10066 u8 untagged_buff[0x4];
10067 };
10068
10069 struct mlx5_ifc_sbcam_reg_bits {
10070 u8 reserved_at_0[0x8];
10071 u8 feature_group[0x8];
10072 u8 reserved_at_10[0x8];
10073 u8 access_reg_group[0x8];
10074
10075 u8 reserved_at_20[0x20];
10076
10077 u8 sb_access_reg_cap_mask[4][0x20];
10078
10079 u8 reserved_at_c0[0x80];
10080
10081 u8 sb_feature_cap_mask[4][0x20];
10082
10083 u8 reserved_at_1c0[0x40];
10084
10085 u8 cap_total_buffer_size[0x20];
10086
10087 u8 cap_cell_size[0x10];
10088 u8 cap_max_pg_buffers[0x8];
10089 u8 cap_num_pool_supported[0x8];
10090
10091 u8 reserved_at_240[0x8];
10092 u8 cap_sbsr_stat_size[0x8];
10093 u8 cap_max_tclass_data[0x8];
10094 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10095 };
10096
10097 struct mlx5_ifc_pbmc_reg_bits {
10098 u8 reserved_at_0[0x8];
10099 u8 local_port[0x8];
10100 u8 reserved_at_10[0x10];
10101
10102 u8 xoff_timer_value[0x10];
10103 u8 xoff_refresh[0x10];
10104
10105 u8 reserved_at_40[0x9];
10106 u8 fullness_threshold[0x7];
10107 u8 port_buffer_size[0x10];
10108
10109 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10110
10111 u8 reserved_at_2e0[0x80];
10112 };
10113
10114 struct mlx5_ifc_qtct_reg_bits {
10115 u8 reserved_at_0[0x8];
10116 u8 port_number[0x8];
10117 u8 reserved_at_10[0xd];
10118 u8 prio[0x3];
10119
10120 u8 reserved_at_20[0x1d];
10121 u8 tclass[0x3];
10122 };
10123
10124 struct mlx5_ifc_mcia_reg_bits {
10125 u8 l[0x1];
10126 u8 reserved_at_1[0x7];
10127 u8 module[0x8];
10128 u8 reserved_at_10[0x8];
10129 u8 status[0x8];
10130
10131 u8 i2c_device_address[0x8];
10132 u8 page_number[0x8];
10133 u8 device_address[0x10];
10134
10135 u8 reserved_at_40[0x10];
10136 u8 size[0x10];
10137
10138 u8 reserved_at_60[0x20];
10139
10140 u8 dword_0[0x20];
10141 u8 dword_1[0x20];
10142 u8 dword_2[0x20];
10143 u8 dword_3[0x20];
10144 u8 dword_4[0x20];
10145 u8 dword_5[0x20];
10146 u8 dword_6[0x20];
10147 u8 dword_7[0x20];
10148 u8 dword_8[0x20];
10149 u8 dword_9[0x20];
10150 u8 dword_10[0x20];
10151 u8 dword_11[0x20];
10152 };
10153
10154 struct mlx5_ifc_dcbx_param_bits {
10155 u8 dcbx_cee_cap[0x1];
10156 u8 dcbx_ieee_cap[0x1];
10157 u8 dcbx_standby_cap[0x1];
10158 u8 reserved_at_3[0x5];
10159 u8 port_number[0x8];
10160 u8 reserved_at_10[0xa];
10161 u8 max_application_table_size[6];
10162 u8 reserved_at_20[0x15];
10163 u8 version_oper[0x3];
10164 u8 reserved_at_38[5];
10165 u8 version_admin[0x3];
10166 u8 willing_admin[0x1];
10167 u8 reserved_at_41[0x3];
10168 u8 pfc_cap_oper[0x4];
10169 u8 reserved_at_48[0x4];
10170 u8 pfc_cap_admin[0x4];
10171 u8 reserved_at_50[0x4];
10172 u8 num_of_tc_oper[0x4];
10173 u8 reserved_at_58[0x4];
10174 u8 num_of_tc_admin[0x4];
10175 u8 remote_willing[0x1];
10176 u8 reserved_at_61[3];
10177 u8 remote_pfc_cap[4];
10178 u8 reserved_at_68[0x14];
10179 u8 remote_num_of_tc[0x4];
10180 u8 reserved_at_80[0x18];
10181 u8 error[0x8];
10182 u8 reserved_at_a0[0x160];
10183 };
10184
10185 struct mlx5_ifc_lagc_bits {
10186 u8 reserved_at_0[0x1d];
10187 u8 lag_state[0x3];
10188
10189 u8 reserved_at_20[0x14];
10190 u8 tx_remap_affinity_2[0x4];
10191 u8 reserved_at_38[0x4];
10192 u8 tx_remap_affinity_1[0x4];
10193 };
10194
10195 struct mlx5_ifc_create_lag_out_bits {
10196 u8 status[0x8];
10197 u8 reserved_at_8[0x18];
10198
10199 u8 syndrome[0x20];
10200
10201 u8 reserved_at_40[0x40];
10202 };
10203
10204 struct mlx5_ifc_create_lag_in_bits {
10205 u8 opcode[0x10];
10206 u8 reserved_at_10[0x10];
10207
10208 u8 reserved_at_20[0x10];
10209 u8 op_mod[0x10];
10210
10211 struct mlx5_ifc_lagc_bits ctx;
10212 };
10213
10214 struct mlx5_ifc_modify_lag_out_bits {
10215 u8 status[0x8];
10216 u8 reserved_at_8[0x18];
10217
10218 u8 syndrome[0x20];
10219
10220 u8 reserved_at_40[0x40];
10221 };
10222
10223 struct mlx5_ifc_modify_lag_in_bits {
10224 u8 opcode[0x10];
10225 u8 reserved_at_10[0x10];
10226
10227 u8 reserved_at_20[0x10];
10228 u8 op_mod[0x10];
10229
10230 u8 reserved_at_40[0x20];
10231 u8 field_select[0x20];
10232
10233 struct mlx5_ifc_lagc_bits ctx;
10234 };
10235
10236 struct mlx5_ifc_query_lag_out_bits {
10237 u8 status[0x8];
10238 u8 reserved_at_8[0x18];
10239
10240 u8 syndrome[0x20];
10241
10242 struct mlx5_ifc_lagc_bits ctx;
10243 };
10244
10245 struct mlx5_ifc_query_lag_in_bits {
10246 u8 opcode[0x10];
10247 u8 reserved_at_10[0x10];
10248
10249 u8 reserved_at_20[0x10];
10250 u8 op_mod[0x10];
10251
10252 u8 reserved_at_40[0x40];
10253 };
10254
10255 struct mlx5_ifc_destroy_lag_out_bits {
10256 u8 status[0x8];
10257 u8 reserved_at_8[0x18];
10258
10259 u8 syndrome[0x20];
10260
10261 u8 reserved_at_40[0x40];
10262 };
10263
10264 struct mlx5_ifc_destroy_lag_in_bits {
10265 u8 opcode[0x10];
10266 u8 reserved_at_10[0x10];
10267
10268 u8 reserved_at_20[0x10];
10269 u8 op_mod[0x10];
10270
10271 u8 reserved_at_40[0x40];
10272 };
10273
10274 struct mlx5_ifc_create_vport_lag_out_bits {
10275 u8 status[0x8];
10276 u8 reserved_at_8[0x18];
10277
10278 u8 syndrome[0x20];
10279
10280 u8 reserved_at_40[0x40];
10281 };
10282
10283 struct mlx5_ifc_create_vport_lag_in_bits {
10284 u8 opcode[0x10];
10285 u8 reserved_at_10[0x10];
10286
10287 u8 reserved_at_20[0x10];
10288 u8 op_mod[0x10];
10289
10290 u8 reserved_at_40[0x40];
10291 };
10292
10293 struct mlx5_ifc_destroy_vport_lag_out_bits {
10294 u8 status[0x8];
10295 u8 reserved_at_8[0x18];
10296
10297 u8 syndrome[0x20];
10298
10299 u8 reserved_at_40[0x40];
10300 };
10301
10302 struct mlx5_ifc_destroy_vport_lag_in_bits {
10303 u8 opcode[0x10];
10304 u8 reserved_at_10[0x10];
10305
10306 u8 reserved_at_20[0x10];
10307 u8 op_mod[0x10];
10308
10309 u8 reserved_at_40[0x40];
10310 };
10311
10312 struct mlx5_ifc_alloc_memic_in_bits {
10313 u8 opcode[0x10];
10314 u8 reserved_at_10[0x10];
10315
10316 u8 reserved_at_20[0x10];
10317 u8 op_mod[0x10];
10318
10319 u8 reserved_at_30[0x20];
10320
10321 u8 reserved_at_40[0x18];
10322 u8 log_memic_addr_alignment[0x8];
10323
10324 u8 range_start_addr[0x40];
10325
10326 u8 range_size[0x20];
10327
10328 u8 memic_size[0x20];
10329 };
10330
10331 struct mlx5_ifc_alloc_memic_out_bits {
10332 u8 status[0x8];
10333 u8 reserved_at_8[0x18];
10334
10335 u8 syndrome[0x20];
10336
10337 u8 memic_start_addr[0x40];
10338 };
10339
10340 struct mlx5_ifc_dealloc_memic_in_bits {
10341 u8 opcode[0x10];
10342 u8 reserved_at_10[0x10];
10343
10344 u8 reserved_at_20[0x10];
10345 u8 op_mod[0x10];
10346
10347 u8 reserved_at_40[0x40];
10348
10349 u8 memic_start_addr[0x40];
10350
10351 u8 memic_size[0x20];
10352
10353 u8 reserved_at_e0[0x20];
10354 };
10355
10356 struct mlx5_ifc_dealloc_memic_out_bits {
10357 u8 status[0x8];
10358 u8 reserved_at_8[0x18];
10359
10360 u8 syndrome[0x20];
10361
10362 u8 reserved_at_40[0x40];
10363 };
10364
10365 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10366 u8 opcode[0x10];
10367 u8 uid[0x10];
10368
10369 u8 vhca_tunnel_id[0x10];
10370 u8 obj_type[0x10];
10371
10372 u8 obj_id[0x20];
10373
10374 u8 reserved_at_60[0x20];
10375 };
10376
10377 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10378 u8 status[0x8];
10379 u8 reserved_at_8[0x18];
10380
10381 u8 syndrome[0x20];
10382
10383 u8 obj_id[0x20];
10384
10385 u8 reserved_at_60[0x20];
10386 };
10387
10388 struct mlx5_ifc_umem_bits {
10389 u8 reserved_at_0[0x80];
10390
10391 u8 reserved_at_80[0x1b];
10392 u8 log_page_size[0x5];
10393
10394 u8 page_offset[0x20];
10395
10396 u8 num_of_mtt[0x40];
10397
10398 struct mlx5_ifc_mtt_bits mtt[];
10399 };
10400
10401 struct mlx5_ifc_uctx_bits {
10402 u8 cap[0x20];
10403
10404 u8 reserved_at_20[0x160];
10405 };
10406
10407 struct mlx5_ifc_sw_icm_bits {
10408 u8 modify_field_select[0x40];
10409
10410 u8 reserved_at_40[0x18];
10411 u8 log_sw_icm_size[0x8];
10412
10413 u8 reserved_at_60[0x20];
10414
10415 u8 sw_icm_start_addr[0x40];
10416
10417 u8 reserved_at_c0[0x140];
10418 };
10419
10420 struct mlx5_ifc_geneve_tlv_option_bits {
10421 u8 modify_field_select[0x40];
10422
10423 u8 reserved_at_40[0x18];
10424 u8 geneve_option_fte_index[0x8];
10425
10426 u8 option_class[0x10];
10427 u8 option_type[0x8];
10428 u8 reserved_at_78[0x3];
10429 u8 option_data_length[0x5];
10430
10431 u8 reserved_at_80[0x180];
10432 };
10433
10434 struct mlx5_ifc_create_umem_in_bits {
10435 u8 opcode[0x10];
10436 u8 uid[0x10];
10437
10438 u8 reserved_at_20[0x10];
10439 u8 op_mod[0x10];
10440
10441 u8 reserved_at_40[0x40];
10442
10443 struct mlx5_ifc_umem_bits umem;
10444 };
10445
10446 struct mlx5_ifc_create_umem_out_bits {
10447 u8 status[0x8];
10448 u8 reserved_at_8[0x18];
10449
10450 u8 syndrome[0x20];
10451
10452 u8 reserved_at_40[0x8];
10453 u8 umem_id[0x18];
10454
10455 u8 reserved_at_60[0x20];
10456 };
10457
10458 struct mlx5_ifc_destroy_umem_in_bits {
10459 u8 opcode[0x10];
10460 u8 uid[0x10];
10461
10462 u8 reserved_at_20[0x10];
10463 u8 op_mod[0x10];
10464
10465 u8 reserved_at_40[0x8];
10466 u8 umem_id[0x18];
10467
10468 u8 reserved_at_60[0x20];
10469 };
10470
10471 struct mlx5_ifc_destroy_umem_out_bits {
10472 u8 status[0x8];
10473 u8 reserved_at_8[0x18];
10474
10475 u8 syndrome[0x20];
10476
10477 u8 reserved_at_40[0x40];
10478 };
10479
10480 struct mlx5_ifc_create_uctx_in_bits {
10481 u8 opcode[0x10];
10482 u8 reserved_at_10[0x10];
10483
10484 u8 reserved_at_20[0x10];
10485 u8 op_mod[0x10];
10486
10487 u8 reserved_at_40[0x40];
10488
10489 struct mlx5_ifc_uctx_bits uctx;
10490 };
10491
10492 struct mlx5_ifc_create_uctx_out_bits {
10493 u8 status[0x8];
10494 u8 reserved_at_8[0x18];
10495
10496 u8 syndrome[0x20];
10497
10498 u8 reserved_at_40[0x10];
10499 u8 uid[0x10];
10500
10501 u8 reserved_at_60[0x20];
10502 };
10503
10504 struct mlx5_ifc_destroy_uctx_in_bits {
10505 u8 opcode[0x10];
10506 u8 reserved_at_10[0x10];
10507
10508 u8 reserved_at_20[0x10];
10509 u8 op_mod[0x10];
10510
10511 u8 reserved_at_40[0x10];
10512 u8 uid[0x10];
10513
10514 u8 reserved_at_60[0x20];
10515 };
10516
10517 struct mlx5_ifc_destroy_uctx_out_bits {
10518 u8 status[0x8];
10519 u8 reserved_at_8[0x18];
10520
10521 u8 syndrome[0x20];
10522
10523 u8 reserved_at_40[0x40];
10524 };
10525
10526 struct mlx5_ifc_create_sw_icm_in_bits {
10527 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10528 struct mlx5_ifc_sw_icm_bits sw_icm;
10529 };
10530
10531 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10532 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10533 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
10534 };
10535
10536 struct mlx5_ifc_mtrc_string_db_param_bits {
10537 u8 string_db_base_address[0x20];
10538
10539 u8 reserved_at_20[0x8];
10540 u8 string_db_size[0x18];
10541 };
10542
10543 struct mlx5_ifc_mtrc_cap_bits {
10544 u8 trace_owner[0x1];
10545 u8 trace_to_memory[0x1];
10546 u8 reserved_at_2[0x4];
10547 u8 trc_ver[0x2];
10548 u8 reserved_at_8[0x14];
10549 u8 num_string_db[0x4];
10550
10551 u8 first_string_trace[0x8];
10552 u8 num_string_trace[0x8];
10553 u8 reserved_at_30[0x28];
10554
10555 u8 log_max_trace_buffer_size[0x8];
10556
10557 u8 reserved_at_60[0x20];
10558
10559 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10560
10561 u8 reserved_at_280[0x180];
10562 };
10563
10564 struct mlx5_ifc_mtrc_conf_bits {
10565 u8 reserved_at_0[0x1c];
10566 u8 trace_mode[0x4];
10567 u8 reserved_at_20[0x18];
10568 u8 log_trace_buffer_size[0x8];
10569 u8 trace_mkey[0x20];
10570 u8 reserved_at_60[0x3a0];
10571 };
10572
10573 struct mlx5_ifc_mtrc_stdb_bits {
10574 u8 string_db_index[0x4];
10575 u8 reserved_at_4[0x4];
10576 u8 read_size[0x18];
10577 u8 start_offset[0x20];
10578 u8 string_db_data[];
10579 };
10580
10581 struct mlx5_ifc_mtrc_ctrl_bits {
10582 u8 trace_status[0x2];
10583 u8 reserved_at_2[0x2];
10584 u8 arm_event[0x1];
10585 u8 reserved_at_5[0xb];
10586 u8 modify_field_select[0x10];
10587 u8 reserved_at_20[0x2b];
10588 u8 current_timestamp52_32[0x15];
10589 u8 current_timestamp31_0[0x20];
10590 u8 reserved_at_80[0x180];
10591 };
10592
10593 struct mlx5_ifc_host_params_context_bits {
10594 u8 host_number[0x8];
10595 u8 reserved_at_8[0x7];
10596 u8 host_pf_disabled[0x1];
10597 u8 host_num_of_vfs[0x10];
10598
10599 u8 host_total_vfs[0x10];
10600 u8 host_pci_bus[0x10];
10601
10602 u8 reserved_at_40[0x10];
10603 u8 host_pci_device[0x10];
10604
10605 u8 reserved_at_60[0x10];
10606 u8 host_pci_function[0x10];
10607
10608 u8 reserved_at_80[0x180];
10609 };
10610
10611 struct mlx5_ifc_query_esw_functions_in_bits {
10612 u8 opcode[0x10];
10613 u8 reserved_at_10[0x10];
10614
10615 u8 reserved_at_20[0x10];
10616 u8 op_mod[0x10];
10617
10618 u8 reserved_at_40[0x40];
10619 };
10620
10621 struct mlx5_ifc_query_esw_functions_out_bits {
10622 u8 status[0x8];
10623 u8 reserved_at_8[0x18];
10624
10625 u8 syndrome[0x20];
10626
10627 u8 reserved_at_40[0x40];
10628
10629 struct mlx5_ifc_host_params_context_bits host_params_context;
10630
10631 u8 reserved_at_280[0x180];
10632 u8 host_sf_enable[][0x40];
10633 };
10634
10635 struct mlx5_ifc_sf_partition_bits {
10636 u8 reserved_at_0[0x10];
10637 u8 log_num_sf[0x8];
10638 u8 log_sf_bar_size[0x8];
10639 };
10640
10641 struct mlx5_ifc_query_sf_partitions_out_bits {
10642 u8 status[0x8];
10643 u8 reserved_at_8[0x18];
10644
10645 u8 syndrome[0x20];
10646
10647 u8 reserved_at_40[0x18];
10648 u8 num_sf_partitions[0x8];
10649
10650 u8 reserved_at_60[0x20];
10651
10652 struct mlx5_ifc_sf_partition_bits sf_partition[];
10653 };
10654
10655 struct mlx5_ifc_query_sf_partitions_in_bits {
10656 u8 opcode[0x10];
10657 u8 reserved_at_10[0x10];
10658
10659 u8 reserved_at_20[0x10];
10660 u8 op_mod[0x10];
10661
10662 u8 reserved_at_40[0x40];
10663 };
10664
10665 struct mlx5_ifc_dealloc_sf_out_bits {
10666 u8 status[0x8];
10667 u8 reserved_at_8[0x18];
10668
10669 u8 syndrome[0x20];
10670
10671 u8 reserved_at_40[0x40];
10672 };
10673
10674 struct mlx5_ifc_dealloc_sf_in_bits {
10675 u8 opcode[0x10];
10676 u8 reserved_at_10[0x10];
10677
10678 u8 reserved_at_20[0x10];
10679 u8 op_mod[0x10];
10680
10681 u8 reserved_at_40[0x10];
10682 u8 function_id[0x10];
10683
10684 u8 reserved_at_60[0x20];
10685 };
10686
10687 struct mlx5_ifc_alloc_sf_out_bits {
10688 u8 status[0x8];
10689 u8 reserved_at_8[0x18];
10690
10691 u8 syndrome[0x20];
10692
10693 u8 reserved_at_40[0x40];
10694 };
10695
10696 struct mlx5_ifc_alloc_sf_in_bits {
10697 u8 opcode[0x10];
10698 u8 reserved_at_10[0x10];
10699
10700 u8 reserved_at_20[0x10];
10701 u8 op_mod[0x10];
10702
10703 u8 reserved_at_40[0x10];
10704 u8 function_id[0x10];
10705
10706 u8 reserved_at_60[0x20];
10707 };
10708
10709 struct mlx5_ifc_affiliated_event_header_bits {
10710 u8 reserved_at_0[0x10];
10711 u8 obj_type[0x10];
10712
10713 u8 obj_id[0x20];
10714 };
10715
10716 enum {
10717 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
10718 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
10719 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
10720 };
10721
10722 enum {
10723 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10724 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10725 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
10726 };
10727
10728 enum {
10729 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10730 MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10731 MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10732 };
10733
10734 struct mlx5_ifc_ipsec_obj_bits {
10735 u8 modify_field_select[0x40];
10736 u8 full_offload[0x1];
10737 u8 reserved_at_41[0x1];
10738 u8 esn_en[0x1];
10739 u8 esn_overlap[0x1];
10740 u8 reserved_at_44[0x2];
10741 u8 icv_length[0x2];
10742 u8 reserved_at_48[0x4];
10743 u8 aso_return_reg[0x4];
10744 u8 reserved_at_50[0x10];
10745
10746 u8 esn_msb[0x20];
10747
10748 u8 reserved_at_80[0x8];
10749 u8 dekn[0x18];
10750
10751 u8 salt[0x20];
10752
10753 u8 implicit_iv[0x40];
10754
10755 u8 reserved_at_100[0x700];
10756 };
10757
10758 struct mlx5_ifc_create_ipsec_obj_in_bits {
10759 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10760 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10761 };
10762
10763 enum {
10764 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10765 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
10766 };
10767
10768 struct mlx5_ifc_query_ipsec_obj_out_bits {
10769 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
10770 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10771 };
10772
10773 struct mlx5_ifc_modify_ipsec_obj_in_bits {
10774 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10775 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10776 };
10777
10778 struct mlx5_ifc_encryption_key_obj_bits {
10779 u8 modify_field_select[0x40];
10780
10781 u8 reserved_at_40[0x14];
10782 u8 key_size[0x4];
10783 u8 reserved_at_58[0x4];
10784 u8 key_type[0x4];
10785
10786 u8 reserved_at_60[0x8];
10787 u8 pd[0x18];
10788
10789 u8 reserved_at_80[0x180];
10790 u8 key[8][0x20];
10791
10792 u8 reserved_at_300[0x500];
10793 };
10794
10795 struct mlx5_ifc_create_encryption_key_in_bits {
10796 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10797 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10798 };
10799
10800 struct mlx5_ifc_sampler_obj_bits {
10801 u8 modify_field_select[0x40];
10802
10803 u8 table_type[0x8];
10804 u8 level[0x8];
10805 u8 reserved_at_50[0xf];
10806 u8 ignore_flow_level[0x1];
10807
10808 u8 sample_ratio[0x20];
10809
10810 u8 reserved_at_80[0x8];
10811 u8 sample_table_id[0x18];
10812
10813 u8 reserved_at_a0[0x8];
10814 u8 default_table_id[0x18];
10815
10816 u8 sw_steering_icm_address_rx[0x40];
10817 u8 sw_steering_icm_address_tx[0x40];
10818
10819 u8 reserved_at_140[0xa0];
10820 };
10821
10822 struct mlx5_ifc_create_sampler_obj_in_bits {
10823 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10824 struct mlx5_ifc_sampler_obj_bits sampler_object;
10825 };
10826
10827 enum {
10828 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10829 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10830 };
10831
10832 enum {
10833 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10834 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
10835 };
10836
10837 struct mlx5_ifc_tls_static_params_bits {
10838 u8 const_2[0x2];
10839 u8 tls_version[0x4];
10840 u8 const_1[0x2];
10841 u8 reserved_at_8[0x14];
10842 u8 encryption_standard[0x4];
10843
10844 u8 reserved_at_20[0x20];
10845
10846 u8 initial_record_number[0x40];
10847
10848 u8 resync_tcp_sn[0x20];
10849
10850 u8 gcm_iv[0x20];
10851
10852 u8 implicit_iv[0x40];
10853
10854 u8 reserved_at_100[0x8];
10855 u8 dek_index[0x18];
10856
10857 u8 reserved_at_120[0xe0];
10858 };
10859
10860 struct mlx5_ifc_tls_progress_params_bits {
10861 u8 next_record_tcp_sn[0x20];
10862
10863 u8 hw_resync_tcp_sn[0x20];
10864
10865 u8 record_tracker_state[0x2];
10866 u8 auth_state[0x2];
10867 u8 reserved_at_44[0x4];
10868 u8 hw_offset_record_number[0x18];
10869 };
10870
10871 enum {
10872 MLX5_MTT_PERM_READ = 1 << 0,
10873 MLX5_MTT_PERM_WRITE = 1 << 1,
10874 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
10875 };
10876
10877 #endif /* MLX5_IFC_H */
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