2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS
= 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED
= 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED
= 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED
= 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED
= 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT
= 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED
= 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION
= 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR
= 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR
= 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED
= 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT
= 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR
= 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR
= 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR
= 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR
= 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE
= 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT
= 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT
= 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT
= 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT
= 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT
= 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION
= 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST
= 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR
= 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR
= 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO
= 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE
= 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH
= 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN
= 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
= 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP
= 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
= 0x3,
80 MLX5_SHARED_RESOURCE_UID
= 0xffff,
84 MLX5_OBJ_TYPE_SW_ICM
= 0x0008,
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM
= (1ULL << MLX5_OBJ_TYPE_SW_ICM
),
89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT
= (1ULL << 11),
93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT
= 0x000b,
94 MLX5_OBJ_TYPE_MKEY
= 0xff01,
95 MLX5_OBJ_TYPE_QP
= 0xff02,
96 MLX5_OBJ_TYPE_PSV
= 0xff03,
97 MLX5_OBJ_TYPE_RMP
= 0xff04,
98 MLX5_OBJ_TYPE_XRC_SRQ
= 0xff05,
99 MLX5_OBJ_TYPE_RQ
= 0xff06,
100 MLX5_OBJ_TYPE_SQ
= 0xff07,
101 MLX5_OBJ_TYPE_TIR
= 0xff08,
102 MLX5_OBJ_TYPE_TIS
= 0xff09,
103 MLX5_OBJ_TYPE_DCT
= 0xff0a,
104 MLX5_OBJ_TYPE_XRQ
= 0xff0b,
105 MLX5_OBJ_TYPE_RQT
= 0xff0e,
106 MLX5_OBJ_TYPE_FLOW_COUNTER
= 0xff0f,
107 MLX5_OBJ_TYPE_CQ
= 0xff10,
111 MLX5_CMD_OP_QUERY_HCA_CAP
= 0x100,
112 MLX5_CMD_OP_QUERY_ADAPTER
= 0x101,
113 MLX5_CMD_OP_INIT_HCA
= 0x102,
114 MLX5_CMD_OP_TEARDOWN_HCA
= 0x103,
115 MLX5_CMD_OP_ENABLE_HCA
= 0x104,
116 MLX5_CMD_OP_DISABLE_HCA
= 0x105,
117 MLX5_CMD_OP_QUERY_PAGES
= 0x107,
118 MLX5_CMD_OP_MANAGE_PAGES
= 0x108,
119 MLX5_CMD_OP_SET_HCA_CAP
= 0x109,
120 MLX5_CMD_OP_QUERY_ISSI
= 0x10a,
121 MLX5_CMD_OP_SET_ISSI
= 0x10b,
122 MLX5_CMD_OP_SET_DRIVER_VERSION
= 0x10d,
123 MLX5_CMD_OP_QUERY_SF_PARTITION
= 0x111,
124 MLX5_CMD_OP_ALLOC_SF
= 0x113,
125 MLX5_CMD_OP_DEALLOC_SF
= 0x114,
126 MLX5_CMD_OP_CREATE_MKEY
= 0x200,
127 MLX5_CMD_OP_QUERY_MKEY
= 0x201,
128 MLX5_CMD_OP_DESTROY_MKEY
= 0x202,
129 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS
= 0x203,
130 MLX5_CMD_OP_PAGE_FAULT_RESUME
= 0x204,
131 MLX5_CMD_OP_ALLOC_MEMIC
= 0x205,
132 MLX5_CMD_OP_DEALLOC_MEMIC
= 0x206,
133 MLX5_CMD_OP_CREATE_EQ
= 0x301,
134 MLX5_CMD_OP_DESTROY_EQ
= 0x302,
135 MLX5_CMD_OP_QUERY_EQ
= 0x303,
136 MLX5_CMD_OP_GEN_EQE
= 0x304,
137 MLX5_CMD_OP_CREATE_CQ
= 0x400,
138 MLX5_CMD_OP_DESTROY_CQ
= 0x401,
139 MLX5_CMD_OP_QUERY_CQ
= 0x402,
140 MLX5_CMD_OP_MODIFY_CQ
= 0x403,
141 MLX5_CMD_OP_CREATE_QP
= 0x500,
142 MLX5_CMD_OP_DESTROY_QP
= 0x501,
143 MLX5_CMD_OP_RST2INIT_QP
= 0x502,
144 MLX5_CMD_OP_INIT2RTR_QP
= 0x503,
145 MLX5_CMD_OP_RTR2RTS_QP
= 0x504,
146 MLX5_CMD_OP_RTS2RTS_QP
= 0x505,
147 MLX5_CMD_OP_SQERR2RTS_QP
= 0x506,
148 MLX5_CMD_OP_2ERR_QP
= 0x507,
149 MLX5_CMD_OP_2RST_QP
= 0x50a,
150 MLX5_CMD_OP_QUERY_QP
= 0x50b,
151 MLX5_CMD_OP_SQD_RTS_QP
= 0x50c,
152 MLX5_CMD_OP_INIT2INIT_QP
= 0x50e,
153 MLX5_CMD_OP_CREATE_PSV
= 0x600,
154 MLX5_CMD_OP_DESTROY_PSV
= 0x601,
155 MLX5_CMD_OP_CREATE_SRQ
= 0x700,
156 MLX5_CMD_OP_DESTROY_SRQ
= 0x701,
157 MLX5_CMD_OP_QUERY_SRQ
= 0x702,
158 MLX5_CMD_OP_ARM_RQ
= 0x703,
159 MLX5_CMD_OP_CREATE_XRC_SRQ
= 0x705,
160 MLX5_CMD_OP_DESTROY_XRC_SRQ
= 0x706,
161 MLX5_CMD_OP_QUERY_XRC_SRQ
= 0x707,
162 MLX5_CMD_OP_ARM_XRC_SRQ
= 0x708,
163 MLX5_CMD_OP_CREATE_DCT
= 0x710,
164 MLX5_CMD_OP_DESTROY_DCT
= 0x711,
165 MLX5_CMD_OP_DRAIN_DCT
= 0x712,
166 MLX5_CMD_OP_QUERY_DCT
= 0x713,
167 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION
= 0x714,
168 MLX5_CMD_OP_CREATE_XRQ
= 0x717,
169 MLX5_CMD_OP_DESTROY_XRQ
= 0x718,
170 MLX5_CMD_OP_QUERY_XRQ
= 0x719,
171 MLX5_CMD_OP_ARM_XRQ
= 0x71a,
172 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY
= 0x725,
173 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY
= 0x726,
174 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS
= 0x727,
175 MLX5_CMD_OP_RELEASE_XRQ_ERROR
= 0x729,
176 MLX5_CMD_OP_MODIFY_XRQ
= 0x72a,
177 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS
= 0x740,
178 MLX5_CMD_OP_QUERY_VPORT_STATE
= 0x750,
179 MLX5_CMD_OP_MODIFY_VPORT_STATE
= 0x751,
180 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT
= 0x752,
181 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT
= 0x753,
182 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT
= 0x754,
183 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT
= 0x755,
184 MLX5_CMD_OP_QUERY_ROCE_ADDRESS
= 0x760,
185 MLX5_CMD_OP_SET_ROCE_ADDRESS
= 0x761,
186 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT
= 0x762,
187 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT
= 0x763,
188 MLX5_CMD_OP_QUERY_HCA_VPORT_GID
= 0x764,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY
= 0x765,
190 MLX5_CMD_OP_QUERY_VNIC_ENV
= 0x76f,
191 MLX5_CMD_OP_QUERY_VPORT_COUNTER
= 0x770,
192 MLX5_CMD_OP_ALLOC_Q_COUNTER
= 0x771,
193 MLX5_CMD_OP_DEALLOC_Q_COUNTER
= 0x772,
194 MLX5_CMD_OP_QUERY_Q_COUNTER
= 0x773,
195 MLX5_CMD_OP_SET_MONITOR_COUNTER
= 0x774,
196 MLX5_CMD_OP_ARM_MONITOR_COUNTER
= 0x775,
197 MLX5_CMD_OP_SET_PP_RATE_LIMIT
= 0x780,
198 MLX5_CMD_OP_QUERY_RATE_LIMIT
= 0x781,
199 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT
= 0x782,
200 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT
= 0x783,
201 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT
= 0x784,
202 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT
= 0x785,
203 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT
= 0x786,
204 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT
= 0x787,
205 MLX5_CMD_OP_ALLOC_PD
= 0x800,
206 MLX5_CMD_OP_DEALLOC_PD
= 0x801,
207 MLX5_CMD_OP_ALLOC_UAR
= 0x802,
208 MLX5_CMD_OP_DEALLOC_UAR
= 0x803,
209 MLX5_CMD_OP_CONFIG_INT_MODERATION
= 0x804,
210 MLX5_CMD_OP_ACCESS_REG
= 0x805,
211 MLX5_CMD_OP_ATTACH_TO_MCG
= 0x806,
212 MLX5_CMD_OP_DETACH_FROM_MCG
= 0x807,
213 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG
= 0x80a,
214 MLX5_CMD_OP_MAD_IFC
= 0x50d,
215 MLX5_CMD_OP_QUERY_MAD_DEMUX
= 0x80b,
216 MLX5_CMD_OP_SET_MAD_DEMUX
= 0x80c,
217 MLX5_CMD_OP_NOP
= 0x80d,
218 MLX5_CMD_OP_ALLOC_XRCD
= 0x80e,
219 MLX5_CMD_OP_DEALLOC_XRCD
= 0x80f,
220 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN
= 0x816,
221 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN
= 0x817,
222 MLX5_CMD_OP_QUERY_CONG_STATUS
= 0x822,
223 MLX5_CMD_OP_MODIFY_CONG_STATUS
= 0x823,
224 MLX5_CMD_OP_QUERY_CONG_PARAMS
= 0x824,
225 MLX5_CMD_OP_MODIFY_CONG_PARAMS
= 0x825,
226 MLX5_CMD_OP_QUERY_CONG_STATISTICS
= 0x826,
227 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT
= 0x827,
228 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT
= 0x828,
229 MLX5_CMD_OP_SET_L2_TABLE_ENTRY
= 0x829,
230 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY
= 0x82a,
231 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY
= 0x82b,
232 MLX5_CMD_OP_SET_WOL_ROL
= 0x830,
233 MLX5_CMD_OP_QUERY_WOL_ROL
= 0x831,
234 MLX5_CMD_OP_CREATE_LAG
= 0x840,
235 MLX5_CMD_OP_MODIFY_LAG
= 0x841,
236 MLX5_CMD_OP_QUERY_LAG
= 0x842,
237 MLX5_CMD_OP_DESTROY_LAG
= 0x843,
238 MLX5_CMD_OP_CREATE_VPORT_LAG
= 0x844,
239 MLX5_CMD_OP_DESTROY_VPORT_LAG
= 0x845,
240 MLX5_CMD_OP_CREATE_TIR
= 0x900,
241 MLX5_CMD_OP_MODIFY_TIR
= 0x901,
242 MLX5_CMD_OP_DESTROY_TIR
= 0x902,
243 MLX5_CMD_OP_QUERY_TIR
= 0x903,
244 MLX5_CMD_OP_CREATE_SQ
= 0x904,
245 MLX5_CMD_OP_MODIFY_SQ
= 0x905,
246 MLX5_CMD_OP_DESTROY_SQ
= 0x906,
247 MLX5_CMD_OP_QUERY_SQ
= 0x907,
248 MLX5_CMD_OP_CREATE_RQ
= 0x908,
249 MLX5_CMD_OP_MODIFY_RQ
= 0x909,
250 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS
= 0x910,
251 MLX5_CMD_OP_DESTROY_RQ
= 0x90a,
252 MLX5_CMD_OP_QUERY_RQ
= 0x90b,
253 MLX5_CMD_OP_CREATE_RMP
= 0x90c,
254 MLX5_CMD_OP_MODIFY_RMP
= 0x90d,
255 MLX5_CMD_OP_DESTROY_RMP
= 0x90e,
256 MLX5_CMD_OP_QUERY_RMP
= 0x90f,
257 MLX5_CMD_OP_CREATE_TIS
= 0x912,
258 MLX5_CMD_OP_MODIFY_TIS
= 0x913,
259 MLX5_CMD_OP_DESTROY_TIS
= 0x914,
260 MLX5_CMD_OP_QUERY_TIS
= 0x915,
261 MLX5_CMD_OP_CREATE_RQT
= 0x916,
262 MLX5_CMD_OP_MODIFY_RQT
= 0x917,
263 MLX5_CMD_OP_DESTROY_RQT
= 0x918,
264 MLX5_CMD_OP_QUERY_RQT
= 0x919,
265 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT
= 0x92f,
266 MLX5_CMD_OP_CREATE_FLOW_TABLE
= 0x930,
267 MLX5_CMD_OP_DESTROY_FLOW_TABLE
= 0x931,
268 MLX5_CMD_OP_QUERY_FLOW_TABLE
= 0x932,
269 MLX5_CMD_OP_CREATE_FLOW_GROUP
= 0x933,
270 MLX5_CMD_OP_DESTROY_FLOW_GROUP
= 0x934,
271 MLX5_CMD_OP_QUERY_FLOW_GROUP
= 0x935,
272 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY
= 0x936,
273 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY
= 0x937,
274 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY
= 0x938,
275 MLX5_CMD_OP_ALLOC_FLOW_COUNTER
= 0x939,
276 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER
= 0x93a,
277 MLX5_CMD_OP_QUERY_FLOW_COUNTER
= 0x93b,
278 MLX5_CMD_OP_MODIFY_FLOW_TABLE
= 0x93c,
279 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT
= 0x93d,
280 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT
= 0x93e,
281 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT
= 0x93f,
282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT
= 0x940,
283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT
= 0x941,
284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT
= 0x942,
285 MLX5_CMD_OP_FPGA_CREATE_QP
= 0x960,
286 MLX5_CMD_OP_FPGA_MODIFY_QP
= 0x961,
287 MLX5_CMD_OP_FPGA_QUERY_QP
= 0x962,
288 MLX5_CMD_OP_FPGA_DESTROY_QP
= 0x963,
289 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS
= 0x964,
290 MLX5_CMD_OP_CREATE_GENERAL_OBJECT
= 0xa00,
291 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT
= 0xa01,
292 MLX5_CMD_OP_QUERY_GENERAL_OBJECT
= 0xa02,
293 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT
= 0xa03,
294 MLX5_CMD_OP_CREATE_UCTX
= 0xa04,
295 MLX5_CMD_OP_DESTROY_UCTX
= 0xa06,
296 MLX5_CMD_OP_CREATE_UMEM
= 0xa08,
297 MLX5_CMD_OP_DESTROY_UMEM
= 0xa0a,
298 MLX5_CMD_OP_SYNC_STEERING
= 0xb00,
302 /* Valid range for general commands that don't work over an object */
304 MLX5_CMD_OP_GENERAL_START
= 0xb00,
305 MLX5_CMD_OP_GENERAL_END
= 0xd00,
308 struct mlx5_ifc_flow_table_fields_supported_bits
{
311 u8 outer_ether_type
[0x1];
312 u8 outer_ip_version
[0x1];
313 u8 outer_first_prio
[0x1];
314 u8 outer_first_cfi
[0x1];
315 u8 outer_first_vid
[0x1];
316 u8 outer_ipv4_ttl
[0x1];
317 u8 outer_second_prio
[0x1];
318 u8 outer_second_cfi
[0x1];
319 u8 outer_second_vid
[0x1];
320 u8 reserved_at_b
[0x1];
324 u8 outer_ip_protocol
[0x1];
325 u8 outer_ip_ecn
[0x1];
326 u8 outer_ip_dscp
[0x1];
327 u8 outer_udp_sport
[0x1];
328 u8 outer_udp_dport
[0x1];
329 u8 outer_tcp_sport
[0x1];
330 u8 outer_tcp_dport
[0x1];
331 u8 outer_tcp_flags
[0x1];
332 u8 outer_gre_protocol
[0x1];
333 u8 outer_gre_key
[0x1];
334 u8 outer_vxlan_vni
[0x1];
335 u8 outer_geneve_vni
[0x1];
336 u8 outer_geneve_oam
[0x1];
337 u8 outer_geneve_protocol_type
[0x1];
338 u8 outer_geneve_opt_len
[0x1];
339 u8 reserved_at_1e
[0x1];
340 u8 source_eswitch_port
[0x1];
344 u8 inner_ether_type
[0x1];
345 u8 inner_ip_version
[0x1];
346 u8 inner_first_prio
[0x1];
347 u8 inner_first_cfi
[0x1];
348 u8 inner_first_vid
[0x1];
349 u8 reserved_at_27
[0x1];
350 u8 inner_second_prio
[0x1];
351 u8 inner_second_cfi
[0x1];
352 u8 inner_second_vid
[0x1];
353 u8 reserved_at_2b
[0x1];
357 u8 inner_ip_protocol
[0x1];
358 u8 inner_ip_ecn
[0x1];
359 u8 inner_ip_dscp
[0x1];
360 u8 inner_udp_sport
[0x1];
361 u8 inner_udp_dport
[0x1];
362 u8 inner_tcp_sport
[0x1];
363 u8 inner_tcp_dport
[0x1];
364 u8 inner_tcp_flags
[0x1];
365 u8 reserved_at_37
[0x9];
367 u8 geneve_tlv_option_0_data
[0x1];
368 u8 reserved_at_41
[0x4];
369 u8 outer_first_mpls_over_udp
[0x4];
370 u8 outer_first_mpls_over_gre
[0x4];
371 u8 inner_first_mpls
[0x4];
372 u8 outer_first_mpls
[0x4];
373 u8 reserved_at_55
[0x2];
374 u8 outer_esp_spi
[0x1];
375 u8 reserved_at_58
[0x2];
378 u8 reserved_at_5b
[0x25];
381 struct mlx5_ifc_flow_table_prop_layout_bits
{
383 u8 reserved_at_1
[0x1];
384 u8 flow_counter
[0x1];
385 u8 flow_modify_en
[0x1];
387 u8 identified_miss_table_mode
[0x1];
388 u8 flow_table_modify
[0x1];
391 u8 reserved_at_9
[0x1];
394 u8 reserved_at_c
[0x1];
397 u8 reformat_and_vlan_action
[0x1];
398 u8 reserved_at_10
[0x1];
400 u8 reformat_l3_tunnel_to_l2
[0x1];
401 u8 reformat_l2_to_l3_tunnel
[0x1];
402 u8 reformat_and_modify_action
[0x1];
403 u8 reserved_at_15
[0x2];
404 u8 table_miss_action_domain
[0x1];
405 u8 termination_table
[0x1];
406 u8 reserved_at_19
[0x7];
407 u8 reserved_at_20
[0x2];
408 u8 log_max_ft_size
[0x6];
409 u8 log_max_modify_header_context
[0x8];
410 u8 max_modify_header_actions
[0x8];
411 u8 max_ft_level
[0x8];
413 u8 reserved_at_40
[0x20];
415 u8 reserved_at_60
[0x18];
416 u8 log_max_ft_num
[0x8];
418 u8 reserved_at_80
[0x18];
419 u8 log_max_destination
[0x8];
421 u8 log_max_flow_counter
[0x8];
422 u8 reserved_at_a8
[0x10];
423 u8 log_max_flow
[0x8];
425 u8 reserved_at_c0
[0x40];
427 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support
;
429 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support
;
432 struct mlx5_ifc_odp_per_transport_service_cap_bits
{
439 u8 reserved_at_6
[0x1a];
442 struct mlx5_ifc_fte_match_set_lyr_2_4_bits
{
467 u8 reserved_at_c0
[0x18];
468 u8 ttl_hoplimit
[0x8];
473 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6
;
475 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6
;
478 struct mlx5_ifc_nvgre_key_bits
{
483 union mlx5_ifc_gre_key_bits
{
484 struct mlx5_ifc_nvgre_key_bits nvgre
;
488 struct mlx5_ifc_fte_match_set_misc_bits
{
489 u8 gre_c_present
[0x1];
490 u8 reserved_at_1
[0x1];
491 u8 gre_k_present
[0x1];
492 u8 gre_s_present
[0x1];
493 u8 source_vhca_port
[0x4];
496 u8 source_eswitch_owner_vhca_id
[0x10];
497 u8 source_port
[0x10];
499 u8 outer_second_prio
[0x3];
500 u8 outer_second_cfi
[0x1];
501 u8 outer_second_vid
[0xc];
502 u8 inner_second_prio
[0x3];
503 u8 inner_second_cfi
[0x1];
504 u8 inner_second_vid
[0xc];
506 u8 outer_second_cvlan_tag
[0x1];
507 u8 inner_second_cvlan_tag
[0x1];
508 u8 outer_second_svlan_tag
[0x1];
509 u8 inner_second_svlan_tag
[0x1];
510 u8 reserved_at_64
[0xc];
511 u8 gre_protocol
[0x10];
513 union mlx5_ifc_gre_key_bits gre_key
;
516 u8 reserved_at_b8
[0x8];
519 u8 reserved_at_d8
[0x7];
522 u8 reserved_at_e0
[0xc];
523 u8 outer_ipv6_flow_label
[0x14];
525 u8 reserved_at_100
[0xc];
526 u8 inner_ipv6_flow_label
[0x14];
528 u8 reserved_at_120
[0xa];
529 u8 geneve_opt_len
[0x6];
530 u8 geneve_protocol_type
[0x10];
532 u8 reserved_at_140
[0x8];
534 u8 reserved_at_160
[0x20];
535 u8 outer_esp_spi
[0x20];
536 u8 reserved_at_1a0
[0x60];
539 struct mlx5_ifc_fte_match_mpls_bits
{
546 struct mlx5_ifc_fte_match_set_misc2_bits
{
547 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls
;
549 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls
;
551 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre
;
553 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp
;
555 u8 metadata_reg_c_7
[0x20];
557 u8 metadata_reg_c_6
[0x20];
559 u8 metadata_reg_c_5
[0x20];
561 u8 metadata_reg_c_4
[0x20];
563 u8 metadata_reg_c_3
[0x20];
565 u8 metadata_reg_c_2
[0x20];
567 u8 metadata_reg_c_1
[0x20];
569 u8 metadata_reg_c_0
[0x20];
571 u8 metadata_reg_a
[0x20];
573 u8 metadata_reg_b
[0x20];
575 u8 reserved_at_1c0
[0x40];
578 struct mlx5_ifc_fte_match_set_misc3_bits
{
579 u8 inner_tcp_seq_num
[0x20];
581 u8 outer_tcp_seq_num
[0x20];
583 u8 inner_tcp_ack_num
[0x20];
585 u8 outer_tcp_ack_num
[0x20];
587 u8 reserved_at_80
[0x8];
588 u8 outer_vxlan_gpe_vni
[0x18];
590 u8 outer_vxlan_gpe_next_protocol
[0x8];
591 u8 outer_vxlan_gpe_flags
[0x8];
592 u8 reserved_at_b0
[0x10];
594 u8 icmp_header_data
[0x20];
596 u8 icmpv6_header_data
[0x20];
603 u8 geneve_tlv_option_0_data
[0x20];
605 u8 reserved_at_140
[0xc0];
608 struct mlx5_ifc_cmd_pas_bits
{
612 u8 reserved_at_34
[0xc];
615 struct mlx5_ifc_uint64_bits
{
622 MLX5_ADS_STAT_RATE_NO_LIMIT
= 0x0,
623 MLX5_ADS_STAT_RATE_2_5GBPS
= 0x7,
624 MLX5_ADS_STAT_RATE_10GBPS
= 0x8,
625 MLX5_ADS_STAT_RATE_30GBPS
= 0x9,
626 MLX5_ADS_STAT_RATE_5GBPS
= 0xa,
627 MLX5_ADS_STAT_RATE_20GBPS
= 0xb,
628 MLX5_ADS_STAT_RATE_40GBPS
= 0xc,
629 MLX5_ADS_STAT_RATE_60GBPS
= 0xd,
630 MLX5_ADS_STAT_RATE_80GBPS
= 0xe,
631 MLX5_ADS_STAT_RATE_120GBPS
= 0xf,
634 struct mlx5_ifc_ads_bits
{
637 u8 reserved_at_2
[0xe];
640 u8 reserved_at_20
[0x8];
646 u8 reserved_at_45
[0x3];
647 u8 src_addr_index
[0x8];
648 u8 reserved_at_50
[0x4];
652 u8 reserved_at_60
[0x4];
656 u8 rgid_rip
[16][0x8];
658 u8 reserved_at_100
[0x4];
661 u8 reserved_at_106
[0x1];
670 u8 vhca_port_num
[0x8];
676 struct mlx5_ifc_flow_table_nic_cap_bits
{
677 u8 nic_rx_multi_path_tirs
[0x1];
678 u8 nic_rx_multi_path_tirs_fts
[0x1];
679 u8 allow_sniffer_and_nic_rx_shared_tir
[0x1];
680 u8 reserved_at_3
[0x1d];
681 u8 encap_general_header
[0x1];
682 u8 reserved_at_21
[0xa];
683 u8 log_max_packet_reformat_context
[0x5];
684 u8 reserved_at_30
[0x6];
685 u8 max_encap_header_size
[0xa];
686 u8 reserved_at_40
[0x1c0];
688 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive
;
690 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma
;
692 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer
;
694 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit
;
696 u8 reserved_at_a00
[0x200];
698 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer
;
700 u8 reserved_at_e00
[0x1200];
702 u8 sw_steering_nic_rx_action_drop_icm_address
[0x40];
704 u8 sw_steering_nic_tx_action_drop_icm_address
[0x40];
706 u8 sw_steering_nic_tx_action_allow_icm_address
[0x40];
708 u8 reserved_at_20c0
[0x5f40];
712 MLX5_FDB_TO_VPORT_REG_C_0
= 0x01,
713 MLX5_FDB_TO_VPORT_REG_C_1
= 0x02,
714 MLX5_FDB_TO_VPORT_REG_C_2
= 0x04,
715 MLX5_FDB_TO_VPORT_REG_C_3
= 0x08,
716 MLX5_FDB_TO_VPORT_REG_C_4
= 0x10,
717 MLX5_FDB_TO_VPORT_REG_C_5
= 0x20,
718 MLX5_FDB_TO_VPORT_REG_C_6
= 0x40,
719 MLX5_FDB_TO_VPORT_REG_C_7
= 0x80,
722 struct mlx5_ifc_flow_table_eswitch_cap_bits
{
723 u8 fdb_to_vport_reg_c_id
[0x8];
724 u8 reserved_at_8
[0xf];
726 u8 reserved_at_18
[0x2];
727 u8 multi_fdb_encap
[0x1];
728 u8 reserved_at_1b
[0x1];
729 u8 fdb_multi_path_to_table
[0x1];
730 u8 reserved_at_1d
[0x3];
732 u8 reserved_at_20
[0x1e0];
734 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb
;
736 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress
;
738 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress
;
740 u8 reserved_at_800
[0x1000];
742 u8 sw_steering_fdb_action_drop_icm_address_rx
[0x40];
744 u8 sw_steering_fdb_action_drop_icm_address_tx
[0x40];
746 u8 sw_steering_uplink_icm_address_rx
[0x40];
748 u8 sw_steering_uplink_icm_address_tx
[0x40];
750 u8 reserved_at_1900
[0x6700];
754 MLX5_COUNTER_SOURCE_ESWITCH
= 0x0,
755 MLX5_COUNTER_FLOW_ESWITCH
= 0x1,
758 struct mlx5_ifc_e_switch_cap_bits
{
759 u8 vport_svlan_strip
[0x1];
760 u8 vport_cvlan_strip
[0x1];
761 u8 vport_svlan_insert
[0x1];
762 u8 vport_cvlan_insert_if_not_exist
[0x1];
763 u8 vport_cvlan_insert_overwrite
[0x1];
764 u8 reserved_at_5
[0x3];
765 u8 esw_uplink_ingress_acl
[0x1];
766 u8 reserved_at_9
[0x10];
767 u8 esw_functions_changed
[0x1];
768 u8 reserved_at_1a
[0x1];
769 u8 ecpf_vport_exists
[0x1];
770 u8 counter_eswitch_affinity
[0x1];
771 u8 merged_eswitch
[0x1];
772 u8 nic_vport_node_guid_modify
[0x1];
773 u8 nic_vport_port_guid_modify
[0x1];
775 u8 vxlan_encap_decap
[0x1];
776 u8 nvgre_encap_decap
[0x1];
777 u8 reserved_at_22
[0x1];
778 u8 log_max_fdb_encap_uplink
[0x5];
779 u8 reserved_at_21
[0x3];
780 u8 log_max_packet_reformat_context
[0x5];
782 u8 max_encap_header_size
[0xa];
784 u8 reserved_at_40
[0xb];
785 u8 log_max_esw_sf
[0x5];
786 u8 esw_sf_base_id
[0x10];
788 u8 reserved_at_60
[0x7a0];
792 struct mlx5_ifc_qos_cap_bits
{
793 u8 packet_pacing
[0x1];
794 u8 esw_scheduling
[0x1];
795 u8 esw_bw_share
[0x1];
796 u8 esw_rate_limit
[0x1];
797 u8 reserved_at_4
[0x1];
798 u8 packet_pacing_burst_bound
[0x1];
799 u8 packet_pacing_typical_size
[0x1];
800 u8 reserved_at_7
[0x19];
802 u8 reserved_at_20
[0x20];
804 u8 packet_pacing_max_rate
[0x20];
806 u8 packet_pacing_min_rate
[0x20];
808 u8 reserved_at_80
[0x10];
809 u8 packet_pacing_rate_table_size
[0x10];
811 u8 esw_element_type
[0x10];
812 u8 esw_tsar_type
[0x10];
814 u8 reserved_at_c0
[0x10];
815 u8 max_qos_para_vport
[0x10];
817 u8 max_tsar_bw_share
[0x20];
819 u8 reserved_at_100
[0x700];
822 struct mlx5_ifc_debug_cap_bits
{
823 u8 core_dump_general
[0x1];
824 u8 core_dump_qp
[0x1];
825 u8 reserved_at_2
[0x1e];
827 u8 reserved_at_20
[0x2];
828 u8 stall_detect
[0x1];
829 u8 reserved_at_23
[0x1d];
831 u8 reserved_at_40
[0x7c0];
834 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
{
838 u8 lro_psh_flag
[0x1];
839 u8 lro_time_stamp
[0x1];
840 u8 reserved_at_5
[0x2];
841 u8 wqe_vlan_insert
[0x1];
842 u8 self_lb_en_modifiable
[0x1];
843 u8 reserved_at_9
[0x2];
845 u8 multi_pkt_send_wqe
[0x2];
846 u8 wqe_inline_mode
[0x2];
847 u8 rss_ind_tbl_cap
[0x4];
850 u8 enhanced_multi_pkt_send_wqe
[0x1];
851 u8 tunnel_lso_const_out_ip_id
[0x1];
852 u8 reserved_at_1c
[0x2];
853 u8 tunnel_stateless_gre
[0x1];
854 u8 tunnel_stateless_vxlan
[0x1];
859 u8 cqe_checksum_full
[0x1];
860 u8 reserved_at_24
[0x5];
861 u8 tunnel_stateless_ip_over_ip
[0x1];
862 u8 reserved_at_2a
[0x6];
863 u8 max_vxlan_udp_ports
[0x8];
864 u8 reserved_at_38
[0x6];
865 u8 max_geneve_opt_len
[0x1];
866 u8 tunnel_stateless_geneve_rx
[0x1];
868 u8 reserved_at_40
[0x10];
869 u8 lro_min_mss_size
[0x10];
871 u8 reserved_at_60
[0x120];
873 u8 lro_timer_supported_periods
[4][0x20];
875 u8 reserved_at_200
[0x600];
878 struct mlx5_ifc_roce_cap_bits
{
880 u8 reserved_at_1
[0x1f];
882 u8 reserved_at_20
[0x60];
884 u8 reserved_at_80
[0xc];
886 u8 reserved_at_90
[0x8];
887 u8 roce_version
[0x8];
889 u8 reserved_at_a0
[0x10];
890 u8 r_roce_dest_udp_port
[0x10];
892 u8 r_roce_max_src_udp_port
[0x10];
893 u8 r_roce_min_src_udp_port
[0x10];
895 u8 reserved_at_e0
[0x10];
896 u8 roce_address_table_size
[0x10];
898 u8 reserved_at_100
[0x700];
901 struct mlx5_ifc_sync_steering_in_bits
{
905 u8 reserved_at_20
[0x10];
908 u8 reserved_at_40
[0xc0];
911 struct mlx5_ifc_sync_steering_out_bits
{
913 u8 reserved_at_8
[0x18];
917 u8 reserved_at_40
[0x40];
920 struct mlx5_ifc_device_mem_cap_bits
{
922 u8 reserved_at_1
[0x1f];
924 u8 reserved_at_20
[0xb];
925 u8 log_min_memic_alloc_size
[0x5];
926 u8 reserved_at_30
[0x8];
927 u8 log_max_memic_addr_alignment
[0x8];
929 u8 memic_bar_start_addr
[0x40];
931 u8 memic_bar_size
[0x20];
933 u8 max_memic_size
[0x20];
935 u8 steering_sw_icm_start_address
[0x40];
937 u8 reserved_at_100
[0x8];
938 u8 log_header_modify_sw_icm_size
[0x8];
939 u8 reserved_at_110
[0x2];
940 u8 log_sw_icm_alloc_granularity
[0x6];
941 u8 log_steering_sw_icm_size
[0x8];
943 u8 reserved_at_120
[0x20];
945 u8 header_modify_sw_icm_start_address
[0x40];
947 u8 reserved_at_180
[0x680];
950 struct mlx5_ifc_device_event_cap_bits
{
951 u8 user_affiliated_events
[4][0x40];
953 u8 user_unaffiliated_events
[4][0x40];
957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE
= 0x0,
958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES
= 0x2,
959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES
= 0x4,
960 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES
= 0x8,
961 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES
= 0x10,
962 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES
= 0x20,
963 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES
= 0x40,
964 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES
= 0x80,
965 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES
= 0x100,
969 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE
= 0x1,
970 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES
= 0x2,
971 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES
= 0x4,
972 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES
= 0x8,
973 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES
= 0x10,
974 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES
= 0x20,
975 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES
= 0x40,
976 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES
= 0x80,
977 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES
= 0x100,
980 struct mlx5_ifc_atomic_caps_bits
{
981 u8 reserved_at_0
[0x40];
983 u8 atomic_req_8B_endianness_mode
[0x2];
984 u8 reserved_at_42
[0x4];
985 u8 supported_atomic_req_8B_endianness_mode_1
[0x1];
987 u8 reserved_at_47
[0x19];
989 u8 reserved_at_60
[0x20];
991 u8 reserved_at_80
[0x10];
992 u8 atomic_operations
[0x10];
994 u8 reserved_at_a0
[0x10];
995 u8 atomic_size_qp
[0x10];
997 u8 reserved_at_c0
[0x10];
998 u8 atomic_size_dc
[0x10];
1000 u8 reserved_at_e0
[0x720];
1003 struct mlx5_ifc_odp_cap_bits
{
1004 u8 reserved_at_0
[0x40];
1007 u8 reserved_at_41
[0x1f];
1009 u8 reserved_at_60
[0x20];
1011 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps
;
1013 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps
;
1015 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps
;
1017 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps
;
1019 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps
;
1021 u8 reserved_at_120
[0x6E0];
1024 struct mlx5_ifc_calc_op
{
1025 u8 reserved_at_0
[0x10];
1026 u8 reserved_at_10
[0x9];
1027 u8 op_swap_endianness
[0x1];
1036 struct mlx5_ifc_vector_calc_cap_bits
{
1037 u8 calc_matrix
[0x1];
1038 u8 reserved_at_1
[0x1f];
1039 u8 reserved_at_20
[0x8];
1040 u8 max_vec_count
[0x8];
1041 u8 reserved_at_30
[0xd];
1042 u8 max_chunk_size
[0x3];
1043 struct mlx5_ifc_calc_op calc0
;
1044 struct mlx5_ifc_calc_op calc1
;
1045 struct mlx5_ifc_calc_op calc2
;
1046 struct mlx5_ifc_calc_op calc3
;
1048 u8 reserved_at_c0
[0x720];
1051 struct mlx5_ifc_tls_cap_bits
{
1052 u8 tls_1_2_aes_gcm_128
[0x1];
1053 u8 tls_1_3_aes_gcm_128
[0x1];
1054 u8 tls_1_2_aes_gcm_256
[0x1];
1055 u8 tls_1_3_aes_gcm_256
[0x1];
1056 u8 reserved_at_4
[0x1c];
1058 u8 reserved_at_20
[0x7e0];
1062 MLX5_WQ_TYPE_LINKED_LIST
= 0x0,
1063 MLX5_WQ_TYPE_CYCLIC
= 0x1,
1064 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
= 0x2,
1065 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ
= 0x3,
1069 MLX5_WQ_END_PAD_MODE_NONE
= 0x0,
1070 MLX5_WQ_END_PAD_MODE_ALIGN
= 0x1,
1074 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES
= 0x0,
1075 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES
= 0x1,
1076 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES
= 0x2,
1077 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES
= 0x3,
1078 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES
= 0x4,
1082 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES
= 0x0,
1083 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES
= 0x1,
1084 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES
= 0x2,
1085 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES
= 0x3,
1086 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES
= 0x4,
1087 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES
= 0x5,
1091 MLX5_CMD_HCA_CAP_PORT_TYPE_IB
= 0x0,
1092 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET
= 0x1,
1096 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED
= 0x0,
1097 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE
= 0x1,
1098 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED
= 0x3,
1102 MLX5_CAP_PORT_TYPE_IB
= 0x0,
1103 MLX5_CAP_PORT_TYPE_ETH
= 0x1,
1107 MLX5_CAP_UMR_FENCE_STRONG
= 0x0,
1108 MLX5_CAP_UMR_FENCE_SMALL
= 0x1,
1109 MLX5_CAP_UMR_FENCE_NONE
= 0x2,
1113 MLX5_FLEX_PARSER_GENEVE_ENABLED
= 1 << 3,
1114 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED
= 1 << 7,
1115 MLX5_FLEX_PARSER_ICMP_V4_ENABLED
= 1 << 8,
1116 MLX5_FLEX_PARSER_ICMP_V6_ENABLED
= 1 << 9,
1120 MLX5_UCTX_CAP_RAW_TX
= 1UL << 0,
1121 MLX5_UCTX_CAP_INTERNAL_DEV_RES
= 1UL << 1,
1124 #define MLX5_FC_BULK_SIZE_FACTOR 128
1126 enum mlx5_fc_bulk_alloc_bitmask
{
1127 MLX5_FC_BULK_128
= (1 << 0),
1128 MLX5_FC_BULK_256
= (1 << 1),
1129 MLX5_FC_BULK_512
= (1 << 2),
1130 MLX5_FC_BULK_1024
= (1 << 3),
1131 MLX5_FC_BULK_2048
= (1 << 4),
1132 MLX5_FC_BULK_4096
= (1 << 5),
1133 MLX5_FC_BULK_8192
= (1 << 6),
1134 MLX5_FC_BULK_16384
= (1 << 7),
1137 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1139 struct mlx5_ifc_cmd_hca_cap_bits
{
1140 u8 reserved_at_0
[0x30];
1143 u8 reserved_at_40
[0x40];
1145 u8 log_max_srq_sz
[0x8];
1146 u8 log_max_qp_sz
[0x8];
1148 u8 reserved_at_91
[0x7];
1149 u8 prio_tag_required
[0x1];
1150 u8 reserved_at_99
[0x2];
1153 u8 reserved_at_a0
[0xb];
1154 u8 log_max_srq
[0x5];
1155 u8 reserved_at_b0
[0x10];
1157 u8 max_sgl_for_optimized_performance
[0x8];
1158 u8 log_max_cq_sz
[0x8];
1159 u8 reserved_at_d0
[0xb];
1162 u8 log_max_eq_sz
[0x8];
1163 u8 reserved_at_e8
[0x2];
1164 u8 log_max_mkey
[0x6];
1165 u8 reserved_at_f0
[0x8];
1166 u8 dump_fill_mkey
[0x1];
1167 u8 reserved_at_f9
[0x2];
1168 u8 fast_teardown
[0x1];
1171 u8 max_indirection
[0x8];
1172 u8 fixed_buffer_size
[0x1];
1173 u8 log_max_mrw_sz
[0x7];
1174 u8 force_teardown
[0x1];
1175 u8 reserved_at_111
[0x1];
1176 u8 log_max_bsf_list_size
[0x6];
1177 u8 umr_extended_translation_offset
[0x1];
1179 u8 log_max_klm_list_size
[0x6];
1181 u8 reserved_at_120
[0xa];
1182 u8 log_max_ra_req_dc
[0x6];
1183 u8 reserved_at_130
[0xa];
1184 u8 log_max_ra_res_dc
[0x6];
1186 u8 reserved_at_140
[0xa];
1187 u8 log_max_ra_req_qp
[0x6];
1188 u8 reserved_at_150
[0xa];
1189 u8 log_max_ra_res_qp
[0x6];
1192 u8 cc_query_allowed
[0x1];
1193 u8 cc_modify_allowed
[0x1];
1195 u8 cache_line_128byte
[0x1];
1196 u8 reserved_at_165
[0x4];
1197 u8 rts2rts_qp_counters_set_id
[0x1];
1198 u8 reserved_at_16a
[0x2];
1199 u8 vnic_env_int_rq_oob
[0x1];
1201 u8 reserved_at_16e
[0x1];
1203 u8 gid_table_size
[0x10];
1205 u8 out_of_seq_cnt
[0x1];
1206 u8 vport_counters
[0x1];
1207 u8 retransmission_q_counters
[0x1];
1209 u8 modify_rq_counter_set_id
[0x1];
1210 u8 rq_delay_drop
[0x1];
1212 u8 pkey_table_size
[0x10];
1214 u8 vport_group_manager
[0x1];
1215 u8 vhca_group_manager
[0x1];
1218 u8 vnic_env_queue_counters
[0x1];
1220 u8 nic_flow_table
[0x1];
1221 u8 eswitch_manager
[0x1];
1222 u8 device_memory
[0x1];
1225 u8 local_ca_ack_delay
[0x5];
1226 u8 port_module_event
[0x1];
1227 u8 enhanced_error_q_counters
[0x1];
1228 u8 ports_check
[0x1];
1229 u8 reserved_at_1b3
[0x1];
1230 u8 disable_link_up
[0x1];
1235 u8 reserved_at_1c0
[0x1];
1238 u8 log_max_msg
[0x5];
1239 u8 reserved_at_1c8
[0x4];
1241 u8 temp_warn_event
[0x1];
1243 u8 general_notification_event
[0x1];
1244 u8 reserved_at_1d3
[0x2];
1248 u8 reserved_at_1d8
[0x1];
1257 u8 stat_rate_support
[0x10];
1258 u8 reserved_at_1f0
[0xc];
1259 u8 cqe_version
[0x4];
1261 u8 compact_address_vector
[0x1];
1262 u8 striding_rq
[0x1];
1263 u8 reserved_at_202
[0x1];
1264 u8 ipoib_enhanced_offloads
[0x1];
1265 u8 ipoib_basic_offloads
[0x1];
1266 u8 reserved_at_205
[0x1];
1267 u8 repeated_block_disabled
[0x1];
1268 u8 umr_modify_entity_size_disabled
[0x1];
1269 u8 umr_modify_atomic_disabled
[0x1];
1270 u8 umr_indirect_mkey_disabled
[0x1];
1272 u8 dc_req_scat_data_cqe
[0x1];
1273 u8 reserved_at_20d
[0x2];
1274 u8 drain_sigerr
[0x1];
1275 u8 cmdif_checksum
[0x2];
1277 u8 reserved_at_213
[0x1];
1278 u8 wq_signature
[0x1];
1279 u8 sctr_data_cqe
[0x1];
1280 u8 reserved_at_216
[0x1];
1286 u8 eth_net_offloads
[0x1];
1289 u8 reserved_at_21f
[0x1];
1293 u8 cq_moderation
[0x1];
1294 u8 reserved_at_223
[0x3];
1295 u8 cq_eq_remap
[0x1];
1297 u8 block_lb_mc
[0x1];
1298 u8 reserved_at_229
[0x1];
1299 u8 scqe_break_moderation
[0x1];
1300 u8 cq_period_start_from_cqe
[0x1];
1302 u8 reserved_at_22d
[0x1];
1304 u8 vector_calc
[0x1];
1305 u8 umr_ptr_rlky
[0x1];
1307 u8 qp_packet_based
[0x1];
1308 u8 reserved_at_233
[0x3];
1311 u8 set_deth_sqpn
[0x1];
1312 u8 reserved_at_239
[0x3];
1319 u8 reserved_at_241
[0x9];
1321 u8 reserved_at_250
[0x8];
1325 u8 driver_version
[0x1];
1326 u8 pad_tx_eth_packet
[0x1];
1327 u8 reserved_at_263
[0x8];
1328 u8 log_bf_reg_size
[0x5];
1330 u8 reserved_at_270
[0x8];
1331 u8 lag_tx_port_affinity
[0x1];
1332 u8 reserved_at_279
[0x2];
1334 u8 num_lag_ports
[0x4];
1336 u8 reserved_at_280
[0x10];
1337 u8 max_wqe_sz_sq
[0x10];
1339 u8 reserved_at_2a0
[0x10];
1340 u8 max_wqe_sz_rq
[0x10];
1342 u8 max_flow_counter_31_16
[0x10];
1343 u8 max_wqe_sz_sq_dc
[0x10];
1345 u8 reserved_at_2e0
[0x7];
1346 u8 max_qp_mcg
[0x19];
1348 u8 reserved_at_300
[0x10];
1349 u8 flow_counter_bulk_alloc
[0x8];
1350 u8 log_max_mcg
[0x8];
1352 u8 reserved_at_320
[0x3];
1353 u8 log_max_transport_domain
[0x5];
1354 u8 reserved_at_328
[0x3];
1356 u8 reserved_at_330
[0xb];
1357 u8 log_max_xrcd
[0x5];
1359 u8 nic_receive_steering_discard
[0x1];
1360 u8 receive_discard_vport_down
[0x1];
1361 u8 transmit_discard_vport_down
[0x1];
1362 u8 reserved_at_343
[0x5];
1363 u8 log_max_flow_counter_bulk
[0x8];
1364 u8 max_flow_counter_15_0
[0x10];
1367 u8 reserved_at_360
[0x3];
1369 u8 reserved_at_368
[0x3];
1371 u8 reserved_at_370
[0x3];
1372 u8 log_max_tir
[0x5];
1373 u8 reserved_at_378
[0x3];
1374 u8 log_max_tis
[0x5];
1376 u8 basic_cyclic_rcv_wqe
[0x1];
1377 u8 reserved_at_381
[0x2];
1378 u8 log_max_rmp
[0x5];
1379 u8 reserved_at_388
[0x3];
1380 u8 log_max_rqt
[0x5];
1381 u8 reserved_at_390
[0x3];
1382 u8 log_max_rqt_size
[0x5];
1383 u8 reserved_at_398
[0x3];
1384 u8 log_max_tis_per_sq
[0x5];
1386 u8 ext_stride_num_range
[0x1];
1387 u8 reserved_at_3a1
[0x2];
1388 u8 log_max_stride_sz_rq
[0x5];
1389 u8 reserved_at_3a8
[0x3];
1390 u8 log_min_stride_sz_rq
[0x5];
1391 u8 reserved_at_3b0
[0x3];
1392 u8 log_max_stride_sz_sq
[0x5];
1393 u8 reserved_at_3b8
[0x3];
1394 u8 log_min_stride_sz_sq
[0x5];
1397 u8 reserved_at_3c1
[0x2];
1398 u8 log_max_hairpin_queues
[0x5];
1399 u8 reserved_at_3c8
[0x3];
1400 u8 log_max_hairpin_wq_data_sz
[0x5];
1401 u8 reserved_at_3d0
[0x3];
1402 u8 log_max_hairpin_num_packets
[0x5];
1403 u8 reserved_at_3d8
[0x3];
1404 u8 log_max_wq_sz
[0x5];
1406 u8 nic_vport_change_event
[0x1];
1407 u8 disable_local_lb_uc
[0x1];
1408 u8 disable_local_lb_mc
[0x1];
1409 u8 log_min_hairpin_wq_data_sz
[0x5];
1410 u8 reserved_at_3e8
[0x3];
1411 u8 log_max_vlan_list
[0x5];
1412 u8 reserved_at_3f0
[0x3];
1413 u8 log_max_current_mc_list
[0x5];
1414 u8 reserved_at_3f8
[0x3];
1415 u8 log_max_current_uc_list
[0x5];
1417 u8 general_obj_types
[0x40];
1419 u8 reserved_at_440
[0x20];
1422 u8 reserved_at_461
[0x2];
1423 u8 log_max_uctx
[0x5];
1424 u8 reserved_at_468
[0x3];
1425 u8 log_max_umem
[0x5];
1426 u8 max_num_eqs
[0x10];
1428 u8 reserved_at_480
[0x3];
1429 u8 log_max_l2_table
[0x5];
1430 u8 reserved_at_488
[0x8];
1431 u8 log_uar_page_sz
[0x10];
1433 u8 reserved_at_4a0
[0x20];
1434 u8 device_frequency_mhz
[0x20];
1435 u8 device_frequency_khz
[0x20];
1437 u8 reserved_at_500
[0x20];
1438 u8 num_of_uars_per_page
[0x20];
1440 u8 flex_parser_protocols
[0x20];
1442 u8 max_geneve_tlv_options
[0x8];
1443 u8 reserved_at_568
[0x3];
1444 u8 max_geneve_tlv_option_data_len
[0x5];
1445 u8 reserved_at_570
[0x10];
1447 u8 reserved_at_580
[0x33];
1448 u8 log_max_dek
[0x5];
1449 u8 reserved_at_5b8
[0x4];
1450 u8 mini_cqe_resp_stride_index
[0x1];
1451 u8 cqe_128_always
[0x1];
1452 u8 cqe_compression_128
[0x1];
1453 u8 cqe_compression
[0x1];
1455 u8 cqe_compression_timeout
[0x10];
1456 u8 cqe_compression_max_num
[0x10];
1458 u8 reserved_at_5e0
[0x10];
1459 u8 tag_matching
[0x1];
1460 u8 rndv_offload_rc
[0x1];
1461 u8 rndv_offload_dc
[0x1];
1462 u8 log_tag_matching_list_sz
[0x5];
1463 u8 reserved_at_5f8
[0x3];
1464 u8 log_max_xrq
[0x5];
1466 u8 affiliate_nic_vport_criteria
[0x8];
1467 u8 native_port_num
[0x8];
1468 u8 num_vhca_ports
[0x8];
1469 u8 reserved_at_618
[0x6];
1470 u8 sw_owner_id
[0x1];
1471 u8 reserved_at_61f
[0x1];
1473 u8 max_num_of_monitor_counters
[0x10];
1474 u8 num_ppcnt_monitor_counters
[0x10];
1476 u8 reserved_at_640
[0x10];
1477 u8 num_q_monitor_counters
[0x10];
1479 u8 reserved_at_660
[0x20];
1482 u8 sf_set_partition
[0x1];
1483 u8 reserved_at_682
[0x1];
1485 u8 reserved_at_688
[0x8];
1486 u8 log_min_sf_size
[0x8];
1487 u8 max_num_sf_partitions
[0x8];
1491 u8 reserved_at_6c0
[0x4];
1492 u8 flex_parser_id_geneve_tlv_option_0
[0x4];
1493 u8 flex_parser_id_icmp_dw1
[0x4];
1494 u8 flex_parser_id_icmp_dw0
[0x4];
1495 u8 flex_parser_id_icmpv6_dw1
[0x4];
1496 u8 flex_parser_id_icmpv6_dw0
[0x4];
1497 u8 flex_parser_id_outer_first_mpls_over_gre
[0x4];
1498 u8 flex_parser_id_outer_first_mpls_over_udp_label
[0x4];
1500 u8 reserved_at_6e0
[0x10];
1501 u8 sf_base_id
[0x10];
1503 u8 reserved_at_700
[0x80];
1504 u8 vhca_tunnel_commands
[0x40];
1505 u8 reserved_at_7c0
[0x40];
1508 enum mlx5_flow_destination_type
{
1509 MLX5_FLOW_DESTINATION_TYPE_VPORT
= 0x0,
1510 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE
= 0x1,
1511 MLX5_FLOW_DESTINATION_TYPE_TIR
= 0x2,
1513 MLX5_FLOW_DESTINATION_TYPE_PORT
= 0x99,
1514 MLX5_FLOW_DESTINATION_TYPE_COUNTER
= 0x100,
1515 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM
= 0x101,
1518 enum mlx5_flow_table_miss_action
{
1519 MLX5_FLOW_TABLE_MISS_ACTION_DEF
,
1520 MLX5_FLOW_TABLE_MISS_ACTION_FWD
,
1521 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN
,
1524 struct mlx5_ifc_dest_format_struct_bits
{
1525 u8 destination_type
[0x8];
1526 u8 destination_id
[0x18];
1528 u8 destination_eswitch_owner_vhca_id_valid
[0x1];
1529 u8 packet_reformat
[0x1];
1530 u8 reserved_at_22
[0xe];
1531 u8 destination_eswitch_owner_vhca_id
[0x10];
1534 struct mlx5_ifc_flow_counter_list_bits
{
1535 u8 flow_counter_id
[0x20];
1537 u8 reserved_at_20
[0x20];
1540 struct mlx5_ifc_extended_dest_format_bits
{
1541 struct mlx5_ifc_dest_format_struct_bits destination_entry
;
1543 u8 packet_reformat_id
[0x20];
1545 u8 reserved_at_60
[0x20];
1548 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits
{
1549 struct mlx5_ifc_extended_dest_format_bits extended_dest_format
;
1550 struct mlx5_ifc_flow_counter_list_bits flow_counter_list
;
1553 struct mlx5_ifc_fte_match_param_bits
{
1554 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers
;
1556 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters
;
1558 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers
;
1560 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2
;
1562 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3
;
1564 u8 reserved_at_a00
[0x600];
1568 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP
= 0x0,
1569 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP
= 0x1,
1570 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT
= 0x2,
1571 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT
= 0x3,
1572 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI
= 0x4,
1575 struct mlx5_ifc_rx_hash_field_select_bits
{
1576 u8 l3_prot_type
[0x1];
1577 u8 l4_prot_type
[0x1];
1578 u8 selected_fields
[0x1e];
1582 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST
= 0x0,
1583 MLX5_WQ_WQ_TYPE_WQ_CYCLIC
= 0x1,
1587 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE
= 0x0,
1588 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN
= 0x1,
1591 struct mlx5_ifc_wq_bits
{
1593 u8 wq_signature
[0x1];
1594 u8 end_padding_mode
[0x2];
1596 u8 reserved_at_8
[0x18];
1598 u8 hds_skip_first_sge
[0x1];
1599 u8 log2_hds_buf_size
[0x3];
1600 u8 reserved_at_24
[0x7];
1601 u8 page_offset
[0x5];
1604 u8 reserved_at_40
[0x8];
1607 u8 reserved_at_60
[0x8];
1612 u8 hw_counter
[0x20];
1614 u8 sw_counter
[0x20];
1616 u8 reserved_at_100
[0xc];
1617 u8 log_wq_stride
[0x4];
1618 u8 reserved_at_110
[0x3];
1619 u8 log_wq_pg_sz
[0x5];
1620 u8 reserved_at_118
[0x3];
1623 u8 dbr_umem_valid
[0x1];
1624 u8 wq_umem_valid
[0x1];
1625 u8 reserved_at_122
[0x1];
1626 u8 log_hairpin_num_packets
[0x5];
1627 u8 reserved_at_128
[0x3];
1628 u8 log_hairpin_data_sz
[0x5];
1630 u8 reserved_at_130
[0x4];
1631 u8 log_wqe_num_of_strides
[0x4];
1632 u8 two_byte_shift_en
[0x1];
1633 u8 reserved_at_139
[0x4];
1634 u8 log_wqe_stride_size
[0x3];
1636 u8 reserved_at_140
[0x4c0];
1638 struct mlx5_ifc_cmd_pas_bits pas
[0];
1641 struct mlx5_ifc_rq_num_bits
{
1642 u8 reserved_at_0
[0x8];
1646 struct mlx5_ifc_mac_address_layout_bits
{
1647 u8 reserved_at_0
[0x10];
1648 u8 mac_addr_47_32
[0x10];
1650 u8 mac_addr_31_0
[0x20];
1653 struct mlx5_ifc_vlan_layout_bits
{
1654 u8 reserved_at_0
[0x14];
1657 u8 reserved_at_20
[0x20];
1660 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits
{
1661 u8 reserved_at_0
[0xa0];
1663 u8 min_time_between_cnps
[0x20];
1665 u8 reserved_at_c0
[0x12];
1667 u8 reserved_at_d8
[0x4];
1668 u8 cnp_prio_mode
[0x1];
1669 u8 cnp_802p_prio
[0x3];
1671 u8 reserved_at_e0
[0x720];
1674 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits
{
1675 u8 reserved_at_0
[0x60];
1677 u8 reserved_at_60
[0x4];
1678 u8 clamp_tgt_rate
[0x1];
1679 u8 reserved_at_65
[0x3];
1680 u8 clamp_tgt_rate_after_time_inc
[0x1];
1681 u8 reserved_at_69
[0x17];
1683 u8 reserved_at_80
[0x20];
1685 u8 rpg_time_reset
[0x20];
1687 u8 rpg_byte_reset
[0x20];
1689 u8 rpg_threshold
[0x20];
1691 u8 rpg_max_rate
[0x20];
1693 u8 rpg_ai_rate
[0x20];
1695 u8 rpg_hai_rate
[0x20];
1699 u8 rpg_min_dec_fac
[0x20];
1701 u8 rpg_min_rate
[0x20];
1703 u8 reserved_at_1c0
[0xe0];
1705 u8 rate_to_set_on_first_cnp
[0x20];
1709 u8 dce_tcp_rtt
[0x20];
1711 u8 rate_reduce_monitor_period
[0x20];
1713 u8 reserved_at_320
[0x20];
1715 u8 initial_alpha_value
[0x20];
1717 u8 reserved_at_360
[0x4a0];
1720 struct mlx5_ifc_cong_control_802_1qau_rp_bits
{
1721 u8 reserved_at_0
[0x80];
1723 u8 rppp_max_rps
[0x20];
1725 u8 rpg_time_reset
[0x20];
1727 u8 rpg_byte_reset
[0x20];
1729 u8 rpg_threshold
[0x20];
1731 u8 rpg_max_rate
[0x20];
1733 u8 rpg_ai_rate
[0x20];
1735 u8 rpg_hai_rate
[0x20];
1739 u8 rpg_min_dec_fac
[0x20];
1741 u8 rpg_min_rate
[0x20];
1743 u8 reserved_at_1c0
[0x640];
1747 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE
= 0x1,
1748 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET
= 0x2,
1749 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE
= 0x4,
1752 struct mlx5_ifc_resize_field_select_bits
{
1753 u8 resize_field_select
[0x20];
1757 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD
= 0x1,
1758 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT
= 0x2,
1759 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI
= 0x4,
1760 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN
= 0x8,
1763 struct mlx5_ifc_modify_field_select_bits
{
1764 u8 modify_field_select
[0x20];
1767 struct mlx5_ifc_field_select_r_roce_np_bits
{
1768 u8 field_select_r_roce_np
[0x20];
1771 struct mlx5_ifc_field_select_r_roce_rp_bits
{
1772 u8 field_select_r_roce_rp
[0x20];
1776 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS
= 0x4,
1777 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET
= 0x8,
1778 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET
= 0x10,
1779 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD
= 0x20,
1780 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE
= 0x40,
1781 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE
= 0x80,
1782 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE
= 0x100,
1783 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD
= 0x200,
1784 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC
= 0x400,
1785 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE
= 0x800,
1788 struct mlx5_ifc_field_select_802_1qau_rp_bits
{
1789 u8 field_select_8021qaurp
[0x20];
1792 struct mlx5_ifc_phys_layer_cntrs_bits
{
1793 u8 time_since_last_clear_high
[0x20];
1795 u8 time_since_last_clear_low
[0x20];
1797 u8 symbol_errors_high
[0x20];
1799 u8 symbol_errors_low
[0x20];
1801 u8 sync_headers_errors_high
[0x20];
1803 u8 sync_headers_errors_low
[0x20];
1805 u8 edpl_bip_errors_lane0_high
[0x20];
1807 u8 edpl_bip_errors_lane0_low
[0x20];
1809 u8 edpl_bip_errors_lane1_high
[0x20];
1811 u8 edpl_bip_errors_lane1_low
[0x20];
1813 u8 edpl_bip_errors_lane2_high
[0x20];
1815 u8 edpl_bip_errors_lane2_low
[0x20];
1817 u8 edpl_bip_errors_lane3_high
[0x20];
1819 u8 edpl_bip_errors_lane3_low
[0x20];
1821 u8 fc_fec_corrected_blocks_lane0_high
[0x20];
1823 u8 fc_fec_corrected_blocks_lane0_low
[0x20];
1825 u8 fc_fec_corrected_blocks_lane1_high
[0x20];
1827 u8 fc_fec_corrected_blocks_lane1_low
[0x20];
1829 u8 fc_fec_corrected_blocks_lane2_high
[0x20];
1831 u8 fc_fec_corrected_blocks_lane2_low
[0x20];
1833 u8 fc_fec_corrected_blocks_lane3_high
[0x20];
1835 u8 fc_fec_corrected_blocks_lane3_low
[0x20];
1837 u8 fc_fec_uncorrectable_blocks_lane0_high
[0x20];
1839 u8 fc_fec_uncorrectable_blocks_lane0_low
[0x20];
1841 u8 fc_fec_uncorrectable_blocks_lane1_high
[0x20];
1843 u8 fc_fec_uncorrectable_blocks_lane1_low
[0x20];
1845 u8 fc_fec_uncorrectable_blocks_lane2_high
[0x20];
1847 u8 fc_fec_uncorrectable_blocks_lane2_low
[0x20];
1849 u8 fc_fec_uncorrectable_blocks_lane3_high
[0x20];
1851 u8 fc_fec_uncorrectable_blocks_lane3_low
[0x20];
1853 u8 rs_fec_corrected_blocks_high
[0x20];
1855 u8 rs_fec_corrected_blocks_low
[0x20];
1857 u8 rs_fec_uncorrectable_blocks_high
[0x20];
1859 u8 rs_fec_uncorrectable_blocks_low
[0x20];
1861 u8 rs_fec_no_errors_blocks_high
[0x20];
1863 u8 rs_fec_no_errors_blocks_low
[0x20];
1865 u8 rs_fec_single_error_blocks_high
[0x20];
1867 u8 rs_fec_single_error_blocks_low
[0x20];
1869 u8 rs_fec_corrected_symbols_total_high
[0x20];
1871 u8 rs_fec_corrected_symbols_total_low
[0x20];
1873 u8 rs_fec_corrected_symbols_lane0_high
[0x20];
1875 u8 rs_fec_corrected_symbols_lane0_low
[0x20];
1877 u8 rs_fec_corrected_symbols_lane1_high
[0x20];
1879 u8 rs_fec_corrected_symbols_lane1_low
[0x20];
1881 u8 rs_fec_corrected_symbols_lane2_high
[0x20];
1883 u8 rs_fec_corrected_symbols_lane2_low
[0x20];
1885 u8 rs_fec_corrected_symbols_lane3_high
[0x20];
1887 u8 rs_fec_corrected_symbols_lane3_low
[0x20];
1889 u8 link_down_events
[0x20];
1891 u8 successful_recovery_events
[0x20];
1893 u8 reserved_at_640
[0x180];
1896 struct mlx5_ifc_phys_layer_statistical_cntrs_bits
{
1897 u8 time_since_last_clear_high
[0x20];
1899 u8 time_since_last_clear_low
[0x20];
1901 u8 phy_received_bits_high
[0x20];
1903 u8 phy_received_bits_low
[0x20];
1905 u8 phy_symbol_errors_high
[0x20];
1907 u8 phy_symbol_errors_low
[0x20];
1909 u8 phy_corrected_bits_high
[0x20];
1911 u8 phy_corrected_bits_low
[0x20];
1913 u8 phy_corrected_bits_lane0_high
[0x20];
1915 u8 phy_corrected_bits_lane0_low
[0x20];
1917 u8 phy_corrected_bits_lane1_high
[0x20];
1919 u8 phy_corrected_bits_lane1_low
[0x20];
1921 u8 phy_corrected_bits_lane2_high
[0x20];
1923 u8 phy_corrected_bits_lane2_low
[0x20];
1925 u8 phy_corrected_bits_lane3_high
[0x20];
1927 u8 phy_corrected_bits_lane3_low
[0x20];
1929 u8 reserved_at_200
[0x5c0];
1932 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits
{
1933 u8 symbol_error_counter
[0x10];
1935 u8 link_error_recovery_counter
[0x8];
1937 u8 link_downed_counter
[0x8];
1939 u8 port_rcv_errors
[0x10];
1941 u8 port_rcv_remote_physical_errors
[0x10];
1943 u8 port_rcv_switch_relay_errors
[0x10];
1945 u8 port_xmit_discards
[0x10];
1947 u8 port_xmit_constraint_errors
[0x8];
1949 u8 port_rcv_constraint_errors
[0x8];
1951 u8 reserved_at_70
[0x8];
1953 u8 link_overrun_errors
[0x8];
1955 u8 reserved_at_80
[0x10];
1957 u8 vl_15_dropped
[0x10];
1959 u8 reserved_at_a0
[0x80];
1961 u8 port_xmit_wait
[0x20];
1964 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits
{
1965 u8 transmit_queue_high
[0x20];
1967 u8 transmit_queue_low
[0x20];
1969 u8 no_buffer_discard_uc_high
[0x20];
1971 u8 no_buffer_discard_uc_low
[0x20];
1973 u8 reserved_at_80
[0x740];
1976 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits
{
1977 u8 wred_discard_high
[0x20];
1979 u8 wred_discard_low
[0x20];
1981 u8 ecn_marked_tc_high
[0x20];
1983 u8 ecn_marked_tc_low
[0x20];
1985 u8 reserved_at_80
[0x740];
1988 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits
{
1989 u8 rx_octets_high
[0x20];
1991 u8 rx_octets_low
[0x20];
1993 u8 reserved_at_40
[0xc0];
1995 u8 rx_frames_high
[0x20];
1997 u8 rx_frames_low
[0x20];
1999 u8 tx_octets_high
[0x20];
2001 u8 tx_octets_low
[0x20];
2003 u8 reserved_at_180
[0xc0];
2005 u8 tx_frames_high
[0x20];
2007 u8 tx_frames_low
[0x20];
2009 u8 rx_pause_high
[0x20];
2011 u8 rx_pause_low
[0x20];
2013 u8 rx_pause_duration_high
[0x20];
2015 u8 rx_pause_duration_low
[0x20];
2017 u8 tx_pause_high
[0x20];
2019 u8 tx_pause_low
[0x20];
2021 u8 tx_pause_duration_high
[0x20];
2023 u8 tx_pause_duration_low
[0x20];
2025 u8 rx_pause_transition_high
[0x20];
2027 u8 rx_pause_transition_low
[0x20];
2029 u8 reserved_at_3c0
[0x40];
2031 u8 device_stall_minor_watermark_cnt_high
[0x20];
2033 u8 device_stall_minor_watermark_cnt_low
[0x20];
2035 u8 device_stall_critical_watermark_cnt_high
[0x20];
2037 u8 device_stall_critical_watermark_cnt_low
[0x20];
2039 u8 reserved_at_480
[0x340];
2042 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits
{
2043 u8 port_transmit_wait_high
[0x20];
2045 u8 port_transmit_wait_low
[0x20];
2047 u8 reserved_at_40
[0x100];
2049 u8 rx_buffer_almost_full_high
[0x20];
2051 u8 rx_buffer_almost_full_low
[0x20];
2053 u8 rx_buffer_full_high
[0x20];
2055 u8 rx_buffer_full_low
[0x20];
2057 u8 rx_icrc_encapsulated_high
[0x20];
2059 u8 rx_icrc_encapsulated_low
[0x20];
2061 u8 reserved_at_200
[0x5c0];
2064 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits
{
2065 u8 dot3stats_alignment_errors_high
[0x20];
2067 u8 dot3stats_alignment_errors_low
[0x20];
2069 u8 dot3stats_fcs_errors_high
[0x20];
2071 u8 dot3stats_fcs_errors_low
[0x20];
2073 u8 dot3stats_single_collision_frames_high
[0x20];
2075 u8 dot3stats_single_collision_frames_low
[0x20];
2077 u8 dot3stats_multiple_collision_frames_high
[0x20];
2079 u8 dot3stats_multiple_collision_frames_low
[0x20];
2081 u8 dot3stats_sqe_test_errors_high
[0x20];
2083 u8 dot3stats_sqe_test_errors_low
[0x20];
2085 u8 dot3stats_deferred_transmissions_high
[0x20];
2087 u8 dot3stats_deferred_transmissions_low
[0x20];
2089 u8 dot3stats_late_collisions_high
[0x20];
2091 u8 dot3stats_late_collisions_low
[0x20];
2093 u8 dot3stats_excessive_collisions_high
[0x20];
2095 u8 dot3stats_excessive_collisions_low
[0x20];
2097 u8 dot3stats_internal_mac_transmit_errors_high
[0x20];
2099 u8 dot3stats_internal_mac_transmit_errors_low
[0x20];
2101 u8 dot3stats_carrier_sense_errors_high
[0x20];
2103 u8 dot3stats_carrier_sense_errors_low
[0x20];
2105 u8 dot3stats_frame_too_longs_high
[0x20];
2107 u8 dot3stats_frame_too_longs_low
[0x20];
2109 u8 dot3stats_internal_mac_receive_errors_high
[0x20];
2111 u8 dot3stats_internal_mac_receive_errors_low
[0x20];
2113 u8 dot3stats_symbol_errors_high
[0x20];
2115 u8 dot3stats_symbol_errors_low
[0x20];
2117 u8 dot3control_in_unknown_opcodes_high
[0x20];
2119 u8 dot3control_in_unknown_opcodes_low
[0x20];
2121 u8 dot3in_pause_frames_high
[0x20];
2123 u8 dot3in_pause_frames_low
[0x20];
2125 u8 dot3out_pause_frames_high
[0x20];
2127 u8 dot3out_pause_frames_low
[0x20];
2129 u8 reserved_at_400
[0x3c0];
2132 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits
{
2133 u8 ether_stats_drop_events_high
[0x20];
2135 u8 ether_stats_drop_events_low
[0x20];
2137 u8 ether_stats_octets_high
[0x20];
2139 u8 ether_stats_octets_low
[0x20];
2141 u8 ether_stats_pkts_high
[0x20];
2143 u8 ether_stats_pkts_low
[0x20];
2145 u8 ether_stats_broadcast_pkts_high
[0x20];
2147 u8 ether_stats_broadcast_pkts_low
[0x20];
2149 u8 ether_stats_multicast_pkts_high
[0x20];
2151 u8 ether_stats_multicast_pkts_low
[0x20];
2153 u8 ether_stats_crc_align_errors_high
[0x20];
2155 u8 ether_stats_crc_align_errors_low
[0x20];
2157 u8 ether_stats_undersize_pkts_high
[0x20];
2159 u8 ether_stats_undersize_pkts_low
[0x20];
2161 u8 ether_stats_oversize_pkts_high
[0x20];
2163 u8 ether_stats_oversize_pkts_low
[0x20];
2165 u8 ether_stats_fragments_high
[0x20];
2167 u8 ether_stats_fragments_low
[0x20];
2169 u8 ether_stats_jabbers_high
[0x20];
2171 u8 ether_stats_jabbers_low
[0x20];
2173 u8 ether_stats_collisions_high
[0x20];
2175 u8 ether_stats_collisions_low
[0x20];
2177 u8 ether_stats_pkts64octets_high
[0x20];
2179 u8 ether_stats_pkts64octets_low
[0x20];
2181 u8 ether_stats_pkts65to127octets_high
[0x20];
2183 u8 ether_stats_pkts65to127octets_low
[0x20];
2185 u8 ether_stats_pkts128to255octets_high
[0x20];
2187 u8 ether_stats_pkts128to255octets_low
[0x20];
2189 u8 ether_stats_pkts256to511octets_high
[0x20];
2191 u8 ether_stats_pkts256to511octets_low
[0x20];
2193 u8 ether_stats_pkts512to1023octets_high
[0x20];
2195 u8 ether_stats_pkts512to1023octets_low
[0x20];
2197 u8 ether_stats_pkts1024to1518octets_high
[0x20];
2199 u8 ether_stats_pkts1024to1518octets_low
[0x20];
2201 u8 ether_stats_pkts1519to2047octets_high
[0x20];
2203 u8 ether_stats_pkts1519to2047octets_low
[0x20];
2205 u8 ether_stats_pkts2048to4095octets_high
[0x20];
2207 u8 ether_stats_pkts2048to4095octets_low
[0x20];
2209 u8 ether_stats_pkts4096to8191octets_high
[0x20];
2211 u8 ether_stats_pkts4096to8191octets_low
[0x20];
2213 u8 ether_stats_pkts8192to10239octets_high
[0x20];
2215 u8 ether_stats_pkts8192to10239octets_low
[0x20];
2217 u8 reserved_at_540
[0x280];
2220 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits
{
2221 u8 if_in_octets_high
[0x20];
2223 u8 if_in_octets_low
[0x20];
2225 u8 if_in_ucast_pkts_high
[0x20];
2227 u8 if_in_ucast_pkts_low
[0x20];
2229 u8 if_in_discards_high
[0x20];
2231 u8 if_in_discards_low
[0x20];
2233 u8 if_in_errors_high
[0x20];
2235 u8 if_in_errors_low
[0x20];
2237 u8 if_in_unknown_protos_high
[0x20];
2239 u8 if_in_unknown_protos_low
[0x20];
2241 u8 if_out_octets_high
[0x20];
2243 u8 if_out_octets_low
[0x20];
2245 u8 if_out_ucast_pkts_high
[0x20];
2247 u8 if_out_ucast_pkts_low
[0x20];
2249 u8 if_out_discards_high
[0x20];
2251 u8 if_out_discards_low
[0x20];
2253 u8 if_out_errors_high
[0x20];
2255 u8 if_out_errors_low
[0x20];
2257 u8 if_in_multicast_pkts_high
[0x20];
2259 u8 if_in_multicast_pkts_low
[0x20];
2261 u8 if_in_broadcast_pkts_high
[0x20];
2263 u8 if_in_broadcast_pkts_low
[0x20];
2265 u8 if_out_multicast_pkts_high
[0x20];
2267 u8 if_out_multicast_pkts_low
[0x20];
2269 u8 if_out_broadcast_pkts_high
[0x20];
2271 u8 if_out_broadcast_pkts_low
[0x20];
2273 u8 reserved_at_340
[0x480];
2276 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits
{
2277 u8 a_frames_transmitted_ok_high
[0x20];
2279 u8 a_frames_transmitted_ok_low
[0x20];
2281 u8 a_frames_received_ok_high
[0x20];
2283 u8 a_frames_received_ok_low
[0x20];
2285 u8 a_frame_check_sequence_errors_high
[0x20];
2287 u8 a_frame_check_sequence_errors_low
[0x20];
2289 u8 a_alignment_errors_high
[0x20];
2291 u8 a_alignment_errors_low
[0x20];
2293 u8 a_octets_transmitted_ok_high
[0x20];
2295 u8 a_octets_transmitted_ok_low
[0x20];
2297 u8 a_octets_received_ok_high
[0x20];
2299 u8 a_octets_received_ok_low
[0x20];
2301 u8 a_multicast_frames_xmitted_ok_high
[0x20];
2303 u8 a_multicast_frames_xmitted_ok_low
[0x20];
2305 u8 a_broadcast_frames_xmitted_ok_high
[0x20];
2307 u8 a_broadcast_frames_xmitted_ok_low
[0x20];
2309 u8 a_multicast_frames_received_ok_high
[0x20];
2311 u8 a_multicast_frames_received_ok_low
[0x20];
2313 u8 a_broadcast_frames_received_ok_high
[0x20];
2315 u8 a_broadcast_frames_received_ok_low
[0x20];
2317 u8 a_in_range_length_errors_high
[0x20];
2319 u8 a_in_range_length_errors_low
[0x20];
2321 u8 a_out_of_range_length_field_high
[0x20];
2323 u8 a_out_of_range_length_field_low
[0x20];
2325 u8 a_frame_too_long_errors_high
[0x20];
2327 u8 a_frame_too_long_errors_low
[0x20];
2329 u8 a_symbol_error_during_carrier_high
[0x20];
2331 u8 a_symbol_error_during_carrier_low
[0x20];
2333 u8 a_mac_control_frames_transmitted_high
[0x20];
2335 u8 a_mac_control_frames_transmitted_low
[0x20];
2337 u8 a_mac_control_frames_received_high
[0x20];
2339 u8 a_mac_control_frames_received_low
[0x20];
2341 u8 a_unsupported_opcodes_received_high
[0x20];
2343 u8 a_unsupported_opcodes_received_low
[0x20];
2345 u8 a_pause_mac_ctrl_frames_received_high
[0x20];
2347 u8 a_pause_mac_ctrl_frames_received_low
[0x20];
2349 u8 a_pause_mac_ctrl_frames_transmitted_high
[0x20];
2351 u8 a_pause_mac_ctrl_frames_transmitted_low
[0x20];
2353 u8 reserved_at_4c0
[0x300];
2356 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits
{
2357 u8 life_time_counter_high
[0x20];
2359 u8 life_time_counter_low
[0x20];
2365 u8 l0_to_recovery_eieos
[0x20];
2367 u8 l0_to_recovery_ts
[0x20];
2369 u8 l0_to_recovery_framing
[0x20];
2371 u8 l0_to_recovery_retrain
[0x20];
2373 u8 crc_error_dllp
[0x20];
2375 u8 crc_error_tlp
[0x20];
2377 u8 tx_overflow_buffer_pkt_high
[0x20];
2379 u8 tx_overflow_buffer_pkt_low
[0x20];
2381 u8 outbound_stalled_reads
[0x20];
2383 u8 outbound_stalled_writes
[0x20];
2385 u8 outbound_stalled_reads_events
[0x20];
2387 u8 outbound_stalled_writes_events
[0x20];
2389 u8 reserved_at_200
[0x5c0];
2392 struct mlx5_ifc_cmd_inter_comp_event_bits
{
2393 u8 command_completion_vector
[0x20];
2395 u8 reserved_at_20
[0xc0];
2398 struct mlx5_ifc_stall_vl_event_bits
{
2399 u8 reserved_at_0
[0x18];
2401 u8 reserved_at_19
[0x3];
2404 u8 reserved_at_20
[0xa0];
2407 struct mlx5_ifc_db_bf_congestion_event_bits
{
2408 u8 event_subtype
[0x8];
2409 u8 reserved_at_8
[0x8];
2410 u8 congestion_level
[0x8];
2411 u8 reserved_at_18
[0x8];
2413 u8 reserved_at_20
[0xa0];
2416 struct mlx5_ifc_gpio_event_bits
{
2417 u8 reserved_at_0
[0x60];
2419 u8 gpio_event_hi
[0x20];
2421 u8 gpio_event_lo
[0x20];
2423 u8 reserved_at_a0
[0x40];
2426 struct mlx5_ifc_port_state_change_event_bits
{
2427 u8 reserved_at_0
[0x40];
2430 u8 reserved_at_44
[0x1c];
2432 u8 reserved_at_60
[0x80];
2435 struct mlx5_ifc_dropped_packet_logged_bits
{
2436 u8 reserved_at_0
[0xe0];
2440 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN
= 0x1,
2441 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR
= 0x2,
2444 struct mlx5_ifc_cq_error_bits
{
2445 u8 reserved_at_0
[0x8];
2448 u8 reserved_at_20
[0x20];
2450 u8 reserved_at_40
[0x18];
2453 u8 reserved_at_60
[0x80];
2456 struct mlx5_ifc_rdma_page_fault_event_bits
{
2457 u8 bytes_committed
[0x20];
2461 u8 reserved_at_40
[0x10];
2462 u8 packet_len
[0x10];
2464 u8 rdma_op_len
[0x20];
2468 u8 reserved_at_c0
[0x5];
2475 struct mlx5_ifc_wqe_associated_page_fault_event_bits
{
2476 u8 bytes_committed
[0x20];
2478 u8 reserved_at_20
[0x10];
2481 u8 reserved_at_40
[0x10];
2484 u8 reserved_at_60
[0x60];
2486 u8 reserved_at_c0
[0x5];
2493 struct mlx5_ifc_qp_events_bits
{
2494 u8 reserved_at_0
[0xa0];
2497 u8 reserved_at_a8
[0x18];
2499 u8 reserved_at_c0
[0x8];
2500 u8 qpn_rqn_sqn
[0x18];
2503 struct mlx5_ifc_dct_events_bits
{
2504 u8 reserved_at_0
[0xc0];
2506 u8 reserved_at_c0
[0x8];
2507 u8 dct_number
[0x18];
2510 struct mlx5_ifc_comp_event_bits
{
2511 u8 reserved_at_0
[0xc0];
2513 u8 reserved_at_c0
[0x8];
2518 MLX5_QPC_STATE_RST
= 0x0,
2519 MLX5_QPC_STATE_INIT
= 0x1,
2520 MLX5_QPC_STATE_RTR
= 0x2,
2521 MLX5_QPC_STATE_RTS
= 0x3,
2522 MLX5_QPC_STATE_SQER
= 0x4,
2523 MLX5_QPC_STATE_ERR
= 0x6,
2524 MLX5_QPC_STATE_SQD
= 0x7,
2525 MLX5_QPC_STATE_SUSPENDED
= 0x9,
2529 MLX5_QPC_ST_RC
= 0x0,
2530 MLX5_QPC_ST_UC
= 0x1,
2531 MLX5_QPC_ST_UD
= 0x2,
2532 MLX5_QPC_ST_XRC
= 0x3,
2533 MLX5_QPC_ST_DCI
= 0x5,
2534 MLX5_QPC_ST_QP0
= 0x7,
2535 MLX5_QPC_ST_QP1
= 0x8,
2536 MLX5_QPC_ST_RAW_DATAGRAM
= 0x9,
2537 MLX5_QPC_ST_REG_UMR
= 0xc,
2541 MLX5_QPC_PM_STATE_ARMED
= 0x0,
2542 MLX5_QPC_PM_STATE_REARM
= 0x1,
2543 MLX5_QPC_PM_STATE_RESERVED
= 0x2,
2544 MLX5_QPC_PM_STATE_MIGRATED
= 0x3,
2548 MLX5_QPC_OFFLOAD_TYPE_RNDV
= 0x1,
2552 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS
= 0x0,
2553 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT
= 0x1,
2557 MLX5_QPC_MTU_256_BYTES
= 0x1,
2558 MLX5_QPC_MTU_512_BYTES
= 0x2,
2559 MLX5_QPC_MTU_1K_BYTES
= 0x3,
2560 MLX5_QPC_MTU_2K_BYTES
= 0x4,
2561 MLX5_QPC_MTU_4K_BYTES
= 0x5,
2562 MLX5_QPC_MTU_RAW_ETHERNET_QP
= 0x7,
2566 MLX5_QPC_ATOMIC_MODE_IB_SPEC
= 0x1,
2567 MLX5_QPC_ATOMIC_MODE_ONLY_8B
= 0x2,
2568 MLX5_QPC_ATOMIC_MODE_UP_TO_8B
= 0x3,
2569 MLX5_QPC_ATOMIC_MODE_UP_TO_16B
= 0x4,
2570 MLX5_QPC_ATOMIC_MODE_UP_TO_32B
= 0x5,
2571 MLX5_QPC_ATOMIC_MODE_UP_TO_64B
= 0x6,
2572 MLX5_QPC_ATOMIC_MODE_UP_TO_128B
= 0x7,
2573 MLX5_QPC_ATOMIC_MODE_UP_TO_256B
= 0x8,
2577 MLX5_QPC_CS_REQ_DISABLE
= 0x0,
2578 MLX5_QPC_CS_REQ_UP_TO_32B
= 0x11,
2579 MLX5_QPC_CS_REQ_UP_TO_64B
= 0x22,
2583 MLX5_QPC_CS_RES_DISABLE
= 0x0,
2584 MLX5_QPC_CS_RES_UP_TO_32B
= 0x1,
2585 MLX5_QPC_CS_RES_UP_TO_64B
= 0x2,
2588 struct mlx5_ifc_qpc_bits
{
2590 u8 lag_tx_port_affinity
[0x4];
2592 u8 reserved_at_10
[0x3];
2594 u8 reserved_at_15
[0x1];
2595 u8 req_e2e_credit_mode
[0x2];
2596 u8 offload_type
[0x4];
2597 u8 end_padding_mode
[0x2];
2598 u8 reserved_at_1e
[0x2];
2600 u8 wq_signature
[0x1];
2601 u8 block_lb_mc
[0x1];
2602 u8 atomic_like_write_en
[0x1];
2603 u8 latency_sensitive
[0x1];
2604 u8 reserved_at_24
[0x1];
2605 u8 drain_sigerr
[0x1];
2606 u8 reserved_at_26
[0x2];
2610 u8 log_msg_max
[0x5];
2611 u8 reserved_at_48
[0x1];
2612 u8 log_rq_size
[0x4];
2613 u8 log_rq_stride
[0x3];
2615 u8 log_sq_size
[0x4];
2616 u8 reserved_at_55
[0x6];
2618 u8 ulp_stateless_offload_mode
[0x4];
2620 u8 counter_set_id
[0x8];
2623 u8 reserved_at_80
[0x8];
2624 u8 user_index
[0x18];
2626 u8 reserved_at_a0
[0x3];
2627 u8 log_page_size
[0x5];
2628 u8 remote_qpn
[0x18];
2630 struct mlx5_ifc_ads_bits primary_address_path
;
2632 struct mlx5_ifc_ads_bits secondary_address_path
;
2634 u8 log_ack_req_freq
[0x4];
2635 u8 reserved_at_384
[0x4];
2636 u8 log_sra_max
[0x3];
2637 u8 reserved_at_38b
[0x2];
2638 u8 retry_count
[0x3];
2640 u8 reserved_at_393
[0x1];
2642 u8 cur_rnr_retry
[0x3];
2643 u8 cur_retry_count
[0x3];
2644 u8 reserved_at_39b
[0x5];
2646 u8 reserved_at_3a0
[0x20];
2648 u8 reserved_at_3c0
[0x8];
2649 u8 next_send_psn
[0x18];
2651 u8 reserved_at_3e0
[0x8];
2654 u8 reserved_at_400
[0x8];
2657 u8 reserved_at_420
[0x20];
2659 u8 reserved_at_440
[0x8];
2660 u8 last_acked_psn
[0x18];
2662 u8 reserved_at_460
[0x8];
2665 u8 reserved_at_480
[0x8];
2666 u8 log_rra_max
[0x3];
2667 u8 reserved_at_48b
[0x1];
2668 u8 atomic_mode
[0x4];
2672 u8 reserved_at_493
[0x1];
2673 u8 page_offset
[0x6];
2674 u8 reserved_at_49a
[0x3];
2675 u8 cd_slave_receive
[0x1];
2676 u8 cd_slave_send
[0x1];
2679 u8 reserved_at_4a0
[0x3];
2680 u8 min_rnr_nak
[0x5];
2681 u8 next_rcv_psn
[0x18];
2683 u8 reserved_at_4c0
[0x8];
2686 u8 reserved_at_4e0
[0x8];
2693 u8 reserved_at_560
[0x5];
2695 u8 srqn_rmpn_xrqn
[0x18];
2697 u8 reserved_at_580
[0x8];
2700 u8 hw_sq_wqebb_counter
[0x10];
2701 u8 sw_sq_wqebb_counter
[0x10];
2703 u8 hw_rq_counter
[0x20];
2705 u8 sw_rq_counter
[0x20];
2707 u8 reserved_at_600
[0x20];
2709 u8 reserved_at_620
[0xf];
2714 u8 dc_access_key
[0x40];
2716 u8 reserved_at_680
[0x3];
2717 u8 dbr_umem_valid
[0x1];
2719 u8 reserved_at_684
[0xbc];
2722 struct mlx5_ifc_roce_addr_layout_bits
{
2723 u8 source_l3_address
[16][0x8];
2725 u8 reserved_at_80
[0x3];
2728 u8 source_mac_47_32
[0x10];
2730 u8 source_mac_31_0
[0x20];
2732 u8 reserved_at_c0
[0x14];
2733 u8 roce_l3_type
[0x4];
2734 u8 roce_version
[0x8];
2736 u8 reserved_at_e0
[0x20];
2739 union mlx5_ifc_hca_cap_union_bits
{
2740 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap
;
2741 struct mlx5_ifc_odp_cap_bits odp_cap
;
2742 struct mlx5_ifc_atomic_caps_bits atomic_caps
;
2743 struct mlx5_ifc_roce_cap_bits roce_cap
;
2744 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps
;
2745 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap
;
2746 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap
;
2747 struct mlx5_ifc_e_switch_cap_bits e_switch_cap
;
2748 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap
;
2749 struct mlx5_ifc_qos_cap_bits qos_cap
;
2750 struct mlx5_ifc_debug_cap_bits debug_cap
;
2751 struct mlx5_ifc_fpga_cap_bits fpga_cap
;
2752 struct mlx5_ifc_tls_cap_bits tls_cap
;
2753 struct mlx5_ifc_device_mem_cap_bits device_mem_cap
;
2754 u8 reserved_at_0
[0x8000];
2758 MLX5_FLOW_CONTEXT_ACTION_ALLOW
= 0x1,
2759 MLX5_FLOW_CONTEXT_ACTION_DROP
= 0x2,
2760 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
= 0x4,
2761 MLX5_FLOW_CONTEXT_ACTION_COUNT
= 0x8,
2762 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT
= 0x10,
2763 MLX5_FLOW_CONTEXT_ACTION_DECAP
= 0x20,
2764 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR
= 0x40,
2765 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP
= 0x80,
2766 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH
= 0x100,
2767 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2
= 0x400,
2768 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2
= 0x800,
2772 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT
= 0x0,
2773 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK
= 0x1,
2774 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT
= 0x2,
2777 struct mlx5_ifc_vlan_bits
{
2784 struct mlx5_ifc_flow_context_bits
{
2785 struct mlx5_ifc_vlan_bits push_vlan
;
2789 u8 reserved_at_40
[0x8];
2792 u8 reserved_at_60
[0x10];
2795 u8 extended_destination
[0x1];
2796 u8 reserved_at_81
[0x1];
2797 u8 flow_source
[0x2];
2798 u8 reserved_at_84
[0x4];
2799 u8 destination_list_size
[0x18];
2801 u8 reserved_at_a0
[0x8];
2802 u8 flow_counter_list_size
[0x18];
2804 u8 packet_reformat_id
[0x20];
2806 u8 modify_header_id
[0x20];
2808 struct mlx5_ifc_vlan_bits push_vlan_2
;
2810 u8 reserved_at_120
[0xe0];
2812 struct mlx5_ifc_fte_match_param_bits match_value
;
2814 u8 reserved_at_1200
[0x600];
2816 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination
[0];
2820 MLX5_XRC_SRQC_STATE_GOOD
= 0x0,
2821 MLX5_XRC_SRQC_STATE_ERROR
= 0x1,
2824 struct mlx5_ifc_xrc_srqc_bits
{
2826 u8 log_xrc_srq_size
[0x4];
2827 u8 reserved_at_8
[0x18];
2829 u8 wq_signature
[0x1];
2831 u8 reserved_at_22
[0x1];
2833 u8 basic_cyclic_rcv_wqe
[0x1];
2834 u8 log_rq_stride
[0x3];
2837 u8 page_offset
[0x6];
2838 u8 reserved_at_46
[0x1];
2839 u8 dbr_umem_valid
[0x1];
2842 u8 reserved_at_60
[0x20];
2844 u8 user_index_equal_xrc_srqn
[0x1];
2845 u8 reserved_at_81
[0x1];
2846 u8 log_page_size
[0x6];
2847 u8 user_index
[0x18];
2849 u8 reserved_at_a0
[0x20];
2851 u8 reserved_at_c0
[0x8];
2857 u8 reserved_at_100
[0x40];
2859 u8 db_record_addr_h
[0x20];
2861 u8 db_record_addr_l
[0x1e];
2862 u8 reserved_at_17e
[0x2];
2864 u8 reserved_at_180
[0x80];
2867 struct mlx5_ifc_vnic_diagnostic_statistics_bits
{
2868 u8 counter_error_queues
[0x20];
2870 u8 total_error_queues
[0x20];
2872 u8 send_queue_priority_update_flow
[0x20];
2874 u8 reserved_at_60
[0x20];
2876 u8 nic_receive_steering_discard
[0x40];
2878 u8 receive_discard_vport_down
[0x40];
2880 u8 transmit_discard_vport_down
[0x40];
2882 u8 reserved_at_140
[0xa0];
2884 u8 internal_rq_out_of_buffer
[0x20];
2886 u8 reserved_at_200
[0xe00];
2889 struct mlx5_ifc_traffic_counter_bits
{
2895 struct mlx5_ifc_tisc_bits
{
2896 u8 strict_lag_tx_port_affinity
[0x1];
2898 u8 reserved_at_2
[0x2];
2899 u8 lag_tx_port_affinity
[0x04];
2901 u8 reserved_at_8
[0x4];
2903 u8 reserved_at_10
[0x10];
2905 u8 reserved_at_20
[0x100];
2907 u8 reserved_at_120
[0x8];
2908 u8 transport_domain
[0x18];
2910 u8 reserved_at_140
[0x8];
2911 u8 underlay_qpn
[0x18];
2913 u8 reserved_at_160
[0x8];
2916 u8 reserved_at_180
[0x380];
2920 MLX5_TIRC_DISP_TYPE_DIRECT
= 0x0,
2921 MLX5_TIRC_DISP_TYPE_INDIRECT
= 0x1,
2925 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
= 0x1,
2926 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
= 0x2,
2930 MLX5_RX_HASH_FN_NONE
= 0x0,
2931 MLX5_RX_HASH_FN_INVERTED_XOR8
= 0x1,
2932 MLX5_RX_HASH_FN_TOEPLITZ
= 0x2,
2936 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST
= 0x1,
2937 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST
= 0x2,
2940 struct mlx5_ifc_tirc_bits
{
2941 u8 reserved_at_0
[0x20];
2944 u8 reserved_at_24
[0x1c];
2946 u8 reserved_at_40
[0x40];
2948 u8 reserved_at_80
[0x4];
2949 u8 lro_timeout_period_usecs
[0x10];
2950 u8 lro_enable_mask
[0x4];
2951 u8 lro_max_ip_payload_size
[0x8];
2953 u8 reserved_at_a0
[0x40];
2955 u8 reserved_at_e0
[0x8];
2956 u8 inline_rqn
[0x18];
2958 u8 rx_hash_symmetric
[0x1];
2959 u8 reserved_at_101
[0x1];
2960 u8 tunneled_offload_en
[0x1];
2961 u8 reserved_at_103
[0x5];
2962 u8 indirect_table
[0x18];
2965 u8 reserved_at_124
[0x2];
2966 u8 self_lb_block
[0x2];
2967 u8 transport_domain
[0x18];
2969 u8 rx_hash_toeplitz_key
[10][0x20];
2971 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer
;
2973 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner
;
2975 u8 reserved_at_2c0
[0x4c0];
2979 MLX5_SRQC_STATE_GOOD
= 0x0,
2980 MLX5_SRQC_STATE_ERROR
= 0x1,
2983 struct mlx5_ifc_srqc_bits
{
2985 u8 log_srq_size
[0x4];
2986 u8 reserved_at_8
[0x18];
2988 u8 wq_signature
[0x1];
2990 u8 reserved_at_22
[0x1];
2992 u8 reserved_at_24
[0x1];
2993 u8 log_rq_stride
[0x3];
2996 u8 page_offset
[0x6];
2997 u8 reserved_at_46
[0x2];
3000 u8 reserved_at_60
[0x20];
3002 u8 reserved_at_80
[0x2];
3003 u8 log_page_size
[0x6];
3004 u8 reserved_at_88
[0x18];
3006 u8 reserved_at_a0
[0x20];
3008 u8 reserved_at_c0
[0x8];
3014 u8 reserved_at_100
[0x40];
3018 u8 reserved_at_180
[0x80];
3022 MLX5_SQC_STATE_RST
= 0x0,
3023 MLX5_SQC_STATE_RDY
= 0x1,
3024 MLX5_SQC_STATE_ERR
= 0x3,
3027 struct mlx5_ifc_sqc_bits
{
3031 u8 flush_in_error_en
[0x1];
3032 u8 allow_multi_pkt_send_wqe
[0x1];
3033 u8 min_wqe_inline_mode
[0x3];
3038 u8 reserved_at_f
[0x11];
3040 u8 reserved_at_20
[0x8];
3041 u8 user_index
[0x18];
3043 u8 reserved_at_40
[0x8];
3046 u8 reserved_at_60
[0x8];
3047 u8 hairpin_peer_rq
[0x18];
3049 u8 reserved_at_80
[0x10];
3050 u8 hairpin_peer_vhca
[0x10];
3052 u8 reserved_at_a0
[0x50];
3054 u8 packet_pacing_rate_limit_index
[0x10];
3055 u8 tis_lst_sz
[0x10];
3056 u8 reserved_at_110
[0x10];
3058 u8 reserved_at_120
[0x40];
3060 u8 reserved_at_160
[0x8];
3063 struct mlx5_ifc_wq_bits wq
;
3067 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR
= 0x0,
3068 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT
= 0x1,
3069 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC
= 0x2,
3070 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC
= 0x3,
3074 ELEMENT_TYPE_CAP_MASK_TASR
= 1 << 0,
3075 ELEMENT_TYPE_CAP_MASK_VPORT
= 1 << 1,
3076 ELEMENT_TYPE_CAP_MASK_VPORT_TC
= 1 << 2,
3077 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC
= 1 << 3,
3080 struct mlx5_ifc_scheduling_context_bits
{
3081 u8 element_type
[0x8];
3082 u8 reserved_at_8
[0x18];
3084 u8 element_attributes
[0x20];
3086 u8 parent_element_id
[0x20];
3088 u8 reserved_at_60
[0x40];
3092 u8 max_average_bw
[0x20];
3094 u8 reserved_at_e0
[0x120];
3097 struct mlx5_ifc_rqtc_bits
{
3098 u8 reserved_at_0
[0xa0];
3100 u8 reserved_at_a0
[0x10];
3101 u8 rqt_max_size
[0x10];
3103 u8 reserved_at_c0
[0x10];
3104 u8 rqt_actual_size
[0x10];
3106 u8 reserved_at_e0
[0x6a0];
3108 struct mlx5_ifc_rq_num_bits rq_num
[0];
3112 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
= 0x0,
3113 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP
= 0x1,
3117 MLX5_RQC_STATE_RST
= 0x0,
3118 MLX5_RQC_STATE_RDY
= 0x1,
3119 MLX5_RQC_STATE_ERR
= 0x3,
3122 struct mlx5_ifc_rqc_bits
{
3124 u8 delay_drop_en
[0x1];
3125 u8 scatter_fcs
[0x1];
3127 u8 mem_rq_type
[0x4];
3129 u8 reserved_at_c
[0x1];
3130 u8 flush_in_error_en
[0x1];
3132 u8 reserved_at_f
[0x11];
3134 u8 reserved_at_20
[0x8];
3135 u8 user_index
[0x18];
3137 u8 reserved_at_40
[0x8];
3140 u8 counter_set_id
[0x8];
3141 u8 reserved_at_68
[0x18];
3143 u8 reserved_at_80
[0x8];
3146 u8 reserved_at_a0
[0x8];
3147 u8 hairpin_peer_sq
[0x18];
3149 u8 reserved_at_c0
[0x10];
3150 u8 hairpin_peer_vhca
[0x10];
3152 u8 reserved_at_e0
[0xa0];
3154 struct mlx5_ifc_wq_bits wq
;
3158 MLX5_RMPC_STATE_RDY
= 0x1,
3159 MLX5_RMPC_STATE_ERR
= 0x3,
3162 struct mlx5_ifc_rmpc_bits
{
3163 u8 reserved_at_0
[0x8];
3165 u8 reserved_at_c
[0x14];
3167 u8 basic_cyclic_rcv_wqe
[0x1];
3168 u8 reserved_at_21
[0x1f];
3170 u8 reserved_at_40
[0x140];
3172 struct mlx5_ifc_wq_bits wq
;
3175 struct mlx5_ifc_nic_vport_context_bits
{
3176 u8 reserved_at_0
[0x5];
3177 u8 min_wqe_inline_mode
[0x3];
3178 u8 reserved_at_8
[0x15];
3179 u8 disable_mc_local_lb
[0x1];
3180 u8 disable_uc_local_lb
[0x1];
3183 u8 arm_change_event
[0x1];
3184 u8 reserved_at_21
[0x1a];
3185 u8 event_on_mtu
[0x1];
3186 u8 event_on_promisc_change
[0x1];
3187 u8 event_on_vlan_change
[0x1];
3188 u8 event_on_mc_address_change
[0x1];
3189 u8 event_on_uc_address_change
[0x1];
3191 u8 reserved_at_40
[0xc];
3193 u8 affiliation_criteria
[0x4];
3194 u8 affiliated_vhca_id
[0x10];
3196 u8 reserved_at_60
[0xd0];
3200 u8 system_image_guid
[0x40];
3204 u8 reserved_at_200
[0x140];
3205 u8 qkey_violation_counter
[0x10];
3206 u8 reserved_at_350
[0x430];
3210 u8 promisc_all
[0x1];
3211 u8 reserved_at_783
[0x2];
3212 u8 allowed_list_type
[0x3];
3213 u8 reserved_at_788
[0xc];
3214 u8 allowed_list_size
[0xc];
3216 struct mlx5_ifc_mac_address_layout_bits permanent_address
;
3218 u8 reserved_at_7e0
[0x20];
3220 u8 current_uc_mac_address
[0][0x40];
3224 MLX5_MKC_ACCESS_MODE_PA
= 0x0,
3225 MLX5_MKC_ACCESS_MODE_MTT
= 0x1,
3226 MLX5_MKC_ACCESS_MODE_KLMS
= 0x2,
3227 MLX5_MKC_ACCESS_MODE_KSM
= 0x3,
3228 MLX5_MKC_ACCESS_MODE_SW_ICM
= 0x4,
3229 MLX5_MKC_ACCESS_MODE_MEMIC
= 0x5,
3232 struct mlx5_ifc_mkc_bits
{
3233 u8 reserved_at_0
[0x1];
3235 u8 reserved_at_2
[0x1];
3236 u8 access_mode_4_2
[0x3];
3237 u8 reserved_at_6
[0x7];
3238 u8 relaxed_ordering_write
[0x1];
3239 u8 reserved_at_e
[0x1];
3240 u8 small_fence_on_rdma_read_response
[0x1];
3247 u8 access_mode_1_0
[0x2];
3248 u8 reserved_at_18
[0x8];
3253 u8 reserved_at_40
[0x20];
3258 u8 reserved_at_63
[0x2];
3259 u8 expected_sigerr_count
[0x1];
3260 u8 reserved_at_66
[0x1];
3264 u8 start_addr
[0x40];
3268 u8 bsf_octword_size
[0x20];
3270 u8 reserved_at_120
[0x80];
3272 u8 translations_octword_size
[0x20];
3274 u8 reserved_at_1c0
[0x1b];
3275 u8 log_page_size
[0x5];
3277 u8 reserved_at_1e0
[0x20];
3280 struct mlx5_ifc_pkey_bits
{
3281 u8 reserved_at_0
[0x10];
3285 struct mlx5_ifc_array128_auto_bits
{
3286 u8 array128_auto
[16][0x8];
3289 struct mlx5_ifc_hca_vport_context_bits
{
3290 u8 field_select
[0x20];
3292 u8 reserved_at_20
[0xe0];
3294 u8 sm_virt_aware
[0x1];
3297 u8 grh_required
[0x1];
3298 u8 reserved_at_104
[0xc];
3299 u8 port_physical_state
[0x4];
3300 u8 vport_state_policy
[0x4];
3302 u8 vport_state
[0x4];
3304 u8 reserved_at_120
[0x20];
3306 u8 system_image_guid
[0x40];
3314 u8 cap_mask1_field_select
[0x20];
3318 u8 cap_mask2_field_select
[0x20];
3320 u8 reserved_at_280
[0x80];
3323 u8 reserved_at_310
[0x4];
3324 u8 init_type_reply
[0x4];
3326 u8 subnet_timeout
[0x5];
3330 u8 reserved_at_334
[0xc];
3332 u8 qkey_violation_counter
[0x10];
3333 u8 pkey_violation_counter
[0x10];
3335 u8 reserved_at_360
[0xca0];
3338 struct mlx5_ifc_esw_vport_context_bits
{
3339 u8 fdb_to_vport_reg_c
[0x1];
3340 u8 reserved_at_1
[0x2];
3341 u8 vport_svlan_strip
[0x1];
3342 u8 vport_cvlan_strip
[0x1];
3343 u8 vport_svlan_insert
[0x1];
3344 u8 vport_cvlan_insert
[0x2];
3345 u8 fdb_to_vport_reg_c_id
[0x8];
3346 u8 reserved_at_10
[0x10];
3348 u8 reserved_at_20
[0x20];
3357 u8 reserved_at_60
[0x720];
3359 u8 sw_steering_vport_icm_address_rx
[0x40];
3361 u8 sw_steering_vport_icm_address_tx
[0x40];
3365 MLX5_EQC_STATUS_OK
= 0x0,
3366 MLX5_EQC_STATUS_EQ_WRITE_FAILURE
= 0xa,
3370 MLX5_EQC_ST_ARMED
= 0x9,
3371 MLX5_EQC_ST_FIRED
= 0xa,
3374 struct mlx5_ifc_eqc_bits
{
3376 u8 reserved_at_4
[0x9];
3379 u8 reserved_at_f
[0x5];
3381 u8 reserved_at_18
[0x8];
3383 u8 reserved_at_20
[0x20];
3385 u8 reserved_at_40
[0x14];
3386 u8 page_offset
[0x6];
3387 u8 reserved_at_5a
[0x6];
3389 u8 reserved_at_60
[0x3];
3390 u8 log_eq_size
[0x5];
3393 u8 reserved_at_80
[0x20];
3395 u8 reserved_at_a0
[0x18];
3398 u8 reserved_at_c0
[0x3];
3399 u8 log_page_size
[0x5];
3400 u8 reserved_at_c8
[0x18];
3402 u8 reserved_at_e0
[0x60];
3404 u8 reserved_at_140
[0x8];
3405 u8 consumer_counter
[0x18];
3407 u8 reserved_at_160
[0x8];
3408 u8 producer_counter
[0x18];
3410 u8 reserved_at_180
[0x80];
3414 MLX5_DCTC_STATE_ACTIVE
= 0x0,
3415 MLX5_DCTC_STATE_DRAINING
= 0x1,
3416 MLX5_DCTC_STATE_DRAINED
= 0x2,
3420 MLX5_DCTC_CS_RES_DISABLE
= 0x0,
3421 MLX5_DCTC_CS_RES_NA
= 0x1,
3422 MLX5_DCTC_CS_RES_UP_TO_64B
= 0x2,
3426 MLX5_DCTC_MTU_256_BYTES
= 0x1,
3427 MLX5_DCTC_MTU_512_BYTES
= 0x2,
3428 MLX5_DCTC_MTU_1K_BYTES
= 0x3,
3429 MLX5_DCTC_MTU_2K_BYTES
= 0x4,
3430 MLX5_DCTC_MTU_4K_BYTES
= 0x5,
3433 struct mlx5_ifc_dctc_bits
{
3434 u8 reserved_at_0
[0x4];
3436 u8 reserved_at_8
[0x18];
3438 u8 reserved_at_20
[0x8];
3439 u8 user_index
[0x18];
3441 u8 reserved_at_40
[0x8];
3444 u8 counter_set_id
[0x8];
3445 u8 atomic_mode
[0x4];
3449 u8 atomic_like_write_en
[0x1];
3450 u8 latency_sensitive
[0x1];
3453 u8 reserved_at_73
[0xd];
3455 u8 reserved_at_80
[0x8];
3457 u8 reserved_at_90
[0x3];
3458 u8 min_rnr_nak
[0x5];
3459 u8 reserved_at_98
[0x8];
3461 u8 reserved_at_a0
[0x8];
3464 u8 reserved_at_c0
[0x8];
3468 u8 reserved_at_e8
[0x4];
3469 u8 flow_label
[0x14];
3471 u8 dc_access_key
[0x40];
3473 u8 reserved_at_140
[0x5];
3476 u8 pkey_index
[0x10];
3478 u8 reserved_at_160
[0x8];
3479 u8 my_addr_index
[0x8];
3480 u8 reserved_at_170
[0x8];
3483 u8 dc_access_key_violation_count
[0x20];
3485 u8 reserved_at_1a0
[0x14];
3491 u8 reserved_at_1c0
[0x40];
3495 MLX5_CQC_STATUS_OK
= 0x0,
3496 MLX5_CQC_STATUS_CQ_OVERFLOW
= 0x9,
3497 MLX5_CQC_STATUS_CQ_WRITE_FAIL
= 0xa,
3501 MLX5_CQC_CQE_SZ_64_BYTES
= 0x0,
3502 MLX5_CQC_CQE_SZ_128_BYTES
= 0x1,
3506 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED
= 0x6,
3507 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED
= 0x9,
3508 MLX5_CQC_ST_FIRED
= 0xa,
3512 MLX5_CQ_PERIOD_MODE_START_FROM_EQE
= 0x0,
3513 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
= 0x1,
3514 MLX5_CQ_PERIOD_NUM_MODES
3517 struct mlx5_ifc_cqc_bits
{
3519 u8 reserved_at_4
[0x2];
3520 u8 dbr_umem_valid
[0x1];
3521 u8 reserved_at_7
[0x1];
3524 u8 reserved_at_c
[0x1];
3525 u8 scqe_break_moderation_en
[0x1];
3527 u8 cq_period_mode
[0x2];
3528 u8 cqe_comp_en
[0x1];
3529 u8 mini_cqe_res_format
[0x2];
3531 u8 reserved_at_18
[0x8];
3533 u8 reserved_at_20
[0x20];
3535 u8 reserved_at_40
[0x14];
3536 u8 page_offset
[0x6];
3537 u8 reserved_at_5a
[0x6];
3539 u8 reserved_at_60
[0x3];
3540 u8 log_cq_size
[0x5];
3543 u8 reserved_at_80
[0x4];
3545 u8 cq_max_count
[0x10];
3547 u8 reserved_at_a0
[0x18];
3550 u8 reserved_at_c0
[0x3];
3551 u8 log_page_size
[0x5];
3552 u8 reserved_at_c8
[0x18];
3554 u8 reserved_at_e0
[0x20];
3556 u8 reserved_at_100
[0x8];
3557 u8 last_notified_index
[0x18];
3559 u8 reserved_at_120
[0x8];
3560 u8 last_solicit_index
[0x18];
3562 u8 reserved_at_140
[0x8];
3563 u8 consumer_counter
[0x18];
3565 u8 reserved_at_160
[0x8];
3566 u8 producer_counter
[0x18];
3568 u8 reserved_at_180
[0x40];
3573 union mlx5_ifc_cong_control_roce_ecn_auto_bits
{
3574 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp
;
3575 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp
;
3576 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np
;
3577 u8 reserved_at_0
[0x800];
3580 struct mlx5_ifc_query_adapter_param_block_bits
{
3581 u8 reserved_at_0
[0xc0];
3583 u8 reserved_at_c0
[0x8];
3584 u8 ieee_vendor_id
[0x18];
3586 u8 reserved_at_e0
[0x10];
3587 u8 vsd_vendor_id
[0x10];
3591 u8 vsd_contd_psid
[16][0x8];
3595 MLX5_XRQC_STATE_GOOD
= 0x0,
3596 MLX5_XRQC_STATE_ERROR
= 0x1,
3600 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY
= 0x0,
3601 MLX5_XRQC_TOPOLOGY_TAG_MATCHING
= 0x1,
3605 MLX5_XRQC_OFFLOAD_RNDV
= 0x1,
3608 struct mlx5_ifc_tag_matching_topology_context_bits
{
3609 u8 log_matching_list_sz
[0x4];
3610 u8 reserved_at_4
[0xc];
3611 u8 append_next_index
[0x10];
3613 u8 sw_phase_cnt
[0x10];
3614 u8 hw_phase_cnt
[0x10];
3616 u8 reserved_at_40
[0x40];
3619 struct mlx5_ifc_xrqc_bits
{
3622 u8 reserved_at_5
[0xf];
3624 u8 reserved_at_18
[0x4];
3627 u8 reserved_at_20
[0x8];
3628 u8 user_index
[0x18];
3630 u8 reserved_at_40
[0x8];
3633 u8 reserved_at_60
[0xa0];
3635 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context
;
3637 u8 reserved_at_180
[0x280];
3639 struct mlx5_ifc_wq_bits wq
;
3642 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits
{
3643 struct mlx5_ifc_modify_field_select_bits modify_field_select
;
3644 struct mlx5_ifc_resize_field_select_bits resize_field_select
;
3645 u8 reserved_at_0
[0x20];
3648 union mlx5_ifc_field_select_802_1_r_roce_auto_bits
{
3649 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp
;
3650 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp
;
3651 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np
;
3652 u8 reserved_at_0
[0x20];
3655 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits
{
3656 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
3657 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
3658 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
3659 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
3660 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
3661 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
3662 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout
;
3663 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout
;
3664 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
3665 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
3666 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs
;
3667 u8 reserved_at_0
[0x7c0];
3670 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits
{
3671 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout
;
3672 u8 reserved_at_0
[0x7c0];
3675 union mlx5_ifc_event_auto_bits
{
3676 struct mlx5_ifc_comp_event_bits comp_event
;
3677 struct mlx5_ifc_dct_events_bits dct_events
;
3678 struct mlx5_ifc_qp_events_bits qp_events
;
3679 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event
;
3680 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event
;
3681 struct mlx5_ifc_cq_error_bits cq_error
;
3682 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged
;
3683 struct mlx5_ifc_port_state_change_event_bits port_state_change_event
;
3684 struct mlx5_ifc_gpio_event_bits gpio_event
;
3685 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event
;
3686 struct mlx5_ifc_stall_vl_event_bits stall_vl_event
;
3687 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event
;
3688 u8 reserved_at_0
[0xe0];
3691 struct mlx5_ifc_health_buffer_bits
{
3692 u8 reserved_at_0
[0x100];
3694 u8 assert_existptr
[0x20];
3696 u8 assert_callra
[0x20];
3698 u8 reserved_at_140
[0x40];
3700 u8 fw_version
[0x20];
3704 u8 reserved_at_1c0
[0x20];
3706 u8 irisc_index
[0x8];
3711 struct mlx5_ifc_register_loopback_control_bits
{
3713 u8 reserved_at_1
[0x7];
3715 u8 reserved_at_10
[0x10];
3717 u8 reserved_at_20
[0x60];
3720 struct mlx5_ifc_vport_tc_element_bits
{
3721 u8 traffic_class
[0x4];
3722 u8 reserved_at_4
[0xc];
3723 u8 vport_number
[0x10];
3726 struct mlx5_ifc_vport_element_bits
{
3727 u8 reserved_at_0
[0x10];
3728 u8 vport_number
[0x10];
3732 TSAR_ELEMENT_TSAR_TYPE_DWRR
= 0x0,
3733 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN
= 0x1,
3734 TSAR_ELEMENT_TSAR_TYPE_ETS
= 0x2,
3737 struct mlx5_ifc_tsar_element_bits
{
3738 u8 reserved_at_0
[0x8];
3740 u8 reserved_at_10
[0x10];
3744 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS
= 0x0,
3745 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL
= 0x1,
3748 struct mlx5_ifc_teardown_hca_out_bits
{
3750 u8 reserved_at_8
[0x18];
3754 u8 reserved_at_40
[0x3f];
3760 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE
= 0x0,
3761 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE
= 0x1,
3762 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN
= 0x2,
3765 struct mlx5_ifc_teardown_hca_in_bits
{
3767 u8 reserved_at_10
[0x10];
3769 u8 reserved_at_20
[0x10];
3772 u8 reserved_at_40
[0x10];
3775 u8 reserved_at_60
[0x20];
3778 struct mlx5_ifc_sqerr2rts_qp_out_bits
{
3780 u8 reserved_at_8
[0x18];
3784 u8 reserved_at_40
[0x40];
3787 struct mlx5_ifc_sqerr2rts_qp_in_bits
{
3791 u8 reserved_at_20
[0x10];
3794 u8 reserved_at_40
[0x8];
3797 u8 reserved_at_60
[0x20];
3799 u8 opt_param_mask
[0x20];
3801 u8 reserved_at_a0
[0x20];
3803 struct mlx5_ifc_qpc_bits qpc
;
3805 u8 reserved_at_800
[0x80];
3808 struct mlx5_ifc_sqd2rts_qp_out_bits
{
3810 u8 reserved_at_8
[0x18];
3814 u8 reserved_at_40
[0x40];
3817 struct mlx5_ifc_sqd2rts_qp_in_bits
{
3821 u8 reserved_at_20
[0x10];
3824 u8 reserved_at_40
[0x8];
3827 u8 reserved_at_60
[0x20];
3829 u8 opt_param_mask
[0x20];
3831 u8 reserved_at_a0
[0x20];
3833 struct mlx5_ifc_qpc_bits qpc
;
3835 u8 reserved_at_800
[0x80];
3838 struct mlx5_ifc_set_roce_address_out_bits
{
3840 u8 reserved_at_8
[0x18];
3844 u8 reserved_at_40
[0x40];
3847 struct mlx5_ifc_set_roce_address_in_bits
{
3849 u8 reserved_at_10
[0x10];
3851 u8 reserved_at_20
[0x10];
3854 u8 roce_address_index
[0x10];
3855 u8 reserved_at_50
[0xc];
3856 u8 vhca_port_num
[0x4];
3858 u8 reserved_at_60
[0x20];
3860 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
3863 struct mlx5_ifc_set_mad_demux_out_bits
{
3865 u8 reserved_at_8
[0x18];
3869 u8 reserved_at_40
[0x40];
3873 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL
= 0x0,
3874 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE
= 0x2,
3877 struct mlx5_ifc_set_mad_demux_in_bits
{
3879 u8 reserved_at_10
[0x10];
3881 u8 reserved_at_20
[0x10];
3884 u8 reserved_at_40
[0x20];
3886 u8 reserved_at_60
[0x6];
3888 u8 reserved_at_68
[0x18];
3891 struct mlx5_ifc_set_l2_table_entry_out_bits
{
3893 u8 reserved_at_8
[0x18];
3897 u8 reserved_at_40
[0x40];
3900 struct mlx5_ifc_set_l2_table_entry_in_bits
{
3902 u8 reserved_at_10
[0x10];
3904 u8 reserved_at_20
[0x10];
3907 u8 reserved_at_40
[0x60];
3909 u8 reserved_at_a0
[0x8];
3910 u8 table_index
[0x18];
3912 u8 reserved_at_c0
[0x20];
3914 u8 reserved_at_e0
[0x13];
3918 struct mlx5_ifc_mac_address_layout_bits mac_address
;
3920 u8 reserved_at_140
[0xc0];
3923 struct mlx5_ifc_set_issi_out_bits
{
3925 u8 reserved_at_8
[0x18];
3929 u8 reserved_at_40
[0x40];
3932 struct mlx5_ifc_set_issi_in_bits
{
3934 u8 reserved_at_10
[0x10];
3936 u8 reserved_at_20
[0x10];
3939 u8 reserved_at_40
[0x10];
3940 u8 current_issi
[0x10];
3942 u8 reserved_at_60
[0x20];
3945 struct mlx5_ifc_set_hca_cap_out_bits
{
3947 u8 reserved_at_8
[0x18];
3951 u8 reserved_at_40
[0x40];
3954 struct mlx5_ifc_set_hca_cap_in_bits
{
3956 u8 reserved_at_10
[0x10];
3958 u8 reserved_at_20
[0x10];
3961 u8 reserved_at_40
[0x40];
3963 union mlx5_ifc_hca_cap_union_bits capability
;
3967 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION
= 0x0,
3968 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG
= 0x1,
3969 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST
= 0x2,
3970 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS
= 0x3
3973 struct mlx5_ifc_set_fte_out_bits
{
3975 u8 reserved_at_8
[0x18];
3979 u8 reserved_at_40
[0x40];
3982 struct mlx5_ifc_set_fte_in_bits
{
3984 u8 reserved_at_10
[0x10];
3986 u8 reserved_at_20
[0x10];
3989 u8 other_vport
[0x1];
3990 u8 reserved_at_41
[0xf];
3991 u8 vport_number
[0x10];
3993 u8 reserved_at_60
[0x20];
3996 u8 reserved_at_88
[0x18];
3998 u8 reserved_at_a0
[0x8];
4001 u8 reserved_at_c0
[0x18];
4002 u8 modify_enable_mask
[0x8];
4004 u8 reserved_at_e0
[0x20];
4006 u8 flow_index
[0x20];
4008 u8 reserved_at_120
[0xe0];
4010 struct mlx5_ifc_flow_context_bits flow_context
;
4013 struct mlx5_ifc_rts2rts_qp_out_bits
{
4015 u8 reserved_at_8
[0x18];
4019 u8 reserved_at_40
[0x40];
4022 struct mlx5_ifc_rts2rts_qp_in_bits
{
4026 u8 reserved_at_20
[0x10];
4029 u8 reserved_at_40
[0x8];
4032 u8 reserved_at_60
[0x20];
4034 u8 opt_param_mask
[0x20];
4036 u8 reserved_at_a0
[0x20];
4038 struct mlx5_ifc_qpc_bits qpc
;
4040 u8 reserved_at_800
[0x80];
4043 struct mlx5_ifc_rtr2rts_qp_out_bits
{
4045 u8 reserved_at_8
[0x18];
4049 u8 reserved_at_40
[0x40];
4052 struct mlx5_ifc_rtr2rts_qp_in_bits
{
4056 u8 reserved_at_20
[0x10];
4059 u8 reserved_at_40
[0x8];
4062 u8 reserved_at_60
[0x20];
4064 u8 opt_param_mask
[0x20];
4066 u8 reserved_at_a0
[0x20];
4068 struct mlx5_ifc_qpc_bits qpc
;
4070 u8 reserved_at_800
[0x80];
4073 struct mlx5_ifc_rst2init_qp_out_bits
{
4075 u8 reserved_at_8
[0x18];
4079 u8 reserved_at_40
[0x40];
4082 struct mlx5_ifc_rst2init_qp_in_bits
{
4086 u8 reserved_at_20
[0x10];
4089 u8 reserved_at_40
[0x8];
4092 u8 reserved_at_60
[0x20];
4094 u8 opt_param_mask
[0x20];
4096 u8 reserved_at_a0
[0x20];
4098 struct mlx5_ifc_qpc_bits qpc
;
4100 u8 reserved_at_800
[0x80];
4103 struct mlx5_ifc_query_xrq_out_bits
{
4105 u8 reserved_at_8
[0x18];
4109 u8 reserved_at_40
[0x40];
4111 struct mlx5_ifc_xrqc_bits xrq_context
;
4114 struct mlx5_ifc_query_xrq_in_bits
{
4116 u8 reserved_at_10
[0x10];
4118 u8 reserved_at_20
[0x10];
4121 u8 reserved_at_40
[0x8];
4124 u8 reserved_at_60
[0x20];
4127 struct mlx5_ifc_query_xrc_srq_out_bits
{
4129 u8 reserved_at_8
[0x18];
4133 u8 reserved_at_40
[0x40];
4135 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
4137 u8 reserved_at_280
[0x600];
4142 struct mlx5_ifc_query_xrc_srq_in_bits
{
4144 u8 reserved_at_10
[0x10];
4146 u8 reserved_at_20
[0x10];
4149 u8 reserved_at_40
[0x8];
4152 u8 reserved_at_60
[0x20];
4156 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN
= 0x0,
4157 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP
= 0x1,
4160 struct mlx5_ifc_query_vport_state_out_bits
{
4162 u8 reserved_at_8
[0x18];
4166 u8 reserved_at_40
[0x20];
4168 u8 reserved_at_60
[0x18];
4169 u8 admin_state
[0x4];
4174 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT
= 0x0,
4175 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT
= 0x1,
4178 struct mlx5_ifc_arm_monitor_counter_in_bits
{
4182 u8 reserved_at_20
[0x10];
4185 u8 reserved_at_40
[0x20];
4187 u8 reserved_at_60
[0x20];
4190 struct mlx5_ifc_arm_monitor_counter_out_bits
{
4192 u8 reserved_at_8
[0x18];
4196 u8 reserved_at_40
[0x40];
4200 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT
= 0x0,
4201 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER
= 0x1,
4204 enum mlx5_monitor_counter_ppcnt
{
4205 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS
= 0x0,
4206 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD
= 0x1,
4207 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS
= 0x2,
4208 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS
= 0x3,
4209 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS
= 0x4,
4210 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS
= 0x5,
4214 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER
= 0x4,
4217 struct mlx5_ifc_monitor_counter_output_bits
{
4218 u8 reserved_at_0
[0x4];
4220 u8 reserved_at_8
[0x8];
4223 u8 counter_group_id
[0x20];
4226 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4227 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4228 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4229 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4231 struct mlx5_ifc_set_monitor_counter_in_bits
{
4235 u8 reserved_at_20
[0x10];
4238 u8 reserved_at_40
[0x10];
4239 u8 num_of_counters
[0x10];
4241 u8 reserved_at_60
[0x20];
4243 struct mlx5_ifc_monitor_counter_output_bits monitor_counter
[MLX5_CMD_SET_MONITOR_NUM_COUNTER
];
4246 struct mlx5_ifc_set_monitor_counter_out_bits
{
4248 u8 reserved_at_8
[0x18];
4252 u8 reserved_at_40
[0x40];
4255 struct mlx5_ifc_query_vport_state_in_bits
{
4257 u8 reserved_at_10
[0x10];
4259 u8 reserved_at_20
[0x10];
4262 u8 other_vport
[0x1];
4263 u8 reserved_at_41
[0xf];
4264 u8 vport_number
[0x10];
4266 u8 reserved_at_60
[0x20];
4269 struct mlx5_ifc_query_vnic_env_out_bits
{
4271 u8 reserved_at_8
[0x18];
4275 u8 reserved_at_40
[0x40];
4277 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env
;
4281 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS
= 0x0,
4284 struct mlx5_ifc_query_vnic_env_in_bits
{
4286 u8 reserved_at_10
[0x10];
4288 u8 reserved_at_20
[0x10];
4291 u8 other_vport
[0x1];
4292 u8 reserved_at_41
[0xf];
4293 u8 vport_number
[0x10];
4295 u8 reserved_at_60
[0x20];
4298 struct mlx5_ifc_query_vport_counter_out_bits
{
4300 u8 reserved_at_8
[0x18];
4304 u8 reserved_at_40
[0x40];
4306 struct mlx5_ifc_traffic_counter_bits received_errors
;
4308 struct mlx5_ifc_traffic_counter_bits transmit_errors
;
4310 struct mlx5_ifc_traffic_counter_bits received_ib_unicast
;
4312 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast
;
4314 struct mlx5_ifc_traffic_counter_bits received_ib_multicast
;
4316 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast
;
4318 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast
;
4320 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast
;
4322 struct mlx5_ifc_traffic_counter_bits received_eth_unicast
;
4324 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast
;
4326 struct mlx5_ifc_traffic_counter_bits received_eth_multicast
;
4328 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast
;
4330 u8 reserved_at_680
[0xa00];
4334 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS
= 0x0,
4337 struct mlx5_ifc_query_vport_counter_in_bits
{
4339 u8 reserved_at_10
[0x10];
4341 u8 reserved_at_20
[0x10];
4344 u8 other_vport
[0x1];
4345 u8 reserved_at_41
[0xb];
4347 u8 vport_number
[0x10];
4349 u8 reserved_at_60
[0x60];
4352 u8 reserved_at_c1
[0x1f];
4354 u8 reserved_at_e0
[0x20];
4357 struct mlx5_ifc_query_tis_out_bits
{
4359 u8 reserved_at_8
[0x18];
4363 u8 reserved_at_40
[0x40];
4365 struct mlx5_ifc_tisc_bits tis_context
;
4368 struct mlx5_ifc_query_tis_in_bits
{
4370 u8 reserved_at_10
[0x10];
4372 u8 reserved_at_20
[0x10];
4375 u8 reserved_at_40
[0x8];
4378 u8 reserved_at_60
[0x20];
4381 struct mlx5_ifc_query_tir_out_bits
{
4383 u8 reserved_at_8
[0x18];
4387 u8 reserved_at_40
[0xc0];
4389 struct mlx5_ifc_tirc_bits tir_context
;
4392 struct mlx5_ifc_query_tir_in_bits
{
4394 u8 reserved_at_10
[0x10];
4396 u8 reserved_at_20
[0x10];
4399 u8 reserved_at_40
[0x8];
4402 u8 reserved_at_60
[0x20];
4405 struct mlx5_ifc_query_srq_out_bits
{
4407 u8 reserved_at_8
[0x18];
4411 u8 reserved_at_40
[0x40];
4413 struct mlx5_ifc_srqc_bits srq_context_entry
;
4415 u8 reserved_at_280
[0x600];
4420 struct mlx5_ifc_query_srq_in_bits
{
4422 u8 reserved_at_10
[0x10];
4424 u8 reserved_at_20
[0x10];
4427 u8 reserved_at_40
[0x8];
4430 u8 reserved_at_60
[0x20];
4433 struct mlx5_ifc_query_sq_out_bits
{
4435 u8 reserved_at_8
[0x18];
4439 u8 reserved_at_40
[0xc0];
4441 struct mlx5_ifc_sqc_bits sq_context
;
4444 struct mlx5_ifc_query_sq_in_bits
{
4446 u8 reserved_at_10
[0x10];
4448 u8 reserved_at_20
[0x10];
4451 u8 reserved_at_40
[0x8];
4454 u8 reserved_at_60
[0x20];
4457 struct mlx5_ifc_query_special_contexts_out_bits
{
4459 u8 reserved_at_8
[0x18];
4463 u8 dump_fill_mkey
[0x20];
4469 u8 reserved_at_a0
[0x60];
4472 struct mlx5_ifc_query_special_contexts_in_bits
{
4474 u8 reserved_at_10
[0x10];
4476 u8 reserved_at_20
[0x10];
4479 u8 reserved_at_40
[0x40];
4482 struct mlx5_ifc_query_scheduling_element_out_bits
{
4484 u8 reserved_at_10
[0x10];
4486 u8 reserved_at_20
[0x10];
4489 u8 reserved_at_40
[0xc0];
4491 struct mlx5_ifc_scheduling_context_bits scheduling_context
;
4493 u8 reserved_at_300
[0x100];
4497 SCHEDULING_HIERARCHY_E_SWITCH
= 0x2,
4500 struct mlx5_ifc_query_scheduling_element_in_bits
{
4502 u8 reserved_at_10
[0x10];
4504 u8 reserved_at_20
[0x10];
4507 u8 scheduling_hierarchy
[0x8];
4508 u8 reserved_at_48
[0x18];
4510 u8 scheduling_element_id
[0x20];
4512 u8 reserved_at_80
[0x180];
4515 struct mlx5_ifc_query_rqt_out_bits
{
4517 u8 reserved_at_8
[0x18];
4521 u8 reserved_at_40
[0xc0];
4523 struct mlx5_ifc_rqtc_bits rqt_context
;
4526 struct mlx5_ifc_query_rqt_in_bits
{
4528 u8 reserved_at_10
[0x10];
4530 u8 reserved_at_20
[0x10];
4533 u8 reserved_at_40
[0x8];
4536 u8 reserved_at_60
[0x20];
4539 struct mlx5_ifc_query_rq_out_bits
{
4541 u8 reserved_at_8
[0x18];
4545 u8 reserved_at_40
[0xc0];
4547 struct mlx5_ifc_rqc_bits rq_context
;
4550 struct mlx5_ifc_query_rq_in_bits
{
4552 u8 reserved_at_10
[0x10];
4554 u8 reserved_at_20
[0x10];
4557 u8 reserved_at_40
[0x8];
4560 u8 reserved_at_60
[0x20];
4563 struct mlx5_ifc_query_roce_address_out_bits
{
4565 u8 reserved_at_8
[0x18];
4569 u8 reserved_at_40
[0x40];
4571 struct mlx5_ifc_roce_addr_layout_bits roce_address
;
4574 struct mlx5_ifc_query_roce_address_in_bits
{
4576 u8 reserved_at_10
[0x10];
4578 u8 reserved_at_20
[0x10];
4581 u8 roce_address_index
[0x10];
4582 u8 reserved_at_50
[0xc];
4583 u8 vhca_port_num
[0x4];
4585 u8 reserved_at_60
[0x20];
4588 struct mlx5_ifc_query_rmp_out_bits
{
4590 u8 reserved_at_8
[0x18];
4594 u8 reserved_at_40
[0xc0];
4596 struct mlx5_ifc_rmpc_bits rmp_context
;
4599 struct mlx5_ifc_query_rmp_in_bits
{
4601 u8 reserved_at_10
[0x10];
4603 u8 reserved_at_20
[0x10];
4606 u8 reserved_at_40
[0x8];
4609 u8 reserved_at_60
[0x20];
4612 struct mlx5_ifc_query_qp_out_bits
{
4614 u8 reserved_at_8
[0x18];
4618 u8 reserved_at_40
[0x40];
4620 u8 opt_param_mask
[0x20];
4622 u8 reserved_at_a0
[0x20];
4624 struct mlx5_ifc_qpc_bits qpc
;
4626 u8 reserved_at_800
[0x80];
4631 struct mlx5_ifc_query_qp_in_bits
{
4633 u8 reserved_at_10
[0x10];
4635 u8 reserved_at_20
[0x10];
4638 u8 reserved_at_40
[0x8];
4641 u8 reserved_at_60
[0x20];
4644 struct mlx5_ifc_query_q_counter_out_bits
{
4646 u8 reserved_at_8
[0x18];
4650 u8 reserved_at_40
[0x40];
4652 u8 rx_write_requests
[0x20];
4654 u8 reserved_at_a0
[0x20];
4656 u8 rx_read_requests
[0x20];
4658 u8 reserved_at_e0
[0x20];
4660 u8 rx_atomic_requests
[0x20];
4662 u8 reserved_at_120
[0x20];
4664 u8 rx_dct_connect
[0x20];
4666 u8 reserved_at_160
[0x20];
4668 u8 out_of_buffer
[0x20];
4670 u8 reserved_at_1a0
[0x20];
4672 u8 out_of_sequence
[0x20];
4674 u8 reserved_at_1e0
[0x20];
4676 u8 duplicate_request
[0x20];
4678 u8 reserved_at_220
[0x20];
4680 u8 rnr_nak_retry_err
[0x20];
4682 u8 reserved_at_260
[0x20];
4684 u8 packet_seq_err
[0x20];
4686 u8 reserved_at_2a0
[0x20];
4688 u8 implied_nak_seq_err
[0x20];
4690 u8 reserved_at_2e0
[0x20];
4692 u8 local_ack_timeout_err
[0x20];
4694 u8 reserved_at_320
[0xa0];
4696 u8 resp_local_length_error
[0x20];
4698 u8 req_local_length_error
[0x20];
4700 u8 resp_local_qp_error
[0x20];
4702 u8 local_operation_error
[0x20];
4704 u8 resp_local_protection
[0x20];
4706 u8 req_local_protection
[0x20];
4708 u8 resp_cqe_error
[0x20];
4710 u8 req_cqe_error
[0x20];
4712 u8 req_mw_binding
[0x20];
4714 u8 req_bad_response
[0x20];
4716 u8 req_remote_invalid_request
[0x20];
4718 u8 resp_remote_invalid_request
[0x20];
4720 u8 req_remote_access_errors
[0x20];
4722 u8 resp_remote_access_errors
[0x20];
4724 u8 req_remote_operation_errors
[0x20];
4726 u8 req_transport_retries_exceeded
[0x20];
4728 u8 cq_overflow
[0x20];
4730 u8 resp_cqe_flush_error
[0x20];
4732 u8 req_cqe_flush_error
[0x20];
4734 u8 reserved_at_620
[0x1e0];
4737 struct mlx5_ifc_query_q_counter_in_bits
{
4739 u8 reserved_at_10
[0x10];
4741 u8 reserved_at_20
[0x10];
4744 u8 reserved_at_40
[0x80];
4747 u8 reserved_at_c1
[0x1f];
4749 u8 reserved_at_e0
[0x18];
4750 u8 counter_set_id
[0x8];
4753 struct mlx5_ifc_query_pages_out_bits
{
4755 u8 reserved_at_8
[0x18];
4759 u8 embedded_cpu_function
[0x1];
4760 u8 reserved_at_41
[0xf];
4761 u8 function_id
[0x10];
4767 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES
= 0x1,
4768 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES
= 0x2,
4769 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES
= 0x3,
4772 struct mlx5_ifc_query_pages_in_bits
{
4774 u8 reserved_at_10
[0x10];
4776 u8 reserved_at_20
[0x10];
4779 u8 embedded_cpu_function
[0x1];
4780 u8 reserved_at_41
[0xf];
4781 u8 function_id
[0x10];
4783 u8 reserved_at_60
[0x20];
4786 struct mlx5_ifc_query_nic_vport_context_out_bits
{
4788 u8 reserved_at_8
[0x18];
4792 u8 reserved_at_40
[0x40];
4794 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
4797 struct mlx5_ifc_query_nic_vport_context_in_bits
{
4799 u8 reserved_at_10
[0x10];
4801 u8 reserved_at_20
[0x10];
4804 u8 other_vport
[0x1];
4805 u8 reserved_at_41
[0xf];
4806 u8 vport_number
[0x10];
4808 u8 reserved_at_60
[0x5];
4809 u8 allowed_list_type
[0x3];
4810 u8 reserved_at_68
[0x18];
4813 struct mlx5_ifc_query_mkey_out_bits
{
4815 u8 reserved_at_8
[0x18];
4819 u8 reserved_at_40
[0x40];
4821 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
4823 u8 reserved_at_280
[0x600];
4825 u8 bsf0_klm0_pas_mtt0_1
[16][0x8];
4827 u8 bsf1_klm1_pas_mtt2_3
[16][0x8];
4830 struct mlx5_ifc_query_mkey_in_bits
{
4832 u8 reserved_at_10
[0x10];
4834 u8 reserved_at_20
[0x10];
4837 u8 reserved_at_40
[0x8];
4838 u8 mkey_index
[0x18];
4841 u8 reserved_at_61
[0x1f];
4844 struct mlx5_ifc_query_mad_demux_out_bits
{
4846 u8 reserved_at_8
[0x18];
4850 u8 reserved_at_40
[0x40];
4852 u8 mad_dumux_parameters_block
[0x20];
4855 struct mlx5_ifc_query_mad_demux_in_bits
{
4857 u8 reserved_at_10
[0x10];
4859 u8 reserved_at_20
[0x10];
4862 u8 reserved_at_40
[0x40];
4865 struct mlx5_ifc_query_l2_table_entry_out_bits
{
4867 u8 reserved_at_8
[0x18];
4871 u8 reserved_at_40
[0xa0];
4873 u8 reserved_at_e0
[0x13];
4877 struct mlx5_ifc_mac_address_layout_bits mac_address
;
4879 u8 reserved_at_140
[0xc0];
4882 struct mlx5_ifc_query_l2_table_entry_in_bits
{
4884 u8 reserved_at_10
[0x10];
4886 u8 reserved_at_20
[0x10];
4889 u8 reserved_at_40
[0x60];
4891 u8 reserved_at_a0
[0x8];
4892 u8 table_index
[0x18];
4894 u8 reserved_at_c0
[0x140];
4897 struct mlx5_ifc_query_issi_out_bits
{
4899 u8 reserved_at_8
[0x18];
4903 u8 reserved_at_40
[0x10];
4904 u8 current_issi
[0x10];
4906 u8 reserved_at_60
[0xa0];
4908 u8 reserved_at_100
[76][0x8];
4909 u8 supported_issi_dw0
[0x20];
4912 struct mlx5_ifc_query_issi_in_bits
{
4914 u8 reserved_at_10
[0x10];
4916 u8 reserved_at_20
[0x10];
4919 u8 reserved_at_40
[0x40];
4922 struct mlx5_ifc_set_driver_version_out_bits
{
4924 u8 reserved_0
[0x18];
4927 u8 reserved_1
[0x40];
4930 struct mlx5_ifc_set_driver_version_in_bits
{
4932 u8 reserved_0
[0x10];
4934 u8 reserved_1
[0x10];
4937 u8 reserved_2
[0x40];
4938 u8 driver_version
[64][0x8];
4941 struct mlx5_ifc_query_hca_vport_pkey_out_bits
{
4943 u8 reserved_at_8
[0x18];
4947 u8 reserved_at_40
[0x40];
4949 struct mlx5_ifc_pkey_bits pkey
[0];
4952 struct mlx5_ifc_query_hca_vport_pkey_in_bits
{
4954 u8 reserved_at_10
[0x10];
4956 u8 reserved_at_20
[0x10];
4959 u8 other_vport
[0x1];
4960 u8 reserved_at_41
[0xb];
4962 u8 vport_number
[0x10];
4964 u8 reserved_at_60
[0x10];
4965 u8 pkey_index
[0x10];
4969 MLX5_HCA_VPORT_SEL_PORT_GUID
= 1 << 0,
4970 MLX5_HCA_VPORT_SEL_NODE_GUID
= 1 << 1,
4971 MLX5_HCA_VPORT_SEL_STATE_POLICY
= 1 << 2,
4974 struct mlx5_ifc_query_hca_vport_gid_out_bits
{
4976 u8 reserved_at_8
[0x18];
4980 u8 reserved_at_40
[0x20];
4983 u8 reserved_at_70
[0x10];
4985 struct mlx5_ifc_array128_auto_bits gid
[0];
4988 struct mlx5_ifc_query_hca_vport_gid_in_bits
{
4990 u8 reserved_at_10
[0x10];
4992 u8 reserved_at_20
[0x10];
4995 u8 other_vport
[0x1];
4996 u8 reserved_at_41
[0xb];
4998 u8 vport_number
[0x10];
5000 u8 reserved_at_60
[0x10];
5004 struct mlx5_ifc_query_hca_vport_context_out_bits
{
5006 u8 reserved_at_8
[0x18];
5010 u8 reserved_at_40
[0x40];
5012 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
5015 struct mlx5_ifc_query_hca_vport_context_in_bits
{
5017 u8 reserved_at_10
[0x10];
5019 u8 reserved_at_20
[0x10];
5022 u8 other_vport
[0x1];
5023 u8 reserved_at_41
[0xb];
5025 u8 vport_number
[0x10];
5027 u8 reserved_at_60
[0x20];
5030 struct mlx5_ifc_query_hca_cap_out_bits
{
5032 u8 reserved_at_8
[0x18];
5036 u8 reserved_at_40
[0x40];
5038 union mlx5_ifc_hca_cap_union_bits capability
;
5041 struct mlx5_ifc_query_hca_cap_in_bits
{
5043 u8 reserved_at_10
[0x10];
5045 u8 reserved_at_20
[0x10];
5048 u8 other_function
[0x1];
5049 u8 reserved_at_41
[0xf];
5050 u8 function_id
[0x10];
5052 u8 reserved_at_60
[0x20];
5055 struct mlx5_ifc_other_hca_cap_bits
{
5057 u8 reserved_at_1
[0x27f];
5060 struct mlx5_ifc_query_other_hca_cap_out_bits
{
5062 u8 reserved_at_8
[0x18];
5066 u8 reserved_at_40
[0x40];
5068 struct mlx5_ifc_other_hca_cap_bits other_capability
;
5071 struct mlx5_ifc_query_other_hca_cap_in_bits
{
5073 u8 reserved_at_10
[0x10];
5075 u8 reserved_at_20
[0x10];
5078 u8 reserved_at_40
[0x10];
5079 u8 function_id
[0x10];
5081 u8 reserved_at_60
[0x20];
5084 struct mlx5_ifc_modify_other_hca_cap_out_bits
{
5086 u8 reserved_at_8
[0x18];
5090 u8 reserved_at_40
[0x40];
5093 struct mlx5_ifc_modify_other_hca_cap_in_bits
{
5095 u8 reserved_at_10
[0x10];
5097 u8 reserved_at_20
[0x10];
5100 u8 reserved_at_40
[0x10];
5101 u8 function_id
[0x10];
5102 u8 field_select
[0x20];
5104 struct mlx5_ifc_other_hca_cap_bits other_capability
;
5107 struct mlx5_ifc_flow_table_context_bits
{
5108 u8 reformat_en
[0x1];
5111 u8 termination_table
[0x1];
5112 u8 table_miss_action
[0x4];
5114 u8 reserved_at_10
[0x8];
5117 u8 reserved_at_20
[0x8];
5118 u8 table_miss_id
[0x18];
5120 u8 reserved_at_40
[0x8];
5121 u8 lag_master_next_table_id
[0x18];
5123 u8 reserved_at_60
[0x60];
5125 u8 sw_owner_icm_root_1
[0x40];
5127 u8 sw_owner_icm_root_0
[0x40];
5131 struct mlx5_ifc_query_flow_table_out_bits
{
5133 u8 reserved_at_8
[0x18];
5137 u8 reserved_at_40
[0x80];
5139 struct mlx5_ifc_flow_table_context_bits flow_table_context
;
5142 struct mlx5_ifc_query_flow_table_in_bits
{
5144 u8 reserved_at_10
[0x10];
5146 u8 reserved_at_20
[0x10];
5149 u8 reserved_at_40
[0x40];
5152 u8 reserved_at_88
[0x18];
5154 u8 reserved_at_a0
[0x8];
5157 u8 reserved_at_c0
[0x140];
5160 struct mlx5_ifc_query_fte_out_bits
{
5162 u8 reserved_at_8
[0x18];
5166 u8 reserved_at_40
[0x1c0];
5168 struct mlx5_ifc_flow_context_bits flow_context
;
5171 struct mlx5_ifc_query_fte_in_bits
{
5173 u8 reserved_at_10
[0x10];
5175 u8 reserved_at_20
[0x10];
5178 u8 reserved_at_40
[0x40];
5181 u8 reserved_at_88
[0x18];
5183 u8 reserved_at_a0
[0x8];
5186 u8 reserved_at_c0
[0x40];
5188 u8 flow_index
[0x20];
5190 u8 reserved_at_120
[0xe0];
5194 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
5195 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
5196 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
5197 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2
= 0x3,
5198 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3
= 0x4,
5201 struct mlx5_ifc_query_flow_group_out_bits
{
5203 u8 reserved_at_8
[0x18];
5207 u8 reserved_at_40
[0xa0];
5209 u8 start_flow_index
[0x20];
5211 u8 reserved_at_100
[0x20];
5213 u8 end_flow_index
[0x20];
5215 u8 reserved_at_140
[0xa0];
5217 u8 reserved_at_1e0
[0x18];
5218 u8 match_criteria_enable
[0x8];
5220 struct mlx5_ifc_fte_match_param_bits match_criteria
;
5222 u8 reserved_at_1200
[0xe00];
5225 struct mlx5_ifc_query_flow_group_in_bits
{
5227 u8 reserved_at_10
[0x10];
5229 u8 reserved_at_20
[0x10];
5232 u8 reserved_at_40
[0x40];
5235 u8 reserved_at_88
[0x18];
5237 u8 reserved_at_a0
[0x8];
5242 u8 reserved_at_e0
[0x120];
5245 struct mlx5_ifc_query_flow_counter_out_bits
{
5247 u8 reserved_at_8
[0x18];
5251 u8 reserved_at_40
[0x40];
5253 struct mlx5_ifc_traffic_counter_bits flow_statistics
[0];
5256 struct mlx5_ifc_query_flow_counter_in_bits
{
5258 u8 reserved_at_10
[0x10];
5260 u8 reserved_at_20
[0x10];
5263 u8 reserved_at_40
[0x80];
5266 u8 reserved_at_c1
[0xf];
5267 u8 num_of_counters
[0x10];
5269 u8 flow_counter_id
[0x20];
5272 struct mlx5_ifc_query_esw_vport_context_out_bits
{
5274 u8 reserved_at_8
[0x18];
5278 u8 reserved_at_40
[0x40];
5280 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
5283 struct mlx5_ifc_query_esw_vport_context_in_bits
{
5285 u8 reserved_at_10
[0x10];
5287 u8 reserved_at_20
[0x10];
5290 u8 other_vport
[0x1];
5291 u8 reserved_at_41
[0xf];
5292 u8 vport_number
[0x10];
5294 u8 reserved_at_60
[0x20];
5297 struct mlx5_ifc_modify_esw_vport_context_out_bits
{
5299 u8 reserved_at_8
[0x18];
5303 u8 reserved_at_40
[0x40];
5306 struct mlx5_ifc_esw_vport_context_fields_select_bits
{
5307 u8 reserved_at_0
[0x1b];
5308 u8 fdb_to_vport_reg_c_id
[0x1];
5309 u8 vport_cvlan_insert
[0x1];
5310 u8 vport_svlan_insert
[0x1];
5311 u8 vport_cvlan_strip
[0x1];
5312 u8 vport_svlan_strip
[0x1];
5315 struct mlx5_ifc_modify_esw_vport_context_in_bits
{
5317 u8 reserved_at_10
[0x10];
5319 u8 reserved_at_20
[0x10];
5322 u8 other_vport
[0x1];
5323 u8 reserved_at_41
[0xf];
5324 u8 vport_number
[0x10];
5326 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select
;
5328 struct mlx5_ifc_esw_vport_context_bits esw_vport_context
;
5331 struct mlx5_ifc_query_eq_out_bits
{
5333 u8 reserved_at_8
[0x18];
5337 u8 reserved_at_40
[0x40];
5339 struct mlx5_ifc_eqc_bits eq_context_entry
;
5341 u8 reserved_at_280
[0x40];
5343 u8 event_bitmask
[0x40];
5345 u8 reserved_at_300
[0x580];
5350 struct mlx5_ifc_query_eq_in_bits
{
5352 u8 reserved_at_10
[0x10];
5354 u8 reserved_at_20
[0x10];
5357 u8 reserved_at_40
[0x18];
5360 u8 reserved_at_60
[0x20];
5363 struct mlx5_ifc_packet_reformat_context_in_bits
{
5364 u8 reserved_at_0
[0x5];
5365 u8 reformat_type
[0x3];
5366 u8 reserved_at_8
[0xe];
5367 u8 reformat_data_size
[0xa];
5369 u8 reserved_at_20
[0x10];
5370 u8 reformat_data
[2][0x8];
5372 u8 more_reformat_data
[0][0x8];
5375 struct mlx5_ifc_query_packet_reformat_context_out_bits
{
5377 u8 reserved_at_8
[0x18];
5381 u8 reserved_at_40
[0xa0];
5383 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context
[0];
5386 struct mlx5_ifc_query_packet_reformat_context_in_bits
{
5388 u8 reserved_at_10
[0x10];
5390 u8 reserved_at_20
[0x10];
5393 u8 packet_reformat_id
[0x20];
5395 u8 reserved_at_60
[0xa0];
5398 struct mlx5_ifc_alloc_packet_reformat_context_out_bits
{
5400 u8 reserved_at_8
[0x18];
5404 u8 packet_reformat_id
[0x20];
5406 u8 reserved_at_60
[0x20];
5409 enum mlx5_reformat_ctx_type
{
5410 MLX5_REFORMAT_TYPE_L2_TO_VXLAN
= 0x0,
5411 MLX5_REFORMAT_TYPE_L2_TO_NVGRE
= 0x1,
5412 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL
= 0x2,
5413 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2
= 0x3,
5414 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL
= 0x4,
5417 struct mlx5_ifc_alloc_packet_reformat_context_in_bits
{
5419 u8 reserved_at_10
[0x10];
5421 u8 reserved_at_20
[0x10];
5424 u8 reserved_at_40
[0xa0];
5426 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context
;
5429 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits
{
5431 u8 reserved_at_8
[0x18];
5435 u8 reserved_at_40
[0x40];
5438 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits
{
5440 u8 reserved_at_10
[0x10];
5442 u8 reserved_20
[0x10];
5445 u8 packet_reformat_id
[0x20];
5447 u8 reserved_60
[0x20];
5450 struct mlx5_ifc_set_action_in_bits
{
5451 u8 action_type
[0x4];
5453 u8 reserved_at_10
[0x3];
5455 u8 reserved_at_18
[0x3];
5461 struct mlx5_ifc_add_action_in_bits
{
5462 u8 action_type
[0x4];
5464 u8 reserved_at_10
[0x10];
5469 union mlx5_ifc_set_action_in_add_action_in_auto_bits
{
5470 struct mlx5_ifc_set_action_in_bits set_action_in
;
5471 struct mlx5_ifc_add_action_in_bits add_action_in
;
5472 u8 reserved_at_0
[0x40];
5476 MLX5_ACTION_TYPE_SET
= 0x1,
5477 MLX5_ACTION_TYPE_ADD
= 0x2,
5481 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16
= 0x1,
5482 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0
= 0x2,
5483 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE
= 0x3,
5484 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16
= 0x4,
5485 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0
= 0x5,
5486 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP
= 0x6,
5487 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS
= 0x7,
5488 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT
= 0x8,
5489 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT
= 0x9,
5490 MLX5_ACTION_IN_FIELD_OUT_IP_TTL
= 0xa,
5491 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT
= 0xb,
5492 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT
= 0xc,
5493 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96
= 0xd,
5494 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64
= 0xe,
5495 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32
= 0xf,
5496 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0
= 0x10,
5497 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96
= 0x11,
5498 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64
= 0x12,
5499 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32
= 0x13,
5500 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0
= 0x14,
5501 MLX5_ACTION_IN_FIELD_OUT_SIPV4
= 0x15,
5502 MLX5_ACTION_IN_FIELD_OUT_DIPV4
= 0x16,
5503 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID
= 0x17,
5504 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT
= 0x47,
5505 MLX5_ACTION_IN_FIELD_METADATA_REG_A
= 0x49,
5506 MLX5_ACTION_IN_FIELD_METADATA_REG_B
= 0x50,
5507 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0
= 0x51,
5508 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1
= 0x52,
5509 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2
= 0x53,
5510 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3
= 0x54,
5511 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4
= 0x55,
5512 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5
= 0x56,
5513 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM
= 0x59,
5514 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM
= 0x5B,
5517 struct mlx5_ifc_alloc_modify_header_context_out_bits
{
5519 u8 reserved_at_8
[0x18];
5523 u8 modify_header_id
[0x20];
5525 u8 reserved_at_60
[0x20];
5528 struct mlx5_ifc_alloc_modify_header_context_in_bits
{
5530 u8 reserved_at_10
[0x10];
5532 u8 reserved_at_20
[0x10];
5535 u8 reserved_at_40
[0x20];
5538 u8 reserved_at_68
[0x10];
5539 u8 num_of_actions
[0x8];
5541 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions
[0];
5544 struct mlx5_ifc_dealloc_modify_header_context_out_bits
{
5546 u8 reserved_at_8
[0x18];
5550 u8 reserved_at_40
[0x40];
5553 struct mlx5_ifc_dealloc_modify_header_context_in_bits
{
5555 u8 reserved_at_10
[0x10];
5557 u8 reserved_at_20
[0x10];
5560 u8 modify_header_id
[0x20];
5562 u8 reserved_at_60
[0x20];
5565 struct mlx5_ifc_query_dct_out_bits
{
5567 u8 reserved_at_8
[0x18];
5571 u8 reserved_at_40
[0x40];
5573 struct mlx5_ifc_dctc_bits dct_context_entry
;
5575 u8 reserved_at_280
[0x180];
5578 struct mlx5_ifc_query_dct_in_bits
{
5580 u8 reserved_at_10
[0x10];
5582 u8 reserved_at_20
[0x10];
5585 u8 reserved_at_40
[0x8];
5588 u8 reserved_at_60
[0x20];
5591 struct mlx5_ifc_query_cq_out_bits
{
5593 u8 reserved_at_8
[0x18];
5597 u8 reserved_at_40
[0x40];
5599 struct mlx5_ifc_cqc_bits cq_context
;
5601 u8 reserved_at_280
[0x600];
5606 struct mlx5_ifc_query_cq_in_bits
{
5608 u8 reserved_at_10
[0x10];
5610 u8 reserved_at_20
[0x10];
5613 u8 reserved_at_40
[0x8];
5616 u8 reserved_at_60
[0x20];
5619 struct mlx5_ifc_query_cong_status_out_bits
{
5621 u8 reserved_at_8
[0x18];
5625 u8 reserved_at_40
[0x20];
5629 u8 reserved_at_62
[0x1e];
5632 struct mlx5_ifc_query_cong_status_in_bits
{
5634 u8 reserved_at_10
[0x10];
5636 u8 reserved_at_20
[0x10];
5639 u8 reserved_at_40
[0x18];
5641 u8 cong_protocol
[0x4];
5643 u8 reserved_at_60
[0x20];
5646 struct mlx5_ifc_query_cong_statistics_out_bits
{
5648 u8 reserved_at_8
[0x18];
5652 u8 reserved_at_40
[0x40];
5654 u8 rp_cur_flows
[0x20];
5658 u8 rp_cnp_ignored_high
[0x20];
5660 u8 rp_cnp_ignored_low
[0x20];
5662 u8 rp_cnp_handled_high
[0x20];
5664 u8 rp_cnp_handled_low
[0x20];
5666 u8 reserved_at_140
[0x100];
5668 u8 time_stamp_high
[0x20];
5670 u8 time_stamp_low
[0x20];
5672 u8 accumulators_period
[0x20];
5674 u8 np_ecn_marked_roce_packets_high
[0x20];
5676 u8 np_ecn_marked_roce_packets_low
[0x20];
5678 u8 np_cnp_sent_high
[0x20];
5680 u8 np_cnp_sent_low
[0x20];
5682 u8 reserved_at_320
[0x560];
5685 struct mlx5_ifc_query_cong_statistics_in_bits
{
5687 u8 reserved_at_10
[0x10];
5689 u8 reserved_at_20
[0x10];
5693 u8 reserved_at_41
[0x1f];
5695 u8 reserved_at_60
[0x20];
5698 struct mlx5_ifc_query_cong_params_out_bits
{
5700 u8 reserved_at_8
[0x18];
5704 u8 reserved_at_40
[0x40];
5706 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
5709 struct mlx5_ifc_query_cong_params_in_bits
{
5711 u8 reserved_at_10
[0x10];
5713 u8 reserved_at_20
[0x10];
5716 u8 reserved_at_40
[0x1c];
5717 u8 cong_protocol
[0x4];
5719 u8 reserved_at_60
[0x20];
5722 struct mlx5_ifc_query_adapter_out_bits
{
5724 u8 reserved_at_8
[0x18];
5728 u8 reserved_at_40
[0x40];
5730 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct
;
5733 struct mlx5_ifc_query_adapter_in_bits
{
5735 u8 reserved_at_10
[0x10];
5737 u8 reserved_at_20
[0x10];
5740 u8 reserved_at_40
[0x40];
5743 struct mlx5_ifc_qp_2rst_out_bits
{
5745 u8 reserved_at_8
[0x18];
5749 u8 reserved_at_40
[0x40];
5752 struct mlx5_ifc_qp_2rst_in_bits
{
5756 u8 reserved_at_20
[0x10];
5759 u8 reserved_at_40
[0x8];
5762 u8 reserved_at_60
[0x20];
5765 struct mlx5_ifc_qp_2err_out_bits
{
5767 u8 reserved_at_8
[0x18];
5771 u8 reserved_at_40
[0x40];
5774 struct mlx5_ifc_qp_2err_in_bits
{
5778 u8 reserved_at_20
[0x10];
5781 u8 reserved_at_40
[0x8];
5784 u8 reserved_at_60
[0x20];
5787 struct mlx5_ifc_page_fault_resume_out_bits
{
5789 u8 reserved_at_8
[0x18];
5793 u8 reserved_at_40
[0x40];
5796 struct mlx5_ifc_page_fault_resume_in_bits
{
5798 u8 reserved_at_10
[0x10];
5800 u8 reserved_at_20
[0x10];
5804 u8 reserved_at_41
[0x4];
5805 u8 page_fault_type
[0x3];
5808 u8 reserved_at_60
[0x8];
5812 struct mlx5_ifc_nop_out_bits
{
5814 u8 reserved_at_8
[0x18];
5818 u8 reserved_at_40
[0x40];
5821 struct mlx5_ifc_nop_in_bits
{
5823 u8 reserved_at_10
[0x10];
5825 u8 reserved_at_20
[0x10];
5828 u8 reserved_at_40
[0x40];
5831 struct mlx5_ifc_modify_vport_state_out_bits
{
5833 u8 reserved_at_8
[0x18];
5837 u8 reserved_at_40
[0x40];
5840 struct mlx5_ifc_modify_vport_state_in_bits
{
5842 u8 reserved_at_10
[0x10];
5844 u8 reserved_at_20
[0x10];
5847 u8 other_vport
[0x1];
5848 u8 reserved_at_41
[0xf];
5849 u8 vport_number
[0x10];
5851 u8 reserved_at_60
[0x18];
5852 u8 admin_state
[0x4];
5853 u8 reserved_at_7c
[0x4];
5856 struct mlx5_ifc_modify_tis_out_bits
{
5858 u8 reserved_at_8
[0x18];
5862 u8 reserved_at_40
[0x40];
5865 struct mlx5_ifc_modify_tis_bitmask_bits
{
5866 u8 reserved_at_0
[0x20];
5868 u8 reserved_at_20
[0x1d];
5869 u8 lag_tx_port_affinity
[0x1];
5870 u8 strict_lag_tx_port_affinity
[0x1];
5874 struct mlx5_ifc_modify_tis_in_bits
{
5878 u8 reserved_at_20
[0x10];
5881 u8 reserved_at_40
[0x8];
5884 u8 reserved_at_60
[0x20];
5886 struct mlx5_ifc_modify_tis_bitmask_bits bitmask
;
5888 u8 reserved_at_c0
[0x40];
5890 struct mlx5_ifc_tisc_bits ctx
;
5893 struct mlx5_ifc_modify_tir_bitmask_bits
{
5894 u8 reserved_at_0
[0x20];
5896 u8 reserved_at_20
[0x1b];
5898 u8 reserved_at_3c
[0x1];
5900 u8 reserved_at_3e
[0x1];
5904 struct mlx5_ifc_modify_tir_out_bits
{
5906 u8 reserved_at_8
[0x18];
5910 u8 reserved_at_40
[0x40];
5913 struct mlx5_ifc_modify_tir_in_bits
{
5917 u8 reserved_at_20
[0x10];
5920 u8 reserved_at_40
[0x8];
5923 u8 reserved_at_60
[0x20];
5925 struct mlx5_ifc_modify_tir_bitmask_bits bitmask
;
5927 u8 reserved_at_c0
[0x40];
5929 struct mlx5_ifc_tirc_bits ctx
;
5932 struct mlx5_ifc_modify_sq_out_bits
{
5934 u8 reserved_at_8
[0x18];
5938 u8 reserved_at_40
[0x40];
5941 struct mlx5_ifc_modify_sq_in_bits
{
5945 u8 reserved_at_20
[0x10];
5949 u8 reserved_at_44
[0x4];
5952 u8 reserved_at_60
[0x20];
5954 u8 modify_bitmask
[0x40];
5956 u8 reserved_at_c0
[0x40];
5958 struct mlx5_ifc_sqc_bits ctx
;
5961 struct mlx5_ifc_modify_scheduling_element_out_bits
{
5963 u8 reserved_at_8
[0x18];
5967 u8 reserved_at_40
[0x1c0];
5971 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE
= 0x1,
5972 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW
= 0x2,
5975 struct mlx5_ifc_modify_scheduling_element_in_bits
{
5977 u8 reserved_at_10
[0x10];
5979 u8 reserved_at_20
[0x10];
5982 u8 scheduling_hierarchy
[0x8];
5983 u8 reserved_at_48
[0x18];
5985 u8 scheduling_element_id
[0x20];
5987 u8 reserved_at_80
[0x20];
5989 u8 modify_bitmask
[0x20];
5991 u8 reserved_at_c0
[0x40];
5993 struct mlx5_ifc_scheduling_context_bits scheduling_context
;
5995 u8 reserved_at_300
[0x100];
5998 struct mlx5_ifc_modify_rqt_out_bits
{
6000 u8 reserved_at_8
[0x18];
6004 u8 reserved_at_40
[0x40];
6007 struct mlx5_ifc_rqt_bitmask_bits
{
6008 u8 reserved_at_0
[0x20];
6010 u8 reserved_at_20
[0x1f];
6014 struct mlx5_ifc_modify_rqt_in_bits
{
6018 u8 reserved_at_20
[0x10];
6021 u8 reserved_at_40
[0x8];
6024 u8 reserved_at_60
[0x20];
6026 struct mlx5_ifc_rqt_bitmask_bits bitmask
;
6028 u8 reserved_at_c0
[0x40];
6030 struct mlx5_ifc_rqtc_bits ctx
;
6033 struct mlx5_ifc_modify_rq_out_bits
{
6035 u8 reserved_at_8
[0x18];
6039 u8 reserved_at_40
[0x40];
6043 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD
= 1ULL << 1,
6044 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS
= 1ULL << 2,
6045 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID
= 1ULL << 3,
6048 struct mlx5_ifc_modify_rq_in_bits
{
6052 u8 reserved_at_20
[0x10];
6056 u8 reserved_at_44
[0x4];
6059 u8 reserved_at_60
[0x20];
6061 u8 modify_bitmask
[0x40];
6063 u8 reserved_at_c0
[0x40];
6065 struct mlx5_ifc_rqc_bits ctx
;
6068 struct mlx5_ifc_modify_rmp_out_bits
{
6070 u8 reserved_at_8
[0x18];
6074 u8 reserved_at_40
[0x40];
6077 struct mlx5_ifc_rmp_bitmask_bits
{
6078 u8 reserved_at_0
[0x20];
6080 u8 reserved_at_20
[0x1f];
6084 struct mlx5_ifc_modify_rmp_in_bits
{
6088 u8 reserved_at_20
[0x10];
6092 u8 reserved_at_44
[0x4];
6095 u8 reserved_at_60
[0x20];
6097 struct mlx5_ifc_rmp_bitmask_bits bitmask
;
6099 u8 reserved_at_c0
[0x40];
6101 struct mlx5_ifc_rmpc_bits ctx
;
6104 struct mlx5_ifc_modify_nic_vport_context_out_bits
{
6106 u8 reserved_at_8
[0x18];
6110 u8 reserved_at_40
[0x40];
6113 struct mlx5_ifc_modify_nic_vport_field_select_bits
{
6114 u8 reserved_at_0
[0x12];
6115 u8 affiliation
[0x1];
6116 u8 reserved_at_13
[0x1];
6117 u8 disable_uc_local_lb
[0x1];
6118 u8 disable_mc_local_lb
[0x1];
6123 u8 change_event
[0x1];
6125 u8 permanent_address
[0x1];
6126 u8 addresses_list
[0x1];
6128 u8 reserved_at_1f
[0x1];
6131 struct mlx5_ifc_modify_nic_vport_context_in_bits
{
6133 u8 reserved_at_10
[0x10];
6135 u8 reserved_at_20
[0x10];
6138 u8 other_vport
[0x1];
6139 u8 reserved_at_41
[0xf];
6140 u8 vport_number
[0x10];
6142 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select
;
6144 u8 reserved_at_80
[0x780];
6146 struct mlx5_ifc_nic_vport_context_bits nic_vport_context
;
6149 struct mlx5_ifc_modify_hca_vport_context_out_bits
{
6151 u8 reserved_at_8
[0x18];
6155 u8 reserved_at_40
[0x40];
6158 struct mlx5_ifc_modify_hca_vport_context_in_bits
{
6160 u8 reserved_at_10
[0x10];
6162 u8 reserved_at_20
[0x10];
6165 u8 other_vport
[0x1];
6166 u8 reserved_at_41
[0xb];
6168 u8 vport_number
[0x10];
6170 u8 reserved_at_60
[0x20];
6172 struct mlx5_ifc_hca_vport_context_bits hca_vport_context
;
6175 struct mlx5_ifc_modify_cq_out_bits
{
6177 u8 reserved_at_8
[0x18];
6181 u8 reserved_at_40
[0x40];
6185 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ
= 0x0,
6186 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ
= 0x1,
6189 struct mlx5_ifc_modify_cq_in_bits
{
6193 u8 reserved_at_20
[0x10];
6196 u8 reserved_at_40
[0x8];
6199 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select
;
6201 struct mlx5_ifc_cqc_bits cq_context
;
6203 u8 reserved_at_280
[0x60];
6205 u8 cq_umem_valid
[0x1];
6206 u8 reserved_at_2e1
[0x1f];
6208 u8 reserved_at_300
[0x580];
6213 struct mlx5_ifc_modify_cong_status_out_bits
{
6215 u8 reserved_at_8
[0x18];
6219 u8 reserved_at_40
[0x40];
6222 struct mlx5_ifc_modify_cong_status_in_bits
{
6224 u8 reserved_at_10
[0x10];
6226 u8 reserved_at_20
[0x10];
6229 u8 reserved_at_40
[0x18];
6231 u8 cong_protocol
[0x4];
6235 u8 reserved_at_62
[0x1e];
6238 struct mlx5_ifc_modify_cong_params_out_bits
{
6240 u8 reserved_at_8
[0x18];
6244 u8 reserved_at_40
[0x40];
6247 struct mlx5_ifc_modify_cong_params_in_bits
{
6249 u8 reserved_at_10
[0x10];
6251 u8 reserved_at_20
[0x10];
6254 u8 reserved_at_40
[0x1c];
6255 u8 cong_protocol
[0x4];
6257 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select
;
6259 u8 reserved_at_80
[0x80];
6261 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters
;
6264 struct mlx5_ifc_manage_pages_out_bits
{
6266 u8 reserved_at_8
[0x18];
6270 u8 output_num_entries
[0x20];
6272 u8 reserved_at_60
[0x20];
6278 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL
= 0x0,
6279 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS
= 0x1,
6280 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES
= 0x2,
6283 struct mlx5_ifc_manage_pages_in_bits
{
6285 u8 reserved_at_10
[0x10];
6287 u8 reserved_at_20
[0x10];
6290 u8 embedded_cpu_function
[0x1];
6291 u8 reserved_at_41
[0xf];
6292 u8 function_id
[0x10];
6294 u8 input_num_entries
[0x20];
6299 struct mlx5_ifc_mad_ifc_out_bits
{
6301 u8 reserved_at_8
[0x18];
6305 u8 reserved_at_40
[0x40];
6307 u8 response_mad_packet
[256][0x8];
6310 struct mlx5_ifc_mad_ifc_in_bits
{
6312 u8 reserved_at_10
[0x10];
6314 u8 reserved_at_20
[0x10];
6317 u8 remote_lid
[0x10];
6318 u8 reserved_at_50
[0x8];
6321 u8 reserved_at_60
[0x20];
6326 struct mlx5_ifc_init_hca_out_bits
{
6328 u8 reserved_at_8
[0x18];
6332 u8 reserved_at_40
[0x40];
6335 struct mlx5_ifc_init_hca_in_bits
{
6337 u8 reserved_at_10
[0x10];
6339 u8 reserved_at_20
[0x10];
6342 u8 reserved_at_40
[0x40];
6343 u8 sw_owner_id
[4][0x20];
6346 struct mlx5_ifc_init2rtr_qp_out_bits
{
6348 u8 reserved_at_8
[0x18];
6352 u8 reserved_at_40
[0x40];
6355 struct mlx5_ifc_init2rtr_qp_in_bits
{
6359 u8 reserved_at_20
[0x10];
6362 u8 reserved_at_40
[0x8];
6365 u8 reserved_at_60
[0x20];
6367 u8 opt_param_mask
[0x20];
6369 u8 reserved_at_a0
[0x20];
6371 struct mlx5_ifc_qpc_bits qpc
;
6373 u8 reserved_at_800
[0x80];
6376 struct mlx5_ifc_init2init_qp_out_bits
{
6378 u8 reserved_at_8
[0x18];
6382 u8 reserved_at_40
[0x40];
6385 struct mlx5_ifc_init2init_qp_in_bits
{
6389 u8 reserved_at_20
[0x10];
6392 u8 reserved_at_40
[0x8];
6395 u8 reserved_at_60
[0x20];
6397 u8 opt_param_mask
[0x20];
6399 u8 reserved_at_a0
[0x20];
6401 struct mlx5_ifc_qpc_bits qpc
;
6403 u8 reserved_at_800
[0x80];
6406 struct mlx5_ifc_get_dropped_packet_log_out_bits
{
6408 u8 reserved_at_8
[0x18];
6412 u8 reserved_at_40
[0x40];
6414 u8 packet_headers_log
[128][0x8];
6416 u8 packet_syndrome
[64][0x8];
6419 struct mlx5_ifc_get_dropped_packet_log_in_bits
{
6421 u8 reserved_at_10
[0x10];
6423 u8 reserved_at_20
[0x10];
6426 u8 reserved_at_40
[0x40];
6429 struct mlx5_ifc_gen_eqe_in_bits
{
6431 u8 reserved_at_10
[0x10];
6433 u8 reserved_at_20
[0x10];
6436 u8 reserved_at_40
[0x18];
6439 u8 reserved_at_60
[0x20];
6444 struct mlx5_ifc_gen_eq_out_bits
{
6446 u8 reserved_at_8
[0x18];
6450 u8 reserved_at_40
[0x40];
6453 struct mlx5_ifc_enable_hca_out_bits
{
6455 u8 reserved_at_8
[0x18];
6459 u8 reserved_at_40
[0x20];
6462 struct mlx5_ifc_enable_hca_in_bits
{
6464 u8 reserved_at_10
[0x10];
6466 u8 reserved_at_20
[0x10];
6469 u8 embedded_cpu_function
[0x1];
6470 u8 reserved_at_41
[0xf];
6471 u8 function_id
[0x10];
6473 u8 reserved_at_60
[0x20];
6476 struct mlx5_ifc_drain_dct_out_bits
{
6478 u8 reserved_at_8
[0x18];
6482 u8 reserved_at_40
[0x40];
6485 struct mlx5_ifc_drain_dct_in_bits
{
6489 u8 reserved_at_20
[0x10];
6492 u8 reserved_at_40
[0x8];
6495 u8 reserved_at_60
[0x20];
6498 struct mlx5_ifc_disable_hca_out_bits
{
6500 u8 reserved_at_8
[0x18];
6504 u8 reserved_at_40
[0x20];
6507 struct mlx5_ifc_disable_hca_in_bits
{
6509 u8 reserved_at_10
[0x10];
6511 u8 reserved_at_20
[0x10];
6514 u8 embedded_cpu_function
[0x1];
6515 u8 reserved_at_41
[0xf];
6516 u8 function_id
[0x10];
6518 u8 reserved_at_60
[0x20];
6521 struct mlx5_ifc_detach_from_mcg_out_bits
{
6523 u8 reserved_at_8
[0x18];
6527 u8 reserved_at_40
[0x40];
6530 struct mlx5_ifc_detach_from_mcg_in_bits
{
6534 u8 reserved_at_20
[0x10];
6537 u8 reserved_at_40
[0x8];
6540 u8 reserved_at_60
[0x20];
6542 u8 multicast_gid
[16][0x8];
6545 struct mlx5_ifc_destroy_xrq_out_bits
{
6547 u8 reserved_at_8
[0x18];
6551 u8 reserved_at_40
[0x40];
6554 struct mlx5_ifc_destroy_xrq_in_bits
{
6558 u8 reserved_at_20
[0x10];
6561 u8 reserved_at_40
[0x8];
6564 u8 reserved_at_60
[0x20];
6567 struct mlx5_ifc_destroy_xrc_srq_out_bits
{
6569 u8 reserved_at_8
[0x18];
6573 u8 reserved_at_40
[0x40];
6576 struct mlx5_ifc_destroy_xrc_srq_in_bits
{
6580 u8 reserved_at_20
[0x10];
6583 u8 reserved_at_40
[0x8];
6586 u8 reserved_at_60
[0x20];
6589 struct mlx5_ifc_destroy_tis_out_bits
{
6591 u8 reserved_at_8
[0x18];
6595 u8 reserved_at_40
[0x40];
6598 struct mlx5_ifc_destroy_tis_in_bits
{
6602 u8 reserved_at_20
[0x10];
6605 u8 reserved_at_40
[0x8];
6608 u8 reserved_at_60
[0x20];
6611 struct mlx5_ifc_destroy_tir_out_bits
{
6613 u8 reserved_at_8
[0x18];
6617 u8 reserved_at_40
[0x40];
6620 struct mlx5_ifc_destroy_tir_in_bits
{
6624 u8 reserved_at_20
[0x10];
6627 u8 reserved_at_40
[0x8];
6630 u8 reserved_at_60
[0x20];
6633 struct mlx5_ifc_destroy_srq_out_bits
{
6635 u8 reserved_at_8
[0x18];
6639 u8 reserved_at_40
[0x40];
6642 struct mlx5_ifc_destroy_srq_in_bits
{
6646 u8 reserved_at_20
[0x10];
6649 u8 reserved_at_40
[0x8];
6652 u8 reserved_at_60
[0x20];
6655 struct mlx5_ifc_destroy_sq_out_bits
{
6657 u8 reserved_at_8
[0x18];
6661 u8 reserved_at_40
[0x40];
6664 struct mlx5_ifc_destroy_sq_in_bits
{
6668 u8 reserved_at_20
[0x10];
6671 u8 reserved_at_40
[0x8];
6674 u8 reserved_at_60
[0x20];
6677 struct mlx5_ifc_destroy_scheduling_element_out_bits
{
6679 u8 reserved_at_8
[0x18];
6683 u8 reserved_at_40
[0x1c0];
6686 struct mlx5_ifc_destroy_scheduling_element_in_bits
{
6688 u8 reserved_at_10
[0x10];
6690 u8 reserved_at_20
[0x10];
6693 u8 scheduling_hierarchy
[0x8];
6694 u8 reserved_at_48
[0x18];
6696 u8 scheduling_element_id
[0x20];
6698 u8 reserved_at_80
[0x180];
6701 struct mlx5_ifc_destroy_rqt_out_bits
{
6703 u8 reserved_at_8
[0x18];
6707 u8 reserved_at_40
[0x40];
6710 struct mlx5_ifc_destroy_rqt_in_bits
{
6714 u8 reserved_at_20
[0x10];
6717 u8 reserved_at_40
[0x8];
6720 u8 reserved_at_60
[0x20];
6723 struct mlx5_ifc_destroy_rq_out_bits
{
6725 u8 reserved_at_8
[0x18];
6729 u8 reserved_at_40
[0x40];
6732 struct mlx5_ifc_destroy_rq_in_bits
{
6736 u8 reserved_at_20
[0x10];
6739 u8 reserved_at_40
[0x8];
6742 u8 reserved_at_60
[0x20];
6745 struct mlx5_ifc_set_delay_drop_params_in_bits
{
6747 u8 reserved_at_10
[0x10];
6749 u8 reserved_at_20
[0x10];
6752 u8 reserved_at_40
[0x20];
6754 u8 reserved_at_60
[0x10];
6755 u8 delay_drop_timeout
[0x10];
6758 struct mlx5_ifc_set_delay_drop_params_out_bits
{
6760 u8 reserved_at_8
[0x18];
6764 u8 reserved_at_40
[0x40];
6767 struct mlx5_ifc_destroy_rmp_out_bits
{
6769 u8 reserved_at_8
[0x18];
6773 u8 reserved_at_40
[0x40];
6776 struct mlx5_ifc_destroy_rmp_in_bits
{
6780 u8 reserved_at_20
[0x10];
6783 u8 reserved_at_40
[0x8];
6786 u8 reserved_at_60
[0x20];
6789 struct mlx5_ifc_destroy_qp_out_bits
{
6791 u8 reserved_at_8
[0x18];
6795 u8 reserved_at_40
[0x40];
6798 struct mlx5_ifc_destroy_qp_in_bits
{
6802 u8 reserved_at_20
[0x10];
6805 u8 reserved_at_40
[0x8];
6808 u8 reserved_at_60
[0x20];
6811 struct mlx5_ifc_destroy_psv_out_bits
{
6813 u8 reserved_at_8
[0x18];
6817 u8 reserved_at_40
[0x40];
6820 struct mlx5_ifc_destroy_psv_in_bits
{
6822 u8 reserved_at_10
[0x10];
6824 u8 reserved_at_20
[0x10];
6827 u8 reserved_at_40
[0x8];
6830 u8 reserved_at_60
[0x20];
6833 struct mlx5_ifc_destroy_mkey_out_bits
{
6835 u8 reserved_at_8
[0x18];
6839 u8 reserved_at_40
[0x40];
6842 struct mlx5_ifc_destroy_mkey_in_bits
{
6844 u8 reserved_at_10
[0x10];
6846 u8 reserved_at_20
[0x10];
6849 u8 reserved_at_40
[0x8];
6850 u8 mkey_index
[0x18];
6852 u8 reserved_at_60
[0x20];
6855 struct mlx5_ifc_destroy_flow_table_out_bits
{
6857 u8 reserved_at_8
[0x18];
6861 u8 reserved_at_40
[0x40];
6864 struct mlx5_ifc_destroy_flow_table_in_bits
{
6866 u8 reserved_at_10
[0x10];
6868 u8 reserved_at_20
[0x10];
6871 u8 other_vport
[0x1];
6872 u8 reserved_at_41
[0xf];
6873 u8 vport_number
[0x10];
6875 u8 reserved_at_60
[0x20];
6878 u8 reserved_at_88
[0x18];
6880 u8 reserved_at_a0
[0x8];
6883 u8 reserved_at_c0
[0x140];
6886 struct mlx5_ifc_destroy_flow_group_out_bits
{
6888 u8 reserved_at_8
[0x18];
6892 u8 reserved_at_40
[0x40];
6895 struct mlx5_ifc_destroy_flow_group_in_bits
{
6897 u8 reserved_at_10
[0x10];
6899 u8 reserved_at_20
[0x10];
6902 u8 other_vport
[0x1];
6903 u8 reserved_at_41
[0xf];
6904 u8 vport_number
[0x10];
6906 u8 reserved_at_60
[0x20];
6909 u8 reserved_at_88
[0x18];
6911 u8 reserved_at_a0
[0x8];
6916 u8 reserved_at_e0
[0x120];
6919 struct mlx5_ifc_destroy_eq_out_bits
{
6921 u8 reserved_at_8
[0x18];
6925 u8 reserved_at_40
[0x40];
6928 struct mlx5_ifc_destroy_eq_in_bits
{
6930 u8 reserved_at_10
[0x10];
6932 u8 reserved_at_20
[0x10];
6935 u8 reserved_at_40
[0x18];
6938 u8 reserved_at_60
[0x20];
6941 struct mlx5_ifc_destroy_dct_out_bits
{
6943 u8 reserved_at_8
[0x18];
6947 u8 reserved_at_40
[0x40];
6950 struct mlx5_ifc_destroy_dct_in_bits
{
6954 u8 reserved_at_20
[0x10];
6957 u8 reserved_at_40
[0x8];
6960 u8 reserved_at_60
[0x20];
6963 struct mlx5_ifc_destroy_cq_out_bits
{
6965 u8 reserved_at_8
[0x18];
6969 u8 reserved_at_40
[0x40];
6972 struct mlx5_ifc_destroy_cq_in_bits
{
6976 u8 reserved_at_20
[0x10];
6979 u8 reserved_at_40
[0x8];
6982 u8 reserved_at_60
[0x20];
6985 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits
{
6987 u8 reserved_at_8
[0x18];
6991 u8 reserved_at_40
[0x40];
6994 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits
{
6996 u8 reserved_at_10
[0x10];
6998 u8 reserved_at_20
[0x10];
7001 u8 reserved_at_40
[0x20];
7003 u8 reserved_at_60
[0x10];
7004 u8 vxlan_udp_port
[0x10];
7007 struct mlx5_ifc_delete_l2_table_entry_out_bits
{
7009 u8 reserved_at_8
[0x18];
7013 u8 reserved_at_40
[0x40];
7016 struct mlx5_ifc_delete_l2_table_entry_in_bits
{
7018 u8 reserved_at_10
[0x10];
7020 u8 reserved_at_20
[0x10];
7023 u8 reserved_at_40
[0x60];
7025 u8 reserved_at_a0
[0x8];
7026 u8 table_index
[0x18];
7028 u8 reserved_at_c0
[0x140];
7031 struct mlx5_ifc_delete_fte_out_bits
{
7033 u8 reserved_at_8
[0x18];
7037 u8 reserved_at_40
[0x40];
7040 struct mlx5_ifc_delete_fte_in_bits
{
7042 u8 reserved_at_10
[0x10];
7044 u8 reserved_at_20
[0x10];
7047 u8 other_vport
[0x1];
7048 u8 reserved_at_41
[0xf];
7049 u8 vport_number
[0x10];
7051 u8 reserved_at_60
[0x20];
7054 u8 reserved_at_88
[0x18];
7056 u8 reserved_at_a0
[0x8];
7059 u8 reserved_at_c0
[0x40];
7061 u8 flow_index
[0x20];
7063 u8 reserved_at_120
[0xe0];
7066 struct mlx5_ifc_dealloc_xrcd_out_bits
{
7068 u8 reserved_at_8
[0x18];
7072 u8 reserved_at_40
[0x40];
7075 struct mlx5_ifc_dealloc_xrcd_in_bits
{
7079 u8 reserved_at_20
[0x10];
7082 u8 reserved_at_40
[0x8];
7085 u8 reserved_at_60
[0x20];
7088 struct mlx5_ifc_dealloc_uar_out_bits
{
7090 u8 reserved_at_8
[0x18];
7094 u8 reserved_at_40
[0x40];
7097 struct mlx5_ifc_dealloc_uar_in_bits
{
7099 u8 reserved_at_10
[0x10];
7101 u8 reserved_at_20
[0x10];
7104 u8 reserved_at_40
[0x8];
7107 u8 reserved_at_60
[0x20];
7110 struct mlx5_ifc_dealloc_transport_domain_out_bits
{
7112 u8 reserved_at_8
[0x18];
7116 u8 reserved_at_40
[0x40];
7119 struct mlx5_ifc_dealloc_transport_domain_in_bits
{
7123 u8 reserved_at_20
[0x10];
7126 u8 reserved_at_40
[0x8];
7127 u8 transport_domain
[0x18];
7129 u8 reserved_at_60
[0x20];
7132 struct mlx5_ifc_dealloc_q_counter_out_bits
{
7134 u8 reserved_at_8
[0x18];
7138 u8 reserved_at_40
[0x40];
7141 struct mlx5_ifc_dealloc_q_counter_in_bits
{
7143 u8 reserved_at_10
[0x10];
7145 u8 reserved_at_20
[0x10];
7148 u8 reserved_at_40
[0x18];
7149 u8 counter_set_id
[0x8];
7151 u8 reserved_at_60
[0x20];
7154 struct mlx5_ifc_dealloc_pd_out_bits
{
7156 u8 reserved_at_8
[0x18];
7160 u8 reserved_at_40
[0x40];
7163 struct mlx5_ifc_dealloc_pd_in_bits
{
7167 u8 reserved_at_20
[0x10];
7170 u8 reserved_at_40
[0x8];
7173 u8 reserved_at_60
[0x20];
7176 struct mlx5_ifc_dealloc_flow_counter_out_bits
{
7178 u8 reserved_at_8
[0x18];
7182 u8 reserved_at_40
[0x40];
7185 struct mlx5_ifc_dealloc_flow_counter_in_bits
{
7187 u8 reserved_at_10
[0x10];
7189 u8 reserved_at_20
[0x10];
7192 u8 flow_counter_id
[0x20];
7194 u8 reserved_at_60
[0x20];
7197 struct mlx5_ifc_create_xrq_out_bits
{
7199 u8 reserved_at_8
[0x18];
7203 u8 reserved_at_40
[0x8];
7206 u8 reserved_at_60
[0x20];
7209 struct mlx5_ifc_create_xrq_in_bits
{
7213 u8 reserved_at_20
[0x10];
7216 u8 reserved_at_40
[0x40];
7218 struct mlx5_ifc_xrqc_bits xrq_context
;
7221 struct mlx5_ifc_create_xrc_srq_out_bits
{
7223 u8 reserved_at_8
[0x18];
7227 u8 reserved_at_40
[0x8];
7230 u8 reserved_at_60
[0x20];
7233 struct mlx5_ifc_create_xrc_srq_in_bits
{
7237 u8 reserved_at_20
[0x10];
7240 u8 reserved_at_40
[0x40];
7242 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry
;
7244 u8 reserved_at_280
[0x60];
7246 u8 xrc_srq_umem_valid
[0x1];
7247 u8 reserved_at_2e1
[0x1f];
7249 u8 reserved_at_300
[0x580];
7254 struct mlx5_ifc_create_tis_out_bits
{
7256 u8 reserved_at_8
[0x18];
7260 u8 reserved_at_40
[0x8];
7263 u8 reserved_at_60
[0x20];
7266 struct mlx5_ifc_create_tis_in_bits
{
7270 u8 reserved_at_20
[0x10];
7273 u8 reserved_at_40
[0xc0];
7275 struct mlx5_ifc_tisc_bits ctx
;
7278 struct mlx5_ifc_create_tir_out_bits
{
7280 u8 icm_address_63_40
[0x18];
7284 u8 icm_address_39_32
[0x8];
7287 u8 icm_address_31_0
[0x20];
7290 struct mlx5_ifc_create_tir_in_bits
{
7294 u8 reserved_at_20
[0x10];
7297 u8 reserved_at_40
[0xc0];
7299 struct mlx5_ifc_tirc_bits ctx
;
7302 struct mlx5_ifc_create_srq_out_bits
{
7304 u8 reserved_at_8
[0x18];
7308 u8 reserved_at_40
[0x8];
7311 u8 reserved_at_60
[0x20];
7314 struct mlx5_ifc_create_srq_in_bits
{
7318 u8 reserved_at_20
[0x10];
7321 u8 reserved_at_40
[0x40];
7323 struct mlx5_ifc_srqc_bits srq_context_entry
;
7325 u8 reserved_at_280
[0x600];
7330 struct mlx5_ifc_create_sq_out_bits
{
7332 u8 reserved_at_8
[0x18];
7336 u8 reserved_at_40
[0x8];
7339 u8 reserved_at_60
[0x20];
7342 struct mlx5_ifc_create_sq_in_bits
{
7346 u8 reserved_at_20
[0x10];
7349 u8 reserved_at_40
[0xc0];
7351 struct mlx5_ifc_sqc_bits ctx
;
7354 struct mlx5_ifc_create_scheduling_element_out_bits
{
7356 u8 reserved_at_8
[0x18];
7360 u8 reserved_at_40
[0x40];
7362 u8 scheduling_element_id
[0x20];
7364 u8 reserved_at_a0
[0x160];
7367 struct mlx5_ifc_create_scheduling_element_in_bits
{
7369 u8 reserved_at_10
[0x10];
7371 u8 reserved_at_20
[0x10];
7374 u8 scheduling_hierarchy
[0x8];
7375 u8 reserved_at_48
[0x18];
7377 u8 reserved_at_60
[0xa0];
7379 struct mlx5_ifc_scheduling_context_bits scheduling_context
;
7381 u8 reserved_at_300
[0x100];
7384 struct mlx5_ifc_create_rqt_out_bits
{
7386 u8 reserved_at_8
[0x18];
7390 u8 reserved_at_40
[0x8];
7393 u8 reserved_at_60
[0x20];
7396 struct mlx5_ifc_create_rqt_in_bits
{
7400 u8 reserved_at_20
[0x10];
7403 u8 reserved_at_40
[0xc0];
7405 struct mlx5_ifc_rqtc_bits rqt_context
;
7408 struct mlx5_ifc_create_rq_out_bits
{
7410 u8 reserved_at_8
[0x18];
7414 u8 reserved_at_40
[0x8];
7417 u8 reserved_at_60
[0x20];
7420 struct mlx5_ifc_create_rq_in_bits
{
7424 u8 reserved_at_20
[0x10];
7427 u8 reserved_at_40
[0xc0];
7429 struct mlx5_ifc_rqc_bits ctx
;
7432 struct mlx5_ifc_create_rmp_out_bits
{
7434 u8 reserved_at_8
[0x18];
7438 u8 reserved_at_40
[0x8];
7441 u8 reserved_at_60
[0x20];
7444 struct mlx5_ifc_create_rmp_in_bits
{
7448 u8 reserved_at_20
[0x10];
7451 u8 reserved_at_40
[0xc0];
7453 struct mlx5_ifc_rmpc_bits ctx
;
7456 struct mlx5_ifc_create_qp_out_bits
{
7458 u8 reserved_at_8
[0x18];
7462 u8 reserved_at_40
[0x8];
7465 u8 reserved_at_60
[0x20];
7468 struct mlx5_ifc_create_qp_in_bits
{
7472 u8 reserved_at_20
[0x10];
7475 u8 reserved_at_40
[0x40];
7477 u8 opt_param_mask
[0x20];
7479 u8 reserved_at_a0
[0x20];
7481 struct mlx5_ifc_qpc_bits qpc
;
7483 u8 reserved_at_800
[0x60];
7485 u8 wq_umem_valid
[0x1];
7486 u8 reserved_at_861
[0x1f];
7491 struct mlx5_ifc_create_psv_out_bits
{
7493 u8 reserved_at_8
[0x18];
7497 u8 reserved_at_40
[0x40];
7499 u8 reserved_at_80
[0x8];
7500 u8 psv0_index
[0x18];
7502 u8 reserved_at_a0
[0x8];
7503 u8 psv1_index
[0x18];
7505 u8 reserved_at_c0
[0x8];
7506 u8 psv2_index
[0x18];
7508 u8 reserved_at_e0
[0x8];
7509 u8 psv3_index
[0x18];
7512 struct mlx5_ifc_create_psv_in_bits
{
7514 u8 reserved_at_10
[0x10];
7516 u8 reserved_at_20
[0x10];
7520 u8 reserved_at_44
[0x4];
7523 u8 reserved_at_60
[0x20];
7526 struct mlx5_ifc_create_mkey_out_bits
{
7528 u8 reserved_at_8
[0x18];
7532 u8 reserved_at_40
[0x8];
7533 u8 mkey_index
[0x18];
7535 u8 reserved_at_60
[0x20];
7538 struct mlx5_ifc_create_mkey_in_bits
{
7540 u8 reserved_at_10
[0x10];
7542 u8 reserved_at_20
[0x10];
7545 u8 reserved_at_40
[0x20];
7548 u8 mkey_umem_valid
[0x1];
7549 u8 reserved_at_62
[0x1e];
7551 struct mlx5_ifc_mkc_bits memory_key_mkey_entry
;
7553 u8 reserved_at_280
[0x80];
7555 u8 translations_octword_actual_size
[0x20];
7557 u8 reserved_at_320
[0x560];
7559 u8 klm_pas_mtt
[0][0x20];
7563 MLX5_FLOW_TABLE_TYPE_NIC_RX
= 0x0,
7564 MLX5_FLOW_TABLE_TYPE_NIC_TX
= 0x1,
7565 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL
= 0x2,
7566 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL
= 0x3,
7567 MLX5_FLOW_TABLE_TYPE_FDB
= 0X4,
7568 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX
= 0X5,
7569 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX
= 0X6,
7572 struct mlx5_ifc_create_flow_table_out_bits
{
7574 u8 icm_address_63_40
[0x18];
7578 u8 icm_address_39_32
[0x8];
7581 u8 icm_address_31_0
[0x20];
7584 struct mlx5_ifc_create_flow_table_in_bits
{
7586 u8 reserved_at_10
[0x10];
7588 u8 reserved_at_20
[0x10];
7591 u8 other_vport
[0x1];
7592 u8 reserved_at_41
[0xf];
7593 u8 vport_number
[0x10];
7595 u8 reserved_at_60
[0x20];
7598 u8 reserved_at_88
[0x18];
7600 u8 reserved_at_a0
[0x20];
7602 struct mlx5_ifc_flow_table_context_bits flow_table_context
;
7605 struct mlx5_ifc_create_flow_group_out_bits
{
7607 u8 reserved_at_8
[0x18];
7611 u8 reserved_at_40
[0x8];
7614 u8 reserved_at_60
[0x20];
7618 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS
= 0x0,
7619 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS
= 0x1,
7620 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS
= 0x2,
7621 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2
= 0x3,
7624 struct mlx5_ifc_create_flow_group_in_bits
{
7626 u8 reserved_at_10
[0x10];
7628 u8 reserved_at_20
[0x10];
7631 u8 other_vport
[0x1];
7632 u8 reserved_at_41
[0xf];
7633 u8 vport_number
[0x10];
7635 u8 reserved_at_60
[0x20];
7638 u8 reserved_at_88
[0x18];
7640 u8 reserved_at_a0
[0x8];
7643 u8 source_eswitch_owner_vhca_id_valid
[0x1];
7645 u8 reserved_at_c1
[0x1f];
7647 u8 start_flow_index
[0x20];
7649 u8 reserved_at_100
[0x20];
7651 u8 end_flow_index
[0x20];
7653 u8 reserved_at_140
[0xa0];
7655 u8 reserved_at_1e0
[0x18];
7656 u8 match_criteria_enable
[0x8];
7658 struct mlx5_ifc_fte_match_param_bits match_criteria
;
7660 u8 reserved_at_1200
[0xe00];
7663 struct mlx5_ifc_create_eq_out_bits
{
7665 u8 reserved_at_8
[0x18];
7669 u8 reserved_at_40
[0x18];
7672 u8 reserved_at_60
[0x20];
7675 struct mlx5_ifc_create_eq_in_bits
{
7679 u8 reserved_at_20
[0x10];
7682 u8 reserved_at_40
[0x40];
7684 struct mlx5_ifc_eqc_bits eq_context_entry
;
7686 u8 reserved_at_280
[0x40];
7688 u8 event_bitmask
[4][0x40];
7690 u8 reserved_at_3c0
[0x4c0];
7695 struct mlx5_ifc_create_dct_out_bits
{
7697 u8 reserved_at_8
[0x18];
7701 u8 reserved_at_40
[0x8];
7704 u8 reserved_at_60
[0x20];
7707 struct mlx5_ifc_create_dct_in_bits
{
7711 u8 reserved_at_20
[0x10];
7714 u8 reserved_at_40
[0x40];
7716 struct mlx5_ifc_dctc_bits dct_context_entry
;
7718 u8 reserved_at_280
[0x180];
7721 struct mlx5_ifc_create_cq_out_bits
{
7723 u8 reserved_at_8
[0x18];
7727 u8 reserved_at_40
[0x8];
7730 u8 reserved_at_60
[0x20];
7733 struct mlx5_ifc_create_cq_in_bits
{
7737 u8 reserved_at_20
[0x10];
7740 u8 reserved_at_40
[0x40];
7742 struct mlx5_ifc_cqc_bits cq_context
;
7744 u8 reserved_at_280
[0x60];
7746 u8 cq_umem_valid
[0x1];
7747 u8 reserved_at_2e1
[0x59f];
7752 struct mlx5_ifc_config_int_moderation_out_bits
{
7754 u8 reserved_at_8
[0x18];
7758 u8 reserved_at_40
[0x4];
7760 u8 int_vector
[0x10];
7762 u8 reserved_at_60
[0x20];
7766 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE
= 0x0,
7767 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ
= 0x1,
7770 struct mlx5_ifc_config_int_moderation_in_bits
{
7772 u8 reserved_at_10
[0x10];
7774 u8 reserved_at_20
[0x10];
7777 u8 reserved_at_40
[0x4];
7779 u8 int_vector
[0x10];
7781 u8 reserved_at_60
[0x20];
7784 struct mlx5_ifc_attach_to_mcg_out_bits
{
7786 u8 reserved_at_8
[0x18];
7790 u8 reserved_at_40
[0x40];
7793 struct mlx5_ifc_attach_to_mcg_in_bits
{
7797 u8 reserved_at_20
[0x10];
7800 u8 reserved_at_40
[0x8];
7803 u8 reserved_at_60
[0x20];
7805 u8 multicast_gid
[16][0x8];
7808 struct mlx5_ifc_arm_xrq_out_bits
{
7810 u8 reserved_at_8
[0x18];
7814 u8 reserved_at_40
[0x40];
7817 struct mlx5_ifc_arm_xrq_in_bits
{
7819 u8 reserved_at_10
[0x10];
7821 u8 reserved_at_20
[0x10];
7824 u8 reserved_at_40
[0x8];
7827 u8 reserved_at_60
[0x10];
7831 struct mlx5_ifc_arm_xrc_srq_out_bits
{
7833 u8 reserved_at_8
[0x18];
7837 u8 reserved_at_40
[0x40];
7841 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ
= 0x1,
7844 struct mlx5_ifc_arm_xrc_srq_in_bits
{
7848 u8 reserved_at_20
[0x10];
7851 u8 reserved_at_40
[0x8];
7854 u8 reserved_at_60
[0x10];
7858 struct mlx5_ifc_arm_rq_out_bits
{
7860 u8 reserved_at_8
[0x18];
7864 u8 reserved_at_40
[0x40];
7868 MLX5_ARM_RQ_IN_OP_MOD_SRQ
= 0x1,
7869 MLX5_ARM_RQ_IN_OP_MOD_XRQ
= 0x2,
7872 struct mlx5_ifc_arm_rq_in_bits
{
7876 u8 reserved_at_20
[0x10];
7879 u8 reserved_at_40
[0x8];
7880 u8 srq_number
[0x18];
7882 u8 reserved_at_60
[0x10];
7886 struct mlx5_ifc_arm_dct_out_bits
{
7888 u8 reserved_at_8
[0x18];
7892 u8 reserved_at_40
[0x40];
7895 struct mlx5_ifc_arm_dct_in_bits
{
7897 u8 reserved_at_10
[0x10];
7899 u8 reserved_at_20
[0x10];
7902 u8 reserved_at_40
[0x8];
7903 u8 dct_number
[0x18];
7905 u8 reserved_at_60
[0x20];
7908 struct mlx5_ifc_alloc_xrcd_out_bits
{
7910 u8 reserved_at_8
[0x18];
7914 u8 reserved_at_40
[0x8];
7917 u8 reserved_at_60
[0x20];
7920 struct mlx5_ifc_alloc_xrcd_in_bits
{
7924 u8 reserved_at_20
[0x10];
7927 u8 reserved_at_40
[0x40];
7930 struct mlx5_ifc_alloc_uar_out_bits
{
7932 u8 reserved_at_8
[0x18];
7936 u8 reserved_at_40
[0x8];
7939 u8 reserved_at_60
[0x20];
7942 struct mlx5_ifc_alloc_uar_in_bits
{
7944 u8 reserved_at_10
[0x10];
7946 u8 reserved_at_20
[0x10];
7949 u8 reserved_at_40
[0x40];
7952 struct mlx5_ifc_alloc_transport_domain_out_bits
{
7954 u8 reserved_at_8
[0x18];
7958 u8 reserved_at_40
[0x8];
7959 u8 transport_domain
[0x18];
7961 u8 reserved_at_60
[0x20];
7964 struct mlx5_ifc_alloc_transport_domain_in_bits
{
7968 u8 reserved_at_20
[0x10];
7971 u8 reserved_at_40
[0x40];
7974 struct mlx5_ifc_alloc_q_counter_out_bits
{
7976 u8 reserved_at_8
[0x18];
7980 u8 reserved_at_40
[0x18];
7981 u8 counter_set_id
[0x8];
7983 u8 reserved_at_60
[0x20];
7986 struct mlx5_ifc_alloc_q_counter_in_bits
{
7990 u8 reserved_at_20
[0x10];
7993 u8 reserved_at_40
[0x40];
7996 struct mlx5_ifc_alloc_pd_out_bits
{
7998 u8 reserved_at_8
[0x18];
8002 u8 reserved_at_40
[0x8];
8005 u8 reserved_at_60
[0x20];
8008 struct mlx5_ifc_alloc_pd_in_bits
{
8012 u8 reserved_at_20
[0x10];
8015 u8 reserved_at_40
[0x40];
8018 struct mlx5_ifc_alloc_flow_counter_out_bits
{
8020 u8 reserved_at_8
[0x18];
8024 u8 flow_counter_id
[0x20];
8026 u8 reserved_at_60
[0x20];
8029 struct mlx5_ifc_alloc_flow_counter_in_bits
{
8031 u8 reserved_at_10
[0x10];
8033 u8 reserved_at_20
[0x10];
8036 u8 reserved_at_40
[0x38];
8037 u8 flow_counter_bulk
[0x8];
8040 struct mlx5_ifc_add_vxlan_udp_dport_out_bits
{
8042 u8 reserved_at_8
[0x18];
8046 u8 reserved_at_40
[0x40];
8049 struct mlx5_ifc_add_vxlan_udp_dport_in_bits
{
8051 u8 reserved_at_10
[0x10];
8053 u8 reserved_at_20
[0x10];
8056 u8 reserved_at_40
[0x20];
8058 u8 reserved_at_60
[0x10];
8059 u8 vxlan_udp_port
[0x10];
8062 struct mlx5_ifc_set_pp_rate_limit_out_bits
{
8064 u8 reserved_at_8
[0x18];
8068 u8 reserved_at_40
[0x40];
8071 struct mlx5_ifc_set_pp_rate_limit_in_bits
{
8073 u8 reserved_at_10
[0x10];
8075 u8 reserved_at_20
[0x10];
8078 u8 reserved_at_40
[0x10];
8079 u8 rate_limit_index
[0x10];
8081 u8 reserved_at_60
[0x20];
8083 u8 rate_limit
[0x20];
8085 u8 burst_upper_bound
[0x20];
8087 u8 reserved_at_c0
[0x10];
8088 u8 typical_packet_size
[0x10];
8090 u8 reserved_at_e0
[0x120];
8093 struct mlx5_ifc_access_register_out_bits
{
8095 u8 reserved_at_8
[0x18];
8099 u8 reserved_at_40
[0x40];
8101 u8 register_data
[0][0x20];
8105 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE
= 0x0,
8106 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ
= 0x1,
8109 struct mlx5_ifc_access_register_in_bits
{
8111 u8 reserved_at_10
[0x10];
8113 u8 reserved_at_20
[0x10];
8116 u8 reserved_at_40
[0x10];
8117 u8 register_id
[0x10];
8121 u8 register_data
[0][0x20];
8124 struct mlx5_ifc_sltp_reg_bits
{
8129 u8 reserved_at_12
[0x2];
8131 u8 reserved_at_18
[0x8];
8133 u8 reserved_at_20
[0x20];
8135 u8 reserved_at_40
[0x7];
8141 u8 reserved_at_60
[0xc];
8142 u8 ob_preemp_mode
[0x4];
8146 u8 reserved_at_80
[0x20];
8149 struct mlx5_ifc_slrg_reg_bits
{
8154 u8 reserved_at_12
[0x2];
8156 u8 reserved_at_18
[0x8];
8158 u8 time_to_link_up
[0x10];
8159 u8 reserved_at_30
[0xc];
8160 u8 grade_lane_speed
[0x4];
8162 u8 grade_version
[0x8];
8165 u8 reserved_at_60
[0x4];
8166 u8 height_grade_type
[0x4];
8167 u8 height_grade
[0x18];
8172 u8 reserved_at_a0
[0x10];
8173 u8 height_sigma
[0x10];
8175 u8 reserved_at_c0
[0x20];
8177 u8 reserved_at_e0
[0x4];
8178 u8 phase_grade_type
[0x4];
8179 u8 phase_grade
[0x18];
8181 u8 reserved_at_100
[0x8];
8182 u8 phase_eo_pos
[0x8];
8183 u8 reserved_at_110
[0x8];
8184 u8 phase_eo_neg
[0x8];
8186 u8 ffe_set_tested
[0x10];
8187 u8 test_errors_per_lane
[0x10];
8190 struct mlx5_ifc_pvlc_reg_bits
{
8191 u8 reserved_at_0
[0x8];
8193 u8 reserved_at_10
[0x10];
8195 u8 reserved_at_20
[0x1c];
8198 u8 reserved_at_40
[0x1c];
8201 u8 reserved_at_60
[0x1c];
8202 u8 vl_operational
[0x4];
8205 struct mlx5_ifc_pude_reg_bits
{
8208 u8 reserved_at_10
[0x4];
8209 u8 admin_status
[0x4];
8210 u8 reserved_at_18
[0x4];
8211 u8 oper_status
[0x4];
8213 u8 reserved_at_20
[0x60];
8216 struct mlx5_ifc_ptys_reg_bits
{
8217 u8 reserved_at_0
[0x1];
8218 u8 an_disable_admin
[0x1];
8219 u8 an_disable_cap
[0x1];
8220 u8 reserved_at_3
[0x5];
8222 u8 reserved_at_10
[0xd];
8226 u8 reserved_at_24
[0x1c];
8228 u8 ext_eth_proto_capability
[0x20];
8230 u8 eth_proto_capability
[0x20];
8232 u8 ib_link_width_capability
[0x10];
8233 u8 ib_proto_capability
[0x10];
8235 u8 ext_eth_proto_admin
[0x20];
8237 u8 eth_proto_admin
[0x20];
8239 u8 ib_link_width_admin
[0x10];
8240 u8 ib_proto_admin
[0x10];
8242 u8 ext_eth_proto_oper
[0x20];
8244 u8 eth_proto_oper
[0x20];
8246 u8 ib_link_width_oper
[0x10];
8247 u8 ib_proto_oper
[0x10];
8249 u8 reserved_at_160
[0x1c];
8250 u8 connector_type
[0x4];
8252 u8 eth_proto_lp_advertise
[0x20];
8254 u8 reserved_at_1a0
[0x60];
8257 struct mlx5_ifc_mlcr_reg_bits
{
8258 u8 reserved_at_0
[0x8];
8260 u8 reserved_at_10
[0x20];
8262 u8 beacon_duration
[0x10];
8263 u8 reserved_at_40
[0x10];
8265 u8 beacon_remain
[0x10];
8268 struct mlx5_ifc_ptas_reg_bits
{
8269 u8 reserved_at_0
[0x20];
8271 u8 algorithm_options
[0x10];
8272 u8 reserved_at_30
[0x4];
8273 u8 repetitions_mode
[0x4];
8274 u8 num_of_repetitions
[0x8];
8276 u8 grade_version
[0x8];
8277 u8 height_grade_type
[0x4];
8278 u8 phase_grade_type
[0x4];
8279 u8 height_grade_weight
[0x8];
8280 u8 phase_grade_weight
[0x8];
8282 u8 gisim_measure_bits
[0x10];
8283 u8 adaptive_tap_measure_bits
[0x10];
8285 u8 ber_bath_high_error_threshold
[0x10];
8286 u8 ber_bath_mid_error_threshold
[0x10];
8288 u8 ber_bath_low_error_threshold
[0x10];
8289 u8 one_ratio_high_threshold
[0x10];
8291 u8 one_ratio_high_mid_threshold
[0x10];
8292 u8 one_ratio_low_mid_threshold
[0x10];
8294 u8 one_ratio_low_threshold
[0x10];
8295 u8 ndeo_error_threshold
[0x10];
8297 u8 mixer_offset_step_size
[0x10];
8298 u8 reserved_at_110
[0x8];
8299 u8 mix90_phase_for_voltage_bath
[0x8];
8301 u8 mixer_offset_start
[0x10];
8302 u8 mixer_offset_end
[0x10];
8304 u8 reserved_at_140
[0x15];
8305 u8 ber_test_time
[0xb];
8308 struct mlx5_ifc_pspa_reg_bits
{
8312 u8 reserved_at_18
[0x8];
8314 u8 reserved_at_20
[0x20];
8317 struct mlx5_ifc_pqdr_reg_bits
{
8318 u8 reserved_at_0
[0x8];
8320 u8 reserved_at_10
[0x5];
8322 u8 reserved_at_18
[0x6];
8325 u8 reserved_at_20
[0x20];
8327 u8 reserved_at_40
[0x10];
8328 u8 min_threshold
[0x10];
8330 u8 reserved_at_60
[0x10];
8331 u8 max_threshold
[0x10];
8333 u8 reserved_at_80
[0x10];
8334 u8 mark_probability_denominator
[0x10];
8336 u8 reserved_at_a0
[0x60];
8339 struct mlx5_ifc_ppsc_reg_bits
{
8340 u8 reserved_at_0
[0x8];
8342 u8 reserved_at_10
[0x10];
8344 u8 reserved_at_20
[0x60];
8346 u8 reserved_at_80
[0x1c];
8349 u8 reserved_at_a0
[0x1c];
8350 u8 wrps_status
[0x4];
8352 u8 reserved_at_c0
[0x8];
8353 u8 up_threshold
[0x8];
8354 u8 reserved_at_d0
[0x8];
8355 u8 down_threshold
[0x8];
8357 u8 reserved_at_e0
[0x20];
8359 u8 reserved_at_100
[0x1c];
8362 u8 reserved_at_120
[0x1c];
8363 u8 srps_status
[0x4];
8365 u8 reserved_at_140
[0x40];
8368 struct mlx5_ifc_pplr_reg_bits
{
8369 u8 reserved_at_0
[0x8];
8371 u8 reserved_at_10
[0x10];
8373 u8 reserved_at_20
[0x8];
8375 u8 reserved_at_30
[0x8];
8379 struct mlx5_ifc_pplm_reg_bits
{
8380 u8 reserved_at_0
[0x8];
8382 u8 reserved_at_10
[0x10];
8384 u8 reserved_at_20
[0x20];
8386 u8 port_profile_mode
[0x8];
8387 u8 static_port_profile
[0x8];
8388 u8 active_port_profile
[0x8];
8389 u8 reserved_at_58
[0x8];
8391 u8 retransmission_active
[0x8];
8392 u8 fec_mode_active
[0x18];
8394 u8 rs_fec_correction_bypass_cap
[0x4];
8395 u8 reserved_at_84
[0x8];
8396 u8 fec_override_cap_56g
[0x4];
8397 u8 fec_override_cap_100g
[0x4];
8398 u8 fec_override_cap_50g
[0x4];
8399 u8 fec_override_cap_25g
[0x4];
8400 u8 fec_override_cap_10g_40g
[0x4];
8402 u8 rs_fec_correction_bypass_admin
[0x4];
8403 u8 reserved_at_a4
[0x8];
8404 u8 fec_override_admin_56g
[0x4];
8405 u8 fec_override_admin_100g
[0x4];
8406 u8 fec_override_admin_50g
[0x4];
8407 u8 fec_override_admin_25g
[0x4];
8408 u8 fec_override_admin_10g_40g
[0x4];
8411 struct mlx5_ifc_ppcnt_reg_bits
{
8415 u8 reserved_at_12
[0x8];
8419 u8 reserved_at_21
[0x1c];
8422 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set
;
8425 struct mlx5_ifc_mpein_reg_bits
{
8426 u8 reserved_at_0
[0x2];
8430 u8 reserved_at_18
[0x8];
8432 u8 capability_mask
[0x20];
8434 u8 reserved_at_40
[0x8];
8435 u8 link_width_enabled
[0x8];
8436 u8 link_speed_enabled
[0x10];
8438 u8 lane0_physical_position
[0x8];
8439 u8 link_width_active
[0x8];
8440 u8 link_speed_active
[0x10];
8442 u8 num_of_pfs
[0x10];
8443 u8 num_of_vfs
[0x10];
8446 u8 reserved_at_b0
[0x10];
8448 u8 max_read_request_size
[0x4];
8449 u8 max_payload_size
[0x4];
8450 u8 reserved_at_c8
[0x5];
8453 u8 reserved_at_d4
[0xb];
8454 u8 lane_reversal
[0x1];
8456 u8 reserved_at_e0
[0x14];
8459 u8 reserved_at_100
[0x20];
8461 u8 device_status
[0x10];
8463 u8 reserved_at_138
[0x8];
8465 u8 reserved_at_140
[0x10];
8466 u8 receiver_detect_result
[0x10];
8468 u8 reserved_at_160
[0x20];
8471 struct mlx5_ifc_mpcnt_reg_bits
{
8472 u8 reserved_at_0
[0x8];
8474 u8 reserved_at_10
[0xa];
8478 u8 reserved_at_21
[0x1f];
8480 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set
;
8483 struct mlx5_ifc_ppad_reg_bits
{
8484 u8 reserved_at_0
[0x3];
8486 u8 reserved_at_4
[0x4];
8492 u8 reserved_at_40
[0x40];
8495 struct mlx5_ifc_pmtu_reg_bits
{
8496 u8 reserved_at_0
[0x8];
8498 u8 reserved_at_10
[0x10];
8501 u8 reserved_at_30
[0x10];
8504 u8 reserved_at_50
[0x10];
8507 u8 reserved_at_70
[0x10];
8510 struct mlx5_ifc_pmpr_reg_bits
{
8511 u8 reserved_at_0
[0x8];
8513 u8 reserved_at_10
[0x10];
8515 u8 reserved_at_20
[0x18];
8516 u8 attenuation_5g
[0x8];
8518 u8 reserved_at_40
[0x18];
8519 u8 attenuation_7g
[0x8];
8521 u8 reserved_at_60
[0x18];
8522 u8 attenuation_12g
[0x8];
8525 struct mlx5_ifc_pmpe_reg_bits
{
8526 u8 reserved_at_0
[0x8];
8528 u8 reserved_at_10
[0xc];
8529 u8 module_status
[0x4];
8531 u8 reserved_at_20
[0x60];
8534 struct mlx5_ifc_pmpc_reg_bits
{
8535 u8 module_state_updated
[32][0x8];
8538 struct mlx5_ifc_pmlpn_reg_bits
{
8539 u8 reserved_at_0
[0x4];
8540 u8 mlpn_status
[0x4];
8542 u8 reserved_at_10
[0x10];
8545 u8 reserved_at_21
[0x1f];
8548 struct mlx5_ifc_pmlp_reg_bits
{
8550 u8 reserved_at_1
[0x7];
8552 u8 reserved_at_10
[0x8];
8555 u8 lane0_module_mapping
[0x20];
8557 u8 lane1_module_mapping
[0x20];
8559 u8 lane2_module_mapping
[0x20];
8561 u8 lane3_module_mapping
[0x20];
8563 u8 reserved_at_a0
[0x160];
8566 struct mlx5_ifc_pmaos_reg_bits
{
8567 u8 reserved_at_0
[0x8];
8569 u8 reserved_at_10
[0x4];
8570 u8 admin_status
[0x4];
8571 u8 reserved_at_18
[0x4];
8572 u8 oper_status
[0x4];
8576 u8 reserved_at_22
[0x1c];
8579 u8 reserved_at_40
[0x40];
8582 struct mlx5_ifc_plpc_reg_bits
{
8583 u8 reserved_at_0
[0x4];
8585 u8 reserved_at_10
[0x4];
8587 u8 reserved_at_18
[0x8];
8589 u8 reserved_at_20
[0x10];
8590 u8 lane_speed
[0x10];
8592 u8 reserved_at_40
[0x17];
8594 u8 fec_mode_policy
[0x8];
8596 u8 retransmission_capability
[0x8];
8597 u8 fec_mode_capability
[0x18];
8599 u8 retransmission_support_admin
[0x8];
8600 u8 fec_mode_support_admin
[0x18];
8602 u8 retransmission_request_admin
[0x8];
8603 u8 fec_mode_request_admin
[0x18];
8605 u8 reserved_at_c0
[0x80];
8608 struct mlx5_ifc_plib_reg_bits
{
8609 u8 reserved_at_0
[0x8];
8611 u8 reserved_at_10
[0x8];
8614 u8 reserved_at_20
[0x60];
8617 struct mlx5_ifc_plbf_reg_bits
{
8618 u8 reserved_at_0
[0x8];
8620 u8 reserved_at_10
[0xd];
8623 u8 reserved_at_20
[0x20];
8626 struct mlx5_ifc_pipg_reg_bits
{
8627 u8 reserved_at_0
[0x8];
8629 u8 reserved_at_10
[0x10];
8632 u8 reserved_at_21
[0x19];
8634 u8 reserved_at_3e
[0x2];
8637 struct mlx5_ifc_pifr_reg_bits
{
8638 u8 reserved_at_0
[0x8];
8640 u8 reserved_at_10
[0x10];
8642 u8 reserved_at_20
[0xe0];
8644 u8 port_filter
[8][0x20];
8646 u8 port_filter_update_en
[8][0x20];
8649 struct mlx5_ifc_pfcc_reg_bits
{
8650 u8 reserved_at_0
[0x8];
8652 u8 reserved_at_10
[0xb];
8653 u8 ppan_mask_n
[0x1];
8654 u8 minor_stall_mask
[0x1];
8655 u8 critical_stall_mask
[0x1];
8656 u8 reserved_at_1e
[0x2];
8659 u8 reserved_at_24
[0x4];
8660 u8 prio_mask_tx
[0x8];
8661 u8 reserved_at_30
[0x8];
8662 u8 prio_mask_rx
[0x8];
8666 u8 pptx_mask_n
[0x1];
8667 u8 reserved_at_43
[0x5];
8669 u8 reserved_at_50
[0x10];
8673 u8 pprx_mask_n
[0x1];
8674 u8 reserved_at_63
[0x5];
8676 u8 reserved_at_70
[0x10];
8678 u8 device_stall_minor_watermark
[0x10];
8679 u8 device_stall_critical_watermark
[0x10];
8681 u8 reserved_at_a0
[0x60];
8684 struct mlx5_ifc_pelc_reg_bits
{
8686 u8 reserved_at_4
[0x4];
8688 u8 reserved_at_10
[0x10];
8691 u8 op_capability
[0x8];
8697 u8 capability
[0x40];
8703 u8 reserved_at_140
[0x80];
8706 struct mlx5_ifc_peir_reg_bits
{
8707 u8 reserved_at_0
[0x8];
8709 u8 reserved_at_10
[0x10];
8711 u8 reserved_at_20
[0xc];
8712 u8 error_count
[0x4];
8713 u8 reserved_at_30
[0x10];
8715 u8 reserved_at_40
[0xc];
8717 u8 reserved_at_50
[0x8];
8721 struct mlx5_ifc_mpegc_reg_bits
{
8722 u8 reserved_at_0
[0x30];
8723 u8 field_select
[0x10];
8725 u8 tx_overflow_sense
[0x1];
8728 u8 reserved_at_43
[0x1b];
8729 u8 tx_lossy_overflow_oper
[0x2];
8731 u8 reserved_at_60
[0x100];
8734 struct mlx5_ifc_pcam_enhanced_features_bits
{
8735 u8 reserved_at_0
[0x6d];
8736 u8 rx_icrc_encapsulated_counter
[0x1];
8737 u8 reserved_at_6e
[0x4];
8738 u8 ptys_extended_ethernet
[0x1];
8739 u8 reserved_at_73
[0x3];
8741 u8 reserved_at_77
[0x3];
8742 u8 per_lane_error_counters
[0x1];
8743 u8 rx_buffer_fullness_counters
[0x1];
8744 u8 ptys_connector_type
[0x1];
8745 u8 reserved_at_7d
[0x1];
8746 u8 ppcnt_discard_group
[0x1];
8747 u8 ppcnt_statistical_group
[0x1];
8750 struct mlx5_ifc_pcam_regs_5000_to_507f_bits
{
8751 u8 port_access_reg_cap_mask_127_to_96
[0x20];
8752 u8 port_access_reg_cap_mask_95_to_64
[0x20];
8754 u8 port_access_reg_cap_mask_63_to_36
[0x1c];
8756 u8 port_access_reg_cap_mask_34_to_32
[0x3];
8758 u8 port_access_reg_cap_mask_31_to_13
[0x13];
8761 u8 port_access_reg_cap_mask_10_to_09
[0x2];
8763 u8 port_access_reg_cap_mask_07_to_00
[0x8];
8766 struct mlx5_ifc_pcam_reg_bits
{
8767 u8 reserved_at_0
[0x8];
8768 u8 feature_group
[0x8];
8769 u8 reserved_at_10
[0x8];
8770 u8 access_reg_group
[0x8];
8772 u8 reserved_at_20
[0x20];
8775 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f
;
8776 u8 reserved_at_0
[0x80];
8777 } port_access_reg_cap_mask
;
8779 u8 reserved_at_c0
[0x80];
8782 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features
;
8783 u8 reserved_at_0
[0x80];
8786 u8 reserved_at_1c0
[0xc0];
8789 struct mlx5_ifc_mcam_enhanced_features_bits
{
8790 u8 reserved_at_0
[0x6e];
8791 u8 pci_status_and_power
[0x1];
8792 u8 reserved_at_6f
[0x5];
8793 u8 mark_tx_action_cnp
[0x1];
8794 u8 mark_tx_action_cqe
[0x1];
8795 u8 dynamic_tx_overflow
[0x1];
8796 u8 reserved_at_77
[0x4];
8797 u8 pcie_outbound_stalled
[0x1];
8798 u8 tx_overflow_buffer_pkt
[0x1];
8799 u8 mtpps_enh_out_per_adj
[0x1];
8801 u8 pcie_performance_group
[0x1];
8804 struct mlx5_ifc_mcam_access_reg_bits
{
8805 u8 reserved_at_0
[0x1c];
8811 u8 regs_95_to_87
[0x9];
8813 u8 regs_85_to_68
[0x12];
8814 u8 tracer_registers
[0x4];
8816 u8 regs_63_to_32
[0x20];
8817 u8 regs_31_to_0
[0x20];
8820 struct mlx5_ifc_mcam_reg_bits
{
8821 u8 reserved_at_0
[0x8];
8822 u8 feature_group
[0x8];
8823 u8 reserved_at_10
[0x8];
8824 u8 access_reg_group
[0x8];
8826 u8 reserved_at_20
[0x20];
8829 struct mlx5_ifc_mcam_access_reg_bits access_regs
;
8830 u8 reserved_at_0
[0x80];
8831 } mng_access_reg_cap_mask
;
8833 u8 reserved_at_c0
[0x80];
8836 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features
;
8837 u8 reserved_at_0
[0x80];
8838 } mng_feature_cap_mask
;
8840 u8 reserved_at_1c0
[0x80];
8843 struct mlx5_ifc_qcam_access_reg_cap_mask
{
8844 u8 qcam_access_reg_cap_mask_127_to_20
[0x6C];
8846 u8 qcam_access_reg_cap_mask_18_to_4
[0x0F];
8850 u8 qcam_access_reg_cap_mask_0
[0x1];
8853 struct mlx5_ifc_qcam_qos_feature_cap_mask
{
8854 u8 qcam_qos_feature_cap_mask_127_to_1
[0x7F];
8855 u8 qpts_trust_both
[0x1];
8858 struct mlx5_ifc_qcam_reg_bits
{
8859 u8 reserved_at_0
[0x8];
8860 u8 feature_group
[0x8];
8861 u8 reserved_at_10
[0x8];
8862 u8 access_reg_group
[0x8];
8863 u8 reserved_at_20
[0x20];
8866 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap
;
8867 u8 reserved_at_0
[0x80];
8868 } qos_access_reg_cap_mask
;
8870 u8 reserved_at_c0
[0x80];
8873 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap
;
8874 u8 reserved_at_0
[0x80];
8875 } qos_feature_cap_mask
;
8877 u8 reserved_at_1c0
[0x80];
8880 struct mlx5_ifc_core_dump_reg_bits
{
8881 u8 reserved_at_0
[0x18];
8882 u8 core_dump_type
[0x8];
8884 u8 reserved_at_20
[0x30];
8887 u8 reserved_at_60
[0x8];
8889 u8 reserved_at_80
[0x180];
8892 struct mlx5_ifc_pcap_reg_bits
{
8893 u8 reserved_at_0
[0x8];
8895 u8 reserved_at_10
[0x10];
8897 u8 port_capability_mask
[4][0x20];
8900 struct mlx5_ifc_paos_reg_bits
{
8903 u8 reserved_at_10
[0x4];
8904 u8 admin_status
[0x4];
8905 u8 reserved_at_18
[0x4];
8906 u8 oper_status
[0x4];
8910 u8 reserved_at_22
[0x1c];
8913 u8 reserved_at_40
[0x40];
8916 struct mlx5_ifc_pamp_reg_bits
{
8917 u8 reserved_at_0
[0x8];
8918 u8 opamp_group
[0x8];
8919 u8 reserved_at_10
[0xc];
8920 u8 opamp_group_type
[0x4];
8922 u8 start_index
[0x10];
8923 u8 reserved_at_30
[0x4];
8924 u8 num_of_indices
[0xc];
8926 u8 index_data
[18][0x10];
8929 struct mlx5_ifc_pcmr_reg_bits
{
8930 u8 reserved_at_0
[0x8];
8932 u8 reserved_at_10
[0x10];
8933 u8 entropy_force_cap
[0x1];
8934 u8 entropy_calc_cap
[0x1];
8935 u8 entropy_gre_calc_cap
[0x1];
8936 u8 reserved_at_23
[0x1b];
8938 u8 reserved_at_3f
[0x1];
8939 u8 entropy_force
[0x1];
8940 u8 entropy_calc
[0x1];
8941 u8 entropy_gre_calc
[0x1];
8942 u8 reserved_at_43
[0x1b];
8944 u8 reserved_at_5f
[0x1];
8947 struct mlx5_ifc_lane_2_module_mapping_bits
{
8948 u8 reserved_at_0
[0x6];
8950 u8 reserved_at_8
[0x6];
8952 u8 reserved_at_10
[0x8];
8956 struct mlx5_ifc_bufferx_reg_bits
{
8957 u8 reserved_at_0
[0x6];
8960 u8 reserved_at_8
[0xc];
8963 u8 xoff_threshold
[0x10];
8964 u8 xon_threshold
[0x10];
8967 struct mlx5_ifc_set_node_in_bits
{
8968 u8 node_description
[64][0x8];
8971 struct mlx5_ifc_register_power_settings_bits
{
8972 u8 reserved_at_0
[0x18];
8973 u8 power_settings_level
[0x8];
8975 u8 reserved_at_20
[0x60];
8978 struct mlx5_ifc_register_host_endianness_bits
{
8980 u8 reserved_at_1
[0x1f];
8982 u8 reserved_at_20
[0x60];
8985 struct mlx5_ifc_umr_pointer_desc_argument_bits
{
8986 u8 reserved_at_0
[0x20];
8990 u8 addressh_63_32
[0x20];
8992 u8 addressl_31_0
[0x20];
8995 struct mlx5_ifc_ud_adrs_vector_bits
{
8999 u8 reserved_at_41
[0x7];
9000 u8 destination_qp_dct
[0x18];
9002 u8 static_rate
[0x4];
9003 u8 sl_eth_prio
[0x4];
9006 u8 rlid_udp_sport
[0x10];
9008 u8 reserved_at_80
[0x20];
9010 u8 rmac_47_16
[0x20];
9016 u8 reserved_at_e0
[0x1];
9018 u8 reserved_at_e2
[0x2];
9019 u8 src_addr_index
[0x8];
9020 u8 flow_label
[0x14];
9022 u8 rgid_rip
[16][0x8];
9025 struct mlx5_ifc_pages_req_event_bits
{
9026 u8 reserved_at_0
[0x10];
9027 u8 function_id
[0x10];
9031 u8 reserved_at_40
[0xa0];
9034 struct mlx5_ifc_eqe_bits
{
9035 u8 reserved_at_0
[0x8];
9037 u8 reserved_at_10
[0x8];
9038 u8 event_sub_type
[0x8];
9040 u8 reserved_at_20
[0xe0];
9042 union mlx5_ifc_event_auto_bits event_data
;
9044 u8 reserved_at_1e0
[0x10];
9046 u8 reserved_at_1f8
[0x7];
9051 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT
= 0x7,
9054 struct mlx5_ifc_cmd_queue_entry_bits
{
9056 u8 reserved_at_8
[0x18];
9058 u8 input_length
[0x20];
9060 u8 input_mailbox_pointer_63_32
[0x20];
9062 u8 input_mailbox_pointer_31_9
[0x17];
9063 u8 reserved_at_77
[0x9];
9065 u8 command_input_inline_data
[16][0x8];
9067 u8 command_output_inline_data
[16][0x8];
9069 u8 output_mailbox_pointer_63_32
[0x20];
9071 u8 output_mailbox_pointer_31_9
[0x17];
9072 u8 reserved_at_1b7
[0x9];
9074 u8 output_length
[0x20];
9078 u8 reserved_at_1f0
[0x8];
9083 struct mlx5_ifc_cmd_out_bits
{
9085 u8 reserved_at_8
[0x18];
9089 u8 command_output
[0x20];
9092 struct mlx5_ifc_cmd_in_bits
{
9094 u8 reserved_at_10
[0x10];
9096 u8 reserved_at_20
[0x10];
9099 u8 command
[0][0x20];
9102 struct mlx5_ifc_cmd_if_box_bits
{
9103 u8 mailbox_data
[512][0x8];
9105 u8 reserved_at_1000
[0x180];
9107 u8 next_pointer_63_32
[0x20];
9109 u8 next_pointer_31_10
[0x16];
9110 u8 reserved_at_11b6
[0xa];
9112 u8 block_number
[0x20];
9114 u8 reserved_at_11e0
[0x8];
9116 u8 ctrl_signature
[0x8];
9120 struct mlx5_ifc_mtt_bits
{
9121 u8 ptag_63_32
[0x20];
9124 u8 reserved_at_38
[0x6];
9129 struct mlx5_ifc_query_wol_rol_out_bits
{
9131 u8 reserved_at_8
[0x18];
9135 u8 reserved_at_40
[0x10];
9139 u8 reserved_at_60
[0x20];
9142 struct mlx5_ifc_query_wol_rol_in_bits
{
9144 u8 reserved_at_10
[0x10];
9146 u8 reserved_at_20
[0x10];
9149 u8 reserved_at_40
[0x40];
9152 struct mlx5_ifc_set_wol_rol_out_bits
{
9154 u8 reserved_at_8
[0x18];
9158 u8 reserved_at_40
[0x40];
9161 struct mlx5_ifc_set_wol_rol_in_bits
{
9163 u8 reserved_at_10
[0x10];
9165 u8 reserved_at_20
[0x10];
9168 u8 rol_mode_valid
[0x1];
9169 u8 wol_mode_valid
[0x1];
9170 u8 reserved_at_42
[0xe];
9174 u8 reserved_at_60
[0x20];
9178 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER
= 0x0,
9179 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED
= 0x1,
9180 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC
= 0x2,
9184 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER
= 0x0,
9185 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED
= 0x1,
9186 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC
= 0x2,
9190 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR
= 0x1,
9191 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC
= 0x7,
9192 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR
= 0x8,
9193 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR
= 0x9,
9194 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR
= 0xa,
9195 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR
= 0xb,
9196 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN
= 0xc,
9197 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR
= 0xd,
9198 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV
= 0xe,
9199 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR
= 0xf,
9200 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR
= 0x10,
9203 struct mlx5_ifc_initial_seg_bits
{
9204 u8 fw_rev_minor
[0x10];
9205 u8 fw_rev_major
[0x10];
9207 u8 cmd_interface_rev
[0x10];
9208 u8 fw_rev_subminor
[0x10];
9210 u8 reserved_at_40
[0x40];
9212 u8 cmdq_phy_addr_63_32
[0x20];
9214 u8 cmdq_phy_addr_31_12
[0x14];
9215 u8 reserved_at_b4
[0x2];
9216 u8 nic_interface
[0x2];
9217 u8 log_cmdq_size
[0x4];
9218 u8 log_cmdq_stride
[0x4];
9220 u8 command_doorbell_vector
[0x20];
9222 u8 reserved_at_e0
[0xf00];
9224 u8 initializing
[0x1];
9225 u8 reserved_at_fe1
[0x4];
9226 u8 nic_interface_supported
[0x3];
9227 u8 embedded_cpu
[0x1];
9228 u8 reserved_at_fe9
[0x17];
9230 struct mlx5_ifc_health_buffer_bits health_buffer
;
9232 u8 no_dram_nic_offset
[0x20];
9234 u8 reserved_at_1220
[0x6e40];
9236 u8 reserved_at_8060
[0x1f];
9239 u8 health_syndrome
[0x8];
9240 u8 health_counter
[0x18];
9242 u8 reserved_at_80a0
[0x17fc0];
9245 struct mlx5_ifc_mtpps_reg_bits
{
9246 u8 reserved_at_0
[0xc];
9247 u8 cap_number_of_pps_pins
[0x4];
9248 u8 reserved_at_10
[0x4];
9249 u8 cap_max_num_of_pps_in_pins
[0x4];
9250 u8 reserved_at_18
[0x4];
9251 u8 cap_max_num_of_pps_out_pins
[0x4];
9253 u8 reserved_at_20
[0x24];
9254 u8 cap_pin_3_mode
[0x4];
9255 u8 reserved_at_48
[0x4];
9256 u8 cap_pin_2_mode
[0x4];
9257 u8 reserved_at_50
[0x4];
9258 u8 cap_pin_1_mode
[0x4];
9259 u8 reserved_at_58
[0x4];
9260 u8 cap_pin_0_mode
[0x4];
9262 u8 reserved_at_60
[0x4];
9263 u8 cap_pin_7_mode
[0x4];
9264 u8 reserved_at_68
[0x4];
9265 u8 cap_pin_6_mode
[0x4];
9266 u8 reserved_at_70
[0x4];
9267 u8 cap_pin_5_mode
[0x4];
9268 u8 reserved_at_78
[0x4];
9269 u8 cap_pin_4_mode
[0x4];
9271 u8 field_select
[0x20];
9272 u8 reserved_at_a0
[0x60];
9275 u8 reserved_at_101
[0xb];
9277 u8 reserved_at_110
[0x4];
9281 u8 reserved_at_120
[0x20];
9283 u8 time_stamp
[0x40];
9285 u8 out_pulse_duration
[0x10];
9286 u8 out_periodic_adjustment
[0x10];
9287 u8 enhanced_out_periodic_adjustment
[0x20];
9289 u8 reserved_at_1c0
[0x20];
9292 struct mlx5_ifc_mtppse_reg_bits
{
9293 u8 reserved_at_0
[0x18];
9296 u8 reserved_at_21
[0x1b];
9297 u8 event_generation_mode
[0x4];
9298 u8 reserved_at_40
[0x40];
9301 struct mlx5_ifc_mcqs_reg_bits
{
9302 u8 last_index_flag
[0x1];
9303 u8 reserved_at_1
[0x7];
9305 u8 component_index
[0x10];
9307 u8 reserved_at_20
[0x10];
9308 u8 identifier
[0x10];
9310 u8 reserved_at_40
[0x17];
9311 u8 component_status
[0x5];
9312 u8 component_update_state
[0x4];
9314 u8 last_update_state_changer_type
[0x4];
9315 u8 last_update_state_changer_host_id
[0x4];
9316 u8 reserved_at_68
[0x18];
9319 struct mlx5_ifc_mcqi_cap_bits
{
9320 u8 supported_info_bitmask
[0x20];
9322 u8 component_size
[0x20];
9324 u8 max_component_size
[0x20];
9326 u8 log_mcda_word_size
[0x4];
9327 u8 reserved_at_64
[0xc];
9328 u8 mcda_max_write_size
[0x10];
9331 u8 reserved_at_81
[0x1];
9332 u8 match_chip_id
[0x1];
9334 u8 check_user_timestamp
[0x1];
9335 u8 match_base_guid_mac
[0x1];
9336 u8 reserved_at_86
[0x1a];
9339 struct mlx5_ifc_mcqi_version_bits
{
9340 u8 reserved_at_0
[0x2];
9341 u8 build_time_valid
[0x1];
9342 u8 user_defined_time_valid
[0x1];
9343 u8 reserved_at_4
[0x14];
9344 u8 version_string_length
[0x8];
9348 u8 build_time
[0x40];
9350 u8 user_defined_time
[0x40];
9352 u8 build_tool_version
[0x20];
9354 u8 reserved_at_e0
[0x20];
9356 u8 version_string
[92][0x8];
9359 struct mlx5_ifc_mcqi_activation_method_bits
{
9360 u8 pending_server_ac_power_cycle
[0x1];
9361 u8 pending_server_dc_power_cycle
[0x1];
9362 u8 pending_server_reboot
[0x1];
9363 u8 pending_fw_reset
[0x1];
9364 u8 auto_activate
[0x1];
9365 u8 all_hosts_sync
[0x1];
9366 u8 device_hw_reset
[0x1];
9367 u8 reserved_at_7
[0x19];
9370 union mlx5_ifc_mcqi_reg_data_bits
{
9371 struct mlx5_ifc_mcqi_cap_bits mcqi_caps
;
9372 struct mlx5_ifc_mcqi_version_bits mcqi_version
;
9373 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod
;
9376 struct mlx5_ifc_mcqi_reg_bits
{
9377 u8 read_pending_component
[0x1];
9378 u8 reserved_at_1
[0xf];
9379 u8 component_index
[0x10];
9381 u8 reserved_at_20
[0x20];
9383 u8 reserved_at_40
[0x1b];
9390 u8 reserved_at_a0
[0x10];
9393 union mlx5_ifc_mcqi_reg_data_bits data
[0];
9396 struct mlx5_ifc_mcc_reg_bits
{
9397 u8 reserved_at_0
[0x4];
9398 u8 time_elapsed_since_last_cmd
[0xc];
9399 u8 reserved_at_10
[0x8];
9400 u8 instruction
[0x8];
9402 u8 reserved_at_20
[0x10];
9403 u8 component_index
[0x10];
9405 u8 reserved_at_40
[0x8];
9406 u8 update_handle
[0x18];
9408 u8 handle_owner_type
[0x4];
9409 u8 handle_owner_host_id
[0x4];
9410 u8 reserved_at_68
[0x1];
9411 u8 control_progress
[0x7];
9413 u8 reserved_at_78
[0x4];
9414 u8 control_state
[0x4];
9416 u8 component_size
[0x20];
9418 u8 reserved_at_a0
[0x60];
9421 struct mlx5_ifc_mcda_reg_bits
{
9422 u8 reserved_at_0
[0x8];
9423 u8 update_handle
[0x18];
9427 u8 reserved_at_40
[0x10];
9430 u8 reserved_at_60
[0x20];
9435 union mlx5_ifc_ports_control_registers_document_bits
{
9436 struct mlx5_ifc_bufferx_reg_bits bufferx_reg
;
9437 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout
;
9438 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout
;
9439 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout
;
9440 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout
;
9441 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout
;
9442 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout
;
9443 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout
;
9444 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout
;
9445 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping
;
9446 struct mlx5_ifc_pamp_reg_bits pamp_reg
;
9447 struct mlx5_ifc_paos_reg_bits paos_reg
;
9448 struct mlx5_ifc_pcap_reg_bits pcap_reg
;
9449 struct mlx5_ifc_peir_reg_bits peir_reg
;
9450 struct mlx5_ifc_pelc_reg_bits pelc_reg
;
9451 struct mlx5_ifc_pfcc_reg_bits pfcc_reg
;
9452 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout
;
9453 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs
;
9454 struct mlx5_ifc_pifr_reg_bits pifr_reg
;
9455 struct mlx5_ifc_pipg_reg_bits pipg_reg
;
9456 struct mlx5_ifc_plbf_reg_bits plbf_reg
;
9457 struct mlx5_ifc_plib_reg_bits plib_reg
;
9458 struct mlx5_ifc_plpc_reg_bits plpc_reg
;
9459 struct mlx5_ifc_pmaos_reg_bits pmaos_reg
;
9460 struct mlx5_ifc_pmlp_reg_bits pmlp_reg
;
9461 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg
;
9462 struct mlx5_ifc_pmpc_reg_bits pmpc_reg
;
9463 struct mlx5_ifc_pmpe_reg_bits pmpe_reg
;
9464 struct mlx5_ifc_pmpr_reg_bits pmpr_reg
;
9465 struct mlx5_ifc_pmtu_reg_bits pmtu_reg
;
9466 struct mlx5_ifc_ppad_reg_bits ppad_reg
;
9467 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg
;
9468 struct mlx5_ifc_mpein_reg_bits mpein_reg
;
9469 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg
;
9470 struct mlx5_ifc_pplm_reg_bits pplm_reg
;
9471 struct mlx5_ifc_pplr_reg_bits pplr_reg
;
9472 struct mlx5_ifc_ppsc_reg_bits ppsc_reg
;
9473 struct mlx5_ifc_pqdr_reg_bits pqdr_reg
;
9474 struct mlx5_ifc_pspa_reg_bits pspa_reg
;
9475 struct mlx5_ifc_ptas_reg_bits ptas_reg
;
9476 struct mlx5_ifc_ptys_reg_bits ptys_reg
;
9477 struct mlx5_ifc_mlcr_reg_bits mlcr_reg
;
9478 struct mlx5_ifc_pude_reg_bits pude_reg
;
9479 struct mlx5_ifc_pvlc_reg_bits pvlc_reg
;
9480 struct mlx5_ifc_slrg_reg_bits slrg_reg
;
9481 struct mlx5_ifc_sltp_reg_bits sltp_reg
;
9482 struct mlx5_ifc_mtpps_reg_bits mtpps_reg
;
9483 struct mlx5_ifc_mtppse_reg_bits mtppse_reg
;
9484 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg
;
9485 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits
;
9486 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits
;
9487 struct mlx5_ifc_mcqi_reg_bits mcqi_reg
;
9488 struct mlx5_ifc_mcc_reg_bits mcc_reg
;
9489 struct mlx5_ifc_mcda_reg_bits mcda_reg
;
9490 u8 reserved_at_0
[0x60e0];
9493 union mlx5_ifc_debug_enhancements_document_bits
{
9494 struct mlx5_ifc_health_buffer_bits health_buffer
;
9495 u8 reserved_at_0
[0x200];
9498 union mlx5_ifc_uplink_pci_interface_document_bits
{
9499 struct mlx5_ifc_initial_seg_bits initial_seg
;
9500 u8 reserved_at_0
[0x20060];
9503 struct mlx5_ifc_set_flow_table_root_out_bits
{
9505 u8 reserved_at_8
[0x18];
9509 u8 reserved_at_40
[0x40];
9512 struct mlx5_ifc_set_flow_table_root_in_bits
{
9514 u8 reserved_at_10
[0x10];
9516 u8 reserved_at_20
[0x10];
9519 u8 other_vport
[0x1];
9520 u8 reserved_at_41
[0xf];
9521 u8 vport_number
[0x10];
9523 u8 reserved_at_60
[0x20];
9526 u8 reserved_at_88
[0x18];
9528 u8 reserved_at_a0
[0x8];
9531 u8 reserved_at_c0
[0x8];
9532 u8 underlay_qpn
[0x18];
9533 u8 reserved_at_e0
[0x120];
9537 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID
= (1UL << 0),
9538 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID
= (1UL << 15),
9541 struct mlx5_ifc_modify_flow_table_out_bits
{
9543 u8 reserved_at_8
[0x18];
9547 u8 reserved_at_40
[0x40];
9550 struct mlx5_ifc_modify_flow_table_in_bits
{
9552 u8 reserved_at_10
[0x10];
9554 u8 reserved_at_20
[0x10];
9557 u8 other_vport
[0x1];
9558 u8 reserved_at_41
[0xf];
9559 u8 vport_number
[0x10];
9561 u8 reserved_at_60
[0x10];
9562 u8 modify_field_select
[0x10];
9565 u8 reserved_at_88
[0x18];
9567 u8 reserved_at_a0
[0x8];
9570 struct mlx5_ifc_flow_table_context_bits flow_table_context
;
9573 struct mlx5_ifc_ets_tcn_config_reg_bits
{
9577 u8 reserved_at_3
[0x9];
9579 u8 reserved_at_10
[0x9];
9580 u8 bw_allocation
[0x7];
9582 u8 reserved_at_20
[0xc];
9583 u8 max_bw_units
[0x4];
9584 u8 reserved_at_30
[0x8];
9585 u8 max_bw_value
[0x8];
9588 struct mlx5_ifc_ets_global_config_reg_bits
{
9589 u8 reserved_at_0
[0x2];
9591 u8 reserved_at_3
[0x1d];
9593 u8 reserved_at_20
[0xc];
9594 u8 max_bw_units
[0x4];
9595 u8 reserved_at_30
[0x8];
9596 u8 max_bw_value
[0x8];
9599 struct mlx5_ifc_qetc_reg_bits
{
9600 u8 reserved_at_0
[0x8];
9601 u8 port_number
[0x8];
9602 u8 reserved_at_10
[0x30];
9604 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration
[0x8];
9605 struct mlx5_ifc_ets_global_config_reg_bits global_configuration
;
9608 struct mlx5_ifc_qpdpm_dscp_reg_bits
{
9610 u8 reserved_at_01
[0x0b];
9614 struct mlx5_ifc_qpdpm_reg_bits
{
9615 u8 reserved_at_0
[0x8];
9617 u8 reserved_at_10
[0x10];
9618 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp
[64];
9621 struct mlx5_ifc_qpts_reg_bits
{
9622 u8 reserved_at_0
[0x8];
9624 u8 reserved_at_10
[0x2d];
9625 u8 trust_state
[0x3];
9628 struct mlx5_ifc_pptb_reg_bits
{
9629 u8 reserved_at_0
[0x2];
9631 u8 reserved_at_4
[0x4];
9633 u8 reserved_at_10
[0x6];
9638 u8 prio_x_buff
[0x20];
9641 u8 reserved_at_48
[0x10];
9643 u8 untagged_buff
[0x4];
9646 struct mlx5_ifc_pbmc_reg_bits
{
9647 u8 reserved_at_0
[0x8];
9649 u8 reserved_at_10
[0x10];
9651 u8 xoff_timer_value
[0x10];
9652 u8 xoff_refresh
[0x10];
9654 u8 reserved_at_40
[0x9];
9655 u8 fullness_threshold
[0x7];
9656 u8 port_buffer_size
[0x10];
9658 struct mlx5_ifc_bufferx_reg_bits buffer
[10];
9660 u8 reserved_at_2e0
[0x40];
9663 struct mlx5_ifc_qtct_reg_bits
{
9664 u8 reserved_at_0
[0x8];
9665 u8 port_number
[0x8];
9666 u8 reserved_at_10
[0xd];
9669 u8 reserved_at_20
[0x1d];
9673 struct mlx5_ifc_mcia_reg_bits
{
9675 u8 reserved_at_1
[0x7];
9677 u8 reserved_at_10
[0x8];
9680 u8 i2c_device_address
[0x8];
9681 u8 page_number
[0x8];
9682 u8 device_address
[0x10];
9684 u8 reserved_at_40
[0x10];
9687 u8 reserved_at_60
[0x20];
9703 struct mlx5_ifc_dcbx_param_bits
{
9704 u8 dcbx_cee_cap
[0x1];
9705 u8 dcbx_ieee_cap
[0x1];
9706 u8 dcbx_standby_cap
[0x1];
9707 u8 reserved_at_3
[0x5];
9708 u8 port_number
[0x8];
9709 u8 reserved_at_10
[0xa];
9710 u8 max_application_table_size
[6];
9711 u8 reserved_at_20
[0x15];
9712 u8 version_oper
[0x3];
9713 u8 reserved_at_38
[5];
9714 u8 version_admin
[0x3];
9715 u8 willing_admin
[0x1];
9716 u8 reserved_at_41
[0x3];
9717 u8 pfc_cap_oper
[0x4];
9718 u8 reserved_at_48
[0x4];
9719 u8 pfc_cap_admin
[0x4];
9720 u8 reserved_at_50
[0x4];
9721 u8 num_of_tc_oper
[0x4];
9722 u8 reserved_at_58
[0x4];
9723 u8 num_of_tc_admin
[0x4];
9724 u8 remote_willing
[0x1];
9725 u8 reserved_at_61
[3];
9726 u8 remote_pfc_cap
[4];
9727 u8 reserved_at_68
[0x14];
9728 u8 remote_num_of_tc
[0x4];
9729 u8 reserved_at_80
[0x18];
9731 u8 reserved_at_a0
[0x160];
9734 struct mlx5_ifc_lagc_bits
{
9735 u8 reserved_at_0
[0x1d];
9738 u8 reserved_at_20
[0x14];
9739 u8 tx_remap_affinity_2
[0x4];
9740 u8 reserved_at_38
[0x4];
9741 u8 tx_remap_affinity_1
[0x4];
9744 struct mlx5_ifc_create_lag_out_bits
{
9746 u8 reserved_at_8
[0x18];
9750 u8 reserved_at_40
[0x40];
9753 struct mlx5_ifc_create_lag_in_bits
{
9755 u8 reserved_at_10
[0x10];
9757 u8 reserved_at_20
[0x10];
9760 struct mlx5_ifc_lagc_bits ctx
;
9763 struct mlx5_ifc_modify_lag_out_bits
{
9765 u8 reserved_at_8
[0x18];
9769 u8 reserved_at_40
[0x40];
9772 struct mlx5_ifc_modify_lag_in_bits
{
9774 u8 reserved_at_10
[0x10];
9776 u8 reserved_at_20
[0x10];
9779 u8 reserved_at_40
[0x20];
9780 u8 field_select
[0x20];
9782 struct mlx5_ifc_lagc_bits ctx
;
9785 struct mlx5_ifc_query_lag_out_bits
{
9787 u8 reserved_at_8
[0x18];
9791 struct mlx5_ifc_lagc_bits ctx
;
9794 struct mlx5_ifc_query_lag_in_bits
{
9796 u8 reserved_at_10
[0x10];
9798 u8 reserved_at_20
[0x10];
9801 u8 reserved_at_40
[0x40];
9804 struct mlx5_ifc_destroy_lag_out_bits
{
9806 u8 reserved_at_8
[0x18];
9810 u8 reserved_at_40
[0x40];
9813 struct mlx5_ifc_destroy_lag_in_bits
{
9815 u8 reserved_at_10
[0x10];
9817 u8 reserved_at_20
[0x10];
9820 u8 reserved_at_40
[0x40];
9823 struct mlx5_ifc_create_vport_lag_out_bits
{
9825 u8 reserved_at_8
[0x18];
9829 u8 reserved_at_40
[0x40];
9832 struct mlx5_ifc_create_vport_lag_in_bits
{
9834 u8 reserved_at_10
[0x10];
9836 u8 reserved_at_20
[0x10];
9839 u8 reserved_at_40
[0x40];
9842 struct mlx5_ifc_destroy_vport_lag_out_bits
{
9844 u8 reserved_at_8
[0x18];
9848 u8 reserved_at_40
[0x40];
9851 struct mlx5_ifc_destroy_vport_lag_in_bits
{
9853 u8 reserved_at_10
[0x10];
9855 u8 reserved_at_20
[0x10];
9858 u8 reserved_at_40
[0x40];
9861 struct mlx5_ifc_alloc_memic_in_bits
{
9863 u8 reserved_at_10
[0x10];
9865 u8 reserved_at_20
[0x10];
9868 u8 reserved_at_30
[0x20];
9870 u8 reserved_at_40
[0x18];
9871 u8 log_memic_addr_alignment
[0x8];
9873 u8 range_start_addr
[0x40];
9875 u8 range_size
[0x20];
9877 u8 memic_size
[0x20];
9880 struct mlx5_ifc_alloc_memic_out_bits
{
9882 u8 reserved_at_8
[0x18];
9886 u8 memic_start_addr
[0x40];
9889 struct mlx5_ifc_dealloc_memic_in_bits
{
9891 u8 reserved_at_10
[0x10];
9893 u8 reserved_at_20
[0x10];
9896 u8 reserved_at_40
[0x40];
9898 u8 memic_start_addr
[0x40];
9900 u8 memic_size
[0x20];
9902 u8 reserved_at_e0
[0x20];
9905 struct mlx5_ifc_dealloc_memic_out_bits
{
9907 u8 reserved_at_8
[0x18];
9911 u8 reserved_at_40
[0x40];
9914 struct mlx5_ifc_general_obj_in_cmd_hdr_bits
{
9918 u8 vhca_tunnel_id
[0x10];
9923 u8 reserved_at_60
[0x20];
9926 struct mlx5_ifc_general_obj_out_cmd_hdr_bits
{
9928 u8 reserved_at_8
[0x18];
9934 u8 reserved_at_60
[0x20];
9937 struct mlx5_ifc_umem_bits
{
9938 u8 reserved_at_0
[0x80];
9940 u8 reserved_at_80
[0x1b];
9941 u8 log_page_size
[0x5];
9943 u8 page_offset
[0x20];
9945 u8 num_of_mtt
[0x40];
9947 struct mlx5_ifc_mtt_bits mtt
[0];
9950 struct mlx5_ifc_uctx_bits
{
9953 u8 reserved_at_20
[0x160];
9956 struct mlx5_ifc_sw_icm_bits
{
9957 u8 modify_field_select
[0x40];
9959 u8 reserved_at_40
[0x18];
9960 u8 log_sw_icm_size
[0x8];
9962 u8 reserved_at_60
[0x20];
9964 u8 sw_icm_start_addr
[0x40];
9966 u8 reserved_at_c0
[0x140];
9969 struct mlx5_ifc_geneve_tlv_option_bits
{
9970 u8 modify_field_select
[0x40];
9972 u8 reserved_at_40
[0x18];
9973 u8 geneve_option_fte_index
[0x8];
9975 u8 option_class
[0x10];
9976 u8 option_type
[0x8];
9977 u8 reserved_at_78
[0x3];
9978 u8 option_data_length
[0x5];
9980 u8 reserved_at_80
[0x180];
9983 struct mlx5_ifc_create_umem_in_bits
{
9987 u8 reserved_at_20
[0x10];
9990 u8 reserved_at_40
[0x40];
9992 struct mlx5_ifc_umem_bits umem
;
9995 struct mlx5_ifc_create_uctx_in_bits
{
9997 u8 reserved_at_10
[0x10];
9999 u8 reserved_at_20
[0x10];
10002 u8 reserved_at_40
[0x40];
10004 struct mlx5_ifc_uctx_bits uctx
;
10007 struct mlx5_ifc_destroy_uctx_in_bits
{
10009 u8 reserved_at_10
[0x10];
10011 u8 reserved_at_20
[0x10];
10014 u8 reserved_at_40
[0x10];
10017 u8 reserved_at_60
[0x20];
10020 struct mlx5_ifc_create_sw_icm_in_bits
{
10021 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr
;
10022 struct mlx5_ifc_sw_icm_bits sw_icm
;
10025 struct mlx5_ifc_create_geneve_tlv_option_in_bits
{
10026 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr
;
10027 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt
;
10030 struct mlx5_ifc_mtrc_string_db_param_bits
{
10031 u8 string_db_base_address
[0x20];
10033 u8 reserved_at_20
[0x8];
10034 u8 string_db_size
[0x18];
10037 struct mlx5_ifc_mtrc_cap_bits
{
10038 u8 trace_owner
[0x1];
10039 u8 trace_to_memory
[0x1];
10040 u8 reserved_at_2
[0x4];
10042 u8 reserved_at_8
[0x14];
10043 u8 num_string_db
[0x4];
10045 u8 first_string_trace
[0x8];
10046 u8 num_string_trace
[0x8];
10047 u8 reserved_at_30
[0x28];
10049 u8 log_max_trace_buffer_size
[0x8];
10051 u8 reserved_at_60
[0x20];
10053 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param
[8];
10055 u8 reserved_at_280
[0x180];
10058 struct mlx5_ifc_mtrc_conf_bits
{
10059 u8 reserved_at_0
[0x1c];
10060 u8 trace_mode
[0x4];
10061 u8 reserved_at_20
[0x18];
10062 u8 log_trace_buffer_size
[0x8];
10063 u8 trace_mkey
[0x20];
10064 u8 reserved_at_60
[0x3a0];
10067 struct mlx5_ifc_mtrc_stdb_bits
{
10068 u8 string_db_index
[0x4];
10069 u8 reserved_at_4
[0x4];
10070 u8 read_size
[0x18];
10071 u8 start_offset
[0x20];
10072 u8 string_db_data
[0];
10075 struct mlx5_ifc_mtrc_ctrl_bits
{
10076 u8 trace_status
[0x2];
10077 u8 reserved_at_2
[0x2];
10079 u8 reserved_at_5
[0xb];
10080 u8 modify_field_select
[0x10];
10081 u8 reserved_at_20
[0x2b];
10082 u8 current_timestamp52_32
[0x15];
10083 u8 current_timestamp31_0
[0x20];
10084 u8 reserved_at_80
[0x180];
10087 struct mlx5_ifc_host_params_context_bits
{
10088 u8 host_number
[0x8];
10089 u8 reserved_at_8
[0x7];
10090 u8 host_pf_disabled
[0x1];
10091 u8 host_num_of_vfs
[0x10];
10093 u8 host_total_vfs
[0x10];
10094 u8 host_pci_bus
[0x10];
10096 u8 reserved_at_40
[0x10];
10097 u8 host_pci_device
[0x10];
10099 u8 reserved_at_60
[0x10];
10100 u8 host_pci_function
[0x10];
10102 u8 reserved_at_80
[0x180];
10105 struct mlx5_ifc_query_esw_functions_in_bits
{
10107 u8 reserved_at_10
[0x10];
10109 u8 reserved_at_20
[0x10];
10112 u8 reserved_at_40
[0x40];
10115 struct mlx5_ifc_query_esw_functions_out_bits
{
10117 u8 reserved_at_8
[0x18];
10121 u8 reserved_at_40
[0x40];
10123 struct mlx5_ifc_host_params_context_bits host_params_context
;
10125 u8 reserved_at_280
[0x180];
10126 u8 host_sf_enable
[0][0x40];
10129 struct mlx5_ifc_sf_partition_bits
{
10130 u8 reserved_at_0
[0x10];
10131 u8 log_num_sf
[0x8];
10132 u8 log_sf_bar_size
[0x8];
10135 struct mlx5_ifc_query_sf_partitions_out_bits
{
10137 u8 reserved_at_8
[0x18];
10141 u8 reserved_at_40
[0x18];
10142 u8 num_sf_partitions
[0x8];
10144 u8 reserved_at_60
[0x20];
10146 struct mlx5_ifc_sf_partition_bits sf_partition
[0];
10149 struct mlx5_ifc_query_sf_partitions_in_bits
{
10151 u8 reserved_at_10
[0x10];
10153 u8 reserved_at_20
[0x10];
10156 u8 reserved_at_40
[0x40];
10159 struct mlx5_ifc_dealloc_sf_out_bits
{
10161 u8 reserved_at_8
[0x18];
10165 u8 reserved_at_40
[0x40];
10168 struct mlx5_ifc_dealloc_sf_in_bits
{
10170 u8 reserved_at_10
[0x10];
10172 u8 reserved_at_20
[0x10];
10175 u8 reserved_at_40
[0x10];
10176 u8 function_id
[0x10];
10178 u8 reserved_at_60
[0x20];
10181 struct mlx5_ifc_alloc_sf_out_bits
{
10183 u8 reserved_at_8
[0x18];
10187 u8 reserved_at_40
[0x40];
10190 struct mlx5_ifc_alloc_sf_in_bits
{
10192 u8 reserved_at_10
[0x10];
10194 u8 reserved_at_20
[0x10];
10197 u8 reserved_at_40
[0x10];
10198 u8 function_id
[0x10];
10200 u8 reserved_at_60
[0x20];
10203 struct mlx5_ifc_affiliated_event_header_bits
{
10204 u8 reserved_at_0
[0x10];
10211 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY
= BIT(0xc),
10215 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY
= 0xc,
10218 struct mlx5_ifc_encryption_key_obj_bits
{
10219 u8 modify_field_select
[0x40];
10221 u8 reserved_at_40
[0x14];
10223 u8 reserved_at_58
[0x4];
10226 u8 reserved_at_60
[0x8];
10229 u8 reserved_at_80
[0x180];
10232 u8 reserved_at_300
[0x500];
10235 struct mlx5_ifc_create_encryption_key_in_bits
{
10236 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr
;
10237 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object
;
10241 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128
= 0x0,
10242 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256
= 0x1,
10246 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK
= 0x1,
10249 struct mlx5_ifc_tls_static_params_bits
{
10251 u8 tls_version
[0x4];
10253 u8 reserved_at_8
[0x14];
10254 u8 encryption_standard
[0x4];
10256 u8 reserved_at_20
[0x20];
10258 u8 initial_record_number
[0x40];
10260 u8 resync_tcp_sn
[0x20];
10264 u8 implicit_iv
[0x40];
10266 u8 reserved_at_100
[0x8];
10267 u8 dek_index
[0x18];
10269 u8 reserved_at_120
[0xe0];
10272 struct mlx5_ifc_tls_progress_params_bits
{
10273 u8 reserved_at_0
[0x8];
10276 u8 next_record_tcp_sn
[0x20];
10278 u8 hw_resync_tcp_sn
[0x20];
10280 u8 record_tracker_state
[0x2];
10281 u8 auth_state
[0x2];
10282 u8 reserved_at_64
[0x4];
10283 u8 hw_offset_record_number
[0x18];
10286 #endif /* MLX5_IFC_H */