include/linux/mlx5/mlx5_ifc_fpga.h

   1 /*
   2  * Copyright (c) 2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef MLX5_IFC_FPGA_H
  33 #define MLX5_IFC_FPGA_H
  34
  35 enum {
  36         MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9,
  37 };
  38
  39 enum {
  40         MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC    = 0x2,
  41 };
  42
  43 struct mlx5_ifc_fpga_shell_caps_bits {
  44         u8         max_num_qps[0x10];
  45         u8         reserved_at_10[0x8];
  46         u8         total_rcv_credits[0x8];
  47
  48         u8         reserved_at_20[0xe];
  49         u8         qp_type[0x2];
  50         u8         reserved_at_30[0x5];
  51         u8         rae[0x1];
  52         u8         rwe[0x1];
  53         u8         rre[0x1];
  54         u8         reserved_at_38[0x4];
  55         u8         dc[0x1];
  56         u8         ud[0x1];
  57         u8         uc[0x1];
  58         u8         rc[0x1];
  59
  60         u8         reserved_at_40[0x1a];
  61         u8         log_ddr_size[0x6];
  62
  63         u8         max_fpga_qp_msg_size[0x20];
  64
  65         u8         reserved_at_80[0x180];
  66 };
  67
  68 struct mlx5_ifc_fpga_cap_bits {
  69         u8         fpga_id[0x8];
  70         u8         fpga_device[0x18];
  71
  72         u8         register_file_ver[0x20];
  73
  74         u8         fpga_ctrl_modify[0x1];
  75         u8         reserved_at_41[0x5];
  76         u8         access_reg_query_mode[0x2];
  77         u8         reserved_at_48[0x6];
  78         u8         access_reg_modify_mode[0x2];
  79         u8         reserved_at_50[0x10];
  80
  81         u8         reserved_at_60[0x20];
  82
  83         u8         image_version[0x20];
  84
  85         u8         image_date[0x20];
  86
  87         u8         image_time[0x20];
  88
  89         u8         shell_version[0x20];
  90
  91         u8         reserved_at_100[0x80];
  92
  93         struct mlx5_ifc_fpga_shell_caps_bits shell_caps;
  94
  95         u8         reserved_at_380[0x8];
  96         u8         ieee_vendor_id[0x18];
  97
  98         u8         sandbox_product_version[0x10];
  99         u8         sandbox_product_id[0x10];
 100
 101         u8         sandbox_basic_caps[0x20];
 102
 103         u8         reserved_at_3e0[0x10];
 104         u8         sandbox_extended_caps_len[0x10];
 105
 106         u8         sandbox_extended_caps_addr[0x40];
 107
 108         u8         fpga_ddr_start_addr[0x40];
 109
 110         u8         fpga_cr_space_start_addr[0x40];
 111
 112         u8         fpga_ddr_size[0x20];
 113
 114         u8         fpga_cr_space_size[0x20];
 115
 116         u8         reserved_at_500[0x300];
 117 };
 118
 119 enum {
 120         MLX5_FPGA_CTRL_OPERATION_LOAD                = 0x1,
 121         MLX5_FPGA_CTRL_OPERATION_RESET               = 0x2,
 122         MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT        = 0x3,
 123         MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON   = 0x4,
 124         MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF  = 0x5,
 125         MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX       = 0x6,
 126 };
 127
 128 struct mlx5_ifc_fpga_ctrl_bits {
 129         u8         reserved_at_0[0x8];
 130         u8         operation[0x8];
 131         u8         reserved_at_10[0x8];
 132         u8         status[0x8];
 133
 134         u8         reserved_at_20[0x8];
 135         u8         flash_select_admin[0x8];
 136         u8         reserved_at_30[0x8];
 137         u8         flash_select_oper[0x8];
 138
 139         u8         reserved_at_40[0x40];
 140 };
 141
 142 enum {
 143         MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR        = 0x1,
 144         MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT        = 0x2,
 145         MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR  = 0x3,
 146         MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE     = 0x4,
 147         MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE          = 0x5,
 148         MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED        = 0x6,
 149         MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7,
 150 };
 151
 152 struct mlx5_ifc_fpga_error_event_bits {
 153         u8         reserved_at_0[0x40];
 154
 155         u8         reserved_at_40[0x18];
 156         u8         syndrome[0x8];
 157
 158         u8         reserved_at_60[0x80];
 159 };
 160
 161 #define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64
 162
 163 struct mlx5_ifc_fpga_access_reg_bits {
 164         u8         reserved_at_0[0x20];
 165
 166         u8         reserved_at_20[0x10];
 167         u8         size[0x10];
 168
 169         u8         address[0x40];
 170
 171         u8         data[0][0x8];
 172 };
 173
 174 enum mlx5_ifc_fpga_qp_state {
 175         MLX5_FPGA_QPC_STATE_INIT    = 0x0,
 176         MLX5_FPGA_QPC_STATE_ACTIVE  = 0x1,
 177         MLX5_FPGA_QPC_STATE_ERROR   = 0x2,
 178 };
 179
 180 enum mlx5_ifc_fpga_qp_type {
 181         MLX5_FPGA_QPC_QP_TYPE_SHELL_QP    = 0x0,
 182         MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP  = 0x1,
 183 };
 184
 185 enum mlx5_ifc_fpga_qp_service_type {
 186         MLX5_FPGA_QPC_ST_RC  = 0x0,
 187 };
 188
 189 struct mlx5_ifc_fpga_qpc_bits {
 190         u8         state[0x4];
 191         u8         reserved_at_4[0x1b];
 192         u8         qp_type[0x1];
 193
 194         u8         reserved_at_20[0x4];
 195         u8         st[0x4];
 196         u8         reserved_at_28[0x10];
 197         u8         traffic_class[0x8];
 198
 199         u8         ether_type[0x10];
 200         u8         prio[0x3];
 201         u8         dei[0x1];
 202         u8         vid[0xc];
 203
 204         u8         reserved_at_60[0x20];
 205
 206         u8         reserved_at_80[0x8];
 207         u8         next_rcv_psn[0x18];
 208
 209         u8         reserved_at_a0[0x8];
 210         u8         next_send_psn[0x18];
 211
 212         u8         reserved_at_c0[0x10];
 213         u8         pkey[0x10];
 214
 215         u8         reserved_at_e0[0x8];
 216         u8         remote_qpn[0x18];
 217
 218         u8         reserved_at_100[0x15];
 219         u8         rnr_retry[0x3];
 220         u8         reserved_at_118[0x5];
 221         u8         retry_count[0x3];
 222
 223         u8         reserved_at_120[0x20];
 224
 225         u8         reserved_at_140[0x10];
 226         u8         remote_mac_47_32[0x10];
 227
 228         u8         remote_mac_31_0[0x20];
 229
 230         u8         remote_ip[16][0x8];
 231
 232         u8         reserved_at_200[0x40];
 233
 234         u8         reserved_at_240[0x10];
 235         u8         fpga_mac_47_32[0x10];
 236
 237         u8         fpga_mac_31_0[0x20];
 238
 239         u8         fpga_ip[16][0x8];
 240 };
 241
 242 struct mlx5_ifc_fpga_create_qp_in_bits {
 243         u8         opcode[0x10];
 244         u8         reserved_at_10[0x10];
 245
 246         u8         reserved_at_20[0x10];
 247         u8         op_mod[0x10];
 248
 249         u8         reserved_at_40[0x40];
 250
 251         struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
 252 };
 253
 254 struct mlx5_ifc_fpga_create_qp_out_bits {
 255         u8         status[0x8];
 256         u8         reserved_at_8[0x18];
 257
 258         u8         syndrome[0x20];
 259
 260         u8         reserved_at_40[0x8];
 261         u8         fpga_qpn[0x18];
 262
 263         u8         reserved_at_60[0x20];
 264
 265         struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
 266 };
 267
 268 struct mlx5_ifc_fpga_modify_qp_in_bits {
 269         u8         opcode[0x10];
 270         u8         reserved_at_10[0x10];
 271
 272         u8         reserved_at_20[0x10];
 273         u8         op_mod[0x10];
 274
 275         u8         reserved_at_40[0x8];
 276         u8         fpga_qpn[0x18];
 277
 278         u8         field_select[0x20];
 279
 280         struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
 281 };
 282
 283 struct mlx5_ifc_fpga_modify_qp_out_bits {
 284         u8         status[0x8];
 285         u8         reserved_at_8[0x18];
 286
 287         u8         syndrome[0x20];
 288
 289         u8         reserved_at_40[0x40];
 290 };
 291
 292 struct mlx5_ifc_fpga_query_qp_in_bits {
 293         u8         opcode[0x10];
 294         u8         reserved_at_10[0x10];
 295
 296         u8         reserved_at_20[0x10];
 297         u8         op_mod[0x10];
 298
 299         u8         reserved_at_40[0x8];
 300         u8         fpga_qpn[0x18];
 301
 302         u8         reserved_at_60[0x20];
 303 };
 304
 305 struct mlx5_ifc_fpga_query_qp_out_bits {
 306         u8         status[0x8];
 307         u8         reserved_at_8[0x18];
 308
 309         u8         syndrome[0x20];
 310
 311         u8         reserved_at_40[0x40];
 312
 313         struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
 314 };
 315
 316 struct mlx5_ifc_fpga_query_qp_counters_in_bits {
 317         u8         opcode[0x10];
 318         u8         reserved_at_10[0x10];
 319
 320         u8         reserved_at_20[0x10];
 321         u8         op_mod[0x10];
 322
 323         u8         clear[0x1];
 324         u8         reserved_at_41[0x7];
 325         u8         fpga_qpn[0x18];
 326
 327         u8         reserved_at_60[0x20];
 328 };
 329
 330 struct mlx5_ifc_fpga_query_qp_counters_out_bits {
 331         u8         status[0x8];
 332         u8         reserved_at_8[0x18];
 333
 334         u8         syndrome[0x20];
 335
 336         u8         reserved_at_40[0x40];
 337
 338         u8         rx_ack_packets[0x40];
 339
 340         u8         rx_send_packets[0x40];
 341
 342         u8         tx_ack_packets[0x40];
 343
 344         u8         tx_send_packets[0x40];
 345
 346         u8         rx_total_drop[0x40];
 347
 348         u8         reserved_at_1c0[0x1c0];
 349 };
 350
 351 struct mlx5_ifc_fpga_destroy_qp_in_bits {
 352         u8         opcode[0x10];
 353         u8         reserved_at_10[0x10];
 354
 355         u8         reserved_at_20[0x10];
 356         u8         op_mod[0x10];
 357
 358         u8         reserved_at_40[0x8];
 359         u8         fpga_qpn[0x18];
 360
 361         u8         reserved_at_60[0x20];
 362 };
 363
 364 struct mlx5_ifc_fpga_destroy_qp_out_bits {
 365         u8         status[0x8];
 366         u8         reserved_at_8[0x18];
 367
 368         u8         syndrome[0x20];
 369
 370         u8         reserved_at_40[0x40];
 371 };
 372
 373 struct mlx5_ifc_ipsec_extended_cap_bits {
 374         u8         encapsulation[0x20];
 375
 376         u8         reserved_0[0x15];
 377         u8         ipv4_fragment[0x1];
 378         u8         ipv6[0x1];
 379         u8         esn[0x1];
 380         u8         lso[0x1];
 381         u8         transport_and_tunnel_mode[0x1];
 382         u8         tunnel_mode[0x1];
 383         u8         transport_mode[0x1];
 384         u8         ah_esp[0x1];
 385         u8         esp[0x1];
 386         u8         ah[0x1];
 387         u8         ipv4_options[0x1];
 388
 389         u8         auth_alg[0x20];
 390
 391         u8         enc_alg[0x20];
 392
 393         u8         sa_cap[0x20];
 394
 395         u8         reserved_1[0x10];
 396         u8         number_of_ipsec_counters[0x10];
 397
 398         u8         ipsec_counters_addr_low[0x20];
 399         u8         ipsec_counters_addr_high[0x20];
 400 };
 401
 402 struct mlx5_ifc_ipsec_counters_bits {
 403         u8         dec_in_packets[0x40];
 404
 405         u8         dec_out_packets[0x40];
 406
 407         u8         dec_bypass_packets[0x40];
 408
 409         u8         enc_in_packets[0x40];
 410
 411         u8         enc_out_packets[0x40];
 412
 413         u8         enc_bypass_packets[0x40];
 414
 415         u8         drop_dec_packets[0x40];
 416
 417         u8         failed_auth_dec_packets[0x40];
 418
 419         u8         drop_enc_packets[0x40];
 420
 421         u8         success_add_sa[0x40];
 422
 423         u8         fail_add_sa[0x40];
 424
 425         u8         success_delete_sa[0x40];
 426
 427         u8         fail_delete_sa[0x40];
 428
 429         u8         dropped_cmd[0x40];
 430 };
 431
 432 #endif /* MLX5_IFC_FPGA_H */