2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_INVALID_LKEY 0x100
40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_DIF_SIZE 8
42 #define MLX5_STRIDE_BLOCK_OP 0x400
43 #define MLX5_CPY_GRD_MASK 0xc0
44 #define MLX5_CPY_APP_MASK 0x30
45 #define MLX5_CPY_REF_MASK 0x0f
46 #define MLX5_BSF_INC_REFTAG (1 << 6)
47 #define MLX5_BSF_INL_VALID (1 << 15)
48 #define MLX5_BSF_REFRESH_DIF (1 << 14)
49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
50 #define MLX5_BSF_APPTAG_ESCAPE 0x1
51 #define MLX5_BSF_APPREF_ESCAPE 0x2
53 #define MLX5_QPN_BITS 24
54 #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1)
57 MLX5_QP_OPTPAR_ALT_ADDR_PATH
= 1 << 0,
58 MLX5_QP_OPTPAR_RRE
= 1 << 1,
59 MLX5_QP_OPTPAR_RAE
= 1 << 2,
60 MLX5_QP_OPTPAR_RWE
= 1 << 3,
61 MLX5_QP_OPTPAR_PKEY_INDEX
= 1 << 4,
62 MLX5_QP_OPTPAR_Q_KEY
= 1 << 5,
63 MLX5_QP_OPTPAR_RNR_TIMEOUT
= 1 << 6,
64 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH
= 1 << 7,
65 MLX5_QP_OPTPAR_SRA_MAX
= 1 << 8,
66 MLX5_QP_OPTPAR_RRA_MAX
= 1 << 9,
67 MLX5_QP_OPTPAR_PM_STATE
= 1 << 10,
68 MLX5_QP_OPTPAR_RETRY_COUNT
= 1 << 12,
69 MLX5_QP_OPTPAR_RNR_RETRY
= 1 << 13,
70 MLX5_QP_OPTPAR_ACK_TIMEOUT
= 1 << 14,
71 MLX5_QP_OPTPAR_PRI_PORT
= 1 << 16,
72 MLX5_QP_OPTPAR_SRQN
= 1 << 18,
73 MLX5_QP_OPTPAR_CQN_RCV
= 1 << 19,
74 MLX5_QP_OPTPAR_DC_HS
= 1 << 20,
75 MLX5_QP_OPTPAR_DC_KEY
= 1 << 21,
79 MLX5_QP_STATE_RST
= 0,
80 MLX5_QP_STATE_INIT
= 1,
81 MLX5_QP_STATE_RTR
= 2,
82 MLX5_QP_STATE_RTS
= 3,
83 MLX5_QP_STATE_SQER
= 4,
84 MLX5_QP_STATE_SQD
= 5,
85 MLX5_QP_STATE_ERR
= 6,
86 MLX5_QP_STATE_SQ_DRAINING
= 7,
87 MLX5_QP_STATE_SUSPENDED
= 9,
100 MLX5_QP_ST_QP1
= 0x8,
101 MLX5_QP_ST_RAW_ETHERTYPE
= 0x9,
102 MLX5_QP_ST_RAW_IPV6
= 0xa,
103 MLX5_QP_ST_SNIFFER
= 0xb,
104 MLX5_QP_ST_SYNC_UMR
= 0xe,
105 MLX5_QP_ST_PTP_1588
= 0xd,
106 MLX5_QP_ST_REG_UMR
= 0xc,
111 MLX5_QP_PM_MIGRATED
= 0x3,
112 MLX5_QP_PM_ARMED
= 0x0,
113 MLX5_QP_PM_REARM
= 0x1
117 MLX5_NON_ZERO_RQ
= 0 << 24,
118 MLX5_SRQ_RQ
= 1 << 24,
119 MLX5_CRQ_RQ
= 2 << 24,
120 MLX5_ZERO_LEN_RQ
= 3 << 24
125 MLX5_QP_BIT_SRE
= 1 << 15,
126 MLX5_QP_BIT_SWE
= 1 << 14,
127 MLX5_QP_BIT_SAE
= 1 << 13,
129 MLX5_QP_BIT_RRE
= 1 << 15,
130 MLX5_QP_BIT_RWE
= 1 << 14,
131 MLX5_QP_BIT_RAE
= 1 << 13,
132 MLX5_QP_BIT_RIC
= 1 << 4,
136 MLX5_WQE_CTRL_CQ_UPDATE
= 2 << 2,
137 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE
= 3 << 2,
138 MLX5_WQE_CTRL_SOLICITED
= 1 << 1,
142 MLX5_SEND_WQE_DS
= 16,
143 MLX5_SEND_WQE_BB
= 64,
146 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
149 MLX5_SEND_WQE_MAX_WQEBBS
= 16,
153 MLX5_WQE_FMR_PERM_LOCAL_READ
= 1 << 27,
154 MLX5_WQE_FMR_PERM_LOCAL_WRITE
= 1 << 28,
155 MLX5_WQE_FMR_PERM_REMOTE_READ
= 1 << 29,
156 MLX5_WQE_FMR_PERM_REMOTE_WRITE
= 1 << 30,
157 MLX5_WQE_FMR_PERM_ATOMIC
= 1 << 31
161 MLX5_FENCE_MODE_NONE
= 0 << 5,
162 MLX5_FENCE_MODE_INITIATOR_SMALL
= 1 << 5,
163 MLX5_FENCE_MODE_STRONG_ORDERING
= 3 << 5,
164 MLX5_FENCE_MODE_SMALL_AND_FENCE
= 4 << 5,
168 MLX5_QP_LAT_SENSITIVE
= 1 << 28,
169 MLX5_QP_BLOCK_MCAST
= 1 << 30,
170 MLX5_QP_ENABLE_SIG
= 1 << 31,
179 MLX5_FLAGS_INLINE
= 1<<7,
180 MLX5_FLAGS_CHECK_FREE
= 1<<5,
183 struct mlx5_wqe_fmr_seg
{
194 struct mlx5_wqe_ctrl_seg
{
195 __be32 opmod_idx_opcode
;
203 #define MLX5_WQE_CTRL_DS_MASK 0x3f
204 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
205 #define MLX5_WQE_CTRL_QPN_SHIFT 8
206 #define MLX5_WQE_DS_UNITS 16
207 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
208 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
209 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
212 MLX5_ETH_WQE_L3_INNER_CSUM
= 1 << 4,
213 MLX5_ETH_WQE_L4_INNER_CSUM
= 1 << 5,
214 MLX5_ETH_WQE_L3_CSUM
= 1 << 6,
215 MLX5_ETH_WQE_L4_CSUM
= 1 << 7,
218 struct mlx5_wqe_eth_seg
{
224 __be16 inline_hdr_sz
;
225 u8 inline_hdr_start
[2];
228 struct mlx5_wqe_xrc_seg
{
233 struct mlx5_wqe_masked_atomic_seg
{
236 __be64 swap_add_mask
;
259 struct mlx5_wqe_datagram_seg
{
263 struct mlx5_wqe_raddr_seg
{
269 struct mlx5_wqe_atomic_seg
{
274 struct mlx5_wqe_data_seg
{
280 struct mlx5_wqe_umr_ctrl_seg
{
283 __be16 klm_octowords
;
284 __be16 bsf_octowords
;
289 struct mlx5_seg_set_psv
{
293 __be32 transient_sig
;
297 struct mlx5_seg_get_psv
{
305 struct mlx5_seg_check_psv
{
307 __be16 err_coalescing_op
;
311 __be16 xport_err_mask
;
319 struct mlx5_rwqe_sig
{
325 struct mlx5_wqe_signature_seg
{
331 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
333 struct mlx5_wqe_inline_seg
{
342 struct mlx5_bsf_inl
{
349 u8 dif_inc_ref_guard_check
;
350 __be16 dif_app_bitmask_check
;
354 struct mlx5_bsf_basic
{
366 __be32 raw_data_size
;
370 struct mlx5_bsf_ext
{
371 __be32 t_init_gen_pro_size
;
372 __be32 rsvd_epi_size
;
376 struct mlx5_bsf_inl w_inl
;
377 struct mlx5_bsf_inl m_inl
;
386 struct mlx5_stride_block_entry
{
393 struct mlx5_stride_block_ctrl_seg
{
394 __be32 bcount_per_cycle
;
401 enum mlx5_pagefault_flags
{
402 MLX5_PFAULT_REQUESTOR
= 1 << 0,
403 MLX5_PFAULT_WRITE
= 1 << 1,
404 MLX5_PFAULT_RDMA
= 1 << 2,
407 /* Contains the details of a pagefault. */
408 struct mlx5_pagefault
{
411 enum mlx5_pagefault_flags flags
;
413 /* Initiator or send message responder pagefault details. */
415 /* Received packet size, only valid for responders. */
418 * WQE index. Refers to either the send queue or
419 * receive queue, according to event_subtype.
423 /* RDMA responder pagefault details */
427 * Received packet size, minimal size page fault
428 * resolution required for forward progress.
437 struct mlx5_core_qp
{
438 struct mlx5_core_rsc_common common
; /* must be first */
439 void (*event
) (struct mlx5_core_qp
*, int);
440 void (*pfault_handler
)(struct mlx5_core_qp
*, struct mlx5_pagefault
*);
442 struct mlx5_rsc_debug
*dbg
;
446 struct mlx5_qp_path
{
458 __be32 tclass_flowlabel
;
466 struct mlx5_qp_context
{
472 __be32 qp_counter_set_usr_page
;
474 __be32 log_pg_sz_remote_qpn
;
475 struct mlx5_qp_path pri_path
;
476 struct mlx5_qp_path alt_path
;
479 __be32 next_send_psn
;
482 __be32 last_acked_psn
;
485 __be32 rnr_nextrecvpsn
;
492 __be16 hw_sq_wqe_counter
;
493 __be16 sw_sq_wqe_counter
;
494 __be16 hw_rcyclic_byte_counter
;
495 __be16 hw_rq_counter
;
496 __be16 sw_rcyclic_byte_counter
;
497 __be16 sw_rq_counter
;
502 __be64 dc_access_key
;
506 struct mlx5_create_qp_mbox_in
{
507 struct mlx5_inbox_hdr hdr
;
510 __be32 opt_param_mask
;
512 struct mlx5_qp_context ctx
;
517 struct mlx5_create_qp_mbox_out
{
518 struct mlx5_outbox_hdr hdr
;
523 struct mlx5_destroy_qp_mbox_in
{
524 struct mlx5_inbox_hdr hdr
;
529 struct mlx5_destroy_qp_mbox_out
{
530 struct mlx5_outbox_hdr hdr
;
534 struct mlx5_modify_qp_mbox_in
{
535 struct mlx5_inbox_hdr hdr
;
540 struct mlx5_qp_context ctx
;
543 struct mlx5_modify_qp_mbox_out
{
544 struct mlx5_outbox_hdr hdr
;
548 struct mlx5_query_qp_mbox_in
{
549 struct mlx5_inbox_hdr hdr
;
554 struct mlx5_query_qp_mbox_out
{
555 struct mlx5_outbox_hdr hdr
;
559 struct mlx5_qp_context ctx
;
564 struct mlx5_conf_sqp_mbox_in
{
565 struct mlx5_inbox_hdr hdr
;
571 struct mlx5_conf_sqp_mbox_out
{
572 struct mlx5_outbox_hdr hdr
;
576 struct mlx5_alloc_xrcd_mbox_in
{
577 struct mlx5_inbox_hdr hdr
;
581 struct mlx5_alloc_xrcd_mbox_out
{
582 struct mlx5_outbox_hdr hdr
;
587 struct mlx5_dealloc_xrcd_mbox_in
{
588 struct mlx5_inbox_hdr hdr
;
593 struct mlx5_dealloc_xrcd_mbox_out
{
594 struct mlx5_outbox_hdr hdr
;
598 static inline struct mlx5_core_qp
*__mlx5_qp_lookup(struct mlx5_core_dev
*dev
, u32 qpn
)
600 return radix_tree_lookup(&dev
->priv
.qp_table
.tree
, qpn
);
603 static inline struct mlx5_core_mr
*__mlx5_mr_lookup(struct mlx5_core_dev
*dev
, u32 key
)
605 return radix_tree_lookup(&dev
->priv
.mr_table
.tree
, key
);
608 struct mlx5_page_fault_resume_mbox_in
{
609 struct mlx5_inbox_hdr hdr
;
614 struct mlx5_page_fault_resume_mbox_out
{
615 struct mlx5_outbox_hdr hdr
;
619 int mlx5_core_create_qp(struct mlx5_core_dev
*dev
,
620 struct mlx5_core_qp
*qp
,
621 struct mlx5_create_qp_mbox_in
*in
,
623 int mlx5_core_qp_modify(struct mlx5_core_dev
*dev
, enum mlx5_qp_state cur_state
,
624 enum mlx5_qp_state new_state
,
625 struct mlx5_modify_qp_mbox_in
*in
, int sqd_event
,
626 struct mlx5_core_qp
*qp
);
627 int mlx5_core_destroy_qp(struct mlx5_core_dev
*dev
,
628 struct mlx5_core_qp
*qp
);
629 int mlx5_core_qp_query(struct mlx5_core_dev
*dev
, struct mlx5_core_qp
*qp
,
630 struct mlx5_query_qp_mbox_out
*out
, int outlen
);
632 int mlx5_core_xrcd_alloc(struct mlx5_core_dev
*dev
, u32
*xrcdn
);
633 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev
*dev
, u32 xrcdn
);
634 void mlx5_init_qp_table(struct mlx5_core_dev
*dev
);
635 void mlx5_cleanup_qp_table(struct mlx5_core_dev
*dev
);
636 int mlx5_debug_qp_add(struct mlx5_core_dev
*dev
, struct mlx5_core_qp
*qp
);
637 void mlx5_debug_qp_remove(struct mlx5_core_dev
*dev
, struct mlx5_core_qp
*qp
);
638 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
639 int mlx5_core_page_fault_resume(struct mlx5_core_dev
*dev
, u32 qpn
,
640 u8 context
, int error
);
643 static inline const char *mlx5_qp_type_str(int type
)
646 case MLX5_QP_ST_RC
: return "RC";
647 case MLX5_QP_ST_UC
: return "C";
648 case MLX5_QP_ST_UD
: return "UD";
649 case MLX5_QP_ST_XRC
: return "XRC";
650 case MLX5_QP_ST_MLX
: return "MLX";
651 case MLX5_QP_ST_QP0
: return "QP0";
652 case MLX5_QP_ST_QP1
: return "QP1";
653 case MLX5_QP_ST_RAW_ETHERTYPE
: return "RAW_ETHERTYPE";
654 case MLX5_QP_ST_RAW_IPV6
: return "RAW_IPV6";
655 case MLX5_QP_ST_SNIFFER
: return "SNIFFER";
656 case MLX5_QP_ST_SYNC_UMR
: return "SYNC_UMR";
657 case MLX5_QP_ST_PTP_1588
: return "PTP_1588";
658 case MLX5_QP_ST_REG_UMR
: return "REG_UMR";
659 default: return "Invalid transport type";
663 static inline const char *mlx5_qp_state_str(int state
)
666 case MLX5_QP_STATE_RST
:
668 case MLX5_QP_STATE_INIT
:
670 case MLX5_QP_STATE_RTR
:
672 case MLX5_QP_STATE_RTS
:
674 case MLX5_QP_STATE_SQER
:
676 case MLX5_QP_STATE_SQD
:
678 case MLX5_QP_STATE_ERR
:
680 case MLX5_QP_STATE_SQ_DRAINING
:
681 return "SQ_DRAINING";
682 case MLX5_QP_STATE_SUSPENDED
:
684 default: return "Invalid QP state";
688 #endif /* MLX5_QP_H */