include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   5  *                        Steven J. Hill <sjhill@realitydiluted.com>
   6  *                        Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Info:
  13  *      Contains standard defines and IDs for NAND flash devices
  14  *
  15  * Changelog:
  16  *      See git changelog.
  17  */
  18 #ifndef __LINUX_MTD_NAND_H
  19 #define __LINUX_MTD_NAND_H
  20
  21 #include <linux/wait.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/flashchip.h>
  25 #include <linux/mtd/bbm.h>
  26
  27 struct mtd_info;
  28 struct nand_flash_dev;
  29 /* Scan and identify a NAND device */
  30 extern int nand_scan(struct mtd_info *mtd, int max_chips);
  31 /*
  32  * Separate phases of nand_scan(), allowing board driver to intervene
  33  * and override command or ECC setup according to flash type.
  34  */
  35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  36                            struct nand_flash_dev *table);
  37 extern int nand_scan_tail(struct mtd_info *mtd);
  38
  39 /* Free resources held by the NAND device */
  40 extern void nand_release(struct mtd_info *mtd);
  41
  42 /* Internal helper for board drivers which need to override command function */
  43 extern void nand_wait_ready(struct mtd_info *mtd);
  44
  45 /* locks all blocks present in the device */
  46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  47
  48 /* unlocks specified locked blocks */
  49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  50
  51 /* The maximum number of NAND chips in an array */
  52 #define NAND_MAX_CHIPS          8
  53
  54 /*
  55  * Constants for hardware specific CLE/ALE/NCE function
  56  *
  57  * These are bits which can be or'ed to set/clear multiple
  58  * bits in one go.
  59  */
  60 /* Select the chip by setting nCE to low */
  61 #define NAND_NCE                0x01
  62 /* Select the command latch by setting CLE to high */
  63 #define NAND_CLE                0x02
  64 /* Select the address latch by setting ALE to high */
  65 #define NAND_ALE                0x04
  66
  67 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  68 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  69 #define NAND_CTRL_CHANGE        0x80
  70
  71 /*
  72  * Standard NAND flash commands
  73  */
  74 #define NAND_CMD_READ0          0
  75 #define NAND_CMD_READ1          1
  76 #define NAND_CMD_RNDOUT         5
  77 #define NAND_CMD_PAGEPROG       0x10
  78 #define NAND_CMD_READOOB        0x50
  79 #define NAND_CMD_ERASE1         0x60
  80 #define NAND_CMD_STATUS         0x70
  81 #define NAND_CMD_SEQIN          0x80
  82 #define NAND_CMD_RNDIN          0x85
  83 #define NAND_CMD_READID         0x90
  84 #define NAND_CMD_ERASE2         0xd0
  85 #define NAND_CMD_PARAM          0xec
  86 #define NAND_CMD_GET_FEATURES   0xee
  87 #define NAND_CMD_SET_FEATURES   0xef
  88 #define NAND_CMD_RESET          0xff
  89
  90 #define NAND_CMD_LOCK           0x2a
  91 #define NAND_CMD_UNLOCK1        0x23
  92 #define NAND_CMD_UNLOCK2        0x24
  93
  94 /* Extended commands for large page devices */
  95 #define NAND_CMD_READSTART      0x30
  96 #define NAND_CMD_RNDOUTSTART    0xE0
  97 #define NAND_CMD_CACHEDPROG     0x15
  98
  99 #define NAND_CMD_NONE           -1
 100
 101 /* Status bits */
 102 #define NAND_STATUS_FAIL        0x01
 103 #define NAND_STATUS_FAIL_N1     0x02
 104 #define NAND_STATUS_TRUE_READY  0x20
 105 #define NAND_STATUS_READY       0x40
 106 #define NAND_STATUS_WP          0x80
 107
 108 /*
 109  * Constants for ECC_MODES
 110  */
 111 typedef enum {
 112         NAND_ECC_NONE,
 113         NAND_ECC_SOFT,
 114         NAND_ECC_HW,
 115         NAND_ECC_HW_SYNDROME,
 116         NAND_ECC_HW_OOB_FIRST,
 117         NAND_ECC_SOFT_BCH,
 118 } nand_ecc_modes_t;
 119
 120 /*
 121  * Constants for Hardware ECC
 122  */
 123 /* Reset Hardware ECC for read */
 124 #define NAND_ECC_READ           0
 125 /* Reset Hardware ECC for write */
 126 #define NAND_ECC_WRITE          1
 127 /* Enable Hardware ECC before syndrome is read back from flash */
 128 #define NAND_ECC_READSYN        2
 129
 130 /* Bit mask for flags passed to do_nand_read_ecc */
 131 #define NAND_GET_DEVICE         0x80
 132
 133
 134 /*
 135  * Option constants for bizarre disfunctionality and real
 136  * features.
 137  */
 138 /* Buswidth is 16 bit */
 139 #define NAND_BUSWIDTH_16        0x00000002
 140 /* Chip has cache program function */
 141 #define NAND_CACHEPRG           0x00000008
 142 /*
 143  * Chip requires ready check on read (for auto-incremented sequential read).
 144  * True only for small page devices; large page devices do not support
 145  * autoincrement.
 146  */
 147 #define NAND_NEED_READRDY       0x00000100
 148
 149 /* Chip does not allow subpage writes */
 150 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 151
 152 /* Device is one of 'new' xD cards that expose fake nand command set */
 153 #define NAND_BROKEN_XD          0x00000400
 154
 155 /* Device behaves just like nand, but is readonly */
 156 #define NAND_ROM                0x00000800
 157
 158 /* Device supports subpage reads */
 159 #define NAND_SUBPAGE_READ       0x00001000
 160
 161 /* Options valid for Samsung large page devices */
 162 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
 163
 164 /* Macros to identify the above */
 165 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 166 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 167
 168 /* Non chip related options */
 169 /* This option skips the bbt scan during initialization. */
 170 #define NAND_SKIP_BBTSCAN       0x00010000
 171 /*
 172  * This option is defined if the board driver allocates its own buffers
 173  * (e.g. because it needs them DMA-coherent).
 174  */
 175 #define NAND_OWN_BUFFERS        0x00020000
 176 /* Chip may not exist, so silence any errors in scan */
 177 #define NAND_SCAN_SILENT_NODEV  0x00040000
 178 /*
 179  * This option could be defined by controller drivers to protect against
 180  * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
 181  */
 182 #define NAND_USE_BOUNCE_BUFFER  0x00080000
 183 /*
 184  * Autodetect nand buswidth with readid/onfi.
 185  * This suppose the driver will configure the hardware in 8 bits mode
 186  * when calling nand_scan_ident, and update its configuration
 187  * before calling nand_scan_tail.
 188  */
 189 #define NAND_BUSWIDTH_AUTO      0x00080000
 190
 191 /* Options set by nand scan */
 192 /* Nand scan has allocated controller struct */
 193 #define NAND_CONTROLLER_ALLOC   0x80000000
 194
 195 /* Cell info constants */
 196 #define NAND_CI_CHIPNR_MSK      0x03
 197 #define NAND_CI_CELLTYPE_MSK    0x0C
 198 #define NAND_CI_CELLTYPE_SHIFT  2
 199
 200 /* Keep gcc happy */
 201 struct nand_chip;
 202
 203 /* ONFI features */
 204 #define ONFI_FEATURE_16_BIT_BUS         (1 << 0)
 205 #define ONFI_FEATURE_EXT_PARAM_PAGE     (1 << 7)
 206
 207 /* ONFI timing mode, used in both asynchronous and synchronous mode */
 208 #define ONFI_TIMING_MODE_0              (1 << 0)
 209 #define ONFI_TIMING_MODE_1              (1 << 1)
 210 #define ONFI_TIMING_MODE_2              (1 << 2)
 211 #define ONFI_TIMING_MODE_3              (1 << 3)
 212 #define ONFI_TIMING_MODE_4              (1 << 4)
 213 #define ONFI_TIMING_MODE_5              (1 << 5)
 214 #define ONFI_TIMING_MODE_UNKNOWN        (1 << 6)
 215
 216 /* ONFI feature address */
 217 #define ONFI_FEATURE_ADDR_TIMING_MODE   0x1
 218
 219 /* Vendor-specific feature address (Micron) */
 220 #define ONFI_FEATURE_ADDR_READ_RETRY    0x89
 221
 222 /* ONFI subfeature parameters length */
 223 #define ONFI_SUBFEATURE_PARAM_LEN       4
 224
 225 /* ONFI optional commands SET/GET FEATURES supported? */
 226 #define ONFI_OPT_CMD_SET_GET_FEATURES   (1 << 2)
 227
 228 struct nand_onfi_params {
 229         /* rev info and features block */
 230         /* 'O' 'N' 'F' 'I'  */
 231         u8 sig[4];
 232         __le16 revision;
 233         __le16 features;
 234         __le16 opt_cmd;
 235         u8 reserved0[2];
 236         __le16 ext_param_page_length; /* since ONFI 2.1 */
 237         u8 num_of_param_pages;        /* since ONFI 2.1 */
 238         u8 reserved1[17];
 239
 240         /* manufacturer information block */
 241         char manufacturer[12];
 242         char model[20];
 243         u8 jedec_id;
 244         __le16 date_code;
 245         u8 reserved2[13];
 246
 247         /* memory organization block */
 248         __le32 byte_per_page;
 249         __le16 spare_bytes_per_page;
 250         __le32 data_bytes_per_ppage;
 251         __le16 spare_bytes_per_ppage;
 252         __le32 pages_per_block;
 253         __le32 blocks_per_lun;
 254         u8 lun_count;
 255         u8 addr_cycles;
 256         u8 bits_per_cell;
 257         __le16 bb_per_lun;
 258         __le16 block_endurance;
 259         u8 guaranteed_good_blocks;
 260         __le16 guaranteed_block_endurance;
 261         u8 programs_per_page;
 262         u8 ppage_attr;
 263         u8 ecc_bits;
 264         u8 interleaved_bits;
 265         u8 interleaved_ops;
 266         u8 reserved3[13];
 267
 268         /* electrical parameter block */
 269         u8 io_pin_capacitance_max;
 270         __le16 async_timing_mode;
 271         __le16 program_cache_timing_mode;
 272         __le16 t_prog;
 273         __le16 t_bers;
 274         __le16 t_r;
 275         __le16 t_ccs;
 276         __le16 src_sync_timing_mode;
 277         __le16 src_ssync_features;
 278         __le16 clk_pin_capacitance_typ;
 279         __le16 io_pin_capacitance_typ;
 280         __le16 input_pin_capacitance_typ;
 281         u8 input_pin_capacitance_max;
 282         u8 driver_strength_support;
 283         __le16 t_int_r;
 284         __le16 t_ald;
 285         u8 reserved4[7];
 286
 287         /* vendor */
 288         __le16 vendor_revision;
 289         u8 vendor[88];
 290
 291         __le16 crc;
 292 } __packed;
 293
 294 #define ONFI_CRC_BASE   0x4F4E
 295
 296 /* Extended ECC information Block Definition (since ONFI 2.1) */
 297 struct onfi_ext_ecc_info {
 298         u8 ecc_bits;
 299         u8 codeword_size;
 300         __le16 bb_per_lun;
 301         __le16 block_endurance;
 302         u8 reserved[2];
 303 } __packed;
 304
 305 #define ONFI_SECTION_TYPE_0     0       /* Unused section. */
 306 #define ONFI_SECTION_TYPE_1     1       /* for additional sections. */
 307 #define ONFI_SECTION_TYPE_2     2       /* for ECC information. */
 308 struct onfi_ext_section {
 309         u8 type;
 310         u8 length;
 311 } __packed;
 312
 313 #define ONFI_EXT_SECTION_MAX 8
 314
 315 /* Extended Parameter Page Definition (since ONFI 2.1) */
 316 struct onfi_ext_param_page {
 317         __le16 crc;
 318         u8 sig[4];             /* 'E' 'P' 'P' 'S' */
 319         u8 reserved0[10];
 320         struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
 321
 322         /*
 323          * The actual size of the Extended Parameter Page is in
 324          * @ext_param_page_length of nand_onfi_params{}.
 325          * The following are the variable length sections.
 326          * So we do not add any fields below. Please see the ONFI spec.
 327          */
 328 } __packed;
 329
 330 struct nand_onfi_vendor_micron {
 331         u8 two_plane_read;
 332         u8 read_cache;
 333         u8 read_unique_id;
 334         u8 dq_imped;
 335         u8 dq_imped_num_settings;
 336         u8 dq_imped_feat_addr;
 337         u8 rb_pulldown_strength;
 338         u8 rb_pulldown_strength_feat_addr;
 339         u8 rb_pulldown_strength_num_settings;
 340         u8 otp_mode;
 341         u8 otp_page_start;
 342         u8 otp_data_prot_addr;
 343         u8 otp_num_pages;
 344         u8 otp_feat_addr;
 345         u8 read_retry_options;
 346         u8 reserved[72];
 347         u8 param_revision;
 348 } __packed;
 349
 350 struct jedec_ecc_info {
 351         u8 ecc_bits;
 352         u8 codeword_size;
 353         __le16 bb_per_lun;
 354         __le16 block_endurance;
 355         u8 reserved[2];
 356 } __packed;
 357
 358 /* JEDEC features */
 359 #define JEDEC_FEATURE_16_BIT_BUS        (1 << 0)
 360
 361 struct nand_jedec_params {
 362         /* rev info and features block */
 363         /* 'J' 'E' 'S' 'D'  */
 364         u8 sig[4];
 365         __le16 revision;
 366         __le16 features;
 367         u8 opt_cmd[3];
 368         __le16 sec_cmd;
 369         u8 num_of_param_pages;
 370         u8 reserved0[18];
 371
 372         /* manufacturer information block */
 373         char manufacturer[12];
 374         char model[20];
 375         u8 jedec_id[6];
 376         u8 reserved1[10];
 377
 378         /* memory organization block */
 379         __le32 byte_per_page;
 380         __le16 spare_bytes_per_page;
 381         u8 reserved2[6];
 382         __le32 pages_per_block;
 383         __le32 blocks_per_lun;
 384         u8 lun_count;
 385         u8 addr_cycles;
 386         u8 bits_per_cell;
 387         u8 programs_per_page;
 388         u8 multi_plane_addr;
 389         u8 multi_plane_op_attr;
 390         u8 reserved3[38];
 391
 392         /* electrical parameter block */
 393         __le16 async_sdr_speed_grade;
 394         __le16 toggle_ddr_speed_grade;
 395         __le16 sync_ddr_speed_grade;
 396         u8 async_sdr_features;
 397         u8 toggle_ddr_features;
 398         u8 sync_ddr_features;
 399         __le16 t_prog;
 400         __le16 t_bers;
 401         __le16 t_r;
 402         __le16 t_r_multi_plane;
 403         __le16 t_ccs;
 404         __le16 io_pin_capacitance_typ;
 405         __le16 input_pin_capacitance_typ;
 406         __le16 clk_pin_capacitance_typ;
 407         u8 driver_strength_support;
 408         __le16 t_ald;
 409         u8 reserved4[36];
 410
 411         /* ECC and endurance block */
 412         u8 guaranteed_good_blocks;
 413         __le16 guaranteed_block_endurance;
 414         struct jedec_ecc_info ecc_info[4];
 415         u8 reserved5[29];
 416
 417         /* reserved */
 418         u8 reserved6[148];
 419
 420         /* vendor */
 421         __le16 vendor_rev_num;
 422         u8 reserved7[88];
 423
 424         /* CRC for Parameter Page */
 425         __le16 crc;
 426 } __packed;
 427
 428 /**
 429  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 430  * @lock:               protection lock
 431  * @active:             the mtd device which holds the controller currently
 432  * @wq:                 wait queue to sleep on if a NAND operation is in
 433  *                      progress used instead of the per chip wait queue
 434  *                      when a hw controller is available.
 435  */
 436 struct nand_hw_control {
 437         spinlock_t lock;
 438         struct nand_chip *active;
 439         wait_queue_head_t wq;
 440 };
 441
 442 /**
 443  * struct nand_ecc_ctrl - Control structure for ECC
 444  * @mode:       ECC mode
 445  * @steps:      number of ECC steps per page
 446  * @size:       data bytes per ECC step
 447  * @bytes:      ECC bytes per step
 448  * @strength:   max number of correctible bits per ECC step
 449  * @total:      total number of ECC bytes per page
 450  * @prepad:     padding information for syndrome based ECC generators
 451  * @postpad:    padding information for syndrome based ECC generators
 452  * @layout:     ECC layout control struct pointer
 453  * @priv:       pointer to private ECC control data
 454  * @hwctl:      function to control hardware ECC generator. Must only
 455  *              be provided if an hardware ECC is available
 456  * @calculate:  function for ECC calculation or readback from ECC hardware
 457  * @correct:    function for ECC correction, matching to ECC generator (sw/hw)
 458  * @read_page_raw:      function to read a raw page without ECC. This function
 459  *                      should hide the specific layout used by the ECC
 460  *                      controller and always return contiguous in-band and
 461  *                      out-of-band data even if they're not stored
 462  *                      contiguously on the NAND chip (e.g.
 463  *                      NAND_ECC_HW_SYNDROME interleaves in-band and
 464  *                      out-of-band data).
 465  * @write_page_raw:     function to write a raw page without ECC. This function
 466  *                      should hide the specific layout used by the ECC
 467  *                      controller and consider the passed data as contiguous
 468  *                      in-band and out-of-band data. ECC controller is
 469  *                      responsible for doing the appropriate transformations
 470  *                      to adapt to its specific layout (e.g.
 471  *                      NAND_ECC_HW_SYNDROME interleaves in-band and
 472  *                      out-of-band data).
 473  * @read_page:  function to read a page according to the ECC generator
 474  *              requirements; returns maximum number of bitflips corrected in
 475  *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
 476  * @read_subpage:       function to read parts of the page covered by ECC;
 477  *                      returns same as read_page()
 478  * @write_subpage:      function to write parts of the page covered by ECC.
 479  * @write_page: function to write a page according to the ECC generator
 480  *              requirements.
 481  * @write_oob_raw:      function to write chip OOB data without ECC
 482  * @read_oob_raw:       function to read chip OOB data without ECC
 483  * @read_oob:   function to read chip OOB data
 484  * @write_oob:  function to write chip OOB data
 485  */
 486 struct nand_ecc_ctrl {
 487         nand_ecc_modes_t mode;
 488         int steps;
 489         int size;
 490         int bytes;
 491         int total;
 492         int strength;
 493         int prepad;
 494         int postpad;
 495         struct nand_ecclayout   *layout;
 496         void *priv;
 497         void (*hwctl)(struct mtd_info *mtd, int mode);
 498         int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 499                         uint8_t *ecc_code);
 500         int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 501                         uint8_t *calc_ecc);
 502         int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 503                         uint8_t *buf, int oob_required, int page);
 504         int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 505                         const uint8_t *buf, int oob_required);
 506         int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 507                         uint8_t *buf, int oob_required, int page);
 508         int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 509                         uint32_t offs, uint32_t len, uint8_t *buf, int page);
 510         int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 511                         uint32_t offset, uint32_t data_len,
 512                         const uint8_t *data_buf, int oob_required);
 513         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 514                         const uint8_t *buf, int oob_required);
 515         int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 516                         int page);
 517         int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 518                         int page);
 519         int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
 520         int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 521                         int page);
 522 };
 523
 524 /**
 525  * struct nand_buffers - buffer structure for read/write
 526  * @ecccalc:    buffer pointer for calculated ECC, size is oobsize.
 527  * @ecccode:    buffer pointer for ECC read from flash, size is oobsize.
 528  * @databuf:    buffer pointer for data, size is (page size + oobsize).
 529  *
 530  * Do not change the order of buffers. databuf and oobrbuf must be in
 531  * consecutive order.
 532  */
 533 struct nand_buffers {
 534         uint8_t *ecccalc;
 535         uint8_t *ecccode;
 536         uint8_t *databuf;
 537 };
 538
 539 /**
 540  * struct nand_chip - NAND Private Flash Chip Data
 541  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
 542  *                      flash device
 543  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
 544  *                      flash device.
 545  * @read_byte:          [REPLACEABLE] read one byte from the chip
 546  * @read_word:          [REPLACEABLE] read one word from the chip
 547  * @write_byte:         [REPLACEABLE] write a single byte to the chip on the
 548  *                      low 8 I/O lines
 549  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 550  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 551  * @select_chip:        [REPLACEABLE] select chip nr
 552  * @block_bad:          [REPLACEABLE] check if a block is bad, using OOB markers
 553  * @block_markbad:      [REPLACEABLE] mark a block bad
 554  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
 555  *                      ALE/CLE/nCE. Also used to write command and address
 556  * @init_size:          [BOARDSPECIFIC] hardwarespecific function for setting
 557  *                      mtd->oobsize, mtd->writesize and so on.
 558  *                      @id_data contains the 8 bytes values of NAND_CMD_READID.
 559  *                      Return with the bus width.
 560  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accessing
 561  *                      device ready/busy line. If set to NULL no access to
 562  *                      ready/busy is available and the ready/busy information
 563  *                      is read from the chip status register.
 564  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
 565  *                      commands to the chip.
 566  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
 567  *                      ready.
 568  * @setup_read_retry:   [FLASHSPECIFIC] flash (vendor) specific function for
 569  *                      setting the read-retry mode. Mostly needed for MLC NAND.
 570  * @ecc:                [BOARDSPECIFIC] ECC control structure
 571  * @buffers:            buffer structure for read/write
 572  * @hwcontrol:          platform-specific hardware control structure
 573  * @erase:              [REPLACEABLE] erase function
 574  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 575  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
 576  *                      data from array to read regs (tR).
 577  * @state:              [INTERN] the current state of the NAND device
 578  * @oob_poi:            "poison value buffer," used for laying out OOB data
 579  *                      before writing
 580  * @page_shift:         [INTERN] number of address bits in a page (column
 581  *                      address bits).
 582  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 583  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 584  * @chip_shift:         [INTERN] number of address bits in one chip
 585  * @options:            [BOARDSPECIFIC] various chip options. They can partly
 586  *                      be set to inform nand_scan about special functionality.
 587  *                      See the defines for further explanation.
 588  * @bbt_options:        [INTERN] bad block specific options. All options used
 589  *                      here must come from bbm.h. By default, these options
 590  *                      will be copied to the appropriate nand_bbt_descr's.
 591  * @badblockpos:        [INTERN] position of the bad block marker in the oob
 592  *                      area.
 593  * @badblockbits:       [INTERN] minimum number of set bits in a good block's
 594  *                      bad block marker position; i.e., BBM == 11110111b is
 595  *                      not bad when badblockbits == 7
 596  * @bits_per_cell:      [INTERN] number of bits per cell. i.e., 1 means SLC.
 597  * @ecc_strength_ds:    [INTERN] ECC correctability from the datasheet.
 598  *                      Minimum amount of bit errors per @ecc_step_ds guaranteed
 599  *                      to be correctable. If unknown, set to zero.
 600  * @ecc_step_ds:        [INTERN] ECC step required by the @ecc_strength_ds,
 601  *                      also from the datasheet. It is the recommended ECC step
 602  *                      size, if known; if unknown, set to zero.
 603  * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
 604  *                            either deduced from the datasheet if the NAND
 605  *                            chip is not ONFI compliant or set to 0 if it is
 606  *                            (an ONFI chip is always configured in mode 0
 607  *                            after a NAND reset)
 608  * @numchips:           [INTERN] number of physical chips
 609  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 610  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 611  * @pagebuf:            [INTERN] holds the pagenumber which is currently in
 612  *                      data_buf.
 613  * @pagebuf_bitflips:   [INTERN] holds the bitflip count for the page which is
 614  *                      currently in data_buf.
 615  * @subpagesize:        [INTERN] holds the subpagesize
 616  * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
 617  *                      non 0 if ONFI supported.
 618  * @jedec_version:      [INTERN] holds the chip JEDEC version (BCD encoded),
 619  *                      non 0 if JEDEC supported.
 620  * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
 621  *                      supported, 0 otherwise.
 622  * @jedec_params:       [INTERN] holds the JEDEC parameter page when JEDEC is
 623  *                      supported, 0 otherwise.
 624  * @read_retries:       [INTERN] the number of read retry modes supported
 625  * @onfi_set_features:  [REPLACEABLE] set the features for ONFI nand
 626  * @onfi_get_features:  [REPLACEABLE] get the features for ONFI nand
 627  * @bbt:                [INTERN] bad block table pointer
 628  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
 629  *                      lookup.
 630  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 631  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
 632  *                      bad block scan.
 633  * @controller:         [REPLACEABLE] a pointer to a hardware controller
 634  *                      structure which is shared among multiple independent
 635  *                      devices.
 636  * @priv:               [OPTIONAL] pointer to private chip data
 637  * @errstat:            [OPTIONAL] hardware specific function to perform
 638  *                      additional error status checks (determine if errors are
 639  *                      correctable).
 640  * @write_page:         [REPLACEABLE] High-level page write function
 641  */
 642
 643 struct nand_chip {
 644         void __iomem *IO_ADDR_R;
 645         void __iomem *IO_ADDR_W;
 646
 647         uint8_t (*read_byte)(struct mtd_info *mtd);
 648         u16 (*read_word)(struct mtd_info *mtd);
 649         void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
 650         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 651         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 652         void (*select_chip)(struct mtd_info *mtd, int chip);
 653         int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 654         int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 655         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 656         int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
 657                         u8 *id_data);
 658         int (*dev_ready)(struct mtd_info *mtd);
 659         void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 660                         int page_addr);
 661         int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 662         int (*erase)(struct mtd_info *mtd, int page);
 663         int (*scan_bbt)(struct mtd_info *mtd);
 664         int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 665                         int status, int page);
 666         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 667                         uint32_t offset, int data_len, const uint8_t *buf,
 668                         int oob_required, int page, int cached, int raw);
 669         int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
 670                         int feature_addr, uint8_t *subfeature_para);
 671         int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
 672                         int feature_addr, uint8_t *subfeature_para);
 673         int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
 674
 675         int chip_delay;
 676         unsigned int options;
 677         unsigned int bbt_options;
 678
 679         int page_shift;
 680         int phys_erase_shift;
 681         int bbt_erase_shift;
 682         int chip_shift;
 683         int numchips;
 684         uint64_t chipsize;
 685         int pagemask;
 686         int pagebuf;
 687         unsigned int pagebuf_bitflips;
 688         int subpagesize;
 689         uint8_t bits_per_cell;
 690         uint16_t ecc_strength_ds;
 691         uint16_t ecc_step_ds;
 692         int onfi_timing_mode_default;
 693         int badblockpos;
 694         int badblockbits;
 695
 696         int onfi_version;
 697         int jedec_version;
 698         union {
 699                 struct nand_onfi_params onfi_params;
 700                 struct nand_jedec_params jedec_params;
 701         };
 702
 703         int read_retries;
 704
 705         flstate_t state;
 706
 707         uint8_t *oob_poi;
 708         struct nand_hw_control *controller;
 709
 710         struct nand_ecc_ctrl ecc;
 711         struct nand_buffers *buffers;
 712         struct nand_hw_control hwcontrol;
 713
 714         uint8_t *bbt;
 715         struct nand_bbt_descr *bbt_td;
 716         struct nand_bbt_descr *bbt_md;
 717
 718         struct nand_bbt_descr *badblock_pattern;
 719
 720         void *priv;
 721 };
 722
 723 /*
 724  * NAND Flash Manufacturer ID Codes
 725  */
 726 #define NAND_MFR_TOSHIBA        0x98
 727 #define NAND_MFR_SAMSUNG        0xec
 728 #define NAND_MFR_FUJITSU        0x04
 729 #define NAND_MFR_NATIONAL       0x8f
 730 #define NAND_MFR_RENESAS        0x07
 731 #define NAND_MFR_STMICRO        0x20
 732 #define NAND_MFR_HYNIX          0xad
 733 #define NAND_MFR_MICRON         0x2c
 734 #define NAND_MFR_AMD            0x01
 735 #define NAND_MFR_MACRONIX       0xc2
 736 #define NAND_MFR_EON            0x92
 737 #define NAND_MFR_SANDISK        0x45
 738 #define NAND_MFR_INTEL          0x89
 739 #define NAND_MFR_ATO            0x9b
 740
 741 /* The maximum expected count of bytes in the NAND ID sequence */
 742 #define NAND_MAX_ID_LEN 8
 743
 744 /*
 745  * A helper for defining older NAND chips where the second ID byte fully
 746  * defined the chip, including the geometry (chip size, eraseblock size, page
 747  * size). All these chips have 512 bytes NAND page size.
 748  */
 749 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
 750         { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
 751           .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
 752
 753 /*
 754  * A helper for defining newer chips which report their page size and
 755  * eraseblock size via the extended ID bytes.
 756  *
 757  * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
 758  * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
 759  * device ID now only represented a particular total chip size (and voltage,
 760  * buswidth), and the page size, eraseblock size, and OOB size could vary while
 761  * using the same device ID.
 762  */
 763 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
 764         { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
 765           .options = (opts) }
 766
 767 #define NAND_ECC_INFO(_strength, _step) \
 768                         { .strength_ds = (_strength), .step_ds = (_step) }
 769 #define NAND_ECC_STRENGTH(type)         ((type)->ecc.strength_ds)
 770 #define NAND_ECC_STEP(type)             ((type)->ecc.step_ds)
 771
 772 /**
 773  * struct nand_flash_dev - NAND Flash Device ID Structure
 774  * @name: a human-readable name of the NAND chip
 775  * @dev_id: the device ID (the second byte of the full chip ID array)
 776  * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
 777  *          memory address as @id[0])
 778  * @dev_id: device ID part of the full chip ID array (refers the same memory
 779  *          address as @id[1])
 780  * @id: full device ID array
 781  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
 782  *            well as the eraseblock size) is determined from the extended NAND
 783  *            chip ID array)
 784  * @chipsize: total chip size in MiB
 785  * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
 786  * @options: stores various chip bit options
 787  * @id_len: The valid length of the @id.
 788  * @oobsize: OOB size
 789  * @ecc: ECC correctability and step information from the datasheet.
 790  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
 791  *                   @ecc_strength_ds in nand_chip{}.
 792  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
 793  *               @ecc_step_ds in nand_chip{}, also from the datasheet.
 794  *               For example, the "4bit ECC for each 512Byte" can be set with
 795  *               NAND_ECC_INFO(4, 512).
 796  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
 797  *                            reset. Should be deduced from timings described
 798  *                            in the datasheet.
 799  *
 800  */
 801 struct nand_flash_dev {
 802         char *name;
 803         union {
 804                 struct {
 805                         uint8_t mfr_id;
 806                         uint8_t dev_id;
 807                 };
 808                 uint8_t id[NAND_MAX_ID_LEN];
 809         };
 810         unsigned int pagesize;
 811         unsigned int chipsize;
 812         unsigned int erasesize;
 813         unsigned int options;
 814         uint16_t id_len;
 815         uint16_t oobsize;
 816         struct {
 817                 uint16_t strength_ds;
 818                 uint16_t step_ds;
 819         } ecc;
 820         int onfi_timing_mode_default;
 821 };
 822
 823 /**
 824  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 825  * @name:       Manufacturer name
 826  * @id:         manufacturer ID code of device.
 827 */
 828 struct nand_manufacturers {
 829         int id;
 830         char *name;
 831 };
 832
 833 extern struct nand_flash_dev nand_flash_ids[];
 834 extern struct nand_manufacturers nand_manuf_ids[];
 835
 836 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 837 extern int nand_default_bbt(struct mtd_info *mtd);
 838 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
 839 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
 840 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 841 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 842                            int allowbbt);
 843 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 844                         size_t *retlen, uint8_t *buf);
 845
 846 /**
 847  * struct platform_nand_chip - chip level device structure
 848  * @nr_chips:           max. number of chips to scan for
 849  * @chip_offset:        chip number offset
 850  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 851  * @partitions:         mtd partition list
 852  * @chip_delay:         R/B delay value in us
 853  * @options:            Option flags, e.g. 16bit buswidth
 854  * @bbt_options:        BBT option flags, e.g. NAND_BBT_USE_FLASH
 855  * @ecclayout:          ECC layout info structure
 856  * @part_probe_types:   NULL-terminated array of probe types
 857  */
 858 struct platform_nand_chip {
 859         int nr_chips;
 860         int chip_offset;
 861         int nr_partitions;
 862         struct mtd_partition *partitions;
 863         struct nand_ecclayout *ecclayout;
 864         int chip_delay;
 865         unsigned int options;
 866         unsigned int bbt_options;
 867         const char **part_probe_types;
 868 };
 869
 870 /* Keep gcc happy */
 871 struct platform_device;
 872
 873 /**
 874  * struct platform_nand_ctrl - controller level device structure
 875  * @probe:              platform specific function to probe/setup hardware
 876  * @remove:             platform specific function to remove/teardown hardware
 877  * @hwcontrol:          platform specific hardware control structure
 878  * @dev_ready:          platform specific function to read ready/busy pin
 879  * @select_chip:        platform specific chip select function
 880  * @cmd_ctrl:           platform specific function for controlling
 881  *                      ALE/CLE/nCE. Also used to write command and address
 882  * @write_buf:          platform specific function for write buffer
 883  * @read_buf:           platform specific function for read buffer
 884  * @read_byte:          platform specific function to read one byte from chip
 885  * @priv:               private data to transport driver specific settings
 886  *
 887  * All fields are optional and depend on the hardware driver requirements
 888  */
 889 struct platform_nand_ctrl {
 890         int (*probe)(struct platform_device *pdev);
 891         void (*remove)(struct platform_device *pdev);
 892         void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 893         int (*dev_ready)(struct mtd_info *mtd);
 894         void (*select_chip)(struct mtd_info *mtd, int chip);
 895         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 896         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 897         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 898         unsigned char (*read_byte)(struct mtd_info *mtd);
 899         void *priv;
 900 };
 901
 902 /**
 903  * struct platform_nand_data - container structure for platform-specific data
 904  * @chip:               chip level chip structure
 905  * @ctrl:               controller level device structure
 906  */
 907 struct platform_nand_data {
 908         struct platform_nand_chip chip;
 909         struct platform_nand_ctrl ctrl;
 910 };
 911
 912 /* Some helpers to access the data structures */
 913 static inline
 914 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 915 {
 916         struct nand_chip *chip = mtd->priv;
 917
 918         return chip->priv;
 919 }
 920
 921 /* return the supported features. */
 922 static inline int onfi_feature(struct nand_chip *chip)
 923 {
 924         return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
 925 }
 926
 927 /* return the supported asynchronous timing mode. */
 928 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
 929 {
 930         if (!chip->onfi_version)
 931                 return ONFI_TIMING_MODE_UNKNOWN;
 932         return le16_to_cpu(chip->onfi_params.async_timing_mode);
 933 }
 934
 935 /* return the supported synchronous timing mode. */
 936 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
 937 {
 938         if (!chip->onfi_version)
 939                 return ONFI_TIMING_MODE_UNKNOWN;
 940         return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
 941 }
 942
 943 /*
 944  * Check if it is a SLC nand.
 945  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
 946  * We do not distinguish the MLC and TLC now.
 947  */
 948 static inline bool nand_is_slc(struct nand_chip *chip)
 949 {
 950         return chip->bits_per_cell == 1;
 951 }
 952
 953 /**
 954  * Check if the opcode's address should be sent only on the lower 8 bits
 955  * @command: opcode to check
 956  */
 957 static inline int nand_opcode_8bits(unsigned int command)
 958 {
 959         switch (command) {
 960         case NAND_CMD_READID:
 961         case NAND_CMD_PARAM:
 962         case NAND_CMD_GET_FEATURES:
 963         case NAND_CMD_SET_FEATURES:
 964                 return 1;
 965         default:
 966                 break;
 967         }
 968         return 0;
 969 }
 970
 971 /* return the supported JEDEC features. */
 972 static inline int jedec_feature(struct nand_chip *chip)
 973 {
 974         return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
 975                 : 0;
 976 }
 977
 978 /*
 979  * struct nand_sdr_timings - SDR NAND chip timings
 980  *
 981  * This struct defines the timing requirements of a SDR NAND chip.
 982  * These informations can be found in every NAND datasheets and the timings
 983  * meaning are described in the ONFI specifications:
 984  * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
 985  * Parameters)
 986  *
 987  * All these timings are expressed in picoseconds.
 988  */
 989
 990 struct nand_sdr_timings {
 991         u32 tALH_min;
 992         u32 tADL_min;
 993         u32 tALS_min;
 994         u32 tAR_min;
 995         u32 tCEA_max;
 996         u32 tCEH_min;
 997         u32 tCH_min;
 998         u32 tCHZ_max;
 999         u32 tCLH_min;
1000         u32 tCLR_min;
1001         u32 tCLS_min;
1002         u32 tCOH_min;
1003         u32 tCS_min;
1004         u32 tDH_min;
1005         u32 tDS_min;
1006         u32 tFEAT_max;
1007         u32 tIR_min;
1008         u32 tITC_max;
1009         u32 tRC_min;
1010         u32 tREA_max;
1011         u32 tREH_min;
1012         u32 tRHOH_min;
1013         u32 tRHW_min;
1014         u32 tRHZ_max;
1015         u32 tRLOH_min;
1016         u32 tRP_min;
1017         u32 tRR_min;
1018         u64 tRST_max;
1019         u32 tWB_max;
1020         u32 tWC_min;
1021         u32 tWH_min;
1022         u32 tWHR_min;
1023         u32 tWP_min;
1024         u32 tWW_min;
1025 };
1026
1027 /* get timing characteristics from ONFI timing mode. */
1028 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1029 #endif /* __LINUX_MTD_NAND_H */