2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev
;
31 /* Scan and identify a NAND device */
32 int nand_scan(struct mtd_info
*mtd
, int max_chips
);
34 * Separate phases of nand_scan(), allowing board driver to intervene
35 * and override command or ECC setup according to flash type.
37 int nand_scan_ident(struct mtd_info
*mtd
, int max_chips
,
38 struct nand_flash_dev
*table
);
39 int nand_scan_tail(struct mtd_info
*mtd
);
41 /* Unregister the MTD device and free resources held by the NAND device */
42 void nand_release(struct mtd_info
*mtd
);
44 /* Internal helper for board drivers which need to override command function */
45 void nand_wait_ready(struct mtd_info
*mtd
);
47 /* locks all blocks present in the device */
48 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
50 /* unlocks specified locked blocks */
51 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
53 /* The maximum number of NAND chips in an array */
54 #define NAND_MAX_CHIPS 8
57 * Constants for hardware specific CLE/ALE/NCE function
59 * These are bits which can be or'ed to set/clear multiple
62 /* Select the chip by setting nCE to low */
64 /* Select the command latch by setting CLE to high */
66 /* Select the address latch by setting ALE to high */
69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
71 #define NAND_CTRL_CHANGE 0x80
74 * Standard NAND flash commands
76 #define NAND_CMD_READ0 0
77 #define NAND_CMD_READ1 1
78 #define NAND_CMD_RNDOUT 5
79 #define NAND_CMD_PAGEPROG 0x10
80 #define NAND_CMD_READOOB 0x50
81 #define NAND_CMD_ERASE1 0x60
82 #define NAND_CMD_STATUS 0x70
83 #define NAND_CMD_SEQIN 0x80
84 #define NAND_CMD_RNDIN 0x85
85 #define NAND_CMD_READID 0x90
86 #define NAND_CMD_ERASE2 0xd0
87 #define NAND_CMD_PARAM 0xec
88 #define NAND_CMD_GET_FEATURES 0xee
89 #define NAND_CMD_SET_FEATURES 0xef
90 #define NAND_CMD_RESET 0xff
92 #define NAND_CMD_LOCK 0x2a
93 #define NAND_CMD_UNLOCK1 0x23
94 #define NAND_CMD_UNLOCK2 0x24
96 /* Extended commands for large page devices */
97 #define NAND_CMD_READSTART 0x30
98 #define NAND_CMD_RNDOUTSTART 0xE0
99 #define NAND_CMD_CACHEDPROG 0x15
101 #define NAND_CMD_NONE -1
104 #define NAND_STATUS_FAIL 0x01
105 #define NAND_STATUS_FAIL_N1 0x02
106 #define NAND_STATUS_TRUE_READY 0x20
107 #define NAND_STATUS_READY 0x40
108 #define NAND_STATUS_WP 0x80
111 * Constants for ECC_MODES
117 NAND_ECC_HW_SYNDROME
,
118 NAND_ECC_HW_OOB_FIRST
,
128 * Constants for Hardware ECC
130 /* Reset Hardware ECC for read */
131 #define NAND_ECC_READ 0
132 /* Reset Hardware ECC for write */
133 #define NAND_ECC_WRITE 1
134 /* Enable Hardware ECC before syndrome is read back from flash */
135 #define NAND_ECC_READSYN 2
138 * Enable generic NAND 'page erased' check. This check is only done when
139 * ecc.correct() returns -EBADMSG.
140 * Set this flag if your implementation does not fix bitflips in erased
141 * pages and you want to rely on the default implementation.
143 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
144 #define NAND_ECC_MAXIMIZE BIT(1)
146 /* Bit mask for flags passed to do_nand_read_ecc */
147 #define NAND_GET_DEVICE 0x80
151 * Option constants for bizarre disfunctionality and real
154 /* Buswidth is 16 bit */
155 #define NAND_BUSWIDTH_16 0x00000002
156 /* Chip has cache program function */
157 #define NAND_CACHEPRG 0x00000008
159 * Chip requires ready check on read (for auto-incremented sequential read).
160 * True only for small page devices; large page devices do not support
163 #define NAND_NEED_READRDY 0x00000100
165 /* Chip does not allow subpage writes */
166 #define NAND_NO_SUBPAGE_WRITE 0x00000200
168 /* Device is one of 'new' xD cards that expose fake nand command set */
169 #define NAND_BROKEN_XD 0x00000400
171 /* Device behaves just like nand, but is readonly */
172 #define NAND_ROM 0x00000800
174 /* Device supports subpage reads */
175 #define NAND_SUBPAGE_READ 0x00001000
178 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
181 #define NAND_NEED_SCRAMBLING 0x00002000
183 /* Options valid for Samsung large page devices */
184 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
186 /* Macros to identify the above */
187 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
188 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
190 /* Non chip related options */
191 /* This option skips the bbt scan during initialization. */
192 #define NAND_SKIP_BBTSCAN 0x00010000
194 * This option is defined if the board driver allocates its own buffers
195 * (e.g. because it needs them DMA-coherent).
197 #define NAND_OWN_BUFFERS 0x00020000
198 /* Chip may not exist, so silence any errors in scan */
199 #define NAND_SCAN_SILENT_NODEV 0x00040000
201 * Autodetect nand buswidth with readid/onfi.
202 * This suppose the driver will configure the hardware in 8 bits mode
203 * when calling nand_scan_ident, and update its configuration
204 * before calling nand_scan_tail.
206 #define NAND_BUSWIDTH_AUTO 0x00080000
208 * This option could be defined by controller drivers to protect against
209 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
211 #define NAND_USE_BOUNCE_BUFFER 0x00100000
214 * In case your controller is implementing ->cmd_ctrl() and is relying on the
215 * default ->cmdfunc() implementation, you may want to let the core handle the
216 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is
218 * If your controller already takes care of this delay, you don't need to set
221 #define NAND_WAIT_TCCS 0x00200000
223 /* Options set by nand scan */
224 /* Nand scan has allocated controller struct */
225 #define NAND_CONTROLLER_ALLOC 0x80000000
227 /* Cell info constants */
228 #define NAND_CI_CHIPNR_MSK 0x03
229 #define NAND_CI_CELLTYPE_MSK 0x0C
230 #define NAND_CI_CELLTYPE_SHIFT 2
236 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
237 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
239 /* ONFI timing mode, used in both asynchronous and synchronous mode */
240 #define ONFI_TIMING_MODE_0 (1 << 0)
241 #define ONFI_TIMING_MODE_1 (1 << 1)
242 #define ONFI_TIMING_MODE_2 (1 << 2)
243 #define ONFI_TIMING_MODE_3 (1 << 3)
244 #define ONFI_TIMING_MODE_4 (1 << 4)
245 #define ONFI_TIMING_MODE_5 (1 << 5)
246 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
248 /* ONFI feature address */
249 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
251 /* Vendor-specific feature address (Micron) */
252 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
254 /* ONFI subfeature parameters length */
255 #define ONFI_SUBFEATURE_PARAM_LEN 4
257 /* ONFI optional commands SET/GET FEATURES supported? */
258 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
260 struct nand_onfi_params
{
261 /* rev info and features block */
262 /* 'O' 'N' 'F' 'I' */
268 __le16 ext_param_page_length
; /* since ONFI 2.1 */
269 u8 num_of_param_pages
; /* since ONFI 2.1 */
272 /* manufacturer information block */
273 char manufacturer
[12];
279 /* memory organization block */
280 __le32 byte_per_page
;
281 __le16 spare_bytes_per_page
;
282 __le32 data_bytes_per_ppage
;
283 __le16 spare_bytes_per_ppage
;
284 __le32 pages_per_block
;
285 __le32 blocks_per_lun
;
290 __le16 block_endurance
;
291 u8 guaranteed_good_blocks
;
292 __le16 guaranteed_block_endurance
;
293 u8 programs_per_page
;
300 /* electrical parameter block */
301 u8 io_pin_capacitance_max
;
302 __le16 async_timing_mode
;
303 __le16 program_cache_timing_mode
;
308 __le16 src_sync_timing_mode
;
309 u8 src_ssync_features
;
310 __le16 clk_pin_capacitance_typ
;
311 __le16 io_pin_capacitance_typ
;
312 __le16 input_pin_capacitance_typ
;
313 u8 input_pin_capacitance_max
;
314 u8 driver_strength_support
;
320 __le16 vendor_revision
;
326 #define ONFI_CRC_BASE 0x4F4E
328 /* Extended ECC information Block Definition (since ONFI 2.1) */
329 struct onfi_ext_ecc_info
{
333 __le16 block_endurance
;
337 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
338 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
339 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
340 struct onfi_ext_section
{
345 #define ONFI_EXT_SECTION_MAX 8
347 /* Extended Parameter Page Definition (since ONFI 2.1) */
348 struct onfi_ext_param_page
{
350 u8 sig
[4]; /* 'E' 'P' 'P' 'S' */
352 struct onfi_ext_section sections
[ONFI_EXT_SECTION_MAX
];
355 * The actual size of the Extended Parameter Page is in
356 * @ext_param_page_length of nand_onfi_params{}.
357 * The following are the variable length sections.
358 * So we do not add any fields below. Please see the ONFI spec.
362 struct nand_onfi_vendor_micron
{
367 u8 dq_imped_num_settings
;
368 u8 dq_imped_feat_addr
;
369 u8 rb_pulldown_strength
;
370 u8 rb_pulldown_strength_feat_addr
;
371 u8 rb_pulldown_strength_num_settings
;
374 u8 otp_data_prot_addr
;
377 u8 read_retry_options
;
382 struct jedec_ecc_info
{
386 __le16 block_endurance
;
391 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
393 struct nand_jedec_params
{
394 /* rev info and features block */
395 /* 'J' 'E' 'S' 'D' */
401 u8 num_of_param_pages
;
404 /* manufacturer information block */
405 char manufacturer
[12];
410 /* memory organization block */
411 __le32 byte_per_page
;
412 __le16 spare_bytes_per_page
;
414 __le32 pages_per_block
;
415 __le32 blocks_per_lun
;
419 u8 programs_per_page
;
421 u8 multi_plane_op_attr
;
424 /* electrical parameter block */
425 __le16 async_sdr_speed_grade
;
426 __le16 toggle_ddr_speed_grade
;
427 __le16 sync_ddr_speed_grade
;
428 u8 async_sdr_features
;
429 u8 toggle_ddr_features
;
430 u8 sync_ddr_features
;
434 __le16 t_r_multi_plane
;
436 __le16 io_pin_capacitance_typ
;
437 __le16 input_pin_capacitance_typ
;
438 __le16 clk_pin_capacitance_typ
;
439 u8 driver_strength_support
;
443 /* ECC and endurance block */
444 u8 guaranteed_good_blocks
;
445 __le16 guaranteed_block_endurance
;
446 struct jedec_ecc_info ecc_info
[4];
453 __le16 vendor_rev_num
;
456 /* CRC for Parameter Page */
461 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
462 * @lock: protection lock
463 * @active: the mtd device which holds the controller currently
464 * @wq: wait queue to sleep on if a NAND operation is in
465 * progress used instead of the per chip wait queue
466 * when a hw controller is available.
468 struct nand_hw_control
{
470 struct nand_chip
*active
;
471 wait_queue_head_t wq
;
474 static inline void nand_hw_control_init(struct nand_hw_control
*nfc
)
477 spin_lock_init(&nfc
->lock
);
478 init_waitqueue_head(&nfc
->wq
);
482 * struct nand_ecc_ctrl - Control structure for ECC
484 * @algo: ECC algorithm
485 * @steps: number of ECC steps per page
486 * @size: data bytes per ECC step
487 * @bytes: ECC bytes per step
488 * @strength: max number of correctible bits per ECC step
489 * @total: total number of ECC bytes per page
490 * @prepad: padding information for syndrome based ECC generators
491 * @postpad: padding information for syndrome based ECC generators
492 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
493 * @priv: pointer to private ECC control data
494 * @hwctl: function to control hardware ECC generator. Must only
495 * be provided if an hardware ECC is available
496 * @calculate: function for ECC calculation or readback from ECC hardware
497 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
498 * Should return a positive number representing the number of
499 * corrected bitflips, -EBADMSG if the number of bitflips exceed
500 * ECC strength, or any other error code if the error is not
501 * directly related to correction.
502 * If -EBADMSG is returned the input buffers should be left
504 * @read_page_raw: function to read a raw page without ECC. This function
505 * should hide the specific layout used by the ECC
506 * controller and always return contiguous in-band and
507 * out-of-band data even if they're not stored
508 * contiguously on the NAND chip (e.g.
509 * NAND_ECC_HW_SYNDROME interleaves in-band and
511 * @write_page_raw: function to write a raw page without ECC. This function
512 * should hide the specific layout used by the ECC
513 * controller and consider the passed data as contiguous
514 * in-band and out-of-band data. ECC controller is
515 * responsible for doing the appropriate transformations
516 * to adapt to its specific layout (e.g.
517 * NAND_ECC_HW_SYNDROME interleaves in-band and
519 * @read_page: function to read a page according to the ECC generator
520 * requirements; returns maximum number of bitflips corrected in
521 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
522 * @read_subpage: function to read parts of the page covered by ECC;
523 * returns same as read_page()
524 * @write_subpage: function to write parts of the page covered by ECC.
525 * @write_page: function to write a page according to the ECC generator
527 * @write_oob_raw: function to write chip OOB data without ECC
528 * @read_oob_raw: function to read chip OOB data without ECC
529 * @read_oob: function to read chip OOB data
530 * @write_oob: function to write chip OOB data
532 struct nand_ecc_ctrl
{
533 nand_ecc_modes_t mode
;
534 enum nand_ecc_algo algo
;
542 unsigned int options
;
544 void (*hwctl
)(struct mtd_info
*mtd
, int mode
);
545 int (*calculate
)(struct mtd_info
*mtd
, const uint8_t *dat
,
547 int (*correct
)(struct mtd_info
*mtd
, uint8_t *dat
, uint8_t *read_ecc
,
549 int (*read_page_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
550 uint8_t *buf
, int oob_required
, int page
);
551 int (*write_page_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
552 const uint8_t *buf
, int oob_required
, int page
);
553 int (*read_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
554 uint8_t *buf
, int oob_required
, int page
);
555 int (*read_subpage
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
556 uint32_t offs
, uint32_t len
, uint8_t *buf
, int page
);
557 int (*write_subpage
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
558 uint32_t offset
, uint32_t data_len
,
559 const uint8_t *data_buf
, int oob_required
, int page
);
560 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
561 const uint8_t *buf
, int oob_required
, int page
);
562 int (*write_oob_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
564 int (*read_oob_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
566 int (*read_oob
)(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
);
567 int (*write_oob
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
572 * struct nand_buffers - buffer structure for read/write
573 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
574 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
575 * @databuf: buffer pointer for data, size is (page size + oobsize).
577 * Do not change the order of buffers. databuf and oobrbuf must be in
580 struct nand_buffers
{
587 * struct nand_sdr_timings - SDR NAND chip timings
589 * This struct defines the timing requirements of a SDR NAND chip.
590 * These information can be found in every NAND datasheets and the timings
591 * meaning are described in the ONFI specifications:
592 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
595 * All these timings are expressed in picoseconds.
597 * @tBERS_max: Block erase time
598 * @tCCS_min: Change column setup time
599 * @tPROG_max: Page program time
600 * @tR_max: Page read time
601 * @tALH_min: ALE hold time
602 * @tADL_min: ALE to data loading time
603 * @tALS_min: ALE setup time
604 * @tAR_min: ALE to RE# delay
605 * @tCEA_max: CE# access time
607 * @tCH_min: CE# hold time
608 * @tCHZ_max: CE# high to output hi-Z
609 * @tCLH_min: CLE hold time
610 * @tCLR_min: CLE to RE# delay
611 * @tCLS_min: CLE setup time
612 * @tCOH_min: CE# high to output hold
613 * @tCS_min: CE# setup time
614 * @tDH_min: Data hold time
615 * @tDS_min: Data setup time
616 * @tFEAT_max: Busy time for Set Features and Get Features
617 * @tIR_min: Output hi-Z to RE# low
618 * @tITC_max: Interface and Timing Mode Change time
619 * @tRC_min: RE# cycle time
620 * @tREA_max: RE# access time
621 * @tREH_min: RE# high hold time
622 * @tRHOH_min: RE# high to output hold
623 * @tRHW_min: RE# high to WE# low
624 * @tRHZ_max: RE# high to output hi-Z
625 * @tRLOH_min: RE# low to output hold
626 * @tRP_min: RE# pulse width
627 * @tRR_min: Ready to RE# low (data only)
628 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
629 * rising edge of R/B#.
630 * @tWB_max: WE# high to SR[6] low
631 * @tWC_min: WE# cycle time
632 * @tWH_min: WE# high hold time
633 * @tWHR_min: WE# high to RE# low
634 * @tWP_min: WE# pulse width
635 * @tWW_min: WP# transition to WE# low
637 struct nand_sdr_timings
{
679 * enum nand_data_interface_type - NAND interface timing type
680 * @NAND_SDR_IFACE: Single Data Rate interface
682 enum nand_data_interface_type
{
687 * struct nand_data_interface - NAND interface timing
688 * @type: type of the timing
689 * @timings: The timing, type according to @type
691 struct nand_data_interface
{
692 enum nand_data_interface_type type
;
694 struct nand_sdr_timings sdr
;
699 * nand_get_sdr_timings - get SDR timing from data interface
700 * @conf: The data interface
702 static inline const struct nand_sdr_timings
*
703 nand_get_sdr_timings(const struct nand_data_interface
*conf
)
705 if (conf
->type
!= NAND_SDR_IFACE
)
706 return ERR_PTR(-EINVAL
);
708 return &conf
->timings
.sdr
;
712 * struct nand_chip - NAND Private Flash Chip Data
713 * @mtd: MTD device registered to the MTD framework
714 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
716 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
718 * @read_byte: [REPLACEABLE] read one byte from the chip
719 * @read_word: [REPLACEABLE] read one word from the chip
720 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
722 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
723 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
724 * @select_chip: [REPLACEABLE] select chip nr
725 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
726 * @block_markbad: [REPLACEABLE] mark a block bad
727 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
728 * ALE/CLE/nCE. Also used to write command and address
729 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
730 * device ready/busy line. If set to NULL no access to
731 * ready/busy is available and the ready/busy information
732 * is read from the chip status register.
733 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
734 * commands to the chip.
735 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
737 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
738 * setting the read-retry mode. Mostly needed for MLC NAND.
739 * @ecc: [BOARDSPECIFIC] ECC control structure
740 * @buffers: buffer structure for read/write
741 * @hwcontrol: platform-specific hardware control structure
742 * @erase: [REPLACEABLE] erase function
743 * @scan_bbt: [REPLACEABLE] function to scan bad block table
744 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
745 * data from array to read regs (tR).
746 * @state: [INTERN] the current state of the NAND device
747 * @oob_poi: "poison value buffer," used for laying out OOB data
749 * @page_shift: [INTERN] number of address bits in a page (column
751 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
752 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
753 * @chip_shift: [INTERN] number of address bits in one chip
754 * @options: [BOARDSPECIFIC] various chip options. They can partly
755 * be set to inform nand_scan about special functionality.
756 * See the defines for further explanation.
757 * @bbt_options: [INTERN] bad block specific options. All options used
758 * here must come from bbm.h. By default, these options
759 * will be copied to the appropriate nand_bbt_descr's.
760 * @badblockpos: [INTERN] position of the bad block marker in the oob
762 * @badblockbits: [INTERN] minimum number of set bits in a good block's
763 * bad block marker position; i.e., BBM == 11110111b is
764 * not bad when badblockbits == 7
765 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
766 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
767 * Minimum amount of bit errors per @ecc_step_ds guaranteed
768 * to be correctable. If unknown, set to zero.
769 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
770 * also from the datasheet. It is the recommended ECC step
771 * size, if known; if unknown, set to zero.
772 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
773 * set to the actually used ONFI mode if the chip is
774 * ONFI compliant or deduced from the datasheet if
775 * the NAND chip is not ONFI compliant.
776 * @numchips: [INTERN] number of physical chips
777 * @chipsize: [INTERN] the size of one chip for multichip arrays
778 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
779 * @pagebuf: [INTERN] holds the pagenumber which is currently in
781 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
782 * currently in data_buf.
783 * @subpagesize: [INTERN] holds the subpagesize
784 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
785 * non 0 if ONFI supported.
786 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
787 * non 0 if JEDEC supported.
788 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
789 * supported, 0 otherwise.
790 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
791 * supported, 0 otherwise.
792 * @read_retries: [INTERN] the number of read retry modes supported
793 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
794 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
795 * @setup_data_interface: [OPTIONAL] setup the data interface and timing
796 * @bbt: [INTERN] bad block table pointer
797 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
799 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
800 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
802 * @controller: [REPLACEABLE] a pointer to a hardware controller
803 * structure which is shared among multiple independent
805 * @priv: [OPTIONAL] pointer to private chip data
806 * @errstat: [OPTIONAL] hardware specific function to perform
807 * additional error status checks (determine if errors are
809 * @write_page: [REPLACEABLE] High-level page write function
814 void __iomem
*IO_ADDR_R
;
815 void __iomem
*IO_ADDR_W
;
817 uint8_t (*read_byte
)(struct mtd_info
*mtd
);
818 u16 (*read_word
)(struct mtd_info
*mtd
);
819 void (*write_byte
)(struct mtd_info
*mtd
, uint8_t byte
);
820 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
821 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
822 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
823 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
);
824 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
825 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
);
826 int (*dev_ready
)(struct mtd_info
*mtd
);
827 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
,
829 int(*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this);
830 int (*erase
)(struct mtd_info
*mtd
, int page
);
831 int (*scan_bbt
)(struct mtd_info
*mtd
);
832 int (*errstat
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
,
833 int status
, int page
);
834 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
835 uint32_t offset
, int data_len
, const uint8_t *buf
,
836 int oob_required
, int page
, int cached
, int raw
);
837 int (*onfi_set_features
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
838 int feature_addr
, uint8_t *subfeature_para
);
839 int (*onfi_get_features
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
840 int feature_addr
, uint8_t *subfeature_para
);
841 int (*setup_read_retry
)(struct mtd_info
*mtd
, int retry_mode
);
842 int (*setup_data_interface
)(struct mtd_info
*mtd
,
843 const struct nand_data_interface
*conf
,
848 unsigned int options
;
849 unsigned int bbt_options
;
852 int phys_erase_shift
;
859 unsigned int pagebuf_bitflips
;
861 uint8_t bits_per_cell
;
862 uint16_t ecc_strength_ds
;
863 uint16_t ecc_step_ds
;
864 int onfi_timing_mode_default
;
871 struct nand_onfi_params onfi_params
;
872 struct nand_jedec_params jedec_params
;
875 struct nand_data_interface
*data_interface
;
882 struct nand_hw_control
*controller
;
884 struct nand_ecc_ctrl ecc
;
885 struct nand_buffers
*buffers
;
886 struct nand_hw_control hwcontrol
;
889 struct nand_bbt_descr
*bbt_td
;
890 struct nand_bbt_descr
*bbt_md
;
892 struct nand_bbt_descr
*badblock_pattern
;
897 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops
;
898 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops
;
900 static inline void nand_set_flash_node(struct nand_chip
*chip
,
901 struct device_node
*np
)
903 mtd_set_of_node(&chip
->mtd
, np
);
906 static inline struct device_node
*nand_get_flash_node(struct nand_chip
*chip
)
908 return mtd_get_of_node(&chip
->mtd
);
911 static inline struct nand_chip
*mtd_to_nand(struct mtd_info
*mtd
)
913 return container_of(mtd
, struct nand_chip
, mtd
);
916 static inline struct mtd_info
*nand_to_mtd(struct nand_chip
*chip
)
921 static inline void *nand_get_controller_data(struct nand_chip
*chip
)
926 static inline void nand_set_controller_data(struct nand_chip
*chip
, void *priv
)
932 * NAND Flash Manufacturer ID Codes
934 #define NAND_MFR_TOSHIBA 0x98
935 #define NAND_MFR_ESMT 0xc8
936 #define NAND_MFR_SAMSUNG 0xec
937 #define NAND_MFR_FUJITSU 0x04
938 #define NAND_MFR_NATIONAL 0x8f
939 #define NAND_MFR_RENESAS 0x07
940 #define NAND_MFR_STMICRO 0x20
941 #define NAND_MFR_HYNIX 0xad
942 #define NAND_MFR_MICRON 0x2c
943 #define NAND_MFR_AMD 0x01
944 #define NAND_MFR_MACRONIX 0xc2
945 #define NAND_MFR_EON 0x92
946 #define NAND_MFR_SANDISK 0x45
947 #define NAND_MFR_INTEL 0x89
948 #define NAND_MFR_ATO 0x9b
950 /* The maximum expected count of bytes in the NAND ID sequence */
951 #define NAND_MAX_ID_LEN 8
954 * A helper for defining older NAND chips where the second ID byte fully
955 * defined the chip, including the geometry (chip size, eraseblock size, page
956 * size). All these chips have 512 bytes NAND page size.
958 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
959 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
960 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
963 * A helper for defining newer chips which report their page size and
964 * eraseblock size via the extended ID bytes.
966 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
967 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
968 * device ID now only represented a particular total chip size (and voltage,
969 * buswidth), and the page size, eraseblock size, and OOB size could vary while
970 * using the same device ID.
972 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
973 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
976 #define NAND_ECC_INFO(_strength, _step) \
977 { .strength_ds = (_strength), .step_ds = (_step) }
978 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
979 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
982 * struct nand_flash_dev - NAND Flash Device ID Structure
983 * @name: a human-readable name of the NAND chip
984 * @dev_id: the device ID (the second byte of the full chip ID array)
985 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
986 * memory address as @id[0])
987 * @dev_id: device ID part of the full chip ID array (refers the same memory
989 * @id: full device ID array
990 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
991 * well as the eraseblock size) is determined from the extended NAND
993 * @chipsize: total chip size in MiB
994 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
995 * @options: stores various chip bit options
996 * @id_len: The valid length of the @id.
998 * @ecc: ECC correctability and step information from the datasheet.
999 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1000 * @ecc_strength_ds in nand_chip{}.
1001 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1002 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1003 * For example, the "4bit ECC for each 512Byte" can be set with
1004 * NAND_ECC_INFO(4, 512).
1005 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1006 * reset. Should be deduced from timings described
1010 struct nand_flash_dev
{
1017 uint8_t id
[NAND_MAX_ID_LEN
];
1019 unsigned int pagesize
;
1020 unsigned int chipsize
;
1021 unsigned int erasesize
;
1022 unsigned int options
;
1026 uint16_t strength_ds
;
1029 int onfi_timing_mode_default
;
1033 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1034 * @name: Manufacturer name
1035 * @id: manufacturer ID code of device.
1037 struct nand_manufacturers
{
1042 extern struct nand_flash_dev nand_flash_ids
[];
1043 extern struct nand_manufacturers nand_manuf_ids
[];
1045 int nand_default_bbt(struct mtd_info
*mtd
);
1046 int nand_markbad_bbt(struct mtd_info
*mtd
, loff_t offs
);
1047 int nand_isreserved_bbt(struct mtd_info
*mtd
, loff_t offs
);
1048 int nand_isbad_bbt(struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
1049 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
1051 int nand_do_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1052 size_t *retlen
, uint8_t *buf
);
1055 * struct platform_nand_chip - chip level device structure
1056 * @nr_chips: max. number of chips to scan for
1057 * @chip_offset: chip number offset
1058 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1059 * @partitions: mtd partition list
1060 * @chip_delay: R/B delay value in us
1061 * @options: Option flags, e.g. 16bit buswidth
1062 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1063 * @part_probe_types: NULL-terminated array of probe types
1065 struct platform_nand_chip
{
1069 struct mtd_partition
*partitions
;
1071 unsigned int options
;
1072 unsigned int bbt_options
;
1073 const char **part_probe_types
;
1076 /* Keep gcc happy */
1077 struct platform_device
;
1080 * struct platform_nand_ctrl - controller level device structure
1081 * @probe: platform specific function to probe/setup hardware
1082 * @remove: platform specific function to remove/teardown hardware
1083 * @hwcontrol: platform specific hardware control structure
1084 * @dev_ready: platform specific function to read ready/busy pin
1085 * @select_chip: platform specific chip select function
1086 * @cmd_ctrl: platform specific function for controlling
1087 * ALE/CLE/nCE. Also used to write command and address
1088 * @write_buf: platform specific function for write buffer
1089 * @read_buf: platform specific function for read buffer
1090 * @read_byte: platform specific function to read one byte from chip
1091 * @priv: private data to transport driver specific settings
1093 * All fields are optional and depend on the hardware driver requirements
1095 struct platform_nand_ctrl
{
1096 int (*probe
)(struct platform_device
*pdev
);
1097 void (*remove
)(struct platform_device
*pdev
);
1098 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
1099 int (*dev_ready
)(struct mtd_info
*mtd
);
1100 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
1101 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
);
1102 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
1103 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
1104 unsigned char (*read_byte
)(struct mtd_info
*mtd
);
1109 * struct platform_nand_data - container structure for platform-specific data
1110 * @chip: chip level chip structure
1111 * @ctrl: controller level device structure
1113 struct platform_nand_data
{
1114 struct platform_nand_chip chip
;
1115 struct platform_nand_ctrl ctrl
;
1118 /* return the supported features. */
1119 static inline int onfi_feature(struct nand_chip
*chip
)
1121 return chip
->onfi_version
? le16_to_cpu(chip
->onfi_params
.features
) : 0;
1124 /* return the supported asynchronous timing mode. */
1125 static inline int onfi_get_async_timing_mode(struct nand_chip
*chip
)
1127 if (!chip
->onfi_version
)
1128 return ONFI_TIMING_MODE_UNKNOWN
;
1129 return le16_to_cpu(chip
->onfi_params
.async_timing_mode
);
1132 /* return the supported synchronous timing mode. */
1133 static inline int onfi_get_sync_timing_mode(struct nand_chip
*chip
)
1135 if (!chip
->onfi_version
)
1136 return ONFI_TIMING_MODE_UNKNOWN
;
1137 return le16_to_cpu(chip
->onfi_params
.src_sync_timing_mode
);
1140 int onfi_init_data_interface(struct nand_chip
*chip
,
1141 struct nand_data_interface
*iface
,
1142 enum nand_data_interface_type type
,
1146 * Check if it is a SLC nand.
1147 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1148 * We do not distinguish the MLC and TLC now.
1150 static inline bool nand_is_slc(struct nand_chip
*chip
)
1152 return chip
->bits_per_cell
== 1;
1156 * Check if the opcode's address should be sent only on the lower 8 bits
1157 * @command: opcode to check
1159 static inline int nand_opcode_8bits(unsigned int command
)
1162 case NAND_CMD_READID
:
1163 case NAND_CMD_PARAM
:
1164 case NAND_CMD_GET_FEATURES
:
1165 case NAND_CMD_SET_FEATURES
:
1173 /* return the supported JEDEC features. */
1174 static inline int jedec_feature(struct nand_chip
*chip
)
1176 return chip
->jedec_version
? le16_to_cpu(chip
->jedec_params
.features
)
1180 /* get timing characteristics from ONFI timing mode. */
1181 const struct nand_sdr_timings
*onfi_async_timing_mode_to_sdr_timings(int mode
);
1182 /* get data interface from ONFI timing mode 0, used after reset. */
1183 const struct nand_data_interface
*nand_get_default_data_interface(void);
1185 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1186 void *ecc
, int ecclen
,
1187 void *extraoob
, int extraooblen
,
1190 /* Default write_oob implementation */
1191 int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
);
1193 /* Default write_oob syndrome implementation */
1194 int nand_write_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1197 /* Default read_oob implementation */
1198 int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
);
1200 /* Default read_oob syndrome implementation */
1201 int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1204 /* Reset and initialize a NAND device */
1205 int nand_reset(struct nand_chip
*chip
);
1207 /* Free resources held by the NAND device */
1208 void nand_cleanup(struct nand_chip
*chip
);
1210 #endif /* __LINUX_MTD_NAND_H */