include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
   5  *                     Steven J. Hill <sjhill@realitydiluted.com>
   6  *                     Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Info:
  15  *      Contains standard defines and IDs for NAND flash devices
  16  *
  17  * Changelog:
  18  *      See git changelog.
  19  */
  20 #ifndef __LINUX_MTD_NAND_H
  21 #define __LINUX_MTD_NAND_H
  22
  23 #include <linux/config.h>
  24 #include <linux/wait.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/mtd/mtd.h>
  27
  28 struct mtd_info;
  29 /* Scan and identify a NAND device */
  30 extern int nand_scan (struct mtd_info *mtd, int max_chips);
  31 /* Free resources held by the NAND device */
  32 extern void nand_release (struct mtd_info *mtd);
  33
  34 /* The maximum number of NAND chips in an array */
  35 #define NAND_MAX_CHIPS          8
  36
  37 /* This constant declares the max. oobsize / page, which
  38  * is supported now. If you add a chip with bigger oobsize/page
  39  * adjust this accordingly.
  40  */
  41 #define NAND_MAX_OOBSIZE        64
  42 #define NAND_MAX_PAGESIZE       2048
  43
  44 /*
  45  * Constants for hardware specific CLE/ALE/NCE function
  46  *
  47  * These are bits which can be or'ed to set/clear multiple
  48  * bits in one go.
  49  */
  50 /* Select the chip by setting nCE to low */
  51 #define NAND_NCE                0x01
  52 /* Select the command latch by setting CLE to high */
  53 #define NAND_CLE                0x02
  54 /* Select the address latch by setting ALE to high */
  55 #define NAND_ALE                0x04
  56
  57 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  58 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  59 #define NAND_CTRL_CHANGE        0x80
  60
  61 /*
  62  * Standard NAND flash commands
  63  */
  64 #define NAND_CMD_READ0          0
  65 #define NAND_CMD_READ1          1
  66 #define NAND_CMD_PAGEPROG       0x10
  67 #define NAND_CMD_READOOB        0x50
  68 #define NAND_CMD_ERASE1         0x60
  69 #define NAND_CMD_STATUS         0x70
  70 #define NAND_CMD_STATUS_MULTI   0x71
  71 #define NAND_CMD_SEQIN          0x80
  72 #define NAND_CMD_READID         0x90
  73 #define NAND_CMD_ERASE2         0xd0
  74 #define NAND_CMD_RESET          0xff
  75
  76 /* Extended commands for large page devices */
  77 #define NAND_CMD_READSTART      0x30
  78 #define NAND_CMD_CACHEDPROG     0x15
  79
  80 /* Extended commands for AG-AND device */
  81 /*
  82  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  83  *       there is no way to distinguish that from NAND_CMD_READ0
  84  *       until the remaining sequence of commands has been completed
  85  *       so add a high order bit and mask it off in the command.
  86  */
  87 #define NAND_CMD_DEPLETE1       0x100
  88 #define NAND_CMD_DEPLETE2       0x38
  89 #define NAND_CMD_STATUS_MULTI   0x71
  90 #define NAND_CMD_STATUS_ERROR   0x72
  91 /* multi-bank error status (banks 0-3) */
  92 #define NAND_CMD_STATUS_ERROR0  0x73
  93 #define NAND_CMD_STATUS_ERROR1  0x74
  94 #define NAND_CMD_STATUS_ERROR2  0x75
  95 #define NAND_CMD_STATUS_ERROR3  0x76
  96 #define NAND_CMD_STATUS_RESET   0x7f
  97 #define NAND_CMD_STATUS_CLEAR   0xff
  98
  99 #define NAND_CMD_NONE           -1
 100
 101 /* Status bits */
 102 #define NAND_STATUS_FAIL        0x01
 103 #define NAND_STATUS_FAIL_N1     0x02
 104 #define NAND_STATUS_TRUE_READY  0x20
 105 #define NAND_STATUS_READY       0x40
 106 #define NAND_STATUS_WP          0x80
 107
 108 /*
 109  * Constants for ECC_MODES
 110  */
 111 typedef enum {
 112         NAND_ECC_NONE,
 113         NAND_ECC_SOFT,
 114         NAND_ECC_HW,
 115         NAND_ECC_HW_SYNDROME,
 116 } nand_ecc_modes_t;
 117
 118 /*
 119  * Constants for Hardware ECC
 120  */
 121 /* Reset Hardware ECC for read */
 122 #define NAND_ECC_READ           0
 123 /* Reset Hardware ECC for write */
 124 #define NAND_ECC_WRITE          1
 125 /* Enable Hardware ECC before syndrom is read back from flash */
 126 #define NAND_ECC_READSYN        2
 127
 128 /* Bit mask for flags passed to do_nand_read_ecc */
 129 #define NAND_GET_DEVICE         0x80
 130
 131
 132 /* Option constants for bizarre disfunctionality and real
 133 *  features
 134 */
 135 /* Chip can not auto increment pages */
 136 #define NAND_NO_AUTOINCR        0x00000001
 137 /* Buswitdh is 16 bit */
 138 #define NAND_BUSWIDTH_16        0x00000002
 139 /* Device supports partial programming without padding */
 140 #define NAND_NO_PADDING         0x00000004
 141 /* Chip has cache program function */
 142 #define NAND_CACHEPRG           0x00000008
 143 /* Chip has copy back function */
 144 #define NAND_COPYBACK           0x00000010
 145 /* AND Chip which has 4 banks and a confusing page / block
 146  * assignment. See Renesas datasheet for further information */
 147 #define NAND_IS_AND             0x00000020
 148 /* Chip has a array of 4 pages which can be read without
 149  * additional ready /busy waits */
 150 #define NAND_4PAGE_ARRAY        0x00000040
 151 /* Chip requires that BBT is periodically rewritten to prevent
 152  * bits from adjacent blocks from 'leaking' in altering data.
 153  * This happens with the Renesas AG-AND chips, possibly others.  */
 154 #define BBT_AUTO_REFRESH        0x00000080
 155 /* Chip does not require ready check on read. True
 156  * for all large page devices, as they do not support
 157  * autoincrement.*/
 158 #define NAND_NO_READRDY         0x00000100
 159
 160 /* Options valid for Samsung large page devices */
 161 #define NAND_SAMSUNG_LP_OPTIONS \
 162         (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 163
 164 /* Macros to identify the above */
 165 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
 166 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 167 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 168 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 169
 170 /* Mask to zero out the chip options, which come from the id table */
 171 #define NAND_CHIPOPTIONS_MSK    (0x0000ffff & ~NAND_NO_AUTOINCR)
 172
 173 /* Non chip related options */
 174 /* Use a flash based bad block table. This option is passed to the
 175  * default bad block table function. */
 176 #define NAND_USE_FLASH_BBT      0x00010000
 177 /* This option skips the bbt scan during initialization. */
 178 #define NAND_SKIP_BBTSCAN       0x00020000
 179
 180 /* Options set by nand scan */
 181 /* Nand scan has allocated controller struct */
 182 #define NAND_CONTROLLER_ALLOC   0x80000000
 183
 184
 185 /*
 186  * nand_state_t - chip states
 187  * Enumeration for NAND flash chip state
 188  */
 189 typedef enum {
 190         FL_READY,
 191         FL_READING,
 192         FL_WRITING,
 193         FL_ERASING,
 194         FL_SYNCING,
 195         FL_CACHEDPRG,
 196         FL_PM_SUSPENDED,
 197 } nand_state_t;
 198
 199 /* Keep gcc happy */
 200 struct nand_chip;
 201
 202 /**
 203  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
 204  * @lock:               protection lock
 205  * @active:             the mtd device which holds the controller currently
 206  * @wq:                 wait queue to sleep on if a NAND operation is in progress
 207  *                      used instead of the per chip wait queue when a hw controller is available
 208  */
 209 struct nand_hw_control {
 210         spinlock_t       lock;
 211         struct nand_chip *active;
 212         wait_queue_head_t wq;
 213 };
 214
 215 /**
 216  * struct nand_ecc_ctrl - Control structure for ecc
 217  * @mode:       ecc mode
 218  * @steps:      number of ecc steps per page
 219  * @size:       data bytes per ecc step
 220  * @bytes:      ecc bytes per step
 221  * @total:      total number of ecc bytes per page
 222  * @prepad:     padding information for syndrome based ecc generators
 223  * @postpad:    padding information for syndrome based ecc generators
 224  * @hwctl:      function to control hardware ecc generator. Must only
 225  *              be provided if an hardware ECC is available
 226  * @calculate:  function for ecc calculation or readback from ecc hardware
 227  * @correct:    function for ecc correction, matching to ecc generator (sw/hw)
 228  * @read_page:  function to read a page according to the ecc generator requirements
 229  * @write_page: function to write a page according to the ecc generator requirements
 230  */
 231 struct nand_ecc_ctrl {
 232         nand_ecc_modes_t        mode;
 233         int                     steps;
 234         int                     size;
 235         int                     bytes;
 236         int                     total;
 237         int                     prepad;
 238         int                     postpad;
 239         struct nand_ecclayout   *layout;
 240         void                    (*hwctl)(struct mtd_info *mtd, int mode);
 241         int                     (*calculate)(struct mtd_info *mtd,
 242                                              const uint8_t *dat,
 243                                              uint8_t *ecc_code);
 244         int                     (*correct)(struct mtd_info *mtd, uint8_t *dat,
 245                                            uint8_t *read_ecc,
 246                                            uint8_t *calc_ecc);
 247         int                     (*read_page)(struct mtd_info *mtd,
 248                                              struct nand_chip *chip,
 249                                              uint8_t *buf);
 250         void                    (*write_page)(struct mtd_info *mtd,
 251                                               struct nand_chip *chip,
 252                                               const uint8_t *buf);
 253 };
 254
 255 /**
 256  * struct nand_buffers - buffer structure for read/write
 257  * @ecccalc:    buffer for calculated ecc
 258  * @ecccode:    buffer for ecc read from flash
 259  * @oobwbuf:    buffer for write oob data
 260  * @databuf:    buffer for data - dynamically sized
 261  * @oobrbuf:    buffer to read oob data
 262  *
 263  * Do not change the order of buffers. databuf and oobrbuf must be in
 264  * consecutive order.
 265  */
 266 struct nand_buffers {
 267         uint8_t ecccalc[NAND_MAX_OOBSIZE];
 268         uint8_t ecccode[NAND_MAX_OOBSIZE];
 269         uint8_t oobwbuf[NAND_MAX_OOBSIZE];
 270         uint8_t databuf[NAND_MAX_PAGESIZE];
 271         uint8_t oobrbuf[NAND_MAX_OOBSIZE];
 272 };
 273
 274 /**
 275  * struct nand_chip - NAND Private Flash Chip Data
 276  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
 277  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
 278  * @read_byte:          [REPLACEABLE] read one byte from the chip
 279  * @read_word:          [REPLACEABLE] read one word from the chip
 280  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 281  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 282  * @verify_buf:         [REPLACEABLE] verify buffer contents against the chip data
 283  * @select_chip:        [REPLACEABLE] select chip nr
 284  * @block_bad:          [REPLACEABLE] check, if the block is bad
 285  * @block_markbad:      [REPLACEABLE] mark the block bad
 286  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific funtion for controlling
 287  *                      ALE/CLE/nCE. Also used to write command and address
 288  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
 289  *                      If set to NULL no access to ready/busy is available and the ready/busy information
 290  *                      is read from the chip status register
 291  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing commands to the chip
 292  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on ready
 293  * @ecc:                [BOARDSPECIFIC] ecc control ctructure
 294  * @erase_cmd:          [INTERN] erase command write function, selectable due to AND support
 295  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 296  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
 297  * @wq:                 [INTERN] wait queue to sleep on if a NAND operation is in progress
 298  * @state:              [INTERN] the current state of the NAND device
 299  * @page_shift:         [INTERN] number of address bits in a page (column address bits)
 300  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 301  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 302  * @chip_shift:         [INTERN] number of address bits in one chip
 303  * @datbuf:             [INTERN] internal buffer for one page + oob
 304  * @oobbuf:             [INTERN] oob buffer for one eraseblock
 305  * @oobdirty:           [INTERN] indicates that oob_buf must be reinitialized
 306  * @data_poi:           [INTERN] pointer to a data buffer
 307  * @options:            [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
 308  *                      special functionality. See the defines for further explanation
 309  * @badblockpos:        [INTERN] position of the bad block marker in the oob area
 310  * @numchips:           [INTERN] number of physical chips
 311  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 312  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 313  * @pagebuf:            [INTERN] holds the pagenumber which is currently in data_buf
 314  * @ecclayout:          [REPLACEABLE] the default ecc placement scheme
 315  * @bbt:                [INTERN] bad block table pointer
 316  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash lookup
 317  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 318  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial bad block scan
 319  * @controller:         [REPLACEABLE] a pointer to a hardware controller structure
 320  *                      which is shared among multiple independend devices
 321  * @priv:               [OPTIONAL] pointer to private chip date
 322  * @errstat:            [OPTIONAL] hardware specific function to perform additional error status checks
 323  *                      (determine if errors are correctable)
 324  */
 325
 326 struct nand_chip {
 327         void  __iomem   *IO_ADDR_R;
 328         void  __iomem   *IO_ADDR_W;
 329
 330         uint8_t         (*read_byte)(struct mtd_info *mtd);
 331         u16             (*read_word)(struct mtd_info *mtd);
 332         void            (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 333         void            (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 334         int             (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 335         void            (*select_chip)(struct mtd_info *mtd, int chip);
 336         int             (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 337         int             (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 338         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 339                                     unsigned int ctrl);
 340         int             (*dev_ready)(struct mtd_info *mtd);
 341         void            (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
 342         int             (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
 343         void            (*erase_cmd)(struct mtd_info *mtd, int page);
 344         int             (*scan_bbt)(struct mtd_info *mtd);
 345         int             (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
 346
 347         int             chip_delay;
 348         unsigned int    options;
 349
 350         int             page_shift;
 351         int             phys_erase_shift;
 352         int             bbt_erase_shift;
 353         int             chip_shift;
 354         int             numchips;
 355         unsigned long   chipsize;
 356         int             pagemask;
 357         int             pagebuf;
 358         int             badblockpos;
 359
 360         nand_state_t    state;
 361
 362         uint8_t         *oob_poi;
 363         struct nand_hw_control  *controller;
 364         struct nand_ecclayout   *ecclayout;
 365
 366         struct nand_ecc_ctrl ecc;
 367         struct nand_buffers buffers;
 368         struct nand_hw_control hwcontrol;
 369
 370         struct mtd_oob_ops ops;
 371
 372         uint8_t         *bbt;
 373         struct nand_bbt_descr   *bbt_td;
 374         struct nand_bbt_descr   *bbt_md;
 375
 376         struct nand_bbt_descr   *badblock_pattern;
 377
 378         void            *priv;
 379 };
 380
 381 /*
 382  * NAND Flash Manufacturer ID Codes
 383  */
 384 #define NAND_MFR_TOSHIBA        0x98
 385 #define NAND_MFR_SAMSUNG        0xec
 386 #define NAND_MFR_FUJITSU        0x04
 387 #define NAND_MFR_NATIONAL       0x8f
 388 #define NAND_MFR_RENESAS        0x07
 389 #define NAND_MFR_STMICRO        0x20
 390 #define NAND_MFR_HYNIX          0xad
 391
 392 /**
 393  * struct nand_flash_dev - NAND Flash Device ID Structure
 394  *
 395  * @name:       Identify the device type
 396  * @id:         device ID code
 397  * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 398  *              If the pagesize is 0, then the real pagesize
 399  *              and the eraseize are determined from the
 400  *              extended id bytes in the chip
 401  * @erasesize:  Size of an erase block in the flash device.
 402  * @chipsize:   Total chipsize in Mega Bytes
 403  * @options:    Bitfield to store chip relevant options
 404  */
 405 struct nand_flash_dev {
 406         char *name;
 407         int id;
 408         unsigned long pagesize;
 409         unsigned long chipsize;
 410         unsigned long erasesize;
 411         unsigned long options;
 412 };
 413
 414 /**
 415  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 416  * @name:       Manufacturer name
 417  * @id:         manufacturer ID code of device.
 418 */
 419 struct nand_manufacturers {
 420         int id;
 421         char * name;
 422 };
 423
 424 extern struct nand_flash_dev nand_flash_ids[];
 425 extern struct nand_manufacturers nand_manuf_ids[];
 426
 427 /**
 428  * struct nand_bbt_descr - bad block table descriptor
 429  * @options:    options for this descriptor
 430  * @pages:      the page(s) where we find the bbt, used with option BBT_ABSPAGE
 431  *              when bbt is searched, then we store the found bbts pages here.
 432  *              Its an array and supports up to 8 chips now
 433  * @offs:       offset of the pattern in the oob area of the page
 434  * @veroffs:    offset of the bbt version counter in the oob are of the page
 435  * @version:    version read from the bbt page during scan
 436  * @len:        length of the pattern, if 0 no pattern check is performed
 437  * @maxblocks:  maximum number of blocks to search for a bbt. This number of
 438  *              blocks is reserved at the end of the device where the tables are
 439  *              written.
 440  * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
 441  *              bad) block in the stored bbt
 442  * @pattern:    pattern to identify bad block table or factory marked good /
 443  *              bad blocks, can be NULL, if len = 0
 444  *
 445  * Descriptor for the bad block table marker and the descriptor for the
 446  * pattern which identifies good and bad blocks. The assumption is made
 447  * that the pattern and the version count are always located in the oob area
 448  * of the first block.
 449  */
 450 struct nand_bbt_descr {
 451         int     options;
 452         int     pages[NAND_MAX_CHIPS];
 453         int     offs;
 454         int     veroffs;
 455         uint8_t version[NAND_MAX_CHIPS];
 456         int     len;
 457         int     maxblocks;
 458         int     reserved_block_code;
 459         uint8_t *pattern;
 460 };
 461
 462 /* Options for the bad block table descriptors */
 463
 464 /* The number of bits used per block in the bbt on the device */
 465 #define NAND_BBT_NRBITS_MSK     0x0000000F
 466 #define NAND_BBT_1BIT           0x00000001
 467 #define NAND_BBT_2BIT           0x00000002
 468 #define NAND_BBT_4BIT           0x00000004
 469 #define NAND_BBT_8BIT           0x00000008
 470 /* The bad block table is in the last good block of the device */
 471 #define NAND_BBT_LASTBLOCK      0x00000010
 472 /* The bbt is at the given page, else we must scan for the bbt */
 473 #define NAND_BBT_ABSPAGE        0x00000020
 474 /* The bbt is at the given page, else we must scan for the bbt */
 475 #define NAND_BBT_SEARCH         0x00000040
 476 /* bbt is stored per chip on multichip devices */
 477 #define NAND_BBT_PERCHIP        0x00000080
 478 /* bbt has a version counter at offset veroffs */
 479 #define NAND_BBT_VERSION        0x00000100
 480 /* Create a bbt if none axists */
 481 #define NAND_BBT_CREATE         0x00000200
 482 /* Search good / bad pattern through all pages of a block */
 483 #define NAND_BBT_SCANALLPAGES   0x00000400
 484 /* Scan block empty during good / bad block scan */
 485 #define NAND_BBT_SCANEMPTY      0x00000800
 486 /* Write bbt if neccecary */
 487 #define NAND_BBT_WRITE          0x00001000
 488 /* Read and write back block contents when writing bbt */
 489 #define NAND_BBT_SAVECONTENT    0x00002000
 490 /* Search good / bad pattern on the first and the second page */
 491 #define NAND_BBT_SCAN2NDPAGE    0x00004000
 492
 493 /* The maximum number of blocks to scan for a bbt */
 494 #define NAND_BBT_SCAN_MAXBLOCKS 4
 495
 496 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 497 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 498 extern int nand_default_bbt(struct mtd_info *mtd);
 499 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 500 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 501                            int allowbbt);
 502 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 503                         size_t * retlen, uint8_t * buf);
 504
 505 /*
 506 * Constants for oob configuration
 507 */
 508 #define NAND_SMALL_BADBLOCK_POS         5
 509 #define NAND_LARGE_BADBLOCK_POS         0
 510
 511 /**
 512  * struct platform_nand_chip - chip level device structure
 513  *
 514  * @nr_chips:           max. number of chips to scan for
 515  * @chip_offs:          chip number offset
 516  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 517  * @partitions:         mtd partition list
 518  * @chip_delay:         R/B delay value in us
 519  * @options:            Option flags, e.g. 16bit buswidth
 520  * @ecclayout:          ecc layout info structure
 521  * @priv:               hardware controller specific settings
 522  */
 523 struct platform_nand_chip {
 524         int                     nr_chips;
 525         int                     chip_offset;
 526         int                     nr_partitions;
 527         struct mtd_partition    *partitions;
 528         struct nand_ecclayout   *ecclayout;
 529         int                     chip_delay;
 530         unsigned int            options;
 531         void                    *priv;
 532 };
 533
 534 /**
 535  * struct platform_nand_ctrl - controller level device structure
 536  *
 537  * @hwcontrol:          platform specific hardware control structure
 538  * @dev_ready:          platform specific function to read ready/busy pin
 539  * @select_chip:        platform specific chip select function
 540  * @priv_data:          private data to transport driver specific settings
 541  *
 542  * All fields are optional and depend on the hardware driver requirements
 543  */
 544 struct platform_nand_ctrl {
 545         void            (*hwcontrol)(struct mtd_info *mtd, int cmd);
 546         int             (*dev_ready)(struct mtd_info *mtd);
 547         void            (*select_chip)(struct mtd_info *mtd, int chip);
 548         void            *priv;
 549 };
 550
 551 /* Some helpers to access the data structures */
 552 static inline
 553 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 554 {
 555         struct nand_chip *chip = mtd->priv;
 556
 557         return chip->priv;
 558 }
 559
 560 #endif /* __LINUX_MTD_NAND_H */