2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * $Id: nand.h,v 1.69 2005/01/17 18:29:18 dmarlin Exp $
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * Contains standard defines and IDs for NAND flash devices
18 * 01-31-2000 DMW Created
19 * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
20 * so it can be used by other NAND flash device
21 * drivers. I also changed the copyright since none
22 * of the original contents of this file are specific
23 * to DoC devices. David can whack me with a baseball
24 * bat later if I did something naughty.
25 * 10-11-2000 SJH Added private NAND flash structure for driver
26 * 10-24-2000 SJH Added prototype for 'nand_scan' function
27 * 10-29-2001 TG changed nand_chip structure to support
28 * hardwarespecific function for accessing control lines
29 * 02-21-2002 TG added support for different read/write adress and
30 * ready/busy line access function
31 * 02-26-2002 TG added chip_delay to nand_chip structure to optimize
32 * command delay times for different chips
33 * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
34 * defines in jffs2/wbuf.c
35 * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if
36 * CONFIG_MTD_NAND_ECC_JFFS2 is not set
37 * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
39 * 08-29-2002 tglx nand_chip structure: data_poi for selecting
40 * internal / fs-driver buffer
41 * support for 6byte/512byte hardware ECC
42 * read_ecc, write_ecc extended for different oob-layout
43 * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
45 * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
46 * Split manufacturer and device ID structures
48 * 02-08-2004 tglx added option field to nand structure for chip anomalities
49 * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
50 * update of nand_chip structure description
51 * 01-17-2005 dmarlin added extended commands for AG-AND device and added option
52 * for BBT_AUTO_REFRESH.
54 #ifndef __LINUX_MTD_NAND_H
55 #define __LINUX_MTD_NAND_H
57 #include <linux/config.h>
58 #include <linux/wait.h>
59 #include <linux/spinlock.h>
60 #include <linux/mtd/mtd.h>
63 /* Scan and identify a NAND device */
64 extern int nand_scan (struct mtd_info
*mtd
, int max_chips
);
65 /* Free resources held by the NAND device */
66 extern void nand_release (struct mtd_info
*mtd
);
68 /* Read raw data from the device without ECC */
69 extern int nand_read_raw (struct mtd_info
*mtd
, uint8_t *buf
, loff_t from
, size_t len
, size_t ooblen
);
72 /* The maximum number of NAND chips in an array */
73 #define NAND_MAX_CHIPS 8
75 /* This constant declares the max. oobsize / page, which
76 * is supported now. If you add a chip with bigger oobsize/page
77 * adjust this accordingly.
79 #define NAND_MAX_OOBSIZE 64
82 * Constants for hardware specific CLE/ALE/NCE function
84 /* Select the chip by setting nCE to low */
85 #define NAND_CTL_SETNCE 1
86 /* Deselect the chip by setting nCE to high */
87 #define NAND_CTL_CLRNCE 2
88 /* Select the command latch by setting CLE to high */
89 #define NAND_CTL_SETCLE 3
90 /* Deselect the command latch by setting CLE to low */
91 #define NAND_CTL_CLRCLE 4
92 /* Select the address latch by setting ALE to high */
93 #define NAND_CTL_SETALE 5
94 /* Deselect the address latch by setting ALE to low */
95 #define NAND_CTL_CLRALE 6
96 /* Set write protection by setting WP to high. Not used! */
97 #define NAND_CTL_SETWP 7
98 /* Clear write protection by setting WP to low. Not used! */
99 #define NAND_CTL_CLRWP 8
102 * Standard NAND flash commands
104 #define NAND_CMD_READ0 0
105 #define NAND_CMD_READ1 1
106 #define NAND_CMD_PAGEPROG 0x10
107 #define NAND_CMD_READOOB 0x50
108 #define NAND_CMD_ERASE1 0x60
109 #define NAND_CMD_STATUS 0x70
110 #define NAND_CMD_STATUS_MULTI 0x71
111 #define NAND_CMD_SEQIN 0x80
112 #define NAND_CMD_READID 0x90
113 #define NAND_CMD_ERASE2 0xd0
114 #define NAND_CMD_RESET 0xff
116 /* Extended commands for large page devices */
117 #define NAND_CMD_READSTART 0x30
118 #define NAND_CMD_CACHEDPROG 0x15
120 /* Extended commands for AG-AND device */
122 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
123 * there is no way to distinguish that from NAND_CMD_READ0
124 * until the remaining sequence of commands has been completed
125 * so add a high order bit and mask it off in the command.
127 #define NAND_CMD_DEPLETE1 0x100
128 #define NAND_CMD_DEPLETE2 0x38
129 #define NAND_CMD_STATUS_MULTI 0x71
130 #define NAND_CMD_STATUS_ERROR 0x72
131 /* multi-bank error status (banks 0-3) */
132 #define NAND_CMD_STATUS_ERROR0 0x73
133 #define NAND_CMD_STATUS_ERROR1 0x74
134 #define NAND_CMD_STATUS_ERROR2 0x75
135 #define NAND_CMD_STATUS_ERROR3 0x76
136 #define NAND_CMD_STATUS_RESET 0x7f
137 #define NAND_CMD_STATUS_CLEAR 0xff
140 #define NAND_STATUS_FAIL 0x01
141 #define NAND_STATUS_FAIL_N1 0x02
142 #define NAND_STATUS_TRUE_READY 0x20
143 #define NAND_STATUS_READY 0x40
144 #define NAND_STATUS_WP 0x80
147 * Constants for ECC_MODES
150 /* No ECC. Usage is not recommended ! */
151 #define NAND_ECC_NONE 0
152 /* Software ECC 3 byte ECC per 256 Byte data */
153 #define NAND_ECC_SOFT 1
154 /* Hardware ECC 3 byte ECC per 256 Byte data */
155 #define NAND_ECC_HW3_256 2
156 /* Hardware ECC 3 byte ECC per 512 Byte data */
157 #define NAND_ECC_HW3_512 3
158 /* Hardware ECC 3 byte ECC per 512 Byte data */
159 #define NAND_ECC_HW6_512 4
160 /* Hardware ECC 8 byte ECC per 512 Byte data */
161 #define NAND_ECC_HW8_512 6
162 /* Hardware ECC 12 byte ECC per 2048 Byte data */
163 #define NAND_ECC_HW12_2048 7
166 * Constants for Hardware ECC
168 /* Reset Hardware ECC for read */
169 #define NAND_ECC_READ 0
170 /* Reset Hardware ECC for write */
171 #define NAND_ECC_WRITE 1
172 /* Enable Hardware ECC before syndrom is read back from flash */
173 #define NAND_ECC_READSYN 2
175 /* Option constants for bizarre disfunctionality and real
178 /* Chip can not auto increment pages */
179 #define NAND_NO_AUTOINCR 0x00000001
180 /* Buswitdh is 16 bit */
181 #define NAND_BUSWIDTH_16 0x00000002
182 /* Device supports partial programming without padding */
183 #define NAND_NO_PADDING 0x00000004
184 /* Chip has cache program function */
185 #define NAND_CACHEPRG 0x00000008
186 /* Chip has copy back function */
187 #define NAND_COPYBACK 0x00000010
188 /* AND Chip which has 4 banks and a confusing page / block
189 * assignment. See Renesas datasheet for further information */
190 #define NAND_IS_AND 0x00000020
191 /* Chip has a array of 4 pages which can be read without
192 * additional ready /busy waits */
193 #define NAND_4PAGE_ARRAY 0x00000040
194 /* Chip requires that BBT is periodically rewritten to prevent
195 * bits from adjacent blocks from 'leaking' in altering data.
196 * This happens with the Renesas AG-AND chips, possibly others. */
197 #define BBT_AUTO_REFRESH 0x00000080
199 /* Options valid for Samsung large page devices */
200 #define NAND_SAMSUNG_LP_OPTIONS \
201 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
203 /* Macros to identify the above */
204 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
205 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
206 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
207 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
209 /* Mask to zero out the chip options, which come from the id table */
210 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
212 /* Non chip related options */
213 /* Use a flash based bad block table. This option is passed to the
214 * default bad block table function. */
215 #define NAND_USE_FLASH_BBT 0x00010000
216 /* The hw ecc generator provides a syndrome instead a ecc value on read
217 * This can only work if we have the ecc bytes directly behind the
218 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
219 #define NAND_HWECC_SYNDROME 0x00020000
222 /* Options set by nand scan */
223 /* Nand scan has allocated oob_buf */
224 #define NAND_OOBBUF_ALLOC 0x40000000
225 /* Nand scan has allocated data_buf */
226 #define NAND_DATABUF_ALLOC 0x80000000
230 * nand_state_t - chip states
231 * Enumeration for NAND flash chip state
246 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
247 * @lock: protection lock
248 * @active: the mtd device which holds the controller currently
250 struct nand_hw_control
{
252 struct nand_chip
*active
;
256 * struct nand_chip - NAND Private Flash Chip Data
257 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
258 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
259 * @read_byte: [REPLACEABLE] read one byte from the chip
260 * @write_byte: [REPLACEABLE] write one byte to the chip
261 * @read_word: [REPLACEABLE] read one word from the chip
262 * @write_word: [REPLACEABLE] write one word to the chip
263 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
264 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
265 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
266 * @select_chip: [REPLACEABLE] select chip nr
267 * @block_bad: [REPLACEABLE] check, if the block is bad
268 * @block_markbad: [REPLACEABLE] mark the block bad
269 * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
270 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
271 * If set to NULL no access to ready/busy is available and the ready/busy information
272 * is read from the chip status register
273 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
274 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
275 * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
276 * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
277 * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
278 * be provided if a hardware ECC is available
279 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
280 * @scan_bbt: [REPLACEABLE] function to scan bad block table
281 * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
282 * @eccsize: [INTERN] databytes used per ecc-calculation
283 * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
284 * @eccsteps: [INTERN] number of ecc calculation steps per page
285 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
286 * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
287 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
288 * @state: [INTERN] the current state of the NAND device
289 * @page_shift: [INTERN] number of address bits in a page (column address bits)
290 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
291 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
292 * @chip_shift: [INTERN] number of address bits in one chip
293 * @data_buf: [INTERN] internal buffer for one page + oob
294 * @oob_buf: [INTERN] oob buffer for one eraseblock
295 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
296 * @data_poi: [INTERN] pointer to a data buffer
297 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
298 * special functionality. See the defines for further explanation
299 * @badblockpos: [INTERN] position of the bad block marker in the oob area
300 * @numchips: [INTERN] number of physical chips
301 * @chipsize: [INTERN] the size of one chip for multichip arrays
302 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
303 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
304 * @autooob: [REPLACEABLE] the default (auto)placement scheme
305 * @bbt: [INTERN] bad block table pointer
306 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
307 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
308 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
309 * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
310 * @priv: [OPTIONAL] pointer to private chip date
314 void __iomem
*IO_ADDR_R
;
315 void __iomem
*IO_ADDR_W
;
317 u_char (*read_byte
)(struct mtd_info
*mtd
);
318 void (*write_byte
)(struct mtd_info
*mtd
, u_char byte
);
319 u16 (*read_word
)(struct mtd_info
*mtd
);
320 void (*write_word
)(struct mtd_info
*mtd
, u16 word
);
322 void (*write_buf
)(struct mtd_info
*mtd
, const u_char
*buf
, int len
);
323 void (*read_buf
)(struct mtd_info
*mtd
, u_char
*buf
, int len
);
324 int (*verify_buf
)(struct mtd_info
*mtd
, const u_char
*buf
, int len
);
325 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
326 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
, int getchip
);
327 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
328 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
329 int (*dev_ready
)(struct mtd_info
*mtd
);
330 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
, int page_addr
);
331 int (*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
);
332 int (*calculate_ecc
)(struct mtd_info
*mtd
, const u_char
*dat
, u_char
*ecc_code
);
333 int (*correct_data
)(struct mtd_info
*mtd
, u_char
*dat
, u_char
*read_ecc
, u_char
*calc_ecc
);
334 void (*enable_hwecc
)(struct mtd_info
*mtd
, int mode
);
335 void (*erase_cmd
)(struct mtd_info
*mtd
, int page
);
336 int (*scan_bbt
)(struct mtd_info
*mtd
);
342 spinlock_t chip_lock
;
343 wait_queue_head_t wq
;
346 int phys_erase_shift
;
353 unsigned int options
;
356 unsigned long chipsize
;
359 struct nand_oobinfo
*autooob
;
361 struct nand_bbt_descr
*bbt_td
;
362 struct nand_bbt_descr
*bbt_md
;
363 struct nand_bbt_descr
*badblock_pattern
;
364 struct nand_hw_control
*controller
;
369 * NAND Flash Manufacturer ID Codes
371 #define NAND_MFR_TOSHIBA 0x98
372 #define NAND_MFR_SAMSUNG 0xec
373 #define NAND_MFR_FUJITSU 0x04
374 #define NAND_MFR_NATIONAL 0x8f
375 #define NAND_MFR_RENESAS 0x07
376 #define NAND_MFR_STMICRO 0x20
379 * struct nand_flash_dev - NAND Flash Device ID Structure
381 * @name: Identify the device type
382 * @id: device ID code
383 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
384 * If the pagesize is 0, then the real pagesize
385 * and the eraseize are determined from the
386 * extended id bytes in the chip
387 * @erasesize: Size of an erase block in the flash device.
388 * @chipsize: Total chipsize in Mega Bytes
389 * @options: Bitfield to store chip relevant options
391 struct nand_flash_dev
{
394 unsigned long pagesize
;
395 unsigned long chipsize
;
396 unsigned long erasesize
;
397 unsigned long options
;
401 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
402 * @name: Manufacturer name
403 * @id: manufacturer ID code of device.
405 struct nand_manufacturers
{
410 extern struct nand_flash_dev nand_flash_ids
[];
411 extern struct nand_manufacturers nand_manuf_ids
[];
414 * struct nand_bbt_descr - bad block table descriptor
415 * @options: options for this descriptor
416 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
417 * when bbt is searched, then we store the found bbts pages here.
418 * Its an array and supports up to 8 chips now
419 * @offs: offset of the pattern in the oob area of the page
420 * @veroffs: offset of the bbt version counter in the oob are of the page
421 * @version: version read from the bbt page during scan
422 * @len: length of the pattern, if 0 no pattern check is performed
423 * @maxblocks: maximum number of blocks to search for a bbt. This number of
424 * blocks is reserved at the end of the device where the tables are
426 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
427 * bad) block in the stored bbt
428 * @pattern: pattern to identify bad block table or factory marked good /
429 * bad blocks, can be NULL, if len = 0
431 * Descriptor for the bad block table marker and the descriptor for the
432 * pattern which identifies good and bad blocks. The assumption is made
433 * that the pattern and the version count are always located in the oob area
434 * of the first block.
436 struct nand_bbt_descr
{
438 int pages
[NAND_MAX_CHIPS
];
441 uint8_t version
[NAND_MAX_CHIPS
];
444 int reserved_block_code
;
448 /* Options for the bad block table descriptors */
450 /* The number of bits used per block in the bbt on the device */
451 #define NAND_BBT_NRBITS_MSK 0x0000000F
452 #define NAND_BBT_1BIT 0x00000001
453 #define NAND_BBT_2BIT 0x00000002
454 #define NAND_BBT_4BIT 0x00000004
455 #define NAND_BBT_8BIT 0x00000008
456 /* The bad block table is in the last good block of the device */
457 #define NAND_BBT_LASTBLOCK 0x00000010
458 /* The bbt is at the given page, else we must scan for the bbt */
459 #define NAND_BBT_ABSPAGE 0x00000020
460 /* The bbt is at the given page, else we must scan for the bbt */
461 #define NAND_BBT_SEARCH 0x00000040
462 /* bbt is stored per chip on multichip devices */
463 #define NAND_BBT_PERCHIP 0x00000080
464 /* bbt has a version counter at offset veroffs */
465 #define NAND_BBT_VERSION 0x00000100
466 /* Create a bbt if none axists */
467 #define NAND_BBT_CREATE 0x00000200
468 /* Search good / bad pattern through all pages of a block */
469 #define NAND_BBT_SCANALLPAGES 0x00000400
470 /* Scan block empty during good / bad block scan */
471 #define NAND_BBT_SCANEMPTY 0x00000800
472 /* Write bbt if neccecary */
473 #define NAND_BBT_WRITE 0x00001000
474 /* Read and write back block contents when writing bbt */
475 #define NAND_BBT_SAVECONTENT 0x00002000
476 /* Search good / bad pattern on the first and the second page */
477 #define NAND_BBT_SCAN2NDPAGE 0x00004000
479 /* The maximum number of blocks to scan for a bbt */
480 #define NAND_BBT_SCAN_MAXBLOCKS 4
482 extern int nand_scan_bbt (struct mtd_info
*mtd
, struct nand_bbt_descr
*bd
);
483 extern int nand_update_bbt (struct mtd_info
*mtd
, loff_t offs
);
484 extern int nand_default_bbt (struct mtd_info
*mtd
);
485 extern int nand_isbad_bbt (struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
486 extern int nand_erase_nand (struct mtd_info
*mtd
, struct erase_info
*instr
, int allowbbt
);
489 * Constants for oob configuration
491 #define NAND_SMALL_BADBLOCK_POS 5
492 #define NAND_LARGE_BADBLOCK_POS 0
494 #endif /* __LINUX_MTD_NAND_H */