2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev
;
31 /* Scan and identify a NAND device */
32 int nand_scan(struct mtd_info
*mtd
, int max_chips
);
34 * Separate phases of nand_scan(), allowing board driver to intervene
35 * and override command or ECC setup according to flash type.
37 int nand_scan_ident(struct mtd_info
*mtd
, int max_chips
,
38 struct nand_flash_dev
*table
);
39 int nand_scan_tail(struct mtd_info
*mtd
);
41 /* Unregister the MTD device and free resources held by the NAND device */
42 void nand_release(struct mtd_info
*mtd
);
44 /* Internal helper for board drivers which need to override command function */
45 void nand_wait_ready(struct mtd_info
*mtd
);
47 /* locks all blocks present in the device */
48 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
50 /* unlocks specified locked blocks */
51 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
53 /* The maximum number of NAND chips in an array */
54 #define NAND_MAX_CHIPS 8
57 * Constants for hardware specific CLE/ALE/NCE function
59 * These are bits which can be or'ed to set/clear multiple
62 /* Select the chip by setting nCE to low */
64 /* Select the command latch by setting CLE to high */
66 /* Select the address latch by setting ALE to high */
69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
71 #define NAND_CTRL_CHANGE 0x80
74 * Standard NAND flash commands
76 #define NAND_CMD_READ0 0
77 #define NAND_CMD_READ1 1
78 #define NAND_CMD_RNDOUT 5
79 #define NAND_CMD_PAGEPROG 0x10
80 #define NAND_CMD_READOOB 0x50
81 #define NAND_CMD_ERASE1 0x60
82 #define NAND_CMD_STATUS 0x70
83 #define NAND_CMD_SEQIN 0x80
84 #define NAND_CMD_RNDIN 0x85
85 #define NAND_CMD_READID 0x90
86 #define NAND_CMD_ERASE2 0xd0
87 #define NAND_CMD_PARAM 0xec
88 #define NAND_CMD_GET_FEATURES 0xee
89 #define NAND_CMD_SET_FEATURES 0xef
90 #define NAND_CMD_RESET 0xff
92 #define NAND_CMD_LOCK 0x2a
93 #define NAND_CMD_UNLOCK1 0x23
94 #define NAND_CMD_UNLOCK2 0x24
96 /* Extended commands for large page devices */
97 #define NAND_CMD_READSTART 0x30
98 #define NAND_CMD_RNDOUTSTART 0xE0
99 #define NAND_CMD_CACHEDPROG 0x15
101 #define NAND_CMD_NONE -1
104 #define NAND_STATUS_FAIL 0x01
105 #define NAND_STATUS_FAIL_N1 0x02
106 #define NAND_STATUS_TRUE_READY 0x20
107 #define NAND_STATUS_READY 0x40
108 #define NAND_STATUS_WP 0x80
111 * Constants for ECC_MODES
117 NAND_ECC_HW_SYNDROME
,
118 NAND_ECC_HW_OOB_FIRST
,
128 * Constants for Hardware ECC
130 /* Reset Hardware ECC for read */
131 #define NAND_ECC_READ 0
132 /* Reset Hardware ECC for write */
133 #define NAND_ECC_WRITE 1
134 /* Enable Hardware ECC before syndrome is read back from flash */
135 #define NAND_ECC_READSYN 2
138 * Enable generic NAND 'page erased' check. This check is only done when
139 * ecc.correct() returns -EBADMSG.
140 * Set this flag if your implementation does not fix bitflips in erased
141 * pages and you want to rely on the default implementation.
143 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
144 #define NAND_ECC_MAXIMIZE BIT(1)
146 /* Bit mask for flags passed to do_nand_read_ecc */
147 #define NAND_GET_DEVICE 0x80
151 * Option constants for bizarre disfunctionality and real
154 /* Buswidth is 16 bit */
155 #define NAND_BUSWIDTH_16 0x00000002
156 /* Chip has cache program function */
157 #define NAND_CACHEPRG 0x00000008
159 * Chip requires ready check on read (for auto-incremented sequential read).
160 * True only for small page devices; large page devices do not support
163 #define NAND_NEED_READRDY 0x00000100
165 /* Chip does not allow subpage writes */
166 #define NAND_NO_SUBPAGE_WRITE 0x00000200
168 /* Device is one of 'new' xD cards that expose fake nand command set */
169 #define NAND_BROKEN_XD 0x00000400
171 /* Device behaves just like nand, but is readonly */
172 #define NAND_ROM 0x00000800
174 /* Device supports subpage reads */
175 #define NAND_SUBPAGE_READ 0x00001000
178 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
181 #define NAND_NEED_SCRAMBLING 0x00002000
183 /* Options valid for Samsung large page devices */
184 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
186 /* Macros to identify the above */
187 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
188 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
190 /* Non chip related options */
191 /* This option skips the bbt scan during initialization. */
192 #define NAND_SKIP_BBTSCAN 0x00010000
194 * This option is defined if the board driver allocates its own buffers
195 * (e.g. because it needs them DMA-coherent).
197 #define NAND_OWN_BUFFERS 0x00020000
198 /* Chip may not exist, so silence any errors in scan */
199 #define NAND_SCAN_SILENT_NODEV 0x00040000
201 * Autodetect nand buswidth with readid/onfi.
202 * This suppose the driver will configure the hardware in 8 bits mode
203 * when calling nand_scan_ident, and update its configuration
204 * before calling nand_scan_tail.
206 #define NAND_BUSWIDTH_AUTO 0x00080000
208 * This option could be defined by controller drivers to protect against
209 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
211 #define NAND_USE_BOUNCE_BUFFER 0x00100000
213 /* Options set by nand scan */
214 /* Nand scan has allocated controller struct */
215 #define NAND_CONTROLLER_ALLOC 0x80000000
217 /* Cell info constants */
218 #define NAND_CI_CHIPNR_MSK 0x03
219 #define NAND_CI_CELLTYPE_MSK 0x0C
220 #define NAND_CI_CELLTYPE_SHIFT 2
226 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
227 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
229 /* ONFI timing mode, used in both asynchronous and synchronous mode */
230 #define ONFI_TIMING_MODE_0 (1 << 0)
231 #define ONFI_TIMING_MODE_1 (1 << 1)
232 #define ONFI_TIMING_MODE_2 (1 << 2)
233 #define ONFI_TIMING_MODE_3 (1 << 3)
234 #define ONFI_TIMING_MODE_4 (1 << 4)
235 #define ONFI_TIMING_MODE_5 (1 << 5)
236 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
238 /* ONFI feature address */
239 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
241 /* Vendor-specific feature address (Micron) */
242 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
244 /* ONFI subfeature parameters length */
245 #define ONFI_SUBFEATURE_PARAM_LEN 4
247 /* ONFI optional commands SET/GET FEATURES supported? */
248 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
250 struct nand_onfi_params
{
251 /* rev info and features block */
252 /* 'O' 'N' 'F' 'I' */
258 __le16 ext_param_page_length
; /* since ONFI 2.1 */
259 u8 num_of_param_pages
; /* since ONFI 2.1 */
262 /* manufacturer information block */
263 char manufacturer
[12];
269 /* memory organization block */
270 __le32 byte_per_page
;
271 __le16 spare_bytes_per_page
;
272 __le32 data_bytes_per_ppage
;
273 __le16 spare_bytes_per_ppage
;
274 __le32 pages_per_block
;
275 __le32 blocks_per_lun
;
280 __le16 block_endurance
;
281 u8 guaranteed_good_blocks
;
282 __le16 guaranteed_block_endurance
;
283 u8 programs_per_page
;
290 /* electrical parameter block */
291 u8 io_pin_capacitance_max
;
292 __le16 async_timing_mode
;
293 __le16 program_cache_timing_mode
;
298 __le16 src_sync_timing_mode
;
299 u8 src_ssync_features
;
300 __le16 clk_pin_capacitance_typ
;
301 __le16 io_pin_capacitance_typ
;
302 __le16 input_pin_capacitance_typ
;
303 u8 input_pin_capacitance_max
;
304 u8 driver_strength_support
;
310 __le16 vendor_revision
;
316 #define ONFI_CRC_BASE 0x4F4E
318 /* Extended ECC information Block Definition (since ONFI 2.1) */
319 struct onfi_ext_ecc_info
{
323 __le16 block_endurance
;
327 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
328 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
329 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
330 struct onfi_ext_section
{
335 #define ONFI_EXT_SECTION_MAX 8
337 /* Extended Parameter Page Definition (since ONFI 2.1) */
338 struct onfi_ext_param_page
{
340 u8 sig
[4]; /* 'E' 'P' 'P' 'S' */
342 struct onfi_ext_section sections
[ONFI_EXT_SECTION_MAX
];
345 * The actual size of the Extended Parameter Page is in
346 * @ext_param_page_length of nand_onfi_params{}.
347 * The following are the variable length sections.
348 * So we do not add any fields below. Please see the ONFI spec.
352 struct nand_onfi_vendor_micron
{
357 u8 dq_imped_num_settings
;
358 u8 dq_imped_feat_addr
;
359 u8 rb_pulldown_strength
;
360 u8 rb_pulldown_strength_feat_addr
;
361 u8 rb_pulldown_strength_num_settings
;
364 u8 otp_data_prot_addr
;
367 u8 read_retry_options
;
372 struct jedec_ecc_info
{
376 __le16 block_endurance
;
381 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
383 struct nand_jedec_params
{
384 /* rev info and features block */
385 /* 'J' 'E' 'S' 'D' */
391 u8 num_of_param_pages
;
394 /* manufacturer information block */
395 char manufacturer
[12];
400 /* memory organization block */
401 __le32 byte_per_page
;
402 __le16 spare_bytes_per_page
;
404 __le32 pages_per_block
;
405 __le32 blocks_per_lun
;
409 u8 programs_per_page
;
411 u8 multi_plane_op_attr
;
414 /* electrical parameter block */
415 __le16 async_sdr_speed_grade
;
416 __le16 toggle_ddr_speed_grade
;
417 __le16 sync_ddr_speed_grade
;
418 u8 async_sdr_features
;
419 u8 toggle_ddr_features
;
420 u8 sync_ddr_features
;
424 __le16 t_r_multi_plane
;
426 __le16 io_pin_capacitance_typ
;
427 __le16 input_pin_capacitance_typ
;
428 __le16 clk_pin_capacitance_typ
;
429 u8 driver_strength_support
;
433 /* ECC and endurance block */
434 u8 guaranteed_good_blocks
;
435 __le16 guaranteed_block_endurance
;
436 struct jedec_ecc_info ecc_info
[4];
443 __le16 vendor_rev_num
;
446 /* CRC for Parameter Page */
451 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
452 * @lock: protection lock
453 * @active: the mtd device which holds the controller currently
454 * @wq: wait queue to sleep on if a NAND operation is in
455 * progress used instead of the per chip wait queue
456 * when a hw controller is available.
458 struct nand_hw_control
{
460 struct nand_chip
*active
;
461 wait_queue_head_t wq
;
464 static inline void nand_hw_control_init(struct nand_hw_control
*nfc
)
467 spin_lock_init(&nfc
->lock
);
468 init_waitqueue_head(&nfc
->wq
);
472 * struct nand_ecc_ctrl - Control structure for ECC
474 * @algo: ECC algorithm
475 * @steps: number of ECC steps per page
476 * @size: data bytes per ECC step
477 * @bytes: ECC bytes per step
478 * @strength: max number of correctible bits per ECC step
479 * @total: total number of ECC bytes per page
480 * @prepad: padding information for syndrome based ECC generators
481 * @postpad: padding information for syndrome based ECC generators
482 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
483 * @priv: pointer to private ECC control data
484 * @hwctl: function to control hardware ECC generator. Must only
485 * be provided if an hardware ECC is available
486 * @calculate: function for ECC calculation or readback from ECC hardware
487 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
488 * Should return a positive number representing the number of
489 * corrected bitflips, -EBADMSG if the number of bitflips exceed
490 * ECC strength, or any other error code if the error is not
491 * directly related to correction.
492 * If -EBADMSG is returned the input buffers should be left
494 * @read_page_raw: function to read a raw page without ECC. This function
495 * should hide the specific layout used by the ECC
496 * controller and always return contiguous in-band and
497 * out-of-band data even if they're not stored
498 * contiguously on the NAND chip (e.g.
499 * NAND_ECC_HW_SYNDROME interleaves in-band and
501 * @write_page_raw: function to write a raw page without ECC. This function
502 * should hide the specific layout used by the ECC
503 * controller and consider the passed data as contiguous
504 * in-band and out-of-band data. ECC controller is
505 * responsible for doing the appropriate transformations
506 * to adapt to its specific layout (e.g.
507 * NAND_ECC_HW_SYNDROME interleaves in-band and
509 * @read_page: function to read a page according to the ECC generator
510 * requirements; returns maximum number of bitflips corrected in
511 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
512 * @read_subpage: function to read parts of the page covered by ECC;
513 * returns same as read_page()
514 * @write_subpage: function to write parts of the page covered by ECC.
515 * @write_page: function to write a page according to the ECC generator
517 * @write_oob_raw: function to write chip OOB data without ECC
518 * @read_oob_raw: function to read chip OOB data without ECC
519 * @read_oob: function to read chip OOB data
520 * @write_oob: function to write chip OOB data
522 struct nand_ecc_ctrl
{
523 nand_ecc_modes_t mode
;
524 enum nand_ecc_algo algo
;
532 unsigned int options
;
534 void (*hwctl
)(struct mtd_info
*mtd
, int mode
);
535 int (*calculate
)(struct mtd_info
*mtd
, const uint8_t *dat
,
537 int (*correct
)(struct mtd_info
*mtd
, uint8_t *dat
, uint8_t *read_ecc
,
539 int (*read_page_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
540 uint8_t *buf
, int oob_required
, int page
);
541 int (*write_page_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
542 const uint8_t *buf
, int oob_required
, int page
);
543 int (*read_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
544 uint8_t *buf
, int oob_required
, int page
);
545 int (*read_subpage
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
546 uint32_t offs
, uint32_t len
, uint8_t *buf
, int page
);
547 int (*write_subpage
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
548 uint32_t offset
, uint32_t data_len
,
549 const uint8_t *data_buf
, int oob_required
, int page
);
550 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
551 const uint8_t *buf
, int oob_required
, int page
);
552 int (*write_oob_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
554 int (*read_oob_raw
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
556 int (*read_oob
)(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
);
557 int (*write_oob
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
562 * struct nand_buffers - buffer structure for read/write
563 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
564 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
565 * @databuf: buffer pointer for data, size is (page size + oobsize).
567 * Do not change the order of buffers. databuf and oobrbuf must be in
570 struct nand_buffers
{
577 * struct nand_sdr_timings - SDR NAND chip timings
579 * This struct defines the timing requirements of a SDR NAND chip.
580 * These information can be found in every NAND datasheets and the timings
581 * meaning are described in the ONFI specifications:
582 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
585 * All these timings are expressed in picoseconds.
587 * @tALH_min: ALE hold time
588 * @tADL_min: ALE to data loading time
589 * @tALS_min: ALE setup time
590 * @tAR_min: ALE to RE# delay
591 * @tCEA_max: CE# access time
593 * @tCH_min: CE# hold time
594 * @tCHZ_max: CE# high to output hi-Z
595 * @tCLH_min: CLE hold time
596 * @tCLR_min: CLE to RE# delay
597 * @tCLS_min: CLE setup time
598 * @tCOH_min: CE# high to output hold
599 * @tCS_min: CE# setup time
600 * @tDH_min: Data hold time
601 * @tDS_min: Data setup time
602 * @tFEAT_max: Busy time for Set Features and Get Features
603 * @tIR_min: Output hi-Z to RE# low
604 * @tITC_max: Interface and Timing Mode Change time
605 * @tRC_min: RE# cycle time
606 * @tREA_max: RE# access time
607 * @tREH_min: RE# high hold time
608 * @tRHOH_min: RE# high to output hold
609 * @tRHW_min: RE# high to WE# low
610 * @tRHZ_max: RE# high to output hi-Z
611 * @tRLOH_min: RE# low to output hold
612 * @tRP_min: RE# pulse width
613 * @tRR_min: Ready to RE# low (data only)
614 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
615 * rising edge of R/B#.
616 * @tWB_max: WE# high to SR[6] low
617 * @tWC_min: WE# cycle time
618 * @tWH_min: WE# high hold time
619 * @tWHR_min: WE# high to RE# low
620 * @tWP_min: WE# pulse width
621 * @tWW_min: WP# transition to WE# low
623 struct nand_sdr_timings
{
661 * enum nand_data_interface_type - NAND interface timing type
662 * @NAND_SDR_IFACE: Single Data Rate interface
664 enum nand_data_interface_type
{
669 * struct nand_data_interface - NAND interface timing
670 * @type: type of the timing
671 * @timings: The timing, type according to @type
673 struct nand_data_interface
{
674 enum nand_data_interface_type type
;
676 struct nand_sdr_timings sdr
;
681 * nand_get_sdr_timings - get SDR timing from data interface
682 * @conf: The data interface
684 static inline const struct nand_sdr_timings
*
685 nand_get_sdr_timings(const struct nand_data_interface
*conf
)
687 if (conf
->type
!= NAND_SDR_IFACE
)
688 return ERR_PTR(-EINVAL
);
690 return &conf
->timings
.sdr
;
694 * struct nand_chip - NAND Private Flash Chip Data
695 * @mtd: MTD device registered to the MTD framework
696 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
698 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
700 * @read_byte: [REPLACEABLE] read one byte from the chip
701 * @read_word: [REPLACEABLE] read one word from the chip
702 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
704 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
705 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
706 * @select_chip: [REPLACEABLE] select chip nr
707 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
708 * @block_markbad: [REPLACEABLE] mark a block bad
709 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
710 * ALE/CLE/nCE. Also used to write command and address
711 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
712 * device ready/busy line. If set to NULL no access to
713 * ready/busy is available and the ready/busy information
714 * is read from the chip status register.
715 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
716 * commands to the chip.
717 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
719 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
720 * setting the read-retry mode. Mostly needed for MLC NAND.
721 * @ecc: [BOARDSPECIFIC] ECC control structure
722 * @buffers: buffer structure for read/write
723 * @hwcontrol: platform-specific hardware control structure
724 * @erase: [REPLACEABLE] erase function
725 * @scan_bbt: [REPLACEABLE] function to scan bad block table
726 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
727 * data from array to read regs (tR).
728 * @state: [INTERN] the current state of the NAND device
729 * @oob_poi: "poison value buffer," used for laying out OOB data
731 * @page_shift: [INTERN] number of address bits in a page (column
733 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
734 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
735 * @chip_shift: [INTERN] number of address bits in one chip
736 * @options: [BOARDSPECIFIC] various chip options. They can partly
737 * be set to inform nand_scan about special functionality.
738 * See the defines for further explanation.
739 * @bbt_options: [INTERN] bad block specific options. All options used
740 * here must come from bbm.h. By default, these options
741 * will be copied to the appropriate nand_bbt_descr's.
742 * @badblockpos: [INTERN] position of the bad block marker in the oob
744 * @badblockbits: [INTERN] minimum number of set bits in a good block's
745 * bad block marker position; i.e., BBM == 11110111b is
746 * not bad when badblockbits == 7
747 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
748 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
749 * Minimum amount of bit errors per @ecc_step_ds guaranteed
750 * to be correctable. If unknown, set to zero.
751 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
752 * also from the datasheet. It is the recommended ECC step
753 * size, if known; if unknown, set to zero.
754 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
755 * set to the actually used ONFI mode if the chip is
756 * ONFI compliant or deduced from the datasheet if
757 * the NAND chip is not ONFI compliant.
758 * @numchips: [INTERN] number of physical chips
759 * @chipsize: [INTERN] the size of one chip for multichip arrays
760 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
761 * @pagebuf: [INTERN] holds the pagenumber which is currently in
763 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
764 * currently in data_buf.
765 * @subpagesize: [INTERN] holds the subpagesize
766 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
767 * non 0 if ONFI supported.
768 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
769 * non 0 if JEDEC supported.
770 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
771 * supported, 0 otherwise.
772 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
773 * supported, 0 otherwise.
774 * @read_retries: [INTERN] the number of read retry modes supported
775 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
776 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
777 * @setup_data_interface: [OPTIONAL] setup the data interface and timing
778 * @bbt: [INTERN] bad block table pointer
779 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
781 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
782 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
784 * @controller: [REPLACEABLE] a pointer to a hardware controller
785 * structure which is shared among multiple independent
787 * @priv: [OPTIONAL] pointer to private chip data
788 * @errstat: [OPTIONAL] hardware specific function to perform
789 * additional error status checks (determine if errors are
791 * @write_page: [REPLACEABLE] High-level page write function
796 void __iomem
*IO_ADDR_R
;
797 void __iomem
*IO_ADDR_W
;
799 uint8_t (*read_byte
)(struct mtd_info
*mtd
);
800 u16 (*read_word
)(struct mtd_info
*mtd
);
801 void (*write_byte
)(struct mtd_info
*mtd
, uint8_t byte
);
802 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
803 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
804 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
805 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
);
806 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
807 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
);
808 int (*dev_ready
)(struct mtd_info
*mtd
);
809 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
,
811 int(*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this);
812 int (*erase
)(struct mtd_info
*mtd
, int page
);
813 int (*scan_bbt
)(struct mtd_info
*mtd
);
814 int (*errstat
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
,
815 int status
, int page
);
816 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
817 uint32_t offset
, int data_len
, const uint8_t *buf
,
818 int oob_required
, int page
, int cached
, int raw
);
819 int (*onfi_set_features
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
820 int feature_addr
, uint8_t *subfeature_para
);
821 int (*onfi_get_features
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
822 int feature_addr
, uint8_t *subfeature_para
);
823 int (*setup_read_retry
)(struct mtd_info
*mtd
, int retry_mode
);
824 int (*setup_data_interface
)(struct mtd_info
*mtd
,
825 const struct nand_data_interface
*conf
,
830 unsigned int options
;
831 unsigned int bbt_options
;
834 int phys_erase_shift
;
841 unsigned int pagebuf_bitflips
;
843 uint8_t bits_per_cell
;
844 uint16_t ecc_strength_ds
;
845 uint16_t ecc_step_ds
;
846 int onfi_timing_mode_default
;
853 struct nand_onfi_params onfi_params
;
854 struct nand_jedec_params jedec_params
;
857 struct nand_data_interface
*data_interface
;
864 struct nand_hw_control
*controller
;
866 struct nand_ecc_ctrl ecc
;
867 struct nand_buffers
*buffers
;
868 struct nand_hw_control hwcontrol
;
871 struct nand_bbt_descr
*bbt_td
;
872 struct nand_bbt_descr
*bbt_md
;
874 struct nand_bbt_descr
*badblock_pattern
;
879 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops
;
880 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops
;
882 static inline void nand_set_flash_node(struct nand_chip
*chip
,
883 struct device_node
*np
)
885 mtd_set_of_node(&chip
->mtd
, np
);
888 static inline struct device_node
*nand_get_flash_node(struct nand_chip
*chip
)
890 return mtd_get_of_node(&chip
->mtd
);
893 static inline struct nand_chip
*mtd_to_nand(struct mtd_info
*mtd
)
895 return container_of(mtd
, struct nand_chip
, mtd
);
898 static inline struct mtd_info
*nand_to_mtd(struct nand_chip
*chip
)
903 static inline void *nand_get_controller_data(struct nand_chip
*chip
)
908 static inline void nand_set_controller_data(struct nand_chip
*chip
, void *priv
)
914 * NAND Flash Manufacturer ID Codes
916 #define NAND_MFR_TOSHIBA 0x98
917 #define NAND_MFR_ESMT 0xc8
918 #define NAND_MFR_SAMSUNG 0xec
919 #define NAND_MFR_FUJITSU 0x04
920 #define NAND_MFR_NATIONAL 0x8f
921 #define NAND_MFR_RENESAS 0x07
922 #define NAND_MFR_STMICRO 0x20
923 #define NAND_MFR_HYNIX 0xad
924 #define NAND_MFR_MICRON 0x2c
925 #define NAND_MFR_AMD 0x01
926 #define NAND_MFR_MACRONIX 0xc2
927 #define NAND_MFR_EON 0x92
928 #define NAND_MFR_SANDISK 0x45
929 #define NAND_MFR_INTEL 0x89
930 #define NAND_MFR_ATO 0x9b
932 /* The maximum expected count of bytes in the NAND ID sequence */
933 #define NAND_MAX_ID_LEN 8
936 * A helper for defining older NAND chips where the second ID byte fully
937 * defined the chip, including the geometry (chip size, eraseblock size, page
938 * size). All these chips have 512 bytes NAND page size.
940 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
941 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
942 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
945 * A helper for defining newer chips which report their page size and
946 * eraseblock size via the extended ID bytes.
948 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
949 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
950 * device ID now only represented a particular total chip size (and voltage,
951 * buswidth), and the page size, eraseblock size, and OOB size could vary while
952 * using the same device ID.
954 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
955 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
958 #define NAND_ECC_INFO(_strength, _step) \
959 { .strength_ds = (_strength), .step_ds = (_step) }
960 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
961 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
964 * struct nand_flash_dev - NAND Flash Device ID Structure
965 * @name: a human-readable name of the NAND chip
966 * @dev_id: the device ID (the second byte of the full chip ID array)
967 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
968 * memory address as @id[0])
969 * @dev_id: device ID part of the full chip ID array (refers the same memory
971 * @id: full device ID array
972 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
973 * well as the eraseblock size) is determined from the extended NAND
975 * @chipsize: total chip size in MiB
976 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
977 * @options: stores various chip bit options
978 * @id_len: The valid length of the @id.
980 * @ecc: ECC correctability and step information from the datasheet.
981 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
982 * @ecc_strength_ds in nand_chip{}.
983 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
984 * @ecc_step_ds in nand_chip{}, also from the datasheet.
985 * For example, the "4bit ECC for each 512Byte" can be set with
986 * NAND_ECC_INFO(4, 512).
987 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
988 * reset. Should be deduced from timings described
992 struct nand_flash_dev
{
999 uint8_t id
[NAND_MAX_ID_LEN
];
1001 unsigned int pagesize
;
1002 unsigned int chipsize
;
1003 unsigned int erasesize
;
1004 unsigned int options
;
1008 uint16_t strength_ds
;
1011 int onfi_timing_mode_default
;
1015 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1016 * @name: Manufacturer name
1017 * @id: manufacturer ID code of device.
1019 struct nand_manufacturers
{
1024 extern struct nand_flash_dev nand_flash_ids
[];
1025 extern struct nand_manufacturers nand_manuf_ids
[];
1027 int nand_default_bbt(struct mtd_info
*mtd
);
1028 int nand_markbad_bbt(struct mtd_info
*mtd
, loff_t offs
);
1029 int nand_isreserved_bbt(struct mtd_info
*mtd
, loff_t offs
);
1030 int nand_isbad_bbt(struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
1031 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
1033 int nand_do_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1034 size_t *retlen
, uint8_t *buf
);
1037 * struct platform_nand_chip - chip level device structure
1038 * @nr_chips: max. number of chips to scan for
1039 * @chip_offset: chip number offset
1040 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1041 * @partitions: mtd partition list
1042 * @chip_delay: R/B delay value in us
1043 * @options: Option flags, e.g. 16bit buswidth
1044 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1045 * @part_probe_types: NULL-terminated array of probe types
1047 struct platform_nand_chip
{
1051 struct mtd_partition
*partitions
;
1053 unsigned int options
;
1054 unsigned int bbt_options
;
1055 const char **part_probe_types
;
1058 /* Keep gcc happy */
1059 struct platform_device
;
1062 * struct platform_nand_ctrl - controller level device structure
1063 * @probe: platform specific function to probe/setup hardware
1064 * @remove: platform specific function to remove/teardown hardware
1065 * @hwcontrol: platform specific hardware control structure
1066 * @dev_ready: platform specific function to read ready/busy pin
1067 * @select_chip: platform specific chip select function
1068 * @cmd_ctrl: platform specific function for controlling
1069 * ALE/CLE/nCE. Also used to write command and address
1070 * @write_buf: platform specific function for write buffer
1071 * @read_buf: platform specific function for read buffer
1072 * @read_byte: platform specific function to read one byte from chip
1073 * @priv: private data to transport driver specific settings
1075 * All fields are optional and depend on the hardware driver requirements
1077 struct platform_nand_ctrl
{
1078 int (*probe
)(struct platform_device
*pdev
);
1079 void (*remove
)(struct platform_device
*pdev
);
1080 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
1081 int (*dev_ready
)(struct mtd_info
*mtd
);
1082 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
1083 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
);
1084 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
1085 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
1086 unsigned char (*read_byte
)(struct mtd_info
*mtd
);
1091 * struct platform_nand_data - container structure for platform-specific data
1092 * @chip: chip level chip structure
1093 * @ctrl: controller level device structure
1095 struct platform_nand_data
{
1096 struct platform_nand_chip chip
;
1097 struct platform_nand_ctrl ctrl
;
1100 /* return the supported features. */
1101 static inline int onfi_feature(struct nand_chip
*chip
)
1103 return chip
->onfi_version
? le16_to_cpu(chip
->onfi_params
.features
) : 0;
1106 /* return the supported asynchronous timing mode. */
1107 static inline int onfi_get_async_timing_mode(struct nand_chip
*chip
)
1109 if (!chip
->onfi_version
)
1110 return ONFI_TIMING_MODE_UNKNOWN
;
1111 return le16_to_cpu(chip
->onfi_params
.async_timing_mode
);
1114 /* return the supported synchronous timing mode. */
1115 static inline int onfi_get_sync_timing_mode(struct nand_chip
*chip
)
1117 if (!chip
->onfi_version
)
1118 return ONFI_TIMING_MODE_UNKNOWN
;
1119 return le16_to_cpu(chip
->onfi_params
.src_sync_timing_mode
);
1122 int onfi_init_data_interface(struct nand_chip
*chip
,
1123 struct nand_data_interface
*iface
,
1124 enum nand_data_interface_type type
,
1128 * Check if it is a SLC nand.
1129 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1130 * We do not distinguish the MLC and TLC now.
1132 static inline bool nand_is_slc(struct nand_chip
*chip
)
1134 return chip
->bits_per_cell
== 1;
1138 * Check if the opcode's address should be sent only on the lower 8 bits
1139 * @command: opcode to check
1141 static inline int nand_opcode_8bits(unsigned int command
)
1144 case NAND_CMD_READID
:
1145 case NAND_CMD_PARAM
:
1146 case NAND_CMD_GET_FEATURES
:
1147 case NAND_CMD_SET_FEATURES
:
1155 /* return the supported JEDEC features. */
1156 static inline int jedec_feature(struct nand_chip
*chip
)
1158 return chip
->jedec_version
? le16_to_cpu(chip
->jedec_params
.features
)
1162 /* get timing characteristics from ONFI timing mode. */
1163 const struct nand_sdr_timings
*onfi_async_timing_mode_to_sdr_timings(int mode
);
1164 /* get data interface from ONFI timing mode 0, used after reset. */
1165 const struct nand_data_interface
*nand_get_default_data_interface(void);
1167 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1168 void *ecc
, int ecclen
,
1169 void *extraoob
, int extraooblen
,
1172 /* Default write_oob implementation */
1173 int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
);
1175 /* Default write_oob syndrome implementation */
1176 int nand_write_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1179 /* Default read_oob implementation */
1180 int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
);
1182 /* Default read_oob syndrome implementation */
1183 int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1186 /* Reset and initialize a NAND device */
1187 int nand_reset(struct nand_chip
*chip
);
1189 /* Free resources held by the NAND device */
1190 void nand_cleanup(struct nand_chip
*chip
);
1192 #endif /* __LINUX_MTD_NAND_H */