include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
   5  *                     Steven J. Hill <sjhill@realitydiluted.com>
   6  *                     Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Info:
  13  *      Contains standard defines and IDs for NAND flash devices
  14  *
  15  * Changelog:
  16  *      See git changelog.
  17  */
  18 #ifndef __LINUX_MTD_NAND_H
  19 #define __LINUX_MTD_NAND_H
  20
  21 #include <linux/wait.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/flashchip.h>
  25 #include <linux/mtd/bbm.h>
  26
  27 struct mtd_info;
  28 struct nand_flash_dev;
  29 /* Scan and identify a NAND device */
  30 extern int nand_scan (struct mtd_info *mtd, int max_chips);
  31 /* Separate phases of nand_scan(), allowing board driver to intervene
  32  * and override command or ECC setup according to flash type */
  33 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  34                            struct nand_flash_dev *table);
  35 extern int nand_scan_tail(struct mtd_info *mtd);
  36
  37 /* Free resources held by the NAND device */
  38 extern void nand_release (struct mtd_info *mtd);
  39
  40 /* Internal helper for board drivers which need to override command function */
  41 extern void nand_wait_ready(struct mtd_info *mtd);
  42
  43 /* locks all blockes present in the device */
  44 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  45
  46 /* unlocks specified locked blockes */
  47 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  48
  49 /* The maximum number of NAND chips in an array */
  50 #define NAND_MAX_CHIPS          8
  51
  52 /* This constant declares the max. oobsize / page, which
  53  * is supported now. If you add a chip with bigger oobsize/page
  54  * adjust this accordingly.
  55  */
  56 #define NAND_MAX_OOBSIZE        256
  57 #define NAND_MAX_PAGESIZE       4096
  58
  59 /*
  60  * Constants for hardware specific CLE/ALE/NCE function
  61  *
  62  * These are bits which can be or'ed to set/clear multiple
  63  * bits in one go.
  64  */
  65 /* Select the chip by setting nCE to low */
  66 #define NAND_NCE                0x01
  67 /* Select the command latch by setting CLE to high */
  68 #define NAND_CLE                0x02
  69 /* Select the address latch by setting ALE to high */
  70 #define NAND_ALE                0x04
  71
  72 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  73 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  74 #define NAND_CTRL_CHANGE        0x80
  75
  76 /*
  77  * Standard NAND flash commands
  78  */
  79 #define NAND_CMD_READ0          0
  80 #define NAND_CMD_READ1          1
  81 #define NAND_CMD_RNDOUT         5
  82 #define NAND_CMD_PAGEPROG       0x10
  83 #define NAND_CMD_READOOB        0x50
  84 #define NAND_CMD_ERASE1         0x60
  85 #define NAND_CMD_STATUS         0x70
  86 #define NAND_CMD_STATUS_MULTI   0x71
  87 #define NAND_CMD_SEQIN          0x80
  88 #define NAND_CMD_RNDIN          0x85
  89 #define NAND_CMD_READID         0x90
  90 #define NAND_CMD_ERASE2         0xd0
  91 #define NAND_CMD_RESET          0xff
  92
  93 #define NAND_CMD_LOCK           0x2a
  94 #define NAND_CMD_UNLOCK1        0x23
  95 #define NAND_CMD_UNLOCK2        0x24
  96
  97 /* Extended commands for large page devices */
  98 #define NAND_CMD_READSTART      0x30
  99 #define NAND_CMD_RNDOUTSTART    0xE0
 100 #define NAND_CMD_CACHEDPROG     0x15
 101
 102 /* Extended commands for AG-AND device */
 103 /*
 104  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
 105  *       there is no way to distinguish that from NAND_CMD_READ0
 106  *       until the remaining sequence of commands has been completed
 107  *       so add a high order bit and mask it off in the command.
 108  */
 109 #define NAND_CMD_DEPLETE1       0x100
 110 #define NAND_CMD_DEPLETE2       0x38
 111 #define NAND_CMD_STATUS_MULTI   0x71
 112 #define NAND_CMD_STATUS_ERROR   0x72
 113 /* multi-bank error status (banks 0-3) */
 114 #define NAND_CMD_STATUS_ERROR0  0x73
 115 #define NAND_CMD_STATUS_ERROR1  0x74
 116 #define NAND_CMD_STATUS_ERROR2  0x75
 117 #define NAND_CMD_STATUS_ERROR3  0x76
 118 #define NAND_CMD_STATUS_RESET   0x7f
 119 #define NAND_CMD_STATUS_CLEAR   0xff
 120
 121 #define NAND_CMD_NONE           -1
 122
 123 /* Status bits */
 124 #define NAND_STATUS_FAIL        0x01
 125 #define NAND_STATUS_FAIL_N1     0x02
 126 #define NAND_STATUS_TRUE_READY  0x20
 127 #define NAND_STATUS_READY       0x40
 128 #define NAND_STATUS_WP          0x80
 129
 130 /*
 131  * Constants for ECC_MODES
 132  */
 133 typedef enum {
 134         NAND_ECC_NONE,
 135         NAND_ECC_SOFT,
 136         NAND_ECC_HW,
 137         NAND_ECC_HW_SYNDROME,
 138         NAND_ECC_HW_OOB_FIRST,
 139 } nand_ecc_modes_t;
 140
 141 /*
 142  * Constants for Hardware ECC
 143  */
 144 /* Reset Hardware ECC for read */
 145 #define NAND_ECC_READ           0
 146 /* Reset Hardware ECC for write */
 147 #define NAND_ECC_WRITE          1
 148 /* Enable Hardware ECC before syndrom is read back from flash */
 149 #define NAND_ECC_READSYN        2
 150
 151 /* Bit mask for flags passed to do_nand_read_ecc */
 152 #define NAND_GET_DEVICE         0x80
 153
 154
 155 /* Option constants for bizarre disfunctionality and real
 156 *  features
 157 */
 158 /* Chip can not auto increment pages */
 159 #define NAND_NO_AUTOINCR        0x00000001
 160 /* Buswitdh is 16 bit */
 161 #define NAND_BUSWIDTH_16        0x00000002
 162 /* Device supports partial programming without padding */
 163 #define NAND_NO_PADDING         0x00000004
 164 /* Chip has cache program function */
 165 #define NAND_CACHEPRG           0x00000008
 166 /* Chip has copy back function */
 167 #define NAND_COPYBACK           0x00000010
 168 /* AND Chip which has 4 banks and a confusing page / block
 169  * assignment. See Renesas datasheet for further information */
 170 #define NAND_IS_AND             0x00000020
 171 /* Chip has a array of 4 pages which can be read without
 172  * additional ready /busy waits */
 173 #define NAND_4PAGE_ARRAY        0x00000040
 174 /* Chip requires that BBT is periodically rewritten to prevent
 175  * bits from adjacent blocks from 'leaking' in altering data.
 176  * This happens with the Renesas AG-AND chips, possibly others.  */
 177 #define BBT_AUTO_REFRESH        0x00000080
 178 /* Chip does not require ready check on read. True
 179  * for all large page devices, as they do not support
 180  * autoincrement.*/
 181 #define NAND_NO_READRDY         0x00000100
 182 /* Chip does not allow subpage writes */
 183 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 184 /* Chip stores bad block marker on the last page of the eraseblock */
 185 #define NAND_BB_LAST_PAGE       0x00000400
 186
 187 /* Device is one of 'new' xD cards that expose fake nand command set */
 188 #define NAND_BROKEN_XD          0x00000400
 189
 190 /* Device behaves just like nand, but is readonly */
 191 #define NAND_ROM                0x00000800
 192
 193 /* Options valid for Samsung large page devices */
 194 #define NAND_SAMSUNG_LP_OPTIONS \
 195         (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 196
 197 /* Macros to identify the above */
 198 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
 199 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 200 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 201 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 202 /* Large page NAND with SOFT_ECC should support subpage reads */
 203 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
 204                                         && (chip->page_shift > 9))
 205
 206 /* Mask to zero out the chip options, which come from the id table */
 207 #define NAND_CHIPOPTIONS_MSK    (0x0000ffff & ~NAND_NO_AUTOINCR)
 208
 209 /* Non chip related options */
 210 /* Use a flash based bad block table. This option is passed to the
 211  * default bad block table function. */
 212 #define NAND_USE_FLASH_BBT      0x00010000
 213 /* This option skips the bbt scan during initialization. */
 214 #define NAND_SKIP_BBTSCAN       0x00020000
 215 /* This option is defined if the board driver allocates its own buffers
 216    (e.g. because it needs them DMA-coherent */
 217 #define NAND_OWN_BUFFERS        0x00040000
 218 /* Chip may not exist, so silence any errors in scan */
 219 #define NAND_SCAN_SILENT_NODEV  0x00080000
 220
 221 /* Options set by nand scan */
 222 /* Nand scan has allocated controller struct */
 223 #define NAND_CONTROLLER_ALLOC   0x80000000
 224
 225 /* Cell info constants */
 226 #define NAND_CI_CHIPNR_MSK      0x03
 227 #define NAND_CI_CELLTYPE_MSK    0x0C
 228
 229 /* Keep gcc happy */
 230 struct nand_chip;
 231
 232 /**
 233  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 234  * @lock:               protection lock
 235  * @active:             the mtd device which holds the controller currently
 236  * @wq:                 wait queue to sleep on if a NAND operation is in progress
 237  *                      used instead of the per chip wait queue when a hw controller is available
 238  */
 239 struct nand_hw_control {
 240         spinlock_t       lock;
 241         struct nand_chip *active;
 242         wait_queue_head_t wq;
 243 };
 244
 245 /**
 246  * struct nand_ecc_ctrl - Control structure for ecc
 247  * @mode:       ecc mode
 248  * @steps:      number of ecc steps per page
 249  * @size:       data bytes per ecc step
 250  * @bytes:      ecc bytes per step
 251  * @total:      total number of ecc bytes per page
 252  * @prepad:     padding information for syndrome based ecc generators
 253  * @postpad:    padding information for syndrome based ecc generators
 254  * @layout:     ECC layout control struct pointer
 255  * @hwctl:      function to control hardware ecc generator. Must only
 256  *              be provided if an hardware ECC is available
 257  * @calculate:  function for ecc calculation or readback from ecc hardware
 258  * @correct:    function for ecc correction, matching to ecc generator (sw/hw)
 259  * @read_page_raw:      function to read a raw page without ECC
 260  * @write_page_raw:     function to write a raw page without ECC
 261  * @read_page:  function to read a page according to the ecc generator requirements
 262  * @read_subpage:       function to read parts of the page covered by ECC.
 263  * @write_page: function to write a page according to the ecc generator requirements
 264  * @read_oob:   function to read chip OOB data
 265  * @write_oob:  function to write chip OOB data
 266  */
 267 struct nand_ecc_ctrl {
 268         nand_ecc_modes_t        mode;
 269         int                     steps;
 270         int                     size;
 271         int                     bytes;
 272         int                     total;
 273         int                     prepad;
 274         int                     postpad;
 275         struct nand_ecclayout   *layout;
 276         void                    (*hwctl)(struct mtd_info *mtd, int mode);
 277         int                     (*calculate)(struct mtd_info *mtd,
 278                                              const uint8_t *dat,
 279                                              uint8_t *ecc_code);
 280         int                     (*correct)(struct mtd_info *mtd, uint8_t *dat,
 281                                            uint8_t *read_ecc,
 282                                            uint8_t *calc_ecc);
 283         int                     (*read_page_raw)(struct mtd_info *mtd,
 284                                                  struct nand_chip *chip,
 285                                                  uint8_t *buf, int page);
 286         void                    (*write_page_raw)(struct mtd_info *mtd,
 287                                                   struct nand_chip *chip,
 288                                                   const uint8_t *buf);
 289         int                     (*read_page)(struct mtd_info *mtd,
 290                                              struct nand_chip *chip,
 291                                              uint8_t *buf, int page);
 292         int                     (*read_subpage)(struct mtd_info *mtd,
 293                                              struct nand_chip *chip,
 294                                              uint32_t offs, uint32_t len,
 295                                              uint8_t *buf);
 296         void                    (*write_page)(struct mtd_info *mtd,
 297                                               struct nand_chip *chip,
 298                                               const uint8_t *buf);
 299         int                     (*read_oob)(struct mtd_info *mtd,
 300                                             struct nand_chip *chip,
 301                                             int page,
 302                                             int sndcmd);
 303         int                     (*write_oob)(struct mtd_info *mtd,
 304                                              struct nand_chip *chip,
 305                                              int page);
 306 };
 307
 308 /**
 309  * struct nand_buffers - buffer structure for read/write
 310  * @ecccalc:    buffer for calculated ecc
 311  * @ecccode:    buffer for ecc read from flash
 312  * @databuf:    buffer for data - dynamically sized
 313  *
 314  * Do not change the order of buffers. databuf and oobrbuf must be in
 315  * consecutive order.
 316  */
 317 struct nand_buffers {
 318         uint8_t ecccalc[NAND_MAX_OOBSIZE];
 319         uint8_t ecccode[NAND_MAX_OOBSIZE];
 320         uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 321 };
 322
 323 /**
 324  * struct nand_chip - NAND Private Flash Chip Data
 325  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
 326  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
 327  * @read_byte:          [REPLACEABLE] read one byte from the chip
 328  * @read_word:          [REPLACEABLE] read one word from the chip
 329  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 330  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 331  * @verify_buf:         [REPLACEABLE] verify buffer contents against the chip data
 332  * @select_chip:        [REPLACEABLE] select chip nr
 333  * @block_bad:          [REPLACEABLE] check, if the block is bad
 334  * @block_markbad:      [REPLACEABLE] mark the block bad
 335  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific funtion for controlling
 336  *                      ALE/CLE/nCE. Also used to write command and address
 337  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
 338  *                      If set to NULL no access to ready/busy is available and the ready/busy information
 339  *                      is read from the chip status register
 340  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing commands to the chip
 341  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on ready
 342  * @ecc:                [BOARDSPECIFIC] ecc control ctructure
 343  * @buffers:            buffer structure for read/write
 344  * @hwcontrol:          platform-specific hardware control structure
 345  * @ops:                oob operation operands
 346  * @erase_cmd:          [INTERN] erase command write function, selectable due to AND support
 347  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 348  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
 349  * @state:              [INTERN] the current state of the NAND device
 350  * @oob_poi:            poison value buffer
 351  * @page_shift:         [INTERN] number of address bits in a page (column address bits)
 352  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 353  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 354  * @chip_shift:         [INTERN] number of address bits in one chip
 355  * @options:            [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
 356  *                      special functionality. See the defines for further explanation
 357  * @badblockpos:        [INTERN] position of the bad block marker in the oob area
 358  * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 359  * @numchips:           [INTERN] number of physical chips
 360  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 361  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 362  * @pagebuf:            [INTERN] holds the pagenumber which is currently in data_buf
 363  * @subpagesize:        [INTERN] holds the subpagesize
 364  * @ecclayout:          [REPLACEABLE] the default ecc placement scheme
 365  * @bbt:                [INTERN] bad block table pointer
 366  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash lookup
 367  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 368  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial bad block scan
 369  * @controller:         [REPLACEABLE] a pointer to a hardware controller structure
 370  *                      which is shared among multiple independend devices
 371  * @priv:               [OPTIONAL] pointer to private chip date
 372  * @errstat:            [OPTIONAL] hardware specific function to perform additional error status checks
 373  *                      (determine if errors are correctable)
 374  * @write_page:         [REPLACEABLE] High-level page write function
 375  */
 376
 377 struct nand_chip {
 378         void  __iomem   *IO_ADDR_R;
 379         void  __iomem   *IO_ADDR_W;
 380
 381         uint8_t         (*read_byte)(struct mtd_info *mtd);
 382         u16             (*read_word)(struct mtd_info *mtd);
 383         void            (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 384         void            (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 385         int             (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 386         void            (*select_chip)(struct mtd_info *mtd, int chip);
 387         int             (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 388         int             (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 389         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 390                                     unsigned int ctrl);
 391         int             (*dev_ready)(struct mtd_info *mtd);
 392         void            (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
 393         int             (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 394         void            (*erase_cmd)(struct mtd_info *mtd, int page);
 395         int             (*scan_bbt)(struct mtd_info *mtd);
 396         int             (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
 397         int             (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 398                                       const uint8_t *buf, int page, int cached, int raw);
 399
 400         int             chip_delay;
 401         unsigned int    options;
 402
 403         int             page_shift;
 404         int             phys_erase_shift;
 405         int             bbt_erase_shift;
 406         int             chip_shift;
 407         int             numchips;
 408         uint64_t        chipsize;
 409         int             pagemask;
 410         int             pagebuf;
 411         int             subpagesize;
 412         uint8_t         cellinfo;
 413         int             badblockpos;
 414         int             badblockbits;
 415
 416         flstate_t       state;
 417
 418         uint8_t         *oob_poi;
 419         struct nand_hw_control  *controller;
 420         struct nand_ecclayout   *ecclayout;
 421
 422         struct nand_ecc_ctrl ecc;
 423         struct nand_buffers *buffers;
 424         struct nand_hw_control hwcontrol;
 425
 426         struct mtd_oob_ops ops;
 427
 428         uint8_t         *bbt;
 429         struct nand_bbt_descr   *bbt_td;
 430         struct nand_bbt_descr   *bbt_md;
 431
 432         struct nand_bbt_descr   *badblock_pattern;
 433
 434         void            *priv;
 435 };
 436
 437 /*
 438  * NAND Flash Manufacturer ID Codes
 439  */
 440 #define NAND_MFR_TOSHIBA        0x98
 441 #define NAND_MFR_SAMSUNG        0xec
 442 #define NAND_MFR_FUJITSU        0x04
 443 #define NAND_MFR_NATIONAL       0x8f
 444 #define NAND_MFR_RENESAS        0x07
 445 #define NAND_MFR_STMICRO        0x20
 446 #define NAND_MFR_HYNIX          0xad
 447 #define NAND_MFR_MICRON         0x2c
 448 #define NAND_MFR_AMD            0x01
 449
 450 /**
 451  * struct nand_flash_dev - NAND Flash Device ID Structure
 452  * @name:       Identify the device type
 453  * @id:         device ID code
 454  * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 455  *              If the pagesize is 0, then the real pagesize
 456  *              and the eraseize are determined from the
 457  *              extended id bytes in the chip
 458  * @erasesize:  Size of an erase block in the flash device.
 459  * @chipsize:   Total chipsize in Mega Bytes
 460  * @options:    Bitfield to store chip relevant options
 461  */
 462 struct nand_flash_dev {
 463         char *name;
 464         int id;
 465         unsigned long pagesize;
 466         unsigned long chipsize;
 467         unsigned long erasesize;
 468         unsigned long options;
 469 };
 470
 471 /**
 472  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 473  * @name:       Manufacturer name
 474  * @id:         manufacturer ID code of device.
 475 */
 476 struct nand_manufacturers {
 477         int id;
 478         char * name;
 479 };
 480
 481 extern struct nand_flash_dev nand_flash_ids[];
 482 extern struct nand_manufacturers nand_manuf_ids[];
 483
 484 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 485 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 486 extern int nand_default_bbt(struct mtd_info *mtd);
 487 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 488 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 489                            int allowbbt);
 490 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 491                         size_t * retlen, uint8_t * buf);
 492
 493 /**
 494  * struct platform_nand_chip - chip level device structure
 495  * @nr_chips:           max. number of chips to scan for
 496  * @chip_offset:        chip number offset
 497  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 498  * @partitions:         mtd partition list
 499  * @chip_delay:         R/B delay value in us
 500  * @options:            Option flags, e.g. 16bit buswidth
 501  * @ecclayout:          ecc layout info structure
 502  * @part_probe_types:   NULL-terminated array of probe types
 503  * @set_parts:          platform specific function to set partitions
 504  * @priv:               hardware controller specific settings
 505  */
 506 struct platform_nand_chip {
 507         int                     nr_chips;
 508         int                     chip_offset;
 509         int                     nr_partitions;
 510         struct mtd_partition    *partitions;
 511         struct nand_ecclayout   *ecclayout;
 512         int                     chip_delay;
 513         unsigned int            options;
 514         const char              **part_probe_types;
 515         void                    (*set_parts)(uint64_t size,
 516                                         struct platform_nand_chip *chip);
 517         void                    *priv;
 518 };
 519
 520 /* Keep gcc happy */
 521 struct platform_device;
 522
 523 /**
 524  * struct platform_nand_ctrl - controller level device structure
 525  * @probe:              platform specific function to probe/setup hardware
 526  * @remove:             platform specific function to remove/teardown hardware
 527  * @hwcontrol:          platform specific hardware control structure
 528  * @dev_ready:          platform specific function to read ready/busy pin
 529  * @select_chip:        platform specific chip select function
 530  * @cmd_ctrl:           platform specific function for controlling
 531  *                      ALE/CLE/nCE. Also used to write command and address
 532  * @write_buf:          platform specific function for write buffer
 533  * @read_buf:           platform specific function for read buffer
 534  * @priv:               private data to transport driver specific settings
 535  *
 536  * All fields are optional and depend on the hardware driver requirements
 537  */
 538 struct platform_nand_ctrl {
 539         int             (*probe)(struct platform_device *pdev);
 540         void            (*remove)(struct platform_device *pdev);
 541         void            (*hwcontrol)(struct mtd_info *mtd, int cmd);
 542         int             (*dev_ready)(struct mtd_info *mtd);
 543         void            (*select_chip)(struct mtd_info *mtd, int chip);
 544         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 545                                     unsigned int ctrl);
 546         void            (*write_buf)(struct mtd_info *mtd,
 547                                     const uint8_t *buf, int len);
 548         void            (*read_buf)(struct mtd_info *mtd,
 549                                     uint8_t *buf, int len);
 550         void            *priv;
 551 };
 552
 553 /**
 554  * struct platform_nand_data - container structure for platform-specific data
 555  * @chip:               chip level chip structure
 556  * @ctrl:               controller level device structure
 557  */
 558 struct platform_nand_data {
 559         struct platform_nand_chip       chip;
 560         struct platform_nand_ctrl       ctrl;
 561 };
 562
 563 /* Some helpers to access the data structures */
 564 static inline
 565 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 566 {
 567         struct nand_chip *chip = mtd->priv;
 568
 569         return chip->priv;
 570 }
 571
 572 #endif /* __LINUX_MTD_NAND_H */