2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev
;
29 /* Scan and identify a NAND device */
30 extern int nand_scan (struct mtd_info
*mtd
, int max_chips
);
31 /* Separate phases of nand_scan(), allowing board driver to intervene
32 * and override command or ECC setup according to flash type */
33 extern int nand_scan_ident(struct mtd_info
*mtd
, int max_chips
,
34 struct nand_flash_dev
*table
);
35 extern int nand_scan_tail(struct mtd_info
*mtd
);
37 /* Free resources held by the NAND device */
38 extern void nand_release (struct mtd_info
*mtd
);
40 /* Internal helper for board drivers which need to override command function */
41 extern void nand_wait_ready(struct mtd_info
*mtd
);
43 /* locks all blockes present in the device */
44 extern int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
46 /* unlocks specified locked blockes */
47 extern int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
49 /* The maximum number of NAND chips in an array */
50 #define NAND_MAX_CHIPS 8
52 /* This constant declares the max. oobsize / page, which
53 * is supported now. If you add a chip with bigger oobsize/page
54 * adjust this accordingly.
56 #define NAND_MAX_OOBSIZE 256
57 #define NAND_MAX_PAGESIZE 4096
60 * Constants for hardware specific CLE/ALE/NCE function
62 * These are bits which can be or'ed to set/clear multiple
65 /* Select the chip by setting nCE to low */
67 /* Select the command latch by setting CLE to high */
69 /* Select the address latch by setting ALE to high */
72 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
73 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
74 #define NAND_CTRL_CHANGE 0x80
77 * Standard NAND flash commands
79 #define NAND_CMD_READ0 0
80 #define NAND_CMD_READ1 1
81 #define NAND_CMD_RNDOUT 5
82 #define NAND_CMD_PAGEPROG 0x10
83 #define NAND_CMD_READOOB 0x50
84 #define NAND_CMD_ERASE1 0x60
85 #define NAND_CMD_STATUS 0x70
86 #define NAND_CMD_STATUS_MULTI 0x71
87 #define NAND_CMD_SEQIN 0x80
88 #define NAND_CMD_RNDIN 0x85
89 #define NAND_CMD_READID 0x90
90 #define NAND_CMD_ERASE2 0xd0
91 #define NAND_CMD_RESET 0xff
93 #define NAND_CMD_LOCK 0x2a
94 #define NAND_CMD_UNLOCK1 0x23
95 #define NAND_CMD_UNLOCK2 0x24
97 /* Extended commands for large page devices */
98 #define NAND_CMD_READSTART 0x30
99 #define NAND_CMD_RNDOUTSTART 0xE0
100 #define NAND_CMD_CACHEDPROG 0x15
102 /* Extended commands for AG-AND device */
104 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
105 * there is no way to distinguish that from NAND_CMD_READ0
106 * until the remaining sequence of commands has been completed
107 * so add a high order bit and mask it off in the command.
109 #define NAND_CMD_DEPLETE1 0x100
110 #define NAND_CMD_DEPLETE2 0x38
111 #define NAND_CMD_STATUS_MULTI 0x71
112 #define NAND_CMD_STATUS_ERROR 0x72
113 /* multi-bank error status (banks 0-3) */
114 #define NAND_CMD_STATUS_ERROR0 0x73
115 #define NAND_CMD_STATUS_ERROR1 0x74
116 #define NAND_CMD_STATUS_ERROR2 0x75
117 #define NAND_CMD_STATUS_ERROR3 0x76
118 #define NAND_CMD_STATUS_RESET 0x7f
119 #define NAND_CMD_STATUS_CLEAR 0xff
121 #define NAND_CMD_NONE -1
124 #define NAND_STATUS_FAIL 0x01
125 #define NAND_STATUS_FAIL_N1 0x02
126 #define NAND_STATUS_TRUE_READY 0x20
127 #define NAND_STATUS_READY 0x40
128 #define NAND_STATUS_WP 0x80
131 * Constants for ECC_MODES
137 NAND_ECC_HW_SYNDROME
,
138 NAND_ECC_HW_OOB_FIRST
,
142 * Constants for Hardware ECC
144 /* Reset Hardware ECC for read */
145 #define NAND_ECC_READ 0
146 /* Reset Hardware ECC for write */
147 #define NAND_ECC_WRITE 1
148 /* Enable Hardware ECC before syndrom is read back from flash */
149 #define NAND_ECC_READSYN 2
151 /* Bit mask for flags passed to do_nand_read_ecc */
152 #define NAND_GET_DEVICE 0x80
155 /* Option constants for bizarre disfunctionality and real
158 /* Chip can not auto increment pages */
159 #define NAND_NO_AUTOINCR 0x00000001
160 /* Buswitdh is 16 bit */
161 #define NAND_BUSWIDTH_16 0x00000002
162 /* Device supports partial programming without padding */
163 #define NAND_NO_PADDING 0x00000004
164 /* Chip has cache program function */
165 #define NAND_CACHEPRG 0x00000008
166 /* Chip has copy back function */
167 #define NAND_COPYBACK 0x00000010
168 /* AND Chip which has 4 banks and a confusing page / block
169 * assignment. See Renesas datasheet for further information */
170 #define NAND_IS_AND 0x00000020
171 /* Chip has a array of 4 pages which can be read without
172 * additional ready /busy waits */
173 #define NAND_4PAGE_ARRAY 0x00000040
174 /* Chip requires that BBT is periodically rewritten to prevent
175 * bits from adjacent blocks from 'leaking' in altering data.
176 * This happens with the Renesas AG-AND chips, possibly others. */
177 #define BBT_AUTO_REFRESH 0x00000080
178 /* Chip does not require ready check on read. True
179 * for all large page devices, as they do not support
181 #define NAND_NO_READRDY 0x00000100
182 /* Chip does not allow subpage writes */
183 #define NAND_NO_SUBPAGE_WRITE 0x00000200
185 /* Device is one of 'new' xD cards that expose fake nand command set */
186 #define NAND_BROKEN_XD 0x00000400
188 /* Device behaves just like nand, but is readonly */
189 #define NAND_ROM 0x00000800
191 /* Options valid for Samsung large page devices */
192 #define NAND_SAMSUNG_LP_OPTIONS \
193 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
195 /* Macros to identify the above */
196 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
197 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
198 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
199 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
200 /* Large page NAND with SOFT_ECC should support subpage reads */
201 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
202 && (chip->page_shift > 9))
204 /* Mask to zero out the chip options, which come from the id table */
205 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
207 /* Non chip related options */
208 /* Use a flash based bad block table. This option is passed to the
209 * default bad block table function. */
210 #define NAND_USE_FLASH_BBT 0x00010000
211 /* This option skips the bbt scan during initialization. */
212 #define NAND_SKIP_BBTSCAN 0x00020000
213 /* This option is defined if the board driver allocates its own buffers
214 (e.g. because it needs them DMA-coherent */
215 #define NAND_OWN_BUFFERS 0x00040000
216 /* Chip may not exist, so silence any errors in scan */
217 #define NAND_SCAN_SILENT_NODEV 0x00080000
219 /* Options set by nand scan */
220 /* Nand scan has allocated controller struct */
221 #define NAND_CONTROLLER_ALLOC 0x80000000
223 /* Cell info constants */
224 #define NAND_CI_CHIPNR_MSK 0x03
225 #define NAND_CI_CELLTYPE_MSK 0x0C
231 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
232 * @lock: protection lock
233 * @active: the mtd device which holds the controller currently
234 * @wq: wait queue to sleep on if a NAND operation is in progress
235 * used instead of the per chip wait queue when a hw controller is available
237 struct nand_hw_control
{
239 struct nand_chip
*active
;
240 wait_queue_head_t wq
;
244 * struct nand_ecc_ctrl - Control structure for ecc
246 * @steps: number of ecc steps per page
247 * @size: data bytes per ecc step
248 * @bytes: ecc bytes per step
249 * @total: total number of ecc bytes per page
250 * @prepad: padding information for syndrome based ecc generators
251 * @postpad: padding information for syndrome based ecc generators
252 * @layout: ECC layout control struct pointer
253 * @hwctl: function to control hardware ecc generator. Must only
254 * be provided if an hardware ECC is available
255 * @calculate: function for ecc calculation or readback from ecc hardware
256 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
257 * @read_page_raw: function to read a raw page without ECC
258 * @write_page_raw: function to write a raw page without ECC
259 * @read_page: function to read a page according to the ecc generator requirements
260 * @read_subpage: function to read parts of the page covered by ECC.
261 * @write_page: function to write a page according to the ecc generator requirements
262 * @read_oob: function to read chip OOB data
263 * @write_oob: function to write chip OOB data
265 struct nand_ecc_ctrl
{
266 nand_ecc_modes_t mode
;
273 struct nand_ecclayout
*layout
;
274 void (*hwctl
)(struct mtd_info
*mtd
, int mode
);
275 int (*calculate
)(struct mtd_info
*mtd
,
278 int (*correct
)(struct mtd_info
*mtd
, uint8_t *dat
,
281 int (*read_page_raw
)(struct mtd_info
*mtd
,
282 struct nand_chip
*chip
,
283 uint8_t *buf
, int page
);
284 void (*write_page_raw
)(struct mtd_info
*mtd
,
285 struct nand_chip
*chip
,
287 int (*read_page
)(struct mtd_info
*mtd
,
288 struct nand_chip
*chip
,
289 uint8_t *buf
, int page
);
290 int (*read_subpage
)(struct mtd_info
*mtd
,
291 struct nand_chip
*chip
,
292 uint32_t offs
, uint32_t len
,
294 void (*write_page
)(struct mtd_info
*mtd
,
295 struct nand_chip
*chip
,
297 int (*read_oob
)(struct mtd_info
*mtd
,
298 struct nand_chip
*chip
,
301 int (*write_oob
)(struct mtd_info
*mtd
,
302 struct nand_chip
*chip
,
307 * struct nand_buffers - buffer structure for read/write
308 * @ecccalc: buffer for calculated ecc
309 * @ecccode: buffer for ecc read from flash
310 * @databuf: buffer for data - dynamically sized
312 * Do not change the order of buffers. databuf and oobrbuf must be in
315 struct nand_buffers
{
316 uint8_t ecccalc
[NAND_MAX_OOBSIZE
];
317 uint8_t ecccode
[NAND_MAX_OOBSIZE
];
318 uint8_t databuf
[NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
];
322 * struct nand_chip - NAND Private Flash Chip Data
323 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
324 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
325 * @read_byte: [REPLACEABLE] read one byte from the chip
326 * @read_word: [REPLACEABLE] read one word from the chip
327 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
328 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
329 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
330 * @select_chip: [REPLACEABLE] select chip nr
331 * @block_bad: [REPLACEABLE] check, if the block is bad
332 * @block_markbad: [REPLACEABLE] mark the block bad
333 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
334 * ALE/CLE/nCE. Also used to write command and address
335 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
336 * If set to NULL no access to ready/busy is available and the ready/busy information
337 * is read from the chip status register
338 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
339 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
340 * @ecc: [BOARDSPECIFIC] ecc control ctructure
341 * @buffers: buffer structure for read/write
342 * @hwcontrol: platform-specific hardware control structure
343 * @ops: oob operation operands
344 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
345 * @scan_bbt: [REPLACEABLE] function to scan bad block table
346 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
347 * @state: [INTERN] the current state of the NAND device
348 * @oob_poi: poison value buffer
349 * @page_shift: [INTERN] number of address bits in a page (column address bits)
350 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
351 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
352 * @chip_shift: [INTERN] number of address bits in one chip
353 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
354 * special functionality. See the defines for further explanation
355 * @badblockpos: [INTERN] position of the bad block marker in the oob area
356 * @cellinfo: [INTERN] MLC/multichip data from chip ident
357 * @numchips: [INTERN] number of physical chips
358 * @chipsize: [INTERN] the size of one chip for multichip arrays
359 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
360 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
361 * @subpagesize: [INTERN] holds the subpagesize
362 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
363 * @bbt: [INTERN] bad block table pointer
364 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
365 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
366 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
367 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
368 * which is shared among multiple independend devices
369 * @priv: [OPTIONAL] pointer to private chip date
370 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
371 * (determine if errors are correctable)
372 * @write_page: [REPLACEABLE] High-level page write function
376 void __iomem
*IO_ADDR_R
;
377 void __iomem
*IO_ADDR_W
;
379 uint8_t (*read_byte
)(struct mtd_info
*mtd
);
380 u16 (*read_word
)(struct mtd_info
*mtd
);
381 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
382 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
383 int (*verify_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
384 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
385 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
, int getchip
);
386 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
387 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
389 int (*dev_ready
)(struct mtd_info
*mtd
);
390 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
, int page_addr
);
391 int (*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this);
392 void (*erase_cmd
)(struct mtd_info
*mtd
, int page
);
393 int (*scan_bbt
)(struct mtd_info
*mtd
);
394 int (*errstat
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
, int status
, int page
);
395 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
396 const uint8_t *buf
, int page
, int cached
, int raw
);
399 unsigned int options
;
402 int phys_erase_shift
;
417 struct nand_hw_control
*controller
;
418 struct nand_ecclayout
*ecclayout
;
420 struct nand_ecc_ctrl ecc
;
421 struct nand_buffers
*buffers
;
422 struct nand_hw_control hwcontrol
;
424 struct mtd_oob_ops ops
;
427 struct nand_bbt_descr
*bbt_td
;
428 struct nand_bbt_descr
*bbt_md
;
430 struct nand_bbt_descr
*badblock_pattern
;
436 * NAND Flash Manufacturer ID Codes
438 #define NAND_MFR_TOSHIBA 0x98
439 #define NAND_MFR_SAMSUNG 0xec
440 #define NAND_MFR_FUJITSU 0x04
441 #define NAND_MFR_NATIONAL 0x8f
442 #define NAND_MFR_RENESAS 0x07
443 #define NAND_MFR_STMICRO 0x20
444 #define NAND_MFR_HYNIX 0xad
445 #define NAND_MFR_MICRON 0x2c
446 #define NAND_MFR_AMD 0x01
449 * struct nand_flash_dev - NAND Flash Device ID Structure
450 * @name: Identify the device type
451 * @id: device ID code
452 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
453 * If the pagesize is 0, then the real pagesize
454 * and the eraseize are determined from the
455 * extended id bytes in the chip
456 * @erasesize: Size of an erase block in the flash device.
457 * @chipsize: Total chipsize in Mega Bytes
458 * @options: Bitfield to store chip relevant options
460 struct nand_flash_dev
{
463 unsigned long pagesize
;
464 unsigned long chipsize
;
465 unsigned long erasesize
;
466 unsigned long options
;
470 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
471 * @name: Manufacturer name
472 * @id: manufacturer ID code of device.
474 struct nand_manufacturers
{
479 extern struct nand_flash_dev nand_flash_ids
[];
480 extern struct nand_manufacturers nand_manuf_ids
[];
482 extern int nand_scan_bbt(struct mtd_info
*mtd
, struct nand_bbt_descr
*bd
);
483 extern int nand_update_bbt(struct mtd_info
*mtd
, loff_t offs
);
484 extern int nand_default_bbt(struct mtd_info
*mtd
);
485 extern int nand_isbad_bbt(struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
486 extern int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
488 extern int nand_do_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
489 size_t * retlen
, uint8_t * buf
);
492 * struct platform_nand_chip - chip level device structure
493 * @nr_chips: max. number of chips to scan for
494 * @chip_offset: chip number offset
495 * @nr_partitions: number of partitions pointed to by partitions (or zero)
496 * @partitions: mtd partition list
497 * @chip_delay: R/B delay value in us
498 * @options: Option flags, e.g. 16bit buswidth
499 * @ecclayout: ecc layout info structure
500 * @part_probe_types: NULL-terminated array of probe types
501 * @set_parts: platform specific function to set partitions
502 * @priv: hardware controller specific settings
504 struct platform_nand_chip
{
508 struct mtd_partition
*partitions
;
509 struct nand_ecclayout
*ecclayout
;
511 unsigned int options
;
512 const char **part_probe_types
;
513 void (*set_parts
)(uint64_t size
,
514 struct platform_nand_chip
*chip
);
519 struct platform_device
;
522 * struct platform_nand_ctrl - controller level device structure
523 * @probe: platform specific function to probe/setup hardware
524 * @remove: platform specific function to remove/teardown hardware
525 * @hwcontrol: platform specific hardware control structure
526 * @dev_ready: platform specific function to read ready/busy pin
527 * @select_chip: platform specific chip select function
528 * @cmd_ctrl: platform specific function for controlling
529 * ALE/CLE/nCE. Also used to write command and address
530 * @write_buf: platform specific function for write buffer
531 * @read_buf: platform specific function for read buffer
532 * @priv: private data to transport driver specific settings
534 * All fields are optional and depend on the hardware driver requirements
536 struct platform_nand_ctrl
{
537 int (*probe
)(struct platform_device
*pdev
);
538 void (*remove
)(struct platform_device
*pdev
);
539 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
540 int (*dev_ready
)(struct mtd_info
*mtd
);
541 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
542 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
544 void (*write_buf
)(struct mtd_info
*mtd
,
545 const uint8_t *buf
, int len
);
546 void (*read_buf
)(struct mtd_info
*mtd
,
547 uint8_t *buf
, int len
);
552 * struct platform_nand_data - container structure for platform-specific data
553 * @chip: chip level chip structure
554 * @ctrl: controller level device structure
556 struct platform_nand_data
{
557 struct platform_nand_chip chip
;
558 struct platform_nand_ctrl ctrl
;
561 /* Some helpers to access the data structures */
563 struct platform_nand_chip
*get_platform_nandchip(struct mtd_info
*mtd
)
565 struct nand_chip
*chip
= mtd
->priv
;
570 #endif /* __LINUX_MTD_NAND_H */