2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev
;
29 /* Scan and identify a NAND device */
30 extern int nand_scan (struct mtd_info
*mtd
, int max_chips
);
31 /* Separate phases of nand_scan(), allowing board driver to intervene
32 * and override command or ECC setup according to flash type */
33 extern int nand_scan_ident(struct mtd_info
*mtd
, int max_chips
,
34 struct nand_flash_dev
*table
);
35 extern int nand_scan_tail(struct mtd_info
*mtd
);
37 /* Free resources held by the NAND device */
38 extern void nand_release (struct mtd_info
*mtd
);
40 /* Internal helper for board drivers which need to override command function */
41 extern void nand_wait_ready(struct mtd_info
*mtd
);
43 /* locks all blockes present in the device */
44 extern int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
46 /* unlocks specified locked blockes */
47 extern int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
);
49 /* The maximum number of NAND chips in an array */
50 #define NAND_MAX_CHIPS 8
52 /* This constant declares the max. oobsize / page, which
53 * is supported now. If you add a chip with bigger oobsize/page
54 * adjust this accordingly.
56 #define NAND_MAX_OOBSIZE 576
57 #define NAND_MAX_PAGESIZE 8192
60 * Constants for hardware specific CLE/ALE/NCE function
62 * These are bits which can be or'ed to set/clear multiple
65 /* Select the chip by setting nCE to low */
67 /* Select the command latch by setting CLE to high */
69 /* Select the address latch by setting ALE to high */
72 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
73 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
74 #define NAND_CTRL_CHANGE 0x80
77 * Standard NAND flash commands
79 #define NAND_CMD_READ0 0
80 #define NAND_CMD_READ1 1
81 #define NAND_CMD_RNDOUT 5
82 #define NAND_CMD_PAGEPROG 0x10
83 #define NAND_CMD_READOOB 0x50
84 #define NAND_CMD_ERASE1 0x60
85 #define NAND_CMD_STATUS 0x70
86 #define NAND_CMD_STATUS_MULTI 0x71
87 #define NAND_CMD_SEQIN 0x80
88 #define NAND_CMD_RNDIN 0x85
89 #define NAND_CMD_READID 0x90
90 #define NAND_CMD_ERASE2 0xd0
91 #define NAND_CMD_PARAM 0xec
92 #define NAND_CMD_RESET 0xff
94 #define NAND_CMD_LOCK 0x2a
95 #define NAND_CMD_UNLOCK1 0x23
96 #define NAND_CMD_UNLOCK2 0x24
98 /* Extended commands for large page devices */
99 #define NAND_CMD_READSTART 0x30
100 #define NAND_CMD_RNDOUTSTART 0xE0
101 #define NAND_CMD_CACHEDPROG 0x15
103 /* Extended commands for AG-AND device */
105 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
106 * there is no way to distinguish that from NAND_CMD_READ0
107 * until the remaining sequence of commands has been completed
108 * so add a high order bit and mask it off in the command.
110 #define NAND_CMD_DEPLETE1 0x100
111 #define NAND_CMD_DEPLETE2 0x38
112 #define NAND_CMD_STATUS_MULTI 0x71
113 #define NAND_CMD_STATUS_ERROR 0x72
114 /* multi-bank error status (banks 0-3) */
115 #define NAND_CMD_STATUS_ERROR0 0x73
116 #define NAND_CMD_STATUS_ERROR1 0x74
117 #define NAND_CMD_STATUS_ERROR2 0x75
118 #define NAND_CMD_STATUS_ERROR3 0x76
119 #define NAND_CMD_STATUS_RESET 0x7f
120 #define NAND_CMD_STATUS_CLEAR 0xff
122 #define NAND_CMD_NONE -1
125 #define NAND_STATUS_FAIL 0x01
126 #define NAND_STATUS_FAIL_N1 0x02
127 #define NAND_STATUS_TRUE_READY 0x20
128 #define NAND_STATUS_READY 0x40
129 #define NAND_STATUS_WP 0x80
132 * Constants for ECC_MODES
138 NAND_ECC_HW_SYNDROME
,
139 NAND_ECC_HW_OOB_FIRST
,
143 * Constants for Hardware ECC
145 /* Reset Hardware ECC for read */
146 #define NAND_ECC_READ 0
147 /* Reset Hardware ECC for write */
148 #define NAND_ECC_WRITE 1
149 /* Enable Hardware ECC before syndrom is read back from flash */
150 #define NAND_ECC_READSYN 2
152 /* Bit mask for flags passed to do_nand_read_ecc */
153 #define NAND_GET_DEVICE 0x80
156 /* Option constants for bizarre disfunctionality and real
159 /* Chip can not auto increment pages */
160 #define NAND_NO_AUTOINCR 0x00000001
161 /* Buswitdh is 16 bit */
162 #define NAND_BUSWIDTH_16 0x00000002
163 /* Device supports partial programming without padding */
164 #define NAND_NO_PADDING 0x00000004
165 /* Chip has cache program function */
166 #define NAND_CACHEPRG 0x00000008
167 /* Chip has copy back function */
168 #define NAND_COPYBACK 0x00000010
169 /* AND Chip which has 4 banks and a confusing page / block
170 * assignment. See Renesas datasheet for further information */
171 #define NAND_IS_AND 0x00000020
172 /* Chip has a array of 4 pages which can be read without
173 * additional ready /busy waits */
174 #define NAND_4PAGE_ARRAY 0x00000040
175 /* Chip requires that BBT is periodically rewritten to prevent
176 * bits from adjacent blocks from 'leaking' in altering data.
177 * This happens with the Renesas AG-AND chips, possibly others. */
178 #define BBT_AUTO_REFRESH 0x00000080
179 /* Chip does not require ready check on read. True
180 * for all large page devices, as they do not support
182 #define NAND_NO_READRDY 0x00000100
183 /* Chip does not allow subpage writes */
184 #define NAND_NO_SUBPAGE_WRITE 0x00000200
186 /* Device is one of 'new' xD cards that expose fake nand command set */
187 #define NAND_BROKEN_XD 0x00000400
189 /* Device behaves just like nand, but is readonly */
190 #define NAND_ROM 0x00000800
192 /* Options valid for Samsung large page devices */
193 #define NAND_SAMSUNG_LP_OPTIONS \
194 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
196 /* Macros to identify the above */
197 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
198 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
199 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
200 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
201 /* Large page NAND with SOFT_ECC should support subpage reads */
202 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
203 && (chip->page_shift > 9))
205 /* Mask to zero out the chip options, which come from the id table */
206 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
208 /* Non chip related options */
209 /* Use a flash based bad block table. This option is passed to the
210 * default bad block table function. */
211 #define NAND_USE_FLASH_BBT 0x00010000
212 /* This option skips the bbt scan during initialization. */
213 #define NAND_SKIP_BBTSCAN 0x00020000
214 /* This option is defined if the board driver allocates its own buffers
215 (e.g. because it needs them DMA-coherent */
216 #define NAND_OWN_BUFFERS 0x00040000
217 /* Chip may not exist, so silence any errors in scan */
218 #define NAND_SCAN_SILENT_NODEV 0x00080000
220 /* Options set by nand scan */
221 /* Nand scan has allocated controller struct */
222 #define NAND_CONTROLLER_ALLOC 0x80000000
224 /* Cell info constants */
225 #define NAND_CI_CHIPNR_MSK 0x03
226 #define NAND_CI_CELLTYPE_MSK 0x0C
232 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
233 * @lock: protection lock
234 * @active: the mtd device which holds the controller currently
235 * @wq: wait queue to sleep on if a NAND operation is in progress
236 * used instead of the per chip wait queue when a hw controller is available
238 struct nand_hw_control
{
240 struct nand_chip
*active
;
241 wait_queue_head_t wq
;
245 * struct nand_ecc_ctrl - Control structure for ecc
247 * @steps: number of ecc steps per page
248 * @size: data bytes per ecc step
249 * @bytes: ecc bytes per step
250 * @total: total number of ecc bytes per page
251 * @prepad: padding information for syndrome based ecc generators
252 * @postpad: padding information for syndrome based ecc generators
253 * @layout: ECC layout control struct pointer
254 * @hwctl: function to control hardware ecc generator. Must only
255 * be provided if an hardware ECC is available
256 * @calculate: function for ecc calculation or readback from ecc hardware
257 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
258 * @read_page_raw: function to read a raw page without ECC
259 * @write_page_raw: function to write a raw page without ECC
260 * @read_page: function to read a page according to the ecc generator requirements
261 * @read_subpage: function to read parts of the page covered by ECC.
262 * @write_page: function to write a page according to the ecc generator requirements
263 * @read_oob: function to read chip OOB data
264 * @write_oob: function to write chip OOB data
266 struct nand_ecc_ctrl
{
267 nand_ecc_modes_t mode
;
274 struct nand_ecclayout
*layout
;
275 void (*hwctl
)(struct mtd_info
*mtd
, int mode
);
276 int (*calculate
)(struct mtd_info
*mtd
,
279 int (*correct
)(struct mtd_info
*mtd
, uint8_t *dat
,
282 int (*read_page_raw
)(struct mtd_info
*mtd
,
283 struct nand_chip
*chip
,
284 uint8_t *buf
, int page
);
285 void (*write_page_raw
)(struct mtd_info
*mtd
,
286 struct nand_chip
*chip
,
288 int (*read_page
)(struct mtd_info
*mtd
,
289 struct nand_chip
*chip
,
290 uint8_t *buf
, int page
);
291 int (*read_subpage
)(struct mtd_info
*mtd
,
292 struct nand_chip
*chip
,
293 uint32_t offs
, uint32_t len
,
295 void (*write_page
)(struct mtd_info
*mtd
,
296 struct nand_chip
*chip
,
298 int (*read_oob
)(struct mtd_info
*mtd
,
299 struct nand_chip
*chip
,
302 int (*write_oob
)(struct mtd_info
*mtd
,
303 struct nand_chip
*chip
,
308 * struct nand_buffers - buffer structure for read/write
309 * @ecccalc: buffer for calculated ecc
310 * @ecccode: buffer for ecc read from flash
311 * @databuf: buffer for data - dynamically sized
313 * Do not change the order of buffers. databuf and oobrbuf must be in
316 struct nand_buffers
{
317 uint8_t ecccalc
[NAND_MAX_OOBSIZE
];
318 uint8_t ecccode
[NAND_MAX_OOBSIZE
];
319 uint8_t databuf
[NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
];
323 * struct nand_chip - NAND Private Flash Chip Data
324 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
325 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
326 * @read_byte: [REPLACEABLE] read one byte from the chip
327 * @read_word: [REPLACEABLE] read one word from the chip
328 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
329 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
330 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
331 * @select_chip: [REPLACEABLE] select chip nr
332 * @block_bad: [REPLACEABLE] check, if the block is bad
333 * @block_markbad: [REPLACEABLE] mark the block bad
334 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
335 * ALE/CLE/nCE. Also used to write command and address
336 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
337 * If set to NULL no access to ready/busy is available and the ready/busy information
338 * is read from the chip status register
339 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
340 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
341 * @ecc: [BOARDSPECIFIC] ecc control ctructure
342 * @buffers: buffer structure for read/write
343 * @hwcontrol: platform-specific hardware control structure
344 * @ops: oob operation operands
345 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
346 * @scan_bbt: [REPLACEABLE] function to scan bad block table
347 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
348 * @state: [INTERN] the current state of the NAND device
349 * @oob_poi: poison value buffer
350 * @page_shift: [INTERN] number of address bits in a page (column address bits)
351 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
352 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
353 * @chip_shift: [INTERN] number of address bits in one chip
354 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
355 * special functionality. See the defines for further explanation
356 * @badblockpos: [INTERN] position of the bad block marker in the oob area
357 * @cellinfo: [INTERN] MLC/multichip data from chip ident
358 * @numchips: [INTERN] number of physical chips
359 * @chipsize: [INTERN] the size of one chip for multichip arrays
360 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
361 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
362 * @subpagesize: [INTERN] holds the subpagesize
363 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
364 * @bbt: [INTERN] bad block table pointer
365 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
366 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
367 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
368 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
369 * which is shared among multiple independend devices
370 * @priv: [OPTIONAL] pointer to private chip date
371 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
372 * (determine if errors are correctable)
373 * @write_page: [REPLACEABLE] High-level page write function
377 void __iomem
*IO_ADDR_R
;
378 void __iomem
*IO_ADDR_W
;
380 uint8_t (*read_byte
)(struct mtd_info
*mtd
);
381 u16 (*read_word
)(struct mtd_info
*mtd
);
382 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
383 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
384 int (*verify_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
385 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
386 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
, int getchip
);
387 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
388 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
390 int (*dev_ready
)(struct mtd_info
*mtd
);
391 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
, int page_addr
);
392 int (*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this);
393 void (*erase_cmd
)(struct mtd_info
*mtd
, int page
);
394 int (*scan_bbt
)(struct mtd_info
*mtd
);
395 int (*errstat
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
, int status
, int page
);
396 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
397 const uint8_t *buf
, int page
, int cached
, int raw
);
400 unsigned int options
;
403 int phys_erase_shift
;
418 struct nand_hw_control
*controller
;
419 struct nand_ecclayout
*ecclayout
;
421 struct nand_ecc_ctrl ecc
;
422 struct nand_buffers
*buffers
;
423 struct nand_hw_control hwcontrol
;
425 struct mtd_oob_ops ops
;
428 struct nand_bbt_descr
*bbt_td
;
429 struct nand_bbt_descr
*bbt_md
;
431 struct nand_bbt_descr
*badblock_pattern
;
437 * NAND Flash Manufacturer ID Codes
439 #define NAND_MFR_TOSHIBA 0x98
440 #define NAND_MFR_SAMSUNG 0xec
441 #define NAND_MFR_FUJITSU 0x04
442 #define NAND_MFR_NATIONAL 0x8f
443 #define NAND_MFR_RENESAS 0x07
444 #define NAND_MFR_STMICRO 0x20
445 #define NAND_MFR_HYNIX 0xad
446 #define NAND_MFR_MICRON 0x2c
447 #define NAND_MFR_AMD 0x01
450 * struct nand_flash_dev - NAND Flash Device ID Structure
451 * @name: Identify the device type
452 * @id: device ID code
453 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
454 * If the pagesize is 0, then the real pagesize
455 * and the eraseize are determined from the
456 * extended id bytes in the chip
457 * @erasesize: Size of an erase block in the flash device.
458 * @chipsize: Total chipsize in Mega Bytes
459 * @options: Bitfield to store chip relevant options
461 struct nand_flash_dev
{
464 unsigned long pagesize
;
465 unsigned long chipsize
;
466 unsigned long erasesize
;
467 unsigned long options
;
471 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
472 * @name: Manufacturer name
473 * @id: manufacturer ID code of device.
475 struct nand_manufacturers
{
480 extern struct nand_flash_dev nand_flash_ids
[];
481 extern struct nand_manufacturers nand_manuf_ids
[];
483 extern int nand_scan_bbt(struct mtd_info
*mtd
, struct nand_bbt_descr
*bd
);
484 extern int nand_update_bbt(struct mtd_info
*mtd
, loff_t offs
);
485 extern int nand_default_bbt(struct mtd_info
*mtd
);
486 extern int nand_isbad_bbt(struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
487 extern int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
489 extern int nand_do_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
490 size_t * retlen
, uint8_t * buf
);
493 * struct platform_nand_chip - chip level device structure
494 * @nr_chips: max. number of chips to scan for
495 * @chip_offset: chip number offset
496 * @nr_partitions: number of partitions pointed to by partitions (or zero)
497 * @partitions: mtd partition list
498 * @chip_delay: R/B delay value in us
499 * @options: Option flags, e.g. 16bit buswidth
500 * @ecclayout: ecc layout info structure
501 * @part_probe_types: NULL-terminated array of probe types
502 * @set_parts: platform specific function to set partitions
503 * @priv: hardware controller specific settings
505 struct platform_nand_chip
{
509 struct mtd_partition
*partitions
;
510 struct nand_ecclayout
*ecclayout
;
512 unsigned int options
;
513 const char **part_probe_types
;
514 void (*set_parts
)(uint64_t size
,
515 struct platform_nand_chip
*chip
);
520 struct platform_device
;
523 * struct platform_nand_ctrl - controller level device structure
524 * @probe: platform specific function to probe/setup hardware
525 * @remove: platform specific function to remove/teardown hardware
526 * @hwcontrol: platform specific hardware control structure
527 * @dev_ready: platform specific function to read ready/busy pin
528 * @select_chip: platform specific chip select function
529 * @cmd_ctrl: platform specific function for controlling
530 * ALE/CLE/nCE. Also used to write command and address
531 * @write_buf: platform specific function for write buffer
532 * @read_buf: platform specific function for read buffer
533 * @priv: private data to transport driver specific settings
535 * All fields are optional and depend on the hardware driver requirements
537 struct platform_nand_ctrl
{
538 int (*probe
)(struct platform_device
*pdev
);
539 void (*remove
)(struct platform_device
*pdev
);
540 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
541 int (*dev_ready
)(struct mtd_info
*mtd
);
542 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
543 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
545 void (*write_buf
)(struct mtd_info
*mtd
,
546 const uint8_t *buf
, int len
);
547 void (*read_buf
)(struct mtd_info
*mtd
,
548 uint8_t *buf
, int len
);
553 * struct platform_nand_data - container structure for platform-specific data
554 * @chip: chip level chip structure
555 * @ctrl: controller level device structure
557 struct platform_nand_data
{
558 struct platform_nand_chip chip
;
559 struct platform_nand_ctrl ctrl
;
562 /* Some helpers to access the data structures */
564 struct platform_nand_chip
*get_platform_nandchip(struct mtd_info
*mtd
)
566 struct nand_chip
*chip
= mtd
->priv
;
571 #endif /* __LINUX_MTD_NAND_H */