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PCI: iproc: Fix return value of iproc_msi_irq_domain_alloc()
[mirror_ubuntu-focal-kernel.git] / include / linux / nvme.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/types.h>
11 #include <linux/uuid.h>
12
13 /* NQN names in commands fields specified one size */
14 #define NVMF_NQN_FIELD_LEN 256
15
16 /* However the max length of a qualified name is another size */
17 #define NVMF_NQN_SIZE 223
18
19 #define NVMF_TRSVCID_SIZE 32
20 #define NVMF_TRADDR_SIZE 256
21 #define NVMF_TSAS_SIZE 256
22
23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
24
25 #define NVME_RDMA_IP_PORT 4420
26
27 #define NVME_NSID_ALL 0xffffffff
28
29 enum nvme_subsys_type {
30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
31 NVME_NQN_NVME = 2, /* NVME type target subsystem */
32 };
33
34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
35 enum {
36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
41 };
42
43 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
44 enum {
45 NVMF_TRTYPE_RDMA = 1, /* RDMA */
46 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
47 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
48 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
49 NVMF_TRTYPE_MAX,
50 };
51
52 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
53 enum {
54 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
55 NVMF_TREQ_REQUIRED = 1, /* Required */
56 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
57 #define NVME_TREQ_SECURE_CHANNEL_MASK \
58 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
59
60 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
61 };
62
63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
64 * RDMA_QPTYPE field
65 */
66 enum {
67 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
68 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
69 };
70
71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
72 * RDMA_QPTYPE field
73 */
74 enum {
75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
76 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
77 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
78 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
79 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
80 };
81
82 /* RDMA Connection Management Service Type codes for Discovery Log Page
83 * entry TSAS RDMA_CMS field
84 */
85 enum {
86 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
87 };
88
89 #define NVME_AQ_DEPTH 32
90 #define NVME_NR_AEN_COMMANDS 1
91 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
92
93 /*
94 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
95 * NVM-Express 1.2 specification, section 4.1.2.
96 */
97 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
98
99 enum {
100 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
101 NVME_REG_VS = 0x0008, /* Version */
102 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
103 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
104 NVME_REG_CC = 0x0014, /* Controller Configuration */
105 NVME_REG_CSTS = 0x001c, /* Controller Status */
106 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
107 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
108 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
109 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
110 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
111 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
112 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
113 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
114 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
115 * Location
116 */
117 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
118 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
119 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
120 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
121 * Buffer Size
122 */
123 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
124 * Write Throughput
125 */
126 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
127 };
128
129 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
130 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
131 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
132 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
133 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
134 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
135
136 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
137 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
138
139 enum {
140 NVME_CMBSZ_SQS = 1 << 0,
141 NVME_CMBSZ_CQS = 1 << 1,
142 NVME_CMBSZ_LISTS = 1 << 2,
143 NVME_CMBSZ_RDS = 1 << 3,
144 NVME_CMBSZ_WDS = 1 << 4,
145
146 NVME_CMBSZ_SZ_SHIFT = 12,
147 NVME_CMBSZ_SZ_MASK = 0xfffff,
148
149 NVME_CMBSZ_SZU_SHIFT = 8,
150 NVME_CMBSZ_SZU_MASK = 0xf,
151 };
152
153 /*
154 * Submission and Completion Queue Entry Sizes for the NVM command set.
155 * (In bytes and specified as a power of two (2^n)).
156 */
157 #define NVME_ADM_SQES 6
158 #define NVME_NVM_IOSQES 6
159 #define NVME_NVM_IOCQES 4
160
161 enum {
162 NVME_CC_ENABLE = 1 << 0,
163 NVME_CC_CSS_NVM = 0 << 4,
164 NVME_CC_EN_SHIFT = 0,
165 NVME_CC_CSS_SHIFT = 4,
166 NVME_CC_MPS_SHIFT = 7,
167 NVME_CC_AMS_SHIFT = 11,
168 NVME_CC_SHN_SHIFT = 14,
169 NVME_CC_IOSQES_SHIFT = 16,
170 NVME_CC_IOCQES_SHIFT = 20,
171 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
172 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
173 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
174 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
175 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
176 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
177 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
178 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
179 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
180 NVME_CSTS_RDY = 1 << 0,
181 NVME_CSTS_CFS = 1 << 1,
182 NVME_CSTS_NSSRO = 1 << 4,
183 NVME_CSTS_PP = 1 << 5,
184 NVME_CSTS_SHST_NORMAL = 0 << 2,
185 NVME_CSTS_SHST_OCCUR = 1 << 2,
186 NVME_CSTS_SHST_CMPLT = 2 << 2,
187 NVME_CSTS_SHST_MASK = 3 << 2,
188 };
189
190 struct nvme_id_power_state {
191 __le16 max_power; /* centiwatts */
192 __u8 rsvd2;
193 __u8 flags;
194 __le32 entry_lat; /* microseconds */
195 __le32 exit_lat; /* microseconds */
196 __u8 read_tput;
197 __u8 read_lat;
198 __u8 write_tput;
199 __u8 write_lat;
200 __le16 idle_power;
201 __u8 idle_scale;
202 __u8 rsvd19;
203 __le16 active_power;
204 __u8 active_work_scale;
205 __u8 rsvd23[9];
206 };
207
208 enum {
209 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
210 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
211 };
212
213 enum nvme_ctrl_attr {
214 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
215 NVME_CTRL_ATTR_TBKAS = (1 << 6),
216 };
217
218 struct nvme_id_ctrl {
219 __le16 vid;
220 __le16 ssvid;
221 char sn[20];
222 char mn[40];
223 char fr[8];
224 __u8 rab;
225 __u8 ieee[3];
226 __u8 cmic;
227 __u8 mdts;
228 __le16 cntlid;
229 __le32 ver;
230 __le32 rtd3r;
231 __le32 rtd3e;
232 __le32 oaes;
233 __le32 ctratt;
234 __u8 rsvd100[28];
235 __le16 crdt1;
236 __le16 crdt2;
237 __le16 crdt3;
238 __u8 rsvd134[122];
239 __le16 oacs;
240 __u8 acl;
241 __u8 aerl;
242 __u8 frmw;
243 __u8 lpa;
244 __u8 elpe;
245 __u8 npss;
246 __u8 avscc;
247 __u8 apsta;
248 __le16 wctemp;
249 __le16 cctemp;
250 __le16 mtfa;
251 __le32 hmpre;
252 __le32 hmmin;
253 __u8 tnvmcap[16];
254 __u8 unvmcap[16];
255 __le32 rpmbs;
256 __le16 edstt;
257 __u8 dsto;
258 __u8 fwug;
259 __le16 kas;
260 __le16 hctma;
261 __le16 mntmt;
262 __le16 mxtmt;
263 __le32 sanicap;
264 __le32 hmminds;
265 __le16 hmmaxd;
266 __u8 rsvd338[4];
267 __u8 anatt;
268 __u8 anacap;
269 __le32 anagrpmax;
270 __le32 nanagrpid;
271 __u8 rsvd352[160];
272 __u8 sqes;
273 __u8 cqes;
274 __le16 maxcmd;
275 __le32 nn;
276 __le16 oncs;
277 __le16 fuses;
278 __u8 fna;
279 __u8 vwc;
280 __le16 awun;
281 __le16 awupf;
282 __u8 nvscc;
283 __u8 nwpc;
284 __le16 acwu;
285 __u8 rsvd534[2];
286 __le32 sgls;
287 __le32 mnan;
288 __u8 rsvd544[224];
289 char subnqn[256];
290 __u8 rsvd1024[768];
291 __le32 ioccsz;
292 __le32 iorcsz;
293 __le16 icdoff;
294 __u8 ctrattr;
295 __u8 msdbd;
296 __u8 rsvd1804[244];
297 struct nvme_id_power_state psd[32];
298 __u8 vs[1024];
299 };
300
301 enum {
302 NVME_CTRL_ONCS_COMPARE = 1 << 0,
303 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
304 NVME_CTRL_ONCS_DSM = 1 << 2,
305 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
306 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
307 NVME_CTRL_VWC_PRESENT = 1 << 0,
308 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
309 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
310 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
311 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
312 NVME_CTRL_CTRATT_128_ID = 1 << 0,
313 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
314 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
315 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
316 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
317 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
318 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
319 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
320 };
321
322 struct nvme_lbaf {
323 __le16 ms;
324 __u8 ds;
325 __u8 rp;
326 };
327
328 struct nvme_id_ns {
329 __le64 nsze;
330 __le64 ncap;
331 __le64 nuse;
332 __u8 nsfeat;
333 __u8 nlbaf;
334 __u8 flbas;
335 __u8 mc;
336 __u8 dpc;
337 __u8 dps;
338 __u8 nmic;
339 __u8 rescap;
340 __u8 fpi;
341 __u8 dlfeat;
342 __le16 nawun;
343 __le16 nawupf;
344 __le16 nacwu;
345 __le16 nabsn;
346 __le16 nabo;
347 __le16 nabspf;
348 __le16 noiob;
349 __u8 nvmcap[16];
350 __le16 npwg;
351 __le16 npwa;
352 __le16 npdg;
353 __le16 npda;
354 __le16 nows;
355 __u8 rsvd74[18];
356 __le32 anagrpid;
357 __u8 rsvd96[3];
358 __u8 nsattr;
359 __le16 nvmsetid;
360 __le16 endgid;
361 __u8 nguid[16];
362 __u8 eui64[8];
363 struct nvme_lbaf lbaf[16];
364 __u8 rsvd192[192];
365 __u8 vs[3712];
366 };
367
368 enum {
369 NVME_ID_CNS_NS = 0x00,
370 NVME_ID_CNS_CTRL = 0x01,
371 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
372 NVME_ID_CNS_NS_DESC_LIST = 0x03,
373 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
374 NVME_ID_CNS_NS_PRESENT = 0x11,
375 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
376 NVME_ID_CNS_CTRL_LIST = 0x13,
377 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
378 NVME_ID_CNS_NS_GRANULARITY = 0x16,
379 NVME_ID_CNS_UUID_LIST = 0x17,
380 };
381
382 enum {
383 NVME_DIR_IDENTIFY = 0x00,
384 NVME_DIR_STREAMS = 0x01,
385 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
386 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
387 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
388 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
389 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
390 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
391 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
392 NVME_DIR_ENDIR = 0x01,
393 };
394
395 enum {
396 NVME_NS_FEAT_THIN = 1 << 0,
397 NVME_NS_FLBAS_LBA_MASK = 0xf,
398 NVME_NS_FLBAS_META_EXT = 0x10,
399 NVME_LBAF_RP_BEST = 0,
400 NVME_LBAF_RP_BETTER = 1,
401 NVME_LBAF_RP_GOOD = 2,
402 NVME_LBAF_RP_DEGRADED = 3,
403 NVME_NS_DPC_PI_LAST = 1 << 4,
404 NVME_NS_DPC_PI_FIRST = 1 << 3,
405 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
406 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
407 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
408 NVME_NS_DPS_PI_FIRST = 1 << 3,
409 NVME_NS_DPS_PI_MASK = 0x7,
410 NVME_NS_DPS_PI_TYPE1 = 1,
411 NVME_NS_DPS_PI_TYPE2 = 2,
412 NVME_NS_DPS_PI_TYPE3 = 3,
413 };
414
415 struct nvme_ns_id_desc {
416 __u8 nidt;
417 __u8 nidl;
418 __le16 reserved;
419 };
420
421 #define NVME_NIDT_EUI64_LEN 8
422 #define NVME_NIDT_NGUID_LEN 16
423 #define NVME_NIDT_UUID_LEN 16
424
425 enum {
426 NVME_NIDT_EUI64 = 0x01,
427 NVME_NIDT_NGUID = 0x02,
428 NVME_NIDT_UUID = 0x03,
429 };
430
431 struct nvme_smart_log {
432 __u8 critical_warning;
433 __u8 temperature[2];
434 __u8 avail_spare;
435 __u8 spare_thresh;
436 __u8 percent_used;
437 __u8 endu_grp_crit_warn_sumry;
438 __u8 rsvd7[25];
439 __u8 data_units_read[16];
440 __u8 data_units_written[16];
441 __u8 host_reads[16];
442 __u8 host_writes[16];
443 __u8 ctrl_busy_time[16];
444 __u8 power_cycles[16];
445 __u8 power_on_hours[16];
446 __u8 unsafe_shutdowns[16];
447 __u8 media_errors[16];
448 __u8 num_err_log_entries[16];
449 __le32 warning_temp_time;
450 __le32 critical_comp_time;
451 __le16 temp_sensor[8];
452 __le32 thm_temp1_trans_count;
453 __le32 thm_temp2_trans_count;
454 __le32 thm_temp1_total_time;
455 __le32 thm_temp2_total_time;
456 __u8 rsvd232[280];
457 };
458
459 struct nvme_fw_slot_info_log {
460 __u8 afi;
461 __u8 rsvd1[7];
462 __le64 frs[7];
463 __u8 rsvd64[448];
464 };
465
466 enum {
467 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
468 NVME_CMD_EFFECTS_LBCC = 1 << 1,
469 NVME_CMD_EFFECTS_NCC = 1 << 2,
470 NVME_CMD_EFFECTS_NIC = 1 << 3,
471 NVME_CMD_EFFECTS_CCC = 1 << 4,
472 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
473 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
474 };
475
476 struct nvme_effects_log {
477 __le32 acs[256];
478 __le32 iocs[256];
479 __u8 resv[2048];
480 };
481
482 enum nvme_ana_state {
483 NVME_ANA_OPTIMIZED = 0x01,
484 NVME_ANA_NONOPTIMIZED = 0x02,
485 NVME_ANA_INACCESSIBLE = 0x03,
486 NVME_ANA_PERSISTENT_LOSS = 0x04,
487 NVME_ANA_CHANGE = 0x0f,
488 };
489
490 struct nvme_ana_group_desc {
491 __le32 grpid;
492 __le32 nnsids;
493 __le64 chgcnt;
494 __u8 state;
495 __u8 rsvd17[15];
496 __le32 nsids[];
497 };
498
499 /* flag for the log specific field of the ANA log */
500 #define NVME_ANA_LOG_RGO (1 << 0)
501
502 struct nvme_ana_rsp_hdr {
503 __le64 chgcnt;
504 __le16 ngrps;
505 __le16 rsvd10[3];
506 };
507
508 enum {
509 NVME_SMART_CRIT_SPARE = 1 << 0,
510 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
511 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
512 NVME_SMART_CRIT_MEDIA = 1 << 3,
513 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
514 };
515
516 enum {
517 NVME_AER_ERROR = 0,
518 NVME_AER_SMART = 1,
519 NVME_AER_NOTICE = 2,
520 NVME_AER_CSS = 6,
521 NVME_AER_VS = 7,
522 };
523
524 enum {
525 NVME_AER_NOTICE_NS_CHANGED = 0x00,
526 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
527 NVME_AER_NOTICE_ANA = 0x03,
528 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
529 };
530
531 enum {
532 NVME_AEN_BIT_NS_ATTR = 8,
533 NVME_AEN_BIT_FW_ACT = 9,
534 NVME_AEN_BIT_ANA_CHANGE = 11,
535 NVME_AEN_BIT_DISC_CHANGE = 31,
536 };
537
538 enum {
539 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
540 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
541 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
542 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
543 };
544
545 struct nvme_lba_range_type {
546 __u8 type;
547 __u8 attributes;
548 __u8 rsvd2[14];
549 __u64 slba;
550 __u64 nlb;
551 __u8 guid[16];
552 __u8 rsvd48[16];
553 };
554
555 enum {
556 NVME_LBART_TYPE_FS = 0x01,
557 NVME_LBART_TYPE_RAID = 0x02,
558 NVME_LBART_TYPE_CACHE = 0x03,
559 NVME_LBART_TYPE_SWAP = 0x04,
560
561 NVME_LBART_ATTRIB_TEMP = 1 << 0,
562 NVME_LBART_ATTRIB_HIDE = 1 << 1,
563 };
564
565 struct nvme_reservation_status {
566 __le32 gen;
567 __u8 rtype;
568 __u8 regctl[2];
569 __u8 resv5[2];
570 __u8 ptpls;
571 __u8 resv10[13];
572 struct {
573 __le16 cntlid;
574 __u8 rcsts;
575 __u8 resv3[5];
576 __le64 hostid;
577 __le64 rkey;
578 } regctl_ds[];
579 };
580
581 enum nvme_async_event_type {
582 NVME_AER_TYPE_ERROR = 0,
583 NVME_AER_TYPE_SMART = 1,
584 NVME_AER_TYPE_NOTICE = 2,
585 };
586
587 /* I/O commands */
588
589 enum nvme_opcode {
590 nvme_cmd_flush = 0x00,
591 nvme_cmd_write = 0x01,
592 nvme_cmd_read = 0x02,
593 nvme_cmd_write_uncor = 0x04,
594 nvme_cmd_compare = 0x05,
595 nvme_cmd_write_zeroes = 0x08,
596 nvme_cmd_dsm = 0x09,
597 nvme_cmd_verify = 0x0c,
598 nvme_cmd_resv_register = 0x0d,
599 nvme_cmd_resv_report = 0x0e,
600 nvme_cmd_resv_acquire = 0x11,
601 nvme_cmd_resv_release = 0x15,
602 };
603
604 #define nvme_opcode_name(opcode) { opcode, #opcode }
605 #define show_nvm_opcode_name(val) \
606 __print_symbolic(val, \
607 nvme_opcode_name(nvme_cmd_flush), \
608 nvme_opcode_name(nvme_cmd_write), \
609 nvme_opcode_name(nvme_cmd_read), \
610 nvme_opcode_name(nvme_cmd_write_uncor), \
611 nvme_opcode_name(nvme_cmd_compare), \
612 nvme_opcode_name(nvme_cmd_write_zeroes), \
613 nvme_opcode_name(nvme_cmd_dsm), \
614 nvme_opcode_name(nvme_cmd_resv_register), \
615 nvme_opcode_name(nvme_cmd_resv_report), \
616 nvme_opcode_name(nvme_cmd_resv_acquire), \
617 nvme_opcode_name(nvme_cmd_resv_release))
618
619
620 /*
621 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
622 *
623 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
624 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
625 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
626 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
627 * request subtype
628 */
629 enum {
630 NVME_SGL_FMT_ADDRESS = 0x00,
631 NVME_SGL_FMT_OFFSET = 0x01,
632 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
633 NVME_SGL_FMT_INVALIDATE = 0x0f,
634 };
635
636 /*
637 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
638 *
639 * For struct nvme_sgl_desc:
640 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
641 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
642 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
643 *
644 * For struct nvme_keyed_sgl_desc:
645 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
646 *
647 * Transport-specific SGL types:
648 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
649 */
650 enum {
651 NVME_SGL_FMT_DATA_DESC = 0x00,
652 NVME_SGL_FMT_SEG_DESC = 0x02,
653 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
654 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
655 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
656 };
657
658 struct nvme_sgl_desc {
659 __le64 addr;
660 __le32 length;
661 __u8 rsvd[3];
662 __u8 type;
663 };
664
665 struct nvme_keyed_sgl_desc {
666 __le64 addr;
667 __u8 length[3];
668 __u8 key[4];
669 __u8 type;
670 };
671
672 union nvme_data_ptr {
673 struct {
674 __le64 prp1;
675 __le64 prp2;
676 };
677 struct nvme_sgl_desc sgl;
678 struct nvme_keyed_sgl_desc ksgl;
679 };
680
681 /*
682 * Lowest two bits of our flags field (FUSE field in the spec):
683 *
684 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
685 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
686 *
687 * Highest two bits in our flags field (PSDT field in the spec):
688 *
689 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
690 * If used, MPTR contains addr of single physical buffer (byte aligned).
691 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
692 * If used, MPTR contains an address of an SGL segment containing
693 * exactly 1 SGL descriptor (qword aligned).
694 */
695 enum {
696 NVME_CMD_FUSE_FIRST = (1 << 0),
697 NVME_CMD_FUSE_SECOND = (1 << 1),
698
699 NVME_CMD_SGL_METABUF = (1 << 6),
700 NVME_CMD_SGL_METASEG = (1 << 7),
701 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
702 };
703
704 struct nvme_common_command {
705 __u8 opcode;
706 __u8 flags;
707 __u16 command_id;
708 __le32 nsid;
709 __le32 cdw2[2];
710 __le64 metadata;
711 union nvme_data_ptr dptr;
712 __le32 cdw10;
713 __le32 cdw11;
714 __le32 cdw12;
715 __le32 cdw13;
716 __le32 cdw14;
717 __le32 cdw15;
718 };
719
720 struct nvme_rw_command {
721 __u8 opcode;
722 __u8 flags;
723 __u16 command_id;
724 __le32 nsid;
725 __u64 rsvd2;
726 __le64 metadata;
727 union nvme_data_ptr dptr;
728 __le64 slba;
729 __le16 length;
730 __le16 control;
731 __le32 dsmgmt;
732 __le32 reftag;
733 __le16 apptag;
734 __le16 appmask;
735 };
736
737 enum {
738 NVME_RW_LR = 1 << 15,
739 NVME_RW_FUA = 1 << 14,
740 NVME_RW_DSM_FREQ_UNSPEC = 0,
741 NVME_RW_DSM_FREQ_TYPICAL = 1,
742 NVME_RW_DSM_FREQ_RARE = 2,
743 NVME_RW_DSM_FREQ_READS = 3,
744 NVME_RW_DSM_FREQ_WRITES = 4,
745 NVME_RW_DSM_FREQ_RW = 5,
746 NVME_RW_DSM_FREQ_ONCE = 6,
747 NVME_RW_DSM_FREQ_PREFETCH = 7,
748 NVME_RW_DSM_FREQ_TEMP = 8,
749 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
750 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
751 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
752 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
753 NVME_RW_DSM_SEQ_REQ = 1 << 6,
754 NVME_RW_DSM_COMPRESSED = 1 << 7,
755 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
756 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
757 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
758 NVME_RW_PRINFO_PRACT = 1 << 13,
759 NVME_RW_DTYPE_STREAMS = 1 << 4,
760 };
761
762 struct nvme_dsm_cmd {
763 __u8 opcode;
764 __u8 flags;
765 __u16 command_id;
766 __le32 nsid;
767 __u64 rsvd2[2];
768 union nvme_data_ptr dptr;
769 __le32 nr;
770 __le32 attributes;
771 __u32 rsvd12[4];
772 };
773
774 enum {
775 NVME_DSMGMT_IDR = 1 << 0,
776 NVME_DSMGMT_IDW = 1 << 1,
777 NVME_DSMGMT_AD = 1 << 2,
778 };
779
780 #define NVME_DSM_MAX_RANGES 256
781
782 struct nvme_dsm_range {
783 __le32 cattr;
784 __le32 nlb;
785 __le64 slba;
786 };
787
788 struct nvme_write_zeroes_cmd {
789 __u8 opcode;
790 __u8 flags;
791 __u16 command_id;
792 __le32 nsid;
793 __u64 rsvd2;
794 __le64 metadata;
795 union nvme_data_ptr dptr;
796 __le64 slba;
797 __le16 length;
798 __le16 control;
799 __le32 dsmgmt;
800 __le32 reftag;
801 __le16 apptag;
802 __le16 appmask;
803 };
804
805 /* Features */
806
807 struct nvme_feat_auto_pst {
808 __le64 entries[32];
809 };
810
811 enum {
812 NVME_HOST_MEM_ENABLE = (1 << 0),
813 NVME_HOST_MEM_RETURN = (1 << 1),
814 };
815
816 struct nvme_feat_host_behavior {
817 __u8 acre;
818 __u8 resv1[511];
819 };
820
821 enum {
822 NVME_ENABLE_ACRE = 1,
823 };
824
825 /* Admin commands */
826
827 enum nvme_admin_opcode {
828 nvme_admin_delete_sq = 0x00,
829 nvme_admin_create_sq = 0x01,
830 nvme_admin_get_log_page = 0x02,
831 nvme_admin_delete_cq = 0x04,
832 nvme_admin_create_cq = 0x05,
833 nvme_admin_identify = 0x06,
834 nvme_admin_abort_cmd = 0x08,
835 nvme_admin_set_features = 0x09,
836 nvme_admin_get_features = 0x0a,
837 nvme_admin_async_event = 0x0c,
838 nvme_admin_ns_mgmt = 0x0d,
839 nvme_admin_activate_fw = 0x10,
840 nvme_admin_download_fw = 0x11,
841 nvme_admin_dev_self_test = 0x14,
842 nvme_admin_ns_attach = 0x15,
843 nvme_admin_keep_alive = 0x18,
844 nvme_admin_directive_send = 0x19,
845 nvme_admin_directive_recv = 0x1a,
846 nvme_admin_virtual_mgmt = 0x1c,
847 nvme_admin_nvme_mi_send = 0x1d,
848 nvme_admin_nvme_mi_recv = 0x1e,
849 nvme_admin_dbbuf = 0x7C,
850 nvme_admin_format_nvm = 0x80,
851 nvme_admin_security_send = 0x81,
852 nvme_admin_security_recv = 0x82,
853 nvme_admin_sanitize_nvm = 0x84,
854 nvme_admin_get_lba_status = 0x86,
855 };
856
857 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
858 #define show_admin_opcode_name(val) \
859 __print_symbolic(val, \
860 nvme_admin_opcode_name(nvme_admin_delete_sq), \
861 nvme_admin_opcode_name(nvme_admin_create_sq), \
862 nvme_admin_opcode_name(nvme_admin_get_log_page), \
863 nvme_admin_opcode_name(nvme_admin_delete_cq), \
864 nvme_admin_opcode_name(nvme_admin_create_cq), \
865 nvme_admin_opcode_name(nvme_admin_identify), \
866 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
867 nvme_admin_opcode_name(nvme_admin_set_features), \
868 nvme_admin_opcode_name(nvme_admin_get_features), \
869 nvme_admin_opcode_name(nvme_admin_async_event), \
870 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
871 nvme_admin_opcode_name(nvme_admin_activate_fw), \
872 nvme_admin_opcode_name(nvme_admin_download_fw), \
873 nvme_admin_opcode_name(nvme_admin_ns_attach), \
874 nvme_admin_opcode_name(nvme_admin_keep_alive), \
875 nvme_admin_opcode_name(nvme_admin_directive_send), \
876 nvme_admin_opcode_name(nvme_admin_directive_recv), \
877 nvme_admin_opcode_name(nvme_admin_dbbuf), \
878 nvme_admin_opcode_name(nvme_admin_format_nvm), \
879 nvme_admin_opcode_name(nvme_admin_security_send), \
880 nvme_admin_opcode_name(nvme_admin_security_recv), \
881 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
882 nvme_admin_opcode_name(nvme_admin_get_lba_status))
883
884 enum {
885 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
886 NVME_CQ_IRQ_ENABLED = (1 << 1),
887 NVME_SQ_PRIO_URGENT = (0 << 1),
888 NVME_SQ_PRIO_HIGH = (1 << 1),
889 NVME_SQ_PRIO_MEDIUM = (2 << 1),
890 NVME_SQ_PRIO_LOW = (3 << 1),
891 NVME_FEAT_ARBITRATION = 0x01,
892 NVME_FEAT_POWER_MGMT = 0x02,
893 NVME_FEAT_LBA_RANGE = 0x03,
894 NVME_FEAT_TEMP_THRESH = 0x04,
895 NVME_FEAT_ERR_RECOVERY = 0x05,
896 NVME_FEAT_VOLATILE_WC = 0x06,
897 NVME_FEAT_NUM_QUEUES = 0x07,
898 NVME_FEAT_IRQ_COALESCE = 0x08,
899 NVME_FEAT_IRQ_CONFIG = 0x09,
900 NVME_FEAT_WRITE_ATOMIC = 0x0a,
901 NVME_FEAT_ASYNC_EVENT = 0x0b,
902 NVME_FEAT_AUTO_PST = 0x0c,
903 NVME_FEAT_HOST_MEM_BUF = 0x0d,
904 NVME_FEAT_TIMESTAMP = 0x0e,
905 NVME_FEAT_KATO = 0x0f,
906 NVME_FEAT_HCTM = 0x10,
907 NVME_FEAT_NOPSC = 0x11,
908 NVME_FEAT_RRL = 0x12,
909 NVME_FEAT_PLM_CONFIG = 0x13,
910 NVME_FEAT_PLM_WINDOW = 0x14,
911 NVME_FEAT_HOST_BEHAVIOR = 0x16,
912 NVME_FEAT_SANITIZE = 0x17,
913 NVME_FEAT_SW_PROGRESS = 0x80,
914 NVME_FEAT_HOST_ID = 0x81,
915 NVME_FEAT_RESV_MASK = 0x82,
916 NVME_FEAT_RESV_PERSIST = 0x83,
917 NVME_FEAT_WRITE_PROTECT = 0x84,
918 NVME_LOG_ERROR = 0x01,
919 NVME_LOG_SMART = 0x02,
920 NVME_LOG_FW_SLOT = 0x03,
921 NVME_LOG_CHANGED_NS = 0x04,
922 NVME_LOG_CMD_EFFECTS = 0x05,
923 NVME_LOG_DEVICE_SELF_TEST = 0x06,
924 NVME_LOG_TELEMETRY_HOST = 0x07,
925 NVME_LOG_TELEMETRY_CTRL = 0x08,
926 NVME_LOG_ENDURANCE_GROUP = 0x09,
927 NVME_LOG_ANA = 0x0c,
928 NVME_LOG_DISC = 0x70,
929 NVME_LOG_RESERVATION = 0x80,
930 NVME_FWACT_REPL = (0 << 3),
931 NVME_FWACT_REPL_ACTV = (1 << 3),
932 NVME_FWACT_ACTV = (2 << 3),
933 };
934
935 /* NVMe Namespace Write Protect State */
936 enum {
937 NVME_NS_NO_WRITE_PROTECT = 0,
938 NVME_NS_WRITE_PROTECT,
939 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
940 NVME_NS_WRITE_PROTECT_PERMANENT,
941 };
942
943 #define NVME_MAX_CHANGED_NAMESPACES 1024
944
945 struct nvme_identify {
946 __u8 opcode;
947 __u8 flags;
948 __u16 command_id;
949 __le32 nsid;
950 __u64 rsvd2[2];
951 union nvme_data_ptr dptr;
952 __u8 cns;
953 __u8 rsvd3;
954 __le16 ctrlid;
955 __u32 rsvd11[5];
956 };
957
958 #define NVME_IDENTIFY_DATA_SIZE 4096
959
960 struct nvme_features {
961 __u8 opcode;
962 __u8 flags;
963 __u16 command_id;
964 __le32 nsid;
965 __u64 rsvd2[2];
966 union nvme_data_ptr dptr;
967 __le32 fid;
968 __le32 dword11;
969 __le32 dword12;
970 __le32 dword13;
971 __le32 dword14;
972 __le32 dword15;
973 };
974
975 struct nvme_host_mem_buf_desc {
976 __le64 addr;
977 __le32 size;
978 __u32 rsvd;
979 };
980
981 struct nvme_create_cq {
982 __u8 opcode;
983 __u8 flags;
984 __u16 command_id;
985 __u32 rsvd1[5];
986 __le64 prp1;
987 __u64 rsvd8;
988 __le16 cqid;
989 __le16 qsize;
990 __le16 cq_flags;
991 __le16 irq_vector;
992 __u32 rsvd12[4];
993 };
994
995 struct nvme_create_sq {
996 __u8 opcode;
997 __u8 flags;
998 __u16 command_id;
999 __u32 rsvd1[5];
1000 __le64 prp1;
1001 __u64 rsvd8;
1002 __le16 sqid;
1003 __le16 qsize;
1004 __le16 sq_flags;
1005 __le16 cqid;
1006 __u32 rsvd12[4];
1007 };
1008
1009 struct nvme_delete_queue {
1010 __u8 opcode;
1011 __u8 flags;
1012 __u16 command_id;
1013 __u32 rsvd1[9];
1014 __le16 qid;
1015 __u16 rsvd10;
1016 __u32 rsvd11[5];
1017 };
1018
1019 struct nvme_abort_cmd {
1020 __u8 opcode;
1021 __u8 flags;
1022 __u16 command_id;
1023 __u32 rsvd1[9];
1024 __le16 sqid;
1025 __u16 cid;
1026 __u32 rsvd11[5];
1027 };
1028
1029 struct nvme_download_firmware {
1030 __u8 opcode;
1031 __u8 flags;
1032 __u16 command_id;
1033 __u32 rsvd1[5];
1034 union nvme_data_ptr dptr;
1035 __le32 numd;
1036 __le32 offset;
1037 __u32 rsvd12[4];
1038 };
1039
1040 struct nvme_format_cmd {
1041 __u8 opcode;
1042 __u8 flags;
1043 __u16 command_id;
1044 __le32 nsid;
1045 __u64 rsvd2[4];
1046 __le32 cdw10;
1047 __u32 rsvd11[5];
1048 };
1049
1050 struct nvme_get_log_page_command {
1051 __u8 opcode;
1052 __u8 flags;
1053 __u16 command_id;
1054 __le32 nsid;
1055 __u64 rsvd2[2];
1056 union nvme_data_ptr dptr;
1057 __u8 lid;
1058 __u8 lsp; /* upper 4 bits reserved */
1059 __le16 numdl;
1060 __le16 numdu;
1061 __u16 rsvd11;
1062 union {
1063 struct {
1064 __le32 lpol;
1065 __le32 lpou;
1066 };
1067 __le64 lpo;
1068 };
1069 __u32 rsvd14[2];
1070 };
1071
1072 struct nvme_directive_cmd {
1073 __u8 opcode;
1074 __u8 flags;
1075 __u16 command_id;
1076 __le32 nsid;
1077 __u64 rsvd2[2];
1078 union nvme_data_ptr dptr;
1079 __le32 numd;
1080 __u8 doper;
1081 __u8 dtype;
1082 __le16 dspec;
1083 __u8 endir;
1084 __u8 tdtype;
1085 __u16 rsvd15;
1086
1087 __u32 rsvd16[3];
1088 };
1089
1090 /*
1091 * Fabrics subcommands.
1092 */
1093 enum nvmf_fabrics_opcode {
1094 nvme_fabrics_command = 0x7f,
1095 };
1096
1097 enum nvmf_capsule_command {
1098 nvme_fabrics_type_property_set = 0x00,
1099 nvme_fabrics_type_connect = 0x01,
1100 nvme_fabrics_type_property_get = 0x04,
1101 };
1102
1103 #define nvme_fabrics_type_name(type) { type, #type }
1104 #define show_fabrics_type_name(type) \
1105 __print_symbolic(type, \
1106 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1107 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1108 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1109
1110 /*
1111 * If not fabrics command, fctype will be ignored.
1112 */
1113 #define show_opcode_name(qid, opcode, fctype) \
1114 ((opcode) == nvme_fabrics_command ? \
1115 show_fabrics_type_name(fctype) : \
1116 ((qid) ? \
1117 show_nvm_opcode_name(opcode) : \
1118 show_admin_opcode_name(opcode)))
1119
1120 struct nvmf_common_command {
1121 __u8 opcode;
1122 __u8 resv1;
1123 __u16 command_id;
1124 __u8 fctype;
1125 __u8 resv2[35];
1126 __u8 ts[24];
1127 };
1128
1129 /*
1130 * The legal cntlid range a NVMe Target will provide.
1131 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1132 * Devices based on earlier specs did not have the subsystem concept;
1133 * therefore, those devices had their cntlid value set to 0 as a result.
1134 */
1135 #define NVME_CNTLID_MIN 1
1136 #define NVME_CNTLID_MAX 0xffef
1137 #define NVME_CNTLID_DYNAMIC 0xffff
1138
1139 #define MAX_DISC_LOGS 255
1140
1141 /* Discovery log page entry */
1142 struct nvmf_disc_rsp_page_entry {
1143 __u8 trtype;
1144 __u8 adrfam;
1145 __u8 subtype;
1146 __u8 treq;
1147 __le16 portid;
1148 __le16 cntlid;
1149 __le16 asqsz;
1150 __u8 resv8[22];
1151 char trsvcid[NVMF_TRSVCID_SIZE];
1152 __u8 resv64[192];
1153 char subnqn[NVMF_NQN_FIELD_LEN];
1154 char traddr[NVMF_TRADDR_SIZE];
1155 union tsas {
1156 char common[NVMF_TSAS_SIZE];
1157 struct rdma {
1158 __u8 qptype;
1159 __u8 prtype;
1160 __u8 cms;
1161 __u8 resv3[5];
1162 __u16 pkey;
1163 __u8 resv10[246];
1164 } rdma;
1165 } tsas;
1166 };
1167
1168 /* Discovery log page header */
1169 struct nvmf_disc_rsp_page_hdr {
1170 __le64 genctr;
1171 __le64 numrec;
1172 __le16 recfmt;
1173 __u8 resv14[1006];
1174 struct nvmf_disc_rsp_page_entry entries[0];
1175 };
1176
1177 enum {
1178 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1179 };
1180
1181 struct nvmf_connect_command {
1182 __u8 opcode;
1183 __u8 resv1;
1184 __u16 command_id;
1185 __u8 fctype;
1186 __u8 resv2[19];
1187 union nvme_data_ptr dptr;
1188 __le16 recfmt;
1189 __le16 qid;
1190 __le16 sqsize;
1191 __u8 cattr;
1192 __u8 resv3;
1193 __le32 kato;
1194 __u8 resv4[12];
1195 };
1196
1197 struct nvmf_connect_data {
1198 uuid_t hostid;
1199 __le16 cntlid;
1200 char resv4[238];
1201 char subsysnqn[NVMF_NQN_FIELD_LEN];
1202 char hostnqn[NVMF_NQN_FIELD_LEN];
1203 char resv5[256];
1204 };
1205
1206 struct nvmf_property_set_command {
1207 __u8 opcode;
1208 __u8 resv1;
1209 __u16 command_id;
1210 __u8 fctype;
1211 __u8 resv2[35];
1212 __u8 attrib;
1213 __u8 resv3[3];
1214 __le32 offset;
1215 __le64 value;
1216 __u8 resv4[8];
1217 };
1218
1219 struct nvmf_property_get_command {
1220 __u8 opcode;
1221 __u8 resv1;
1222 __u16 command_id;
1223 __u8 fctype;
1224 __u8 resv2[35];
1225 __u8 attrib;
1226 __u8 resv3[3];
1227 __le32 offset;
1228 __u8 resv4[16];
1229 };
1230
1231 struct nvme_dbbuf {
1232 __u8 opcode;
1233 __u8 flags;
1234 __u16 command_id;
1235 __u32 rsvd1[5];
1236 __le64 prp1;
1237 __le64 prp2;
1238 __u32 rsvd12[6];
1239 };
1240
1241 struct streams_directive_params {
1242 __le16 msl;
1243 __le16 nssa;
1244 __le16 nsso;
1245 __u8 rsvd[10];
1246 __le32 sws;
1247 __le16 sgs;
1248 __le16 nsa;
1249 __le16 nso;
1250 __u8 rsvd2[6];
1251 };
1252
1253 struct nvme_command {
1254 union {
1255 struct nvme_common_command common;
1256 struct nvme_rw_command rw;
1257 struct nvme_identify identify;
1258 struct nvme_features features;
1259 struct nvme_create_cq create_cq;
1260 struct nvme_create_sq create_sq;
1261 struct nvme_delete_queue delete_queue;
1262 struct nvme_download_firmware dlfw;
1263 struct nvme_format_cmd format;
1264 struct nvme_dsm_cmd dsm;
1265 struct nvme_write_zeroes_cmd write_zeroes;
1266 struct nvme_abort_cmd abort;
1267 struct nvme_get_log_page_command get_log_page;
1268 struct nvmf_common_command fabrics;
1269 struct nvmf_connect_command connect;
1270 struct nvmf_property_set_command prop_set;
1271 struct nvmf_property_get_command prop_get;
1272 struct nvme_dbbuf dbbuf;
1273 struct nvme_directive_cmd directive;
1274 };
1275 };
1276
1277 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1278 {
1279 return cmd->common.opcode == nvme_fabrics_command;
1280 }
1281
1282 struct nvme_error_slot {
1283 __le64 error_count;
1284 __le16 sqid;
1285 __le16 cmdid;
1286 __le16 status_field;
1287 __le16 param_error_location;
1288 __le64 lba;
1289 __le32 nsid;
1290 __u8 vs;
1291 __u8 resv[3];
1292 __le64 cs;
1293 __u8 resv2[24];
1294 };
1295
1296 static inline bool nvme_is_write(struct nvme_command *cmd)
1297 {
1298 /*
1299 * What a mess...
1300 *
1301 * Why can't we simply have a Fabrics In and Fabrics out command?
1302 */
1303 if (unlikely(nvme_is_fabrics(cmd)))
1304 return cmd->fabrics.fctype & 1;
1305 return cmd->common.opcode & 1;
1306 }
1307
1308 enum {
1309 /*
1310 * Generic Command Status:
1311 */
1312 NVME_SC_SUCCESS = 0x0,
1313 NVME_SC_INVALID_OPCODE = 0x1,
1314 NVME_SC_INVALID_FIELD = 0x2,
1315 NVME_SC_CMDID_CONFLICT = 0x3,
1316 NVME_SC_DATA_XFER_ERROR = 0x4,
1317 NVME_SC_POWER_LOSS = 0x5,
1318 NVME_SC_INTERNAL = 0x6,
1319 NVME_SC_ABORT_REQ = 0x7,
1320 NVME_SC_ABORT_QUEUE = 0x8,
1321 NVME_SC_FUSED_FAIL = 0x9,
1322 NVME_SC_FUSED_MISSING = 0xa,
1323 NVME_SC_INVALID_NS = 0xb,
1324 NVME_SC_CMD_SEQ_ERROR = 0xc,
1325 NVME_SC_SGL_INVALID_LAST = 0xd,
1326 NVME_SC_SGL_INVALID_COUNT = 0xe,
1327 NVME_SC_SGL_INVALID_DATA = 0xf,
1328 NVME_SC_SGL_INVALID_METADATA = 0x10,
1329 NVME_SC_SGL_INVALID_TYPE = 0x11,
1330
1331 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1332 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1333
1334 NVME_SC_SANITIZE_FAILED = 0x1C,
1335 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1336
1337 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1338 NVME_SC_CMD_INTERRUPTED = 0x21,
1339
1340 NVME_SC_LBA_RANGE = 0x80,
1341 NVME_SC_CAP_EXCEEDED = 0x81,
1342 NVME_SC_NS_NOT_READY = 0x82,
1343 NVME_SC_RESERVATION_CONFLICT = 0x83,
1344
1345 /*
1346 * Command Specific Status:
1347 */
1348 NVME_SC_CQ_INVALID = 0x100,
1349 NVME_SC_QID_INVALID = 0x101,
1350 NVME_SC_QUEUE_SIZE = 0x102,
1351 NVME_SC_ABORT_LIMIT = 0x103,
1352 NVME_SC_ABORT_MISSING = 0x104,
1353 NVME_SC_ASYNC_LIMIT = 0x105,
1354 NVME_SC_FIRMWARE_SLOT = 0x106,
1355 NVME_SC_FIRMWARE_IMAGE = 0x107,
1356 NVME_SC_INVALID_VECTOR = 0x108,
1357 NVME_SC_INVALID_LOG_PAGE = 0x109,
1358 NVME_SC_INVALID_FORMAT = 0x10a,
1359 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1360 NVME_SC_INVALID_QUEUE = 0x10c,
1361 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1362 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1363 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1364 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1365 NVME_SC_FW_NEEDS_RESET = 0x111,
1366 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1367 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1368 NVME_SC_OVERLAPPING_RANGE = 0x114,
1369 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1370 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1371 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1372 NVME_SC_NS_IS_PRIVATE = 0x119,
1373 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1374 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1375 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1376 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1377 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1378
1379 /*
1380 * I/O Command Set Specific - NVM commands:
1381 */
1382 NVME_SC_BAD_ATTRIBUTES = 0x180,
1383 NVME_SC_INVALID_PI = 0x181,
1384 NVME_SC_READ_ONLY = 0x182,
1385 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1386
1387 /*
1388 * I/O Command Set Specific - Fabrics commands:
1389 */
1390 NVME_SC_CONNECT_FORMAT = 0x180,
1391 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1392 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1393 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1394 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1395
1396 NVME_SC_DISCOVERY_RESTART = 0x190,
1397 NVME_SC_AUTH_REQUIRED = 0x191,
1398
1399 /*
1400 * Media and Data Integrity Errors:
1401 */
1402 NVME_SC_WRITE_FAULT = 0x280,
1403 NVME_SC_READ_ERROR = 0x281,
1404 NVME_SC_GUARD_CHECK = 0x282,
1405 NVME_SC_APPTAG_CHECK = 0x283,
1406 NVME_SC_REFTAG_CHECK = 0x284,
1407 NVME_SC_COMPARE_FAILED = 0x285,
1408 NVME_SC_ACCESS_DENIED = 0x286,
1409 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1410
1411 /*
1412 * Path-related Errors:
1413 */
1414 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1415 NVME_SC_ANA_INACCESSIBLE = 0x302,
1416 NVME_SC_ANA_TRANSITION = 0x303,
1417 NVME_SC_HOST_PATH_ERROR = 0x370,
1418 NVME_SC_HOST_ABORTED_CMD = 0x371,
1419
1420 NVME_SC_CRD = 0x1800,
1421 NVME_SC_DNR = 0x4000,
1422 };
1423
1424 struct nvme_completion {
1425 /*
1426 * Used by Admin and Fabrics commands to return data:
1427 */
1428 union nvme_result {
1429 __le16 u16;
1430 __le32 u32;
1431 __le64 u64;
1432 } result;
1433 __le16 sq_head; /* how much of this queue may be reclaimed */
1434 __le16 sq_id; /* submission queue that generated this entry */
1435 __u16 command_id; /* of the command which completed */
1436 __le16 status; /* did the command fail, and if so, why? */
1437 };
1438
1439 #define NVME_VS(major, minor, tertiary) \
1440 (((major) << 16) | ((minor) << 8) | (tertiary))
1441
1442 #define NVME_MAJOR(ver) ((ver) >> 16)
1443 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1444 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1445
1446 #endif /* _LINUX_NVME_H */
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