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nvme: expose cntrltype and dctype through sysfs
[mirror_ubuntu-jammy-kernel.git] / include / linux / nvme.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/types.h>
11 #include <linux/uuid.h>
12
13 /* NQN names in commands fields specified one size */
14 #define NVMF_NQN_FIELD_LEN 256
15
16 /* However the max length of a qualified name is another size */
17 #define NVMF_NQN_SIZE 223
18
19 #define NVMF_TRSVCID_SIZE 32
20 #define NVMF_TRADDR_SIZE 256
21 #define NVMF_TSAS_SIZE 256
22
23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
24
25 #define NVME_RDMA_IP_PORT 4420
26
27 #define NVME_NSID_ALL 0xffffffff
28
29 enum nvme_subsys_type {
30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
31 NVME_NQN_NVME = 2, /* NVME type target subsystem */
32 };
33
34 enum nvme_ctrl_type {
35 NVME_CTRL_IO = 1, /* I/O controller */
36 NVME_CTRL_DISC = 2, /* Discovery controller */
37 NVME_CTRL_ADMIN = 3, /* Administrative controller */
38 };
39
40 enum nvme_dctype {
41 NVME_DCTYPE_NOT_REPORTED = 0,
42 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
43 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
44 };
45
46 /* Address Family codes for Discovery Log Page entry ADRFAM field */
47 enum {
48 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
49 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
50 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
51 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
52 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
53 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
54 NVMF_ADDR_FAMILY_MAX,
55 };
56
57 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
58 enum {
59 NVMF_TRTYPE_RDMA = 1, /* RDMA */
60 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
61 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
62 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
63 NVMF_TRTYPE_MAX,
64 };
65
66 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
67 enum {
68 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
69 NVMF_TREQ_REQUIRED = 1, /* Required */
70 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
71 #define NVME_TREQ_SECURE_CHANNEL_MASK \
72 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
73
74 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
75 };
76
77 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
78 * RDMA_QPTYPE field
79 */
80 enum {
81 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
82 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
83 };
84
85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
86 * RDMA_QPTYPE field
87 */
88 enum {
89 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
90 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
91 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
92 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
93 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
94 };
95
96 /* RDMA Connection Management Service Type codes for Discovery Log Page
97 * entry TSAS RDMA_CMS field
98 */
99 enum {
100 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
101 };
102
103 #define NVME_AQ_DEPTH 32
104 #define NVME_NR_AEN_COMMANDS 1
105 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
106
107 /*
108 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
109 * NVM-Express 1.2 specification, section 4.1.2.
110 */
111 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
112
113 enum {
114 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
115 NVME_REG_VS = 0x0008, /* Version */
116 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
117 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
118 NVME_REG_CC = 0x0014, /* Controller Configuration */
119 NVME_REG_CSTS = 0x001c, /* Controller Status */
120 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
121 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
122 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
123 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
124 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
125 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
126 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
127 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
128 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
129 * Location
130 */
131 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
132 * Space Control
133 */
134 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
135 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
136 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
137 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
138 * Buffer Size
139 */
140 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
141 * Write Throughput
142 */
143 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
144 };
145
146 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
147 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
148 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
149 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
150 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
151 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
152 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
153 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
154
155 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
156 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
157
158 enum {
159 NVME_CMBSZ_SQS = 1 << 0,
160 NVME_CMBSZ_CQS = 1 << 1,
161 NVME_CMBSZ_LISTS = 1 << 2,
162 NVME_CMBSZ_RDS = 1 << 3,
163 NVME_CMBSZ_WDS = 1 << 4,
164
165 NVME_CMBSZ_SZ_SHIFT = 12,
166 NVME_CMBSZ_SZ_MASK = 0xfffff,
167
168 NVME_CMBSZ_SZU_SHIFT = 8,
169 NVME_CMBSZ_SZU_MASK = 0xf,
170 };
171
172 /*
173 * Submission and Completion Queue Entry Sizes for the NVM command set.
174 * (In bytes and specified as a power of two (2^n)).
175 */
176 #define NVME_ADM_SQES 6
177 #define NVME_NVM_IOSQES 6
178 #define NVME_NVM_IOCQES 4
179
180 enum {
181 NVME_CC_ENABLE = 1 << 0,
182 NVME_CC_EN_SHIFT = 0,
183 NVME_CC_CSS_SHIFT = 4,
184 NVME_CC_MPS_SHIFT = 7,
185 NVME_CC_AMS_SHIFT = 11,
186 NVME_CC_SHN_SHIFT = 14,
187 NVME_CC_IOSQES_SHIFT = 16,
188 NVME_CC_IOCQES_SHIFT = 20,
189 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
190 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
191 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
192 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
193 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
194 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
195 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
196 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
197 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
198 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
199 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
200 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
201 NVME_CAP_CSS_NVM = 1 << 0,
202 NVME_CAP_CSS_CSI = 1 << 6,
203 NVME_CSTS_RDY = 1 << 0,
204 NVME_CSTS_CFS = 1 << 1,
205 NVME_CSTS_NSSRO = 1 << 4,
206 NVME_CSTS_PP = 1 << 5,
207 NVME_CSTS_SHST_NORMAL = 0 << 2,
208 NVME_CSTS_SHST_OCCUR = 1 << 2,
209 NVME_CSTS_SHST_CMPLT = 2 << 2,
210 NVME_CSTS_SHST_MASK = 3 << 2,
211 NVME_CMBMSC_CRE = 1 << 0,
212 NVME_CMBMSC_CMSE = 1 << 1,
213 };
214
215 struct nvme_id_power_state {
216 __le16 max_power; /* centiwatts */
217 __u8 rsvd2;
218 __u8 flags;
219 __le32 entry_lat; /* microseconds */
220 __le32 exit_lat; /* microseconds */
221 __u8 read_tput;
222 __u8 read_lat;
223 __u8 write_tput;
224 __u8 write_lat;
225 __le16 idle_power;
226 __u8 idle_scale;
227 __u8 rsvd19;
228 __le16 active_power;
229 __u8 active_work_scale;
230 __u8 rsvd23[9];
231 };
232
233 enum {
234 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
235 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
236 };
237
238 enum nvme_ctrl_attr {
239 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
240 NVME_CTRL_ATTR_TBKAS = (1 << 6),
241 };
242
243 struct nvme_id_ctrl {
244 __le16 vid;
245 __le16 ssvid;
246 char sn[20];
247 char mn[40];
248 char fr[8];
249 __u8 rab;
250 __u8 ieee[3];
251 __u8 cmic;
252 __u8 mdts;
253 __le16 cntlid;
254 __le32 ver;
255 __le32 rtd3r;
256 __le32 rtd3e;
257 __le32 oaes;
258 __le32 ctratt;
259 __u8 rsvd100[11];
260 __u8 cntrltype;
261 __u8 fguid[16];
262 __le16 crdt1;
263 __le16 crdt2;
264 __le16 crdt3;
265 __u8 rsvd134[122];
266 __le16 oacs;
267 __u8 acl;
268 __u8 aerl;
269 __u8 frmw;
270 __u8 lpa;
271 __u8 elpe;
272 __u8 npss;
273 __u8 avscc;
274 __u8 apsta;
275 __le16 wctemp;
276 __le16 cctemp;
277 __le16 mtfa;
278 __le32 hmpre;
279 __le32 hmmin;
280 __u8 tnvmcap[16];
281 __u8 unvmcap[16];
282 __le32 rpmbs;
283 __le16 edstt;
284 __u8 dsto;
285 __u8 fwug;
286 __le16 kas;
287 __le16 hctma;
288 __le16 mntmt;
289 __le16 mxtmt;
290 __le32 sanicap;
291 __le32 hmminds;
292 __le16 hmmaxd;
293 __u8 rsvd338[4];
294 __u8 anatt;
295 __u8 anacap;
296 __le32 anagrpmax;
297 __le32 nanagrpid;
298 __u8 rsvd352[160];
299 __u8 sqes;
300 __u8 cqes;
301 __le16 maxcmd;
302 __le32 nn;
303 __le16 oncs;
304 __le16 fuses;
305 __u8 fna;
306 __u8 vwc;
307 __le16 awun;
308 __le16 awupf;
309 __u8 nvscc;
310 __u8 nwpc;
311 __le16 acwu;
312 __u8 rsvd534[2];
313 __le32 sgls;
314 __le32 mnan;
315 __u8 rsvd544[224];
316 char subnqn[256];
317 __u8 rsvd1024[768];
318 __le32 ioccsz;
319 __le32 iorcsz;
320 __le16 icdoff;
321 __u8 ctrattr;
322 __u8 msdbd;
323 __u8 rsvd1804[2];
324 __u8 dctype;
325 __u8 rsvd1807[241];
326 struct nvme_id_power_state psd[32];
327 __u8 vs[1024];
328 };
329
330 enum {
331 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
332 NVME_CTRL_CMIC_ANA = 1 << 3,
333 NVME_CTRL_ONCS_COMPARE = 1 << 0,
334 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
335 NVME_CTRL_ONCS_DSM = 1 << 2,
336 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
337 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
338 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
339 NVME_CTRL_VWC_PRESENT = 1 << 0,
340 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
341 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
342 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
343 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
344 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
345 NVME_CTRL_CTRATT_128_ID = 1 << 0,
346 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
347 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
348 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
349 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
350 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
351 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
352 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
353 };
354
355 struct nvme_lbaf {
356 __le16 ms;
357 __u8 ds;
358 __u8 rp;
359 };
360
361 struct nvme_id_ns {
362 __le64 nsze;
363 __le64 ncap;
364 __le64 nuse;
365 __u8 nsfeat;
366 __u8 nlbaf;
367 __u8 flbas;
368 __u8 mc;
369 __u8 dpc;
370 __u8 dps;
371 __u8 nmic;
372 __u8 rescap;
373 __u8 fpi;
374 __u8 dlfeat;
375 __le16 nawun;
376 __le16 nawupf;
377 __le16 nacwu;
378 __le16 nabsn;
379 __le16 nabo;
380 __le16 nabspf;
381 __le16 noiob;
382 __u8 nvmcap[16];
383 __le16 npwg;
384 __le16 npwa;
385 __le16 npdg;
386 __le16 npda;
387 __le16 nows;
388 __u8 rsvd74[18];
389 __le32 anagrpid;
390 __u8 rsvd96[3];
391 __u8 nsattr;
392 __le16 nvmsetid;
393 __le16 endgid;
394 __u8 nguid[16];
395 __u8 eui64[8];
396 struct nvme_lbaf lbaf[16];
397 __u8 rsvd192[192];
398 __u8 vs[3712];
399 };
400
401 struct nvme_zns_lbafe {
402 __le64 zsze;
403 __u8 zdes;
404 __u8 rsvd9[7];
405 };
406
407 struct nvme_id_ns_zns {
408 __le16 zoc;
409 __le16 ozcs;
410 __le32 mar;
411 __le32 mor;
412 __le32 rrl;
413 __le32 frl;
414 __u8 rsvd20[2796];
415 struct nvme_zns_lbafe lbafe[16];
416 __u8 rsvd3072[768];
417 __u8 vs[256];
418 };
419
420 struct nvme_id_ctrl_zns {
421 __u8 zasl;
422 __u8 rsvd1[4095];
423 };
424
425 struct nvme_id_ctrl_nvm {
426 __u8 vsl;
427 __u8 wzsl;
428 __u8 wusl;
429 __u8 dmrl;
430 __le32 dmrsl;
431 __le64 dmsl;
432 __u8 rsvd16[4080];
433 };
434
435 enum {
436 NVME_ID_CNS_NS = 0x00,
437 NVME_ID_CNS_CTRL = 0x01,
438 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
439 NVME_ID_CNS_NS_DESC_LIST = 0x03,
440 NVME_ID_CNS_CS_NS = 0x05,
441 NVME_ID_CNS_CS_CTRL = 0x06,
442 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
443 NVME_ID_CNS_NS_PRESENT = 0x11,
444 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
445 NVME_ID_CNS_CTRL_LIST = 0x13,
446 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
447 NVME_ID_CNS_NS_GRANULARITY = 0x16,
448 NVME_ID_CNS_UUID_LIST = 0x17,
449 };
450
451 enum {
452 NVME_CSI_NVM = 0,
453 NVME_CSI_ZNS = 2,
454 };
455
456 enum {
457 NVME_DIR_IDENTIFY = 0x00,
458 NVME_DIR_STREAMS = 0x01,
459 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
460 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
461 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
462 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
463 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
464 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
465 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
466 NVME_DIR_ENDIR = 0x01,
467 };
468
469 enum {
470 NVME_NS_FEAT_THIN = 1 << 0,
471 NVME_NS_FEAT_ATOMICS = 1 << 1,
472 NVME_NS_FEAT_IO_OPT = 1 << 4,
473 NVME_NS_ATTR_RO = 1 << 0,
474 NVME_NS_FLBAS_LBA_MASK = 0xf,
475 NVME_NS_FLBAS_META_EXT = 0x10,
476 NVME_NS_NMIC_SHARED = 1 << 0,
477 NVME_LBAF_RP_BEST = 0,
478 NVME_LBAF_RP_BETTER = 1,
479 NVME_LBAF_RP_GOOD = 2,
480 NVME_LBAF_RP_DEGRADED = 3,
481 NVME_NS_DPC_PI_LAST = 1 << 4,
482 NVME_NS_DPC_PI_FIRST = 1 << 3,
483 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
484 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
485 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
486 NVME_NS_DPS_PI_FIRST = 1 << 3,
487 NVME_NS_DPS_PI_MASK = 0x7,
488 NVME_NS_DPS_PI_TYPE1 = 1,
489 NVME_NS_DPS_PI_TYPE2 = 2,
490 NVME_NS_DPS_PI_TYPE3 = 3,
491 };
492
493 /* Identify Namespace Metadata Capabilities (MC): */
494 enum {
495 NVME_MC_EXTENDED_LBA = (1 << 0),
496 NVME_MC_METADATA_PTR = (1 << 1),
497 };
498
499 struct nvme_ns_id_desc {
500 __u8 nidt;
501 __u8 nidl;
502 __le16 reserved;
503 };
504
505 #define NVME_NIDT_EUI64_LEN 8
506 #define NVME_NIDT_NGUID_LEN 16
507 #define NVME_NIDT_UUID_LEN 16
508 #define NVME_NIDT_CSI_LEN 1
509
510 enum {
511 NVME_NIDT_EUI64 = 0x01,
512 NVME_NIDT_NGUID = 0x02,
513 NVME_NIDT_UUID = 0x03,
514 NVME_NIDT_CSI = 0x04,
515 };
516
517 struct nvme_smart_log {
518 __u8 critical_warning;
519 __u8 temperature[2];
520 __u8 avail_spare;
521 __u8 spare_thresh;
522 __u8 percent_used;
523 __u8 endu_grp_crit_warn_sumry;
524 __u8 rsvd7[25];
525 __u8 data_units_read[16];
526 __u8 data_units_written[16];
527 __u8 host_reads[16];
528 __u8 host_writes[16];
529 __u8 ctrl_busy_time[16];
530 __u8 power_cycles[16];
531 __u8 power_on_hours[16];
532 __u8 unsafe_shutdowns[16];
533 __u8 media_errors[16];
534 __u8 num_err_log_entries[16];
535 __le32 warning_temp_time;
536 __le32 critical_comp_time;
537 __le16 temp_sensor[8];
538 __le32 thm_temp1_trans_count;
539 __le32 thm_temp2_trans_count;
540 __le32 thm_temp1_total_time;
541 __le32 thm_temp2_total_time;
542 __u8 rsvd232[280];
543 };
544
545 struct nvme_fw_slot_info_log {
546 __u8 afi;
547 __u8 rsvd1[7];
548 __le64 frs[7];
549 __u8 rsvd64[448];
550 };
551
552 enum {
553 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
554 NVME_CMD_EFFECTS_LBCC = 1 << 1,
555 NVME_CMD_EFFECTS_NCC = 1 << 2,
556 NVME_CMD_EFFECTS_NIC = 1 << 3,
557 NVME_CMD_EFFECTS_CCC = 1 << 4,
558 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
559 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
560 };
561
562 struct nvme_effects_log {
563 __le32 acs[256];
564 __le32 iocs[256];
565 __u8 resv[2048];
566 };
567
568 enum nvme_ana_state {
569 NVME_ANA_OPTIMIZED = 0x01,
570 NVME_ANA_NONOPTIMIZED = 0x02,
571 NVME_ANA_INACCESSIBLE = 0x03,
572 NVME_ANA_PERSISTENT_LOSS = 0x04,
573 NVME_ANA_CHANGE = 0x0f,
574 };
575
576 struct nvme_ana_group_desc {
577 __le32 grpid;
578 __le32 nnsids;
579 __le64 chgcnt;
580 __u8 state;
581 __u8 rsvd17[15];
582 __le32 nsids[];
583 };
584
585 /* flag for the log specific field of the ANA log */
586 #define NVME_ANA_LOG_RGO (1 << 0)
587
588 struct nvme_ana_rsp_hdr {
589 __le64 chgcnt;
590 __le16 ngrps;
591 __le16 rsvd10[3];
592 };
593
594 struct nvme_zone_descriptor {
595 __u8 zt;
596 __u8 zs;
597 __u8 za;
598 __u8 rsvd3[5];
599 __le64 zcap;
600 __le64 zslba;
601 __le64 wp;
602 __u8 rsvd32[32];
603 };
604
605 enum {
606 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
607 };
608
609 struct nvme_zone_report {
610 __le64 nr_zones;
611 __u8 resv8[56];
612 struct nvme_zone_descriptor entries[];
613 };
614
615 enum {
616 NVME_SMART_CRIT_SPARE = 1 << 0,
617 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
618 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
619 NVME_SMART_CRIT_MEDIA = 1 << 3,
620 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
621 };
622
623 enum {
624 NVME_AER_ERROR = 0,
625 NVME_AER_SMART = 1,
626 NVME_AER_NOTICE = 2,
627 NVME_AER_CSS = 6,
628 NVME_AER_VS = 7,
629 };
630
631 enum {
632 NVME_AER_NOTICE_NS_CHANGED = 0x00,
633 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
634 NVME_AER_NOTICE_ANA = 0x03,
635 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
636 };
637
638 enum {
639 NVME_AEN_BIT_NS_ATTR = 8,
640 NVME_AEN_BIT_FW_ACT = 9,
641 NVME_AEN_BIT_ANA_CHANGE = 11,
642 NVME_AEN_BIT_DISC_CHANGE = 31,
643 };
644
645 enum {
646 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
647 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
648 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
649 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
650 };
651
652 struct nvme_lba_range_type {
653 __u8 type;
654 __u8 attributes;
655 __u8 rsvd2[14];
656 __le64 slba;
657 __le64 nlb;
658 __u8 guid[16];
659 __u8 rsvd48[16];
660 };
661
662 enum {
663 NVME_LBART_TYPE_FS = 0x01,
664 NVME_LBART_TYPE_RAID = 0x02,
665 NVME_LBART_TYPE_CACHE = 0x03,
666 NVME_LBART_TYPE_SWAP = 0x04,
667
668 NVME_LBART_ATTRIB_TEMP = 1 << 0,
669 NVME_LBART_ATTRIB_HIDE = 1 << 1,
670 };
671
672 struct nvme_reservation_status {
673 __le32 gen;
674 __u8 rtype;
675 __u8 regctl[2];
676 __u8 resv5[2];
677 __u8 ptpls;
678 __u8 resv10[13];
679 struct {
680 __le16 cntlid;
681 __u8 rcsts;
682 __u8 resv3[5];
683 __le64 hostid;
684 __le64 rkey;
685 } regctl_ds[];
686 };
687
688 enum nvme_async_event_type {
689 NVME_AER_TYPE_ERROR = 0,
690 NVME_AER_TYPE_SMART = 1,
691 NVME_AER_TYPE_NOTICE = 2,
692 };
693
694 /* I/O commands */
695
696 enum nvme_opcode {
697 nvme_cmd_flush = 0x00,
698 nvme_cmd_write = 0x01,
699 nvme_cmd_read = 0x02,
700 nvme_cmd_write_uncor = 0x04,
701 nvme_cmd_compare = 0x05,
702 nvme_cmd_write_zeroes = 0x08,
703 nvme_cmd_dsm = 0x09,
704 nvme_cmd_verify = 0x0c,
705 nvme_cmd_resv_register = 0x0d,
706 nvme_cmd_resv_report = 0x0e,
707 nvme_cmd_resv_acquire = 0x11,
708 nvme_cmd_resv_release = 0x15,
709 nvme_cmd_zone_mgmt_send = 0x79,
710 nvme_cmd_zone_mgmt_recv = 0x7a,
711 nvme_cmd_zone_append = 0x7d,
712 };
713
714 #define nvme_opcode_name(opcode) { opcode, #opcode }
715 #define show_nvm_opcode_name(val) \
716 __print_symbolic(val, \
717 nvme_opcode_name(nvme_cmd_flush), \
718 nvme_opcode_name(nvme_cmd_write), \
719 nvme_opcode_name(nvme_cmd_read), \
720 nvme_opcode_name(nvme_cmd_write_uncor), \
721 nvme_opcode_name(nvme_cmd_compare), \
722 nvme_opcode_name(nvme_cmd_write_zeroes), \
723 nvme_opcode_name(nvme_cmd_dsm), \
724 nvme_opcode_name(nvme_cmd_resv_register), \
725 nvme_opcode_name(nvme_cmd_resv_report), \
726 nvme_opcode_name(nvme_cmd_resv_acquire), \
727 nvme_opcode_name(nvme_cmd_resv_release), \
728 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
729 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
730 nvme_opcode_name(nvme_cmd_zone_append))
731
732
733
734 /*
735 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
736 *
737 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
738 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
739 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
740 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
741 * request subtype
742 */
743 enum {
744 NVME_SGL_FMT_ADDRESS = 0x00,
745 NVME_SGL_FMT_OFFSET = 0x01,
746 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
747 NVME_SGL_FMT_INVALIDATE = 0x0f,
748 };
749
750 /*
751 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
752 *
753 * For struct nvme_sgl_desc:
754 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
755 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
756 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
757 *
758 * For struct nvme_keyed_sgl_desc:
759 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
760 *
761 * Transport-specific SGL types:
762 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
763 */
764 enum {
765 NVME_SGL_FMT_DATA_DESC = 0x00,
766 NVME_SGL_FMT_SEG_DESC = 0x02,
767 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
768 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
769 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
770 };
771
772 struct nvme_sgl_desc {
773 __le64 addr;
774 __le32 length;
775 __u8 rsvd[3];
776 __u8 type;
777 };
778
779 struct nvme_keyed_sgl_desc {
780 __le64 addr;
781 __u8 length[3];
782 __u8 key[4];
783 __u8 type;
784 };
785
786 union nvme_data_ptr {
787 struct {
788 __le64 prp1;
789 __le64 prp2;
790 };
791 struct nvme_sgl_desc sgl;
792 struct nvme_keyed_sgl_desc ksgl;
793 };
794
795 /*
796 * Lowest two bits of our flags field (FUSE field in the spec):
797 *
798 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
799 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
800 *
801 * Highest two bits in our flags field (PSDT field in the spec):
802 *
803 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
804 * If used, MPTR contains addr of single physical buffer (byte aligned).
805 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
806 * If used, MPTR contains an address of an SGL segment containing
807 * exactly 1 SGL descriptor (qword aligned).
808 */
809 enum {
810 NVME_CMD_FUSE_FIRST = (1 << 0),
811 NVME_CMD_FUSE_SECOND = (1 << 1),
812
813 NVME_CMD_SGL_METABUF = (1 << 6),
814 NVME_CMD_SGL_METASEG = (1 << 7),
815 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
816 };
817
818 struct nvme_common_command {
819 __u8 opcode;
820 __u8 flags;
821 __u16 command_id;
822 __le32 nsid;
823 __le32 cdw2[2];
824 __le64 metadata;
825 union nvme_data_ptr dptr;
826 __le32 cdw10;
827 __le32 cdw11;
828 __le32 cdw12;
829 __le32 cdw13;
830 __le32 cdw14;
831 __le32 cdw15;
832 };
833
834 struct nvme_rw_command {
835 __u8 opcode;
836 __u8 flags;
837 __u16 command_id;
838 __le32 nsid;
839 __u64 rsvd2;
840 __le64 metadata;
841 union nvme_data_ptr dptr;
842 __le64 slba;
843 __le16 length;
844 __le16 control;
845 __le32 dsmgmt;
846 __le32 reftag;
847 __le16 apptag;
848 __le16 appmask;
849 };
850
851 enum {
852 NVME_RW_LR = 1 << 15,
853 NVME_RW_FUA = 1 << 14,
854 NVME_RW_APPEND_PIREMAP = 1 << 9,
855 NVME_RW_DSM_FREQ_UNSPEC = 0,
856 NVME_RW_DSM_FREQ_TYPICAL = 1,
857 NVME_RW_DSM_FREQ_RARE = 2,
858 NVME_RW_DSM_FREQ_READS = 3,
859 NVME_RW_DSM_FREQ_WRITES = 4,
860 NVME_RW_DSM_FREQ_RW = 5,
861 NVME_RW_DSM_FREQ_ONCE = 6,
862 NVME_RW_DSM_FREQ_PREFETCH = 7,
863 NVME_RW_DSM_FREQ_TEMP = 8,
864 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
865 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
866 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
867 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
868 NVME_RW_DSM_SEQ_REQ = 1 << 6,
869 NVME_RW_DSM_COMPRESSED = 1 << 7,
870 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
871 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
872 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
873 NVME_RW_PRINFO_PRACT = 1 << 13,
874 NVME_RW_DTYPE_STREAMS = 1 << 4,
875 };
876
877 struct nvme_dsm_cmd {
878 __u8 opcode;
879 __u8 flags;
880 __u16 command_id;
881 __le32 nsid;
882 __u64 rsvd2[2];
883 union nvme_data_ptr dptr;
884 __le32 nr;
885 __le32 attributes;
886 __u32 rsvd12[4];
887 };
888
889 enum {
890 NVME_DSMGMT_IDR = 1 << 0,
891 NVME_DSMGMT_IDW = 1 << 1,
892 NVME_DSMGMT_AD = 1 << 2,
893 };
894
895 #define NVME_DSM_MAX_RANGES 256
896
897 struct nvme_dsm_range {
898 __le32 cattr;
899 __le32 nlb;
900 __le64 slba;
901 };
902
903 struct nvme_write_zeroes_cmd {
904 __u8 opcode;
905 __u8 flags;
906 __u16 command_id;
907 __le32 nsid;
908 __u64 rsvd2;
909 __le64 metadata;
910 union nvme_data_ptr dptr;
911 __le64 slba;
912 __le16 length;
913 __le16 control;
914 __le32 dsmgmt;
915 __le32 reftag;
916 __le16 apptag;
917 __le16 appmask;
918 };
919
920 enum nvme_zone_mgmt_action {
921 NVME_ZONE_CLOSE = 0x1,
922 NVME_ZONE_FINISH = 0x2,
923 NVME_ZONE_OPEN = 0x3,
924 NVME_ZONE_RESET = 0x4,
925 NVME_ZONE_OFFLINE = 0x5,
926 NVME_ZONE_SET_DESC_EXT = 0x10,
927 };
928
929 struct nvme_zone_mgmt_send_cmd {
930 __u8 opcode;
931 __u8 flags;
932 __u16 command_id;
933 __le32 nsid;
934 __le32 cdw2[2];
935 __le64 metadata;
936 union nvme_data_ptr dptr;
937 __le64 slba;
938 __le32 cdw12;
939 __u8 zsa;
940 __u8 select_all;
941 __u8 rsvd13[2];
942 __le32 cdw14[2];
943 };
944
945 struct nvme_zone_mgmt_recv_cmd {
946 __u8 opcode;
947 __u8 flags;
948 __u16 command_id;
949 __le32 nsid;
950 __le64 rsvd2[2];
951 union nvme_data_ptr dptr;
952 __le64 slba;
953 __le32 numd;
954 __u8 zra;
955 __u8 zrasf;
956 __u8 pr;
957 __u8 rsvd13;
958 __le32 cdw14[2];
959 };
960
961 enum {
962 NVME_ZRA_ZONE_REPORT = 0,
963 NVME_ZRASF_ZONE_REPORT_ALL = 0,
964 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
965 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
966 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
967 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
968 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
969 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
970 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
971 NVME_REPORT_ZONE_PARTIAL = 1,
972 };
973
974 /* Features */
975
976 enum {
977 NVME_TEMP_THRESH_MASK = 0xffff,
978 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
979 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
980 };
981
982 struct nvme_feat_auto_pst {
983 __le64 entries[32];
984 };
985
986 enum {
987 NVME_HOST_MEM_ENABLE = (1 << 0),
988 NVME_HOST_MEM_RETURN = (1 << 1),
989 };
990
991 struct nvme_feat_host_behavior {
992 __u8 acre;
993 __u8 resv1[511];
994 };
995
996 enum {
997 NVME_ENABLE_ACRE = 1,
998 };
999
1000 /* Admin commands */
1001
1002 enum nvme_admin_opcode {
1003 nvme_admin_delete_sq = 0x00,
1004 nvme_admin_create_sq = 0x01,
1005 nvme_admin_get_log_page = 0x02,
1006 nvme_admin_delete_cq = 0x04,
1007 nvme_admin_create_cq = 0x05,
1008 nvme_admin_identify = 0x06,
1009 nvme_admin_abort_cmd = 0x08,
1010 nvme_admin_set_features = 0x09,
1011 nvme_admin_get_features = 0x0a,
1012 nvme_admin_async_event = 0x0c,
1013 nvme_admin_ns_mgmt = 0x0d,
1014 nvme_admin_activate_fw = 0x10,
1015 nvme_admin_download_fw = 0x11,
1016 nvme_admin_dev_self_test = 0x14,
1017 nvme_admin_ns_attach = 0x15,
1018 nvme_admin_keep_alive = 0x18,
1019 nvme_admin_directive_send = 0x19,
1020 nvme_admin_directive_recv = 0x1a,
1021 nvme_admin_virtual_mgmt = 0x1c,
1022 nvme_admin_nvme_mi_send = 0x1d,
1023 nvme_admin_nvme_mi_recv = 0x1e,
1024 nvme_admin_dbbuf = 0x7C,
1025 nvme_admin_format_nvm = 0x80,
1026 nvme_admin_security_send = 0x81,
1027 nvme_admin_security_recv = 0x82,
1028 nvme_admin_sanitize_nvm = 0x84,
1029 nvme_admin_get_lba_status = 0x86,
1030 nvme_admin_vendor_start = 0xC0,
1031 };
1032
1033 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1034 #define show_admin_opcode_name(val) \
1035 __print_symbolic(val, \
1036 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1037 nvme_admin_opcode_name(nvme_admin_create_sq), \
1038 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1039 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1040 nvme_admin_opcode_name(nvme_admin_create_cq), \
1041 nvme_admin_opcode_name(nvme_admin_identify), \
1042 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1043 nvme_admin_opcode_name(nvme_admin_set_features), \
1044 nvme_admin_opcode_name(nvme_admin_get_features), \
1045 nvme_admin_opcode_name(nvme_admin_async_event), \
1046 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1047 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1048 nvme_admin_opcode_name(nvme_admin_download_fw), \
1049 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1050 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1051 nvme_admin_opcode_name(nvme_admin_directive_send), \
1052 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1053 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1054 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1055 nvme_admin_opcode_name(nvme_admin_security_send), \
1056 nvme_admin_opcode_name(nvme_admin_security_recv), \
1057 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1058 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1059
1060 enum {
1061 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1062 NVME_CQ_IRQ_ENABLED = (1 << 1),
1063 NVME_SQ_PRIO_URGENT = (0 << 1),
1064 NVME_SQ_PRIO_HIGH = (1 << 1),
1065 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1066 NVME_SQ_PRIO_LOW = (3 << 1),
1067 NVME_FEAT_ARBITRATION = 0x01,
1068 NVME_FEAT_POWER_MGMT = 0x02,
1069 NVME_FEAT_LBA_RANGE = 0x03,
1070 NVME_FEAT_TEMP_THRESH = 0x04,
1071 NVME_FEAT_ERR_RECOVERY = 0x05,
1072 NVME_FEAT_VOLATILE_WC = 0x06,
1073 NVME_FEAT_NUM_QUEUES = 0x07,
1074 NVME_FEAT_IRQ_COALESCE = 0x08,
1075 NVME_FEAT_IRQ_CONFIG = 0x09,
1076 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1077 NVME_FEAT_ASYNC_EVENT = 0x0b,
1078 NVME_FEAT_AUTO_PST = 0x0c,
1079 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1080 NVME_FEAT_TIMESTAMP = 0x0e,
1081 NVME_FEAT_KATO = 0x0f,
1082 NVME_FEAT_HCTM = 0x10,
1083 NVME_FEAT_NOPSC = 0x11,
1084 NVME_FEAT_RRL = 0x12,
1085 NVME_FEAT_PLM_CONFIG = 0x13,
1086 NVME_FEAT_PLM_WINDOW = 0x14,
1087 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1088 NVME_FEAT_SANITIZE = 0x17,
1089 NVME_FEAT_SW_PROGRESS = 0x80,
1090 NVME_FEAT_HOST_ID = 0x81,
1091 NVME_FEAT_RESV_MASK = 0x82,
1092 NVME_FEAT_RESV_PERSIST = 0x83,
1093 NVME_FEAT_WRITE_PROTECT = 0x84,
1094 NVME_FEAT_VENDOR_START = 0xC0,
1095 NVME_FEAT_VENDOR_END = 0xFF,
1096 NVME_LOG_ERROR = 0x01,
1097 NVME_LOG_SMART = 0x02,
1098 NVME_LOG_FW_SLOT = 0x03,
1099 NVME_LOG_CHANGED_NS = 0x04,
1100 NVME_LOG_CMD_EFFECTS = 0x05,
1101 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1102 NVME_LOG_TELEMETRY_HOST = 0x07,
1103 NVME_LOG_TELEMETRY_CTRL = 0x08,
1104 NVME_LOG_ENDURANCE_GROUP = 0x09,
1105 NVME_LOG_ANA = 0x0c,
1106 NVME_LOG_DISC = 0x70,
1107 NVME_LOG_RESERVATION = 0x80,
1108 NVME_FWACT_REPL = (0 << 3),
1109 NVME_FWACT_REPL_ACTV = (1 << 3),
1110 NVME_FWACT_ACTV = (2 << 3),
1111 };
1112
1113 /* NVMe Namespace Write Protect State */
1114 enum {
1115 NVME_NS_NO_WRITE_PROTECT = 0,
1116 NVME_NS_WRITE_PROTECT,
1117 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1118 NVME_NS_WRITE_PROTECT_PERMANENT,
1119 };
1120
1121 #define NVME_MAX_CHANGED_NAMESPACES 1024
1122
1123 struct nvme_identify {
1124 __u8 opcode;
1125 __u8 flags;
1126 __u16 command_id;
1127 __le32 nsid;
1128 __u64 rsvd2[2];
1129 union nvme_data_ptr dptr;
1130 __u8 cns;
1131 __u8 rsvd3;
1132 __le16 ctrlid;
1133 __u8 rsvd11[3];
1134 __u8 csi;
1135 __u32 rsvd12[4];
1136 };
1137
1138 #define NVME_IDENTIFY_DATA_SIZE 4096
1139
1140 struct nvme_features {
1141 __u8 opcode;
1142 __u8 flags;
1143 __u16 command_id;
1144 __le32 nsid;
1145 __u64 rsvd2[2];
1146 union nvme_data_ptr dptr;
1147 __le32 fid;
1148 __le32 dword11;
1149 __le32 dword12;
1150 __le32 dword13;
1151 __le32 dword14;
1152 __le32 dword15;
1153 };
1154
1155 struct nvme_host_mem_buf_desc {
1156 __le64 addr;
1157 __le32 size;
1158 __u32 rsvd;
1159 };
1160
1161 struct nvme_create_cq {
1162 __u8 opcode;
1163 __u8 flags;
1164 __u16 command_id;
1165 __u32 rsvd1[5];
1166 __le64 prp1;
1167 __u64 rsvd8;
1168 __le16 cqid;
1169 __le16 qsize;
1170 __le16 cq_flags;
1171 __le16 irq_vector;
1172 __u32 rsvd12[4];
1173 };
1174
1175 struct nvme_create_sq {
1176 __u8 opcode;
1177 __u8 flags;
1178 __u16 command_id;
1179 __u32 rsvd1[5];
1180 __le64 prp1;
1181 __u64 rsvd8;
1182 __le16 sqid;
1183 __le16 qsize;
1184 __le16 sq_flags;
1185 __le16 cqid;
1186 __u32 rsvd12[4];
1187 };
1188
1189 struct nvme_delete_queue {
1190 __u8 opcode;
1191 __u8 flags;
1192 __u16 command_id;
1193 __u32 rsvd1[9];
1194 __le16 qid;
1195 __u16 rsvd10;
1196 __u32 rsvd11[5];
1197 };
1198
1199 struct nvme_abort_cmd {
1200 __u8 opcode;
1201 __u8 flags;
1202 __u16 command_id;
1203 __u32 rsvd1[9];
1204 __le16 sqid;
1205 __u16 cid;
1206 __u32 rsvd11[5];
1207 };
1208
1209 struct nvme_download_firmware {
1210 __u8 opcode;
1211 __u8 flags;
1212 __u16 command_id;
1213 __u32 rsvd1[5];
1214 union nvme_data_ptr dptr;
1215 __le32 numd;
1216 __le32 offset;
1217 __u32 rsvd12[4];
1218 };
1219
1220 struct nvme_format_cmd {
1221 __u8 opcode;
1222 __u8 flags;
1223 __u16 command_id;
1224 __le32 nsid;
1225 __u64 rsvd2[4];
1226 __le32 cdw10;
1227 __u32 rsvd11[5];
1228 };
1229
1230 struct nvme_get_log_page_command {
1231 __u8 opcode;
1232 __u8 flags;
1233 __u16 command_id;
1234 __le32 nsid;
1235 __u64 rsvd2[2];
1236 union nvme_data_ptr dptr;
1237 __u8 lid;
1238 __u8 lsp; /* upper 4 bits reserved */
1239 __le16 numdl;
1240 __le16 numdu;
1241 __u16 rsvd11;
1242 union {
1243 struct {
1244 __le32 lpol;
1245 __le32 lpou;
1246 };
1247 __le64 lpo;
1248 };
1249 __u8 rsvd14[3];
1250 __u8 csi;
1251 __u32 rsvd15;
1252 };
1253
1254 struct nvme_directive_cmd {
1255 __u8 opcode;
1256 __u8 flags;
1257 __u16 command_id;
1258 __le32 nsid;
1259 __u64 rsvd2[2];
1260 union nvme_data_ptr dptr;
1261 __le32 numd;
1262 __u8 doper;
1263 __u8 dtype;
1264 __le16 dspec;
1265 __u8 endir;
1266 __u8 tdtype;
1267 __u16 rsvd15;
1268
1269 __u32 rsvd16[3];
1270 };
1271
1272 /*
1273 * Fabrics subcommands.
1274 */
1275 enum nvmf_fabrics_opcode {
1276 nvme_fabrics_command = 0x7f,
1277 };
1278
1279 enum nvmf_capsule_command {
1280 nvme_fabrics_type_property_set = 0x00,
1281 nvme_fabrics_type_connect = 0x01,
1282 nvme_fabrics_type_property_get = 0x04,
1283 };
1284
1285 #define nvme_fabrics_type_name(type) { type, #type }
1286 #define show_fabrics_type_name(type) \
1287 __print_symbolic(type, \
1288 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1289 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1290 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1291
1292 /*
1293 * If not fabrics command, fctype will be ignored.
1294 */
1295 #define show_opcode_name(qid, opcode, fctype) \
1296 ((opcode) == nvme_fabrics_command ? \
1297 show_fabrics_type_name(fctype) : \
1298 ((qid) ? \
1299 show_nvm_opcode_name(opcode) : \
1300 show_admin_opcode_name(opcode)))
1301
1302 struct nvmf_common_command {
1303 __u8 opcode;
1304 __u8 resv1;
1305 __u16 command_id;
1306 __u8 fctype;
1307 __u8 resv2[35];
1308 __u8 ts[24];
1309 };
1310
1311 /*
1312 * The legal cntlid range a NVMe Target will provide.
1313 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1314 * Devices based on earlier specs did not have the subsystem concept;
1315 * therefore, those devices had their cntlid value set to 0 as a result.
1316 */
1317 #define NVME_CNTLID_MIN 1
1318 #define NVME_CNTLID_MAX 0xffef
1319 #define NVME_CNTLID_DYNAMIC 0xffff
1320
1321 #define MAX_DISC_LOGS 255
1322
1323 /* Discovery log page entry */
1324 struct nvmf_disc_rsp_page_entry {
1325 __u8 trtype;
1326 __u8 adrfam;
1327 __u8 subtype;
1328 __u8 treq;
1329 __le16 portid;
1330 __le16 cntlid;
1331 __le16 asqsz;
1332 __u8 resv8[22];
1333 char trsvcid[NVMF_TRSVCID_SIZE];
1334 __u8 resv64[192];
1335 char subnqn[NVMF_NQN_FIELD_LEN];
1336 char traddr[NVMF_TRADDR_SIZE];
1337 union tsas {
1338 char common[NVMF_TSAS_SIZE];
1339 struct rdma {
1340 __u8 qptype;
1341 __u8 prtype;
1342 __u8 cms;
1343 __u8 resv3[5];
1344 __u16 pkey;
1345 __u8 resv10[246];
1346 } rdma;
1347 } tsas;
1348 };
1349
1350 /* Discovery log page header */
1351 struct nvmf_disc_rsp_page_hdr {
1352 __le64 genctr;
1353 __le64 numrec;
1354 __le16 recfmt;
1355 __u8 resv14[1006];
1356 struct nvmf_disc_rsp_page_entry entries[];
1357 };
1358
1359 enum {
1360 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1361 };
1362
1363 struct nvmf_connect_command {
1364 __u8 opcode;
1365 __u8 resv1;
1366 __u16 command_id;
1367 __u8 fctype;
1368 __u8 resv2[19];
1369 union nvme_data_ptr dptr;
1370 __le16 recfmt;
1371 __le16 qid;
1372 __le16 sqsize;
1373 __u8 cattr;
1374 __u8 resv3;
1375 __le32 kato;
1376 __u8 resv4[12];
1377 };
1378
1379 struct nvmf_connect_data {
1380 uuid_t hostid;
1381 __le16 cntlid;
1382 char resv4[238];
1383 char subsysnqn[NVMF_NQN_FIELD_LEN];
1384 char hostnqn[NVMF_NQN_FIELD_LEN];
1385 char resv5[256];
1386 };
1387
1388 struct nvmf_property_set_command {
1389 __u8 opcode;
1390 __u8 resv1;
1391 __u16 command_id;
1392 __u8 fctype;
1393 __u8 resv2[35];
1394 __u8 attrib;
1395 __u8 resv3[3];
1396 __le32 offset;
1397 __le64 value;
1398 __u8 resv4[8];
1399 };
1400
1401 struct nvmf_property_get_command {
1402 __u8 opcode;
1403 __u8 resv1;
1404 __u16 command_id;
1405 __u8 fctype;
1406 __u8 resv2[35];
1407 __u8 attrib;
1408 __u8 resv3[3];
1409 __le32 offset;
1410 __u8 resv4[16];
1411 };
1412
1413 struct nvme_dbbuf {
1414 __u8 opcode;
1415 __u8 flags;
1416 __u16 command_id;
1417 __u32 rsvd1[5];
1418 __le64 prp1;
1419 __le64 prp2;
1420 __u32 rsvd12[6];
1421 };
1422
1423 struct streams_directive_params {
1424 __le16 msl;
1425 __le16 nssa;
1426 __le16 nsso;
1427 __u8 rsvd[10];
1428 __le32 sws;
1429 __le16 sgs;
1430 __le16 nsa;
1431 __le16 nso;
1432 __u8 rsvd2[6];
1433 };
1434
1435 struct nvme_command {
1436 union {
1437 struct nvme_common_command common;
1438 struct nvme_rw_command rw;
1439 struct nvme_identify identify;
1440 struct nvme_features features;
1441 struct nvme_create_cq create_cq;
1442 struct nvme_create_sq create_sq;
1443 struct nvme_delete_queue delete_queue;
1444 struct nvme_download_firmware dlfw;
1445 struct nvme_format_cmd format;
1446 struct nvme_dsm_cmd dsm;
1447 struct nvme_write_zeroes_cmd write_zeroes;
1448 struct nvme_zone_mgmt_send_cmd zms;
1449 struct nvme_zone_mgmt_recv_cmd zmr;
1450 struct nvme_abort_cmd abort;
1451 struct nvme_get_log_page_command get_log_page;
1452 struct nvmf_common_command fabrics;
1453 struct nvmf_connect_command connect;
1454 struct nvmf_property_set_command prop_set;
1455 struct nvmf_property_get_command prop_get;
1456 struct nvme_dbbuf dbbuf;
1457 struct nvme_directive_cmd directive;
1458 };
1459 };
1460
1461 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1462 {
1463 return cmd->common.opcode == nvme_fabrics_command;
1464 }
1465
1466 struct nvme_error_slot {
1467 __le64 error_count;
1468 __le16 sqid;
1469 __le16 cmdid;
1470 __le16 status_field;
1471 __le16 param_error_location;
1472 __le64 lba;
1473 __le32 nsid;
1474 __u8 vs;
1475 __u8 resv[3];
1476 __le64 cs;
1477 __u8 resv2[24];
1478 };
1479
1480 static inline bool nvme_is_write(struct nvme_command *cmd)
1481 {
1482 /*
1483 * What a mess...
1484 *
1485 * Why can't we simply have a Fabrics In and Fabrics out command?
1486 */
1487 if (unlikely(nvme_is_fabrics(cmd)))
1488 return cmd->fabrics.fctype & 1;
1489 return cmd->common.opcode & 1;
1490 }
1491
1492 enum {
1493 /*
1494 * Generic Command Status:
1495 */
1496 NVME_SC_SUCCESS = 0x0,
1497 NVME_SC_INVALID_OPCODE = 0x1,
1498 NVME_SC_INVALID_FIELD = 0x2,
1499 NVME_SC_CMDID_CONFLICT = 0x3,
1500 NVME_SC_DATA_XFER_ERROR = 0x4,
1501 NVME_SC_POWER_LOSS = 0x5,
1502 NVME_SC_INTERNAL = 0x6,
1503 NVME_SC_ABORT_REQ = 0x7,
1504 NVME_SC_ABORT_QUEUE = 0x8,
1505 NVME_SC_FUSED_FAIL = 0x9,
1506 NVME_SC_FUSED_MISSING = 0xa,
1507 NVME_SC_INVALID_NS = 0xb,
1508 NVME_SC_CMD_SEQ_ERROR = 0xc,
1509 NVME_SC_SGL_INVALID_LAST = 0xd,
1510 NVME_SC_SGL_INVALID_COUNT = 0xe,
1511 NVME_SC_SGL_INVALID_DATA = 0xf,
1512 NVME_SC_SGL_INVALID_METADATA = 0x10,
1513 NVME_SC_SGL_INVALID_TYPE = 0x11,
1514 NVME_SC_CMB_INVALID_USE = 0x12,
1515 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1516 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1517 NVME_SC_OP_DENIED = 0x15,
1518 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1519 NVME_SC_RESERVED = 0x17,
1520 NVME_SC_HOST_ID_INCONSIST = 0x18,
1521 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1522 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1523 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1524 NVME_SC_SANITIZE_FAILED = 0x1C,
1525 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1526 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1527 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1528 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1529 NVME_SC_CMD_INTERRUPTED = 0x21,
1530 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1531 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
1532
1533 NVME_SC_LBA_RANGE = 0x80,
1534 NVME_SC_CAP_EXCEEDED = 0x81,
1535 NVME_SC_NS_NOT_READY = 0x82,
1536 NVME_SC_RESERVATION_CONFLICT = 0x83,
1537 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1538
1539 /*
1540 * Command Specific Status:
1541 */
1542 NVME_SC_CQ_INVALID = 0x100,
1543 NVME_SC_QID_INVALID = 0x101,
1544 NVME_SC_QUEUE_SIZE = 0x102,
1545 NVME_SC_ABORT_LIMIT = 0x103,
1546 NVME_SC_ABORT_MISSING = 0x104,
1547 NVME_SC_ASYNC_LIMIT = 0x105,
1548 NVME_SC_FIRMWARE_SLOT = 0x106,
1549 NVME_SC_FIRMWARE_IMAGE = 0x107,
1550 NVME_SC_INVALID_VECTOR = 0x108,
1551 NVME_SC_INVALID_LOG_PAGE = 0x109,
1552 NVME_SC_INVALID_FORMAT = 0x10a,
1553 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1554 NVME_SC_INVALID_QUEUE = 0x10c,
1555 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1556 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1557 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1558 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1559 NVME_SC_FW_NEEDS_RESET = 0x111,
1560 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1561 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1562 NVME_SC_OVERLAPPING_RANGE = 0x114,
1563 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1564 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1565 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1566 NVME_SC_NS_IS_PRIVATE = 0x119,
1567 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1568 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1569 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1570 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
1571 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1572 NVME_SC_CTRL_ID_INVALID = 0x11f,
1573 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1574 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1575 NVME_SC_RES_ID_INVALID = 0x122,
1576 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1577 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1578 NVME_SC_ANA_ATTACH_FAILED = 0x125,
1579
1580 /*
1581 * I/O Command Set Specific - NVM commands:
1582 */
1583 NVME_SC_BAD_ATTRIBUTES = 0x180,
1584 NVME_SC_INVALID_PI = 0x181,
1585 NVME_SC_READ_ONLY = 0x182,
1586 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1587
1588 /*
1589 * I/O Command Set Specific - Fabrics commands:
1590 */
1591 NVME_SC_CONNECT_FORMAT = 0x180,
1592 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1593 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1594 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1595 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1596
1597 NVME_SC_DISCOVERY_RESTART = 0x190,
1598 NVME_SC_AUTH_REQUIRED = 0x191,
1599
1600 /*
1601 * I/O Command Set Specific - Zoned commands:
1602 */
1603 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1604 NVME_SC_ZONE_FULL = 0x1b9,
1605 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1606 NVME_SC_ZONE_OFFLINE = 0x1bb,
1607 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1608 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1609 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1610 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1611
1612 /*
1613 * Media and Data Integrity Errors:
1614 */
1615 NVME_SC_WRITE_FAULT = 0x280,
1616 NVME_SC_READ_ERROR = 0x281,
1617 NVME_SC_GUARD_CHECK = 0x282,
1618 NVME_SC_APPTAG_CHECK = 0x283,
1619 NVME_SC_REFTAG_CHECK = 0x284,
1620 NVME_SC_COMPARE_FAILED = 0x285,
1621 NVME_SC_ACCESS_DENIED = 0x286,
1622 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1623
1624 /*
1625 * Path-related Errors:
1626 */
1627 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1628 NVME_SC_ANA_INACCESSIBLE = 0x302,
1629 NVME_SC_ANA_TRANSITION = 0x303,
1630 NVME_SC_HOST_PATH_ERROR = 0x370,
1631 NVME_SC_HOST_ABORTED_CMD = 0x371,
1632
1633 NVME_SC_CRD = 0x1800,
1634 NVME_SC_DNR = 0x4000,
1635 };
1636
1637 struct nvme_completion {
1638 /*
1639 * Used by Admin and Fabrics commands to return data:
1640 */
1641 union nvme_result {
1642 __le16 u16;
1643 __le32 u32;
1644 __le64 u64;
1645 } result;
1646 __le16 sq_head; /* how much of this queue may be reclaimed */
1647 __le16 sq_id; /* submission queue that generated this entry */
1648 __u16 command_id; /* of the command which completed */
1649 __le16 status; /* did the command fail, and if so, why? */
1650 };
1651
1652 #define NVME_VS(major, minor, tertiary) \
1653 (((major) << 16) | ((minor) << 8) | (tertiary))
1654
1655 #define NVME_MAJOR(ver) ((ver) >> 16)
1656 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1657 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1658
1659 #endif /* _LINUX_NVME_H */
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