1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
10 #include <linux/types.h>
11 #include <linux/uuid.h>
13 /* NQN names in commands fields specified one size */
14 #define NVMF_NQN_FIELD_LEN 256
16 /* However the max length of a qualified name is another size */
17 #define NVMF_NQN_SIZE 223
19 #define NVMF_TRSVCID_SIZE 32
20 #define NVMF_TRADDR_SIZE 256
21 #define NVMF_TSAS_SIZE 256
23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25 #define NVME_RDMA_IP_PORT 4420
27 #define NVME_NSID_ALL 0xffffffff
29 enum nvme_subsys_type
{
30 NVME_NQN_DISC
= 1, /* Discovery type target subsystem */
31 NVME_NQN_NVME
= 2, /* NVME type target subsystem */
34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
36 NVMF_ADDR_FAMILY_PCI
= 0, /* PCIe */
37 NVMF_ADDR_FAMILY_IP4
= 1, /* IP4 */
38 NVMF_ADDR_FAMILY_IP6
= 2, /* IP6 */
39 NVMF_ADDR_FAMILY_IB
= 3, /* InfiniBand */
40 NVMF_ADDR_FAMILY_FC
= 4, /* Fibre Channel */
43 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
45 NVMF_TRTYPE_RDMA
= 1, /* RDMA */
46 NVMF_TRTYPE_FC
= 2, /* Fibre Channel */
47 NVMF_TRTYPE_TCP
= 3, /* TCP/IP */
48 NVMF_TRTYPE_LOOP
= 254, /* Reserved for host usage */
52 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
54 NVMF_TREQ_NOT_SPECIFIED
= 0, /* Not specified */
55 NVMF_TREQ_REQUIRED
= 1, /* Required */
56 NVMF_TREQ_NOT_REQUIRED
= 2, /* Not Required */
57 #define NVME_TREQ_SECURE_CHANNEL_MASK \
58 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
60 NVMF_TREQ_DISABLE_SQFLOW
= (1 << 2), /* Supports SQ flow control disable */
63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 NVMF_RDMA_QPTYPE_CONNECTED
= 1, /* Reliable Connected */
68 NVMF_RDMA_QPTYPE_DATAGRAM
= 2, /* Reliable Datagram */
71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED
= 1, /* No Provider Specified */
76 NVMF_RDMA_PRTYPE_IB
= 2, /* InfiniBand */
77 NVMF_RDMA_PRTYPE_ROCE
= 3, /* InfiniBand RoCE */
78 NVMF_RDMA_PRTYPE_ROCEV2
= 4, /* InfiniBand RoCEV2 */
79 NVMF_RDMA_PRTYPE_IWARP
= 5, /* IWARP */
82 /* RDMA Connection Management Service Type codes for Discovery Log Page
83 * entry TSAS RDMA_CMS field
86 NVMF_RDMA_CMS_RDMA_CM
= 1, /* Sockets based endpoint addressing */
89 #define NVME_AQ_DEPTH 32
90 #define NVME_NR_AEN_COMMANDS 1
91 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
94 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
95 * NVM-Express 1.2 specification, section 4.1.2.
97 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
100 NVME_REG_CAP
= 0x0000, /* Controller Capabilities */
101 NVME_REG_VS
= 0x0008, /* Version */
102 NVME_REG_INTMS
= 0x000c, /* Interrupt Mask Set */
103 NVME_REG_INTMC
= 0x0010, /* Interrupt Mask Clear */
104 NVME_REG_CC
= 0x0014, /* Controller Configuration */
105 NVME_REG_CSTS
= 0x001c, /* Controller Status */
106 NVME_REG_NSSR
= 0x0020, /* NVM Subsystem Reset */
107 NVME_REG_AQA
= 0x0024, /* Admin Queue Attributes */
108 NVME_REG_ASQ
= 0x0028, /* Admin SQ Base Address */
109 NVME_REG_ACQ
= 0x0030, /* Admin CQ Base Address */
110 NVME_REG_CMBLOC
= 0x0038, /* Controller Memory Buffer Location */
111 NVME_REG_CMBSZ
= 0x003c, /* Controller Memory Buffer Size */
112 NVME_REG_DBS
= 0x1000, /* SQ 0 Tail Doorbell */
115 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
116 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
117 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
118 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
119 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
120 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
122 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
123 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
126 NVME_CMBSZ_SQS
= 1 << 0,
127 NVME_CMBSZ_CQS
= 1 << 1,
128 NVME_CMBSZ_LISTS
= 1 << 2,
129 NVME_CMBSZ_RDS
= 1 << 3,
130 NVME_CMBSZ_WDS
= 1 << 4,
132 NVME_CMBSZ_SZ_SHIFT
= 12,
133 NVME_CMBSZ_SZ_MASK
= 0xfffff,
135 NVME_CMBSZ_SZU_SHIFT
= 8,
136 NVME_CMBSZ_SZU_MASK
= 0xf,
140 * Submission and Completion Queue Entry Sizes for the NVM command set.
141 * (In bytes and specified as a power of two (2^n)).
143 #define NVME_NVM_IOSQES 6
144 #define NVME_NVM_IOCQES 4
147 NVME_CC_ENABLE
= 1 << 0,
148 NVME_CC_CSS_NVM
= 0 << 4,
149 NVME_CC_EN_SHIFT
= 0,
150 NVME_CC_CSS_SHIFT
= 4,
151 NVME_CC_MPS_SHIFT
= 7,
152 NVME_CC_AMS_SHIFT
= 11,
153 NVME_CC_SHN_SHIFT
= 14,
154 NVME_CC_IOSQES_SHIFT
= 16,
155 NVME_CC_IOCQES_SHIFT
= 20,
156 NVME_CC_AMS_RR
= 0 << NVME_CC_AMS_SHIFT
,
157 NVME_CC_AMS_WRRU
= 1 << NVME_CC_AMS_SHIFT
,
158 NVME_CC_AMS_VS
= 7 << NVME_CC_AMS_SHIFT
,
159 NVME_CC_SHN_NONE
= 0 << NVME_CC_SHN_SHIFT
,
160 NVME_CC_SHN_NORMAL
= 1 << NVME_CC_SHN_SHIFT
,
161 NVME_CC_SHN_ABRUPT
= 2 << NVME_CC_SHN_SHIFT
,
162 NVME_CC_SHN_MASK
= 3 << NVME_CC_SHN_SHIFT
,
163 NVME_CC_IOSQES
= NVME_NVM_IOSQES
<< NVME_CC_IOSQES_SHIFT
,
164 NVME_CC_IOCQES
= NVME_NVM_IOCQES
<< NVME_CC_IOCQES_SHIFT
,
165 NVME_CSTS_RDY
= 1 << 0,
166 NVME_CSTS_CFS
= 1 << 1,
167 NVME_CSTS_NSSRO
= 1 << 4,
168 NVME_CSTS_PP
= 1 << 5,
169 NVME_CSTS_SHST_NORMAL
= 0 << 2,
170 NVME_CSTS_SHST_OCCUR
= 1 << 2,
171 NVME_CSTS_SHST_CMPLT
= 2 << 2,
172 NVME_CSTS_SHST_MASK
= 3 << 2,
175 struct nvme_id_power_state
{
176 __le16 max_power
; /* centiwatts */
179 __le32 entry_lat
; /* microseconds */
180 __le32 exit_lat
; /* microseconds */
189 __u8 active_work_scale
;
194 NVME_PS_FLAGS_MAX_POWER_SCALE
= 1 << 0,
195 NVME_PS_FLAGS_NON_OP_STATE
= 1 << 1,
198 enum nvme_ctrl_attr
{
199 NVME_CTRL_ATTR_HID_128_BIT
= (1 << 0),
200 NVME_CTRL_ATTR_TBKAS
= (1 << 6),
203 struct nvme_id_ctrl
{
282 struct nvme_id_power_state psd
[32];
287 NVME_CTRL_ONCS_COMPARE
= 1 << 0,
288 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE
= 1 << 1,
289 NVME_CTRL_ONCS_DSM
= 1 << 2,
290 NVME_CTRL_ONCS_WRITE_ZEROES
= 1 << 3,
291 NVME_CTRL_ONCS_TIMESTAMP
= 1 << 6,
292 NVME_CTRL_VWC_PRESENT
= 1 << 0,
293 NVME_CTRL_OACS_SEC_SUPP
= 1 << 0,
294 NVME_CTRL_OACS_DIRECTIVES
= 1 << 5,
295 NVME_CTRL_OACS_DBBUF_SUPP
= 1 << 8,
296 NVME_CTRL_LPA_CMD_EFFECTS_LOG
= 1 << 1,
334 struct nvme_lbaf lbaf
[16];
340 NVME_ID_CNS_NS
= 0x00,
341 NVME_ID_CNS_CTRL
= 0x01,
342 NVME_ID_CNS_NS_ACTIVE_LIST
= 0x02,
343 NVME_ID_CNS_NS_DESC_LIST
= 0x03,
344 NVME_ID_CNS_NS_PRESENT_LIST
= 0x10,
345 NVME_ID_CNS_NS_PRESENT
= 0x11,
346 NVME_ID_CNS_CTRL_NS_LIST
= 0x12,
347 NVME_ID_CNS_CTRL_LIST
= 0x13,
351 NVME_DIR_IDENTIFY
= 0x00,
352 NVME_DIR_STREAMS
= 0x01,
353 NVME_DIR_SND_ID_OP_ENABLE
= 0x01,
354 NVME_DIR_SND_ST_OP_REL_ID
= 0x01,
355 NVME_DIR_SND_ST_OP_REL_RSC
= 0x02,
356 NVME_DIR_RCV_ID_OP_PARAM
= 0x01,
357 NVME_DIR_RCV_ST_OP_PARAM
= 0x01,
358 NVME_DIR_RCV_ST_OP_STATUS
= 0x02,
359 NVME_DIR_RCV_ST_OP_RESOURCE
= 0x03,
360 NVME_DIR_ENDIR
= 0x01,
364 NVME_NS_FEAT_THIN
= 1 << 0,
365 NVME_NS_FLBAS_LBA_MASK
= 0xf,
366 NVME_NS_FLBAS_META_EXT
= 0x10,
367 NVME_LBAF_RP_BEST
= 0,
368 NVME_LBAF_RP_BETTER
= 1,
369 NVME_LBAF_RP_GOOD
= 2,
370 NVME_LBAF_RP_DEGRADED
= 3,
371 NVME_NS_DPC_PI_LAST
= 1 << 4,
372 NVME_NS_DPC_PI_FIRST
= 1 << 3,
373 NVME_NS_DPC_PI_TYPE3
= 1 << 2,
374 NVME_NS_DPC_PI_TYPE2
= 1 << 1,
375 NVME_NS_DPC_PI_TYPE1
= 1 << 0,
376 NVME_NS_DPS_PI_FIRST
= 1 << 3,
377 NVME_NS_DPS_PI_MASK
= 0x7,
378 NVME_NS_DPS_PI_TYPE1
= 1,
379 NVME_NS_DPS_PI_TYPE2
= 2,
380 NVME_NS_DPS_PI_TYPE3
= 3,
383 struct nvme_ns_id_desc
{
389 #define NVME_NIDT_EUI64_LEN 8
390 #define NVME_NIDT_NGUID_LEN 16
391 #define NVME_NIDT_UUID_LEN 16
394 NVME_NIDT_EUI64
= 0x01,
395 NVME_NIDT_NGUID
= 0x02,
396 NVME_NIDT_UUID
= 0x03,
399 struct nvme_smart_log
{
400 __u8 critical_warning
;
406 __u8 data_units_read
[16];
407 __u8 data_units_written
[16];
409 __u8 host_writes
[16];
410 __u8 ctrl_busy_time
[16];
411 __u8 power_cycles
[16];
412 __u8 power_on_hours
[16];
413 __u8 unsafe_shutdowns
[16];
414 __u8 media_errors
[16];
415 __u8 num_err_log_entries
[16];
416 __le32 warning_temp_time
;
417 __le32 critical_comp_time
;
418 __le16 temp_sensor
[8];
422 struct nvme_fw_slot_info_log
{
430 NVME_CMD_EFFECTS_CSUPP
= 1 << 0,
431 NVME_CMD_EFFECTS_LBCC
= 1 << 1,
432 NVME_CMD_EFFECTS_NCC
= 1 << 2,
433 NVME_CMD_EFFECTS_NIC
= 1 << 3,
434 NVME_CMD_EFFECTS_CCC
= 1 << 4,
435 NVME_CMD_EFFECTS_CSE_MASK
= 3 << 16,
438 struct nvme_effects_log
{
444 enum nvme_ana_state
{
445 NVME_ANA_OPTIMIZED
= 0x01,
446 NVME_ANA_NONOPTIMIZED
= 0x02,
447 NVME_ANA_INACCESSIBLE
= 0x03,
448 NVME_ANA_PERSISTENT_LOSS
= 0x04,
449 NVME_ANA_CHANGE
= 0x0f,
452 struct nvme_ana_group_desc
{
461 /* flag for the log specific field of the ANA log */
462 #define NVME_ANA_LOG_RGO (1 << 0)
464 struct nvme_ana_rsp_hdr
{
471 NVME_SMART_CRIT_SPARE
= 1 << 0,
472 NVME_SMART_CRIT_TEMPERATURE
= 1 << 1,
473 NVME_SMART_CRIT_RELIABILITY
= 1 << 2,
474 NVME_SMART_CRIT_MEDIA
= 1 << 3,
475 NVME_SMART_CRIT_VOLATILE_MEMORY
= 1 << 4,
487 NVME_AER_NOTICE_NS_CHANGED
= 0x00,
488 NVME_AER_NOTICE_FW_ACT_STARTING
= 0x01,
489 NVME_AER_NOTICE_ANA
= 0x03,
490 NVME_AER_NOTICE_DISC_CHANGED
= 0xf0,
494 NVME_AEN_BIT_NS_ATTR
= 8,
495 NVME_AEN_BIT_FW_ACT
= 9,
496 NVME_AEN_BIT_ANA_CHANGE
= 11,
497 NVME_AEN_BIT_DISC_CHANGE
= 31,
501 NVME_AEN_CFG_NS_ATTR
= 1 << NVME_AEN_BIT_NS_ATTR
,
502 NVME_AEN_CFG_FW_ACT
= 1 << NVME_AEN_BIT_FW_ACT
,
503 NVME_AEN_CFG_ANA_CHANGE
= 1 << NVME_AEN_BIT_ANA_CHANGE
,
504 NVME_AEN_CFG_DISC_CHANGE
= 1 << NVME_AEN_BIT_DISC_CHANGE
,
507 struct nvme_lba_range_type
{
518 NVME_LBART_TYPE_FS
= 0x01,
519 NVME_LBART_TYPE_RAID
= 0x02,
520 NVME_LBART_TYPE_CACHE
= 0x03,
521 NVME_LBART_TYPE_SWAP
= 0x04,
523 NVME_LBART_ATTRIB_TEMP
= 1 << 0,
524 NVME_LBART_ATTRIB_HIDE
= 1 << 1,
527 struct nvme_reservation_status
{
543 enum nvme_async_event_type
{
544 NVME_AER_TYPE_ERROR
= 0,
545 NVME_AER_TYPE_SMART
= 1,
546 NVME_AER_TYPE_NOTICE
= 2,
552 nvme_cmd_flush
= 0x00,
553 nvme_cmd_write
= 0x01,
554 nvme_cmd_read
= 0x02,
555 nvme_cmd_write_uncor
= 0x04,
556 nvme_cmd_compare
= 0x05,
557 nvme_cmd_write_zeroes
= 0x08,
559 nvme_cmd_resv_register
= 0x0d,
560 nvme_cmd_resv_report
= 0x0e,
561 nvme_cmd_resv_acquire
= 0x11,
562 nvme_cmd_resv_release
= 0x15,
566 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
568 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
569 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
570 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
571 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
575 NVME_SGL_FMT_ADDRESS
= 0x00,
576 NVME_SGL_FMT_OFFSET
= 0x01,
577 NVME_SGL_FMT_TRANSPORT_A
= 0x0A,
578 NVME_SGL_FMT_INVALIDATE
= 0x0f,
582 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
584 * For struct nvme_sgl_desc:
585 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
586 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
587 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
589 * For struct nvme_keyed_sgl_desc:
590 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
592 * Transport-specific SGL types:
593 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
596 NVME_SGL_FMT_DATA_DESC
= 0x00,
597 NVME_SGL_FMT_SEG_DESC
= 0x02,
598 NVME_SGL_FMT_LAST_SEG_DESC
= 0x03,
599 NVME_KEY_SGL_FMT_DATA_DESC
= 0x04,
600 NVME_TRANSPORT_SGL_DATA_DESC
= 0x05,
603 struct nvme_sgl_desc
{
610 struct nvme_keyed_sgl_desc
{
617 union nvme_data_ptr
{
622 struct nvme_sgl_desc sgl
;
623 struct nvme_keyed_sgl_desc ksgl
;
627 * Lowest two bits of our flags field (FUSE field in the spec):
629 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
630 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
632 * Highest two bits in our flags field (PSDT field in the spec):
634 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
635 * If used, MPTR contains addr of single physical buffer (byte aligned).
636 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
637 * If used, MPTR contains an address of an SGL segment containing
638 * exactly 1 SGL descriptor (qword aligned).
641 NVME_CMD_FUSE_FIRST
= (1 << 0),
642 NVME_CMD_FUSE_SECOND
= (1 << 1),
644 NVME_CMD_SGL_METABUF
= (1 << 6),
645 NVME_CMD_SGL_METASEG
= (1 << 7),
646 NVME_CMD_SGL_ALL
= NVME_CMD_SGL_METABUF
| NVME_CMD_SGL_METASEG
,
649 struct nvme_common_command
{
656 union nvme_data_ptr dptr
;
665 struct nvme_rw_command
{
672 union nvme_data_ptr dptr
;
683 NVME_RW_LR
= 1 << 15,
684 NVME_RW_FUA
= 1 << 14,
685 NVME_RW_DSM_FREQ_UNSPEC
= 0,
686 NVME_RW_DSM_FREQ_TYPICAL
= 1,
687 NVME_RW_DSM_FREQ_RARE
= 2,
688 NVME_RW_DSM_FREQ_READS
= 3,
689 NVME_RW_DSM_FREQ_WRITES
= 4,
690 NVME_RW_DSM_FREQ_RW
= 5,
691 NVME_RW_DSM_FREQ_ONCE
= 6,
692 NVME_RW_DSM_FREQ_PREFETCH
= 7,
693 NVME_RW_DSM_FREQ_TEMP
= 8,
694 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
695 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
696 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
697 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
698 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
699 NVME_RW_DSM_COMPRESSED
= 1 << 7,
700 NVME_RW_PRINFO_PRCHK_REF
= 1 << 10,
701 NVME_RW_PRINFO_PRCHK_APP
= 1 << 11,
702 NVME_RW_PRINFO_PRCHK_GUARD
= 1 << 12,
703 NVME_RW_PRINFO_PRACT
= 1 << 13,
704 NVME_RW_DTYPE_STREAMS
= 1 << 4,
707 struct nvme_dsm_cmd
{
713 union nvme_data_ptr dptr
;
720 NVME_DSMGMT_IDR
= 1 << 0,
721 NVME_DSMGMT_IDW
= 1 << 1,
722 NVME_DSMGMT_AD
= 1 << 2,
725 #define NVME_DSM_MAX_RANGES 256
727 struct nvme_dsm_range
{
733 struct nvme_write_zeroes_cmd
{
740 union nvme_data_ptr dptr
;
752 struct nvme_feat_auto_pst
{
757 NVME_HOST_MEM_ENABLE
= (1 << 0),
758 NVME_HOST_MEM_RETURN
= (1 << 1),
761 struct nvme_feat_host_behavior
{
767 NVME_ENABLE_ACRE
= 1,
772 enum nvme_admin_opcode
{
773 nvme_admin_delete_sq
= 0x00,
774 nvme_admin_create_sq
= 0x01,
775 nvme_admin_get_log_page
= 0x02,
776 nvme_admin_delete_cq
= 0x04,
777 nvme_admin_create_cq
= 0x05,
778 nvme_admin_identify
= 0x06,
779 nvme_admin_abort_cmd
= 0x08,
780 nvme_admin_set_features
= 0x09,
781 nvme_admin_get_features
= 0x0a,
782 nvme_admin_async_event
= 0x0c,
783 nvme_admin_ns_mgmt
= 0x0d,
784 nvme_admin_activate_fw
= 0x10,
785 nvme_admin_download_fw
= 0x11,
786 nvme_admin_ns_attach
= 0x15,
787 nvme_admin_keep_alive
= 0x18,
788 nvme_admin_directive_send
= 0x19,
789 nvme_admin_directive_recv
= 0x1a,
790 nvme_admin_dbbuf
= 0x7C,
791 nvme_admin_format_nvm
= 0x80,
792 nvme_admin_security_send
= 0x81,
793 nvme_admin_security_recv
= 0x82,
794 nvme_admin_sanitize_nvm
= 0x84,
798 NVME_QUEUE_PHYS_CONTIG
= (1 << 0),
799 NVME_CQ_IRQ_ENABLED
= (1 << 1),
800 NVME_SQ_PRIO_URGENT
= (0 << 1),
801 NVME_SQ_PRIO_HIGH
= (1 << 1),
802 NVME_SQ_PRIO_MEDIUM
= (2 << 1),
803 NVME_SQ_PRIO_LOW
= (3 << 1),
804 NVME_FEAT_ARBITRATION
= 0x01,
805 NVME_FEAT_POWER_MGMT
= 0x02,
806 NVME_FEAT_LBA_RANGE
= 0x03,
807 NVME_FEAT_TEMP_THRESH
= 0x04,
808 NVME_FEAT_ERR_RECOVERY
= 0x05,
809 NVME_FEAT_VOLATILE_WC
= 0x06,
810 NVME_FEAT_NUM_QUEUES
= 0x07,
811 NVME_FEAT_IRQ_COALESCE
= 0x08,
812 NVME_FEAT_IRQ_CONFIG
= 0x09,
813 NVME_FEAT_WRITE_ATOMIC
= 0x0a,
814 NVME_FEAT_ASYNC_EVENT
= 0x0b,
815 NVME_FEAT_AUTO_PST
= 0x0c,
816 NVME_FEAT_HOST_MEM_BUF
= 0x0d,
817 NVME_FEAT_TIMESTAMP
= 0x0e,
818 NVME_FEAT_KATO
= 0x0f,
819 NVME_FEAT_HCTM
= 0x10,
820 NVME_FEAT_NOPSC
= 0x11,
821 NVME_FEAT_RRL
= 0x12,
822 NVME_FEAT_PLM_CONFIG
= 0x13,
823 NVME_FEAT_PLM_WINDOW
= 0x14,
824 NVME_FEAT_HOST_BEHAVIOR
= 0x16,
825 NVME_FEAT_SW_PROGRESS
= 0x80,
826 NVME_FEAT_HOST_ID
= 0x81,
827 NVME_FEAT_RESV_MASK
= 0x82,
828 NVME_FEAT_RESV_PERSIST
= 0x83,
829 NVME_FEAT_WRITE_PROTECT
= 0x84,
830 NVME_LOG_ERROR
= 0x01,
831 NVME_LOG_SMART
= 0x02,
832 NVME_LOG_FW_SLOT
= 0x03,
833 NVME_LOG_CHANGED_NS
= 0x04,
834 NVME_LOG_CMD_EFFECTS
= 0x05,
836 NVME_LOG_DISC
= 0x70,
837 NVME_LOG_RESERVATION
= 0x80,
838 NVME_FWACT_REPL
= (0 << 3),
839 NVME_FWACT_REPL_ACTV
= (1 << 3),
840 NVME_FWACT_ACTV
= (2 << 3),
843 /* NVMe Namespace Write Protect State */
845 NVME_NS_NO_WRITE_PROTECT
= 0,
846 NVME_NS_WRITE_PROTECT
,
847 NVME_NS_WRITE_PROTECT_POWER_CYCLE
,
848 NVME_NS_WRITE_PROTECT_PERMANENT
,
851 #define NVME_MAX_CHANGED_NAMESPACES 1024
853 struct nvme_identify
{
859 union nvme_data_ptr dptr
;
866 #define NVME_IDENTIFY_DATA_SIZE 4096
868 struct nvme_features
{
874 union nvme_data_ptr dptr
;
883 struct nvme_host_mem_buf_desc
{
889 struct nvme_create_cq
{
903 struct nvme_create_sq
{
917 struct nvme_delete_queue
{
927 struct nvme_abort_cmd
{
937 struct nvme_download_firmware
{
942 union nvme_data_ptr dptr
;
948 struct nvme_format_cmd
{
958 struct nvme_get_log_page_command
{
964 union nvme_data_ptr dptr
;
966 __u8 lsp
; /* upper 4 bits reserved */
980 struct nvme_directive_cmd
{
986 union nvme_data_ptr dptr
;
999 * Fabrics subcommands.
1001 enum nvmf_fabrics_opcode
{
1002 nvme_fabrics_command
= 0x7f,
1005 enum nvmf_capsule_command
{
1006 nvme_fabrics_type_property_set
= 0x00,
1007 nvme_fabrics_type_connect
= 0x01,
1008 nvme_fabrics_type_property_get
= 0x04,
1011 struct nvmf_common_command
{
1021 * The legal cntlid range a NVMe Target will provide.
1022 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1023 * Devices based on earlier specs did not have the subsystem concept;
1024 * therefore, those devices had their cntlid value set to 0 as a result.
1026 #define NVME_CNTLID_MIN 1
1027 #define NVME_CNTLID_MAX 0xffef
1028 #define NVME_CNTLID_DYNAMIC 0xffff
1030 #define MAX_DISC_LOGS 255
1032 /* Discovery log page entry */
1033 struct nvmf_disc_rsp_page_entry
{
1042 char trsvcid
[NVMF_TRSVCID_SIZE
];
1044 char subnqn
[NVMF_NQN_FIELD_LEN
];
1045 char traddr
[NVMF_TRADDR_SIZE
];
1047 char common
[NVMF_TSAS_SIZE
];
1059 /* Discovery log page header */
1060 struct nvmf_disc_rsp_page_hdr
{
1065 struct nvmf_disc_rsp_page_entry entries
[0];
1069 NVME_CONNECT_DISABLE_SQFLOW
= (1 << 2),
1072 struct nvmf_connect_command
{
1078 union nvme_data_ptr dptr
;
1088 struct nvmf_connect_data
{
1092 char subsysnqn
[NVMF_NQN_FIELD_LEN
];
1093 char hostnqn
[NVMF_NQN_FIELD_LEN
];
1097 struct nvmf_property_set_command
{
1110 struct nvmf_property_get_command
{
1132 struct streams_directive_params
{
1144 struct nvme_command
{
1146 struct nvme_common_command common
;
1147 struct nvme_rw_command rw
;
1148 struct nvme_identify identify
;
1149 struct nvme_features features
;
1150 struct nvme_create_cq create_cq
;
1151 struct nvme_create_sq create_sq
;
1152 struct nvme_delete_queue delete_queue
;
1153 struct nvme_download_firmware dlfw
;
1154 struct nvme_format_cmd format
;
1155 struct nvme_dsm_cmd dsm
;
1156 struct nvme_write_zeroes_cmd write_zeroes
;
1157 struct nvme_abort_cmd abort
;
1158 struct nvme_get_log_page_command get_log_page
;
1159 struct nvmf_common_command fabrics
;
1160 struct nvmf_connect_command connect
;
1161 struct nvmf_property_set_command prop_set
;
1162 struct nvmf_property_get_command prop_get
;
1163 struct nvme_dbbuf dbbuf
;
1164 struct nvme_directive_cmd directive
;
1168 struct nvme_error_slot
{
1172 __le16 status_field
;
1173 __le16 param_error_location
;
1182 static inline bool nvme_is_write(struct nvme_command
*cmd
)
1187 * Why can't we simply have a Fabrics In and Fabrics out command?
1189 if (unlikely(cmd
->common
.opcode
== nvme_fabrics_command
))
1190 return cmd
->fabrics
.fctype
& 1;
1191 return cmd
->common
.opcode
& 1;
1196 * Generic Command Status:
1198 NVME_SC_SUCCESS
= 0x0,
1199 NVME_SC_INVALID_OPCODE
= 0x1,
1200 NVME_SC_INVALID_FIELD
= 0x2,
1201 NVME_SC_CMDID_CONFLICT
= 0x3,
1202 NVME_SC_DATA_XFER_ERROR
= 0x4,
1203 NVME_SC_POWER_LOSS
= 0x5,
1204 NVME_SC_INTERNAL
= 0x6,
1205 NVME_SC_ABORT_REQ
= 0x7,
1206 NVME_SC_ABORT_QUEUE
= 0x8,
1207 NVME_SC_FUSED_FAIL
= 0x9,
1208 NVME_SC_FUSED_MISSING
= 0xa,
1209 NVME_SC_INVALID_NS
= 0xb,
1210 NVME_SC_CMD_SEQ_ERROR
= 0xc,
1211 NVME_SC_SGL_INVALID_LAST
= 0xd,
1212 NVME_SC_SGL_INVALID_COUNT
= 0xe,
1213 NVME_SC_SGL_INVALID_DATA
= 0xf,
1214 NVME_SC_SGL_INVALID_METADATA
= 0x10,
1215 NVME_SC_SGL_INVALID_TYPE
= 0x11,
1217 NVME_SC_SGL_INVALID_OFFSET
= 0x16,
1218 NVME_SC_SGL_INVALID_SUBTYPE
= 0x17,
1220 NVME_SC_NS_WRITE_PROTECTED
= 0x20,
1222 NVME_SC_LBA_RANGE
= 0x80,
1223 NVME_SC_CAP_EXCEEDED
= 0x81,
1224 NVME_SC_NS_NOT_READY
= 0x82,
1225 NVME_SC_RESERVATION_CONFLICT
= 0x83,
1228 * Command Specific Status:
1230 NVME_SC_CQ_INVALID
= 0x100,
1231 NVME_SC_QID_INVALID
= 0x101,
1232 NVME_SC_QUEUE_SIZE
= 0x102,
1233 NVME_SC_ABORT_LIMIT
= 0x103,
1234 NVME_SC_ABORT_MISSING
= 0x104,
1235 NVME_SC_ASYNC_LIMIT
= 0x105,
1236 NVME_SC_FIRMWARE_SLOT
= 0x106,
1237 NVME_SC_FIRMWARE_IMAGE
= 0x107,
1238 NVME_SC_INVALID_VECTOR
= 0x108,
1239 NVME_SC_INVALID_LOG_PAGE
= 0x109,
1240 NVME_SC_INVALID_FORMAT
= 0x10a,
1241 NVME_SC_FW_NEEDS_CONV_RESET
= 0x10b,
1242 NVME_SC_INVALID_QUEUE
= 0x10c,
1243 NVME_SC_FEATURE_NOT_SAVEABLE
= 0x10d,
1244 NVME_SC_FEATURE_NOT_CHANGEABLE
= 0x10e,
1245 NVME_SC_FEATURE_NOT_PER_NS
= 0x10f,
1246 NVME_SC_FW_NEEDS_SUBSYS_RESET
= 0x110,
1247 NVME_SC_FW_NEEDS_RESET
= 0x111,
1248 NVME_SC_FW_NEEDS_MAX_TIME
= 0x112,
1249 NVME_SC_FW_ACTIVATE_PROHIBITED
= 0x113,
1250 NVME_SC_OVERLAPPING_RANGE
= 0x114,
1251 NVME_SC_NS_INSUFFICIENT_CAP
= 0x115,
1252 NVME_SC_NS_ID_UNAVAILABLE
= 0x116,
1253 NVME_SC_NS_ALREADY_ATTACHED
= 0x118,
1254 NVME_SC_NS_IS_PRIVATE
= 0x119,
1255 NVME_SC_NS_NOT_ATTACHED
= 0x11a,
1256 NVME_SC_THIN_PROV_NOT_SUPP
= 0x11b,
1257 NVME_SC_CTRL_LIST_INVALID
= 0x11c,
1260 * I/O Command Set Specific - NVM commands:
1262 NVME_SC_BAD_ATTRIBUTES
= 0x180,
1263 NVME_SC_INVALID_PI
= 0x181,
1264 NVME_SC_READ_ONLY
= 0x182,
1265 NVME_SC_ONCS_NOT_SUPPORTED
= 0x183,
1268 * I/O Command Set Specific - Fabrics commands:
1270 NVME_SC_CONNECT_FORMAT
= 0x180,
1271 NVME_SC_CONNECT_CTRL_BUSY
= 0x181,
1272 NVME_SC_CONNECT_INVALID_PARAM
= 0x182,
1273 NVME_SC_CONNECT_RESTART_DISC
= 0x183,
1274 NVME_SC_CONNECT_INVALID_HOST
= 0x184,
1276 NVME_SC_DISCOVERY_RESTART
= 0x190,
1277 NVME_SC_AUTH_REQUIRED
= 0x191,
1280 * Media and Data Integrity Errors:
1282 NVME_SC_WRITE_FAULT
= 0x280,
1283 NVME_SC_READ_ERROR
= 0x281,
1284 NVME_SC_GUARD_CHECK
= 0x282,
1285 NVME_SC_APPTAG_CHECK
= 0x283,
1286 NVME_SC_REFTAG_CHECK
= 0x284,
1287 NVME_SC_COMPARE_FAILED
= 0x285,
1288 NVME_SC_ACCESS_DENIED
= 0x286,
1289 NVME_SC_UNWRITTEN_BLOCK
= 0x287,
1292 * Path-related Errors:
1294 NVME_SC_ANA_PERSISTENT_LOSS
= 0x301,
1295 NVME_SC_ANA_INACCESSIBLE
= 0x302,
1296 NVME_SC_ANA_TRANSITION
= 0x303,
1297 NVME_SC_HOST_PATH_ERROR
= 0x370,
1299 NVME_SC_CRD
= 0x1800,
1300 NVME_SC_DNR
= 0x4000,
1303 struct nvme_completion
{
1305 * Used by Admin and Fabrics commands to return data:
1312 __le16 sq_head
; /* how much of this queue may be reclaimed */
1313 __le16 sq_id
; /* submission queue that generated this entry */
1314 __u16 command_id
; /* of the command which completed */
1315 __le16 status
; /* did the command fail, and if so, why? */
1318 #define NVME_VS(major, minor, tertiary) \
1319 (((major) << 16) | ((minor) << 8) | (tertiary))
1321 #define NVME_MAJOR(ver) ((ver) >> 16)
1322 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1323 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1325 #endif /* _LINUX_NVME_H */