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[mirror_ubuntu-bionic-kernel.git] / include / linux / nvme.h
1 /*
2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #ifndef _LINUX_NVME_H
16 #define _LINUX_NVME_H
17
18 #include <linux/types.h>
19 #include <linux/uuid.h>
20
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN 256
23
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE 223
26
27 #define NVMF_TRSVCID_SIZE 32
28 #define NVMF_TRADDR_SIZE 256
29 #define NVMF_TSAS_SIZE 256
30
31 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32
33 #define NVME_RDMA_IP_PORT 4420
34
35 #define NVME_NSID_ALL 0xffffffff
36
37 enum nvme_subsys_type {
38 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
39 NVME_NQN_NVME = 2, /* NVME type target subsystem */
40 };
41
42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
43 enum {
44 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
45 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
46 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
49 };
50
51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
52 enum {
53 NVMF_TRTYPE_RDMA = 1, /* RDMA */
54 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
55 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
56 NVMF_TRTYPE_MAX,
57 };
58
59 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
60 enum {
61 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
62 NVMF_TREQ_REQUIRED = 1, /* Required */
63 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
64 };
65
66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 * RDMA_QPTYPE field
68 */
69 enum {
70 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
71 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
72 };
73
74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 * RDMA_QPTYPE field
76 */
77 enum {
78 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
79 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
80 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
81 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
82 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
83 };
84
85 /* RDMA Connection Management Service Type codes for Discovery Log Page
86 * entry TSAS RDMA_CMS field
87 */
88 enum {
89 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
90 };
91
92 #define NVME_AQ_DEPTH 32
93 #define NVME_NR_AEN_COMMANDS 1
94 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
95
96 /*
97 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
98 * NVM-Express 1.2 specification, section 4.1.2.
99 */
100 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
101
102 enum {
103 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
104 NVME_REG_VS = 0x0008, /* Version */
105 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
106 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
107 NVME_REG_CC = 0x0014, /* Controller Configuration */
108 NVME_REG_CSTS = 0x001c, /* Controller Status */
109 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
110 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
111 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
112 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
113 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
114 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
115 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
116 };
117
118 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
119 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
120 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
121 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
122 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
123 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
124
125 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
126 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
127 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
128 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
129
130 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
131 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
132 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
133 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
134 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
135
136 /*
137 * Submission and Completion Queue Entry Sizes for the NVM command set.
138 * (In bytes and specified as a power of two (2^n)).
139 */
140 #define NVME_NVM_IOSQES 6
141 #define NVME_NVM_IOCQES 4
142
143 enum {
144 NVME_CC_ENABLE = 1 << 0,
145 NVME_CC_CSS_NVM = 0 << 4,
146 NVME_CC_EN_SHIFT = 0,
147 NVME_CC_CSS_SHIFT = 4,
148 NVME_CC_MPS_SHIFT = 7,
149 NVME_CC_AMS_SHIFT = 11,
150 NVME_CC_SHN_SHIFT = 14,
151 NVME_CC_IOSQES_SHIFT = 16,
152 NVME_CC_IOCQES_SHIFT = 20,
153 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
154 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
155 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
156 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
157 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
158 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
159 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
160 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
161 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
162 NVME_CSTS_RDY = 1 << 0,
163 NVME_CSTS_CFS = 1 << 1,
164 NVME_CSTS_NSSRO = 1 << 4,
165 NVME_CSTS_PP = 1 << 5,
166 NVME_CSTS_SHST_NORMAL = 0 << 2,
167 NVME_CSTS_SHST_OCCUR = 1 << 2,
168 NVME_CSTS_SHST_CMPLT = 2 << 2,
169 NVME_CSTS_SHST_MASK = 3 << 2,
170 };
171
172 struct nvme_id_power_state {
173 __le16 max_power; /* centiwatts */
174 __u8 rsvd2;
175 __u8 flags;
176 __le32 entry_lat; /* microseconds */
177 __le32 exit_lat; /* microseconds */
178 __u8 read_tput;
179 __u8 read_lat;
180 __u8 write_tput;
181 __u8 write_lat;
182 __le16 idle_power;
183 __u8 idle_scale;
184 __u8 rsvd19;
185 __le16 active_power;
186 __u8 active_work_scale;
187 __u8 rsvd23[9];
188 };
189
190 enum {
191 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
192 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
193 };
194
195 struct nvme_id_ctrl {
196 __le16 vid;
197 __le16 ssvid;
198 char sn[20];
199 char mn[40];
200 char fr[8];
201 __u8 rab;
202 __u8 ieee[3];
203 __u8 cmic;
204 __u8 mdts;
205 __le16 cntlid;
206 __le32 ver;
207 __le32 rtd3r;
208 __le32 rtd3e;
209 __le32 oaes;
210 __le32 ctratt;
211 __u8 rsvd100[156];
212 __le16 oacs;
213 __u8 acl;
214 __u8 aerl;
215 __u8 frmw;
216 __u8 lpa;
217 __u8 elpe;
218 __u8 npss;
219 __u8 avscc;
220 __u8 apsta;
221 __le16 wctemp;
222 __le16 cctemp;
223 __le16 mtfa;
224 __le32 hmpre;
225 __le32 hmmin;
226 __u8 tnvmcap[16];
227 __u8 unvmcap[16];
228 __le32 rpmbs;
229 __le16 edstt;
230 __u8 dsto;
231 __u8 fwug;
232 __le16 kas;
233 __le16 hctma;
234 __le16 mntmt;
235 __le16 mxtmt;
236 __le32 sanicap;
237 __le32 hmminds;
238 __le16 hmmaxd;
239 __u8 rsvd338[174];
240 __u8 sqes;
241 __u8 cqes;
242 __le16 maxcmd;
243 __le32 nn;
244 __le16 oncs;
245 __le16 fuses;
246 __u8 fna;
247 __u8 vwc;
248 __le16 awun;
249 __le16 awupf;
250 __u8 nvscc;
251 __u8 rsvd531;
252 __le16 acwu;
253 __u8 rsvd534[2];
254 __le32 sgls;
255 __u8 rsvd540[228];
256 char subnqn[256];
257 __u8 rsvd1024[768];
258 __le32 ioccsz;
259 __le32 iorcsz;
260 __le16 icdoff;
261 __u8 ctrattr;
262 __u8 msdbd;
263 __u8 rsvd1804[244];
264 struct nvme_id_power_state psd[32];
265 __u8 vs[1024];
266 };
267
268 enum {
269 NVME_CTRL_ONCS_COMPARE = 1 << 0,
270 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
271 NVME_CTRL_ONCS_DSM = 1 << 2,
272 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
273 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
274 NVME_CTRL_VWC_PRESENT = 1 << 0,
275 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
276 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
277 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
278 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
279 };
280
281 struct nvme_lbaf {
282 __le16 ms;
283 __u8 ds;
284 __u8 rp;
285 };
286
287 struct nvme_id_ns {
288 __le64 nsze;
289 __le64 ncap;
290 __le64 nuse;
291 __u8 nsfeat;
292 __u8 nlbaf;
293 __u8 flbas;
294 __u8 mc;
295 __u8 dpc;
296 __u8 dps;
297 __u8 nmic;
298 __u8 rescap;
299 __u8 fpi;
300 __u8 rsvd33;
301 __le16 nawun;
302 __le16 nawupf;
303 __le16 nacwu;
304 __le16 nabsn;
305 __le16 nabo;
306 __le16 nabspf;
307 __le16 noiob;
308 __u8 nvmcap[16];
309 __u8 rsvd64[40];
310 __u8 nguid[16];
311 __u8 eui64[8];
312 struct nvme_lbaf lbaf[16];
313 __u8 rsvd192[192];
314 __u8 vs[3712];
315 };
316
317 enum {
318 NVME_ID_CNS_NS = 0x00,
319 NVME_ID_CNS_CTRL = 0x01,
320 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
321 NVME_ID_CNS_NS_DESC_LIST = 0x03,
322 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
323 NVME_ID_CNS_NS_PRESENT = 0x11,
324 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
325 NVME_ID_CNS_CTRL_LIST = 0x13,
326 };
327
328 enum {
329 NVME_DIR_IDENTIFY = 0x00,
330 NVME_DIR_STREAMS = 0x01,
331 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
332 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
333 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
334 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
335 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
336 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
337 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
338 NVME_DIR_ENDIR = 0x01,
339 };
340
341 enum {
342 NVME_NS_FEAT_THIN = 1 << 0,
343 NVME_NS_FLBAS_LBA_MASK = 0xf,
344 NVME_NS_FLBAS_META_EXT = 0x10,
345 NVME_LBAF_RP_BEST = 0,
346 NVME_LBAF_RP_BETTER = 1,
347 NVME_LBAF_RP_GOOD = 2,
348 NVME_LBAF_RP_DEGRADED = 3,
349 NVME_NS_DPC_PI_LAST = 1 << 4,
350 NVME_NS_DPC_PI_FIRST = 1 << 3,
351 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
352 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
353 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
354 NVME_NS_DPS_PI_FIRST = 1 << 3,
355 NVME_NS_DPS_PI_MASK = 0x7,
356 NVME_NS_DPS_PI_TYPE1 = 1,
357 NVME_NS_DPS_PI_TYPE2 = 2,
358 NVME_NS_DPS_PI_TYPE3 = 3,
359 };
360
361 struct nvme_ns_id_desc {
362 __u8 nidt;
363 __u8 nidl;
364 __le16 reserved;
365 };
366
367 #define NVME_NIDT_EUI64_LEN 8
368 #define NVME_NIDT_NGUID_LEN 16
369 #define NVME_NIDT_UUID_LEN 16
370
371 enum {
372 NVME_NIDT_EUI64 = 0x01,
373 NVME_NIDT_NGUID = 0x02,
374 NVME_NIDT_UUID = 0x03,
375 };
376
377 struct nvme_smart_log {
378 __u8 critical_warning;
379 __u8 temperature[2];
380 __u8 avail_spare;
381 __u8 spare_thresh;
382 __u8 percent_used;
383 __u8 rsvd6[26];
384 __u8 data_units_read[16];
385 __u8 data_units_written[16];
386 __u8 host_reads[16];
387 __u8 host_writes[16];
388 __u8 ctrl_busy_time[16];
389 __u8 power_cycles[16];
390 __u8 power_on_hours[16];
391 __u8 unsafe_shutdowns[16];
392 __u8 media_errors[16];
393 __u8 num_err_log_entries[16];
394 __le32 warning_temp_time;
395 __le32 critical_comp_time;
396 __le16 temp_sensor[8];
397 __u8 rsvd216[296];
398 };
399
400 struct nvme_fw_slot_info_log {
401 __u8 afi;
402 __u8 rsvd1[7];
403 __le64 frs[7];
404 __u8 rsvd64[448];
405 };
406
407 enum {
408 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
409 NVME_CMD_EFFECTS_LBCC = 1 << 1,
410 NVME_CMD_EFFECTS_NCC = 1 << 2,
411 NVME_CMD_EFFECTS_NIC = 1 << 3,
412 NVME_CMD_EFFECTS_CCC = 1 << 4,
413 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
414 };
415
416 struct nvme_effects_log {
417 __le32 acs[256];
418 __le32 iocs[256];
419 __u8 resv[2048];
420 };
421
422 enum {
423 NVME_SMART_CRIT_SPARE = 1 << 0,
424 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
425 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
426 NVME_SMART_CRIT_MEDIA = 1 << 3,
427 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
428 };
429
430 enum {
431 NVME_AER_ERROR = 0,
432 NVME_AER_SMART = 1,
433 NVME_AER_CSS = 6,
434 NVME_AER_VS = 7,
435 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
436 NVME_AER_NOTICE_FW_ACT_STARTING = 0x0102,
437 };
438
439 struct nvme_lba_range_type {
440 __u8 type;
441 __u8 attributes;
442 __u8 rsvd2[14];
443 __u64 slba;
444 __u64 nlb;
445 __u8 guid[16];
446 __u8 rsvd48[16];
447 };
448
449 enum {
450 NVME_LBART_TYPE_FS = 0x01,
451 NVME_LBART_TYPE_RAID = 0x02,
452 NVME_LBART_TYPE_CACHE = 0x03,
453 NVME_LBART_TYPE_SWAP = 0x04,
454
455 NVME_LBART_ATTRIB_TEMP = 1 << 0,
456 NVME_LBART_ATTRIB_HIDE = 1 << 1,
457 };
458
459 struct nvme_reservation_status {
460 __le32 gen;
461 __u8 rtype;
462 __u8 regctl[2];
463 __u8 resv5[2];
464 __u8 ptpls;
465 __u8 resv10[13];
466 struct {
467 __le16 cntlid;
468 __u8 rcsts;
469 __u8 resv3[5];
470 __le64 hostid;
471 __le64 rkey;
472 } regctl_ds[];
473 };
474
475 enum nvme_async_event_type {
476 NVME_AER_TYPE_ERROR = 0,
477 NVME_AER_TYPE_SMART = 1,
478 NVME_AER_TYPE_NOTICE = 2,
479 };
480
481 /* I/O commands */
482
483 enum nvme_opcode {
484 nvme_cmd_flush = 0x00,
485 nvme_cmd_write = 0x01,
486 nvme_cmd_read = 0x02,
487 nvme_cmd_write_uncor = 0x04,
488 nvme_cmd_compare = 0x05,
489 nvme_cmd_write_zeroes = 0x08,
490 nvme_cmd_dsm = 0x09,
491 nvme_cmd_resv_register = 0x0d,
492 nvme_cmd_resv_report = 0x0e,
493 nvme_cmd_resv_acquire = 0x11,
494 nvme_cmd_resv_release = 0x15,
495 };
496
497 /*
498 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
499 *
500 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
501 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
502 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
503 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
504 * request subtype
505 */
506 enum {
507 NVME_SGL_FMT_ADDRESS = 0x00,
508 NVME_SGL_FMT_OFFSET = 0x01,
509 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
510 NVME_SGL_FMT_INVALIDATE = 0x0f,
511 };
512
513 /*
514 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
515 *
516 * For struct nvme_sgl_desc:
517 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
518 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
519 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
520 *
521 * For struct nvme_keyed_sgl_desc:
522 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
523 *
524 * Transport-specific SGL types:
525 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
526 */
527 enum {
528 NVME_SGL_FMT_DATA_DESC = 0x00,
529 NVME_SGL_FMT_SEG_DESC = 0x02,
530 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
531 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
532 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
533 };
534
535 struct nvme_sgl_desc {
536 __le64 addr;
537 __le32 length;
538 __u8 rsvd[3];
539 __u8 type;
540 };
541
542 struct nvme_keyed_sgl_desc {
543 __le64 addr;
544 __u8 length[3];
545 __u8 key[4];
546 __u8 type;
547 };
548
549 union nvme_data_ptr {
550 struct {
551 __le64 prp1;
552 __le64 prp2;
553 };
554 struct nvme_sgl_desc sgl;
555 struct nvme_keyed_sgl_desc ksgl;
556 };
557
558 /*
559 * Lowest two bits of our flags field (FUSE field in the spec):
560 *
561 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
562 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
563 *
564 * Highest two bits in our flags field (PSDT field in the spec):
565 *
566 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
567 * If used, MPTR contains addr of single physical buffer (byte aligned).
568 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
569 * If used, MPTR contains an address of an SGL segment containing
570 * exactly 1 SGL descriptor (qword aligned).
571 */
572 enum {
573 NVME_CMD_FUSE_FIRST = (1 << 0),
574 NVME_CMD_FUSE_SECOND = (1 << 1),
575
576 NVME_CMD_SGL_METABUF = (1 << 6),
577 NVME_CMD_SGL_METASEG = (1 << 7),
578 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
579 };
580
581 struct nvme_common_command {
582 __u8 opcode;
583 __u8 flags;
584 __u16 command_id;
585 __le32 nsid;
586 __le32 cdw2[2];
587 __le64 metadata;
588 union nvme_data_ptr dptr;
589 __le32 cdw10[6];
590 };
591
592 struct nvme_rw_command {
593 __u8 opcode;
594 __u8 flags;
595 __u16 command_id;
596 __le32 nsid;
597 __u64 rsvd2;
598 __le64 metadata;
599 union nvme_data_ptr dptr;
600 __le64 slba;
601 __le16 length;
602 __le16 control;
603 __le32 dsmgmt;
604 __le32 reftag;
605 __le16 apptag;
606 __le16 appmask;
607 };
608
609 enum {
610 NVME_RW_LR = 1 << 15,
611 NVME_RW_FUA = 1 << 14,
612 NVME_RW_DSM_FREQ_UNSPEC = 0,
613 NVME_RW_DSM_FREQ_TYPICAL = 1,
614 NVME_RW_DSM_FREQ_RARE = 2,
615 NVME_RW_DSM_FREQ_READS = 3,
616 NVME_RW_DSM_FREQ_WRITES = 4,
617 NVME_RW_DSM_FREQ_RW = 5,
618 NVME_RW_DSM_FREQ_ONCE = 6,
619 NVME_RW_DSM_FREQ_PREFETCH = 7,
620 NVME_RW_DSM_FREQ_TEMP = 8,
621 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
622 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
623 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
624 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
625 NVME_RW_DSM_SEQ_REQ = 1 << 6,
626 NVME_RW_DSM_COMPRESSED = 1 << 7,
627 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
628 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
629 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
630 NVME_RW_PRINFO_PRACT = 1 << 13,
631 NVME_RW_DTYPE_STREAMS = 1 << 4,
632 };
633
634 struct nvme_dsm_cmd {
635 __u8 opcode;
636 __u8 flags;
637 __u16 command_id;
638 __le32 nsid;
639 __u64 rsvd2[2];
640 union nvme_data_ptr dptr;
641 __le32 nr;
642 __le32 attributes;
643 __u32 rsvd12[4];
644 };
645
646 enum {
647 NVME_DSMGMT_IDR = 1 << 0,
648 NVME_DSMGMT_IDW = 1 << 1,
649 NVME_DSMGMT_AD = 1 << 2,
650 };
651
652 #define NVME_DSM_MAX_RANGES 256
653
654 struct nvme_dsm_range {
655 __le32 cattr;
656 __le32 nlb;
657 __le64 slba;
658 };
659
660 struct nvme_write_zeroes_cmd {
661 __u8 opcode;
662 __u8 flags;
663 __u16 command_id;
664 __le32 nsid;
665 __u64 rsvd2;
666 __le64 metadata;
667 union nvme_data_ptr dptr;
668 __le64 slba;
669 __le16 length;
670 __le16 control;
671 __le32 dsmgmt;
672 __le32 reftag;
673 __le16 apptag;
674 __le16 appmask;
675 };
676
677 /* Features */
678
679 struct nvme_feat_auto_pst {
680 __le64 entries[32];
681 };
682
683 enum {
684 NVME_HOST_MEM_ENABLE = (1 << 0),
685 NVME_HOST_MEM_RETURN = (1 << 1),
686 };
687
688 /* Admin commands */
689
690 enum nvme_admin_opcode {
691 nvme_admin_delete_sq = 0x00,
692 nvme_admin_create_sq = 0x01,
693 nvme_admin_get_log_page = 0x02,
694 nvme_admin_delete_cq = 0x04,
695 nvme_admin_create_cq = 0x05,
696 nvme_admin_identify = 0x06,
697 nvme_admin_abort_cmd = 0x08,
698 nvme_admin_set_features = 0x09,
699 nvme_admin_get_features = 0x0a,
700 nvme_admin_async_event = 0x0c,
701 nvme_admin_ns_mgmt = 0x0d,
702 nvme_admin_activate_fw = 0x10,
703 nvme_admin_download_fw = 0x11,
704 nvme_admin_ns_attach = 0x15,
705 nvme_admin_keep_alive = 0x18,
706 nvme_admin_directive_send = 0x19,
707 nvme_admin_directive_recv = 0x1a,
708 nvme_admin_dbbuf = 0x7C,
709 nvme_admin_format_nvm = 0x80,
710 nvme_admin_security_send = 0x81,
711 nvme_admin_security_recv = 0x82,
712 nvme_admin_sanitize_nvm = 0x84,
713 };
714
715 enum {
716 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
717 NVME_CQ_IRQ_ENABLED = (1 << 1),
718 NVME_SQ_PRIO_URGENT = (0 << 1),
719 NVME_SQ_PRIO_HIGH = (1 << 1),
720 NVME_SQ_PRIO_MEDIUM = (2 << 1),
721 NVME_SQ_PRIO_LOW = (3 << 1),
722 NVME_FEAT_ARBITRATION = 0x01,
723 NVME_FEAT_POWER_MGMT = 0x02,
724 NVME_FEAT_LBA_RANGE = 0x03,
725 NVME_FEAT_TEMP_THRESH = 0x04,
726 NVME_FEAT_ERR_RECOVERY = 0x05,
727 NVME_FEAT_VOLATILE_WC = 0x06,
728 NVME_FEAT_NUM_QUEUES = 0x07,
729 NVME_FEAT_IRQ_COALESCE = 0x08,
730 NVME_FEAT_IRQ_CONFIG = 0x09,
731 NVME_FEAT_WRITE_ATOMIC = 0x0a,
732 NVME_FEAT_ASYNC_EVENT = 0x0b,
733 NVME_FEAT_AUTO_PST = 0x0c,
734 NVME_FEAT_HOST_MEM_BUF = 0x0d,
735 NVME_FEAT_TIMESTAMP = 0x0e,
736 NVME_FEAT_KATO = 0x0f,
737 NVME_FEAT_SW_PROGRESS = 0x80,
738 NVME_FEAT_HOST_ID = 0x81,
739 NVME_FEAT_RESV_MASK = 0x82,
740 NVME_FEAT_RESV_PERSIST = 0x83,
741 NVME_LOG_ERROR = 0x01,
742 NVME_LOG_SMART = 0x02,
743 NVME_LOG_FW_SLOT = 0x03,
744 NVME_LOG_CMD_EFFECTS = 0x05,
745 NVME_LOG_DISC = 0x70,
746 NVME_LOG_RESERVATION = 0x80,
747 NVME_FWACT_REPL = (0 << 3),
748 NVME_FWACT_REPL_ACTV = (1 << 3),
749 NVME_FWACT_ACTV = (2 << 3),
750 };
751
752 struct nvme_identify {
753 __u8 opcode;
754 __u8 flags;
755 __u16 command_id;
756 __le32 nsid;
757 __u64 rsvd2[2];
758 union nvme_data_ptr dptr;
759 __u8 cns;
760 __u8 rsvd3;
761 __le16 ctrlid;
762 __u32 rsvd11[5];
763 };
764
765 #define NVME_IDENTIFY_DATA_SIZE 4096
766
767 struct nvme_features {
768 __u8 opcode;
769 __u8 flags;
770 __u16 command_id;
771 __le32 nsid;
772 __u64 rsvd2[2];
773 union nvme_data_ptr dptr;
774 __le32 fid;
775 __le32 dword11;
776 __le32 dword12;
777 __le32 dword13;
778 __le32 dword14;
779 __le32 dword15;
780 };
781
782 struct nvme_host_mem_buf_desc {
783 __le64 addr;
784 __le32 size;
785 __u32 rsvd;
786 };
787
788 struct nvme_create_cq {
789 __u8 opcode;
790 __u8 flags;
791 __u16 command_id;
792 __u32 rsvd1[5];
793 __le64 prp1;
794 __u64 rsvd8;
795 __le16 cqid;
796 __le16 qsize;
797 __le16 cq_flags;
798 __le16 irq_vector;
799 __u32 rsvd12[4];
800 };
801
802 struct nvme_create_sq {
803 __u8 opcode;
804 __u8 flags;
805 __u16 command_id;
806 __u32 rsvd1[5];
807 __le64 prp1;
808 __u64 rsvd8;
809 __le16 sqid;
810 __le16 qsize;
811 __le16 sq_flags;
812 __le16 cqid;
813 __u32 rsvd12[4];
814 };
815
816 struct nvme_delete_queue {
817 __u8 opcode;
818 __u8 flags;
819 __u16 command_id;
820 __u32 rsvd1[9];
821 __le16 qid;
822 __u16 rsvd10;
823 __u32 rsvd11[5];
824 };
825
826 struct nvme_abort_cmd {
827 __u8 opcode;
828 __u8 flags;
829 __u16 command_id;
830 __u32 rsvd1[9];
831 __le16 sqid;
832 __u16 cid;
833 __u32 rsvd11[5];
834 };
835
836 struct nvme_download_firmware {
837 __u8 opcode;
838 __u8 flags;
839 __u16 command_id;
840 __u32 rsvd1[5];
841 union nvme_data_ptr dptr;
842 __le32 numd;
843 __le32 offset;
844 __u32 rsvd12[4];
845 };
846
847 struct nvme_format_cmd {
848 __u8 opcode;
849 __u8 flags;
850 __u16 command_id;
851 __le32 nsid;
852 __u64 rsvd2[4];
853 __le32 cdw10;
854 __u32 rsvd11[5];
855 };
856
857 struct nvme_get_log_page_command {
858 __u8 opcode;
859 __u8 flags;
860 __u16 command_id;
861 __le32 nsid;
862 __u64 rsvd2[2];
863 union nvme_data_ptr dptr;
864 __u8 lid;
865 __u8 rsvd10;
866 __le16 numdl;
867 __le16 numdu;
868 __u16 rsvd11;
869 __le32 lpol;
870 __le32 lpou;
871 __u32 rsvd14[2];
872 };
873
874 struct nvme_directive_cmd {
875 __u8 opcode;
876 __u8 flags;
877 __u16 command_id;
878 __le32 nsid;
879 __u64 rsvd2[2];
880 union nvme_data_ptr dptr;
881 __le32 numd;
882 __u8 doper;
883 __u8 dtype;
884 __le16 dspec;
885 __u8 endir;
886 __u8 tdtype;
887 __u16 rsvd15;
888
889 __u32 rsvd16[3];
890 };
891
892 /*
893 * Fabrics subcommands.
894 */
895 enum nvmf_fabrics_opcode {
896 nvme_fabrics_command = 0x7f,
897 };
898
899 enum nvmf_capsule_command {
900 nvme_fabrics_type_property_set = 0x00,
901 nvme_fabrics_type_connect = 0x01,
902 nvme_fabrics_type_property_get = 0x04,
903 };
904
905 struct nvmf_common_command {
906 __u8 opcode;
907 __u8 resv1;
908 __u16 command_id;
909 __u8 fctype;
910 __u8 resv2[35];
911 __u8 ts[24];
912 };
913
914 /*
915 * The legal cntlid range a NVMe Target will provide.
916 * Note that cntlid of value 0 is considered illegal in the fabrics world.
917 * Devices based on earlier specs did not have the subsystem concept;
918 * therefore, those devices had their cntlid value set to 0 as a result.
919 */
920 #define NVME_CNTLID_MIN 1
921 #define NVME_CNTLID_MAX 0xffef
922 #define NVME_CNTLID_DYNAMIC 0xffff
923
924 #define MAX_DISC_LOGS 255
925
926 /* Discovery log page entry */
927 struct nvmf_disc_rsp_page_entry {
928 __u8 trtype;
929 __u8 adrfam;
930 __u8 subtype;
931 __u8 treq;
932 __le16 portid;
933 __le16 cntlid;
934 __le16 asqsz;
935 __u8 resv8[22];
936 char trsvcid[NVMF_TRSVCID_SIZE];
937 __u8 resv64[192];
938 char subnqn[NVMF_NQN_FIELD_LEN];
939 char traddr[NVMF_TRADDR_SIZE];
940 union tsas {
941 char common[NVMF_TSAS_SIZE];
942 struct rdma {
943 __u8 qptype;
944 __u8 prtype;
945 __u8 cms;
946 __u8 resv3[5];
947 __u16 pkey;
948 __u8 resv10[246];
949 } rdma;
950 } tsas;
951 };
952
953 /* Discovery log page header */
954 struct nvmf_disc_rsp_page_hdr {
955 __le64 genctr;
956 __le64 numrec;
957 __le16 recfmt;
958 __u8 resv14[1006];
959 struct nvmf_disc_rsp_page_entry entries[0];
960 };
961
962 struct nvmf_connect_command {
963 __u8 opcode;
964 __u8 resv1;
965 __u16 command_id;
966 __u8 fctype;
967 __u8 resv2[19];
968 union nvme_data_ptr dptr;
969 __le16 recfmt;
970 __le16 qid;
971 __le16 sqsize;
972 __u8 cattr;
973 __u8 resv3;
974 __le32 kato;
975 __u8 resv4[12];
976 };
977
978 struct nvmf_connect_data {
979 uuid_t hostid;
980 __le16 cntlid;
981 char resv4[238];
982 char subsysnqn[NVMF_NQN_FIELD_LEN];
983 char hostnqn[NVMF_NQN_FIELD_LEN];
984 char resv5[256];
985 };
986
987 struct nvmf_property_set_command {
988 __u8 opcode;
989 __u8 resv1;
990 __u16 command_id;
991 __u8 fctype;
992 __u8 resv2[35];
993 __u8 attrib;
994 __u8 resv3[3];
995 __le32 offset;
996 __le64 value;
997 __u8 resv4[8];
998 };
999
1000 struct nvmf_property_get_command {
1001 __u8 opcode;
1002 __u8 resv1;
1003 __u16 command_id;
1004 __u8 fctype;
1005 __u8 resv2[35];
1006 __u8 attrib;
1007 __u8 resv3[3];
1008 __le32 offset;
1009 __u8 resv4[16];
1010 };
1011
1012 struct nvme_dbbuf {
1013 __u8 opcode;
1014 __u8 flags;
1015 __u16 command_id;
1016 __u32 rsvd1[5];
1017 __le64 prp1;
1018 __le64 prp2;
1019 __u32 rsvd12[6];
1020 };
1021
1022 struct streams_directive_params {
1023 __le16 msl;
1024 __le16 nssa;
1025 __le16 nsso;
1026 __u8 rsvd[10];
1027 __le32 sws;
1028 __le16 sgs;
1029 __le16 nsa;
1030 __le16 nso;
1031 __u8 rsvd2[6];
1032 };
1033
1034 struct nvme_command {
1035 union {
1036 struct nvme_common_command common;
1037 struct nvme_rw_command rw;
1038 struct nvme_identify identify;
1039 struct nvme_features features;
1040 struct nvme_create_cq create_cq;
1041 struct nvme_create_sq create_sq;
1042 struct nvme_delete_queue delete_queue;
1043 struct nvme_download_firmware dlfw;
1044 struct nvme_format_cmd format;
1045 struct nvme_dsm_cmd dsm;
1046 struct nvme_write_zeroes_cmd write_zeroes;
1047 struct nvme_abort_cmd abort;
1048 struct nvme_get_log_page_command get_log_page;
1049 struct nvmf_common_command fabrics;
1050 struct nvmf_connect_command connect;
1051 struct nvmf_property_set_command prop_set;
1052 struct nvmf_property_get_command prop_get;
1053 struct nvme_dbbuf dbbuf;
1054 struct nvme_directive_cmd directive;
1055 };
1056 };
1057
1058 static inline bool nvme_is_write(struct nvme_command *cmd)
1059 {
1060 /*
1061 * What a mess...
1062 *
1063 * Why can't we simply have a Fabrics In and Fabrics out command?
1064 */
1065 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1066 return cmd->fabrics.fctype & 1;
1067 return cmd->common.opcode & 1;
1068 }
1069
1070 enum {
1071 /*
1072 * Generic Command Status:
1073 */
1074 NVME_SC_SUCCESS = 0x0,
1075 NVME_SC_INVALID_OPCODE = 0x1,
1076 NVME_SC_INVALID_FIELD = 0x2,
1077 NVME_SC_CMDID_CONFLICT = 0x3,
1078 NVME_SC_DATA_XFER_ERROR = 0x4,
1079 NVME_SC_POWER_LOSS = 0x5,
1080 NVME_SC_INTERNAL = 0x6,
1081 NVME_SC_ABORT_REQ = 0x7,
1082 NVME_SC_ABORT_QUEUE = 0x8,
1083 NVME_SC_FUSED_FAIL = 0x9,
1084 NVME_SC_FUSED_MISSING = 0xa,
1085 NVME_SC_INVALID_NS = 0xb,
1086 NVME_SC_CMD_SEQ_ERROR = 0xc,
1087 NVME_SC_SGL_INVALID_LAST = 0xd,
1088 NVME_SC_SGL_INVALID_COUNT = 0xe,
1089 NVME_SC_SGL_INVALID_DATA = 0xf,
1090 NVME_SC_SGL_INVALID_METADATA = 0x10,
1091 NVME_SC_SGL_INVALID_TYPE = 0x11,
1092
1093 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1094 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1095
1096 NVME_SC_LBA_RANGE = 0x80,
1097 NVME_SC_CAP_EXCEEDED = 0x81,
1098 NVME_SC_NS_NOT_READY = 0x82,
1099 NVME_SC_RESERVATION_CONFLICT = 0x83,
1100
1101 /*
1102 * Command Specific Status:
1103 */
1104 NVME_SC_CQ_INVALID = 0x100,
1105 NVME_SC_QID_INVALID = 0x101,
1106 NVME_SC_QUEUE_SIZE = 0x102,
1107 NVME_SC_ABORT_LIMIT = 0x103,
1108 NVME_SC_ABORT_MISSING = 0x104,
1109 NVME_SC_ASYNC_LIMIT = 0x105,
1110 NVME_SC_FIRMWARE_SLOT = 0x106,
1111 NVME_SC_FIRMWARE_IMAGE = 0x107,
1112 NVME_SC_INVALID_VECTOR = 0x108,
1113 NVME_SC_INVALID_LOG_PAGE = 0x109,
1114 NVME_SC_INVALID_FORMAT = 0x10a,
1115 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1116 NVME_SC_INVALID_QUEUE = 0x10c,
1117 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1118 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1119 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1120 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1121 NVME_SC_FW_NEEDS_RESET = 0x111,
1122 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1123 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1124 NVME_SC_OVERLAPPING_RANGE = 0x114,
1125 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1126 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1127 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1128 NVME_SC_NS_IS_PRIVATE = 0x119,
1129 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1130 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1131 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1132
1133 /*
1134 * I/O Command Set Specific - NVM commands:
1135 */
1136 NVME_SC_BAD_ATTRIBUTES = 0x180,
1137 NVME_SC_INVALID_PI = 0x181,
1138 NVME_SC_READ_ONLY = 0x182,
1139 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1140
1141 /*
1142 * I/O Command Set Specific - Fabrics commands:
1143 */
1144 NVME_SC_CONNECT_FORMAT = 0x180,
1145 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1146 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1147 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1148 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1149
1150 NVME_SC_DISCOVERY_RESTART = 0x190,
1151 NVME_SC_AUTH_REQUIRED = 0x191,
1152
1153 /*
1154 * Media and Data Integrity Errors:
1155 */
1156 NVME_SC_WRITE_FAULT = 0x280,
1157 NVME_SC_READ_ERROR = 0x281,
1158 NVME_SC_GUARD_CHECK = 0x282,
1159 NVME_SC_APPTAG_CHECK = 0x283,
1160 NVME_SC_REFTAG_CHECK = 0x284,
1161 NVME_SC_COMPARE_FAILED = 0x285,
1162 NVME_SC_ACCESS_DENIED = 0x286,
1163 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1164
1165 NVME_SC_DNR = 0x4000,
1166 };
1167
1168 struct nvme_completion {
1169 /*
1170 * Used by Admin and Fabrics commands to return data:
1171 */
1172 union nvme_result {
1173 __le16 u16;
1174 __le32 u32;
1175 __le64 u64;
1176 } result;
1177 __le16 sq_head; /* how much of this queue may be reclaimed */
1178 __le16 sq_id; /* submission queue that generated this entry */
1179 __u16 command_id; /* of the command which completed */
1180 __le16 status; /* did the command fail, and if so, why? */
1181 };
1182
1183 #define NVME_VS(major, minor, tertiary) \
1184 (((major) << 16) | ((minor) << 8) | (tertiary))
1185
1186 #define NVME_MAJOR(ver) ((ver) >> 16)
1187 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1188 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1189
1190 #endif /* _LINUX_NVME_H */
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