2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 #include <linux/types.h>
20 /* NQN names in commands fields specified one size */
21 #define NVMF_NQN_FIELD_LEN 256
23 /* However the max length of a qualified name is another size */
24 #define NVMF_NQN_SIZE 223
26 #define NVMF_TRSVCID_SIZE 32
27 #define NVMF_TRADDR_SIZE 256
28 #define NVMF_TSAS_SIZE 256
30 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32 #define NVME_RDMA_IP_PORT 4420
34 enum nvme_subsys_type
{
35 NVME_NQN_DISC
= 1, /* Discovery type target subsystem */
36 NVME_NQN_NVME
= 2, /* NVME type target subsystem */
39 /* Address Family codes for Discovery Log Page entry ADRFAM field */
41 NVMF_ADDR_FAMILY_PCI
= 0, /* PCIe */
42 NVMF_ADDR_FAMILY_IP4
= 1, /* IP4 */
43 NVMF_ADDR_FAMILY_IP6
= 2, /* IP6 */
44 NVMF_ADDR_FAMILY_IB
= 3, /* InfiniBand */
45 NVMF_ADDR_FAMILY_FC
= 4, /* Fibre Channel */
48 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
50 NVMF_TRTYPE_RDMA
= 1, /* RDMA */
51 NVMF_TRTYPE_FC
= 2, /* Fibre Channel */
52 NVMF_TRTYPE_LOOP
= 254, /* Reserved for host usage */
56 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
58 NVMF_TREQ_NOT_SPECIFIED
= 0, /* Not specified */
59 NVMF_TREQ_REQUIRED
= 1, /* Required */
60 NVMF_TREQ_NOT_REQUIRED
= 2, /* Not Required */
63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 NVMF_RDMA_QPTYPE_CONNECTED
= 1, /* Reliable Connected */
68 NVMF_RDMA_QPTYPE_DATAGRAM
= 2, /* Reliable Datagram */
71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED
= 1, /* No Provider Specified */
76 NVMF_RDMA_PRTYPE_IB
= 2, /* InfiniBand */
77 NVMF_RDMA_PRTYPE_ROCE
= 3, /* InfiniBand RoCE */
78 NVMF_RDMA_PRTYPE_ROCEV2
= 4, /* InfiniBand RoCEV2 */
79 NVMF_RDMA_PRTYPE_IWARP
= 5, /* IWARP */
82 /* RDMA Connection Management Service Type codes for Discovery Log Page
83 * entry TSAS RDMA_CMS field
86 NVMF_RDMA_CMS_RDMA_CM
= 1, /* Sockets based endpoint addressing */
89 #define NVMF_AQ_DEPTH 32
92 NVME_REG_CAP
= 0x0000, /* Controller Capabilities */
93 NVME_REG_VS
= 0x0008, /* Version */
94 NVME_REG_INTMS
= 0x000c, /* Interrupt Mask Set */
95 NVME_REG_INTMC
= 0x0010, /* Interrupt Mask Clear */
96 NVME_REG_CC
= 0x0014, /* Controller Configuration */
97 NVME_REG_CSTS
= 0x001c, /* Controller Status */
98 NVME_REG_NSSR
= 0x0020, /* NVM Subsystem Reset */
99 NVME_REG_AQA
= 0x0024, /* Admin Queue Attributes */
100 NVME_REG_ASQ
= 0x0028, /* Admin SQ Base Address */
101 NVME_REG_ACQ
= 0x0030, /* Admin CQ Base Address */
102 NVME_REG_CMBLOC
= 0x0038, /* Controller Memory Buffer Location */
103 NVME_REG_CMBSZ
= 0x003c, /* Controller Memory Buffer Size */
106 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
107 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
108 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
109 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
110 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
111 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
113 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
114 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
115 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
116 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
118 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
119 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
120 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
121 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
122 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
125 * Submission and Completion Queue Entry Sizes for the NVM command set.
126 * (In bytes and specified as a power of two (2^n)).
128 #define NVME_NVM_IOSQES 6
129 #define NVME_NVM_IOCQES 4
132 NVME_CC_ENABLE
= 1 << 0,
133 NVME_CC_CSS_NVM
= 0 << 4,
134 NVME_CC_MPS_SHIFT
= 7,
135 NVME_CC_ARB_RR
= 0 << 11,
136 NVME_CC_ARB_WRRU
= 1 << 11,
137 NVME_CC_ARB_VS
= 7 << 11,
138 NVME_CC_SHN_NONE
= 0 << 14,
139 NVME_CC_SHN_NORMAL
= 1 << 14,
140 NVME_CC_SHN_ABRUPT
= 2 << 14,
141 NVME_CC_SHN_MASK
= 3 << 14,
142 NVME_CC_IOSQES
= NVME_NVM_IOSQES
<< 16,
143 NVME_CC_IOCQES
= NVME_NVM_IOCQES
<< 20,
144 NVME_CSTS_RDY
= 1 << 0,
145 NVME_CSTS_CFS
= 1 << 1,
146 NVME_CSTS_NSSRO
= 1 << 4,
147 NVME_CSTS_SHST_NORMAL
= 0 << 2,
148 NVME_CSTS_SHST_OCCUR
= 1 << 2,
149 NVME_CSTS_SHST_CMPLT
= 2 << 2,
150 NVME_CSTS_SHST_MASK
= 3 << 2,
153 struct nvme_id_power_state
{
154 __le16 max_power
; /* centiwatts */
157 __le32 entry_lat
; /* microseconds */
158 __le32 exit_lat
; /* microseconds */
167 __u8 active_work_scale
;
172 NVME_PS_FLAGS_MAX_POWER_SCALE
= 1 << 0,
173 NVME_PS_FLAGS_NON_OP_STATE
= 1 << 1,
176 struct nvme_id_ctrl
{
237 struct nvme_id_power_state psd
[32];
242 NVME_CTRL_ONCS_COMPARE
= 1 << 0,
243 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE
= 1 << 1,
244 NVME_CTRL_ONCS_DSM
= 1 << 2,
245 NVME_CTRL_ONCS_WRITE_ZEROES
= 1 << 3,
246 NVME_CTRL_VWC_PRESENT
= 1 << 0,
247 NVME_CTRL_OACS_SEC_SUPP
= 1 << 0,
248 NVME_CTRL_OACS_DBBUF_SUPP
= 1 << 7,
282 struct nvme_lbaf lbaf
[16];
288 NVME_ID_CNS_NS
= 0x00,
289 NVME_ID_CNS_CTRL
= 0x01,
290 NVME_ID_CNS_NS_ACTIVE_LIST
= 0x02,
291 NVME_ID_CNS_NS_PRESENT_LIST
= 0x10,
292 NVME_ID_CNS_NS_PRESENT
= 0x11,
293 NVME_ID_CNS_CTRL_NS_LIST
= 0x12,
294 NVME_ID_CNS_CTRL_LIST
= 0x13,
298 NVME_NS_FEAT_THIN
= 1 << 0,
299 NVME_NS_FLBAS_LBA_MASK
= 0xf,
300 NVME_NS_FLBAS_META_EXT
= 0x10,
301 NVME_LBAF_RP_BEST
= 0,
302 NVME_LBAF_RP_BETTER
= 1,
303 NVME_LBAF_RP_GOOD
= 2,
304 NVME_LBAF_RP_DEGRADED
= 3,
305 NVME_NS_DPC_PI_LAST
= 1 << 4,
306 NVME_NS_DPC_PI_FIRST
= 1 << 3,
307 NVME_NS_DPC_PI_TYPE3
= 1 << 2,
308 NVME_NS_DPC_PI_TYPE2
= 1 << 1,
309 NVME_NS_DPC_PI_TYPE1
= 1 << 0,
310 NVME_NS_DPS_PI_FIRST
= 1 << 3,
311 NVME_NS_DPS_PI_MASK
= 0x7,
312 NVME_NS_DPS_PI_TYPE1
= 1,
313 NVME_NS_DPS_PI_TYPE2
= 2,
314 NVME_NS_DPS_PI_TYPE3
= 3,
317 struct nvme_smart_log
{
318 __u8 critical_warning
;
324 __u8 data_units_read
[16];
325 __u8 data_units_written
[16];
327 __u8 host_writes
[16];
328 __u8 ctrl_busy_time
[16];
329 __u8 power_cycles
[16];
330 __u8 power_on_hours
[16];
331 __u8 unsafe_shutdowns
[16];
332 __u8 media_errors
[16];
333 __u8 num_err_log_entries
[16];
334 __le32 warning_temp_time
;
335 __le32 critical_comp_time
;
336 __le16 temp_sensor
[8];
341 NVME_SMART_CRIT_SPARE
= 1 << 0,
342 NVME_SMART_CRIT_TEMPERATURE
= 1 << 1,
343 NVME_SMART_CRIT_RELIABILITY
= 1 << 2,
344 NVME_SMART_CRIT_MEDIA
= 1 << 3,
345 NVME_SMART_CRIT_VOLATILE_MEMORY
= 1 << 4,
349 NVME_AER_NOTICE_NS_CHANGED
= 0x0002,
352 struct nvme_lba_range_type
{
363 NVME_LBART_TYPE_FS
= 0x01,
364 NVME_LBART_TYPE_RAID
= 0x02,
365 NVME_LBART_TYPE_CACHE
= 0x03,
366 NVME_LBART_TYPE_SWAP
= 0x04,
368 NVME_LBART_ATTRIB_TEMP
= 1 << 0,
369 NVME_LBART_ATTRIB_HIDE
= 1 << 1,
372 struct nvme_reservation_status
{
388 enum nvme_async_event_type
{
389 NVME_AER_TYPE_ERROR
= 0,
390 NVME_AER_TYPE_SMART
= 1,
391 NVME_AER_TYPE_NOTICE
= 2,
397 nvme_cmd_flush
= 0x00,
398 nvme_cmd_write
= 0x01,
399 nvme_cmd_read
= 0x02,
400 nvme_cmd_write_uncor
= 0x04,
401 nvme_cmd_compare
= 0x05,
402 nvme_cmd_write_zeroes
= 0x08,
404 nvme_cmd_resv_register
= 0x0d,
405 nvme_cmd_resv_report
= 0x0e,
406 nvme_cmd_resv_acquire
= 0x11,
407 nvme_cmd_resv_release
= 0x15,
411 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
413 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
414 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
415 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
419 NVME_SGL_FMT_ADDRESS
= 0x00,
420 NVME_SGL_FMT_OFFSET
= 0x01,
421 NVME_SGL_FMT_INVALIDATE
= 0x0f,
425 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
427 * For struct nvme_sgl_desc:
428 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
429 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
430 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
432 * For struct nvme_keyed_sgl_desc:
433 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
436 NVME_SGL_FMT_DATA_DESC
= 0x00,
437 NVME_SGL_FMT_SEG_DESC
= 0x02,
438 NVME_SGL_FMT_LAST_SEG_DESC
= 0x03,
439 NVME_KEY_SGL_FMT_DATA_DESC
= 0x04,
442 struct nvme_sgl_desc
{
449 struct nvme_keyed_sgl_desc
{
456 union nvme_data_ptr
{
461 struct nvme_sgl_desc sgl
;
462 struct nvme_keyed_sgl_desc ksgl
;
466 * Lowest two bits of our flags field (FUSE field in the spec):
468 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
469 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
471 * Highest two bits in our flags field (PSDT field in the spec):
473 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
474 * If used, MPTR contains addr of single physical buffer (byte aligned).
475 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
476 * If used, MPTR contains an address of an SGL segment containing
477 * exactly 1 SGL descriptor (qword aligned).
480 NVME_CMD_FUSE_FIRST
= (1 << 0),
481 NVME_CMD_FUSE_SECOND
= (1 << 1),
483 NVME_CMD_SGL_METABUF
= (1 << 6),
484 NVME_CMD_SGL_METASEG
= (1 << 7),
485 NVME_CMD_SGL_ALL
= NVME_CMD_SGL_METABUF
| NVME_CMD_SGL_METASEG
,
488 struct nvme_common_command
{
495 union nvme_data_ptr dptr
;
499 struct nvme_rw_command
{
506 union nvme_data_ptr dptr
;
517 NVME_RW_LR
= 1 << 15,
518 NVME_RW_FUA
= 1 << 14,
519 NVME_RW_DSM_FREQ_UNSPEC
= 0,
520 NVME_RW_DSM_FREQ_TYPICAL
= 1,
521 NVME_RW_DSM_FREQ_RARE
= 2,
522 NVME_RW_DSM_FREQ_READS
= 3,
523 NVME_RW_DSM_FREQ_WRITES
= 4,
524 NVME_RW_DSM_FREQ_RW
= 5,
525 NVME_RW_DSM_FREQ_ONCE
= 6,
526 NVME_RW_DSM_FREQ_PREFETCH
= 7,
527 NVME_RW_DSM_FREQ_TEMP
= 8,
528 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
529 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
530 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
531 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
532 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
533 NVME_RW_DSM_COMPRESSED
= 1 << 7,
534 NVME_RW_PRINFO_PRCHK_REF
= 1 << 10,
535 NVME_RW_PRINFO_PRCHK_APP
= 1 << 11,
536 NVME_RW_PRINFO_PRCHK_GUARD
= 1 << 12,
537 NVME_RW_PRINFO_PRACT
= 1 << 13,
540 struct nvme_dsm_cmd
{
546 union nvme_data_ptr dptr
;
553 NVME_DSMGMT_IDR
= 1 << 0,
554 NVME_DSMGMT_IDW
= 1 << 1,
555 NVME_DSMGMT_AD
= 1 << 2,
558 #define NVME_DSM_MAX_RANGES 256
560 struct nvme_dsm_range
{
566 struct nvme_write_zeroes_cmd
{
573 union nvme_data_ptr dptr
;
585 struct nvme_feat_auto_pst
{
591 enum nvme_admin_opcode
{
592 nvme_admin_delete_sq
= 0x00,
593 nvme_admin_create_sq
= 0x01,
594 nvme_admin_get_log_page
= 0x02,
595 nvme_admin_delete_cq
= 0x04,
596 nvme_admin_create_cq
= 0x05,
597 nvme_admin_identify
= 0x06,
598 nvme_admin_abort_cmd
= 0x08,
599 nvme_admin_set_features
= 0x09,
600 nvme_admin_get_features
= 0x0a,
601 nvme_admin_async_event
= 0x0c,
602 nvme_admin_ns_mgmt
= 0x0d,
603 nvme_admin_activate_fw
= 0x10,
604 nvme_admin_download_fw
= 0x11,
605 nvme_admin_ns_attach
= 0x15,
606 nvme_admin_keep_alive
= 0x18,
607 nvme_admin_dbbuf
= 0x7C,
608 nvme_admin_format_nvm
= 0x80,
609 nvme_admin_security_send
= 0x81,
610 nvme_admin_security_recv
= 0x82,
614 NVME_QUEUE_PHYS_CONTIG
= (1 << 0),
615 NVME_CQ_IRQ_ENABLED
= (1 << 1),
616 NVME_SQ_PRIO_URGENT
= (0 << 1),
617 NVME_SQ_PRIO_HIGH
= (1 << 1),
618 NVME_SQ_PRIO_MEDIUM
= (2 << 1),
619 NVME_SQ_PRIO_LOW
= (3 << 1),
620 NVME_FEAT_ARBITRATION
= 0x01,
621 NVME_FEAT_POWER_MGMT
= 0x02,
622 NVME_FEAT_LBA_RANGE
= 0x03,
623 NVME_FEAT_TEMP_THRESH
= 0x04,
624 NVME_FEAT_ERR_RECOVERY
= 0x05,
625 NVME_FEAT_VOLATILE_WC
= 0x06,
626 NVME_FEAT_NUM_QUEUES
= 0x07,
627 NVME_FEAT_IRQ_COALESCE
= 0x08,
628 NVME_FEAT_IRQ_CONFIG
= 0x09,
629 NVME_FEAT_WRITE_ATOMIC
= 0x0a,
630 NVME_FEAT_ASYNC_EVENT
= 0x0b,
631 NVME_FEAT_AUTO_PST
= 0x0c,
632 NVME_FEAT_HOST_MEM_BUF
= 0x0d,
633 NVME_FEAT_KATO
= 0x0f,
634 NVME_FEAT_SW_PROGRESS
= 0x80,
635 NVME_FEAT_HOST_ID
= 0x81,
636 NVME_FEAT_RESV_MASK
= 0x82,
637 NVME_FEAT_RESV_PERSIST
= 0x83,
638 NVME_LOG_ERROR
= 0x01,
639 NVME_LOG_SMART
= 0x02,
640 NVME_LOG_FW_SLOT
= 0x03,
641 NVME_LOG_DISC
= 0x70,
642 NVME_LOG_RESERVATION
= 0x80,
643 NVME_FWACT_REPL
= (0 << 3),
644 NVME_FWACT_REPL_ACTV
= (1 << 3),
645 NVME_FWACT_ACTV
= (2 << 3),
648 struct nvme_identify
{
654 union nvme_data_ptr dptr
;
661 struct nvme_features
{
667 union nvme_data_ptr dptr
;
673 struct nvme_create_cq
{
687 struct nvme_create_sq
{
701 struct nvme_delete_queue
{
711 struct nvme_abort_cmd
{
721 struct nvme_download_firmware
{
726 union nvme_data_ptr dptr
;
732 struct nvme_format_cmd
{
742 struct nvme_get_log_page_command
{
748 union nvme_data_ptr dptr
;
760 * Fabrics subcommands.
762 enum nvmf_fabrics_opcode
{
763 nvme_fabrics_command
= 0x7f,
766 enum nvmf_capsule_command
{
767 nvme_fabrics_type_property_set
= 0x00,
768 nvme_fabrics_type_connect
= 0x01,
769 nvme_fabrics_type_property_get
= 0x04,
772 struct nvmf_common_command
{
782 * The legal cntlid range a NVMe Target will provide.
783 * Note that cntlid of value 0 is considered illegal in the fabrics world.
784 * Devices based on earlier specs did not have the subsystem concept;
785 * therefore, those devices had their cntlid value set to 0 as a result.
787 #define NVME_CNTLID_MIN 1
788 #define NVME_CNTLID_MAX 0xffef
789 #define NVME_CNTLID_DYNAMIC 0xffff
791 #define MAX_DISC_LOGS 255
793 /* Discovery log page entry */
794 struct nvmf_disc_rsp_page_entry
{
803 char trsvcid
[NVMF_TRSVCID_SIZE
];
805 char subnqn
[NVMF_NQN_FIELD_LEN
];
806 char traddr
[NVMF_TRADDR_SIZE
];
808 char common
[NVMF_TSAS_SIZE
];
820 /* Discovery log page header */
821 struct nvmf_disc_rsp_page_hdr
{
826 struct nvmf_disc_rsp_page_entry entries
[0];
829 struct nvmf_connect_command
{
835 union nvme_data_ptr dptr
;
845 struct nvmf_connect_data
{
849 char subsysnqn
[NVMF_NQN_FIELD_LEN
];
850 char hostnqn
[NVMF_NQN_FIELD_LEN
];
854 struct nvmf_property_set_command
{
867 struct nvmf_property_get_command
{
889 struct nvme_command
{
891 struct nvme_common_command common
;
892 struct nvme_rw_command rw
;
893 struct nvme_identify identify
;
894 struct nvme_features features
;
895 struct nvme_create_cq create_cq
;
896 struct nvme_create_sq create_sq
;
897 struct nvme_delete_queue delete_queue
;
898 struct nvme_download_firmware dlfw
;
899 struct nvme_format_cmd format
;
900 struct nvme_dsm_cmd dsm
;
901 struct nvme_write_zeroes_cmd write_zeroes
;
902 struct nvme_abort_cmd abort
;
903 struct nvme_get_log_page_command get_log_page
;
904 struct nvmf_common_command fabrics
;
905 struct nvmf_connect_command connect
;
906 struct nvmf_property_set_command prop_set
;
907 struct nvmf_property_get_command prop_get
;
908 struct nvme_dbbuf dbbuf
;
912 static inline bool nvme_is_write(struct nvme_command
*cmd
)
917 * Why can't we simply have a Fabrics In and Fabrics out command?
919 if (unlikely(cmd
->common
.opcode
== nvme_fabrics_command
))
920 return cmd
->fabrics
.opcode
& 1;
921 return cmd
->common
.opcode
& 1;
926 * Generic Command Status:
928 NVME_SC_SUCCESS
= 0x0,
929 NVME_SC_INVALID_OPCODE
= 0x1,
930 NVME_SC_INVALID_FIELD
= 0x2,
931 NVME_SC_CMDID_CONFLICT
= 0x3,
932 NVME_SC_DATA_XFER_ERROR
= 0x4,
933 NVME_SC_POWER_LOSS
= 0x5,
934 NVME_SC_INTERNAL
= 0x6,
935 NVME_SC_ABORT_REQ
= 0x7,
936 NVME_SC_ABORT_QUEUE
= 0x8,
937 NVME_SC_FUSED_FAIL
= 0x9,
938 NVME_SC_FUSED_MISSING
= 0xa,
939 NVME_SC_INVALID_NS
= 0xb,
940 NVME_SC_CMD_SEQ_ERROR
= 0xc,
941 NVME_SC_SGL_INVALID_LAST
= 0xd,
942 NVME_SC_SGL_INVALID_COUNT
= 0xe,
943 NVME_SC_SGL_INVALID_DATA
= 0xf,
944 NVME_SC_SGL_INVALID_METADATA
= 0x10,
945 NVME_SC_SGL_INVALID_TYPE
= 0x11,
947 NVME_SC_SGL_INVALID_OFFSET
= 0x16,
948 NVME_SC_SGL_INVALID_SUBTYPE
= 0x17,
950 NVME_SC_LBA_RANGE
= 0x80,
951 NVME_SC_CAP_EXCEEDED
= 0x81,
952 NVME_SC_NS_NOT_READY
= 0x82,
953 NVME_SC_RESERVATION_CONFLICT
= 0x83,
956 * Command Specific Status:
958 NVME_SC_CQ_INVALID
= 0x100,
959 NVME_SC_QID_INVALID
= 0x101,
960 NVME_SC_QUEUE_SIZE
= 0x102,
961 NVME_SC_ABORT_LIMIT
= 0x103,
962 NVME_SC_ABORT_MISSING
= 0x104,
963 NVME_SC_ASYNC_LIMIT
= 0x105,
964 NVME_SC_FIRMWARE_SLOT
= 0x106,
965 NVME_SC_FIRMWARE_IMAGE
= 0x107,
966 NVME_SC_INVALID_VECTOR
= 0x108,
967 NVME_SC_INVALID_LOG_PAGE
= 0x109,
968 NVME_SC_INVALID_FORMAT
= 0x10a,
969 NVME_SC_FW_NEEDS_CONV_RESET
= 0x10b,
970 NVME_SC_INVALID_QUEUE
= 0x10c,
971 NVME_SC_FEATURE_NOT_SAVEABLE
= 0x10d,
972 NVME_SC_FEATURE_NOT_CHANGEABLE
= 0x10e,
973 NVME_SC_FEATURE_NOT_PER_NS
= 0x10f,
974 NVME_SC_FW_NEEDS_SUBSYS_RESET
= 0x110,
975 NVME_SC_FW_NEEDS_RESET
= 0x111,
976 NVME_SC_FW_NEEDS_MAX_TIME
= 0x112,
977 NVME_SC_FW_ACIVATE_PROHIBITED
= 0x113,
978 NVME_SC_OVERLAPPING_RANGE
= 0x114,
979 NVME_SC_NS_INSUFFICENT_CAP
= 0x115,
980 NVME_SC_NS_ID_UNAVAILABLE
= 0x116,
981 NVME_SC_NS_ALREADY_ATTACHED
= 0x118,
982 NVME_SC_NS_IS_PRIVATE
= 0x119,
983 NVME_SC_NS_NOT_ATTACHED
= 0x11a,
984 NVME_SC_THIN_PROV_NOT_SUPP
= 0x11b,
985 NVME_SC_CTRL_LIST_INVALID
= 0x11c,
988 * I/O Command Set Specific - NVM commands:
990 NVME_SC_BAD_ATTRIBUTES
= 0x180,
991 NVME_SC_INVALID_PI
= 0x181,
992 NVME_SC_READ_ONLY
= 0x182,
993 NVME_SC_ONCS_NOT_SUPPORTED
= 0x183,
996 * I/O Command Set Specific - Fabrics commands:
998 NVME_SC_CONNECT_FORMAT
= 0x180,
999 NVME_SC_CONNECT_CTRL_BUSY
= 0x181,
1000 NVME_SC_CONNECT_INVALID_PARAM
= 0x182,
1001 NVME_SC_CONNECT_RESTART_DISC
= 0x183,
1002 NVME_SC_CONNECT_INVALID_HOST
= 0x184,
1004 NVME_SC_DISCOVERY_RESTART
= 0x190,
1005 NVME_SC_AUTH_REQUIRED
= 0x191,
1008 * Media and Data Integrity Errors:
1010 NVME_SC_WRITE_FAULT
= 0x280,
1011 NVME_SC_READ_ERROR
= 0x281,
1012 NVME_SC_GUARD_CHECK
= 0x282,
1013 NVME_SC_APPTAG_CHECK
= 0x283,
1014 NVME_SC_REFTAG_CHECK
= 0x284,
1015 NVME_SC_COMPARE_FAILED
= 0x285,
1016 NVME_SC_ACCESS_DENIED
= 0x286,
1017 NVME_SC_UNWRITTEN_BLOCK
= 0x287,
1019 NVME_SC_DNR
= 0x4000,
1023 * FC Transport-specific error status values for NVME commands
1025 * Transport-specific status code values must be in the range 0xB0..0xBF
1028 /* Generic FC failure - catchall */
1029 NVME_SC_FC_TRANSPORT_ERROR
= 0x00B0,
1031 /* I/O failure due to FC ABTS'd */
1032 NVME_SC_FC_TRANSPORT_ABORTED
= 0x00B1,
1035 struct nvme_completion
{
1037 * Used by Admin and Fabrics commands to return data:
1044 __le16 sq_head
; /* how much of this queue may be reclaimed */
1045 __le16 sq_id
; /* submission queue that generated this entry */
1046 __u16 command_id
; /* of the command which completed */
1047 __le16 status
; /* did the command fail, and if so, why? */
1050 #define NVME_VS(major, minor, tertiary) \
1051 (((major) << 16) | ((minor) << 8) | (tertiary))
1053 #endif /* _LINUX_NVME_H */