2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 #include <linux/types.h>
19 #include <linux/uuid.h>
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN 256
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE 223
27 #define NVMF_TRSVCID_SIZE 32
28 #define NVMF_TRADDR_SIZE 256
29 #define NVMF_TSAS_SIZE 256
31 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
33 #define NVME_RDMA_IP_PORT 4420
35 #define NVME_NSID_ALL 0xffffffff
37 enum nvme_subsys_type
{
38 NVME_NQN_DISC
= 1, /* Discovery type target subsystem */
39 NVME_NQN_NVME
= 2, /* NVME type target subsystem */
42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
44 NVMF_ADDR_FAMILY_PCI
= 0, /* PCIe */
45 NVMF_ADDR_FAMILY_IP4
= 1, /* IP4 */
46 NVMF_ADDR_FAMILY_IP6
= 2, /* IP6 */
47 NVMF_ADDR_FAMILY_IB
= 3, /* InfiniBand */
48 NVMF_ADDR_FAMILY_FC
= 4, /* Fibre Channel */
51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
53 NVMF_TRTYPE_RDMA
= 1, /* RDMA */
54 NVMF_TRTYPE_FC
= 2, /* Fibre Channel */
55 NVMF_TRTYPE_LOOP
= 254, /* Reserved for host usage */
59 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
61 NVMF_TREQ_NOT_SPECIFIED
= 0, /* Not specified */
62 NVMF_TREQ_REQUIRED
= 1, /* Required */
63 NVMF_TREQ_NOT_REQUIRED
= 2, /* Not Required */
66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
70 NVMF_RDMA_QPTYPE_CONNECTED
= 1, /* Reliable Connected */
71 NVMF_RDMA_QPTYPE_DATAGRAM
= 2, /* Reliable Datagram */
74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
78 NVMF_RDMA_PRTYPE_NOT_SPECIFIED
= 1, /* No Provider Specified */
79 NVMF_RDMA_PRTYPE_IB
= 2, /* InfiniBand */
80 NVMF_RDMA_PRTYPE_ROCE
= 3, /* InfiniBand RoCE */
81 NVMF_RDMA_PRTYPE_ROCEV2
= 4, /* InfiniBand RoCEV2 */
82 NVMF_RDMA_PRTYPE_IWARP
= 5, /* IWARP */
85 /* RDMA Connection Management Service Type codes for Discovery Log Page
86 * entry TSAS RDMA_CMS field
89 NVMF_RDMA_CMS_RDMA_CM
= 1, /* Sockets based endpoint addressing */
92 #define NVME_AQ_DEPTH 32
95 NVME_REG_CAP
= 0x0000, /* Controller Capabilities */
96 NVME_REG_VS
= 0x0008, /* Version */
97 NVME_REG_INTMS
= 0x000c, /* Interrupt Mask Set */
98 NVME_REG_INTMC
= 0x0010, /* Interrupt Mask Clear */
99 NVME_REG_CC
= 0x0014, /* Controller Configuration */
100 NVME_REG_CSTS
= 0x001c, /* Controller Status */
101 NVME_REG_NSSR
= 0x0020, /* NVM Subsystem Reset */
102 NVME_REG_AQA
= 0x0024, /* Admin Queue Attributes */
103 NVME_REG_ASQ
= 0x0028, /* Admin SQ Base Address */
104 NVME_REG_ACQ
= 0x0030, /* Admin CQ Base Address */
105 NVME_REG_CMBLOC
= 0x0038, /* Controller Memory Buffer Location */
106 NVME_REG_CMBSZ
= 0x003c, /* Controller Memory Buffer Size */
107 NVME_REG_DBS
= 0x1000, /* SQ 0 Tail Doorbell */
110 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
111 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
112 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
113 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
114 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
115 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
117 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
118 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
119 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
120 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
122 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
123 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
124 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
125 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
126 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
129 * Submission and Completion Queue Entry Sizes for the NVM command set.
130 * (In bytes and specified as a power of two (2^n)).
132 #define NVME_NVM_IOSQES 6
133 #define NVME_NVM_IOCQES 4
136 NVME_CC_ENABLE
= 1 << 0,
137 NVME_CC_CSS_NVM
= 0 << 4,
138 NVME_CC_EN_SHIFT
= 0,
139 NVME_CC_CSS_SHIFT
= 4,
140 NVME_CC_MPS_SHIFT
= 7,
141 NVME_CC_AMS_SHIFT
= 11,
142 NVME_CC_SHN_SHIFT
= 14,
143 NVME_CC_IOSQES_SHIFT
= 16,
144 NVME_CC_IOCQES_SHIFT
= 20,
145 NVME_CC_AMS_RR
= 0 << NVME_CC_AMS_SHIFT
,
146 NVME_CC_AMS_WRRU
= 1 << NVME_CC_AMS_SHIFT
,
147 NVME_CC_AMS_VS
= 7 << NVME_CC_AMS_SHIFT
,
148 NVME_CC_SHN_NONE
= 0 << NVME_CC_SHN_SHIFT
,
149 NVME_CC_SHN_NORMAL
= 1 << NVME_CC_SHN_SHIFT
,
150 NVME_CC_SHN_ABRUPT
= 2 << NVME_CC_SHN_SHIFT
,
151 NVME_CC_SHN_MASK
= 3 << NVME_CC_SHN_SHIFT
,
152 NVME_CC_IOSQES
= NVME_NVM_IOSQES
<< NVME_CC_IOSQES_SHIFT
,
153 NVME_CC_IOCQES
= NVME_NVM_IOCQES
<< NVME_CC_IOCQES_SHIFT
,
154 NVME_CSTS_RDY
= 1 << 0,
155 NVME_CSTS_CFS
= 1 << 1,
156 NVME_CSTS_NSSRO
= 1 << 4,
157 NVME_CSTS_PP
= 1 << 5,
158 NVME_CSTS_SHST_NORMAL
= 0 << 2,
159 NVME_CSTS_SHST_OCCUR
= 1 << 2,
160 NVME_CSTS_SHST_CMPLT
= 2 << 2,
161 NVME_CSTS_SHST_MASK
= 3 << 2,
164 struct nvme_id_power_state
{
165 __le16 max_power
; /* centiwatts */
168 __le32 entry_lat
; /* microseconds */
169 __le32 exit_lat
; /* microseconds */
178 __u8 active_work_scale
;
183 NVME_PS_FLAGS_MAX_POWER_SCALE
= 1 << 0,
184 NVME_PS_FLAGS_NON_OP_STATE
= 1 << 1,
187 struct nvme_id_ctrl
{
256 struct nvme_id_power_state psd
[32];
261 NVME_CTRL_ONCS_COMPARE
= 1 << 0,
262 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE
= 1 << 1,
263 NVME_CTRL_ONCS_DSM
= 1 << 2,
264 NVME_CTRL_ONCS_WRITE_ZEROES
= 1 << 3,
265 NVME_CTRL_ONCS_TIMESTAMP
= 1 << 6,
266 NVME_CTRL_VWC_PRESENT
= 1 << 0,
267 NVME_CTRL_OACS_SEC_SUPP
= 1 << 0,
268 NVME_CTRL_OACS_DIRECTIVES
= 1 << 5,
269 NVME_CTRL_OACS_DBBUF_SUPP
= 1 << 8,
303 struct nvme_lbaf lbaf
[16];
309 NVME_ID_CNS_NS
= 0x00,
310 NVME_ID_CNS_CTRL
= 0x01,
311 NVME_ID_CNS_NS_ACTIVE_LIST
= 0x02,
312 NVME_ID_CNS_NS_DESC_LIST
= 0x03,
313 NVME_ID_CNS_NS_PRESENT_LIST
= 0x10,
314 NVME_ID_CNS_NS_PRESENT
= 0x11,
315 NVME_ID_CNS_CTRL_NS_LIST
= 0x12,
316 NVME_ID_CNS_CTRL_LIST
= 0x13,
320 NVME_DIR_IDENTIFY
= 0x00,
321 NVME_DIR_STREAMS
= 0x01,
322 NVME_DIR_SND_ID_OP_ENABLE
= 0x01,
323 NVME_DIR_SND_ST_OP_REL_ID
= 0x01,
324 NVME_DIR_SND_ST_OP_REL_RSC
= 0x02,
325 NVME_DIR_RCV_ID_OP_PARAM
= 0x01,
326 NVME_DIR_RCV_ST_OP_PARAM
= 0x01,
327 NVME_DIR_RCV_ST_OP_STATUS
= 0x02,
328 NVME_DIR_RCV_ST_OP_RESOURCE
= 0x03,
329 NVME_DIR_ENDIR
= 0x01,
333 NVME_NS_FEAT_THIN
= 1 << 0,
334 NVME_NS_FLBAS_LBA_MASK
= 0xf,
335 NVME_NS_FLBAS_META_EXT
= 0x10,
336 NVME_LBAF_RP_BEST
= 0,
337 NVME_LBAF_RP_BETTER
= 1,
338 NVME_LBAF_RP_GOOD
= 2,
339 NVME_LBAF_RP_DEGRADED
= 3,
340 NVME_NS_DPC_PI_LAST
= 1 << 4,
341 NVME_NS_DPC_PI_FIRST
= 1 << 3,
342 NVME_NS_DPC_PI_TYPE3
= 1 << 2,
343 NVME_NS_DPC_PI_TYPE2
= 1 << 1,
344 NVME_NS_DPC_PI_TYPE1
= 1 << 0,
345 NVME_NS_DPS_PI_FIRST
= 1 << 3,
346 NVME_NS_DPS_PI_MASK
= 0x7,
347 NVME_NS_DPS_PI_TYPE1
= 1,
348 NVME_NS_DPS_PI_TYPE2
= 2,
349 NVME_NS_DPS_PI_TYPE3
= 3,
352 struct nvme_ns_id_desc
{
358 #define NVME_NIDT_EUI64_LEN 8
359 #define NVME_NIDT_NGUID_LEN 16
360 #define NVME_NIDT_UUID_LEN 16
363 NVME_NIDT_EUI64
= 0x01,
364 NVME_NIDT_NGUID
= 0x02,
365 NVME_NIDT_UUID
= 0x03,
368 struct nvme_smart_log
{
369 __u8 critical_warning
;
375 __u8 data_units_read
[16];
376 __u8 data_units_written
[16];
378 __u8 host_writes
[16];
379 __u8 ctrl_busy_time
[16];
380 __u8 power_cycles
[16];
381 __u8 power_on_hours
[16];
382 __u8 unsafe_shutdowns
[16];
383 __u8 media_errors
[16];
384 __u8 num_err_log_entries
[16];
385 __le32 warning_temp_time
;
386 __le32 critical_comp_time
;
387 __le16 temp_sensor
[8];
391 struct nvme_fw_slot_info_log
{
399 NVME_SMART_CRIT_SPARE
= 1 << 0,
400 NVME_SMART_CRIT_TEMPERATURE
= 1 << 1,
401 NVME_SMART_CRIT_RELIABILITY
= 1 << 2,
402 NVME_SMART_CRIT_MEDIA
= 1 << 3,
403 NVME_SMART_CRIT_VOLATILE_MEMORY
= 1 << 4,
407 NVME_AER_NOTICE_NS_CHANGED
= 0x0002,
408 NVME_AER_NOTICE_FW_ACT_STARTING
= 0x0102,
411 struct nvme_lba_range_type
{
422 NVME_LBART_TYPE_FS
= 0x01,
423 NVME_LBART_TYPE_RAID
= 0x02,
424 NVME_LBART_TYPE_CACHE
= 0x03,
425 NVME_LBART_TYPE_SWAP
= 0x04,
427 NVME_LBART_ATTRIB_TEMP
= 1 << 0,
428 NVME_LBART_ATTRIB_HIDE
= 1 << 1,
431 struct nvme_reservation_status
{
447 enum nvme_async_event_type
{
448 NVME_AER_TYPE_ERROR
= 0,
449 NVME_AER_TYPE_SMART
= 1,
450 NVME_AER_TYPE_NOTICE
= 2,
456 nvme_cmd_flush
= 0x00,
457 nvme_cmd_write
= 0x01,
458 nvme_cmd_read
= 0x02,
459 nvme_cmd_write_uncor
= 0x04,
460 nvme_cmd_compare
= 0x05,
461 nvme_cmd_write_zeroes
= 0x08,
463 nvme_cmd_resv_register
= 0x0d,
464 nvme_cmd_resv_report
= 0x0e,
465 nvme_cmd_resv_acquire
= 0x11,
466 nvme_cmd_resv_release
= 0x15,
470 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
472 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
473 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
474 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
475 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
479 NVME_SGL_FMT_ADDRESS
= 0x00,
480 NVME_SGL_FMT_OFFSET
= 0x01,
481 NVME_SGL_FMT_TRANSPORT_A
= 0x0A,
482 NVME_SGL_FMT_INVALIDATE
= 0x0f,
486 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
488 * For struct nvme_sgl_desc:
489 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
490 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
491 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
493 * For struct nvme_keyed_sgl_desc:
494 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
496 * Transport-specific SGL types:
497 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
500 NVME_SGL_FMT_DATA_DESC
= 0x00,
501 NVME_SGL_FMT_SEG_DESC
= 0x02,
502 NVME_SGL_FMT_LAST_SEG_DESC
= 0x03,
503 NVME_KEY_SGL_FMT_DATA_DESC
= 0x04,
504 NVME_TRANSPORT_SGL_DATA_DESC
= 0x05,
507 struct nvme_sgl_desc
{
514 struct nvme_keyed_sgl_desc
{
521 union nvme_data_ptr
{
526 struct nvme_sgl_desc sgl
;
527 struct nvme_keyed_sgl_desc ksgl
;
531 * Lowest two bits of our flags field (FUSE field in the spec):
533 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
534 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
536 * Highest two bits in our flags field (PSDT field in the spec):
538 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
539 * If used, MPTR contains addr of single physical buffer (byte aligned).
540 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
541 * If used, MPTR contains an address of an SGL segment containing
542 * exactly 1 SGL descriptor (qword aligned).
545 NVME_CMD_FUSE_FIRST
= (1 << 0),
546 NVME_CMD_FUSE_SECOND
= (1 << 1),
548 NVME_CMD_SGL_METABUF
= (1 << 6),
549 NVME_CMD_SGL_METASEG
= (1 << 7),
550 NVME_CMD_SGL_ALL
= NVME_CMD_SGL_METABUF
| NVME_CMD_SGL_METASEG
,
553 struct nvme_common_command
{
560 union nvme_data_ptr dptr
;
564 struct nvme_rw_command
{
571 union nvme_data_ptr dptr
;
582 NVME_RW_LR
= 1 << 15,
583 NVME_RW_FUA
= 1 << 14,
584 NVME_RW_DSM_FREQ_UNSPEC
= 0,
585 NVME_RW_DSM_FREQ_TYPICAL
= 1,
586 NVME_RW_DSM_FREQ_RARE
= 2,
587 NVME_RW_DSM_FREQ_READS
= 3,
588 NVME_RW_DSM_FREQ_WRITES
= 4,
589 NVME_RW_DSM_FREQ_RW
= 5,
590 NVME_RW_DSM_FREQ_ONCE
= 6,
591 NVME_RW_DSM_FREQ_PREFETCH
= 7,
592 NVME_RW_DSM_FREQ_TEMP
= 8,
593 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
594 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
595 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
596 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
597 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
598 NVME_RW_DSM_COMPRESSED
= 1 << 7,
599 NVME_RW_PRINFO_PRCHK_REF
= 1 << 10,
600 NVME_RW_PRINFO_PRCHK_APP
= 1 << 11,
601 NVME_RW_PRINFO_PRCHK_GUARD
= 1 << 12,
602 NVME_RW_PRINFO_PRACT
= 1 << 13,
603 NVME_RW_DTYPE_STREAMS
= 1 << 4,
606 struct nvme_dsm_cmd
{
612 union nvme_data_ptr dptr
;
619 NVME_DSMGMT_IDR
= 1 << 0,
620 NVME_DSMGMT_IDW
= 1 << 1,
621 NVME_DSMGMT_AD
= 1 << 2,
624 #define NVME_DSM_MAX_RANGES 256
626 struct nvme_dsm_range
{
632 struct nvme_write_zeroes_cmd
{
639 union nvme_data_ptr dptr
;
651 struct nvme_feat_auto_pst
{
656 NVME_HOST_MEM_ENABLE
= (1 << 0),
657 NVME_HOST_MEM_RETURN
= (1 << 1),
662 enum nvme_admin_opcode
{
663 nvme_admin_delete_sq
= 0x00,
664 nvme_admin_create_sq
= 0x01,
665 nvme_admin_get_log_page
= 0x02,
666 nvme_admin_delete_cq
= 0x04,
667 nvme_admin_create_cq
= 0x05,
668 nvme_admin_identify
= 0x06,
669 nvme_admin_abort_cmd
= 0x08,
670 nvme_admin_set_features
= 0x09,
671 nvme_admin_get_features
= 0x0a,
672 nvme_admin_async_event
= 0x0c,
673 nvme_admin_ns_mgmt
= 0x0d,
674 nvme_admin_activate_fw
= 0x10,
675 nvme_admin_download_fw
= 0x11,
676 nvme_admin_ns_attach
= 0x15,
677 nvme_admin_keep_alive
= 0x18,
678 nvme_admin_directive_send
= 0x19,
679 nvme_admin_directive_recv
= 0x1a,
680 nvme_admin_dbbuf
= 0x7C,
681 nvme_admin_format_nvm
= 0x80,
682 nvme_admin_security_send
= 0x81,
683 nvme_admin_security_recv
= 0x82,
687 NVME_QUEUE_PHYS_CONTIG
= (1 << 0),
688 NVME_CQ_IRQ_ENABLED
= (1 << 1),
689 NVME_SQ_PRIO_URGENT
= (0 << 1),
690 NVME_SQ_PRIO_HIGH
= (1 << 1),
691 NVME_SQ_PRIO_MEDIUM
= (2 << 1),
692 NVME_SQ_PRIO_LOW
= (3 << 1),
693 NVME_FEAT_ARBITRATION
= 0x01,
694 NVME_FEAT_POWER_MGMT
= 0x02,
695 NVME_FEAT_LBA_RANGE
= 0x03,
696 NVME_FEAT_TEMP_THRESH
= 0x04,
697 NVME_FEAT_ERR_RECOVERY
= 0x05,
698 NVME_FEAT_VOLATILE_WC
= 0x06,
699 NVME_FEAT_NUM_QUEUES
= 0x07,
700 NVME_FEAT_IRQ_COALESCE
= 0x08,
701 NVME_FEAT_IRQ_CONFIG
= 0x09,
702 NVME_FEAT_WRITE_ATOMIC
= 0x0a,
703 NVME_FEAT_ASYNC_EVENT
= 0x0b,
704 NVME_FEAT_AUTO_PST
= 0x0c,
705 NVME_FEAT_HOST_MEM_BUF
= 0x0d,
706 NVME_FEAT_TIMESTAMP
= 0x0e,
707 NVME_FEAT_KATO
= 0x0f,
708 NVME_FEAT_SW_PROGRESS
= 0x80,
709 NVME_FEAT_HOST_ID
= 0x81,
710 NVME_FEAT_RESV_MASK
= 0x82,
711 NVME_FEAT_RESV_PERSIST
= 0x83,
712 NVME_LOG_ERROR
= 0x01,
713 NVME_LOG_SMART
= 0x02,
714 NVME_LOG_FW_SLOT
= 0x03,
715 NVME_LOG_DISC
= 0x70,
716 NVME_LOG_RESERVATION
= 0x80,
717 NVME_FWACT_REPL
= (0 << 3),
718 NVME_FWACT_REPL_ACTV
= (1 << 3),
719 NVME_FWACT_ACTV
= (2 << 3),
722 struct nvme_identify
{
728 union nvme_data_ptr dptr
;
735 #define NVME_IDENTIFY_DATA_SIZE 4096
737 struct nvme_features
{
743 union nvme_data_ptr dptr
;
752 struct nvme_host_mem_buf_desc
{
758 struct nvme_create_cq
{
772 struct nvme_create_sq
{
786 struct nvme_delete_queue
{
796 struct nvme_abort_cmd
{
806 struct nvme_download_firmware
{
811 union nvme_data_ptr dptr
;
817 struct nvme_format_cmd
{
827 struct nvme_get_log_page_command
{
833 union nvme_data_ptr dptr
;
844 struct nvme_directive_cmd
{
850 union nvme_data_ptr dptr
;
863 * Fabrics subcommands.
865 enum nvmf_fabrics_opcode
{
866 nvme_fabrics_command
= 0x7f,
869 enum nvmf_capsule_command
{
870 nvme_fabrics_type_property_set
= 0x00,
871 nvme_fabrics_type_connect
= 0x01,
872 nvme_fabrics_type_property_get
= 0x04,
875 struct nvmf_common_command
{
885 * The legal cntlid range a NVMe Target will provide.
886 * Note that cntlid of value 0 is considered illegal in the fabrics world.
887 * Devices based on earlier specs did not have the subsystem concept;
888 * therefore, those devices had their cntlid value set to 0 as a result.
890 #define NVME_CNTLID_MIN 1
891 #define NVME_CNTLID_MAX 0xffef
892 #define NVME_CNTLID_DYNAMIC 0xffff
894 #define MAX_DISC_LOGS 255
896 /* Discovery log page entry */
897 struct nvmf_disc_rsp_page_entry
{
906 char trsvcid
[NVMF_TRSVCID_SIZE
];
908 char subnqn
[NVMF_NQN_FIELD_LEN
];
909 char traddr
[NVMF_TRADDR_SIZE
];
911 char common
[NVMF_TSAS_SIZE
];
923 /* Discovery log page header */
924 struct nvmf_disc_rsp_page_hdr
{
929 struct nvmf_disc_rsp_page_entry entries
[0];
932 struct nvmf_connect_command
{
938 union nvme_data_ptr dptr
;
948 struct nvmf_connect_data
{
952 char subsysnqn
[NVMF_NQN_FIELD_LEN
];
953 char hostnqn
[NVMF_NQN_FIELD_LEN
];
957 struct nvmf_property_set_command
{
970 struct nvmf_property_get_command
{
992 struct streams_directive_params
{
1004 struct nvme_command
{
1006 struct nvme_common_command common
;
1007 struct nvme_rw_command rw
;
1008 struct nvme_identify identify
;
1009 struct nvme_features features
;
1010 struct nvme_create_cq create_cq
;
1011 struct nvme_create_sq create_sq
;
1012 struct nvme_delete_queue delete_queue
;
1013 struct nvme_download_firmware dlfw
;
1014 struct nvme_format_cmd format
;
1015 struct nvme_dsm_cmd dsm
;
1016 struct nvme_write_zeroes_cmd write_zeroes
;
1017 struct nvme_abort_cmd abort
;
1018 struct nvme_get_log_page_command get_log_page
;
1019 struct nvmf_common_command fabrics
;
1020 struct nvmf_connect_command connect
;
1021 struct nvmf_property_set_command prop_set
;
1022 struct nvmf_property_get_command prop_get
;
1023 struct nvme_dbbuf dbbuf
;
1024 struct nvme_directive_cmd directive
;
1028 static inline bool nvme_is_write(struct nvme_command
*cmd
)
1033 * Why can't we simply have a Fabrics In and Fabrics out command?
1035 if (unlikely(cmd
->common
.opcode
== nvme_fabrics_command
))
1036 return cmd
->fabrics
.fctype
& 1;
1037 return cmd
->common
.opcode
& 1;
1042 * Generic Command Status:
1044 NVME_SC_SUCCESS
= 0x0,
1045 NVME_SC_INVALID_OPCODE
= 0x1,
1046 NVME_SC_INVALID_FIELD
= 0x2,
1047 NVME_SC_CMDID_CONFLICT
= 0x3,
1048 NVME_SC_DATA_XFER_ERROR
= 0x4,
1049 NVME_SC_POWER_LOSS
= 0x5,
1050 NVME_SC_INTERNAL
= 0x6,
1051 NVME_SC_ABORT_REQ
= 0x7,
1052 NVME_SC_ABORT_QUEUE
= 0x8,
1053 NVME_SC_FUSED_FAIL
= 0x9,
1054 NVME_SC_FUSED_MISSING
= 0xa,
1055 NVME_SC_INVALID_NS
= 0xb,
1056 NVME_SC_CMD_SEQ_ERROR
= 0xc,
1057 NVME_SC_SGL_INVALID_LAST
= 0xd,
1058 NVME_SC_SGL_INVALID_COUNT
= 0xe,
1059 NVME_SC_SGL_INVALID_DATA
= 0xf,
1060 NVME_SC_SGL_INVALID_METADATA
= 0x10,
1061 NVME_SC_SGL_INVALID_TYPE
= 0x11,
1063 NVME_SC_SGL_INVALID_OFFSET
= 0x16,
1064 NVME_SC_SGL_INVALID_SUBTYPE
= 0x17,
1066 NVME_SC_LBA_RANGE
= 0x80,
1067 NVME_SC_CAP_EXCEEDED
= 0x81,
1068 NVME_SC_NS_NOT_READY
= 0x82,
1069 NVME_SC_RESERVATION_CONFLICT
= 0x83,
1072 * Command Specific Status:
1074 NVME_SC_CQ_INVALID
= 0x100,
1075 NVME_SC_QID_INVALID
= 0x101,
1076 NVME_SC_QUEUE_SIZE
= 0x102,
1077 NVME_SC_ABORT_LIMIT
= 0x103,
1078 NVME_SC_ABORT_MISSING
= 0x104,
1079 NVME_SC_ASYNC_LIMIT
= 0x105,
1080 NVME_SC_FIRMWARE_SLOT
= 0x106,
1081 NVME_SC_FIRMWARE_IMAGE
= 0x107,
1082 NVME_SC_INVALID_VECTOR
= 0x108,
1083 NVME_SC_INVALID_LOG_PAGE
= 0x109,
1084 NVME_SC_INVALID_FORMAT
= 0x10a,
1085 NVME_SC_FW_NEEDS_CONV_RESET
= 0x10b,
1086 NVME_SC_INVALID_QUEUE
= 0x10c,
1087 NVME_SC_FEATURE_NOT_SAVEABLE
= 0x10d,
1088 NVME_SC_FEATURE_NOT_CHANGEABLE
= 0x10e,
1089 NVME_SC_FEATURE_NOT_PER_NS
= 0x10f,
1090 NVME_SC_FW_NEEDS_SUBSYS_RESET
= 0x110,
1091 NVME_SC_FW_NEEDS_RESET
= 0x111,
1092 NVME_SC_FW_NEEDS_MAX_TIME
= 0x112,
1093 NVME_SC_FW_ACIVATE_PROHIBITED
= 0x113,
1094 NVME_SC_OVERLAPPING_RANGE
= 0x114,
1095 NVME_SC_NS_INSUFFICENT_CAP
= 0x115,
1096 NVME_SC_NS_ID_UNAVAILABLE
= 0x116,
1097 NVME_SC_NS_ALREADY_ATTACHED
= 0x118,
1098 NVME_SC_NS_IS_PRIVATE
= 0x119,
1099 NVME_SC_NS_NOT_ATTACHED
= 0x11a,
1100 NVME_SC_THIN_PROV_NOT_SUPP
= 0x11b,
1101 NVME_SC_CTRL_LIST_INVALID
= 0x11c,
1104 * I/O Command Set Specific - NVM commands:
1106 NVME_SC_BAD_ATTRIBUTES
= 0x180,
1107 NVME_SC_INVALID_PI
= 0x181,
1108 NVME_SC_READ_ONLY
= 0x182,
1109 NVME_SC_ONCS_NOT_SUPPORTED
= 0x183,
1112 * I/O Command Set Specific - Fabrics commands:
1114 NVME_SC_CONNECT_FORMAT
= 0x180,
1115 NVME_SC_CONNECT_CTRL_BUSY
= 0x181,
1116 NVME_SC_CONNECT_INVALID_PARAM
= 0x182,
1117 NVME_SC_CONNECT_RESTART_DISC
= 0x183,
1118 NVME_SC_CONNECT_INVALID_HOST
= 0x184,
1120 NVME_SC_DISCOVERY_RESTART
= 0x190,
1121 NVME_SC_AUTH_REQUIRED
= 0x191,
1124 * Media and Data Integrity Errors:
1126 NVME_SC_WRITE_FAULT
= 0x280,
1127 NVME_SC_READ_ERROR
= 0x281,
1128 NVME_SC_GUARD_CHECK
= 0x282,
1129 NVME_SC_APPTAG_CHECK
= 0x283,
1130 NVME_SC_REFTAG_CHECK
= 0x284,
1131 NVME_SC_COMPARE_FAILED
= 0x285,
1132 NVME_SC_ACCESS_DENIED
= 0x286,
1133 NVME_SC_UNWRITTEN_BLOCK
= 0x287,
1135 NVME_SC_DNR
= 0x4000,
1138 struct nvme_completion
{
1140 * Used by Admin and Fabrics commands to return data:
1147 __le16 sq_head
; /* how much of this queue may be reclaimed */
1148 __le16 sq_id
; /* submission queue that generated this entry */
1149 __u16 command_id
; /* of the command which completed */
1150 __le16 status
; /* did the command fail, and if so, why? */
1153 #define NVME_VS(major, minor, tertiary) \
1154 (((major) << 16) | ((minor) << 8) | (tertiary))
1156 #define NVME_MAJOR(ver) ((ver) >> 16)
1157 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1158 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1160 #endif /* _LINUX_NVME_H */