2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 #include <linux/types.h>
21 __u64 cap
; /* Controller Capabilities */
22 __u32 vs
; /* Version */
23 __u32 intms
; /* Interrupt Mask Set */
24 __u32 intmc
; /* Interrupt Mask Clear */
25 __u32 cc
; /* Controller Configuration */
26 __u32 rsvd1
; /* Reserved */
27 __u32 csts
; /* Controller Status */
28 __u32 nssr
; /* Subsystem Reset */
29 __u32 aqa
; /* Admin Queue Attributes */
30 __u64 asq
; /* Admin SQ Base Address */
31 __u64 acq
; /* Admin CQ Base Address */
32 __u32 cmbloc
; /* Controller Memory Buffer Location */
33 __u32 cmbsz
; /* Controller Memory Buffer Size */
36 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
37 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
38 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
39 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
40 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
41 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
43 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
44 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
45 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
46 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
48 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
49 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
50 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
51 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
52 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
55 NVME_CC_ENABLE
= 1 << 0,
56 NVME_CC_CSS_NVM
= 0 << 4,
57 NVME_CC_MPS_SHIFT
= 7,
58 NVME_CC_ARB_RR
= 0 << 11,
59 NVME_CC_ARB_WRRU
= 1 << 11,
60 NVME_CC_ARB_VS
= 7 << 11,
61 NVME_CC_SHN_NONE
= 0 << 14,
62 NVME_CC_SHN_NORMAL
= 1 << 14,
63 NVME_CC_SHN_ABRUPT
= 2 << 14,
64 NVME_CC_SHN_MASK
= 3 << 14,
65 NVME_CC_IOSQES
= 6 << 16,
66 NVME_CC_IOCQES
= 4 << 20,
67 NVME_CSTS_RDY
= 1 << 0,
68 NVME_CSTS_CFS
= 1 << 1,
69 NVME_CSTS_NSSRO
= 1 << 4,
70 NVME_CSTS_SHST_NORMAL
= 0 << 2,
71 NVME_CSTS_SHST_OCCUR
= 1 << 2,
72 NVME_CSTS_SHST_CMPLT
= 2 << 2,
73 NVME_CSTS_SHST_MASK
= 3 << 2,
76 struct nvme_id_power_state
{
77 __le16 max_power
; /* centiwatts */
80 __le32 entry_lat
; /* microseconds */
81 __le32 exit_lat
; /* microseconds */
90 __u8 active_work_scale
;
95 NVME_PS_FLAGS_MAX_POWER_SCALE
= 1 << 0,
96 NVME_PS_FLAGS_NON_OP_STATE
= 1 << 1,
140 struct nvme_id_power_state psd
[32];
145 NVME_CTRL_ONCS_COMPARE
= 1 << 0,
146 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE
= 1 << 1,
147 NVME_CTRL_ONCS_DSM
= 1 << 2,
148 NVME_CTRL_VWC_PRESENT
= 1 << 0,
182 struct nvme_lbaf lbaf
[16];
188 NVME_NS_FEAT_THIN
= 1 << 0,
189 NVME_NS_FLBAS_LBA_MASK
= 0xf,
190 NVME_NS_FLBAS_META_EXT
= 0x10,
191 NVME_LBAF_RP_BEST
= 0,
192 NVME_LBAF_RP_BETTER
= 1,
193 NVME_LBAF_RP_GOOD
= 2,
194 NVME_LBAF_RP_DEGRADED
= 3,
195 NVME_NS_DPC_PI_LAST
= 1 << 4,
196 NVME_NS_DPC_PI_FIRST
= 1 << 3,
197 NVME_NS_DPC_PI_TYPE3
= 1 << 2,
198 NVME_NS_DPC_PI_TYPE2
= 1 << 1,
199 NVME_NS_DPC_PI_TYPE1
= 1 << 0,
200 NVME_NS_DPS_PI_FIRST
= 1 << 3,
201 NVME_NS_DPS_PI_MASK
= 0x7,
202 NVME_NS_DPS_PI_TYPE1
= 1,
203 NVME_NS_DPS_PI_TYPE2
= 2,
204 NVME_NS_DPS_PI_TYPE3
= 3,
207 struct nvme_smart_log
{
208 __u8 critical_warning
;
214 __u8 data_units_read
[16];
215 __u8 data_units_written
[16];
217 __u8 host_writes
[16];
218 __u8 ctrl_busy_time
[16];
219 __u8 power_cycles
[16];
220 __u8 power_on_hours
[16];
221 __u8 unsafe_shutdowns
[16];
222 __u8 media_errors
[16];
223 __u8 num_err_log_entries
[16];
224 __le32 warning_temp_time
;
225 __le32 critical_comp_time
;
226 __le16 temp_sensor
[8];
231 NVME_SMART_CRIT_SPARE
= 1 << 0,
232 NVME_SMART_CRIT_TEMPERATURE
= 1 << 1,
233 NVME_SMART_CRIT_RELIABILITY
= 1 << 2,
234 NVME_SMART_CRIT_MEDIA
= 1 << 3,
235 NVME_SMART_CRIT_VOLATILE_MEMORY
= 1 << 4,
239 NVME_AER_NOTICE_NS_CHANGED
= 0x0002,
242 struct nvme_lba_range_type
{
253 NVME_LBART_TYPE_FS
= 0x01,
254 NVME_LBART_TYPE_RAID
= 0x02,
255 NVME_LBART_TYPE_CACHE
= 0x03,
256 NVME_LBART_TYPE_SWAP
= 0x04,
258 NVME_LBART_ATTRIB_TEMP
= 1 << 0,
259 NVME_LBART_ATTRIB_HIDE
= 1 << 1,
262 struct nvme_reservation_status
{
281 nvme_cmd_flush
= 0x00,
282 nvme_cmd_write
= 0x01,
283 nvme_cmd_read
= 0x02,
284 nvme_cmd_write_uncor
= 0x04,
285 nvme_cmd_compare
= 0x05,
286 nvme_cmd_write_zeroes
= 0x08,
288 nvme_cmd_resv_register
= 0x0d,
289 nvme_cmd_resv_report
= 0x0e,
290 nvme_cmd_resv_acquire
= 0x11,
291 nvme_cmd_resv_release
= 0x15,
294 struct nvme_common_command
{
306 struct nvme_rw_command
{
325 NVME_RW_LR
= 1 << 15,
326 NVME_RW_FUA
= 1 << 14,
327 NVME_RW_DSM_FREQ_UNSPEC
= 0,
328 NVME_RW_DSM_FREQ_TYPICAL
= 1,
329 NVME_RW_DSM_FREQ_RARE
= 2,
330 NVME_RW_DSM_FREQ_READS
= 3,
331 NVME_RW_DSM_FREQ_WRITES
= 4,
332 NVME_RW_DSM_FREQ_RW
= 5,
333 NVME_RW_DSM_FREQ_ONCE
= 6,
334 NVME_RW_DSM_FREQ_PREFETCH
= 7,
335 NVME_RW_DSM_FREQ_TEMP
= 8,
336 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
337 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
338 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
339 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
340 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
341 NVME_RW_DSM_COMPRESSED
= 1 << 7,
342 NVME_RW_PRINFO_PRCHK_REF
= 1 << 10,
343 NVME_RW_PRINFO_PRCHK_APP
= 1 << 11,
344 NVME_RW_PRINFO_PRCHK_GUARD
= 1 << 12,
345 NVME_RW_PRINFO_PRACT
= 1 << 13,
348 struct nvme_dsm_cmd
{
362 NVME_DSMGMT_IDR
= 1 << 0,
363 NVME_DSMGMT_IDW
= 1 << 1,
364 NVME_DSMGMT_AD
= 1 << 2,
367 struct nvme_dsm_range
{
375 enum nvme_admin_opcode
{
376 nvme_admin_delete_sq
= 0x00,
377 nvme_admin_create_sq
= 0x01,
378 nvme_admin_get_log_page
= 0x02,
379 nvme_admin_delete_cq
= 0x04,
380 nvme_admin_create_cq
= 0x05,
381 nvme_admin_identify
= 0x06,
382 nvme_admin_abort_cmd
= 0x08,
383 nvme_admin_set_features
= 0x09,
384 nvme_admin_get_features
= 0x0a,
385 nvme_admin_async_event
= 0x0c,
386 nvme_admin_activate_fw
= 0x10,
387 nvme_admin_download_fw
= 0x11,
388 nvme_admin_format_nvm
= 0x80,
389 nvme_admin_security_send
= 0x81,
390 nvme_admin_security_recv
= 0x82,
394 NVME_QUEUE_PHYS_CONTIG
= (1 << 0),
395 NVME_CQ_IRQ_ENABLED
= (1 << 1),
396 NVME_SQ_PRIO_URGENT
= (0 << 1),
397 NVME_SQ_PRIO_HIGH
= (1 << 1),
398 NVME_SQ_PRIO_MEDIUM
= (2 << 1),
399 NVME_SQ_PRIO_LOW
= (3 << 1),
400 NVME_FEAT_ARBITRATION
= 0x01,
401 NVME_FEAT_POWER_MGMT
= 0x02,
402 NVME_FEAT_LBA_RANGE
= 0x03,
403 NVME_FEAT_TEMP_THRESH
= 0x04,
404 NVME_FEAT_ERR_RECOVERY
= 0x05,
405 NVME_FEAT_VOLATILE_WC
= 0x06,
406 NVME_FEAT_NUM_QUEUES
= 0x07,
407 NVME_FEAT_IRQ_COALESCE
= 0x08,
408 NVME_FEAT_IRQ_CONFIG
= 0x09,
409 NVME_FEAT_WRITE_ATOMIC
= 0x0a,
410 NVME_FEAT_ASYNC_EVENT
= 0x0b,
411 NVME_FEAT_AUTO_PST
= 0x0c,
412 NVME_FEAT_SW_PROGRESS
= 0x80,
413 NVME_FEAT_HOST_ID
= 0x81,
414 NVME_FEAT_RESV_MASK
= 0x82,
415 NVME_FEAT_RESV_PERSIST
= 0x83,
416 NVME_LOG_ERROR
= 0x01,
417 NVME_LOG_SMART
= 0x02,
418 NVME_LOG_FW_SLOT
= 0x03,
419 NVME_LOG_RESERVATION
= 0x80,
420 NVME_FWACT_REPL
= (0 << 3),
421 NVME_FWACT_REPL_ACTV
= (1 << 3),
422 NVME_FWACT_ACTV
= (2 << 3),
425 struct nvme_identify
{
437 struct nvme_features
{
450 struct nvme_create_cq
{
464 struct nvme_create_sq
{
478 struct nvme_delete_queue
{
488 struct nvme_abort_cmd
{
498 struct nvme_download_firmware
{
510 struct nvme_format_cmd
{
520 struct nvme_command
{
522 struct nvme_common_command common
;
523 struct nvme_rw_command rw
;
524 struct nvme_identify identify
;
525 struct nvme_features features
;
526 struct nvme_create_cq create_cq
;
527 struct nvme_create_sq create_sq
;
528 struct nvme_delete_queue delete_queue
;
529 struct nvme_download_firmware dlfw
;
530 struct nvme_format_cmd format
;
531 struct nvme_dsm_cmd dsm
;
532 struct nvme_abort_cmd abort
;
537 NVME_SC_SUCCESS
= 0x0,
538 NVME_SC_INVALID_OPCODE
= 0x1,
539 NVME_SC_INVALID_FIELD
= 0x2,
540 NVME_SC_CMDID_CONFLICT
= 0x3,
541 NVME_SC_DATA_XFER_ERROR
= 0x4,
542 NVME_SC_POWER_LOSS
= 0x5,
543 NVME_SC_INTERNAL
= 0x6,
544 NVME_SC_ABORT_REQ
= 0x7,
545 NVME_SC_ABORT_QUEUE
= 0x8,
546 NVME_SC_FUSED_FAIL
= 0x9,
547 NVME_SC_FUSED_MISSING
= 0xa,
548 NVME_SC_INVALID_NS
= 0xb,
549 NVME_SC_CMD_SEQ_ERROR
= 0xc,
550 NVME_SC_SGL_INVALID_LAST
= 0xd,
551 NVME_SC_SGL_INVALID_COUNT
= 0xe,
552 NVME_SC_SGL_INVALID_DATA
= 0xf,
553 NVME_SC_SGL_INVALID_METADATA
= 0x10,
554 NVME_SC_SGL_INVALID_TYPE
= 0x11,
555 NVME_SC_LBA_RANGE
= 0x80,
556 NVME_SC_CAP_EXCEEDED
= 0x81,
557 NVME_SC_NS_NOT_READY
= 0x82,
558 NVME_SC_RESERVATION_CONFLICT
= 0x83,
559 NVME_SC_CQ_INVALID
= 0x100,
560 NVME_SC_QID_INVALID
= 0x101,
561 NVME_SC_QUEUE_SIZE
= 0x102,
562 NVME_SC_ABORT_LIMIT
= 0x103,
563 NVME_SC_ABORT_MISSING
= 0x104,
564 NVME_SC_ASYNC_LIMIT
= 0x105,
565 NVME_SC_FIRMWARE_SLOT
= 0x106,
566 NVME_SC_FIRMWARE_IMAGE
= 0x107,
567 NVME_SC_INVALID_VECTOR
= 0x108,
568 NVME_SC_INVALID_LOG_PAGE
= 0x109,
569 NVME_SC_INVALID_FORMAT
= 0x10a,
570 NVME_SC_FIRMWARE_NEEDS_RESET
= 0x10b,
571 NVME_SC_INVALID_QUEUE
= 0x10c,
572 NVME_SC_FEATURE_NOT_SAVEABLE
= 0x10d,
573 NVME_SC_FEATURE_NOT_CHANGEABLE
= 0x10e,
574 NVME_SC_FEATURE_NOT_PER_NS
= 0x10f,
575 NVME_SC_FW_NEEDS_RESET_SUBSYS
= 0x110,
576 NVME_SC_BAD_ATTRIBUTES
= 0x180,
577 NVME_SC_INVALID_PI
= 0x181,
578 NVME_SC_READ_ONLY
= 0x182,
579 NVME_SC_WRITE_FAULT
= 0x280,
580 NVME_SC_READ_ERROR
= 0x281,
581 NVME_SC_GUARD_CHECK
= 0x282,
582 NVME_SC_APPTAG_CHECK
= 0x283,
583 NVME_SC_REFTAG_CHECK
= 0x284,
584 NVME_SC_COMPARE_FAILED
= 0x285,
585 NVME_SC_ACCESS_DENIED
= 0x286,
586 NVME_SC_DNR
= 0x4000,
589 struct nvme_completion
{
590 __le32 result
; /* Used by admin commands to return data */
592 __le16 sq_head
; /* how much of this queue may be reclaimed */
593 __le16 sq_id
; /* submission queue that generated this entry */
594 __u16 command_id
; /* of the command which completed */
595 __le16 status
; /* did the command fail, and if so, why? */
598 #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
600 #endif /* _LINUX_NVME_H */