include/linux/omap-dma.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __LINUX_OMAP_DMA_H
   3 #define __LINUX_OMAP_DMA_H
   4 /*
   5  *  Legacy OMAP DMA handling defines and functions
   6  *
   7  *  NOTE: Do not use these any longer.
   8  *
   9  *  Use the generic dmaengine functions as defined in
  10  *  include/linux/dmaengine.h.
  11  *
  12  *  Copyright (C) 2003 Nokia Corporation
  13  *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
  14  *
  15  */
  16
  17 #include <linux/platform_device.h>
  18
  19 #define INT_DMA_LCD                     (NR_IRQS_LEGACY + 25)
  20
  21 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
  22 #define OMAP_DMA_DROP_IRQ               (1 << 1)
  23 #define OMAP_DMA_HALF_IRQ               (1 << 2)
  24 #define OMAP_DMA_FRAME_IRQ              (1 << 3)
  25 #define OMAP_DMA_LAST_IRQ               (1 << 4)
  26 #define OMAP_DMA_BLOCK_IRQ              (1 << 5)
  27 #define OMAP1_DMA_SYNC_IRQ              (1 << 6)
  28 #define OMAP2_DMA_PKT_IRQ               (1 << 7)
  29 #define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
  30 #define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
  31 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
  32 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
  33
  34 #define OMAP_DMA_CCR_EN                 (1 << 7)
  35 #define OMAP_DMA_CCR_RD_ACTIVE          (1 << 9)
  36 #define OMAP_DMA_CCR_WR_ACTIVE          (1 << 10)
  37 #define OMAP_DMA_CCR_SEL_SRC_DST_SYNC   (1 << 24)
  38 #define OMAP_DMA_CCR_BUFFERING_DISABLE  (1 << 25)
  39
  40 #define OMAP_DMA_DATA_TYPE_S8           0x00
  41 #define OMAP_DMA_DATA_TYPE_S16          0x01
  42 #define OMAP_DMA_DATA_TYPE_S32          0x02
  43
  44 #define OMAP_DMA_SYNC_ELEMENT           0x00
  45 #define OMAP_DMA_SYNC_FRAME             0x01
  46 #define OMAP_DMA_SYNC_BLOCK             0x02
  47 #define OMAP_DMA_SYNC_PACKET            0x03
  48
  49 #define OMAP_DMA_DST_SYNC_PREFETCH      0x02
  50 #define OMAP_DMA_SRC_SYNC               0x01
  51 #define OMAP_DMA_DST_SYNC               0x00
  52
  53 #define OMAP_DMA_PORT_EMIFF             0x00
  54 #define OMAP_DMA_PORT_EMIFS             0x01
  55 #define OMAP_DMA_PORT_OCP_T1            0x02
  56 #define OMAP_DMA_PORT_TIPB              0x03
  57 #define OMAP_DMA_PORT_OCP_T2            0x04
  58 #define OMAP_DMA_PORT_MPUI              0x05
  59
  60 #define OMAP_DMA_AMODE_CONSTANT         0x00
  61 #define OMAP_DMA_AMODE_POST_INC         0x01
  62 #define OMAP_DMA_AMODE_SINGLE_IDX       0x02
  63 #define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
  64
  65 #define DMA_DEFAULT_FIFO_DEPTH          0x10
  66 #define DMA_DEFAULT_ARB_RATE            0x01
  67 /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
  68 #define DMA_THREAD_RESERVE_NORM         (0x00 << 12) /* Def */
  69 #define DMA_THREAD_RESERVE_ONET         (0x01 << 12)
  70 #define DMA_THREAD_RESERVE_TWOT         (0x02 << 12)
  71 #define DMA_THREAD_RESERVE_THREET       (0x03 << 12)
  72 #define DMA_THREAD_FIFO_NONE            (0x00 << 14) /* Def */
  73 #define DMA_THREAD_FIFO_75              (0x01 << 14)
  74 #define DMA_THREAD_FIFO_25              (0x02 << 14)
  75 #define DMA_THREAD_FIFO_50              (0x03 << 14)
  76
  77 /* DMA4_OCP_SYSCONFIG bits */
  78 #define DMA_SYSCONFIG_MIDLEMODE_MASK            (3 << 12)
  79 #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK        (3 << 8)
  80 #define DMA_SYSCONFIG_EMUFREE                   (1 << 5)
  81 #define DMA_SYSCONFIG_SIDLEMODE_MASK            (3 << 3)
  82 #define DMA_SYSCONFIG_SOFTRESET                 (1 << 2)
  83 #define DMA_SYSCONFIG_AUTOIDLE                  (1 << 0)
  84
  85 #define DMA_SYSCONFIG_MIDLEMODE(n)              ((n) << 12)
  86 #define DMA_SYSCONFIG_SIDLEMODE(n)              ((n) << 3)
  87
  88 #define DMA_IDLEMODE_SMARTIDLE                  0x2
  89 #define DMA_IDLEMODE_NO_IDLE                    0x1
  90 #define DMA_IDLEMODE_FORCE_IDLE                 0x0
  91
  92 /* Chaining modes*/
  93 #ifndef CONFIG_ARCH_OMAP1
  94 #define OMAP_DMA_STATIC_CHAIN           0x1
  95 #define OMAP_DMA_DYNAMIC_CHAIN          0x2
  96 #define OMAP_DMA_CHAIN_ACTIVE           0x1
  97 #define OMAP_DMA_CHAIN_INACTIVE         0x0
  98 #endif
  99
 100 #define DMA_CH_PRIO_HIGH                0x1
 101 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
 102
 103 /* Errata handling */
 104 #define IS_DMA_ERRATA(id)               (errata & (id))
 105 #define SET_DMA_ERRATA(id)              (errata |= (id))
 106
 107 #define DMA_ERRATA_IFRAME_BUFFERING     BIT(0x0)
 108 #define DMA_ERRATA_PARALLEL_CHANNELS    BIT(0x1)
 109 #define DMA_ERRATA_i378                 BIT(0x2)
 110 #define DMA_ERRATA_i541                 BIT(0x3)
 111 #define DMA_ERRATA_i88                  BIT(0x4)
 112 #define DMA_ERRATA_3_3                  BIT(0x5)
 113 #define DMA_ROMCODE_BUG                 BIT(0x6)
 114
 115 /* Attributes for OMAP DMA Contrller */
 116 #define DMA_LINKED_LCH                  BIT(0x0)
 117 #define GLOBAL_PRIORITY                 BIT(0x1)
 118 #define RESERVE_CHANNEL                 BIT(0x2)
 119 #define IS_CSSA_32                      BIT(0x3)
 120 #define IS_CDSA_32                      BIT(0x4)
 121 #define IS_RW_PRIORITY                  BIT(0x5)
 122 #define ENABLE_1510_MODE                BIT(0x6)
 123 #define SRC_PORT                        BIT(0x7)
 124 #define DST_PORT                        BIT(0x8)
 125 #define SRC_INDEX                       BIT(0x9)
 126 #define DST_INDEX                       BIT(0xa)
 127 #define IS_BURST_ONLY4                  BIT(0xb)
 128 #define CLEAR_CSR_ON_READ               BIT(0xc)
 129 #define IS_WORD_16                      BIT(0xd)
 130 #define ENABLE_16XX_MODE                BIT(0xe)
 131 #define HS_CHANNELS_RESERVED            BIT(0xf)
 132
 133 /* Defines for DMA Capabilities */
 134 #define DMA_HAS_TRANSPARENT_CAPS        (0x1 << 18)
 135 #define DMA_HAS_CONSTANT_FILL_CAPS      (0x1 << 19)
 136 #define DMA_HAS_DESCRIPTOR_CAPS         (0x3 << 20)
 137
 138 enum omap_reg_offsets {
 139
 140 GCR,            GSCR,           GRST1,          HW_ID,
 141 PCH2_ID,        PCH0_ID,        PCH1_ID,        PCHG_ID,
 142 PCHD_ID,        CAPS_0,         CAPS_1,         CAPS_2,
 143 CAPS_3,         CAPS_4,         PCH2_SR,        PCH0_SR,
 144 PCH1_SR,        PCHD_SR,        REVISION,       IRQSTATUS_L0,
 145 IRQSTATUS_L1,   IRQSTATUS_L2,   IRQSTATUS_L3,   IRQENABLE_L0,
 146 IRQENABLE_L1,   IRQENABLE_L2,   IRQENABLE_L3,   SYSSTATUS,
 147 OCP_SYSCONFIG,
 148
 149 /* omap1+ specific */
 150 CPC, CCR2, LCH_CTRL,
 151
 152 /* Common registers for all omap's */
 153 CSDP,           CCR,            CICR,           CSR,
 154 CEN,            CFN,            CSFI,           CSEI,
 155 CSAC,           CDAC,           CDEI,
 156 CDFI,           CLNK_CTRL,
 157
 158 /* Channel specific registers */
 159 CSSA,           CDSA,           COLOR,
 160 CCEN,           CCFN,
 161
 162 /* omap3630 and omap4 specific */
 163 CDP,            CNDP,           CCDN,
 164
 165 };
 166
 167 enum omap_dma_burst_mode {
 168         OMAP_DMA_DATA_BURST_DIS = 0,
 169         OMAP_DMA_DATA_BURST_4,
 170         OMAP_DMA_DATA_BURST_8,
 171         OMAP_DMA_DATA_BURST_16,
 172 };
 173
 174 enum end_type {
 175         OMAP_DMA_LITTLE_ENDIAN = 0,
 176         OMAP_DMA_BIG_ENDIAN
 177 };
 178
 179 enum omap_dma_color_mode {
 180         OMAP_DMA_COLOR_DIS = 0,
 181         OMAP_DMA_CONSTANT_FILL,
 182         OMAP_DMA_TRANSPARENT_COPY
 183 };
 184
 185 enum omap_dma_write_mode {
 186         OMAP_DMA_WRITE_NON_POSTED = 0,
 187         OMAP_DMA_WRITE_POSTED,
 188         OMAP_DMA_WRITE_LAST_NON_POSTED
 189 };
 190
 191 enum omap_dma_channel_mode {
 192         OMAP_DMA_LCH_2D = 0,
 193         OMAP_DMA_LCH_G,
 194         OMAP_DMA_LCH_P,
 195         OMAP_DMA_LCH_PD
 196 };
 197
 198 struct omap_dma_channel_params {
 199         int data_type;          /* data type 8,16,32 */
 200         int elem_count;         /* number of elements in a frame */
 201         int frame_count;        /* number of frames in a element */
 202
 203         int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 204         int src_amode;          /* constant, post increment, indexed,
 205                                         double indexed */
 206         unsigned long src_start;        /* source address : physical */
 207         int src_ei;             /* source element index */
 208         int src_fi;             /* source frame index */
 209
 210         int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 211         int dst_amode;          /* constant, post increment, indexed,
 212                                         double indexed */
 213         unsigned long dst_start;        /* source address : physical */
 214         int dst_ei;             /* source element index */
 215         int dst_fi;             /* source frame index */
 216
 217         int trigger;            /* trigger attached if the channel is
 218                                         synchronized */
 219         int sync_mode;          /* sycn on element, frame , block or packet */
 220         int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
 221
 222         int ie;                 /* interrupt enabled */
 223
 224         unsigned char read_prio;/* read priority */
 225         unsigned char write_prio;/* write priority */
 226
 227 #ifndef CONFIG_ARCH_OMAP1
 228         enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
 229 #endif
 230 };
 231
 232 struct omap_dma_lch {
 233         int next_lch;
 234         int dev_id;
 235         u16 saved_csr;
 236         u16 enabled_irqs;
 237         const char *dev_name;
 238         void (*callback)(int lch, u16 ch_status, void *data);
 239         void *data;
 240         long flags;
 241         int state;
 242         int chain_id;
 243         int status;
 244 };
 245
 246 struct omap_dma_dev_attr {
 247         u32 dev_caps;
 248         u16 lch_count;
 249         u16 chan_count;
 250 };
 251
 252 enum {
 253         OMAP_DMA_REG_NONE,
 254         OMAP_DMA_REG_16BIT,
 255         OMAP_DMA_REG_2X16BIT,
 256         OMAP_DMA_REG_32BIT,
 257 };
 258
 259 struct omap_dma_reg {
 260         u16     offset;
 261         u8      stride;
 262         u8      type;
 263 };
 264
 265 #define SDMA_FILTER_PARAM(hw_req)       ((int[]) { (hw_req) })
 266 struct dma_slave_map;
 267
 268 /* System DMA platform data structure */
 269 struct omap_system_dma_plat_info {
 270         const struct omap_dma_reg *reg_map;
 271         unsigned channel_stride;
 272         struct omap_dma_dev_attr *dma_attr;
 273         u32 errata;
 274         void (*show_dma_caps)(void);
 275         void (*clear_lch_regs)(int lch);
 276         void (*clear_dma)(int lch);
 277         void (*dma_write)(u32 val, int reg, int lch);
 278         u32 (*dma_read)(int reg, int lch);
 279
 280         const struct dma_slave_map *slave_map;
 281         int slavecnt;
 282 };
 283
 284 #ifdef CONFIG_ARCH_OMAP2PLUS
 285 #define dma_omap2plus() 1
 286 #else
 287 #define dma_omap2plus() 0
 288 #endif
 289 #define dma_omap1()     (!dma_omap2plus())
 290 #define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
 291 #define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
 292 #define dma_omap15xx()  __dma_omap15xx(d)
 293 #define dma_omap16xx()  __dma_omap16xx(d)
 294
 295 #if defined(CONFIG_ARCH_OMAP)
 296 extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
 297
 298 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 299 extern int omap_request_dma(int dev_id, const char *dev_name,
 300                         void (*callback)(int lch, u16 ch_status, void *data),
 301                         void *data, int *dma_ch);
 302 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
 303 extern void omap_free_dma(int ch);
 304 extern void omap_start_dma(int lch);
 305 extern void omap_stop_dma(int lch);
 306 extern void omap_set_dma_transfer_params(int lch, int data_type,
 307                                          int elem_count, int frame_count,
 308                                          int sync_mode,
 309                                          int dma_trigger, int src_or_dst_synch);
 310 extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
 311
 312 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 313                                     unsigned long src_start,
 314                                     int src_ei, int src_fi);
 315 extern void omap_set_dma_src_data_pack(int lch, int enable);
 316 extern void omap_set_dma_src_burst_mode(int lch,
 317                                         enum omap_dma_burst_mode burst_mode);
 318
 319 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 320                                      unsigned long dest_start,
 321                                      int dst_ei, int dst_fi);
 322 extern void omap_set_dma_dest_data_pack(int lch, int enable);
 323 extern void omap_set_dma_dest_burst_mode(int lch,
 324                                          enum omap_dma_burst_mode burst_mode);
 325
 326 extern dma_addr_t omap_get_dma_src_pos(int lch);
 327 extern dma_addr_t omap_get_dma_dst_pos(int lch);
 328 extern int omap_get_dma_active_status(int lch);
 329 extern int omap_dma_running(void);
 330
 331 #if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP)
 332 #include <mach/lcd_dma.h>
 333 #else
 334 static inline int omap_lcd_dma_running(void)
 335 {
 336         return 0;
 337 }
 338 #endif
 339
 340 #else /* CONFIG_ARCH_OMAP */
 341
 342 static inline struct omap_system_dma_plat_info *omap_get_plat_info(void)
 343 {
 344         return NULL;
 345 }
 346
 347 static inline int omap_request_dma(int dev_id, const char *dev_name,
 348                         void (*callback)(int lch, u16 ch_status, void *data),
 349                         void *data, int *dma_ch)
 350 {
 351         return -ENODEV;
 352 }
 353
 354 static inline void omap_free_dma(int ch) { }
 355
 356 #endif /* CONFIG_ARCH_OMAP */
 357
 358 #endif /* __LINUX_OMAP_DMA_H */