1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus
*bus
; /* The bus this slot is on */
58 struct list_head list
; /* node in list of slots on this bus */
59 struct hotplug_slot
*hotplug
; /* Hotplug info (migrate over time) */
60 unsigned char number
; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot
*slot
)
66 return kobject_name(&slot
->kobj
);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
76 * For PCI devices, the region numbers are assigned this way:
79 /* #0-5: standard PCI resources */
81 PCI_STD_RESOURCE_END
= 5,
83 /* #6: expansion ROM resource */
86 /* device specific resources */
89 PCI_IOV_RESOURCE_END
= PCI_IOV_RESOURCES
+ PCI_SRIOV_NUM_BARS
- 1,
92 /* resources assigned to buses behind the bridge */
93 #define PCI_BRIDGE_RESOURCE_NUM 4
96 PCI_BRIDGE_RESOURCE_END
= PCI_BRIDGE_RESOURCES
+
97 PCI_BRIDGE_RESOURCE_NUM
- 1,
99 /* total resources associated with a PCI device */
102 /* preserve this for compatibility */
103 DEVICE_COUNT_RESOURCE
= PCI_NUM_RESOURCES
,
107 * enum pci_interrupt_pin - PCI INTx interrupt values
108 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
109 * @PCI_INTERRUPT_INTA: PCI INTA pin
110 * @PCI_INTERRUPT_INTB: PCI INTB pin
111 * @PCI_INTERRUPT_INTC: PCI INTC pin
112 * @PCI_INTERRUPT_INTD: PCI INTD pin
114 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
115 * PCI_INTERRUPT_PIN register.
117 enum pci_interrupt_pin
{
118 PCI_INTERRUPT_UNKNOWN
,
125 /* The number of legacy PCI INTx interrupts */
126 #define PCI_NUM_INTX 4
129 * pci_power_t values must match the bits in the Capabilities PME_Support
130 * and Control/Status PowerState fields in the Power Management capability.
132 typedef int __bitwise pci_power_t
;
134 #define PCI_D0 ((pci_power_t __force) 0)
135 #define PCI_D1 ((pci_power_t __force) 1)
136 #define PCI_D2 ((pci_power_t __force) 2)
137 #define PCI_D3hot ((pci_power_t __force) 3)
138 #define PCI_D3cold ((pci_power_t __force) 4)
139 #define PCI_UNKNOWN ((pci_power_t __force) 5)
140 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
142 /* Remember to update this when the list above changes! */
143 extern const char *pci_power_names
[];
145 static inline const char *pci_power_name(pci_power_t state
)
147 return pci_power_names
[1 + (__force
int) state
];
150 #define PCI_PM_D2_DELAY 200
151 #define PCI_PM_D3_WAIT 10
152 #define PCI_PM_D3COLD_WAIT 100
153 #define PCI_PM_BUS_WAIT 50
155 /** The pci_channel state describes connectivity between the CPU and
156 * the pci device. If some PCI bus between here and the pci device
157 * has crashed or locked up, this info is reflected here.
159 typedef unsigned int __bitwise pci_channel_state_t
;
161 enum pci_channel_state
{
162 /* I/O channel is in normal state */
163 pci_channel_io_normal
= (__force pci_channel_state_t
) 1,
165 /* I/O to channel is blocked */
166 pci_channel_io_frozen
= (__force pci_channel_state_t
) 2,
168 /* PCI card is dead */
169 pci_channel_io_perm_failure
= (__force pci_channel_state_t
) 3,
172 typedef unsigned int __bitwise pcie_reset_state_t
;
174 enum pcie_reset_state
{
175 /* Reset is NOT asserted (Use to deassert reset) */
176 pcie_deassert_reset
= (__force pcie_reset_state_t
) 1,
178 /* Use #PERST to reset PCIe device */
179 pcie_warm_reset
= (__force pcie_reset_state_t
) 2,
181 /* Use PCIe Hot Reset to reset device */
182 pcie_hot_reset
= (__force pcie_reset_state_t
) 3
185 typedef unsigned short __bitwise pci_dev_flags_t
;
187 /* INTX_DISABLE in PCI_COMMAND register disables MSI
190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
= (__force pci_dev_flags_t
) (1 << 0),
191 /* Device configuration is irrevocably lost if disabled into D3 */
192 PCI_DEV_FLAGS_NO_D3
= (__force pci_dev_flags_t
) (1 << 1),
193 /* Provide indication device is assigned by a Virtual Machine Manager */
194 PCI_DEV_FLAGS_ASSIGNED
= (__force pci_dev_flags_t
) (1 << 2),
195 /* Flag for quirk use to store if quirk-specific ACS is enabled */
196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
= (__force pci_dev_flags_t
) (1 << 3),
197 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
= (__force pci_dev_flags_t
) (1 << 5),
199 /* Do not use bus resets for device */
200 PCI_DEV_FLAGS_NO_BUS_RESET
= (__force pci_dev_flags_t
) (1 << 6),
201 /* Do not use PM reset even if device advertises NoSoftRst- */
202 PCI_DEV_FLAGS_NO_PM_RESET
= (__force pci_dev_flags_t
) (1 << 7),
203 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0
= (__force pci_dev_flags_t
) (1 << 8),
205 /* a non-root bridge where translation occurs, stop alias search here */
206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
= (__force pci_dev_flags_t
) (1 << 9),
207 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET
= (__force pci_dev_flags_t
) (1 << 10),
209 /* Don't use Relaxed Ordering for TLPs directed at this device */
210 PCI_DEV_FLAGS_NO_RELAXED_ORDERING
= (__force pci_dev_flags_t
) (1 << 11),
213 enum pci_irq_reroute_variant
{
214 INTEL_IRQ_REROUTE_VARIANT
= 1,
215 MAX_IRQ_REROUTE_VARIANTS
= 3
218 typedef unsigned short __bitwise pci_bus_flags_t
;
220 PCI_BUS_FLAGS_NO_MSI
= (__force pci_bus_flags_t
) 1,
221 PCI_BUS_FLAGS_NO_MMRBC
= (__force pci_bus_flags_t
) 2,
222 PCI_BUS_FLAGS_NO_AERSID
= (__force pci_bus_flags_t
) 4,
225 /* These values come from the PCI Express Spec */
226 enum pcie_link_width
{
227 PCIE_LNK_WIDTH_RESRV
= 0x00,
235 PCIE_LNK_WIDTH_UNKNOWN
= 0xFF,
238 /* Based on the PCI Hotplug Spec, but some values are made up by us */
240 PCI_SPEED_33MHz
= 0x00,
241 PCI_SPEED_66MHz
= 0x01,
242 PCI_SPEED_66MHz_PCIX
= 0x02,
243 PCI_SPEED_100MHz_PCIX
= 0x03,
244 PCI_SPEED_133MHz_PCIX
= 0x04,
245 PCI_SPEED_66MHz_PCIX_ECC
= 0x05,
246 PCI_SPEED_100MHz_PCIX_ECC
= 0x06,
247 PCI_SPEED_133MHz_PCIX_ECC
= 0x07,
248 PCI_SPEED_66MHz_PCIX_266
= 0x09,
249 PCI_SPEED_100MHz_PCIX_266
= 0x0a,
250 PCI_SPEED_133MHz_PCIX_266
= 0x0b,
256 PCI_SPEED_66MHz_PCIX_533
= 0x11,
257 PCI_SPEED_100MHz_PCIX_533
= 0x12,
258 PCI_SPEED_133MHz_PCIX_533
= 0x13,
259 PCIE_SPEED_2_5GT
= 0x14,
260 PCIE_SPEED_5_0GT
= 0x15,
261 PCIE_SPEED_8_0GT
= 0x16,
262 PCI_SPEED_UNKNOWN
= 0xff,
265 struct pci_cap_saved_data
{
272 struct pci_cap_saved_state
{
273 struct hlist_node next
;
274 struct pci_cap_saved_data cap
;
278 struct pcie_link_state
;
284 * The pci_dev structure is used to describe PCI devices.
287 struct list_head bus_list
; /* node in per-bus list */
288 struct pci_bus
*bus
; /* bus this device is on */
289 struct pci_bus
*subordinate
; /* bus this device bridges to */
291 void *sysdata
; /* hook for sys-specific extension */
292 struct proc_dir_entry
*procent
; /* device entry in /proc/bus/pci */
293 struct pci_slot
*slot
; /* Physical slot this device is in */
295 unsigned int devfn
; /* encoded device & function index */
296 unsigned short vendor
;
297 unsigned short device
;
298 unsigned short subsystem_vendor
;
299 unsigned short subsystem_device
;
300 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
301 u8 revision
; /* PCI revision, low byte of class word */
302 u8 hdr_type
; /* PCI header type (`multi' flag masked out) */
303 #ifdef CONFIG_PCIEAER
304 u16 aer_cap
; /* AER capability offset */
306 u8 pcie_cap
; /* PCIe capability offset */
307 u8 msi_cap
; /* MSI capability offset */
308 u8 msix_cap
; /* MSI-X capability offset */
309 u8 pcie_mpss
:3; /* PCIe Max Payload Size Supported */
310 u8 rom_base_reg
; /* which config register controls the ROM */
311 u8 pin
; /* which interrupt pin this device uses */
312 u16 pcie_flags_reg
; /* cached PCIe Capabilities Register */
313 unsigned long *dma_alias_mask
;/* mask of enabled devfn aliases */
315 struct pci_driver
*driver
; /* which driver has allocated this device */
316 u64 dma_mask
; /* Mask of the bits of bus address this
317 device implements. Normally this is
318 0xffffffff. You only need to change
319 this if your device has broken DMA
320 or supports 64-bit transfers. */
322 struct device_dma_parameters dma_parms
;
324 pci_power_t current_state
; /* Current operating state. In ACPI-speak,
325 this is D0-D3, D0 being fully functional,
327 u8 pm_cap
; /* PM capability offset */
328 unsigned int pme_support
:5; /* Bitmask of states from which PME#
330 unsigned int pme_poll
:1; /* Poll device's PME status bit */
331 unsigned int d1_support
:1; /* Low power state D1 is supported */
332 unsigned int d2_support
:1; /* Low power state D2 is supported */
333 unsigned int no_d1d2
:1; /* D1 and D2 are forbidden */
334 unsigned int no_d3cold
:1; /* D3cold is forbidden */
335 unsigned int bridge_d3
:1; /* Allow D3 for bridge */
336 unsigned int d3cold_allowed
:1; /* D3cold is allowed by user */
337 unsigned int mmio_always_on
:1; /* disallow turning off io/mem
338 decoding during bar sizing */
339 unsigned int wakeup_prepared
:1;
340 unsigned int runtime_d3cold
:1; /* whether go through runtime
341 D3cold, not set for devices
342 powered on/off by the
343 corresponding bridge */
344 unsigned int ignore_hotplug
:1; /* Ignore hotplug events */
345 unsigned int hotplug_user_indicators
:1; /* SlotCtl indicators
346 controlled exclusively by
348 unsigned int d3_delay
; /* D3->D0 transition time in ms */
349 unsigned int d3cold_delay
; /* D3cold->D0 transition time in ms */
351 #ifdef CONFIG_PCIEASPM
352 struct pcie_link_state
*link_state
; /* ASPM link state */
353 unsigned int ltr_path
:1; /* Latency Tolerance Reporting
354 supported from root to here */
357 pci_channel_state_t error_state
; /* current connectivity state */
358 struct device dev
; /* Generic device interface */
360 int cfg_size
; /* Size of configuration space */
363 * Instead of touching interrupt line and base address registers
364 * directly, use the values stored here. They might be different!
367 struct resource resource
[DEVICE_COUNT_RESOURCE
]; /* I/O and memory regions + expansion ROMs */
369 bool match_driver
; /* Skip attaching driver */
370 /* These fields are used by common fixups */
371 unsigned int transparent
:1; /* Subtractive decode PCI bridge */
372 unsigned int multifunction
:1;/* Part of multi-function device */
373 /* keep track of device state */
374 unsigned int is_added
:1;
375 unsigned int is_busmaster
:1; /* device is busmaster */
376 unsigned int no_msi
:1; /* device may not use msi */
377 unsigned int no_64bit_msi
:1; /* device may only use 32-bit MSIs */
378 unsigned int block_cfg_access
:1; /* config space access is blocked */
379 unsigned int broken_parity_status
:1; /* Device generates false positive parity */
380 unsigned int irq_reroute_variant
:2; /* device needs IRQ rerouting variant */
381 unsigned int msi_enabled
:1;
382 unsigned int msix_enabled
:1;
383 unsigned int ari_enabled
:1; /* ARI forwarding */
384 unsigned int ats_enabled
:1; /* Address Translation Service */
385 unsigned int pasid_enabled
:1; /* Process Address Space ID */
386 unsigned int pri_enabled
:1; /* Page Request Interface */
387 unsigned int is_managed
:1;
388 unsigned int needs_freset
:1; /* Dev requires fundamental reset */
389 unsigned int state_saved
:1;
390 unsigned int is_physfn
:1;
391 unsigned int is_virtfn
:1;
392 unsigned int reset_fn
:1;
393 unsigned int is_hotplug_bridge
:1;
394 unsigned int is_thunderbolt
:1; /* Thunderbolt controller */
395 unsigned int __aer_firmware_first_valid
:1;
396 unsigned int __aer_firmware_first
:1;
397 unsigned int broken_intx_masking
:1; /* INTx masking can't be used */
398 unsigned int io_window_1k
:1; /* Intel P2P bridge 1K I/O windows */
399 unsigned int irq_managed
:1;
400 unsigned int has_secondary_link
:1;
401 unsigned int non_compliant_bars
:1; /* broken BARs; ignore them */
402 unsigned int is_probed
:1; /* device probing in progress */
403 pci_dev_flags_t dev_flags
;
404 atomic_t enable_cnt
; /* pci_enable_device has been called */
406 u32 saved_config_space
[16]; /* config space saved at suspend time */
407 struct hlist_head saved_cap_space
;
408 struct bin_attribute
*rom_attr
; /* attribute descriptor for sysfs ROM entry */
409 int rom_attr_enabled
; /* has display of the rom attribute been enabled? */
410 struct bin_attribute
*res_attr
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for resources */
411 struct bin_attribute
*res_attr_wc
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for WC mapping of resources */
413 #ifdef CONFIG_PCIE_PTM
414 unsigned int ptm_root
:1;
415 unsigned int ptm_enabled
:1;
418 #ifdef CONFIG_PCI_MSI
419 const struct attribute_group
**msi_irq_groups
;
422 #ifdef CONFIG_PCI_ATS
424 struct pci_sriov
*sriov
; /* SR-IOV capability related */
425 struct pci_dev
*physfn
; /* the PF this VF is associated with */
427 u16 ats_cap
; /* ATS Capability offset */
428 u8 ats_stu
; /* ATS Smallest Translation Unit */
429 atomic_t ats_ref_cnt
; /* number of VFs with ATS enabled */
431 #ifdef CONFIG_PCI_PRI
432 u32 pri_reqs_alloc
; /* Number of PRI requests allocated */
434 #ifdef CONFIG_PCI_PASID
437 phys_addr_t rom
; /* Physical address of ROM if it's not from the BAR */
438 size_t romlen
; /* Length of ROM if it's not from the BAR */
439 char *driver_override
; /* Driver name to force a match */
441 unsigned long priv_flags
; /* Private flags for the pci driver */
444 static inline struct pci_dev
*pci_physfn(struct pci_dev
*dev
)
446 #ifdef CONFIG_PCI_IOV
453 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
);
455 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
456 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
458 static inline int pci_channel_offline(struct pci_dev
*pdev
)
460 return (pdev
->error_state
!= pci_channel_io_normal
);
463 struct pci_host_bridge
{
465 struct pci_bus
*bus
; /* root bus */
469 struct list_head windows
; /* resource_entry */
470 u8 (*swizzle_irq
)(struct pci_dev
*, u8
*); /* platform IRQ swizzler */
471 int (*map_irq
)(const struct pci_dev
*, u8
, u8
);
472 void (*release_fn
)(struct pci_host_bridge
*);
474 struct msi_controller
*msi
;
475 unsigned int ignore_reset_delay
:1; /* for entire hierarchy */
476 unsigned int no_ext_tags
:1; /* no Extended Tags */
477 /* Resource alignment requirements */
478 resource_size_t (*align_resource
)(struct pci_dev
*dev
,
479 const struct resource
*res
,
480 resource_size_t start
,
481 resource_size_t size
,
482 resource_size_t align
);
483 unsigned long private[0] ____cacheline_aligned
;
486 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
488 static inline void *pci_host_bridge_priv(struct pci_host_bridge
*bridge
)
490 return (void *)bridge
->private;
493 static inline struct pci_host_bridge
*pci_host_bridge_from_priv(void *priv
)
495 return container_of(priv
, struct pci_host_bridge
, private);
498 struct pci_host_bridge
*pci_alloc_host_bridge(size_t priv
);
499 struct pci_host_bridge
*devm_pci_alloc_host_bridge(struct device
*dev
,
501 void pci_free_host_bridge(struct pci_host_bridge
*bridge
);
502 struct pci_host_bridge
*pci_find_host_bridge(struct pci_bus
*bus
);
504 void pci_set_host_bridge_release(struct pci_host_bridge
*bridge
,
505 void (*release_fn
)(struct pci_host_bridge
*),
508 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
);
511 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
512 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
513 * buses below host bridges or subtractive decode bridges) go in the list.
514 * Use pci_bus_for_each_resource() to iterate through all the resources.
518 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
519 * and there's no way to program the bridge with the details of the window.
520 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
521 * decode bit set, because they are explicit and can be programmed with _SRS.
523 #define PCI_SUBTRACTIVE_DECODE 0x1
525 struct pci_bus_resource
{
526 struct list_head list
;
527 struct resource
*res
;
531 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
534 struct list_head node
; /* node in list of buses */
535 struct pci_bus
*parent
; /* parent bus this bridge is on */
536 struct list_head children
; /* list of child buses */
537 struct list_head devices
; /* list of devices on this bus */
538 struct pci_dev
*self
; /* bridge device as seen by parent */
539 struct list_head slots
; /* list of slots on this bus;
540 protected by pci_slot_mutex */
541 struct resource
*resource
[PCI_BRIDGE_RESOURCE_NUM
];
542 struct list_head resources
; /* address space routed to this bus */
543 struct resource busn_res
; /* bus numbers routed to this bus */
545 struct pci_ops
*ops
; /* configuration access functions */
546 struct msi_controller
*msi
; /* MSI controller */
547 void *sysdata
; /* hook for sys-specific extension */
548 struct proc_dir_entry
*procdir
; /* directory entry in /proc/bus/pci */
550 unsigned char number
; /* bus number */
551 unsigned char primary
; /* number of primary bridge */
552 unsigned char max_bus_speed
; /* enum pci_bus_speed */
553 unsigned char cur_bus_speed
; /* enum pci_bus_speed */
554 #ifdef CONFIG_PCI_DOMAINS_GENERIC
560 unsigned short bridge_ctl
; /* manage NO_ISA/FBB/et al behaviors */
561 pci_bus_flags_t bus_flags
; /* inherited by child buses */
562 struct device
*bridge
;
564 struct bin_attribute
*legacy_io
; /* legacy I/O for this bus */
565 struct bin_attribute
*legacy_mem
; /* legacy mem */
566 unsigned int is_added
:1;
569 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
572 * Returns true if the PCI bus is root (behind host-PCI bridge),
575 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
576 * This is incorrect because "virtual" buses added for SR-IOV (via
577 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
579 static inline bool pci_is_root_bus(struct pci_bus
*pbus
)
581 return !(pbus
->parent
);
585 * pci_is_bridge - check if the PCI device is a bridge
588 * Return true if the PCI device is bridge whether it has subordinate
591 static inline bool pci_is_bridge(struct pci_dev
*dev
)
593 return dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
594 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
;
597 #define for_each_pci_bridge(dev, bus) \
598 list_for_each_entry(dev, &bus->devices, bus_list) \
599 if (!pci_is_bridge(dev)) {} else
601 static inline struct pci_dev
*pci_upstream_bridge(struct pci_dev
*dev
)
603 dev
= pci_physfn(dev
);
604 if (pci_is_root_bus(dev
->bus
))
607 return dev
->bus
->self
;
610 struct device
*pci_get_host_bridge_device(struct pci_dev
*dev
);
611 void pci_put_host_bridge_device(struct device
*dev
);
613 #ifdef CONFIG_PCI_MSI
614 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
)
616 return pci_dev
->msi_enabled
|| pci_dev
->msix_enabled
;
619 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
) { return false; }
623 * Error values that may be returned by PCI functions.
625 #define PCIBIOS_SUCCESSFUL 0x00
626 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
627 #define PCIBIOS_BAD_VENDOR_ID 0x83
628 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
629 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
630 #define PCIBIOS_SET_FAILED 0x88
631 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
634 * Translate above to generic errno for passing back through non-PCI code.
636 static inline int pcibios_err_to_errno(int err
)
638 if (err
<= PCIBIOS_SUCCESSFUL
)
639 return err
; /* Assume already errno */
642 case PCIBIOS_FUNC_NOT_SUPPORTED
:
644 case PCIBIOS_BAD_VENDOR_ID
:
646 case PCIBIOS_DEVICE_NOT_FOUND
:
648 case PCIBIOS_BAD_REGISTER_NUMBER
:
650 case PCIBIOS_SET_FAILED
:
652 case PCIBIOS_BUFFER_TOO_SMALL
:
659 /* Low-level architecture-dependent routines */
662 int (*add_bus
)(struct pci_bus
*bus
);
663 void (*remove_bus
)(struct pci_bus
*bus
);
664 void __iomem
*(*map_bus
)(struct pci_bus
*bus
, unsigned int devfn
, int where
);
665 int (*read
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
666 int (*write
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
670 * ACPI needs to be able to access PCI config space before we've done a
671 * PCI bus scan and created pci_bus structures.
673 int raw_pci_read(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
674 int reg
, int len
, u32
*val
);
675 int raw_pci_write(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
676 int reg
, int len
, u32 val
);
678 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
679 typedef u64 pci_bus_addr_t
;
681 typedef u32 pci_bus_addr_t
;
684 struct pci_bus_region
{
685 pci_bus_addr_t start
;
690 spinlock_t lock
; /* protects list, index */
691 struct list_head list
; /* for IDs added at runtime */
696 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
697 * a set of callbacks in struct pci_error_handlers, that device driver
698 * will be notified of PCI bus errors, and will be driven to recovery
699 * when an error occurs.
702 typedef unsigned int __bitwise pci_ers_result_t
;
704 enum pci_ers_result
{
705 /* no result/none/not supported in device driver */
706 PCI_ERS_RESULT_NONE
= (__force pci_ers_result_t
) 1,
708 /* Device driver can recover without slot reset */
709 PCI_ERS_RESULT_CAN_RECOVER
= (__force pci_ers_result_t
) 2,
711 /* Device driver wants slot to be reset. */
712 PCI_ERS_RESULT_NEED_RESET
= (__force pci_ers_result_t
) 3,
714 /* Device has completely failed, is unrecoverable */
715 PCI_ERS_RESULT_DISCONNECT
= (__force pci_ers_result_t
) 4,
717 /* Device driver is fully recovered and operational */
718 PCI_ERS_RESULT_RECOVERED
= (__force pci_ers_result_t
) 5,
720 /* No AER capabilities registered for the driver */
721 PCI_ERS_RESULT_NO_AER_DRIVER
= (__force pci_ers_result_t
) 6,
724 /* PCI bus error event callbacks */
725 struct pci_error_handlers
{
726 /* PCI bus error detected on this device */
727 pci_ers_result_t (*error_detected
)(struct pci_dev
*dev
,
728 enum pci_channel_state error
);
730 /* MMIO has been re-enabled, but not DMA */
731 pci_ers_result_t (*mmio_enabled
)(struct pci_dev
*dev
);
733 /* PCI slot has been reset */
734 pci_ers_result_t (*slot_reset
)(struct pci_dev
*dev
);
736 /* PCI function reset prepare or completed */
737 void (*reset_prepare
)(struct pci_dev
*dev
);
738 void (*reset_done
)(struct pci_dev
*dev
);
740 /* Device driver may resume normal operations */
741 void (*resume
)(struct pci_dev
*dev
);
747 struct list_head node
;
749 const struct pci_device_id
*id_table
; /* must be non-NULL for probe to be called */
750 int (*probe
) (struct pci_dev
*dev
, const struct pci_device_id
*id
); /* New device inserted */
751 void (*remove
) (struct pci_dev
*dev
); /* Device removed (NULL if not a hot-plug capable driver) */
752 int (*suspend
) (struct pci_dev
*dev
, pm_message_t state
); /* Device suspended */
753 int (*suspend_late
) (struct pci_dev
*dev
, pm_message_t state
);
754 int (*resume_early
) (struct pci_dev
*dev
);
755 int (*resume
) (struct pci_dev
*dev
); /* Device woken up */
756 void (*shutdown
) (struct pci_dev
*dev
);
757 int (*sriov_configure
) (struct pci_dev
*dev
, int num_vfs
); /* PF pdev */
758 const struct pci_error_handlers
*err_handler
;
759 const struct attribute_group
**groups
;
760 struct device_driver driver
;
761 struct pci_dynids dynids
;
764 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
767 * PCI_DEVICE - macro used to describe a specific pci device
768 * @vend: the 16 bit PCI Vendor ID
769 * @dev: the 16 bit PCI Device ID
771 * This macro is used to create a struct pci_device_id that matches a
772 * specific device. The subvendor and subdevice fields will be set to
775 #define PCI_DEVICE(vend,dev) \
776 .vendor = (vend), .device = (dev), \
777 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
780 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
781 * @vend: the 16 bit PCI Vendor ID
782 * @dev: the 16 bit PCI Device ID
783 * @subvend: the 16 bit PCI Subvendor ID
784 * @subdev: the 16 bit PCI Subdevice ID
786 * This macro is used to create a struct pci_device_id that matches a
787 * specific device with subsystem information.
789 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
790 .vendor = (vend), .device = (dev), \
791 .subvendor = (subvend), .subdevice = (subdev)
794 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
795 * @dev_class: the class, subclass, prog-if triple for this device
796 * @dev_class_mask: the class mask for this device
798 * This macro is used to create a struct pci_device_id that matches a
799 * specific PCI class. The vendor, device, subvendor, and subdevice
800 * fields will be set to PCI_ANY_ID.
802 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
803 .class = (dev_class), .class_mask = (dev_class_mask), \
804 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
805 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
808 * PCI_VDEVICE - macro used to describe a specific pci device in short form
809 * @vend: the vendor name
810 * @dev: the 16 bit PCI Device ID
812 * This macro is used to create a struct pci_device_id that matches a
813 * specific PCI device. The subvendor, and subdevice fields will be set
814 * to PCI_ANY_ID. The macro allows the next field to follow as the device
818 #define PCI_VDEVICE(vend, dev) \
819 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
820 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
823 PCI_REASSIGN_ALL_RSRC
= 0x00000001, /* ignore firmware setup */
824 PCI_REASSIGN_ALL_BUS
= 0x00000002, /* reassign all bus numbers */
825 PCI_PROBE_ONLY
= 0x00000004, /* use existing setup */
826 PCI_CAN_SKIP_ISA_ALIGN
= 0x00000008, /* don't do ISA alignment */
827 PCI_ENABLE_PROC_DOMAINS
= 0x00000010, /* enable domains in /proc */
828 PCI_COMPAT_DOMAIN_0
= 0x00000020, /* ... except domain 0 */
829 PCI_SCAN_ALL_PCIE_DEVS
= 0x00000040, /* scan all, not just dev 0 */
832 /* these external functions are only available when PCI support is enabled */
835 extern unsigned int pci_flags
;
837 static inline void pci_set_flags(int flags
) { pci_flags
= flags
; }
838 static inline void pci_add_flags(int flags
) { pci_flags
|= flags
; }
839 static inline void pci_clear_flags(int flags
) { pci_flags
&= ~flags
; }
840 static inline int pci_has_flag(int flag
) { return pci_flags
& flag
; }
842 void pcie_bus_configure_settings(struct pci_bus
*bus
);
844 enum pcie_bus_config_types
{
845 PCIE_BUS_TUNE_OFF
, /* don't touch MPS at all */
846 PCIE_BUS_DEFAULT
, /* ensure MPS matches upstream bridge */
847 PCIE_BUS_SAFE
, /* use largest MPS boot-time devices support */
848 PCIE_BUS_PERFORMANCE
, /* use MPS and MRRS for best performance */
849 PCIE_BUS_PEER2PEER
, /* set MPS = 128 for all devices */
852 extern enum pcie_bus_config_types pcie_bus_config
;
854 extern struct bus_type pci_bus_type
;
856 /* Do NOT directly access these two variables, unless you are arch-specific PCI
857 * code, or PCI core code. */
858 extern struct list_head pci_root_buses
; /* list of all known PCI buses */
859 /* Some device drivers need know if PCI is initiated */
860 int no_pci_devices(void);
862 void pcibios_resource_survey_bus(struct pci_bus
*bus
);
863 void pcibios_bus_add_device(struct pci_dev
*pdev
);
864 void pcibios_add_bus(struct pci_bus
*bus
);
865 void pcibios_remove_bus(struct pci_bus
*bus
);
866 void pcibios_fixup_bus(struct pci_bus
*);
867 int __must_check
pcibios_enable_device(struct pci_dev
*, int mask
);
868 /* Architecture-specific versions may override this (weak) */
869 char *pcibios_setup(char *str
);
871 /* Used only when drivers/pci/setup.c is used */
872 resource_size_t
pcibios_align_resource(void *, const struct resource
*,
876 /* Weak but can be overriden by arch */
877 void pci_fixup_cardbus(struct pci_bus
*);
879 /* Generic PCI functions used internally */
881 void pcibios_resource_to_bus(struct pci_bus
*bus
, struct pci_bus_region
*region
,
882 struct resource
*res
);
883 void pcibios_bus_to_resource(struct pci_bus
*bus
, struct resource
*res
,
884 struct pci_bus_region
*region
);
885 void pcibios_scan_specific_bus(int busn
);
886 struct pci_bus
*pci_find_bus(int domain
, int busnr
);
887 void pci_bus_add_devices(const struct pci_bus
*bus
);
888 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
);
889 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
890 struct pci_ops
*ops
, void *sysdata
,
891 struct list_head
*resources
);
892 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int busmax
);
893 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int busmax
);
894 void pci_bus_release_busn_res(struct pci_bus
*b
);
895 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
896 struct pci_ops
*ops
, void *sysdata
,
897 struct list_head
*resources
);
898 int pci_scan_root_bus_bridge(struct pci_host_bridge
*bridge
);
899 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
901 void pcie_update_link_speed(struct pci_bus
*bus
, u16 link_status
);
902 struct pci_slot
*pci_create_slot(struct pci_bus
*parent
, int slot_nr
,
904 struct hotplug_slot
*hotplug
);
905 void pci_destroy_slot(struct pci_slot
*slot
);
907 void pci_dev_assign_slot(struct pci_dev
*dev
);
909 static inline void pci_dev_assign_slot(struct pci_dev
*dev
) { }
911 int pci_scan_slot(struct pci_bus
*bus
, int devfn
);
912 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
);
913 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
);
914 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
915 void pci_bus_add_device(struct pci_dev
*dev
);
916 void pci_read_bridge_bases(struct pci_bus
*child
);
917 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
918 struct resource
*res
);
919 struct pci_dev
*pci_find_pcie_root_port(struct pci_dev
*dev
);
920 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
);
921 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
);
922 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
);
923 struct pci_dev
*pci_dev_get(struct pci_dev
*dev
);
924 void pci_dev_put(struct pci_dev
*dev
);
925 void pci_remove_bus(struct pci_bus
*b
);
926 void pci_stop_and_remove_bus_device(struct pci_dev
*dev
);
927 void pci_stop_and_remove_bus_device_locked(struct pci_dev
*dev
);
928 void pci_stop_root_bus(struct pci_bus
*bus
);
929 void pci_remove_root_bus(struct pci_bus
*bus
);
930 void pci_setup_cardbus(struct pci_bus
*bus
);
931 void pcibios_setup_bridge(struct pci_bus
*bus
, unsigned long type
);
932 void pci_sort_breadthfirst(void);
933 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
934 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
936 /* Generic PCI functions exported to card drivers */
938 enum pci_lost_interrupt_reason
{
939 PCI_LOST_IRQ_NO_INFORMATION
= 0,
940 PCI_LOST_IRQ_DISABLE_MSI
,
941 PCI_LOST_IRQ_DISABLE_MSIX
,
942 PCI_LOST_IRQ_DISABLE_ACPI
,
944 enum pci_lost_interrupt_reason
pci_lost_interrupt(struct pci_dev
*dev
);
945 int pci_find_capability(struct pci_dev
*dev
, int cap
);
946 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
);
947 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
);
948 int pci_find_next_ext_capability(struct pci_dev
*dev
, int pos
, int cap
);
949 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
);
950 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
);
951 struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
);
953 struct pci_dev
*pci_get_device(unsigned int vendor
, unsigned int device
,
954 struct pci_dev
*from
);
955 struct pci_dev
*pci_get_subsys(unsigned int vendor
, unsigned int device
,
956 unsigned int ss_vendor
, unsigned int ss_device
,
957 struct pci_dev
*from
);
958 struct pci_dev
*pci_get_slot(struct pci_bus
*bus
, unsigned int devfn
);
959 struct pci_dev
*pci_get_domain_bus_and_slot(int domain
, unsigned int bus
,
961 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
964 return pci_get_domain_bus_and_slot(0, bus
, devfn
);
966 struct pci_dev
*pci_get_class(unsigned int class, struct pci_dev
*from
);
967 int pci_dev_present(const struct pci_device_id
*ids
);
969 int pci_bus_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
971 int pci_bus_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
972 int where
, u16
*val
);
973 int pci_bus_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
974 int where
, u32
*val
);
975 int pci_bus_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
977 int pci_bus_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
979 int pci_bus_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
982 int pci_generic_config_read(struct pci_bus
*bus
, unsigned int devfn
,
983 int where
, int size
, u32
*val
);
984 int pci_generic_config_write(struct pci_bus
*bus
, unsigned int devfn
,
985 int where
, int size
, u32 val
);
986 int pci_generic_config_read32(struct pci_bus
*bus
, unsigned int devfn
,
987 int where
, int size
, u32
*val
);
988 int pci_generic_config_write32(struct pci_bus
*bus
, unsigned int devfn
,
989 int where
, int size
, u32 val
);
991 struct pci_ops
*pci_bus_set_ops(struct pci_bus
*bus
, struct pci_ops
*ops
);
993 int pci_read_config_byte(const struct pci_dev
*dev
, int where
, u8
*val
);
994 int pci_read_config_word(const struct pci_dev
*dev
, int where
, u16
*val
);
995 int pci_read_config_dword(const struct pci_dev
*dev
, int where
, u32
*val
);
996 int pci_write_config_byte(const struct pci_dev
*dev
, int where
, u8 val
);
997 int pci_write_config_word(const struct pci_dev
*dev
, int where
, u16 val
);
998 int pci_write_config_dword(const struct pci_dev
*dev
, int where
, u32 val
);
1000 int pcie_capability_read_word(struct pci_dev
*dev
, int pos
, u16
*val
);
1001 int pcie_capability_read_dword(struct pci_dev
*dev
, int pos
, u32
*val
);
1002 int pcie_capability_write_word(struct pci_dev
*dev
, int pos
, u16 val
);
1003 int pcie_capability_write_dword(struct pci_dev
*dev
, int pos
, u32 val
);
1004 int pcie_capability_clear_and_set_word(struct pci_dev
*dev
, int pos
,
1005 u16 clear
, u16 set
);
1006 int pcie_capability_clear_and_set_dword(struct pci_dev
*dev
, int pos
,
1007 u32 clear
, u32 set
);
1009 static inline int pcie_capability_set_word(struct pci_dev
*dev
, int pos
,
1012 return pcie_capability_clear_and_set_word(dev
, pos
, 0, set
);
1015 static inline int pcie_capability_set_dword(struct pci_dev
*dev
, int pos
,
1018 return pcie_capability_clear_and_set_dword(dev
, pos
, 0, set
);
1021 static inline int pcie_capability_clear_word(struct pci_dev
*dev
, int pos
,
1024 return pcie_capability_clear_and_set_word(dev
, pos
, clear
, 0);
1027 static inline int pcie_capability_clear_dword(struct pci_dev
*dev
, int pos
,
1030 return pcie_capability_clear_and_set_dword(dev
, pos
, clear
, 0);
1033 /* user-space driven config access */
1034 int pci_user_read_config_byte(struct pci_dev
*dev
, int where
, u8
*val
);
1035 int pci_user_read_config_word(struct pci_dev
*dev
, int where
, u16
*val
);
1036 int pci_user_read_config_dword(struct pci_dev
*dev
, int where
, u32
*val
);
1037 int pci_user_write_config_byte(struct pci_dev
*dev
, int where
, u8 val
);
1038 int pci_user_write_config_word(struct pci_dev
*dev
, int where
, u16 val
);
1039 int pci_user_write_config_dword(struct pci_dev
*dev
, int where
, u32 val
);
1041 int __must_check
pci_enable_device(struct pci_dev
*dev
);
1042 int __must_check
pci_enable_device_io(struct pci_dev
*dev
);
1043 int __must_check
pci_enable_device_mem(struct pci_dev
*dev
);
1044 int __must_check
pci_reenable_device(struct pci_dev
*);
1045 int __must_check
pcim_enable_device(struct pci_dev
*pdev
);
1046 void pcim_pin_device(struct pci_dev
*pdev
);
1048 static inline bool pci_intx_mask_supported(struct pci_dev
*pdev
)
1051 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1052 * writable and no quirk has marked the feature broken.
1054 return !pdev
->broken_intx_masking
;
1057 static inline int pci_is_enabled(struct pci_dev
*pdev
)
1059 return (atomic_read(&pdev
->enable_cnt
) > 0);
1062 static inline int pci_is_managed(struct pci_dev
*pdev
)
1064 return pdev
->is_managed
;
1067 void pci_disable_device(struct pci_dev
*dev
);
1069 extern unsigned int pcibios_max_latency
;
1070 void pci_set_master(struct pci_dev
*dev
);
1071 void pci_clear_master(struct pci_dev
*dev
);
1073 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
);
1074 int pci_set_cacheline_size(struct pci_dev
*dev
);
1075 #define HAVE_PCI_SET_MWI
1076 int __must_check
pci_set_mwi(struct pci_dev
*dev
);
1077 int pci_try_set_mwi(struct pci_dev
*dev
);
1078 void pci_clear_mwi(struct pci_dev
*dev
);
1079 void pci_intx(struct pci_dev
*dev
, int enable
);
1080 bool pci_check_and_mask_intx(struct pci_dev
*dev
);
1081 bool pci_check_and_unmask_intx(struct pci_dev
*dev
);
1082 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
);
1083 int pci_wait_for_pending_transaction(struct pci_dev
*dev
);
1084 int pcix_get_max_mmrbc(struct pci_dev
*dev
);
1085 int pcix_get_mmrbc(struct pci_dev
*dev
);
1086 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
);
1087 int pcie_get_readrq(struct pci_dev
*dev
);
1088 int pcie_set_readrq(struct pci_dev
*dev
, int rq
);
1089 int pcie_get_mps(struct pci_dev
*dev
);
1090 int pcie_set_mps(struct pci_dev
*dev
, int mps
);
1091 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
1092 enum pcie_link_width
*width
);
1093 void pcie_flr(struct pci_dev
*dev
);
1094 int __pci_reset_function_locked(struct pci_dev
*dev
);
1095 int pci_reset_function(struct pci_dev
*dev
);
1096 int pci_reset_function_locked(struct pci_dev
*dev
);
1097 int pci_try_reset_function(struct pci_dev
*dev
);
1098 int pci_probe_reset_slot(struct pci_slot
*slot
);
1099 int pci_reset_slot(struct pci_slot
*slot
);
1100 int pci_try_reset_slot(struct pci_slot
*slot
);
1101 int pci_probe_reset_bus(struct pci_bus
*bus
);
1102 int pci_reset_bus(struct pci_bus
*bus
);
1103 int pci_try_reset_bus(struct pci_bus
*bus
);
1104 void pci_reset_secondary_bus(struct pci_dev
*dev
);
1105 void pcibios_reset_secondary_bus(struct pci_dev
*dev
);
1106 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
);
1107 void pci_update_resource(struct pci_dev
*dev
, int resno
);
1108 int __must_check
pci_assign_resource(struct pci_dev
*dev
, int i
);
1109 int __must_check
pci_reassign_resource(struct pci_dev
*dev
, int i
, resource_size_t add_size
, resource_size_t align
);
1110 void pci_release_resource(struct pci_dev
*dev
, int resno
);
1111 int __must_check
pci_resize_resource(struct pci_dev
*dev
, int i
, int size
);
1112 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
);
1113 bool pci_device_is_present(struct pci_dev
*pdev
);
1114 void pci_ignore_hotplug(struct pci_dev
*dev
);
1116 int __printf(6, 7) pci_request_irq(struct pci_dev
*dev
, unsigned int nr
,
1117 irq_handler_t handler
, irq_handler_t thread_fn
, void *dev_id
,
1118 const char *fmt
, ...);
1119 void pci_free_irq(struct pci_dev
*dev
, unsigned int nr
, void *dev_id
);
1121 /* ROM control related routines */
1122 int pci_enable_rom(struct pci_dev
*pdev
);
1123 void pci_disable_rom(struct pci_dev
*pdev
);
1124 void __iomem __must_check
*pci_map_rom(struct pci_dev
*pdev
, size_t *size
);
1125 void pci_unmap_rom(struct pci_dev
*pdev
, void __iomem
*rom
);
1126 size_t pci_get_rom_size(struct pci_dev
*pdev
, void __iomem
*rom
, size_t size
);
1127 void __iomem __must_check
*pci_platform_rom(struct pci_dev
*pdev
, size_t *size
);
1129 /* Power management related routines */
1130 int pci_save_state(struct pci_dev
*dev
);
1131 void pci_restore_state(struct pci_dev
*dev
);
1132 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
);
1133 int pci_load_saved_state(struct pci_dev
*dev
,
1134 struct pci_saved_state
*state
);
1135 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1136 struct pci_saved_state
**state
);
1137 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
);
1138 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
,
1140 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
);
1141 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
,
1142 u16 cap
, unsigned int size
);
1143 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
);
1144 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
);
1145 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
);
1146 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
);
1147 void pci_pme_active(struct pci_dev
*dev
, bool enable
);
1148 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
);
1149 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
);
1150 int pci_prepare_to_sleep(struct pci_dev
*dev
);
1151 int pci_back_from_sleep(struct pci_dev
*dev
);
1152 bool pci_dev_run_wake(struct pci_dev
*dev
);
1153 bool pci_check_pme_status(struct pci_dev
*dev
);
1154 void pci_pme_wakeup_bus(struct pci_bus
*bus
);
1155 void pci_d3cold_enable(struct pci_dev
*dev
);
1156 void pci_d3cold_disable(struct pci_dev
*dev
);
1157 bool pcie_relaxed_ordering_enabled(struct pci_dev
*dev
);
1159 /* PCI Virtual Channel */
1160 int pci_save_vc_state(struct pci_dev
*dev
);
1161 void pci_restore_vc_state(struct pci_dev
*dev
);
1162 void pci_allocate_vc_save_buffers(struct pci_dev
*dev
);
1164 /* For use by arch with custom probe code */
1165 void set_pcie_port_type(struct pci_dev
*pdev
);
1166 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
);
1168 /* Functions for PCI Hotplug drivers to use */
1169 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1170 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
);
1171 unsigned int pci_rescan_bus(struct pci_bus
*bus
);
1172 void pci_lock_rescan_remove(void);
1173 void pci_unlock_rescan_remove(void);
1175 /* Vital product data routines */
1176 ssize_t
pci_read_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, void *buf
);
1177 ssize_t
pci_write_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, const void *buf
);
1178 int pci_set_vpd_size(struct pci_dev
*dev
, size_t len
);
1180 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1181 resource_size_t
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
);
1182 void pci_bus_assign_resources(const struct pci_bus
*bus
);
1183 void pci_bus_claim_resources(struct pci_bus
*bus
);
1184 void pci_bus_size_bridges(struct pci_bus
*bus
);
1185 int pci_claim_resource(struct pci_dev
*, int);
1186 int pci_claim_bridge_resource(struct pci_dev
*bridge
, int i
);
1187 void pci_assign_unassigned_resources(void);
1188 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
);
1189 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
);
1190 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
);
1191 int pci_reassign_bridge_resources(struct pci_dev
*bridge
, unsigned long type
);
1192 void pdev_enable_device(struct pci_dev
*);
1193 int pci_enable_resources(struct pci_dev
*, int mask
);
1194 void pci_assign_irq(struct pci_dev
*dev
);
1195 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
);
1196 #define HAVE_PCI_REQ_REGIONS 2
1197 int __must_check
pci_request_regions(struct pci_dev
*, const char *);
1198 int __must_check
pci_request_regions_exclusive(struct pci_dev
*, const char *);
1199 void pci_release_regions(struct pci_dev
*);
1200 int __must_check
pci_request_region(struct pci_dev
*, int, const char *);
1201 int __must_check
pci_request_region_exclusive(struct pci_dev
*, int, const char *);
1202 void pci_release_region(struct pci_dev
*, int);
1203 int pci_request_selected_regions(struct pci_dev
*, int, const char *);
1204 int pci_request_selected_regions_exclusive(struct pci_dev
*, int, const char *);
1205 void pci_release_selected_regions(struct pci_dev
*, int);
1207 /* drivers/pci/bus.c */
1208 struct pci_bus
*pci_bus_get(struct pci_bus
*bus
);
1209 void pci_bus_put(struct pci_bus
*bus
);
1210 void pci_add_resource(struct list_head
*resources
, struct resource
*res
);
1211 void pci_add_resource_offset(struct list_head
*resources
, struct resource
*res
,
1212 resource_size_t offset
);
1213 void pci_free_resource_list(struct list_head
*resources
);
1214 void pci_bus_add_resource(struct pci_bus
*bus
, struct resource
*res
,
1215 unsigned int flags
);
1216 struct resource
*pci_bus_resource_n(const struct pci_bus
*bus
, int n
);
1217 void pci_bus_remove_resources(struct pci_bus
*bus
);
1218 int devm_request_pci_bus_resources(struct device
*dev
,
1219 struct list_head
*resources
);
1221 #define pci_bus_for_each_resource(bus, res, i) \
1223 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1226 int __must_check
pci_bus_alloc_resource(struct pci_bus
*bus
,
1227 struct resource
*res
, resource_size_t size
,
1228 resource_size_t align
, resource_size_t min
,
1229 unsigned long type_mask
,
1230 resource_size_t (*alignf
)(void *,
1231 const struct resource
*,
1237 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
1238 resource_size_t size
);
1239 unsigned long pci_address_to_pio(phys_addr_t addr
);
1240 phys_addr_t
pci_pio_to_address(unsigned long pio
);
1241 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
);
1242 void pci_unmap_iospace(struct resource
*res
);
1243 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
1244 resource_size_t offset
,
1245 resource_size_t size
);
1246 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
1247 struct resource
*res
);
1249 static inline pci_bus_addr_t
pci_bus_address(struct pci_dev
*pdev
, int bar
)
1251 struct pci_bus_region region
;
1253 pcibios_resource_to_bus(pdev
->bus
, ®ion
, &pdev
->resource
[bar
]);
1254 return region
.start
;
1257 /* Proper probing supporting hot-pluggable devices */
1258 int __must_check
__pci_register_driver(struct pci_driver
*, struct module
*,
1259 const char *mod_name
);
1262 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1264 #define pci_register_driver(driver) \
1265 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1267 void pci_unregister_driver(struct pci_driver
*dev
);
1270 * module_pci_driver() - Helper macro for registering a PCI driver
1271 * @__pci_driver: pci_driver struct
1273 * Helper macro for PCI drivers which do not do anything special in module
1274 * init/exit. This eliminates a lot of boilerplate. Each module may only
1275 * use this macro once, and calling it replaces module_init() and module_exit()
1277 #define module_pci_driver(__pci_driver) \
1278 module_driver(__pci_driver, pci_register_driver, \
1279 pci_unregister_driver)
1282 * builtin_pci_driver() - Helper macro for registering a PCI driver
1283 * @__pci_driver: pci_driver struct
1285 * Helper macro for PCI drivers which do not do anything special in their
1286 * init code. This eliminates a lot of boilerplate. Each driver may only
1287 * use this macro once, and calling it replaces device_initcall(...)
1289 #define builtin_pci_driver(__pci_driver) \
1290 builtin_driver(__pci_driver, pci_register_driver)
1292 struct pci_driver
*pci_dev_driver(const struct pci_dev
*dev
);
1293 int pci_add_dynid(struct pci_driver
*drv
,
1294 unsigned int vendor
, unsigned int device
,
1295 unsigned int subvendor
, unsigned int subdevice
,
1296 unsigned int class, unsigned int class_mask
,
1297 unsigned long driver_data
);
1298 const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1299 struct pci_dev
*dev
);
1300 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
,
1303 void pci_walk_bus(struct pci_bus
*top
, int (*cb
)(struct pci_dev
*, void *),
1305 int pci_cfg_space_size(struct pci_dev
*dev
);
1306 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
);
1307 void pci_setup_bridge(struct pci_bus
*bus
);
1308 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
1309 unsigned long type
);
1310 resource_size_t
pcibios_iov_resource_alignment(struct pci_dev
*dev
, int resno
);
1312 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1313 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1315 int pci_set_vga_state(struct pci_dev
*pdev
, bool decode
,
1316 unsigned int command_bits
, u32 flags
);
1318 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1319 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1320 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1321 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1322 #define PCI_IRQ_ALL_TYPES \
1323 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1325 /* kmem_cache style wrapper around pci_alloc_consistent() */
1327 #include <linux/pci-dma.h>
1328 #include <linux/dmapool.h>
1330 #define pci_pool dma_pool
1331 #define pci_pool_create(name, pdev, size, align, allocation) \
1332 dma_pool_create(name, &pdev->dev, size, align, allocation)
1333 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1334 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1335 #define pci_pool_zalloc(pool, flags, handle) \
1336 dma_pool_zalloc(pool, flags, handle)
1337 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1340 u32 vector
; /* kernel uses to write allocated vector */
1341 u16 entry
; /* driver uses to specify entry, OS writes */
1344 #ifdef CONFIG_PCI_MSI
1345 int pci_msi_vec_count(struct pci_dev
*dev
);
1346 void pci_disable_msi(struct pci_dev
*dev
);
1347 int pci_msix_vec_count(struct pci_dev
*dev
);
1348 void pci_disable_msix(struct pci_dev
*dev
);
1349 void pci_restore_msi_state(struct pci_dev
*dev
);
1350 int pci_msi_enabled(void);
1351 int pci_enable_msi(struct pci_dev
*dev
);
1352 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1353 int minvec
, int maxvec
);
1354 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1355 struct msix_entry
*entries
, int nvec
)
1357 int rc
= pci_enable_msix_range(dev
, entries
, nvec
, nvec
);
1362 int pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1363 unsigned int max_vecs
, unsigned int flags
,
1364 const struct irq_affinity
*affd
);
1366 void pci_free_irq_vectors(struct pci_dev
*dev
);
1367 int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
);
1368 const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*pdev
, int vec
);
1369 int pci_irq_get_node(struct pci_dev
*pdev
, int vec
);
1372 static inline int pci_msi_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1373 static inline void pci_disable_msi(struct pci_dev
*dev
) { }
1374 static inline int pci_msix_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1375 static inline void pci_disable_msix(struct pci_dev
*dev
) { }
1376 static inline void pci_restore_msi_state(struct pci_dev
*dev
) { }
1377 static inline int pci_msi_enabled(void) { return 0; }
1378 static inline int pci_enable_msi(struct pci_dev
*dev
)
1380 static inline int pci_enable_msix_range(struct pci_dev
*dev
,
1381 struct msix_entry
*entries
, int minvec
, int maxvec
)
1383 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1384 struct msix_entry
*entries
, int nvec
)
1388 pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1389 unsigned int max_vecs
, unsigned int flags
,
1390 const struct irq_affinity
*aff_desc
)
1392 if ((flags
& PCI_IRQ_LEGACY
) && min_vecs
== 1 && dev
->irq
)
1397 static inline void pci_free_irq_vectors(struct pci_dev
*dev
)
1401 static inline int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
)
1403 if (WARN_ON_ONCE(nr
> 0))
1407 static inline const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*pdev
,
1410 return cpu_possible_mask
;
1413 static inline int pci_irq_get_node(struct pci_dev
*pdev
, int vec
)
1415 return first_online_node
;
1420 pci_alloc_irq_vectors(struct pci_dev
*dev
, unsigned int min_vecs
,
1421 unsigned int max_vecs
, unsigned int flags
)
1423 return pci_alloc_irq_vectors_affinity(dev
, min_vecs
, max_vecs
, flags
,
1428 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1429 * @d: the INTx IRQ domain
1430 * @node: the DT node for the device whose interrupt we're translating
1431 * @intspec: the interrupt specifier data from the DT
1432 * @intsize: the number of entries in @intspec
1433 * @out_hwirq: pointer at which to write the hwirq number
1434 * @out_type: pointer at which to write the interrupt type
1436 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1437 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1438 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1439 * INTx value to obtain the hwirq number.
1441 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1443 static inline int pci_irqd_intx_xlate(struct irq_domain
*d
,
1444 struct device_node
*node
,
1446 unsigned int intsize
,
1447 unsigned long *out_hwirq
,
1448 unsigned int *out_type
)
1450 const u32 intx
= intspec
[0];
1452 if (intx
< PCI_INTERRUPT_INTA
|| intx
> PCI_INTERRUPT_INTD
)
1455 *out_hwirq
= intx
- PCI_INTERRUPT_INTA
;
1459 #ifdef CONFIG_PCIEPORTBUS
1460 extern bool pcie_ports_disabled
;
1461 extern bool pcie_ports_auto
;
1463 #define pcie_ports_disabled true
1464 #define pcie_ports_auto false
1467 #ifdef CONFIG_PCIEASPM
1468 bool pcie_aspm_support_enabled(void);
1470 static inline bool pcie_aspm_support_enabled(void) { return false; }
1473 #ifdef CONFIG_PCIEAER
1474 void pci_no_aer(void);
1475 bool pci_aer_available(void);
1476 int pci_aer_init(struct pci_dev
*dev
);
1478 static inline void pci_no_aer(void) { }
1479 static inline bool pci_aer_available(void) { return false; }
1480 static inline int pci_aer_init(struct pci_dev
*d
) { return -ENODEV
; }
1483 #ifdef CONFIG_PCIE_ECRC
1484 void pcie_set_ecrc_checking(struct pci_dev
*dev
);
1485 void pcie_ecrc_get_policy(char *str
);
1487 static inline void pcie_set_ecrc_checking(struct pci_dev
*dev
) { }
1488 static inline void pcie_ecrc_get_policy(char *str
) { }
1491 #ifdef CONFIG_PCI_ATS
1492 /* Address Translation Service */
1493 void pci_ats_init(struct pci_dev
*dev
);
1494 int pci_enable_ats(struct pci_dev
*dev
, int ps
);
1495 void pci_disable_ats(struct pci_dev
*dev
);
1496 int pci_ats_queue_depth(struct pci_dev
*dev
);
1498 static inline void pci_ats_init(struct pci_dev
*d
) { }
1499 static inline int pci_enable_ats(struct pci_dev
*d
, int ps
) { return -ENODEV
; }
1500 static inline void pci_disable_ats(struct pci_dev
*d
) { }
1501 static inline int pci_ats_queue_depth(struct pci_dev
*d
) { return -ENODEV
; }
1504 #ifdef CONFIG_PCIE_PTM
1505 int pci_enable_ptm(struct pci_dev
*dev
, u8
*granularity
);
1507 static inline int pci_enable_ptm(struct pci_dev
*dev
, u8
*granularity
)
1511 void pci_cfg_access_lock(struct pci_dev
*dev
);
1512 bool pci_cfg_access_trylock(struct pci_dev
*dev
);
1513 void pci_cfg_access_unlock(struct pci_dev
*dev
);
1516 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1517 * a PCI domain is defined to be a set of PCI buses which share
1518 * configuration space.
1520 #ifdef CONFIG_PCI_DOMAINS
1521 extern int pci_domains_supported
;
1522 int pci_get_new_domain_nr(void);
1524 enum { pci_domains_supported
= 0 };
1525 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1526 static inline int pci_proc_domain(struct pci_bus
*bus
) { return 0; }
1527 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1528 #endif /* CONFIG_PCI_DOMAINS */
1531 * Generic implementation for PCI domain support. If your
1532 * architecture does not need custom management of PCI
1533 * domains then this implementation will be used
1535 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1536 static inline int pci_domain_nr(struct pci_bus
*bus
)
1538 return bus
->domain_nr
;
1541 int acpi_pci_bus_find_domain_nr(struct pci_bus
*bus
);
1543 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus
*bus
)
1546 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
);
1549 /* some architectures require additional setup to direct VGA traffic */
1550 typedef int (*arch_set_vga_state_t
)(struct pci_dev
*pdev
, bool decode
,
1551 unsigned int command_bits
, u32 flags
);
1552 void pci_register_set_vga_state(arch_set_vga_state_t func
);
1555 pci_request_io_regions(struct pci_dev
*pdev
, const char *name
)
1557 return pci_request_selected_regions(pdev
,
1558 pci_select_bars(pdev
, IORESOURCE_IO
), name
);
1562 pci_release_io_regions(struct pci_dev
*pdev
)
1564 return pci_release_selected_regions(pdev
,
1565 pci_select_bars(pdev
, IORESOURCE_IO
));
1569 pci_request_mem_regions(struct pci_dev
*pdev
, const char *name
)
1571 return pci_request_selected_regions(pdev
,
1572 pci_select_bars(pdev
, IORESOURCE_MEM
), name
);
1576 pci_release_mem_regions(struct pci_dev
*pdev
)
1578 return pci_release_selected_regions(pdev
,
1579 pci_select_bars(pdev
, IORESOURCE_MEM
));
1582 #else /* CONFIG_PCI is not enabled */
1584 static inline void pci_set_flags(int flags
) { }
1585 static inline void pci_add_flags(int flags
) { }
1586 static inline void pci_clear_flags(int flags
) { }
1587 static inline int pci_has_flag(int flag
) { return 0; }
1590 * If the system does not have PCI, clearly these return errors. Define
1591 * these as simple inline functions to avoid hair in drivers.
1594 #define _PCI_NOP(o, s, t) \
1595 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1597 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1599 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1600 _PCI_NOP(o, word, u16 x) \
1601 _PCI_NOP(o, dword, u32 x)
1602 _PCI_NOP_ALL(read
, *)
1603 _PCI_NOP_ALL(write
,)
1605 static inline struct pci_dev
*pci_get_device(unsigned int vendor
,
1606 unsigned int device
,
1607 struct pci_dev
*from
)
1610 static inline struct pci_dev
*pci_get_subsys(unsigned int vendor
,
1611 unsigned int device
,
1612 unsigned int ss_vendor
,
1613 unsigned int ss_device
,
1614 struct pci_dev
*from
)
1617 static inline struct pci_dev
*pci_get_class(unsigned int class,
1618 struct pci_dev
*from
)
1621 #define pci_dev_present(ids) (0)
1622 #define no_pci_devices() (1)
1623 #define pci_dev_put(dev) do { } while (0)
1625 static inline void pci_set_master(struct pci_dev
*dev
) { }
1626 static inline int pci_enable_device(struct pci_dev
*dev
) { return -EIO
; }
1627 static inline void pci_disable_device(struct pci_dev
*dev
) { }
1628 static inline int pci_assign_resource(struct pci_dev
*dev
, int i
)
1630 static inline int __pci_register_driver(struct pci_driver
*drv
,
1631 struct module
*owner
)
1633 static inline int pci_register_driver(struct pci_driver
*drv
)
1635 static inline void pci_unregister_driver(struct pci_driver
*drv
) { }
1636 static inline int pci_find_capability(struct pci_dev
*dev
, int cap
)
1638 static inline int pci_find_next_capability(struct pci_dev
*dev
, u8 post
,
1641 static inline int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
1644 /* Power management related routines */
1645 static inline int pci_save_state(struct pci_dev
*dev
) { return 0; }
1646 static inline void pci_restore_state(struct pci_dev
*dev
) { }
1647 static inline int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1649 static inline int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1651 static inline pci_power_t
pci_choose_state(struct pci_dev
*dev
,
1654 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1658 static inline struct resource
*pci_find_resource(struct pci_dev
*dev
,
1659 struct resource
*res
)
1661 static inline int pci_request_regions(struct pci_dev
*dev
, const char *res_name
)
1663 static inline void pci_release_regions(struct pci_dev
*dev
) { }
1665 static inline unsigned long pci_address_to_pio(phys_addr_t addr
) { return -1; }
1667 static inline void pci_block_cfg_access(struct pci_dev
*dev
) { }
1668 static inline int pci_block_cfg_access_in_atomic(struct pci_dev
*dev
)
1670 static inline void pci_unblock_cfg_access(struct pci_dev
*dev
) { }
1672 static inline struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
)
1674 static inline struct pci_dev
*pci_get_slot(struct pci_bus
*bus
,
1677 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
1680 static inline struct pci_dev
*pci_get_domain_bus_and_slot(int domain
,
1681 unsigned int bus
, unsigned int devfn
)
1684 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1685 static inline struct pci_dev
*pci_dev_get(struct pci_dev
*dev
) { return NULL
; }
1686 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1688 #define dev_is_pci(d) (false)
1689 #define dev_is_pf(d) (false)
1690 static inline bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
1692 #endif /* CONFIG_PCI */
1694 /* Include architecture-dependent settings and functions */
1696 #include <asm/pci.h>
1698 /* These two functions provide almost identical functionality. Depennding
1699 * on the architecture, one will be implemented as a wrapper around the
1700 * other (in drivers/pci/mmap.c).
1702 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1703 * is expected to be an offset within that region.
1705 * pci_mmap_page_range() is the legacy architecture-specific interface,
1706 * which accepts a "user visible" resource address converted by
1707 * pci_resource_to_user(), as used in the legacy mmap() interface in
1710 int pci_mmap_resource_range(struct pci_dev
*dev
, int bar
,
1711 struct vm_area_struct
*vma
,
1712 enum pci_mmap_state mmap_state
, int write_combine
);
1713 int pci_mmap_page_range(struct pci_dev
*pdev
, int bar
,
1714 struct vm_area_struct
*vma
,
1715 enum pci_mmap_state mmap_state
, int write_combine
);
1717 #ifndef arch_can_pci_mmap_wc
1718 #define arch_can_pci_mmap_wc() 0
1721 #ifndef arch_can_pci_mmap_io
1722 #define arch_can_pci_mmap_io() 0
1723 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1725 int pci_iobar_pfn(struct pci_dev
*pdev
, int bar
, struct vm_area_struct
*vma
);
1728 #ifndef pci_root_bus_fwnode
1729 #define pci_root_bus_fwnode(bus) NULL
1732 /* these helpers provide future and backwards compatibility
1733 * for accessing popular PCI BAR info */
1734 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1735 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1736 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1737 #define pci_resource_len(dev,bar) \
1738 ((pci_resource_start((dev), (bar)) == 0 && \
1739 pci_resource_end((dev), (bar)) == \
1740 pci_resource_start((dev), (bar))) ? 0 : \
1742 (pci_resource_end((dev), (bar)) - \
1743 pci_resource_start((dev), (bar)) + 1))
1745 /* Similar to the helpers above, these manipulate per-pci_dev
1746 * driver-specific data. They are really just a wrapper around
1747 * the generic device structure functions of these calls.
1749 static inline void *pci_get_drvdata(struct pci_dev
*pdev
)
1751 return dev_get_drvdata(&pdev
->dev
);
1754 static inline void pci_set_drvdata(struct pci_dev
*pdev
, void *data
)
1756 dev_set_drvdata(&pdev
->dev
, data
);
1759 /* If you want to know what to call your pci_dev, ask this function.
1760 * Again, it's a wrapper around the generic device.
1762 static inline const char *pci_name(const struct pci_dev
*pdev
)
1764 return dev_name(&pdev
->dev
);
1768 /* Some archs don't want to expose struct resource to userland as-is
1769 * in sysfs and /proc
1771 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1772 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1773 const struct resource
*rsrc
,
1774 resource_size_t
*start
, resource_size_t
*end
);
1776 static inline void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1777 const struct resource
*rsrc
, resource_size_t
*start
,
1778 resource_size_t
*end
)
1780 *start
= rsrc
->start
;
1783 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1787 * The world is not perfect and supplies us with broken PCI devices.
1788 * For at least a part of these bugs we need a work-around, so both
1789 * generic (drivers/pci/quirks.c) and per-architecture code can define
1790 * fixup hooks to be called for particular buggy devices.
1794 u16 vendor
; /* You can use PCI_ANY_ID here of course */
1795 u16 device
; /* You can use PCI_ANY_ID here of course */
1796 u32
class; /* You can use PCI_ANY_ID here too */
1797 unsigned int class_shift
; /* should be 0, 8, 16 */
1798 void (*hook
)(struct pci_dev
*dev
);
1801 enum pci_fixup_pass
{
1802 pci_fixup_early
, /* Before probing BARs */
1803 pci_fixup_header
, /* After reading configuration header */
1804 pci_fixup_final
, /* Final phase of device fixups */
1805 pci_fixup_enable
, /* pci_enable_device() time */
1806 pci_fixup_resume
, /* pci_device_resume() */
1807 pci_fixup_suspend
, /* pci_device_suspend() */
1808 pci_fixup_resume_early
, /* pci_device_resume_early() */
1809 pci_fixup_suspend_late
, /* pci_device_suspend_late() */
1812 /* Anonymous variables would be nice... */
1813 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1814 class_shift, hook) \
1815 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1816 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1817 = { vendor, device, class, class_shift, hook };
1819 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1820 class_shift, hook) \
1821 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1822 hook, vendor, device, class, class_shift, hook)
1823 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1824 class_shift, hook) \
1825 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1826 hook, vendor, device, class, class_shift, hook)
1827 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1828 class_shift, hook) \
1829 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1830 hook, vendor, device, class, class_shift, hook)
1831 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1832 class_shift, hook) \
1833 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1834 hook, vendor, device, class, class_shift, hook)
1835 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1836 class_shift, hook) \
1837 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1838 resume##hook, vendor, device, class, \
1840 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1841 class_shift, hook) \
1842 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1843 resume_early##hook, vendor, device, \
1844 class, class_shift, hook)
1845 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1846 class_shift, hook) \
1847 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1848 suspend##hook, vendor, device, class, \
1850 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1851 class_shift, hook) \
1852 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1853 suspend_late##hook, vendor, device, \
1854 class, class_shift, hook)
1856 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1857 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1858 hook, vendor, device, PCI_ANY_ID, 0, hook)
1859 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1860 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1861 hook, vendor, device, PCI_ANY_ID, 0, hook)
1862 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1864 hook, vendor, device, PCI_ANY_ID, 0, hook)
1865 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1866 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1867 hook, vendor, device, PCI_ANY_ID, 0, hook)
1868 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1869 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1870 resume##hook, vendor, device, \
1871 PCI_ANY_ID, 0, hook)
1872 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1873 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1874 resume_early##hook, vendor, device, \
1875 PCI_ANY_ID, 0, hook)
1876 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1877 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1878 suspend##hook, vendor, device, \
1879 PCI_ANY_ID, 0, hook)
1880 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1881 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1882 suspend_late##hook, vendor, device, \
1883 PCI_ANY_ID, 0, hook)
1885 #ifdef CONFIG_PCI_QUIRKS
1886 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
);
1887 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
);
1888 int pci_dev_specific_enable_acs(struct pci_dev
*dev
);
1890 static inline void pci_fixup_device(enum pci_fixup_pass pass
,
1891 struct pci_dev
*dev
) { }
1892 static inline int pci_dev_specific_acs_enabled(struct pci_dev
*dev
,
1897 static inline int pci_dev_specific_enable_acs(struct pci_dev
*dev
)
1903 void __iomem
*pcim_iomap(struct pci_dev
*pdev
, int bar
, unsigned long maxlen
);
1904 void pcim_iounmap(struct pci_dev
*pdev
, void __iomem
*addr
);
1905 void __iomem
* const *pcim_iomap_table(struct pci_dev
*pdev
);
1906 int pcim_iomap_regions(struct pci_dev
*pdev
, int mask
, const char *name
);
1907 int pcim_iomap_regions_request_all(struct pci_dev
*pdev
, int mask
,
1909 void pcim_iounmap_regions(struct pci_dev
*pdev
, int mask
);
1911 extern int pci_pci_problems
;
1912 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1913 #define PCIPCI_TRITON 2
1914 #define PCIPCI_NATOMA 4
1915 #define PCIPCI_VIAETBF 8
1916 #define PCIPCI_VSFX 16
1917 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1918 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1920 extern unsigned long pci_cardbus_io_size
;
1921 extern unsigned long pci_cardbus_mem_size
;
1922 extern u8 pci_dfl_cache_line_size
;
1923 extern u8 pci_cache_line_size
;
1925 extern unsigned long pci_hotplug_io_size
;
1926 extern unsigned long pci_hotplug_mem_size
;
1927 extern unsigned long pci_hotplug_bus_size
;
1929 /* Architecture-specific versions may override these (weak) */
1930 void pcibios_disable_device(struct pci_dev
*dev
);
1931 void pcibios_set_master(struct pci_dev
*dev
);
1932 int pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1933 enum pcie_reset_state state
);
1934 int pcibios_add_device(struct pci_dev
*dev
);
1935 void pcibios_release_device(struct pci_dev
*dev
);
1936 void pcibios_penalize_isa_irq(int irq
, int active
);
1937 int pcibios_alloc_irq(struct pci_dev
*dev
);
1938 void pcibios_free_irq(struct pci_dev
*dev
);
1940 #ifdef CONFIG_HIBERNATE_CALLBACKS
1941 extern struct dev_pm_ops pcibios_pm_ops
;
1944 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1945 void __init
pci_mmcfg_early_init(void);
1946 void __init
pci_mmcfg_late_init(void);
1948 static inline void pci_mmcfg_early_init(void) { }
1949 static inline void pci_mmcfg_late_init(void) { }
1952 int pci_ext_cfg_avail(void);
1954 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
);
1955 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
);
1957 #ifdef CONFIG_PCI_IOV
1958 int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
);
1959 int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
);
1961 int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
);
1962 void pci_disable_sriov(struct pci_dev
*dev
);
1963 int pci_iov_add_virtfn(struct pci_dev
*dev
, int id
);
1964 void pci_iov_remove_virtfn(struct pci_dev
*dev
, int id
);
1965 int pci_num_vf(struct pci_dev
*dev
);
1966 int pci_vfs_assigned(struct pci_dev
*dev
);
1967 int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
);
1968 int pci_sriov_get_totalvfs(struct pci_dev
*dev
);
1969 resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
);
1971 static inline int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
)
1975 static inline int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
)
1979 static inline int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
)
1981 static inline int pci_iov_add_virtfn(struct pci_dev
*dev
, int id
)
1985 static inline void pci_iov_remove_virtfn(struct pci_dev
*dev
,
1987 static inline void pci_disable_sriov(struct pci_dev
*dev
) { }
1988 static inline int pci_num_vf(struct pci_dev
*dev
) { return 0; }
1989 static inline int pci_vfs_assigned(struct pci_dev
*dev
)
1991 static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
)
1993 static inline int pci_sriov_get_totalvfs(struct pci_dev
*dev
)
1995 static inline resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
)
1999 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2000 void pci_hp_create_module_link(struct pci_slot
*pci_slot
);
2001 void pci_hp_remove_module_link(struct pci_slot
*pci_slot
);
2005 * pci_pcie_cap - get the saved PCIe capability offset
2008 * PCIe capability offset is calculated at PCI device initialization
2009 * time and saved in the data structure. This function returns saved
2010 * PCIe capability offset. Using this instead of pci_find_capability()
2011 * reduces unnecessary search in the PCI configuration space. If you
2012 * need to calculate PCIe capability offset from raw device for some
2013 * reasons, please use pci_find_capability() instead.
2015 static inline int pci_pcie_cap(struct pci_dev
*dev
)
2017 return dev
->pcie_cap
;
2021 * pci_is_pcie - check if the PCI device is PCI Express capable
2024 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2026 static inline bool pci_is_pcie(struct pci_dev
*dev
)
2028 return pci_pcie_cap(dev
);
2032 * pcie_caps_reg - get the PCIe Capabilities Register
2035 static inline u16
pcie_caps_reg(const struct pci_dev
*dev
)
2037 return dev
->pcie_flags_reg
;
2041 * pci_pcie_type - get the PCIe device/port type
2044 static inline int pci_pcie_type(const struct pci_dev
*dev
)
2046 return (pcie_caps_reg(dev
) & PCI_EXP_FLAGS_TYPE
) >> 4;
2049 static inline struct pci_dev
*pcie_find_root_port(struct pci_dev
*dev
)
2052 if (!pci_is_pcie(dev
))
2054 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2056 if (!dev
->bus
->self
)
2058 dev
= dev
->bus
->self
;
2063 void pci_request_acs(void);
2064 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
);
2065 bool pci_acs_path_enabled(struct pci_dev
*start
,
2066 struct pci_dev
*end
, u16 acs_flags
);
2068 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2069 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2071 /* Large Resource Data Type Tag Item Names */
2072 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2073 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2074 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2076 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2077 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2078 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2080 /* Small Resource Data Type Tag Item Names */
2081 #define PCI_VPD_STIN_END 0x0f /* End */
2083 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2085 #define PCI_VPD_SRDT_TIN_MASK 0x78
2086 #define PCI_VPD_SRDT_LEN_MASK 0x07
2087 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2089 #define PCI_VPD_LRDT_TAG_SIZE 3
2090 #define PCI_VPD_SRDT_TAG_SIZE 1
2092 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2094 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2095 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2096 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2097 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2100 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2101 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2103 * Returns the extracted Large Resource Data Type length.
2105 static inline u16
pci_vpd_lrdt_size(const u8
*lrdt
)
2107 return (u16
)lrdt
[1] + ((u16
)lrdt
[2] << 8);
2111 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2112 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2114 * Returns the extracted Large Resource Data Type Tag item.
2116 static inline u16
pci_vpd_lrdt_tag(const u8
*lrdt
)
2118 return (u16
)(lrdt
[0] & PCI_VPD_LRDT_TIN_MASK
);
2122 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2123 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2125 * Returns the extracted Small Resource Data Type length.
2127 static inline u8
pci_vpd_srdt_size(const u8
*srdt
)
2129 return (*srdt
) & PCI_VPD_SRDT_LEN_MASK
;
2133 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2134 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2136 * Returns the extracted Small Resource Data Type Tag Item.
2138 static inline u8
pci_vpd_srdt_tag(const u8
*srdt
)
2140 return ((*srdt
) & PCI_VPD_SRDT_TIN_MASK
) >> 3;
2144 * pci_vpd_info_field_size - Extracts the information field length
2145 * @lrdt: Pointer to the beginning of an information field header
2147 * Returns the extracted information field length.
2149 static inline u8
pci_vpd_info_field_size(const u8
*info_field
)
2151 return info_field
[2];
2155 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2156 * @buf: Pointer to buffered vpd data
2157 * @off: The offset into the buffer at which to begin the search
2158 * @len: The length of the vpd buffer
2159 * @rdt: The Resource Data Type to search for
2161 * Returns the index where the Resource Data Type was found or
2162 * -ENOENT otherwise.
2164 int pci_vpd_find_tag(const u8
*buf
, unsigned int off
, unsigned int len
, u8 rdt
);
2167 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2168 * @buf: Pointer to buffered vpd data
2169 * @off: The offset into the buffer at which to begin the search
2170 * @len: The length of the buffer area, relative to off, in which to search
2171 * @kw: The keyword to search for
2173 * Returns the index where the information field keyword was found or
2174 * -ENOENT otherwise.
2176 int pci_vpd_find_info_keyword(const u8
*buf
, unsigned int off
,
2177 unsigned int len
, const char *kw
);
2179 /* PCI <-> OF binding helpers */
2183 void pci_set_of_node(struct pci_dev
*dev
);
2184 void pci_release_of_node(struct pci_dev
*dev
);
2185 void pci_set_bus_of_node(struct pci_bus
*bus
);
2186 void pci_release_bus_of_node(struct pci_bus
*bus
);
2187 struct irq_domain
*pci_host_bridge_of_msi_domain(struct pci_bus
*bus
);
2189 /* Arch may override this (weak) */
2190 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
);
2192 static inline struct device_node
*
2193 pci_device_to_OF_node(const struct pci_dev
*pdev
)
2195 return pdev
? pdev
->dev
.of_node
: NULL
;
2198 static inline struct device_node
*pci_bus_to_OF_node(struct pci_bus
*bus
)
2200 return bus
? bus
->dev
.of_node
: NULL
;
2203 #else /* CONFIG_OF */
2204 static inline void pci_set_of_node(struct pci_dev
*dev
) { }
2205 static inline void pci_release_of_node(struct pci_dev
*dev
) { }
2206 static inline void pci_set_bus_of_node(struct pci_bus
*bus
) { }
2207 static inline void pci_release_bus_of_node(struct pci_bus
*bus
) { }
2208 static inline struct device_node
*
2209 pci_device_to_OF_node(const struct pci_dev
*pdev
) { return NULL
; }
2210 static inline struct irq_domain
*
2211 pci_host_bridge_of_msi_domain(struct pci_bus
*bus
) { return NULL
; }
2212 #endif /* CONFIG_OF */
2215 struct irq_domain
*pci_host_bridge_acpi_msi_domain(struct pci_bus
*bus
);
2218 pci_msi_register_fwnode_provider(struct fwnode_handle
*(*fn
)(struct device
*));
2220 static inline struct irq_domain
*
2221 pci_host_bridge_acpi_msi_domain(struct pci_bus
*bus
) { return NULL
; }
2225 static inline struct eeh_dev
*pci_dev_to_eeh_dev(struct pci_dev
*pdev
)
2227 return pdev
->dev
.archdata
.edev
;
2231 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn
);
2232 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
);
2233 int pci_for_each_dma_alias(struct pci_dev
*pdev
,
2234 int (*fn
)(struct pci_dev
*pdev
,
2235 u16 alias
, void *data
), void *data
);
2237 /* helper functions for operation of device flag */
2238 static inline void pci_set_dev_assigned(struct pci_dev
*pdev
)
2240 pdev
->dev_flags
|= PCI_DEV_FLAGS_ASSIGNED
;
2242 static inline void pci_clear_dev_assigned(struct pci_dev
*pdev
)
2244 pdev
->dev_flags
&= ~PCI_DEV_FLAGS_ASSIGNED
;
2246 static inline bool pci_is_dev_assigned(struct pci_dev
*pdev
)
2248 return (pdev
->dev_flags
& PCI_DEV_FLAGS_ASSIGNED
) == PCI_DEV_FLAGS_ASSIGNED
;
2252 * pci_ari_enabled - query ARI forwarding status
2255 * Returns true if ARI forwarding is enabled.
2257 static inline bool pci_ari_enabled(struct pci_bus
*bus
)
2259 return bus
->self
&& bus
->self
->ari_enabled
;
2263 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2264 * @pdev: PCI device to check
2266 * Walk upwards from @pdev and check for each encountered bridge if it's part
2267 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2268 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2270 static inline bool pci_is_thunderbolt_attached(struct pci_dev
*pdev
)
2272 struct pci_dev
*parent
= pdev
;
2274 if (pdev
->is_thunderbolt
)
2277 while ((parent
= pci_upstream_bridge(parent
)))
2278 if (parent
->is_thunderbolt
)
2284 /* provide the legacy pci_dma_* API */
2285 #include <linux/pci-dma-compat.h>
2287 #endif /* LINUX_PCI_H */