1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus
*bus
; /* Bus this slot is on */
58 struct list_head list
; /* Node in list of slots */
59 struct hotplug_slot
*hotplug
; /* Hotplug info (move here) */
60 unsigned char number
; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot
*slot
)
66 return kobject_name(&slot
->kobj
);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 /* For PCI devices, the region numbers are assigned this way: */
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END
= 5,
81 /* #6: expansion ROM resource */
84 /* Device-specific resources */
87 PCI_IOV_RESOURCE_END
= PCI_IOV_RESOURCES
+ PCI_SRIOV_NUM_BARS
- 1,
90 /* Resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END
= PCI_BRIDGE_RESOURCES
+
95 PCI_BRIDGE_RESOURCE_NUM
- 1,
97 /* Total resources associated with a PCI device */
100 /* Preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE
= PCI_NUM_RESOURCES
,
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
115 enum pci_interrupt_pin
{
116 PCI_INTERRUPT_UNKNOWN
,
123 /* The number of legacy PCI INTx interrupts */
124 #define PCI_NUM_INTX 4
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
130 typedef int __bitwise pci_power_t
;
132 #define PCI_D0 ((pci_power_t __force) 0)
133 #define PCI_D1 ((pci_power_t __force) 1)
134 #define PCI_D2 ((pci_power_t __force) 2)
135 #define PCI_D3hot ((pci_power_t __force) 3)
136 #define PCI_D3cold ((pci_power_t __force) 4)
137 #define PCI_UNKNOWN ((pci_power_t __force) 5)
138 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
140 /* Remember to update this when the list above changes! */
141 extern const char *pci_power_names
[];
143 static inline const char *pci_power_name(pci_power_t state
)
145 return pci_power_names
[1 + (__force
int) state
];
148 #define PCI_PM_D2_DELAY 200
149 #define PCI_PM_D3_WAIT 10
150 #define PCI_PM_D3COLD_WAIT 100
151 #define PCI_PM_BUS_WAIT 50
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
158 typedef unsigned int __bitwise pci_channel_state_t
;
160 enum pci_channel_state
{
161 /* I/O channel is in normal state */
162 pci_channel_io_normal
= (__force pci_channel_state_t
) 1,
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen
= (__force pci_channel_state_t
) 2,
167 /* PCI card is dead */
168 pci_channel_io_perm_failure
= (__force pci_channel_state_t
) 3,
171 typedef unsigned int __bitwise pcie_reset_state_t
;
173 enum pcie_reset_state
{
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset
= (__force pcie_reset_state_t
) 1,
177 /* Use #PERST to reset PCIe device */
178 pcie_warm_reset
= (__force pcie_reset_state_t
) 2,
180 /* Use PCIe Hot Reset to reset device */
181 pcie_hot_reset
= (__force pcie_reset_state_t
) 3
184 typedef unsigned short __bitwise pci_dev_flags_t
;
186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
= (__force pci_dev_flags_t
) (1 << 0),
188 /* Device configuration is irrevocably lost if disabled into D3 */
189 PCI_DEV_FLAGS_NO_D3
= (__force pci_dev_flags_t
) (1 << 1),
190 /* Provide indication device is assigned by a Virtual Machine Manager */
191 PCI_DEV_FLAGS_ASSIGNED
= (__force pci_dev_flags_t
) (1 << 2),
192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
= (__force pci_dev_flags_t
) (1 << 3),
194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
= (__force pci_dev_flags_t
) (1 << 5),
196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET
= (__force pci_dev_flags_t
) (1 << 6),
198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET
= (__force pci_dev_flags_t
) (1 << 7),
200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0
= (__force pci_dev_flags_t
) (1 << 8),
202 /* A non-root bridge where translation occurs, stop alias search here */
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
= (__force pci_dev_flags_t
) (1 << 9),
204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET
= (__force pci_dev_flags_t
) (1 << 10),
206 /* Don't use Relaxed Ordering for TLPs directed at this device */
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING
= (__force pci_dev_flags_t
) (1 << 11),
210 enum pci_irq_reroute_variant
{
211 INTEL_IRQ_REROUTE_VARIANT
= 1,
212 MAX_IRQ_REROUTE_VARIANTS
= 3
215 typedef unsigned short __bitwise pci_bus_flags_t
;
217 PCI_BUS_FLAGS_NO_MSI
= (__force pci_bus_flags_t
) 1,
218 PCI_BUS_FLAGS_NO_MMRBC
= (__force pci_bus_flags_t
) 2,
219 PCI_BUS_FLAGS_NO_AERSID
= (__force pci_bus_flags_t
) 4,
220 PCI_BUS_FLAGS_NO_EXTCFG
= (__force pci_bus_flags_t
) 8,
223 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
224 enum pcie_link_width
{
225 PCIE_LNK_WIDTH_RESRV
= 0x00,
233 PCIE_LNK_WIDTH_UNKNOWN
= 0xff,
236 /* Based on the PCI Hotplug Spec, but some values are made up by us */
238 PCI_SPEED_33MHz
= 0x00,
239 PCI_SPEED_66MHz
= 0x01,
240 PCI_SPEED_66MHz_PCIX
= 0x02,
241 PCI_SPEED_100MHz_PCIX
= 0x03,
242 PCI_SPEED_133MHz_PCIX
= 0x04,
243 PCI_SPEED_66MHz_PCIX_ECC
= 0x05,
244 PCI_SPEED_100MHz_PCIX_ECC
= 0x06,
245 PCI_SPEED_133MHz_PCIX_ECC
= 0x07,
246 PCI_SPEED_66MHz_PCIX_266
= 0x09,
247 PCI_SPEED_100MHz_PCIX_266
= 0x0a,
248 PCI_SPEED_133MHz_PCIX_266
= 0x0b,
254 PCI_SPEED_66MHz_PCIX_533
= 0x11,
255 PCI_SPEED_100MHz_PCIX_533
= 0x12,
256 PCI_SPEED_133MHz_PCIX_533
= 0x13,
257 PCIE_SPEED_2_5GT
= 0x14,
258 PCIE_SPEED_5_0GT
= 0x15,
259 PCIE_SPEED_8_0GT
= 0x16,
260 PCIE_SPEED_16_0GT
= 0x17,
261 PCI_SPEED_UNKNOWN
= 0xff,
264 enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev
*dev
);
265 enum pcie_link_width
pcie_get_width_cap(struct pci_dev
*dev
);
267 struct pci_cap_saved_data
{
274 struct pci_cap_saved_state
{
275 struct hlist_node next
;
276 struct pci_cap_saved_data cap
;
280 struct pcie_link_state
;
286 /* The pci_dev structure describes PCI devices */
288 struct list_head bus_list
; /* Node in per-bus list */
289 struct pci_bus
*bus
; /* Bus this device is on */
290 struct pci_bus
*subordinate
; /* Bus this device bridges to */
292 void *sysdata
; /* Hook for sys-specific extension */
293 struct proc_dir_entry
*procent
; /* Device entry in /proc/bus/pci */
294 struct pci_slot
*slot
; /* Physical slot this device is in */
296 unsigned int devfn
; /* Encoded device & function index */
297 unsigned short vendor
;
298 unsigned short device
;
299 unsigned short subsystem_vendor
;
300 unsigned short subsystem_device
;
301 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
302 u8 revision
; /* PCI revision, low byte of class word */
303 u8 hdr_type
; /* PCI header type (`multi' flag masked out) */
304 #ifdef CONFIG_PCIEAER
305 u16 aer_cap
; /* AER capability offset */
306 struct aer_stats
*aer_stats
; /* AER stats for this device */
308 u8 pcie_cap
; /* PCIe capability offset */
309 u8 msi_cap
; /* MSI capability offset */
310 u8 msix_cap
; /* MSI-X capability offset */
311 u8 pcie_mpss
:3; /* PCIe Max Payload Size Supported */
312 u8 rom_base_reg
; /* Config register controlling ROM */
313 u8 pin
; /* Interrupt pin this device uses */
314 u16 pcie_flags_reg
; /* Cached PCIe Capabilities Register */
315 unsigned long *dma_alias_mask
;/* Mask of enabled devfn aliases */
317 struct pci_driver
*driver
; /* Driver bound to this device */
318 u64 dma_mask
; /* Mask of the bits of bus address this
319 device implements. Normally this is
320 0xffffffff. You only need to change
321 this if your device has broken DMA
322 or supports 64-bit transfers. */
324 struct device_dma_parameters dma_parms
;
326 pci_power_t current_state
; /* Current operating state. In ACPI,
327 this is D0-D3, D0 being fully
328 functional, and D3 being off. */
329 unsigned int imm_ready
:1; /* Supports Immediate Readiness */
330 u8 pm_cap
; /* PM capability offset */
331 unsigned int pme_support
:5; /* Bitmask of states from which PME#
333 unsigned int pme_poll
:1; /* Poll device's PME status bit */
334 unsigned int d1_support
:1; /* Low power state D1 is supported */
335 unsigned int d2_support
:1; /* Low power state D2 is supported */
336 unsigned int no_d1d2
:1; /* D1 and D2 are forbidden */
337 unsigned int no_d3cold
:1; /* D3cold is forbidden */
338 unsigned int bridge_d3
:1; /* Allow D3 for bridge */
339 unsigned int d3cold_allowed
:1; /* D3cold is allowed by user */
340 unsigned int mmio_always_on
:1; /* Disallow turning off io/mem
341 decoding during BAR sizing */
342 unsigned int wakeup_prepared
:1;
343 unsigned int runtime_d3cold
:1; /* Whether go through runtime
344 D3cold, not set for devices
345 powered on/off by the
346 corresponding bridge */
347 unsigned int ignore_hotplug
:1; /* Ignore hotplug events */
348 unsigned int hotplug_user_indicators
:1; /* SlotCtl indicators
349 controlled exclusively by
351 unsigned int d3_delay
; /* D3->D0 transition time in ms */
352 unsigned int d3cold_delay
; /* D3cold->D0 transition time in ms */
354 #ifdef CONFIG_PCIEASPM
355 struct pcie_link_state
*link_state
; /* ASPM link state */
356 unsigned int ltr_path
:1; /* Latency Tolerance Reporting
357 supported from root to here */
359 unsigned int eetlp_prefix_path
:1; /* End-to-End TLP Prefix */
361 pci_channel_state_t error_state
; /* Current connectivity state */
362 struct device dev
; /* Generic device interface */
364 int cfg_size
; /* Size of config space */
367 * Instead of touching interrupt line and base address registers
368 * directly, use the values stored here. They might be different!
371 struct resource resource
[DEVICE_COUNT_RESOURCE
]; /* I/O and memory regions + expansion ROMs */
373 bool match_driver
; /* Skip attaching driver */
375 unsigned int transparent
:1; /* Subtractive decode bridge */
376 unsigned int multifunction
:1; /* Multi-function device */
378 unsigned int is_busmaster
:1; /* Is busmaster */
379 unsigned int no_msi
:1; /* May not use MSI */
380 unsigned int no_64bit_msi
:1; /* May only use 32-bit MSIs */
381 unsigned int block_cfg_access
:1; /* Config space access blocked */
382 unsigned int broken_parity_status
:1; /* Generates false positive parity */
383 unsigned int irq_reroute_variant
:2; /* Needs IRQ rerouting variant */
384 unsigned int msi_enabled
:1;
385 unsigned int msix_enabled
:1;
386 unsigned int ari_enabled
:1; /* ARI forwarding */
387 unsigned int ats_enabled
:1; /* Address Translation Svc */
388 unsigned int pasid_enabled
:1; /* Process Address Space ID */
389 unsigned int pri_enabled
:1; /* Page Request Interface */
390 unsigned int is_managed
:1;
391 unsigned int needs_freset
:1; /* Requires fundamental reset */
392 unsigned int state_saved
:1;
393 unsigned int is_physfn
:1;
394 unsigned int is_virtfn
:1;
395 unsigned int reset_fn
:1;
396 unsigned int is_hotplug_bridge
:1;
397 unsigned int shpc_managed
:1; /* SHPC owned by shpchp */
398 unsigned int is_thunderbolt
:1; /* Thunderbolt controller */
399 unsigned int __aer_firmware_first_valid
:1;
400 unsigned int __aer_firmware_first
:1;
401 unsigned int broken_intx_masking
:1; /* INTx masking can't be used */
402 unsigned int io_window_1k
:1; /* Intel bridge 1K I/O windows */
403 unsigned int irq_managed
:1;
404 unsigned int has_secondary_link
:1;
405 unsigned int non_compliant_bars
:1; /* Broken BARs; ignore them */
406 unsigned int is_probed
:1; /* Device probing in progress */
407 unsigned int link_active_reporting
:1;/* Device capable of reporting link active */
408 pci_dev_flags_t dev_flags
;
409 atomic_t enable_cnt
; /* pci_enable_device has been called */
411 u32 saved_config_space
[16]; /* Config space saved at suspend time */
412 struct hlist_head saved_cap_space
;
413 struct bin_attribute
*rom_attr
; /* Attribute descriptor for sysfs ROM entry */
414 int rom_attr_enabled
; /* Display of ROM attribute enabled? */
415 struct bin_attribute
*res_attr
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for resources */
416 struct bin_attribute
*res_attr_wc
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for WC mapping of resources */
418 #ifdef CONFIG_HOTPLUG_PCI_PCIE
419 unsigned int broken_cmd_compl
:1; /* No compl for some cmds */
421 #ifdef CONFIG_PCIE_PTM
422 unsigned int ptm_root
:1;
423 unsigned int ptm_enabled
:1;
426 #ifdef CONFIG_PCI_MSI
427 const struct attribute_group
**msi_irq_groups
;
430 #ifdef CONFIG_PCI_ATS
432 struct pci_sriov
*sriov
; /* PF: SR-IOV info */
433 struct pci_dev
*physfn
; /* VF: related PF */
435 u16 ats_cap
; /* ATS Capability offset */
436 u8 ats_stu
; /* ATS Smallest Translation Unit */
437 atomic_t ats_ref_cnt
; /* Number of VFs with ATS enabled */
439 #ifdef CONFIG_PCI_PRI
440 u32 pri_reqs_alloc
; /* Number of PRI requests allocated */
442 #ifdef CONFIG_PCI_PASID
445 #ifdef CONFIG_PCI_P2PDMA
446 struct pci_p2pdma
*p2pdma
;
448 phys_addr_t rom
; /* Physical address if not from BAR */
449 size_t romlen
; /* Length if not from BAR */
450 char *driver_override
; /* Driver name to force a match */
452 unsigned long priv_flags
; /* Private flags for the PCI driver */
455 static inline struct pci_dev
*pci_physfn(struct pci_dev
*dev
)
457 #ifdef CONFIG_PCI_IOV
464 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
);
466 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
467 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
469 static inline int pci_channel_offline(struct pci_dev
*pdev
)
471 return (pdev
->error_state
!= pci_channel_io_normal
);
474 struct pci_host_bridge
{
476 struct pci_bus
*bus
; /* Root bus */
480 struct list_head windows
; /* resource_entry */
481 u8 (*swizzle_irq
)(struct pci_dev
*, u8
*); /* Platform IRQ swizzler */
482 int (*map_irq
)(const struct pci_dev
*, u8
, u8
);
483 void (*release_fn
)(struct pci_host_bridge
*);
485 struct msi_controller
*msi
;
486 unsigned int ignore_reset_delay
:1; /* For entire hierarchy */
487 unsigned int no_ext_tags
:1; /* No Extended Tags */
488 unsigned int native_aer
:1; /* OS may use PCIe AER */
489 unsigned int native_pcie_hotplug
:1; /* OS may use PCIe hotplug */
490 unsigned int native_shpc_hotplug
:1; /* OS may use SHPC hotplug */
491 unsigned int native_pme
:1; /* OS may use PCIe PME */
492 unsigned int native_ltr
:1; /* OS may use PCIe LTR */
493 /* Resource alignment requirements */
494 resource_size_t (*align_resource
)(struct pci_dev
*dev
,
495 const struct resource
*res
,
496 resource_size_t start
,
497 resource_size_t size
,
498 resource_size_t align
);
499 unsigned long private[0] ____cacheline_aligned
;
502 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
504 static inline void *pci_host_bridge_priv(struct pci_host_bridge
*bridge
)
506 return (void *)bridge
->private;
509 static inline struct pci_host_bridge
*pci_host_bridge_from_priv(void *priv
)
511 return container_of(priv
, struct pci_host_bridge
, private);
514 struct pci_host_bridge
*pci_alloc_host_bridge(size_t priv
);
515 struct pci_host_bridge
*devm_pci_alloc_host_bridge(struct device
*dev
,
517 void pci_free_host_bridge(struct pci_host_bridge
*bridge
);
518 struct pci_host_bridge
*pci_find_host_bridge(struct pci_bus
*bus
);
520 void pci_set_host_bridge_release(struct pci_host_bridge
*bridge
,
521 void (*release_fn
)(struct pci_host_bridge
*),
524 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
);
527 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
528 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
529 * buses below host bridges or subtractive decode bridges) go in the list.
530 * Use pci_bus_for_each_resource() to iterate through all the resources.
534 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
535 * and there's no way to program the bridge with the details of the window.
536 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
537 * decode bit set, because they are explicit and can be programmed with _SRS.
539 #define PCI_SUBTRACTIVE_DECODE 0x1
541 struct pci_bus_resource
{
542 struct list_head list
;
543 struct resource
*res
;
547 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
550 struct list_head node
; /* Node in list of buses */
551 struct pci_bus
*parent
; /* Parent bus this bridge is on */
552 struct list_head children
; /* List of child buses */
553 struct list_head devices
; /* List of devices on this bus */
554 struct pci_dev
*self
; /* Bridge device as seen by parent */
555 struct list_head slots
; /* List of slots on this bus;
556 protected by pci_slot_mutex */
557 struct resource
*resource
[PCI_BRIDGE_RESOURCE_NUM
];
558 struct list_head resources
; /* Address space routed to this bus */
559 struct resource busn_res
; /* Bus numbers routed to this bus */
561 struct pci_ops
*ops
; /* Configuration access functions */
562 struct msi_controller
*msi
; /* MSI controller */
563 void *sysdata
; /* Hook for sys-specific extension */
564 struct proc_dir_entry
*procdir
; /* Directory entry in /proc/bus/pci */
566 unsigned char number
; /* Bus number */
567 unsigned char primary
; /* Number of primary bridge */
568 unsigned char max_bus_speed
; /* enum pci_bus_speed */
569 unsigned char cur_bus_speed
; /* enum pci_bus_speed */
570 #ifdef CONFIG_PCI_DOMAINS_GENERIC
576 unsigned short bridge_ctl
; /* Manage NO_ISA/FBB/et al behaviors */
577 pci_bus_flags_t bus_flags
; /* Inherited by child buses */
578 struct device
*bridge
;
580 struct bin_attribute
*legacy_io
; /* Legacy I/O for this bus */
581 struct bin_attribute
*legacy_mem
; /* Legacy mem */
582 unsigned int is_added
:1;
585 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
588 * Returns true if the PCI bus is root (behind host-PCI bridge),
591 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
592 * This is incorrect because "virtual" buses added for SR-IOV (via
593 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
595 static inline bool pci_is_root_bus(struct pci_bus
*pbus
)
597 return !(pbus
->parent
);
601 * pci_is_bridge - check if the PCI device is a bridge
604 * Return true if the PCI device is bridge whether it has subordinate
607 static inline bool pci_is_bridge(struct pci_dev
*dev
)
609 return dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
610 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
;
613 #define for_each_pci_bridge(dev, bus) \
614 list_for_each_entry(dev, &bus->devices, bus_list) \
615 if (!pci_is_bridge(dev)) {} else
617 static inline struct pci_dev
*pci_upstream_bridge(struct pci_dev
*dev
)
619 dev
= pci_physfn(dev
);
620 if (pci_is_root_bus(dev
->bus
))
623 return dev
->bus
->self
;
626 struct device
*pci_get_host_bridge_device(struct pci_dev
*dev
);
627 void pci_put_host_bridge_device(struct device
*dev
);
629 #ifdef CONFIG_PCI_MSI
630 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
)
632 return pci_dev
->msi_enabled
|| pci_dev
->msix_enabled
;
635 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
) { return false; }
638 /* Error values that may be returned by PCI functions */
639 #define PCIBIOS_SUCCESSFUL 0x00
640 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
641 #define PCIBIOS_BAD_VENDOR_ID 0x83
642 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
643 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
644 #define PCIBIOS_SET_FAILED 0x88
645 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
647 /* Translate above to generic errno for passing back through non-PCI code */
648 static inline int pcibios_err_to_errno(int err
)
650 if (err
<= PCIBIOS_SUCCESSFUL
)
651 return err
; /* Assume already errno */
654 case PCIBIOS_FUNC_NOT_SUPPORTED
:
656 case PCIBIOS_BAD_VENDOR_ID
:
658 case PCIBIOS_DEVICE_NOT_FOUND
:
660 case PCIBIOS_BAD_REGISTER_NUMBER
:
662 case PCIBIOS_SET_FAILED
:
664 case PCIBIOS_BUFFER_TOO_SMALL
:
671 /* Low-level architecture-dependent routines */
674 int (*add_bus
)(struct pci_bus
*bus
);
675 void (*remove_bus
)(struct pci_bus
*bus
);
676 void __iomem
*(*map_bus
)(struct pci_bus
*bus
, unsigned int devfn
, int where
);
677 int (*read
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
678 int (*write
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
682 * ACPI needs to be able to access PCI config space before we've done a
683 * PCI bus scan and created pci_bus structures.
685 int raw_pci_read(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
686 int reg
, int len
, u32
*val
);
687 int raw_pci_write(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
688 int reg
, int len
, u32 val
);
690 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
691 typedef u64 pci_bus_addr_t
;
693 typedef u32 pci_bus_addr_t
;
696 struct pci_bus_region
{
697 pci_bus_addr_t start
;
702 spinlock_t lock
; /* Protects list, index */
703 struct list_head list
; /* For IDs added at runtime */
708 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
709 * a set of callbacks in struct pci_error_handlers, that device driver
710 * will be notified of PCI bus errors, and will be driven to recovery
711 * when an error occurs.
714 typedef unsigned int __bitwise pci_ers_result_t
;
716 enum pci_ers_result
{
717 /* No result/none/not supported in device driver */
718 PCI_ERS_RESULT_NONE
= (__force pci_ers_result_t
) 1,
720 /* Device driver can recover without slot reset */
721 PCI_ERS_RESULT_CAN_RECOVER
= (__force pci_ers_result_t
) 2,
723 /* Device driver wants slot to be reset */
724 PCI_ERS_RESULT_NEED_RESET
= (__force pci_ers_result_t
) 3,
726 /* Device has completely failed, is unrecoverable */
727 PCI_ERS_RESULT_DISCONNECT
= (__force pci_ers_result_t
) 4,
729 /* Device driver is fully recovered and operational */
730 PCI_ERS_RESULT_RECOVERED
= (__force pci_ers_result_t
) 5,
732 /* No AER capabilities registered for the driver */
733 PCI_ERS_RESULT_NO_AER_DRIVER
= (__force pci_ers_result_t
) 6,
736 /* PCI bus error event callbacks */
737 struct pci_error_handlers
{
738 /* PCI bus error detected on this device */
739 pci_ers_result_t (*error_detected
)(struct pci_dev
*dev
,
740 enum pci_channel_state error
);
742 /* MMIO has been re-enabled, but not DMA */
743 pci_ers_result_t (*mmio_enabled
)(struct pci_dev
*dev
);
745 /* PCI slot has been reset */
746 pci_ers_result_t (*slot_reset
)(struct pci_dev
*dev
);
748 /* PCI function reset prepare or completed */
749 void (*reset_prepare
)(struct pci_dev
*dev
);
750 void (*reset_done
)(struct pci_dev
*dev
);
752 /* Device driver may resume normal operations */
753 void (*resume
)(struct pci_dev
*dev
);
759 struct list_head node
;
761 const struct pci_device_id
*id_table
; /* Must be non-NULL for probe to be called */
762 int (*probe
)(struct pci_dev
*dev
, const struct pci_device_id
*id
); /* New device inserted */
763 void (*remove
)(struct pci_dev
*dev
); /* Device removed (NULL if not a hot-plug capable driver) */
764 int (*suspend
)(struct pci_dev
*dev
, pm_message_t state
); /* Device suspended */
765 int (*suspend_late
)(struct pci_dev
*dev
, pm_message_t state
);
766 int (*resume_early
)(struct pci_dev
*dev
);
767 int (*resume
) (struct pci_dev
*dev
); /* Device woken up */
768 void (*shutdown
) (struct pci_dev
*dev
);
769 int (*sriov_configure
) (struct pci_dev
*dev
, int num_vfs
); /* On PF */
770 const struct pci_error_handlers
*err_handler
;
771 const struct attribute_group
**groups
;
772 struct device_driver driver
;
773 struct pci_dynids dynids
;
776 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
779 * PCI_DEVICE - macro used to describe a specific PCI device
780 * @vend: the 16 bit PCI Vendor ID
781 * @dev: the 16 bit PCI Device ID
783 * This macro is used to create a struct pci_device_id that matches a
784 * specific device. The subvendor and subdevice fields will be set to
787 #define PCI_DEVICE(vend,dev) \
788 .vendor = (vend), .device = (dev), \
789 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
792 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
793 * @vend: the 16 bit PCI Vendor ID
794 * @dev: the 16 bit PCI Device ID
795 * @subvend: the 16 bit PCI Subvendor ID
796 * @subdev: the 16 bit PCI Subdevice ID
798 * This macro is used to create a struct pci_device_id that matches a
799 * specific device with subsystem information.
801 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
802 .vendor = (vend), .device = (dev), \
803 .subvendor = (subvend), .subdevice = (subdev)
806 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
807 * @dev_class: the class, subclass, prog-if triple for this device
808 * @dev_class_mask: the class mask for this device
810 * This macro is used to create a struct pci_device_id that matches a
811 * specific PCI class. The vendor, device, subvendor, and subdevice
812 * fields will be set to PCI_ANY_ID.
814 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
815 .class = (dev_class), .class_mask = (dev_class_mask), \
816 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
817 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
820 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
821 * @vend: the vendor name
822 * @dev: the 16 bit PCI Device ID
824 * This macro is used to create a struct pci_device_id that matches a
825 * specific PCI device. The subvendor, and subdevice fields will be set
826 * to PCI_ANY_ID. The macro allows the next field to follow as the device
829 #define PCI_VDEVICE(vend, dev) \
830 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
831 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
834 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
835 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
836 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
837 * @data: the driver data to be filled
839 * This macro is used to create a struct pci_device_id that matches a
840 * specific PCI device. The subvendor, and subdevice fields will be set
843 #define PCI_DEVICE_DATA(vend, dev, data) \
844 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
845 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
846 .driver_data = (kernel_ulong_t)(data)
849 PCI_REASSIGN_ALL_RSRC
= 0x00000001, /* Ignore firmware setup */
850 PCI_REASSIGN_ALL_BUS
= 0x00000002, /* Reassign all bus numbers */
851 PCI_PROBE_ONLY
= 0x00000004, /* Use existing setup */
852 PCI_CAN_SKIP_ISA_ALIGN
= 0x00000008, /* Don't do ISA alignment */
853 PCI_ENABLE_PROC_DOMAINS
= 0x00000010, /* Enable domains in /proc */
854 PCI_COMPAT_DOMAIN_0
= 0x00000020, /* ... except domain 0 */
855 PCI_SCAN_ALL_PCIE_DEVS
= 0x00000040, /* Scan all, not just dev 0 */
858 /* These external functions are only available when PCI support is enabled */
861 extern unsigned int pci_flags
;
863 static inline void pci_set_flags(int flags
) { pci_flags
= flags
; }
864 static inline void pci_add_flags(int flags
) { pci_flags
|= flags
; }
865 static inline void pci_clear_flags(int flags
) { pci_flags
&= ~flags
; }
866 static inline int pci_has_flag(int flag
) { return pci_flags
& flag
; }
868 void pcie_bus_configure_settings(struct pci_bus
*bus
);
870 enum pcie_bus_config_types
{
871 PCIE_BUS_TUNE_OFF
, /* Don't touch MPS at all */
872 PCIE_BUS_DEFAULT
, /* Ensure MPS matches upstream bridge */
873 PCIE_BUS_SAFE
, /* Use largest MPS boot-time devices support */
874 PCIE_BUS_PERFORMANCE
, /* Use MPS and MRRS for best performance */
875 PCIE_BUS_PEER2PEER
, /* Set MPS = 128 for all devices */
878 extern enum pcie_bus_config_types pcie_bus_config
;
880 extern struct bus_type pci_bus_type
;
882 /* Do NOT directly access these two variables, unless you are arch-specific PCI
883 * code, or PCI core code. */
884 extern struct list_head pci_root_buses
; /* List of all known PCI buses */
885 /* Some device drivers need know if PCI is initiated */
886 int no_pci_devices(void);
888 void pcibios_resource_survey_bus(struct pci_bus
*bus
);
889 void pcibios_bus_add_device(struct pci_dev
*pdev
);
890 void pcibios_add_bus(struct pci_bus
*bus
);
891 void pcibios_remove_bus(struct pci_bus
*bus
);
892 void pcibios_fixup_bus(struct pci_bus
*);
893 int __must_check
pcibios_enable_device(struct pci_dev
*, int mask
);
894 /* Architecture-specific versions may override this (weak) */
895 char *pcibios_setup(char *str
);
897 /* Used only when drivers/pci/setup.c is used */
898 resource_size_t
pcibios_align_resource(void *, const struct resource
*,
902 /* Weak but can be overriden by arch */
903 void pci_fixup_cardbus(struct pci_bus
*);
905 /* Generic PCI functions used internally */
907 void pcibios_resource_to_bus(struct pci_bus
*bus
, struct pci_bus_region
*region
,
908 struct resource
*res
);
909 void pcibios_bus_to_resource(struct pci_bus
*bus
, struct resource
*res
,
910 struct pci_bus_region
*region
);
911 void pcibios_scan_specific_bus(int busn
);
912 struct pci_bus
*pci_find_bus(int domain
, int busnr
);
913 void pci_bus_add_devices(const struct pci_bus
*bus
);
914 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
);
915 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
916 struct pci_ops
*ops
, void *sysdata
,
917 struct list_head
*resources
);
918 int pci_host_probe(struct pci_host_bridge
*bridge
);
919 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int busmax
);
920 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int busmax
);
921 void pci_bus_release_busn_res(struct pci_bus
*b
);
922 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
923 struct pci_ops
*ops
, void *sysdata
,
924 struct list_head
*resources
);
925 int pci_scan_root_bus_bridge(struct pci_host_bridge
*bridge
);
926 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
928 void pcie_update_link_speed(struct pci_bus
*bus
, u16 link_status
);
929 struct pci_slot
*pci_create_slot(struct pci_bus
*parent
, int slot_nr
,
931 struct hotplug_slot
*hotplug
);
932 void pci_destroy_slot(struct pci_slot
*slot
);
934 void pci_dev_assign_slot(struct pci_dev
*dev
);
936 static inline void pci_dev_assign_slot(struct pci_dev
*dev
) { }
938 int pci_scan_slot(struct pci_bus
*bus
, int devfn
);
939 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
);
940 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
);
941 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
942 void pci_bus_add_device(struct pci_dev
*dev
);
943 void pci_read_bridge_bases(struct pci_bus
*child
);
944 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
945 struct resource
*res
);
946 struct pci_dev
*pci_find_pcie_root_port(struct pci_dev
*dev
);
947 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
);
948 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
);
949 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
);
950 struct pci_dev
*pci_dev_get(struct pci_dev
*dev
);
951 void pci_dev_put(struct pci_dev
*dev
);
952 void pci_remove_bus(struct pci_bus
*b
);
953 void pci_stop_and_remove_bus_device(struct pci_dev
*dev
);
954 void pci_stop_and_remove_bus_device_locked(struct pci_dev
*dev
);
955 void pci_stop_root_bus(struct pci_bus
*bus
);
956 void pci_remove_root_bus(struct pci_bus
*bus
);
957 void pci_setup_cardbus(struct pci_bus
*bus
);
958 void pcibios_setup_bridge(struct pci_bus
*bus
, unsigned long type
);
959 void pci_sort_breadthfirst(void);
960 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
961 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
963 /* Generic PCI functions exported to card drivers */
965 enum pci_lost_interrupt_reason
{
966 PCI_LOST_IRQ_NO_INFORMATION
= 0,
967 PCI_LOST_IRQ_DISABLE_MSI
,
968 PCI_LOST_IRQ_DISABLE_MSIX
,
969 PCI_LOST_IRQ_DISABLE_ACPI
,
971 enum pci_lost_interrupt_reason
pci_lost_interrupt(struct pci_dev
*dev
);
972 int pci_find_capability(struct pci_dev
*dev
, int cap
);
973 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
);
974 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
);
975 int pci_find_next_ext_capability(struct pci_dev
*dev
, int pos
, int cap
);
976 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
);
977 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
);
978 struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
);
980 struct pci_dev
*pci_get_device(unsigned int vendor
, unsigned int device
,
981 struct pci_dev
*from
);
982 struct pci_dev
*pci_get_subsys(unsigned int vendor
, unsigned int device
,
983 unsigned int ss_vendor
, unsigned int ss_device
,
984 struct pci_dev
*from
);
985 struct pci_dev
*pci_get_slot(struct pci_bus
*bus
, unsigned int devfn
);
986 struct pci_dev
*pci_get_domain_bus_and_slot(int domain
, unsigned int bus
,
988 struct pci_dev
*pci_get_class(unsigned int class, struct pci_dev
*from
);
989 int pci_dev_present(const struct pci_device_id
*ids
);
991 int pci_bus_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
993 int pci_bus_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
994 int where
, u16
*val
);
995 int pci_bus_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
996 int where
, u32
*val
);
997 int pci_bus_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
999 int pci_bus_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
1000 int where
, u16 val
);
1001 int pci_bus_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
1002 int where
, u32 val
);
1004 int pci_generic_config_read(struct pci_bus
*bus
, unsigned int devfn
,
1005 int where
, int size
, u32
*val
);
1006 int pci_generic_config_write(struct pci_bus
*bus
, unsigned int devfn
,
1007 int where
, int size
, u32 val
);
1008 int pci_generic_config_read32(struct pci_bus
*bus
, unsigned int devfn
,
1009 int where
, int size
, u32
*val
);
1010 int pci_generic_config_write32(struct pci_bus
*bus
, unsigned int devfn
,
1011 int where
, int size
, u32 val
);
1013 struct pci_ops
*pci_bus_set_ops(struct pci_bus
*bus
, struct pci_ops
*ops
);
1015 int pci_read_config_byte(const struct pci_dev
*dev
, int where
, u8
*val
);
1016 int pci_read_config_word(const struct pci_dev
*dev
, int where
, u16
*val
);
1017 int pci_read_config_dword(const struct pci_dev
*dev
, int where
, u32
*val
);
1018 int pci_write_config_byte(const struct pci_dev
*dev
, int where
, u8 val
);
1019 int pci_write_config_word(const struct pci_dev
*dev
, int where
, u16 val
);
1020 int pci_write_config_dword(const struct pci_dev
*dev
, int where
, u32 val
);
1022 int pcie_capability_read_word(struct pci_dev
*dev
, int pos
, u16
*val
);
1023 int pcie_capability_read_dword(struct pci_dev
*dev
, int pos
, u32
*val
);
1024 int pcie_capability_write_word(struct pci_dev
*dev
, int pos
, u16 val
);
1025 int pcie_capability_write_dword(struct pci_dev
*dev
, int pos
, u32 val
);
1026 int pcie_capability_clear_and_set_word(struct pci_dev
*dev
, int pos
,
1027 u16 clear
, u16 set
);
1028 int pcie_capability_clear_and_set_dword(struct pci_dev
*dev
, int pos
,
1029 u32 clear
, u32 set
);
1031 static inline int pcie_capability_set_word(struct pci_dev
*dev
, int pos
,
1034 return pcie_capability_clear_and_set_word(dev
, pos
, 0, set
);
1037 static inline int pcie_capability_set_dword(struct pci_dev
*dev
, int pos
,
1040 return pcie_capability_clear_and_set_dword(dev
, pos
, 0, set
);
1043 static inline int pcie_capability_clear_word(struct pci_dev
*dev
, int pos
,
1046 return pcie_capability_clear_and_set_word(dev
, pos
, clear
, 0);
1049 static inline int pcie_capability_clear_dword(struct pci_dev
*dev
, int pos
,
1052 return pcie_capability_clear_and_set_dword(dev
, pos
, clear
, 0);
1055 /* User-space driven config access */
1056 int pci_user_read_config_byte(struct pci_dev
*dev
, int where
, u8
*val
);
1057 int pci_user_read_config_word(struct pci_dev
*dev
, int where
, u16
*val
);
1058 int pci_user_read_config_dword(struct pci_dev
*dev
, int where
, u32
*val
);
1059 int pci_user_write_config_byte(struct pci_dev
*dev
, int where
, u8 val
);
1060 int pci_user_write_config_word(struct pci_dev
*dev
, int where
, u16 val
);
1061 int pci_user_write_config_dword(struct pci_dev
*dev
, int where
, u32 val
);
1063 int __must_check
pci_enable_device(struct pci_dev
*dev
);
1064 int __must_check
pci_enable_device_io(struct pci_dev
*dev
);
1065 int __must_check
pci_enable_device_mem(struct pci_dev
*dev
);
1066 int __must_check
pci_reenable_device(struct pci_dev
*);
1067 int __must_check
pcim_enable_device(struct pci_dev
*pdev
);
1068 void pcim_pin_device(struct pci_dev
*pdev
);
1070 static inline bool pci_intx_mask_supported(struct pci_dev
*pdev
)
1073 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1074 * writable and no quirk has marked the feature broken.
1076 return !pdev
->broken_intx_masking
;
1079 static inline int pci_is_enabled(struct pci_dev
*pdev
)
1081 return (atomic_read(&pdev
->enable_cnt
) > 0);
1084 static inline int pci_is_managed(struct pci_dev
*pdev
)
1086 return pdev
->is_managed
;
1089 void pci_disable_device(struct pci_dev
*dev
);
1091 extern unsigned int pcibios_max_latency
;
1092 void pci_set_master(struct pci_dev
*dev
);
1093 void pci_clear_master(struct pci_dev
*dev
);
1095 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
);
1096 int pci_set_cacheline_size(struct pci_dev
*dev
);
1097 #define HAVE_PCI_SET_MWI
1098 int __must_check
pci_set_mwi(struct pci_dev
*dev
);
1099 int __must_check
pcim_set_mwi(struct pci_dev
*dev
);
1100 int pci_try_set_mwi(struct pci_dev
*dev
);
1101 void pci_clear_mwi(struct pci_dev
*dev
);
1102 void pci_intx(struct pci_dev
*dev
, int enable
);
1103 bool pci_check_and_mask_intx(struct pci_dev
*dev
);
1104 bool pci_check_and_unmask_intx(struct pci_dev
*dev
);
1105 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
);
1106 int pci_wait_for_pending_transaction(struct pci_dev
*dev
);
1107 int pcix_get_max_mmrbc(struct pci_dev
*dev
);
1108 int pcix_get_mmrbc(struct pci_dev
*dev
);
1109 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
);
1110 int pcie_get_readrq(struct pci_dev
*dev
);
1111 int pcie_set_readrq(struct pci_dev
*dev
, int rq
);
1112 int pcie_get_mps(struct pci_dev
*dev
);
1113 int pcie_set_mps(struct pci_dev
*dev
, int mps
);
1114 u32
pcie_bandwidth_available(struct pci_dev
*dev
, struct pci_dev
**limiting_dev
,
1115 enum pci_bus_speed
*speed
,
1116 enum pcie_link_width
*width
);
1117 void pcie_print_link_status(struct pci_dev
*dev
);
1118 bool pcie_has_flr(struct pci_dev
*dev
);
1119 int pcie_flr(struct pci_dev
*dev
);
1120 int __pci_reset_function_locked(struct pci_dev
*dev
);
1121 int pci_reset_function(struct pci_dev
*dev
);
1122 int pci_reset_function_locked(struct pci_dev
*dev
);
1123 int pci_try_reset_function(struct pci_dev
*dev
);
1124 int pci_probe_reset_slot(struct pci_slot
*slot
);
1125 int pci_probe_reset_bus(struct pci_bus
*bus
);
1126 int pci_reset_bus(struct pci_dev
*dev
);
1127 void pci_reset_secondary_bus(struct pci_dev
*dev
);
1128 void pcibios_reset_secondary_bus(struct pci_dev
*dev
);
1129 void pci_update_resource(struct pci_dev
*dev
, int resno
);
1130 int __must_check
pci_assign_resource(struct pci_dev
*dev
, int i
);
1131 int __must_check
pci_reassign_resource(struct pci_dev
*dev
, int i
, resource_size_t add_size
, resource_size_t align
);
1132 void pci_release_resource(struct pci_dev
*dev
, int resno
);
1133 int __must_check
pci_resize_resource(struct pci_dev
*dev
, int i
, int size
);
1134 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
);
1135 bool pci_device_is_present(struct pci_dev
*pdev
);
1136 void pci_ignore_hotplug(struct pci_dev
*dev
);
1138 int __printf(6, 7) pci_request_irq(struct pci_dev
*dev
, unsigned int nr
,
1139 irq_handler_t handler
, irq_handler_t thread_fn
, void *dev_id
,
1140 const char *fmt
, ...);
1141 void pci_free_irq(struct pci_dev
*dev
, unsigned int nr
, void *dev_id
);
1143 /* ROM control related routines */
1144 int pci_enable_rom(struct pci_dev
*pdev
);
1145 void pci_disable_rom(struct pci_dev
*pdev
);
1146 void __iomem __must_check
*pci_map_rom(struct pci_dev
*pdev
, size_t *size
);
1147 void pci_unmap_rom(struct pci_dev
*pdev
, void __iomem
*rom
);
1148 void __iomem __must_check
*pci_platform_rom(struct pci_dev
*pdev
, size_t *size
);
1150 /* Power management related routines */
1151 int pci_save_state(struct pci_dev
*dev
);
1152 void pci_restore_state(struct pci_dev
*dev
);
1153 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
);
1154 int pci_load_saved_state(struct pci_dev
*dev
,
1155 struct pci_saved_state
*state
);
1156 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1157 struct pci_saved_state
**state
);
1158 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
);
1159 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
,
1161 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
);
1162 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
,
1163 u16 cap
, unsigned int size
);
1164 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
);
1165 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
);
1166 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
);
1167 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
);
1168 void pci_pme_active(struct pci_dev
*dev
, bool enable
);
1169 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
);
1170 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
);
1171 int pci_prepare_to_sleep(struct pci_dev
*dev
);
1172 int pci_back_from_sleep(struct pci_dev
*dev
);
1173 bool pci_dev_run_wake(struct pci_dev
*dev
);
1174 bool pci_check_pme_status(struct pci_dev
*dev
);
1175 void pci_pme_wakeup_bus(struct pci_bus
*bus
);
1176 void pci_d3cold_enable(struct pci_dev
*dev
);
1177 void pci_d3cold_disable(struct pci_dev
*dev
);
1178 bool pcie_relaxed_ordering_enabled(struct pci_dev
*dev
);
1179 void pci_wakeup_bus(struct pci_bus
*bus
);
1180 void pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
);
1182 /* PCI Virtual Channel */
1183 int pci_save_vc_state(struct pci_dev
*dev
);
1184 void pci_restore_vc_state(struct pci_dev
*dev
);
1185 void pci_allocate_vc_save_buffers(struct pci_dev
*dev
);
1187 /* For use by arch with custom probe code */
1188 void set_pcie_port_type(struct pci_dev
*pdev
);
1189 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
);
1191 /* Functions for PCI Hotplug drivers to use */
1192 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1193 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
);
1194 unsigned int pci_rescan_bus(struct pci_bus
*bus
);
1195 void pci_lock_rescan_remove(void);
1196 void pci_unlock_rescan_remove(void);
1198 /* Vital Product Data routines */
1199 ssize_t
pci_read_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, void *buf
);
1200 ssize_t
pci_write_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, const void *buf
);
1201 int pci_set_vpd_size(struct pci_dev
*dev
, size_t len
);
1203 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1204 resource_size_t
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
);
1205 void pci_bus_assign_resources(const struct pci_bus
*bus
);
1206 void pci_bus_claim_resources(struct pci_bus
*bus
);
1207 void pci_bus_size_bridges(struct pci_bus
*bus
);
1208 int pci_claim_resource(struct pci_dev
*, int);
1209 int pci_claim_bridge_resource(struct pci_dev
*bridge
, int i
);
1210 void pci_assign_unassigned_resources(void);
1211 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
);
1212 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
);
1213 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
);
1214 int pci_reassign_bridge_resources(struct pci_dev
*bridge
, unsigned long type
);
1215 void pdev_enable_device(struct pci_dev
*);
1216 int pci_enable_resources(struct pci_dev
*, int mask
);
1217 void pci_assign_irq(struct pci_dev
*dev
);
1218 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
);
1219 #define HAVE_PCI_REQ_REGIONS 2
1220 int __must_check
pci_request_regions(struct pci_dev
*, const char *);
1221 int __must_check
pci_request_regions_exclusive(struct pci_dev
*, const char *);
1222 void pci_release_regions(struct pci_dev
*);
1223 int __must_check
pci_request_region(struct pci_dev
*, int, const char *);
1224 int __must_check
pci_request_region_exclusive(struct pci_dev
*, int, const char *);
1225 void pci_release_region(struct pci_dev
*, int);
1226 int pci_request_selected_regions(struct pci_dev
*, int, const char *);
1227 int pci_request_selected_regions_exclusive(struct pci_dev
*, int, const char *);
1228 void pci_release_selected_regions(struct pci_dev
*, int);
1230 /* drivers/pci/bus.c */
1231 struct pci_bus
*pci_bus_get(struct pci_bus
*bus
);
1232 void pci_bus_put(struct pci_bus
*bus
);
1233 void pci_add_resource(struct list_head
*resources
, struct resource
*res
);
1234 void pci_add_resource_offset(struct list_head
*resources
, struct resource
*res
,
1235 resource_size_t offset
);
1236 void pci_free_resource_list(struct list_head
*resources
);
1237 void pci_bus_add_resource(struct pci_bus
*bus
, struct resource
*res
,
1238 unsigned int flags
);
1239 struct resource
*pci_bus_resource_n(const struct pci_bus
*bus
, int n
);
1240 void pci_bus_remove_resources(struct pci_bus
*bus
);
1241 int devm_request_pci_bus_resources(struct device
*dev
,
1242 struct list_head
*resources
);
1244 /* Temporary until new and working PCI SBR API in place */
1245 int pci_bridge_secondary_bus_reset(struct pci_dev
*dev
);
1247 #define pci_bus_for_each_resource(bus, res, i) \
1249 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1252 int __must_check
pci_bus_alloc_resource(struct pci_bus
*bus
,
1253 struct resource
*res
, resource_size_t size
,
1254 resource_size_t align
, resource_size_t min
,
1255 unsigned long type_mask
,
1256 resource_size_t (*alignf
)(void *,
1257 const struct resource
*,
1263 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
1264 resource_size_t size
);
1265 unsigned long pci_address_to_pio(phys_addr_t addr
);
1266 phys_addr_t
pci_pio_to_address(unsigned long pio
);
1267 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
);
1268 int devm_pci_remap_iospace(struct device
*dev
, const struct resource
*res
,
1269 phys_addr_t phys_addr
);
1270 void pci_unmap_iospace(struct resource
*res
);
1271 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
1272 resource_size_t offset
,
1273 resource_size_t size
);
1274 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
1275 struct resource
*res
);
1277 static inline pci_bus_addr_t
pci_bus_address(struct pci_dev
*pdev
, int bar
)
1279 struct pci_bus_region region
;
1281 pcibios_resource_to_bus(pdev
->bus
, ®ion
, &pdev
->resource
[bar
]);
1282 return region
.start
;
1285 /* Proper probing supporting hot-pluggable devices */
1286 int __must_check
__pci_register_driver(struct pci_driver
*, struct module
*,
1287 const char *mod_name
);
1289 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1290 #define pci_register_driver(driver) \
1291 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1293 void pci_unregister_driver(struct pci_driver
*dev
);
1296 * module_pci_driver() - Helper macro for registering a PCI driver
1297 * @__pci_driver: pci_driver struct
1299 * Helper macro for PCI drivers which do not do anything special in module
1300 * init/exit. This eliminates a lot of boilerplate. Each module may only
1301 * use this macro once, and calling it replaces module_init() and module_exit()
1303 #define module_pci_driver(__pci_driver) \
1304 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1307 * builtin_pci_driver() - Helper macro for registering a PCI driver
1308 * @__pci_driver: pci_driver struct
1310 * Helper macro for PCI drivers which do not do anything special in their
1311 * init code. This eliminates a lot of boilerplate. Each driver may only
1312 * use this macro once, and calling it replaces device_initcall(...)
1314 #define builtin_pci_driver(__pci_driver) \
1315 builtin_driver(__pci_driver, pci_register_driver)
1317 struct pci_driver
*pci_dev_driver(const struct pci_dev
*dev
);
1318 int pci_add_dynid(struct pci_driver
*drv
,
1319 unsigned int vendor
, unsigned int device
,
1320 unsigned int subvendor
, unsigned int subdevice
,
1321 unsigned int class, unsigned int class_mask
,
1322 unsigned long driver_data
);
1323 const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1324 struct pci_dev
*dev
);
1325 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
,
1328 void pci_walk_bus(struct pci_bus
*top
, int (*cb
)(struct pci_dev
*, void *),
1330 int pci_cfg_space_size(struct pci_dev
*dev
);
1331 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
);
1332 void pci_setup_bridge(struct pci_bus
*bus
);
1333 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
1334 unsigned long type
);
1336 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1337 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1339 int pci_set_vga_state(struct pci_dev
*pdev
, bool decode
,
1340 unsigned int command_bits
, u32 flags
);
1342 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1343 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1344 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1345 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1346 #define PCI_IRQ_ALL_TYPES \
1347 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1349 /* kmem_cache style wrapper around pci_alloc_consistent() */
1351 #include <linux/dmapool.h>
1353 #define pci_pool dma_pool
1354 #define pci_pool_create(name, pdev, size, align, allocation) \
1355 dma_pool_create(name, &pdev->dev, size, align, allocation)
1356 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1357 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1358 #define pci_pool_zalloc(pool, flags, handle) \
1359 dma_pool_zalloc(pool, flags, handle)
1360 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1363 u32 vector
; /* Kernel uses to write allocated vector */
1364 u16 entry
; /* Driver uses to specify entry, OS writes */
1367 #ifdef CONFIG_PCI_MSI
1368 int pci_msi_vec_count(struct pci_dev
*dev
);
1369 void pci_disable_msi(struct pci_dev
*dev
);
1370 int pci_msix_vec_count(struct pci_dev
*dev
);
1371 void pci_disable_msix(struct pci_dev
*dev
);
1372 void pci_restore_msi_state(struct pci_dev
*dev
);
1373 int pci_msi_enabled(void);
1374 int pci_enable_msi(struct pci_dev
*dev
);
1375 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1376 int minvec
, int maxvec
);
1377 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1378 struct msix_entry
*entries
, int nvec
)
1380 int rc
= pci_enable_msix_range(dev
, entries
, nvec
, nvec
);
1385 int pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1386 unsigned int max_vecs
, unsigned int flags
,
1387 const struct irq_affinity
*affd
);
1389 void pci_free_irq_vectors(struct pci_dev
*dev
);
1390 int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
);
1391 const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*pdev
, int vec
);
1392 int pci_irq_get_node(struct pci_dev
*pdev
, int vec
);
1395 static inline int pci_msi_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1396 static inline void pci_disable_msi(struct pci_dev
*dev
) { }
1397 static inline int pci_msix_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1398 static inline void pci_disable_msix(struct pci_dev
*dev
) { }
1399 static inline void pci_restore_msi_state(struct pci_dev
*dev
) { }
1400 static inline int pci_msi_enabled(void) { return 0; }
1401 static inline int pci_enable_msi(struct pci_dev
*dev
)
1403 static inline int pci_enable_msix_range(struct pci_dev
*dev
,
1404 struct msix_entry
*entries
, int minvec
, int maxvec
)
1406 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1407 struct msix_entry
*entries
, int nvec
)
1411 pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1412 unsigned int max_vecs
, unsigned int flags
,
1413 const struct irq_affinity
*aff_desc
)
1415 if ((flags
& PCI_IRQ_LEGACY
) && min_vecs
== 1 && dev
->irq
)
1420 static inline void pci_free_irq_vectors(struct pci_dev
*dev
)
1424 static inline int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
)
1426 if (WARN_ON_ONCE(nr
> 0))
1430 static inline const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*pdev
,
1433 return cpu_possible_mask
;
1436 static inline int pci_irq_get_node(struct pci_dev
*pdev
, int vec
)
1438 return first_online_node
;
1443 pci_alloc_irq_vectors(struct pci_dev
*dev
, unsigned int min_vecs
,
1444 unsigned int max_vecs
, unsigned int flags
)
1446 return pci_alloc_irq_vectors_affinity(dev
, min_vecs
, max_vecs
, flags
,
1451 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1452 * @d: the INTx IRQ domain
1453 * @node: the DT node for the device whose interrupt we're translating
1454 * @intspec: the interrupt specifier data from the DT
1455 * @intsize: the number of entries in @intspec
1456 * @out_hwirq: pointer at which to write the hwirq number
1457 * @out_type: pointer at which to write the interrupt type
1459 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1460 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1461 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1462 * INTx value to obtain the hwirq number.
1464 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1466 static inline int pci_irqd_intx_xlate(struct irq_domain
*d
,
1467 struct device_node
*node
,
1469 unsigned int intsize
,
1470 unsigned long *out_hwirq
,
1471 unsigned int *out_type
)
1473 const u32 intx
= intspec
[0];
1475 if (intx
< PCI_INTERRUPT_INTA
|| intx
> PCI_INTERRUPT_INTD
)
1478 *out_hwirq
= intx
- PCI_INTERRUPT_INTA
;
1482 #ifdef CONFIG_PCIEPORTBUS
1483 extern bool pcie_ports_disabled
;
1484 extern bool pcie_ports_native
;
1486 #define pcie_ports_disabled true
1487 #define pcie_ports_native false
1490 #ifdef CONFIG_PCIEASPM
1491 bool pcie_aspm_support_enabled(void);
1493 static inline bool pcie_aspm_support_enabled(void) { return false; }
1496 #ifdef CONFIG_PCIEAER
1497 bool pci_aer_available(void);
1499 static inline bool pci_aer_available(void) { return false; }
1502 #ifdef CONFIG_PCIE_ECRC
1503 void pcie_set_ecrc_checking(struct pci_dev
*dev
);
1504 void pcie_ecrc_get_policy(char *str
);
1506 static inline void pcie_set_ecrc_checking(struct pci_dev
*dev
) { }
1507 static inline void pcie_ecrc_get_policy(char *str
) { }
1510 bool pci_ats_disabled(void);
1512 #ifdef CONFIG_PCI_ATS
1513 /* Address Translation Service */
1514 void pci_ats_init(struct pci_dev
*dev
);
1515 int pci_enable_ats(struct pci_dev
*dev
, int ps
);
1516 void pci_disable_ats(struct pci_dev
*dev
);
1517 int pci_ats_queue_depth(struct pci_dev
*dev
);
1519 static inline void pci_ats_init(struct pci_dev
*d
) { }
1520 static inline int pci_enable_ats(struct pci_dev
*d
, int ps
) { return -ENODEV
; }
1521 static inline void pci_disable_ats(struct pci_dev
*d
) { }
1522 static inline int pci_ats_queue_depth(struct pci_dev
*d
) { return -ENODEV
; }
1525 #ifdef CONFIG_PCIE_PTM
1526 int pci_enable_ptm(struct pci_dev
*dev
, u8
*granularity
);
1528 static inline int pci_enable_ptm(struct pci_dev
*dev
, u8
*granularity
)
1532 void pci_cfg_access_lock(struct pci_dev
*dev
);
1533 bool pci_cfg_access_trylock(struct pci_dev
*dev
);
1534 void pci_cfg_access_unlock(struct pci_dev
*dev
);
1537 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1538 * a PCI domain is defined to be a set of PCI buses which share
1539 * configuration space.
1541 #ifdef CONFIG_PCI_DOMAINS
1542 extern int pci_domains_supported
;
1544 enum { pci_domains_supported
= 0 };
1545 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1546 static inline int pci_proc_domain(struct pci_bus
*bus
) { return 0; }
1547 #endif /* CONFIG_PCI_DOMAINS */
1550 * Generic implementation for PCI domain support. If your
1551 * architecture does not need custom management of PCI
1552 * domains then this implementation will be used
1554 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1555 static inline int pci_domain_nr(struct pci_bus
*bus
)
1557 return bus
->domain_nr
;
1560 int acpi_pci_bus_find_domain_nr(struct pci_bus
*bus
);
1562 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus
*bus
)
1565 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
);
1568 /* Some architectures require additional setup to direct VGA traffic */
1569 typedef int (*arch_set_vga_state_t
)(struct pci_dev
*pdev
, bool decode
,
1570 unsigned int command_bits
, u32 flags
);
1571 void pci_register_set_vga_state(arch_set_vga_state_t func
);
1574 pci_request_io_regions(struct pci_dev
*pdev
, const char *name
)
1576 return pci_request_selected_regions(pdev
,
1577 pci_select_bars(pdev
, IORESOURCE_IO
), name
);
1581 pci_release_io_regions(struct pci_dev
*pdev
)
1583 return pci_release_selected_regions(pdev
,
1584 pci_select_bars(pdev
, IORESOURCE_IO
));
1588 pci_request_mem_regions(struct pci_dev
*pdev
, const char *name
)
1590 return pci_request_selected_regions(pdev
,
1591 pci_select_bars(pdev
, IORESOURCE_MEM
), name
);
1595 pci_release_mem_regions(struct pci_dev
*pdev
)
1597 return pci_release_selected_regions(pdev
,
1598 pci_select_bars(pdev
, IORESOURCE_MEM
));
1601 #else /* CONFIG_PCI is not enabled */
1603 static inline void pci_set_flags(int flags
) { }
1604 static inline void pci_add_flags(int flags
) { }
1605 static inline void pci_clear_flags(int flags
) { }
1606 static inline int pci_has_flag(int flag
) { return 0; }
1609 * If the system does not have PCI, clearly these return errors. Define
1610 * these as simple inline functions to avoid hair in drivers.
1612 #define _PCI_NOP(o, s, t) \
1613 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1615 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1617 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1618 _PCI_NOP(o, word, u16 x) \
1619 _PCI_NOP(o, dword, u32 x)
1620 _PCI_NOP_ALL(read
, *)
1621 _PCI_NOP_ALL(write
,)
1623 static inline struct pci_dev
*pci_get_device(unsigned int vendor
,
1624 unsigned int device
,
1625 struct pci_dev
*from
)
1628 static inline struct pci_dev
*pci_get_subsys(unsigned int vendor
,
1629 unsigned int device
,
1630 unsigned int ss_vendor
,
1631 unsigned int ss_device
,
1632 struct pci_dev
*from
)
1635 static inline struct pci_dev
*pci_get_class(unsigned int class,
1636 struct pci_dev
*from
)
1639 #define pci_dev_present(ids) (0)
1640 #define no_pci_devices() (1)
1641 #define pci_dev_put(dev) do { } while (0)
1643 static inline void pci_set_master(struct pci_dev
*dev
) { }
1644 static inline int pci_enable_device(struct pci_dev
*dev
) { return -EIO
; }
1645 static inline void pci_disable_device(struct pci_dev
*dev
) { }
1646 static inline int pci_assign_resource(struct pci_dev
*dev
, int i
)
1648 static inline int __pci_register_driver(struct pci_driver
*drv
,
1649 struct module
*owner
)
1651 static inline int pci_register_driver(struct pci_driver
*drv
)
1653 static inline void pci_unregister_driver(struct pci_driver
*drv
) { }
1654 static inline int pci_find_capability(struct pci_dev
*dev
, int cap
)
1656 static inline int pci_find_next_capability(struct pci_dev
*dev
, u8 post
,
1659 static inline int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
1662 /* Power management related routines */
1663 static inline int pci_save_state(struct pci_dev
*dev
) { return 0; }
1664 static inline void pci_restore_state(struct pci_dev
*dev
) { }
1665 static inline int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1667 static inline int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1669 static inline pci_power_t
pci_choose_state(struct pci_dev
*dev
,
1672 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1676 static inline struct resource
*pci_find_resource(struct pci_dev
*dev
,
1677 struct resource
*res
)
1679 static inline int pci_request_regions(struct pci_dev
*dev
, const char *res_name
)
1681 static inline void pci_release_regions(struct pci_dev
*dev
) { }
1683 static inline unsigned long pci_address_to_pio(phys_addr_t addr
) { return -1; }
1685 static inline void pci_block_cfg_access(struct pci_dev
*dev
) { }
1686 static inline int pci_block_cfg_access_in_atomic(struct pci_dev
*dev
)
1688 static inline void pci_unblock_cfg_access(struct pci_dev
*dev
) { }
1690 static inline struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
)
1692 static inline struct pci_dev
*pci_get_slot(struct pci_bus
*bus
,
1695 static inline struct pci_dev
*pci_get_domain_bus_and_slot(int domain
,
1696 unsigned int bus
, unsigned int devfn
)
1699 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1700 static inline struct pci_dev
*pci_dev_get(struct pci_dev
*dev
) { return NULL
; }
1702 #define dev_is_pci(d) (false)
1703 #define dev_is_pf(d) (false)
1704 static inline bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
1706 static inline int pci_irqd_intx_xlate(struct irq_domain
*d
,
1707 struct device_node
*node
,
1709 unsigned int intsize
,
1710 unsigned long *out_hwirq
,
1711 unsigned int *out_type
)
1714 static inline const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1715 struct pci_dev
*dev
)
1717 #endif /* CONFIG_PCI */
1719 /* Include architecture-dependent settings and functions */
1721 #include <asm/pci.h>
1723 /* These two functions provide almost identical functionality. Depennding
1724 * on the architecture, one will be implemented as a wrapper around the
1725 * other (in drivers/pci/mmap.c).
1727 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1728 * is expected to be an offset within that region.
1730 * pci_mmap_page_range() is the legacy architecture-specific interface,
1731 * which accepts a "user visible" resource address converted by
1732 * pci_resource_to_user(), as used in the legacy mmap() interface in
1735 int pci_mmap_resource_range(struct pci_dev
*dev
, int bar
,
1736 struct vm_area_struct
*vma
,
1737 enum pci_mmap_state mmap_state
, int write_combine
);
1738 int pci_mmap_page_range(struct pci_dev
*pdev
, int bar
,
1739 struct vm_area_struct
*vma
,
1740 enum pci_mmap_state mmap_state
, int write_combine
);
1742 #ifndef arch_can_pci_mmap_wc
1743 #define arch_can_pci_mmap_wc() 0
1746 #ifndef arch_can_pci_mmap_io
1747 #define arch_can_pci_mmap_io() 0
1748 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1750 int pci_iobar_pfn(struct pci_dev
*pdev
, int bar
, struct vm_area_struct
*vma
);
1753 #ifndef pci_root_bus_fwnode
1754 #define pci_root_bus_fwnode(bus) NULL
1758 * These helpers provide future and backwards compatibility
1759 * for accessing popular PCI BAR info
1761 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1762 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1763 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1764 #define pci_resource_len(dev,bar) \
1765 ((pci_resource_start((dev), (bar)) == 0 && \
1766 pci_resource_end((dev), (bar)) == \
1767 pci_resource_start((dev), (bar))) ? 0 : \
1769 (pci_resource_end((dev), (bar)) - \
1770 pci_resource_start((dev), (bar)) + 1))
1773 * Similar to the helpers above, these manipulate per-pci_dev
1774 * driver-specific data. They are really just a wrapper around
1775 * the generic device structure functions of these calls.
1777 static inline void *pci_get_drvdata(struct pci_dev
*pdev
)
1779 return dev_get_drvdata(&pdev
->dev
);
1782 static inline void pci_set_drvdata(struct pci_dev
*pdev
, void *data
)
1784 dev_set_drvdata(&pdev
->dev
, data
);
1787 static inline const char *pci_name(const struct pci_dev
*pdev
)
1789 return dev_name(&pdev
->dev
);
1794 * Some archs don't want to expose struct resource to userland as-is
1795 * in sysfs and /proc
1797 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1798 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1799 const struct resource
*rsrc
,
1800 resource_size_t
*start
, resource_size_t
*end
);
1802 static inline void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1803 const struct resource
*rsrc
, resource_size_t
*start
,
1804 resource_size_t
*end
)
1806 *start
= rsrc
->start
;
1809 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1813 * The world is not perfect and supplies us with broken PCI devices.
1814 * For at least a part of these bugs we need a work-around, so both
1815 * generic (drivers/pci/quirks.c) and per-architecture code can define
1816 * fixup hooks to be called for particular buggy devices.
1820 u16 vendor
; /* Or PCI_ANY_ID */
1821 u16 device
; /* Or PCI_ANY_ID */
1822 u32
class; /* Or PCI_ANY_ID */
1823 unsigned int class_shift
; /* should be 0, 8, 16 */
1824 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1827 void (*hook
)(struct pci_dev
*dev
);
1831 enum pci_fixup_pass
{
1832 pci_fixup_early
, /* Before probing BARs */
1833 pci_fixup_header
, /* After reading configuration header */
1834 pci_fixup_final
, /* Final phase of device fixups */
1835 pci_fixup_enable
, /* pci_enable_device() time */
1836 pci_fixup_resume
, /* pci_device_resume() */
1837 pci_fixup_suspend
, /* pci_device_suspend() */
1838 pci_fixup_resume_early
, /* pci_device_resume_early() */
1839 pci_fixup_suspend_late
, /* pci_device_suspend_late() */
1842 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1843 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1844 class_shift, hook) \
1845 __ADDRESSABLE(hook) \
1846 asm(".section " #sec ", \"a\" \n" \
1848 ".short " #vendor ", " #device " \n" \
1849 ".long " #class ", " #class_shift " \n" \
1850 ".long " #hook " - . \n" \
1852 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1853 class_shift, hook) \
1854 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1857 /* Anonymous variables would be nice... */
1858 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1859 class_shift, hook) \
1860 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1861 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1862 = { vendor, device, class, class_shift, hook };
1865 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1866 class_shift, hook) \
1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1868 hook, vendor, device, class, class_shift, hook)
1869 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1870 class_shift, hook) \
1871 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1872 hook, vendor, device, class, class_shift, hook)
1873 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1874 class_shift, hook) \
1875 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1876 hook, vendor, device, class, class_shift, hook)
1877 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1878 class_shift, hook) \
1879 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1880 hook, vendor, device, class, class_shift, hook)
1881 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1882 class_shift, hook) \
1883 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1884 resume##hook, vendor, device, class, class_shift, hook)
1885 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1886 class_shift, hook) \
1887 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1888 resume_early##hook, vendor, device, class, class_shift, hook)
1889 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1890 class_shift, hook) \
1891 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1892 suspend##hook, vendor, device, class, class_shift, hook)
1893 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1894 class_shift, hook) \
1895 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1896 suspend_late##hook, vendor, device, class, class_shift, hook)
1898 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1899 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1900 hook, vendor, device, PCI_ANY_ID, 0, hook)
1901 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1902 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1903 hook, vendor, device, PCI_ANY_ID, 0, hook)
1904 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1905 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1906 hook, vendor, device, PCI_ANY_ID, 0, hook)
1907 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1908 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1909 hook, vendor, device, PCI_ANY_ID, 0, hook)
1910 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1911 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1912 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1913 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1914 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1915 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1916 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1917 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1918 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1919 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1920 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1921 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1923 #ifdef CONFIG_PCI_QUIRKS
1924 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
);
1926 static inline void pci_fixup_device(enum pci_fixup_pass pass
,
1927 struct pci_dev
*dev
) { }
1930 void __iomem
*pcim_iomap(struct pci_dev
*pdev
, int bar
, unsigned long maxlen
);
1931 void pcim_iounmap(struct pci_dev
*pdev
, void __iomem
*addr
);
1932 void __iomem
* const *pcim_iomap_table(struct pci_dev
*pdev
);
1933 int pcim_iomap_regions(struct pci_dev
*pdev
, int mask
, const char *name
);
1934 int pcim_iomap_regions_request_all(struct pci_dev
*pdev
, int mask
,
1936 void pcim_iounmap_regions(struct pci_dev
*pdev
, int mask
);
1938 extern int pci_pci_problems
;
1939 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1940 #define PCIPCI_TRITON 2
1941 #define PCIPCI_NATOMA 4
1942 #define PCIPCI_VIAETBF 8
1943 #define PCIPCI_VSFX 16
1944 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1945 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1947 extern unsigned long pci_cardbus_io_size
;
1948 extern unsigned long pci_cardbus_mem_size
;
1949 extern u8 pci_dfl_cache_line_size
;
1950 extern u8 pci_cache_line_size
;
1952 extern unsigned long pci_hotplug_io_size
;
1953 extern unsigned long pci_hotplug_mem_size
;
1954 extern unsigned long pci_hotplug_bus_size
;
1956 /* Architecture-specific versions may override these (weak) */
1957 void pcibios_disable_device(struct pci_dev
*dev
);
1958 void pcibios_set_master(struct pci_dev
*dev
);
1959 int pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1960 enum pcie_reset_state state
);
1961 int pcibios_add_device(struct pci_dev
*dev
);
1962 void pcibios_release_device(struct pci_dev
*dev
);
1963 void pcibios_penalize_isa_irq(int irq
, int active
);
1964 int pcibios_alloc_irq(struct pci_dev
*dev
);
1965 void pcibios_free_irq(struct pci_dev
*dev
);
1966 resource_size_t
pcibios_default_alignment(void);
1968 #ifdef CONFIG_HIBERNATE_CALLBACKS
1969 extern struct dev_pm_ops pcibios_pm_ops
;
1972 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1973 void __init
pci_mmcfg_early_init(void);
1974 void __init
pci_mmcfg_late_init(void);
1976 static inline void pci_mmcfg_early_init(void) { }
1977 static inline void pci_mmcfg_late_init(void) { }
1980 int pci_ext_cfg_avail(void);
1982 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
);
1983 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
);
1985 #ifdef CONFIG_PCI_IOV
1986 int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
);
1987 int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
);
1989 int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
);
1990 void pci_disable_sriov(struct pci_dev
*dev
);
1991 int pci_iov_add_virtfn(struct pci_dev
*dev
, int id
);
1992 void pci_iov_remove_virtfn(struct pci_dev
*dev
, int id
);
1993 int pci_num_vf(struct pci_dev
*dev
);
1994 int pci_vfs_assigned(struct pci_dev
*dev
);
1995 int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
);
1996 int pci_sriov_get_totalvfs(struct pci_dev
*dev
);
1997 int pci_sriov_configure_simple(struct pci_dev
*dev
, int nr_virtfn
);
1998 resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
);
1999 void pci_vf_drivers_autoprobe(struct pci_dev
*dev
, bool probe
);
2001 /* Arch may override these (weak) */
2002 int pcibios_sriov_enable(struct pci_dev
*pdev
, u16 num_vfs
);
2003 int pcibios_sriov_disable(struct pci_dev
*pdev
);
2004 resource_size_t
pcibios_iov_resource_alignment(struct pci_dev
*dev
, int resno
);
2006 static inline int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
)
2010 static inline int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
)
2014 static inline int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
)
2016 static inline int pci_iov_add_virtfn(struct pci_dev
*dev
, int id
)
2020 static inline void pci_iov_remove_virtfn(struct pci_dev
*dev
,
2022 static inline void pci_disable_sriov(struct pci_dev
*dev
) { }
2023 static inline int pci_num_vf(struct pci_dev
*dev
) { return 0; }
2024 static inline int pci_vfs_assigned(struct pci_dev
*dev
)
2026 static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
)
2028 static inline int pci_sriov_get_totalvfs(struct pci_dev
*dev
)
2030 #define pci_sriov_configure_simple NULL
2031 static inline resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
)
2033 static inline void pci_vf_drivers_autoprobe(struct pci_dev
*dev
, bool probe
) { }
2036 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2037 void pci_hp_create_module_link(struct pci_slot
*pci_slot
);
2038 void pci_hp_remove_module_link(struct pci_slot
*pci_slot
);
2042 * pci_pcie_cap - get the saved PCIe capability offset
2045 * PCIe capability offset is calculated at PCI device initialization
2046 * time and saved in the data structure. This function returns saved
2047 * PCIe capability offset. Using this instead of pci_find_capability()
2048 * reduces unnecessary search in the PCI configuration space. If you
2049 * need to calculate PCIe capability offset from raw device for some
2050 * reasons, please use pci_find_capability() instead.
2052 static inline int pci_pcie_cap(struct pci_dev
*dev
)
2054 return dev
->pcie_cap
;
2058 * pci_is_pcie - check if the PCI device is PCI Express capable
2061 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2063 static inline bool pci_is_pcie(struct pci_dev
*dev
)
2065 return pci_pcie_cap(dev
);
2069 * pcie_caps_reg - get the PCIe Capabilities Register
2072 static inline u16
pcie_caps_reg(const struct pci_dev
*dev
)
2074 return dev
->pcie_flags_reg
;
2078 * pci_pcie_type - get the PCIe device/port type
2081 static inline int pci_pcie_type(const struct pci_dev
*dev
)
2083 return (pcie_caps_reg(dev
) & PCI_EXP_FLAGS_TYPE
) >> 4;
2086 static inline struct pci_dev
*pcie_find_root_port(struct pci_dev
*dev
)
2089 if (!pci_is_pcie(dev
))
2091 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2093 if (!dev
->bus
->self
)
2095 dev
= dev
->bus
->self
;
2100 void pci_request_acs(void);
2101 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
);
2102 bool pci_acs_path_enabled(struct pci_dev
*start
,
2103 struct pci_dev
*end
, u16 acs_flags
);
2104 int pci_enable_atomic_ops_to_root(struct pci_dev
*dev
, u32 cap_mask
);
2106 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2107 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2109 /* Large Resource Data Type Tag Item Names */
2110 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2111 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2112 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2114 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2115 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2116 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2118 /* Small Resource Data Type Tag Item Names */
2119 #define PCI_VPD_STIN_END 0x0f /* End */
2121 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2123 #define PCI_VPD_SRDT_TIN_MASK 0x78
2124 #define PCI_VPD_SRDT_LEN_MASK 0x07
2125 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2127 #define PCI_VPD_LRDT_TAG_SIZE 3
2128 #define PCI_VPD_SRDT_TAG_SIZE 1
2130 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2132 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2133 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2134 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2135 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2138 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2139 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2141 * Returns the extracted Large Resource Data Type length.
2143 static inline u16
pci_vpd_lrdt_size(const u8
*lrdt
)
2145 return (u16
)lrdt
[1] + ((u16
)lrdt
[2] << 8);
2149 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2150 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2152 * Returns the extracted Large Resource Data Type Tag item.
2154 static inline u16
pci_vpd_lrdt_tag(const u8
*lrdt
)
2156 return (u16
)(lrdt
[0] & PCI_VPD_LRDT_TIN_MASK
);
2160 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2161 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2163 * Returns the extracted Small Resource Data Type length.
2165 static inline u8
pci_vpd_srdt_size(const u8
*srdt
)
2167 return (*srdt
) & PCI_VPD_SRDT_LEN_MASK
;
2171 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2172 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2174 * Returns the extracted Small Resource Data Type Tag Item.
2176 static inline u8
pci_vpd_srdt_tag(const u8
*srdt
)
2178 return ((*srdt
) & PCI_VPD_SRDT_TIN_MASK
) >> 3;
2182 * pci_vpd_info_field_size - Extracts the information field length
2183 * @lrdt: Pointer to the beginning of an information field header
2185 * Returns the extracted information field length.
2187 static inline u8
pci_vpd_info_field_size(const u8
*info_field
)
2189 return info_field
[2];
2193 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2194 * @buf: Pointer to buffered vpd data
2195 * @off: The offset into the buffer at which to begin the search
2196 * @len: The length of the vpd buffer
2197 * @rdt: The Resource Data Type to search for
2199 * Returns the index where the Resource Data Type was found or
2200 * -ENOENT otherwise.
2202 int pci_vpd_find_tag(const u8
*buf
, unsigned int off
, unsigned int len
, u8 rdt
);
2205 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2206 * @buf: Pointer to buffered vpd data
2207 * @off: The offset into the buffer at which to begin the search
2208 * @len: The length of the buffer area, relative to off, in which to search
2209 * @kw: The keyword to search for
2211 * Returns the index where the information field keyword was found or
2212 * -ENOENT otherwise.
2214 int pci_vpd_find_info_keyword(const u8
*buf
, unsigned int off
,
2215 unsigned int len
, const char *kw
);
2217 /* PCI <-> OF binding helpers */
2221 void pci_set_of_node(struct pci_dev
*dev
);
2222 void pci_release_of_node(struct pci_dev
*dev
);
2223 void pci_set_bus_of_node(struct pci_bus
*bus
);
2224 void pci_release_bus_of_node(struct pci_bus
*bus
);
2225 struct irq_domain
*pci_host_bridge_of_msi_domain(struct pci_bus
*bus
);
2226 int pci_parse_request_of_pci_ranges(struct device
*dev
,
2227 struct list_head
*resources
,
2228 struct resource
**bus_range
);
2230 /* Arch may override this (weak) */
2231 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
);
2233 #else /* CONFIG_OF */
2234 static inline void pci_set_of_node(struct pci_dev
*dev
) { }
2235 static inline void pci_release_of_node(struct pci_dev
*dev
) { }
2236 static inline void pci_set_bus_of_node(struct pci_bus
*bus
) { }
2237 static inline void pci_release_bus_of_node(struct pci_bus
*bus
) { }
2238 static inline struct irq_domain
*
2239 pci_host_bridge_of_msi_domain(struct pci_bus
*bus
) { return NULL
; }
2240 static inline int pci_parse_request_of_pci_ranges(struct device
*dev
,
2241 struct list_head
*resources
,
2242 struct resource
**bus_range
)
2246 #endif /* CONFIG_OF */
2248 static inline struct device_node
*
2249 pci_device_to_OF_node(const struct pci_dev
*pdev
)
2251 return pdev
? pdev
->dev
.of_node
: NULL
;
2254 static inline struct device_node
*pci_bus_to_OF_node(struct pci_bus
*bus
)
2256 return bus
? bus
->dev
.of_node
: NULL
;
2260 struct irq_domain
*pci_host_bridge_acpi_msi_domain(struct pci_bus
*bus
);
2263 pci_msi_register_fwnode_provider(struct fwnode_handle
*(*fn
)(struct device
*));
2265 static inline struct irq_domain
*
2266 pci_host_bridge_acpi_msi_domain(struct pci_bus
*bus
) { return NULL
; }
2270 static inline struct eeh_dev
*pci_dev_to_eeh_dev(struct pci_dev
*pdev
)
2272 return pdev
->dev
.archdata
.edev
;
2276 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn
);
2277 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
);
2278 int pci_for_each_dma_alias(struct pci_dev
*pdev
,
2279 int (*fn
)(struct pci_dev
*pdev
,
2280 u16 alias
, void *data
), void *data
);
2282 /* Helper functions for operation of device flag */
2283 static inline void pci_set_dev_assigned(struct pci_dev
*pdev
)
2285 pdev
->dev_flags
|= PCI_DEV_FLAGS_ASSIGNED
;
2287 static inline void pci_clear_dev_assigned(struct pci_dev
*pdev
)
2289 pdev
->dev_flags
&= ~PCI_DEV_FLAGS_ASSIGNED
;
2291 static inline bool pci_is_dev_assigned(struct pci_dev
*pdev
)
2293 return (pdev
->dev_flags
& PCI_DEV_FLAGS_ASSIGNED
) == PCI_DEV_FLAGS_ASSIGNED
;
2297 * pci_ari_enabled - query ARI forwarding status
2300 * Returns true if ARI forwarding is enabled.
2302 static inline bool pci_ari_enabled(struct pci_bus
*bus
)
2304 return bus
->self
&& bus
->self
->ari_enabled
;
2308 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2309 * @pdev: PCI device to check
2311 * Walk upwards from @pdev and check for each encountered bridge if it's part
2312 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2313 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2315 static inline bool pci_is_thunderbolt_attached(struct pci_dev
*pdev
)
2317 struct pci_dev
*parent
= pdev
;
2319 if (pdev
->is_thunderbolt
)
2322 while ((parent
= pci_upstream_bridge(parent
)))
2323 if (parent
->is_thunderbolt
)
2329 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2330 void pci_uevent_ers(struct pci_dev
*pdev
, enum pci_ers_result err_type
);
2333 /* Provide the legacy pci_dma_* API */
2334 #include <linux/pci-dma-compat.h>
2336 #define pci_printk(level, pdev, fmt, arg...) \
2337 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2339 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2340 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2341 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2342 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2343 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2344 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2345 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2346 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2348 #endif /* LINUX_PCI_H */