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1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
191 enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 AGP_UNKNOWN = 0x0c,
204 AGP_1X = 0x0d,
205 AGP_2X = 0x0e,
206 AGP_4X = 0x0f,
207 AGP_8X = 0x10,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
215 };
216
217 struct pci_cap_saved_state {
218 struct hlist_node next;
219 char cap_nr;
220 u32 data[0];
221 };
222
223 struct pcie_link_state;
224 struct pci_vpd;
225 struct pci_sriov;
226 struct pci_ats;
227
228 /*
229 * The pci_dev structure is used to describe PCI devices.
230 */
231 struct pci_dev {
232 struct list_head bus_list; /* node in per-bus list */
233 struct pci_bus *bus; /* bus this device is on */
234 struct pci_bus *subordinate; /* bus this device bridges to */
235
236 void *sysdata; /* hook for sys-specific extension */
237 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
238 struct pci_slot *slot; /* Physical slot this device is in */
239
240 unsigned int devfn; /* encoded device & function index */
241 unsigned short vendor;
242 unsigned short device;
243 unsigned short subsystem_vendor;
244 unsigned short subsystem_device;
245 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
246 u8 revision; /* PCI revision, low byte of class word */
247 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
248 u8 pcie_cap; /* PCI-E capability offset */
249 u8 pcie_type; /* PCI-E device/port type */
250 u8 rom_base_reg; /* which config register controls the ROM */
251 u8 pin; /* which interrupt pin this device uses */
252
253 struct pci_driver *driver; /* which driver has allocated this device */
254 u64 dma_mask; /* Mask of the bits of bus address this
255 device implements. Normally this is
256 0xffffffff. You only need to change
257 this if your device has broken DMA
258 or supports 64-bit transfers. */
259
260 struct device_dma_parameters dma_parms;
261
262 pci_power_t current_state; /* Current operating state. In ACPI-speak,
263 this is D0-D3, D0 being fully functional,
264 and D3 being off. */
265 int pm_cap; /* PM capability offset in the
266 configuration space */
267 unsigned int pme_support:5; /* Bitmask of states from which PME#
268 can be generated */
269 unsigned int pme_interrupt:1;
270 unsigned int d1_support:1; /* Low power state D1 is supported */
271 unsigned int d2_support:1; /* Low power state D2 is supported */
272 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
273 unsigned int wakeup_prepared:1;
274 unsigned int d3_delay; /* D3->D0 transition time in ms */
275
276 #ifdef CONFIG_PCIEASPM
277 struct pcie_link_state *link_state; /* ASPM link state. */
278 #endif
279
280 pci_channel_state_t error_state; /* current connectivity state */
281 struct device dev; /* Generic device interface */
282
283 int cfg_size; /* Size of configuration space */
284
285 /*
286 * Instead of touching interrupt line and base address registers
287 * directly, use the values stored here. They might be different!
288 */
289 unsigned int irq;
290 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
291
292 /* These fields are used by common fixups */
293 unsigned int transparent:1; /* Transparent PCI bridge */
294 unsigned int multifunction:1;/* Part of multi-function device */
295 /* keep track of device state */
296 unsigned int is_added:1;
297 unsigned int is_busmaster:1; /* device is busmaster */
298 unsigned int no_msi:1; /* device may not use msi */
299 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
300 unsigned int broken_parity_status:1; /* Device generates false positive parity */
301 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
302 unsigned int msi_enabled:1;
303 unsigned int msix_enabled:1;
304 unsigned int ari_enabled:1; /* ARI forwarding */
305 unsigned int is_managed:1;
306 unsigned int is_pcie:1; /* Obsolete. Will be removed.
307 Use pci_is_pcie() instead */
308 unsigned int needs_freset:1; /* Dev requires fundamental reset */
309 unsigned int state_saved:1;
310 unsigned int is_physfn:1;
311 unsigned int is_virtfn:1;
312 unsigned int reset_fn:1;
313 unsigned int is_hotplug_bridge:1;
314 unsigned int aer_firmware_first:1;
315 pci_dev_flags_t dev_flags;
316 atomic_t enable_cnt; /* pci_enable_device has been called */
317
318 u32 saved_config_space[16]; /* config space saved at suspend time */
319 struct hlist_head saved_cap_space;
320 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
321 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
322 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
323 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
324 #ifdef CONFIG_PCI_MSI
325 struct list_head msi_list;
326 #endif
327 struct pci_vpd *vpd;
328 #ifdef CONFIG_PCI_IOV
329 union {
330 struct pci_sriov *sriov; /* SR-IOV capability related */
331 struct pci_dev *physfn; /* the PF this VF is associated with */
332 };
333 struct pci_ats *ats; /* Address Translation Service */
334 #endif
335 };
336
337 extern struct pci_dev *alloc_pci_dev(void);
338
339 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
340 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
341 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
342
343 static inline int pci_channel_offline(struct pci_dev *pdev)
344 {
345 return (pdev->error_state != pci_channel_io_normal);
346 }
347
348 static inline struct pci_cap_saved_state *pci_find_saved_cap(
349 struct pci_dev *pci_dev, char cap)
350 {
351 struct pci_cap_saved_state *tmp;
352 struct hlist_node *pos;
353
354 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
355 if (tmp->cap_nr == cap)
356 return tmp;
357 }
358 return NULL;
359 }
360
361 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
362 struct pci_cap_saved_state *new_cap)
363 {
364 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
365 }
366
367 #ifndef PCI_BUS_NUM_RESOURCES
368 #define PCI_BUS_NUM_RESOURCES 16
369 #endif
370
371 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
372
373 struct pci_bus {
374 struct list_head node; /* node in list of buses */
375 struct pci_bus *parent; /* parent bus this bridge is on */
376 struct list_head children; /* list of child buses */
377 struct list_head devices; /* list of devices on this bus */
378 struct pci_dev *self; /* bridge device as seen by parent */
379 struct list_head slots; /* list of slots on this bus */
380 struct resource *resource[PCI_BUS_NUM_RESOURCES];
381 /* address space routed to this bus */
382
383 struct pci_ops *ops; /* configuration access functions */
384 void *sysdata; /* hook for sys-specific extension */
385 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
386
387 unsigned char number; /* bus number */
388 unsigned char primary; /* number of primary bridge */
389 unsigned char secondary; /* number of secondary bridge */
390 unsigned char subordinate; /* max number of subordinate buses */
391 unsigned char max_bus_speed; /* enum pci_bus_speed */
392 unsigned char cur_bus_speed; /* enum pci_bus_speed */
393
394 char name[48];
395
396 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
397 pci_bus_flags_t bus_flags; /* Inherited by child busses */
398 struct device *bridge;
399 struct device dev;
400 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
401 struct bin_attribute *legacy_mem; /* legacy mem */
402 unsigned int is_added:1;
403 };
404
405 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
406 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
407
408 /*
409 * Returns true if the pci bus is root (behind host-pci bridge),
410 * false otherwise
411 */
412 static inline bool pci_is_root_bus(struct pci_bus *pbus)
413 {
414 return !(pbus->parent);
415 }
416
417 #ifdef CONFIG_PCI_MSI
418 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
419 {
420 return pci_dev->msi_enabled || pci_dev->msix_enabled;
421 }
422 #else
423 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
424 #endif
425
426 /*
427 * Error values that may be returned by PCI functions.
428 */
429 #define PCIBIOS_SUCCESSFUL 0x00
430 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
431 #define PCIBIOS_BAD_VENDOR_ID 0x83
432 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
433 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
434 #define PCIBIOS_SET_FAILED 0x88
435 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
436
437 /* Low-level architecture-dependent routines */
438
439 struct pci_ops {
440 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
441 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
442 };
443
444 /*
445 * ACPI needs to be able to access PCI config space before we've done a
446 * PCI bus scan and created pci_bus structures.
447 */
448 extern int raw_pci_read(unsigned int domain, unsigned int bus,
449 unsigned int devfn, int reg, int len, u32 *val);
450 extern int raw_pci_write(unsigned int domain, unsigned int bus,
451 unsigned int devfn, int reg, int len, u32 val);
452
453 struct pci_bus_region {
454 resource_size_t start;
455 resource_size_t end;
456 };
457
458 struct pci_dynids {
459 spinlock_t lock; /* protects list, index */
460 struct list_head list; /* for IDs added at runtime */
461 };
462
463 /* ---------------------------------------------------------------- */
464 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
465 * a set of callbacks in struct pci_error_handlers, then that device driver
466 * will be notified of PCI bus errors, and will be driven to recovery
467 * when an error occurs.
468 */
469
470 typedef unsigned int __bitwise pci_ers_result_t;
471
472 enum pci_ers_result {
473 /* no result/none/not supported in device driver */
474 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
475
476 /* Device driver can recover without slot reset */
477 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
478
479 /* Device driver wants slot to be reset. */
480 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
481
482 /* Device has completely failed, is unrecoverable */
483 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
484
485 /* Device driver is fully recovered and operational */
486 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
487 };
488
489 /* PCI bus error event callbacks */
490 struct pci_error_handlers {
491 /* PCI bus error detected on this device */
492 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
493 enum pci_channel_state error);
494
495 /* MMIO has been re-enabled, but not DMA */
496 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
497
498 /* PCI Express link has been reset */
499 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
500
501 /* PCI slot has been reset */
502 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
503
504 /* Device driver may resume normal operations */
505 void (*resume)(struct pci_dev *dev);
506 };
507
508 /* ---------------------------------------------------------------- */
509
510 struct module;
511 struct pci_driver {
512 struct list_head node;
513 char *name;
514 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
515 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
516 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
517 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
518 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
519 int (*resume_early) (struct pci_dev *dev);
520 int (*resume) (struct pci_dev *dev); /* Device woken up */
521 void (*shutdown) (struct pci_dev *dev);
522 struct pci_error_handlers *err_handler;
523 struct device_driver driver;
524 struct pci_dynids dynids;
525 };
526
527 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
528
529 /**
530 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
531 * @_table: device table name
532 *
533 * This macro is used to create a struct pci_device_id array (a device table)
534 * in a generic manner.
535 */
536 #define DEFINE_PCI_DEVICE_TABLE(_table) \
537 const struct pci_device_id _table[] __devinitconst
538
539 /**
540 * PCI_DEVICE - macro used to describe a specific pci device
541 * @vend: the 16 bit PCI Vendor ID
542 * @dev: the 16 bit PCI Device ID
543 *
544 * This macro is used to create a struct pci_device_id that matches a
545 * specific device. The subvendor and subdevice fields will be set to
546 * PCI_ANY_ID.
547 */
548 #define PCI_DEVICE(vend,dev) \
549 .vendor = (vend), .device = (dev), \
550 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
551
552 /**
553 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
554 * @dev_class: the class, subclass, prog-if triple for this device
555 * @dev_class_mask: the class mask for this device
556 *
557 * This macro is used to create a struct pci_device_id that matches a
558 * specific PCI class. The vendor, device, subvendor, and subdevice
559 * fields will be set to PCI_ANY_ID.
560 */
561 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
562 .class = (dev_class), .class_mask = (dev_class_mask), \
563 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
564 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
565
566 /**
567 * PCI_VDEVICE - macro used to describe a specific pci device in short form
568 * @vendor: the vendor name
569 * @device: the 16 bit PCI Device ID
570 *
571 * This macro is used to create a struct pci_device_id that matches a
572 * specific PCI device. The subvendor, and subdevice fields will be set
573 * to PCI_ANY_ID. The macro allows the next field to follow as the device
574 * private data.
575 */
576
577 #define PCI_VDEVICE(vendor, device) \
578 PCI_VENDOR_ID_##vendor, (device), \
579 PCI_ANY_ID, PCI_ANY_ID, 0, 0
580
581 /* these external functions are only available when PCI support is enabled */
582 #ifdef CONFIG_PCI
583
584 extern struct bus_type pci_bus_type;
585
586 /* Do NOT directly access these two variables, unless you are arch specific pci
587 * code, or pci core code. */
588 extern struct list_head pci_root_buses; /* list of all known PCI buses */
589 /* Some device drivers need know if pci is initiated */
590 extern int no_pci_devices(void);
591
592 void pcibios_fixup_bus(struct pci_bus *);
593 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
594 char *pcibios_setup(char *str);
595
596 /* Used only when drivers/pci/setup.c is used */
597 resource_size_t pcibios_align_resource(void *, const struct resource *,
598 resource_size_t,
599 resource_size_t);
600 void pcibios_update_irq(struct pci_dev *, int irq);
601
602 /* Weak but can be overriden by arch */
603 void pci_fixup_cardbus(struct pci_bus *);
604
605 /* Generic PCI functions used internally */
606
607 extern struct pci_bus *pci_find_bus(int domain, int busnr);
608 void pci_bus_add_devices(const struct pci_bus *bus);
609 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
610 struct pci_ops *ops, void *sysdata);
611 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
612 void *sysdata)
613 {
614 struct pci_bus *root_bus;
615 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
616 if (root_bus)
617 pci_bus_add_devices(root_bus);
618 return root_bus;
619 }
620 struct pci_bus *pci_create_bus(struct device *parent, int bus,
621 struct pci_ops *ops, void *sysdata);
622 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
623 int busnr);
624 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
625 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
626 const char *name,
627 struct hotplug_slot *hotplug);
628 void pci_destroy_slot(struct pci_slot *slot);
629 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
630 int pci_scan_slot(struct pci_bus *bus, int devfn);
631 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
632 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
633 unsigned int pci_scan_child_bus(struct pci_bus *bus);
634 int __must_check pci_bus_add_device(struct pci_dev *dev);
635 void pci_read_bridge_bases(struct pci_bus *child);
636 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
637 struct resource *res);
638 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
639 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
640 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
641 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
642 extern void pci_dev_put(struct pci_dev *dev);
643 extern void pci_remove_bus(struct pci_bus *b);
644 extern void pci_remove_bus_device(struct pci_dev *dev);
645 extern void pci_stop_bus_device(struct pci_dev *dev);
646 void pci_setup_cardbus(struct pci_bus *bus);
647 extern void pci_sort_breadthfirst(void);
648
649 /* Generic PCI functions exported to card drivers */
650
651 enum pci_lost_interrupt_reason {
652 PCI_LOST_IRQ_NO_INFORMATION = 0,
653 PCI_LOST_IRQ_DISABLE_MSI,
654 PCI_LOST_IRQ_DISABLE_MSIX,
655 PCI_LOST_IRQ_DISABLE_ACPI,
656 };
657 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
658 int pci_find_capability(struct pci_dev *dev, int cap);
659 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
660 int pci_find_ext_capability(struct pci_dev *dev, int cap);
661 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
662 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
663 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
664
665 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
666 struct pci_dev *from);
667 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
668 unsigned int ss_vendor, unsigned int ss_device,
669 struct pci_dev *from);
670 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
671 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
672 unsigned int devfn);
673 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
674 unsigned int devfn)
675 {
676 return pci_get_domain_bus_and_slot(0, bus, devfn);
677 }
678 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
679 int pci_dev_present(const struct pci_device_id *ids);
680
681 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
682 int where, u8 *val);
683 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
684 int where, u16 *val);
685 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
686 int where, u32 *val);
687 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
688 int where, u8 val);
689 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
690 int where, u16 val);
691 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
692 int where, u32 val);
693 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
694
695 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
696 {
697 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
698 }
699 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
700 {
701 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
702 }
703 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
704 u32 *val)
705 {
706 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
707 }
708 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
709 {
710 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
711 }
712 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
713 {
714 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
715 }
716 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
717 u32 val)
718 {
719 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
720 }
721
722 int __must_check pci_enable_device(struct pci_dev *dev);
723 int __must_check pci_enable_device_io(struct pci_dev *dev);
724 int __must_check pci_enable_device_mem(struct pci_dev *dev);
725 int __must_check pci_reenable_device(struct pci_dev *);
726 int __must_check pcim_enable_device(struct pci_dev *pdev);
727 void pcim_pin_device(struct pci_dev *pdev);
728
729 static inline int pci_is_enabled(struct pci_dev *pdev)
730 {
731 return (atomic_read(&pdev->enable_cnt) > 0);
732 }
733
734 static inline int pci_is_managed(struct pci_dev *pdev)
735 {
736 return pdev->is_managed;
737 }
738
739 void pci_disable_device(struct pci_dev *dev);
740 void pci_set_master(struct pci_dev *dev);
741 void pci_clear_master(struct pci_dev *dev);
742 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
743 int pci_set_cacheline_size(struct pci_dev *dev);
744 #define HAVE_PCI_SET_MWI
745 int __must_check pci_set_mwi(struct pci_dev *dev);
746 int pci_try_set_mwi(struct pci_dev *dev);
747 void pci_clear_mwi(struct pci_dev *dev);
748 void pci_intx(struct pci_dev *dev, int enable);
749 void pci_msi_off(struct pci_dev *dev);
750 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
751 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
752 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
753 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
754 int pcix_get_max_mmrbc(struct pci_dev *dev);
755 int pcix_get_mmrbc(struct pci_dev *dev);
756 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
757 int pcie_get_readrq(struct pci_dev *dev);
758 int pcie_set_readrq(struct pci_dev *dev, int rq);
759 int __pci_reset_function(struct pci_dev *dev);
760 int pci_reset_function(struct pci_dev *dev);
761 void pci_update_resource(struct pci_dev *dev, int resno);
762 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
763 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
764
765 /* ROM control related routines */
766 int pci_enable_rom(struct pci_dev *pdev);
767 void pci_disable_rom(struct pci_dev *pdev);
768 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
769 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
770 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
771
772 /* Power management related routines */
773 int pci_save_state(struct pci_dev *dev);
774 int pci_restore_state(struct pci_dev *dev);
775 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
776 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
777 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
778 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
779 void pci_pme_active(struct pci_dev *dev, bool enable);
780 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
781 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
782 pci_power_t pci_target_state(struct pci_dev *dev);
783 int pci_prepare_to_sleep(struct pci_dev *dev);
784 int pci_back_from_sleep(struct pci_dev *dev);
785 bool pci_dev_run_wake(struct pci_dev *dev);
786
787 /* For use by arch with custom probe code */
788 void set_pcie_port_type(struct pci_dev *pdev);
789 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
790
791 /* Functions for PCI Hotplug drivers to use */
792 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
793 #ifdef CONFIG_HOTPLUG
794 unsigned int pci_rescan_bus(struct pci_bus *bus);
795 #endif
796
797 /* Vital product data routines */
798 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
799 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
800 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
801
802 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
803 void pci_bus_assign_resources(const struct pci_bus *bus);
804 void pci_bus_size_bridges(struct pci_bus *bus);
805 int pci_claim_resource(struct pci_dev *, int);
806 void pci_assign_unassigned_resources(void);
807 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
808 void pdev_enable_device(struct pci_dev *);
809 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
810 int pci_enable_resources(struct pci_dev *, int mask);
811 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
812 int (*)(struct pci_dev *, u8, u8));
813 #define HAVE_PCI_REQ_REGIONS 2
814 int __must_check pci_request_regions(struct pci_dev *, const char *);
815 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
816 void pci_release_regions(struct pci_dev *);
817 int __must_check pci_request_region(struct pci_dev *, int, const char *);
818 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
819 void pci_release_region(struct pci_dev *, int);
820 int pci_request_selected_regions(struct pci_dev *, int, const char *);
821 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
822 void pci_release_selected_regions(struct pci_dev *, int);
823
824 /* drivers/pci/bus.c */
825 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
826 struct resource *res, resource_size_t size,
827 resource_size_t align, resource_size_t min,
828 unsigned int type_mask,
829 resource_size_t (*alignf)(void *,
830 const struct resource *,
831 resource_size_t,
832 resource_size_t),
833 void *alignf_data);
834 void pci_enable_bridges(struct pci_bus *bus);
835
836 /* Proper probing supporting hot-pluggable devices */
837 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
838 const char *mod_name);
839
840 /*
841 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
842 */
843 #define pci_register_driver(driver) \
844 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
845
846 void pci_unregister_driver(struct pci_driver *dev);
847 void pci_remove_behind_bridge(struct pci_dev *dev);
848 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
849 int pci_add_dynid(struct pci_driver *drv,
850 unsigned int vendor, unsigned int device,
851 unsigned int subvendor, unsigned int subdevice,
852 unsigned int class, unsigned int class_mask,
853 unsigned long driver_data);
854 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
855 struct pci_dev *dev);
856 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
857 int pass);
858
859 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
860 void *userdata);
861 int pci_cfg_space_size_ext(struct pci_dev *dev);
862 int pci_cfg_space_size(struct pci_dev *dev);
863 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
864
865 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
866 unsigned int command_bits, bool change_bridge);
867 /* kmem_cache style wrapper around pci_alloc_consistent() */
868
869 #include <linux/dmapool.h>
870
871 #define pci_pool dma_pool
872 #define pci_pool_create(name, pdev, size, align, allocation) \
873 dma_pool_create(name, &pdev->dev, size, align, allocation)
874 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
875 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
876 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
877
878 enum pci_dma_burst_strategy {
879 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
880 strategy_parameter is N/A */
881 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
882 byte boundaries */
883 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
884 strategy_parameter byte boundaries */
885 };
886
887 struct msix_entry {
888 u32 vector; /* kernel uses to write allocated vector */
889 u16 entry; /* driver uses to specify entry, OS writes */
890 };
891
892
893 #ifndef CONFIG_PCI_MSI
894 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
895 {
896 return -1;
897 }
898
899 static inline void pci_msi_shutdown(struct pci_dev *dev)
900 { }
901 static inline void pci_disable_msi(struct pci_dev *dev)
902 { }
903
904 static inline int pci_msix_table_size(struct pci_dev *dev)
905 {
906 return 0;
907 }
908 static inline int pci_enable_msix(struct pci_dev *dev,
909 struct msix_entry *entries, int nvec)
910 {
911 return -1;
912 }
913
914 static inline void pci_msix_shutdown(struct pci_dev *dev)
915 { }
916 static inline void pci_disable_msix(struct pci_dev *dev)
917 { }
918
919 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
920 { }
921
922 static inline void pci_restore_msi_state(struct pci_dev *dev)
923 { }
924 static inline int pci_msi_enabled(void)
925 {
926 return 0;
927 }
928 #else
929 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
930 extern void pci_msi_shutdown(struct pci_dev *dev);
931 extern void pci_disable_msi(struct pci_dev *dev);
932 extern int pci_msix_table_size(struct pci_dev *dev);
933 extern int pci_enable_msix(struct pci_dev *dev,
934 struct msix_entry *entries, int nvec);
935 extern void pci_msix_shutdown(struct pci_dev *dev);
936 extern void pci_disable_msix(struct pci_dev *dev);
937 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
938 extern void pci_restore_msi_state(struct pci_dev *dev);
939 extern int pci_msi_enabled(void);
940 #endif
941
942 #ifndef CONFIG_PCIEASPM
943 static inline int pcie_aspm_enabled(void)
944 {
945 return 0;
946 }
947 #else
948 extern int pcie_aspm_enabled(void);
949 #endif
950
951 #ifndef CONFIG_PCIE_ECRC
952 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
953 {
954 return;
955 }
956 static inline void pcie_ecrc_get_policy(char *str) {};
957 #else
958 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
959 extern void pcie_ecrc_get_policy(char *str);
960 #endif
961
962 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
963
964 #ifdef CONFIG_HT_IRQ
965 /* The functions a driver should call */
966 int ht_create_irq(struct pci_dev *dev, int idx);
967 void ht_destroy_irq(unsigned int irq);
968 #endif /* CONFIG_HT_IRQ */
969
970 extern void pci_block_user_cfg_access(struct pci_dev *dev);
971 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
972
973 /*
974 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
975 * a PCI domain is defined to be a set of PCI busses which share
976 * configuration space.
977 */
978 #ifdef CONFIG_PCI_DOMAINS
979 extern int pci_domains_supported;
980 #else
981 enum { pci_domains_supported = 0 };
982 static inline int pci_domain_nr(struct pci_bus *bus)
983 {
984 return 0;
985 }
986
987 static inline int pci_proc_domain(struct pci_bus *bus)
988 {
989 return 0;
990 }
991 #endif /* CONFIG_PCI_DOMAINS */
992
993 #else /* CONFIG_PCI is not enabled */
994
995 /*
996 * If the system does not have PCI, clearly these return errors. Define
997 * these as simple inline functions to avoid hair in drivers.
998 */
999
1000 #define _PCI_NOP(o, s, t) \
1001 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1002 int where, t val) \
1003 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1004
1005 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1006 _PCI_NOP(o, word, u16 x) \
1007 _PCI_NOP(o, dword, u32 x)
1008 _PCI_NOP_ALL(read, *)
1009 _PCI_NOP_ALL(write,)
1010
1011 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1012 unsigned int device,
1013 struct pci_dev *from)
1014 {
1015 return NULL;
1016 }
1017
1018 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1019 unsigned int device,
1020 unsigned int ss_vendor,
1021 unsigned int ss_device,
1022 struct pci_dev *from)
1023 {
1024 return NULL;
1025 }
1026
1027 static inline struct pci_dev *pci_get_class(unsigned int class,
1028 struct pci_dev *from)
1029 {
1030 return NULL;
1031 }
1032
1033 #define pci_dev_present(ids) (0)
1034 #define no_pci_devices() (1)
1035 #define pci_dev_put(dev) do { } while (0)
1036
1037 static inline void pci_set_master(struct pci_dev *dev)
1038 { }
1039
1040 static inline int pci_enable_device(struct pci_dev *dev)
1041 {
1042 return -EIO;
1043 }
1044
1045 static inline void pci_disable_device(struct pci_dev *dev)
1046 { }
1047
1048 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1049 {
1050 return -EIO;
1051 }
1052
1053 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1054 {
1055 return -EIO;
1056 }
1057
1058 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1059 unsigned int size)
1060 {
1061 return -EIO;
1062 }
1063
1064 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1065 unsigned long mask)
1066 {
1067 return -EIO;
1068 }
1069
1070 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1071 {
1072 return -EBUSY;
1073 }
1074
1075 static inline int __pci_register_driver(struct pci_driver *drv,
1076 struct module *owner)
1077 {
1078 return 0;
1079 }
1080
1081 static inline int pci_register_driver(struct pci_driver *drv)
1082 {
1083 return 0;
1084 }
1085
1086 static inline void pci_unregister_driver(struct pci_driver *drv)
1087 { }
1088
1089 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1090 {
1091 return 0;
1092 }
1093
1094 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1095 int cap)
1096 {
1097 return 0;
1098 }
1099
1100 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1101 {
1102 return 0;
1103 }
1104
1105 /* Power management related routines */
1106 static inline int pci_save_state(struct pci_dev *dev)
1107 {
1108 return 0;
1109 }
1110
1111 static inline int pci_restore_state(struct pci_dev *dev)
1112 {
1113 return 0;
1114 }
1115
1116 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1117 {
1118 return 0;
1119 }
1120
1121 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1122 pm_message_t state)
1123 {
1124 return PCI_D0;
1125 }
1126
1127 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1128 int enable)
1129 {
1130 return 0;
1131 }
1132
1133 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1134 {
1135 return -EIO;
1136 }
1137
1138 static inline void pci_release_regions(struct pci_dev *dev)
1139 { }
1140
1141 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1142
1143 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1144 { }
1145
1146 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1147 { }
1148
1149 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1150 { return NULL; }
1151
1152 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1153 unsigned int devfn)
1154 { return NULL; }
1155
1156 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1157 unsigned int devfn)
1158 { return NULL; }
1159
1160 #endif /* CONFIG_PCI */
1161
1162 /* Include architecture-dependent settings and functions */
1163
1164 #include <asm/pci.h>
1165
1166 #ifndef PCIBIOS_MAX_MEM_32
1167 #define PCIBIOS_MAX_MEM_32 (-1)
1168 #endif
1169
1170 /* these helpers provide future and backwards compatibility
1171 * for accessing popular PCI BAR info */
1172 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1173 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1174 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1175 #define pci_resource_len(dev,bar) \
1176 ((pci_resource_start((dev), (bar)) == 0 && \
1177 pci_resource_end((dev), (bar)) == \
1178 pci_resource_start((dev), (bar))) ? 0 : \
1179 \
1180 (pci_resource_end((dev), (bar)) - \
1181 pci_resource_start((dev), (bar)) + 1))
1182
1183 /* Similar to the helpers above, these manipulate per-pci_dev
1184 * driver-specific data. They are really just a wrapper around
1185 * the generic device structure functions of these calls.
1186 */
1187 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1188 {
1189 return dev_get_drvdata(&pdev->dev);
1190 }
1191
1192 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1193 {
1194 dev_set_drvdata(&pdev->dev, data);
1195 }
1196
1197 /* If you want to know what to call your pci_dev, ask this function.
1198 * Again, it's a wrapper around the generic device.
1199 */
1200 static inline const char *pci_name(const struct pci_dev *pdev)
1201 {
1202 return dev_name(&pdev->dev);
1203 }
1204
1205
1206 /* Some archs don't want to expose struct resource to userland as-is
1207 * in sysfs and /proc
1208 */
1209 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1210 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1211 const struct resource *rsrc, resource_size_t *start,
1212 resource_size_t *end)
1213 {
1214 *start = rsrc->start;
1215 *end = rsrc->end;
1216 }
1217 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1218
1219
1220 /*
1221 * The world is not perfect and supplies us with broken PCI devices.
1222 * For at least a part of these bugs we need a work-around, so both
1223 * generic (drivers/pci/quirks.c) and per-architecture code can define
1224 * fixup hooks to be called for particular buggy devices.
1225 */
1226
1227 struct pci_fixup {
1228 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1229 void (*hook)(struct pci_dev *dev);
1230 };
1231
1232 enum pci_fixup_pass {
1233 pci_fixup_early, /* Before probing BARs */
1234 pci_fixup_header, /* After reading configuration header */
1235 pci_fixup_final, /* Final phase of device fixups */
1236 pci_fixup_enable, /* pci_enable_device() time */
1237 pci_fixup_resume, /* pci_device_resume() */
1238 pci_fixup_suspend, /* pci_device_suspend */
1239 pci_fixup_resume_early, /* pci_device_resume_early() */
1240 };
1241
1242 /* Anonymous variables would be nice... */
1243 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1244 static const struct pci_fixup __pci_fixup_##name __used \
1245 __attribute__((__section__(#section))) = { vendor, device, hook };
1246 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1247 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1248 vendor##device##hook, vendor, device, hook)
1249 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1250 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1251 vendor##device##hook, vendor, device, hook)
1252 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1253 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1254 vendor##device##hook, vendor, device, hook)
1255 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1256 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1257 vendor##device##hook, vendor, device, hook)
1258 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1259 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1260 resume##vendor##device##hook, vendor, device, hook)
1261 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1262 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1263 resume_early##vendor##device##hook, vendor, device, hook)
1264 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1265 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1266 suspend##vendor##device##hook, vendor, device, hook)
1267
1268 #ifdef CONFIG_PCI_QUIRKS
1269 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1270 #else
1271 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1272 struct pci_dev *dev) {}
1273 #endif
1274
1275 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1276 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1277 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1278 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1279 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1280 const char *name);
1281 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1282
1283 extern int pci_pci_problems;
1284 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1285 #define PCIPCI_TRITON 2
1286 #define PCIPCI_NATOMA 4
1287 #define PCIPCI_VIAETBF 8
1288 #define PCIPCI_VSFX 16
1289 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1290 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1291
1292 extern unsigned long pci_cardbus_io_size;
1293 extern unsigned long pci_cardbus_mem_size;
1294 extern u8 __devinitdata pci_dfl_cache_line_size;
1295 extern u8 pci_cache_line_size;
1296
1297 extern unsigned long pci_hotplug_io_size;
1298 extern unsigned long pci_hotplug_mem_size;
1299
1300 int pcibios_add_platform_entries(struct pci_dev *dev);
1301 void pcibios_disable_device(struct pci_dev *dev);
1302 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1303 enum pcie_reset_state state);
1304
1305 #ifdef CONFIG_PCI_MMCONFIG
1306 extern void __init pci_mmcfg_early_init(void);
1307 extern void __init pci_mmcfg_late_init(void);
1308 #else
1309 static inline void pci_mmcfg_early_init(void) { }
1310 static inline void pci_mmcfg_late_init(void) { }
1311 #endif
1312
1313 int pci_ext_cfg_avail(struct pci_dev *dev);
1314
1315 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1316
1317 #ifdef CONFIG_PCI_IOV
1318 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1319 extern void pci_disable_sriov(struct pci_dev *dev);
1320 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1321 #else
1322 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1323 {
1324 return -ENODEV;
1325 }
1326 static inline void pci_disable_sriov(struct pci_dev *dev)
1327 {
1328 }
1329 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1330 {
1331 return IRQ_NONE;
1332 }
1333 #endif
1334
1335 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1336 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1337 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1338 #endif
1339
1340 /**
1341 * pci_pcie_cap - get the saved PCIe capability offset
1342 * @dev: PCI device
1343 *
1344 * PCIe capability offset is calculated at PCI device initialization
1345 * time and saved in the data structure. This function returns saved
1346 * PCIe capability offset. Using this instead of pci_find_capability()
1347 * reduces unnecessary search in the PCI configuration space. If you
1348 * need to calculate PCIe capability offset from raw device for some
1349 * reasons, please use pci_find_capability() instead.
1350 */
1351 static inline int pci_pcie_cap(struct pci_dev *dev)
1352 {
1353 return dev->pcie_cap;
1354 }
1355
1356 /**
1357 * pci_is_pcie - check if the PCI device is PCI Express capable
1358 * @dev: PCI device
1359 *
1360 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1361 */
1362 static inline bool pci_is_pcie(struct pci_dev *dev)
1363 {
1364 return !!pci_pcie_cap(dev);
1365 }
1366
1367 void pci_request_acs(void);
1368
1369 #endif /* __KERNEL__ */
1370 #endif /* LINUX_PCI_H */
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