1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus
*bus
; /* The bus this slot is on */
58 struct list_head list
; /* node in list of slots on this bus */
59 struct hotplug_slot
*hotplug
; /* Hotplug info (migrate over time) */
60 unsigned char number
; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot
*slot
)
66 return kobject_name(&slot
->kobj
);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
76 * For PCI devices, the region numbers are assigned this way:
79 /* #0-5: standard PCI resources */
81 PCI_STD_RESOURCE_END
= 5,
83 /* #6: expansion ROM resource */
86 /* device specific resources */
89 PCI_IOV_RESOURCE_END
= PCI_IOV_RESOURCES
+ PCI_SRIOV_NUM_BARS
- 1,
92 /* resources assigned to buses behind the bridge */
93 #define PCI_BRIDGE_RESOURCE_NUM 4
96 PCI_BRIDGE_RESOURCE_END
= PCI_BRIDGE_RESOURCES
+
97 PCI_BRIDGE_RESOURCE_NUM
- 1,
99 /* total resources associated with a PCI device */
102 /* preserve this for compatibility */
103 DEVICE_COUNT_RESOURCE
= PCI_NUM_RESOURCES
,
107 * enum pci_interrupt_pin - PCI INTx interrupt values
108 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
109 * @PCI_INTERRUPT_INTA: PCI INTA pin
110 * @PCI_INTERRUPT_INTB: PCI INTB pin
111 * @PCI_INTERRUPT_INTC: PCI INTC pin
112 * @PCI_INTERRUPT_INTD: PCI INTD pin
114 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
115 * PCI_INTERRUPT_PIN register.
117 enum pci_interrupt_pin
{
118 PCI_INTERRUPT_UNKNOWN
,
125 /* The number of legacy PCI INTx interrupts */
126 #define PCI_NUM_INTX 4
129 * pci_power_t values must match the bits in the Capabilities PME_Support
130 * and Control/Status PowerState fields in the Power Management capability.
132 typedef int __bitwise pci_power_t
;
134 #define PCI_D0 ((pci_power_t __force) 0)
135 #define PCI_D1 ((pci_power_t __force) 1)
136 #define PCI_D2 ((pci_power_t __force) 2)
137 #define PCI_D3hot ((pci_power_t __force) 3)
138 #define PCI_D3cold ((pci_power_t __force) 4)
139 #define PCI_UNKNOWN ((pci_power_t __force) 5)
140 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
142 /* Remember to update this when the list above changes! */
143 extern const char *pci_power_names
[];
145 static inline const char *pci_power_name(pci_power_t state
)
147 return pci_power_names
[1 + (__force
int) state
];
150 #define PCI_PM_D2_DELAY 200
151 #define PCI_PM_D3_WAIT 10
152 #define PCI_PM_D3COLD_WAIT 100
153 #define PCI_PM_BUS_WAIT 50
155 /** The pci_channel state describes connectivity between the CPU and
156 * the pci device. If some PCI bus between here and the pci device
157 * has crashed or locked up, this info is reflected here.
159 typedef unsigned int __bitwise pci_channel_state_t
;
161 enum pci_channel_state
{
162 /* I/O channel is in normal state */
163 pci_channel_io_normal
= (__force pci_channel_state_t
) 1,
165 /* I/O to channel is blocked */
166 pci_channel_io_frozen
= (__force pci_channel_state_t
) 2,
168 /* PCI card is dead */
169 pci_channel_io_perm_failure
= (__force pci_channel_state_t
) 3,
172 typedef unsigned int __bitwise pcie_reset_state_t
;
174 enum pcie_reset_state
{
175 /* Reset is NOT asserted (Use to deassert reset) */
176 pcie_deassert_reset
= (__force pcie_reset_state_t
) 1,
178 /* Use #PERST to reset PCIe device */
179 pcie_warm_reset
= (__force pcie_reset_state_t
) 2,
181 /* Use PCIe Hot Reset to reset device */
182 pcie_hot_reset
= (__force pcie_reset_state_t
) 3
185 typedef unsigned short __bitwise pci_dev_flags_t
;
187 /* INTX_DISABLE in PCI_COMMAND register disables MSI
190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
= (__force pci_dev_flags_t
) (1 << 0),
191 /* Device configuration is irrevocably lost if disabled into D3 */
192 PCI_DEV_FLAGS_NO_D3
= (__force pci_dev_flags_t
) (1 << 1),
193 /* Provide indication device is assigned by a Virtual Machine Manager */
194 PCI_DEV_FLAGS_ASSIGNED
= (__force pci_dev_flags_t
) (1 << 2),
195 /* Flag for quirk use to store if quirk-specific ACS is enabled */
196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
= (__force pci_dev_flags_t
) (1 << 3),
197 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
= (__force pci_dev_flags_t
) (1 << 5),
199 /* Do not use bus resets for device */
200 PCI_DEV_FLAGS_NO_BUS_RESET
= (__force pci_dev_flags_t
) (1 << 6),
201 /* Do not use PM reset even if device advertises NoSoftRst- */
202 PCI_DEV_FLAGS_NO_PM_RESET
= (__force pci_dev_flags_t
) (1 << 7),
203 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0
= (__force pci_dev_flags_t
) (1 << 8),
205 /* a non-root bridge where translation occurs, stop alias search here */
206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
= (__force pci_dev_flags_t
) (1 << 9),
207 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET
= (__force pci_dev_flags_t
) (1 << 10),
209 /* Don't use Relaxed Ordering for TLPs directed at this device */
210 PCI_DEV_FLAGS_NO_RELAXED_ORDERING
= (__force pci_dev_flags_t
) (1 << 11),
213 enum pci_irq_reroute_variant
{
214 INTEL_IRQ_REROUTE_VARIANT
= 1,
215 MAX_IRQ_REROUTE_VARIANTS
= 3
218 typedef unsigned short __bitwise pci_bus_flags_t
;
220 PCI_BUS_FLAGS_NO_MSI
= (__force pci_bus_flags_t
) 1,
221 PCI_BUS_FLAGS_NO_MMRBC
= (__force pci_bus_flags_t
) 2,
222 PCI_BUS_FLAGS_NO_AERSID
= (__force pci_bus_flags_t
) 4,
225 /* These values come from the PCI Express Spec */
226 enum pcie_link_width
{
227 PCIE_LNK_WIDTH_RESRV
= 0x00,
235 PCIE_LNK_WIDTH_UNKNOWN
= 0xFF,
238 /* Based on the PCI Hotplug Spec, but some values are made up by us */
240 PCI_SPEED_33MHz
= 0x00,
241 PCI_SPEED_66MHz
= 0x01,
242 PCI_SPEED_66MHz_PCIX
= 0x02,
243 PCI_SPEED_100MHz_PCIX
= 0x03,
244 PCI_SPEED_133MHz_PCIX
= 0x04,
245 PCI_SPEED_66MHz_PCIX_ECC
= 0x05,
246 PCI_SPEED_100MHz_PCIX_ECC
= 0x06,
247 PCI_SPEED_133MHz_PCIX_ECC
= 0x07,
248 PCI_SPEED_66MHz_PCIX_266
= 0x09,
249 PCI_SPEED_100MHz_PCIX_266
= 0x0a,
250 PCI_SPEED_133MHz_PCIX_266
= 0x0b,
256 PCI_SPEED_66MHz_PCIX_533
= 0x11,
257 PCI_SPEED_100MHz_PCIX_533
= 0x12,
258 PCI_SPEED_133MHz_PCIX_533
= 0x13,
259 PCIE_SPEED_2_5GT
= 0x14,
260 PCIE_SPEED_5_0GT
= 0x15,
261 PCIE_SPEED_8_0GT
= 0x16,
262 PCIE_SPEED_16_0GT
= 0x17,
263 PCI_SPEED_UNKNOWN
= 0xff,
266 struct pci_cap_saved_data
{
273 struct pci_cap_saved_state
{
274 struct hlist_node next
;
275 struct pci_cap_saved_data cap
;
279 struct pcie_link_state
;
285 * The pci_dev structure is used to describe PCI devices.
288 struct list_head bus_list
; /* node in per-bus list */
289 struct pci_bus
*bus
; /* bus this device is on */
290 struct pci_bus
*subordinate
; /* bus this device bridges to */
292 void *sysdata
; /* hook for sys-specific extension */
293 struct proc_dir_entry
*procent
; /* device entry in /proc/bus/pci */
294 struct pci_slot
*slot
; /* Physical slot this device is in */
296 unsigned int devfn
; /* encoded device & function index */
297 unsigned short vendor
;
298 unsigned short device
;
299 unsigned short subsystem_vendor
;
300 unsigned short subsystem_device
;
301 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
302 u8 revision
; /* PCI revision, low byte of class word */
303 u8 hdr_type
; /* PCI header type (`multi' flag masked out) */
304 #ifdef CONFIG_PCIEAER
305 u16 aer_cap
; /* AER capability offset */
307 u8 pcie_cap
; /* PCIe capability offset */
308 u8 msi_cap
; /* MSI capability offset */
309 u8 msix_cap
; /* MSI-X capability offset */
310 u8 pcie_mpss
:3; /* PCIe Max Payload Size Supported */
311 u8 rom_base_reg
; /* which config register controls the ROM */
312 u8 pin
; /* which interrupt pin this device uses */
313 u16 pcie_flags_reg
; /* cached PCIe Capabilities Register */
314 unsigned long *dma_alias_mask
;/* mask of enabled devfn aliases */
316 struct pci_driver
*driver
; /* which driver has allocated this device */
317 u64 dma_mask
; /* Mask of the bits of bus address this
318 device implements. Normally this is
319 0xffffffff. You only need to change
320 this if your device has broken DMA
321 or supports 64-bit transfers. */
323 struct device_dma_parameters dma_parms
;
325 pci_power_t current_state
; /* Current operating state. In ACPI-speak,
326 this is D0-D3, D0 being fully functional,
328 u8 pm_cap
; /* PM capability offset */
329 unsigned int pme_support
:5; /* Bitmask of states from which PME#
331 unsigned int pme_poll
:1; /* Poll device's PME status bit */
332 unsigned int d1_support
:1; /* Low power state D1 is supported */
333 unsigned int d2_support
:1; /* Low power state D2 is supported */
334 unsigned int no_d1d2
:1; /* D1 and D2 are forbidden */
335 unsigned int no_d3cold
:1; /* D3cold is forbidden */
336 unsigned int bridge_d3
:1; /* Allow D3 for bridge */
337 unsigned int d3cold_allowed
:1; /* D3cold is allowed by user */
338 unsigned int mmio_always_on
:1; /* disallow turning off io/mem
339 decoding during bar sizing */
340 unsigned int wakeup_prepared
:1;
341 unsigned int runtime_d3cold
:1; /* whether go through runtime
342 D3cold, not set for devices
343 powered on/off by the
344 corresponding bridge */
345 unsigned int ignore_hotplug
:1; /* Ignore hotplug events */
346 unsigned int hotplug_user_indicators
:1; /* SlotCtl indicators
347 controlled exclusively by
349 unsigned int d3_delay
; /* D3->D0 transition time in ms */
350 unsigned int d3cold_delay
; /* D3cold->D0 transition time in ms */
352 #ifdef CONFIG_PCIEASPM
353 struct pcie_link_state
*link_state
; /* ASPM link state */
354 unsigned int ltr_path
:1; /* Latency Tolerance Reporting
355 supported from root to here */
358 pci_channel_state_t error_state
; /* current connectivity state */
359 struct device dev
; /* Generic device interface */
361 int cfg_size
; /* Size of configuration space */
364 * Instead of touching interrupt line and base address registers
365 * directly, use the values stored here. They might be different!
368 struct resource resource
[DEVICE_COUNT_RESOURCE
]; /* I/O and memory regions + expansion ROMs */
370 bool match_driver
; /* Skip attaching driver */
371 /* These fields are used by common fixups */
372 unsigned int transparent
:1; /* Subtractive decode PCI bridge */
373 unsigned int multifunction
:1;/* Part of multi-function device */
374 /* keep track of device state */
375 unsigned int is_added
:1;
376 unsigned int is_busmaster
:1; /* device is busmaster */
377 unsigned int no_msi
:1; /* device may not use msi */
378 unsigned int no_64bit_msi
:1; /* device may only use 32-bit MSIs */
379 unsigned int block_cfg_access
:1; /* config space access is blocked */
380 unsigned int broken_parity_status
:1; /* Device generates false positive parity */
381 unsigned int irq_reroute_variant
:2; /* device needs IRQ rerouting variant */
382 unsigned int msi_enabled
:1;
383 unsigned int msix_enabled
:1;
384 unsigned int ari_enabled
:1; /* ARI forwarding */
385 unsigned int ats_enabled
:1; /* Address Translation Service */
386 unsigned int pasid_enabled
:1; /* Process Address Space ID */
387 unsigned int pri_enabled
:1; /* Page Request Interface */
388 unsigned int is_managed
:1;
389 unsigned int needs_freset
:1; /* Dev requires fundamental reset */
390 unsigned int state_saved
:1;
391 unsigned int is_physfn
:1;
392 unsigned int is_virtfn
:1;
393 unsigned int reset_fn
:1;
394 unsigned int is_hotplug_bridge
:1;
395 unsigned int is_thunderbolt
:1; /* Thunderbolt controller */
396 unsigned int __aer_firmware_first_valid
:1;
397 unsigned int __aer_firmware_first
:1;
398 unsigned int broken_intx_masking
:1; /* INTx masking can't be used */
399 unsigned int io_window_1k
:1; /* Intel P2P bridge 1K I/O windows */
400 unsigned int irq_managed
:1;
401 unsigned int has_secondary_link
:1;
402 unsigned int non_compliant_bars
:1; /* broken BARs; ignore them */
403 unsigned int is_probed
:1; /* device probing in progress */
404 pci_dev_flags_t dev_flags
;
405 atomic_t enable_cnt
; /* pci_enable_device has been called */
407 u32 saved_config_space
[16]; /* config space saved at suspend time */
408 struct hlist_head saved_cap_space
;
409 struct bin_attribute
*rom_attr
; /* attribute descriptor for sysfs ROM entry */
410 int rom_attr_enabled
; /* has display of the rom attribute been enabled? */
411 struct bin_attribute
*res_attr
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for resources */
412 struct bin_attribute
*res_attr_wc
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for WC mapping of resources */
414 #ifdef CONFIG_PCIE_PTM
415 unsigned int ptm_root
:1;
416 unsigned int ptm_enabled
:1;
419 #ifdef CONFIG_PCI_MSI
420 const struct attribute_group
**msi_irq_groups
;
423 #ifdef CONFIG_PCI_ATS
425 struct pci_sriov
*sriov
; /* SR-IOV capability related */
426 struct pci_dev
*physfn
; /* the PF this VF is associated with */
428 u16 ats_cap
; /* ATS Capability offset */
429 u8 ats_stu
; /* ATS Smallest Translation Unit */
430 atomic_t ats_ref_cnt
; /* number of VFs with ATS enabled */
432 #ifdef CONFIG_PCI_PRI
433 u32 pri_reqs_alloc
; /* Number of PRI requests allocated */
435 #ifdef CONFIG_PCI_PASID
438 phys_addr_t rom
; /* Physical address of ROM if it's not from the BAR */
439 size_t romlen
; /* Length of ROM if it's not from the BAR */
440 char *driver_override
; /* Driver name to force a match */
442 unsigned long priv_flags
; /* Private flags for the pci driver */
445 static inline struct pci_dev
*pci_physfn(struct pci_dev
*dev
)
447 #ifdef CONFIG_PCI_IOV
454 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
);
456 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
457 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
459 static inline int pci_channel_offline(struct pci_dev
*pdev
)
461 return (pdev
->error_state
!= pci_channel_io_normal
);
464 struct pci_host_bridge
{
466 struct pci_bus
*bus
; /* root bus */
470 struct list_head windows
; /* resource_entry */
471 u8 (*swizzle_irq
)(struct pci_dev
*, u8
*); /* platform IRQ swizzler */
472 int (*map_irq
)(const struct pci_dev
*, u8
, u8
);
473 void (*release_fn
)(struct pci_host_bridge
*);
475 struct msi_controller
*msi
;
476 unsigned int ignore_reset_delay
:1; /* for entire hierarchy */
477 unsigned int no_ext_tags
:1; /* no Extended Tags */
478 /* Resource alignment requirements */
479 resource_size_t (*align_resource
)(struct pci_dev
*dev
,
480 const struct resource
*res
,
481 resource_size_t start
,
482 resource_size_t size
,
483 resource_size_t align
);
484 unsigned long private[0] ____cacheline_aligned
;
487 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
489 static inline void *pci_host_bridge_priv(struct pci_host_bridge
*bridge
)
491 return (void *)bridge
->private;
494 static inline struct pci_host_bridge
*pci_host_bridge_from_priv(void *priv
)
496 return container_of(priv
, struct pci_host_bridge
, private);
499 struct pci_host_bridge
*pci_alloc_host_bridge(size_t priv
);
500 struct pci_host_bridge
*devm_pci_alloc_host_bridge(struct device
*dev
,
502 void pci_free_host_bridge(struct pci_host_bridge
*bridge
);
503 struct pci_host_bridge
*pci_find_host_bridge(struct pci_bus
*bus
);
505 void pci_set_host_bridge_release(struct pci_host_bridge
*bridge
,
506 void (*release_fn
)(struct pci_host_bridge
*),
509 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
);
512 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
513 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
514 * buses below host bridges or subtractive decode bridges) go in the list.
515 * Use pci_bus_for_each_resource() to iterate through all the resources.
519 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
520 * and there's no way to program the bridge with the details of the window.
521 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
522 * decode bit set, because they are explicit and can be programmed with _SRS.
524 #define PCI_SUBTRACTIVE_DECODE 0x1
526 struct pci_bus_resource
{
527 struct list_head list
;
528 struct resource
*res
;
532 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
535 struct list_head node
; /* node in list of buses */
536 struct pci_bus
*parent
; /* parent bus this bridge is on */
537 struct list_head children
; /* list of child buses */
538 struct list_head devices
; /* list of devices on this bus */
539 struct pci_dev
*self
; /* bridge device as seen by parent */
540 struct list_head slots
; /* list of slots on this bus;
541 protected by pci_slot_mutex */
542 struct resource
*resource
[PCI_BRIDGE_RESOURCE_NUM
];
543 struct list_head resources
; /* address space routed to this bus */
544 struct resource busn_res
; /* bus numbers routed to this bus */
546 struct pci_ops
*ops
; /* configuration access functions */
547 struct msi_controller
*msi
; /* MSI controller */
548 void *sysdata
; /* hook for sys-specific extension */
549 struct proc_dir_entry
*procdir
; /* directory entry in /proc/bus/pci */
551 unsigned char number
; /* bus number */
552 unsigned char primary
; /* number of primary bridge */
553 unsigned char max_bus_speed
; /* enum pci_bus_speed */
554 unsigned char cur_bus_speed
; /* enum pci_bus_speed */
555 #ifdef CONFIG_PCI_DOMAINS_GENERIC
561 unsigned short bridge_ctl
; /* manage NO_ISA/FBB/et al behaviors */
562 pci_bus_flags_t bus_flags
; /* inherited by child buses */
563 struct device
*bridge
;
565 struct bin_attribute
*legacy_io
; /* legacy I/O for this bus */
566 struct bin_attribute
*legacy_mem
; /* legacy mem */
567 unsigned int is_added
:1;
570 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
573 * Returns true if the PCI bus is root (behind host-PCI bridge),
576 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
577 * This is incorrect because "virtual" buses added for SR-IOV (via
578 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
580 static inline bool pci_is_root_bus(struct pci_bus
*pbus
)
582 return !(pbus
->parent
);
586 * pci_is_bridge - check if the PCI device is a bridge
589 * Return true if the PCI device is bridge whether it has subordinate
592 static inline bool pci_is_bridge(struct pci_dev
*dev
)
594 return dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
595 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
;
598 #define for_each_pci_bridge(dev, bus) \
599 list_for_each_entry(dev, &bus->devices, bus_list) \
600 if (!pci_is_bridge(dev)) {} else
602 static inline struct pci_dev
*pci_upstream_bridge(struct pci_dev
*dev
)
604 dev
= pci_physfn(dev
);
605 if (pci_is_root_bus(dev
->bus
))
608 return dev
->bus
->self
;
611 struct device
*pci_get_host_bridge_device(struct pci_dev
*dev
);
612 void pci_put_host_bridge_device(struct device
*dev
);
614 #ifdef CONFIG_PCI_MSI
615 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
)
617 return pci_dev
->msi_enabled
|| pci_dev
->msix_enabled
;
620 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
) { return false; }
624 * Error values that may be returned by PCI functions.
626 #define PCIBIOS_SUCCESSFUL 0x00
627 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
628 #define PCIBIOS_BAD_VENDOR_ID 0x83
629 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
630 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
631 #define PCIBIOS_SET_FAILED 0x88
632 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
635 * Translate above to generic errno for passing back through non-PCI code.
637 static inline int pcibios_err_to_errno(int err
)
639 if (err
<= PCIBIOS_SUCCESSFUL
)
640 return err
; /* Assume already errno */
643 case PCIBIOS_FUNC_NOT_SUPPORTED
:
645 case PCIBIOS_BAD_VENDOR_ID
:
647 case PCIBIOS_DEVICE_NOT_FOUND
:
649 case PCIBIOS_BAD_REGISTER_NUMBER
:
651 case PCIBIOS_SET_FAILED
:
653 case PCIBIOS_BUFFER_TOO_SMALL
:
660 /* Low-level architecture-dependent routines */
663 int (*add_bus
)(struct pci_bus
*bus
);
664 void (*remove_bus
)(struct pci_bus
*bus
);
665 void __iomem
*(*map_bus
)(struct pci_bus
*bus
, unsigned int devfn
, int where
);
666 int (*read
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
667 int (*write
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
671 * ACPI needs to be able to access PCI config space before we've done a
672 * PCI bus scan and created pci_bus structures.
674 int raw_pci_read(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
675 int reg
, int len
, u32
*val
);
676 int raw_pci_write(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
677 int reg
, int len
, u32 val
);
679 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
680 typedef u64 pci_bus_addr_t
;
682 typedef u32 pci_bus_addr_t
;
685 struct pci_bus_region
{
686 pci_bus_addr_t start
;
691 spinlock_t lock
; /* protects list, index */
692 struct list_head list
; /* for IDs added at runtime */
697 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
698 * a set of callbacks in struct pci_error_handlers, that device driver
699 * will be notified of PCI bus errors, and will be driven to recovery
700 * when an error occurs.
703 typedef unsigned int __bitwise pci_ers_result_t
;
705 enum pci_ers_result
{
706 /* no result/none/not supported in device driver */
707 PCI_ERS_RESULT_NONE
= (__force pci_ers_result_t
) 1,
709 /* Device driver can recover without slot reset */
710 PCI_ERS_RESULT_CAN_RECOVER
= (__force pci_ers_result_t
) 2,
712 /* Device driver wants slot to be reset. */
713 PCI_ERS_RESULT_NEED_RESET
= (__force pci_ers_result_t
) 3,
715 /* Device has completely failed, is unrecoverable */
716 PCI_ERS_RESULT_DISCONNECT
= (__force pci_ers_result_t
) 4,
718 /* Device driver is fully recovered and operational */
719 PCI_ERS_RESULT_RECOVERED
= (__force pci_ers_result_t
) 5,
721 /* No AER capabilities registered for the driver */
722 PCI_ERS_RESULT_NO_AER_DRIVER
= (__force pci_ers_result_t
) 6,
725 /* PCI bus error event callbacks */
726 struct pci_error_handlers
{
727 /* PCI bus error detected on this device */
728 pci_ers_result_t (*error_detected
)(struct pci_dev
*dev
,
729 enum pci_channel_state error
);
731 /* MMIO has been re-enabled, but not DMA */
732 pci_ers_result_t (*mmio_enabled
)(struct pci_dev
*dev
);
734 /* PCI slot has been reset */
735 pci_ers_result_t (*slot_reset
)(struct pci_dev
*dev
);
737 /* PCI function reset prepare or completed */
738 void (*reset_prepare
)(struct pci_dev
*dev
);
739 void (*reset_done
)(struct pci_dev
*dev
);
741 /* Device driver may resume normal operations */
742 void (*resume
)(struct pci_dev
*dev
);
748 struct list_head node
;
750 const struct pci_device_id
*id_table
; /* must be non-NULL for probe to be called */
751 int (*probe
) (struct pci_dev
*dev
, const struct pci_device_id
*id
); /* New device inserted */
752 void (*remove
) (struct pci_dev
*dev
); /* Device removed (NULL if not a hot-plug capable driver) */
753 int (*suspend
) (struct pci_dev
*dev
, pm_message_t state
); /* Device suspended */
754 int (*suspend_late
) (struct pci_dev
*dev
, pm_message_t state
);
755 int (*resume_early
) (struct pci_dev
*dev
);
756 int (*resume
) (struct pci_dev
*dev
); /* Device woken up */
757 void (*shutdown
) (struct pci_dev
*dev
);
758 int (*sriov_configure
) (struct pci_dev
*dev
, int num_vfs
); /* PF pdev */
759 const struct pci_error_handlers
*err_handler
;
760 const struct attribute_group
**groups
;
761 struct device_driver driver
;
762 struct pci_dynids dynids
;
765 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
768 * PCI_DEVICE - macro used to describe a specific pci device
769 * @vend: the 16 bit PCI Vendor ID
770 * @dev: the 16 bit PCI Device ID
772 * This macro is used to create a struct pci_device_id that matches a
773 * specific device. The subvendor and subdevice fields will be set to
776 #define PCI_DEVICE(vend,dev) \
777 .vendor = (vend), .device = (dev), \
778 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
781 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
782 * @vend: the 16 bit PCI Vendor ID
783 * @dev: the 16 bit PCI Device ID
784 * @subvend: the 16 bit PCI Subvendor ID
785 * @subdev: the 16 bit PCI Subdevice ID
787 * This macro is used to create a struct pci_device_id that matches a
788 * specific device with subsystem information.
790 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
791 .vendor = (vend), .device = (dev), \
792 .subvendor = (subvend), .subdevice = (subdev)
795 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
796 * @dev_class: the class, subclass, prog-if triple for this device
797 * @dev_class_mask: the class mask for this device
799 * This macro is used to create a struct pci_device_id that matches a
800 * specific PCI class. The vendor, device, subvendor, and subdevice
801 * fields will be set to PCI_ANY_ID.
803 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
804 .class = (dev_class), .class_mask = (dev_class_mask), \
805 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
806 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
809 * PCI_VDEVICE - macro used to describe a specific pci device in short form
810 * @vend: the vendor name
811 * @dev: the 16 bit PCI Device ID
813 * This macro is used to create a struct pci_device_id that matches a
814 * specific PCI device. The subvendor, and subdevice fields will be set
815 * to PCI_ANY_ID. The macro allows the next field to follow as the device
819 #define PCI_VDEVICE(vend, dev) \
820 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
821 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
824 PCI_REASSIGN_ALL_RSRC
= 0x00000001, /* ignore firmware setup */
825 PCI_REASSIGN_ALL_BUS
= 0x00000002, /* reassign all bus numbers */
826 PCI_PROBE_ONLY
= 0x00000004, /* use existing setup */
827 PCI_CAN_SKIP_ISA_ALIGN
= 0x00000008, /* don't do ISA alignment */
828 PCI_ENABLE_PROC_DOMAINS
= 0x00000010, /* enable domains in /proc */
829 PCI_COMPAT_DOMAIN_0
= 0x00000020, /* ... except domain 0 */
830 PCI_SCAN_ALL_PCIE_DEVS
= 0x00000040, /* scan all, not just dev 0 */
833 /* these external functions are only available when PCI support is enabled */
836 extern unsigned int pci_flags
;
838 static inline void pci_set_flags(int flags
) { pci_flags
= flags
; }
839 static inline void pci_add_flags(int flags
) { pci_flags
|= flags
; }
840 static inline void pci_clear_flags(int flags
) { pci_flags
&= ~flags
; }
841 static inline int pci_has_flag(int flag
) { return pci_flags
& flag
; }
843 void pcie_bus_configure_settings(struct pci_bus
*bus
);
845 enum pcie_bus_config_types
{
846 PCIE_BUS_TUNE_OFF
, /* don't touch MPS at all */
847 PCIE_BUS_DEFAULT
, /* ensure MPS matches upstream bridge */
848 PCIE_BUS_SAFE
, /* use largest MPS boot-time devices support */
849 PCIE_BUS_PERFORMANCE
, /* use MPS and MRRS for best performance */
850 PCIE_BUS_PEER2PEER
, /* set MPS = 128 for all devices */
853 extern enum pcie_bus_config_types pcie_bus_config
;
855 extern struct bus_type pci_bus_type
;
857 /* Do NOT directly access these two variables, unless you are arch-specific PCI
858 * code, or PCI core code. */
859 extern struct list_head pci_root_buses
; /* list of all known PCI buses */
860 /* Some device drivers need know if PCI is initiated */
861 int no_pci_devices(void);
863 void pcibios_resource_survey_bus(struct pci_bus
*bus
);
864 void pcibios_bus_add_device(struct pci_dev
*pdev
);
865 void pcibios_add_bus(struct pci_bus
*bus
);
866 void pcibios_remove_bus(struct pci_bus
*bus
);
867 void pcibios_fixup_bus(struct pci_bus
*);
868 int __must_check
pcibios_enable_device(struct pci_dev
*, int mask
);
869 /* Architecture-specific versions may override this (weak) */
870 char *pcibios_setup(char *str
);
872 /* Used only when drivers/pci/setup.c is used */
873 resource_size_t
pcibios_align_resource(void *, const struct resource
*,
877 /* Weak but can be overriden by arch */
878 void pci_fixup_cardbus(struct pci_bus
*);
880 /* Generic PCI functions used internally */
882 void pcibios_resource_to_bus(struct pci_bus
*bus
, struct pci_bus_region
*region
,
883 struct resource
*res
);
884 void pcibios_bus_to_resource(struct pci_bus
*bus
, struct resource
*res
,
885 struct pci_bus_region
*region
);
886 void pcibios_scan_specific_bus(int busn
);
887 struct pci_bus
*pci_find_bus(int domain
, int busnr
);
888 void pci_bus_add_devices(const struct pci_bus
*bus
);
889 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
);
890 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
891 struct pci_ops
*ops
, void *sysdata
,
892 struct list_head
*resources
);
893 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int busmax
);
894 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int busmax
);
895 void pci_bus_release_busn_res(struct pci_bus
*b
);
896 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
897 struct pci_ops
*ops
, void *sysdata
,
898 struct list_head
*resources
);
899 int pci_scan_root_bus_bridge(struct pci_host_bridge
*bridge
);
900 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
902 void pcie_update_link_speed(struct pci_bus
*bus
, u16 link_status
);
903 struct pci_slot
*pci_create_slot(struct pci_bus
*parent
, int slot_nr
,
905 struct hotplug_slot
*hotplug
);
906 void pci_destroy_slot(struct pci_slot
*slot
);
908 void pci_dev_assign_slot(struct pci_dev
*dev
);
910 static inline void pci_dev_assign_slot(struct pci_dev
*dev
) { }
912 int pci_scan_slot(struct pci_bus
*bus
, int devfn
);
913 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
);
914 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
);
915 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
916 void pci_bus_add_device(struct pci_dev
*dev
);
917 void pci_read_bridge_bases(struct pci_bus
*child
);
918 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
919 struct resource
*res
);
920 struct pci_dev
*pci_find_pcie_root_port(struct pci_dev
*dev
);
921 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
);
922 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
);
923 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
);
924 struct pci_dev
*pci_dev_get(struct pci_dev
*dev
);
925 void pci_dev_put(struct pci_dev
*dev
);
926 void pci_remove_bus(struct pci_bus
*b
);
927 void pci_stop_and_remove_bus_device(struct pci_dev
*dev
);
928 void pci_stop_and_remove_bus_device_locked(struct pci_dev
*dev
);
929 void pci_stop_root_bus(struct pci_bus
*bus
);
930 void pci_remove_root_bus(struct pci_bus
*bus
);
931 void pci_setup_cardbus(struct pci_bus
*bus
);
932 void pcibios_setup_bridge(struct pci_bus
*bus
, unsigned long type
);
933 void pci_sort_breadthfirst(void);
934 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
935 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
937 /* Generic PCI functions exported to card drivers */
939 enum pci_lost_interrupt_reason
{
940 PCI_LOST_IRQ_NO_INFORMATION
= 0,
941 PCI_LOST_IRQ_DISABLE_MSI
,
942 PCI_LOST_IRQ_DISABLE_MSIX
,
943 PCI_LOST_IRQ_DISABLE_ACPI
,
945 enum pci_lost_interrupt_reason
pci_lost_interrupt(struct pci_dev
*dev
);
946 int pci_find_capability(struct pci_dev
*dev
, int cap
);
947 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
);
948 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
);
949 int pci_find_next_ext_capability(struct pci_dev
*dev
, int pos
, int cap
);
950 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
);
951 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
);
952 struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
);
954 struct pci_dev
*pci_get_device(unsigned int vendor
, unsigned int device
,
955 struct pci_dev
*from
);
956 struct pci_dev
*pci_get_subsys(unsigned int vendor
, unsigned int device
,
957 unsigned int ss_vendor
, unsigned int ss_device
,
958 struct pci_dev
*from
);
959 struct pci_dev
*pci_get_slot(struct pci_bus
*bus
, unsigned int devfn
);
960 struct pci_dev
*pci_get_domain_bus_and_slot(int domain
, unsigned int bus
,
962 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
965 return pci_get_domain_bus_and_slot(0, bus
, devfn
);
967 struct pci_dev
*pci_get_class(unsigned int class, struct pci_dev
*from
);
968 int pci_dev_present(const struct pci_device_id
*ids
);
970 int pci_bus_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
972 int pci_bus_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
973 int where
, u16
*val
);
974 int pci_bus_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
975 int where
, u32
*val
);
976 int pci_bus_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
978 int pci_bus_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
980 int pci_bus_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
983 int pci_generic_config_read(struct pci_bus
*bus
, unsigned int devfn
,
984 int where
, int size
, u32
*val
);
985 int pci_generic_config_write(struct pci_bus
*bus
, unsigned int devfn
,
986 int where
, int size
, u32 val
);
987 int pci_generic_config_read32(struct pci_bus
*bus
, unsigned int devfn
,
988 int where
, int size
, u32
*val
);
989 int pci_generic_config_write32(struct pci_bus
*bus
, unsigned int devfn
,
990 int where
, int size
, u32 val
);
992 struct pci_ops
*pci_bus_set_ops(struct pci_bus
*bus
, struct pci_ops
*ops
);
994 int pci_read_config_byte(const struct pci_dev
*dev
, int where
, u8
*val
);
995 int pci_read_config_word(const struct pci_dev
*dev
, int where
, u16
*val
);
996 int pci_read_config_dword(const struct pci_dev
*dev
, int where
, u32
*val
);
997 int pci_write_config_byte(const struct pci_dev
*dev
, int where
, u8 val
);
998 int pci_write_config_word(const struct pci_dev
*dev
, int where
, u16 val
);
999 int pci_write_config_dword(const struct pci_dev
*dev
, int where
, u32 val
);
1001 int pcie_capability_read_word(struct pci_dev
*dev
, int pos
, u16
*val
);
1002 int pcie_capability_read_dword(struct pci_dev
*dev
, int pos
, u32
*val
);
1003 int pcie_capability_write_word(struct pci_dev
*dev
, int pos
, u16 val
);
1004 int pcie_capability_write_dword(struct pci_dev
*dev
, int pos
, u32 val
);
1005 int pcie_capability_clear_and_set_word(struct pci_dev
*dev
, int pos
,
1006 u16 clear
, u16 set
);
1007 int pcie_capability_clear_and_set_dword(struct pci_dev
*dev
, int pos
,
1008 u32 clear
, u32 set
);
1010 static inline int pcie_capability_set_word(struct pci_dev
*dev
, int pos
,
1013 return pcie_capability_clear_and_set_word(dev
, pos
, 0, set
);
1016 static inline int pcie_capability_set_dword(struct pci_dev
*dev
, int pos
,
1019 return pcie_capability_clear_and_set_dword(dev
, pos
, 0, set
);
1022 static inline int pcie_capability_clear_word(struct pci_dev
*dev
, int pos
,
1025 return pcie_capability_clear_and_set_word(dev
, pos
, clear
, 0);
1028 static inline int pcie_capability_clear_dword(struct pci_dev
*dev
, int pos
,
1031 return pcie_capability_clear_and_set_dword(dev
, pos
, clear
, 0);
1034 /* user-space driven config access */
1035 int pci_user_read_config_byte(struct pci_dev
*dev
, int where
, u8
*val
);
1036 int pci_user_read_config_word(struct pci_dev
*dev
, int where
, u16
*val
);
1037 int pci_user_read_config_dword(struct pci_dev
*dev
, int where
, u32
*val
);
1038 int pci_user_write_config_byte(struct pci_dev
*dev
, int where
, u8 val
);
1039 int pci_user_write_config_word(struct pci_dev
*dev
, int where
, u16 val
);
1040 int pci_user_write_config_dword(struct pci_dev
*dev
, int where
, u32 val
);
1042 int __must_check
pci_enable_device(struct pci_dev
*dev
);
1043 int __must_check
pci_enable_device_io(struct pci_dev
*dev
);
1044 int __must_check
pci_enable_device_mem(struct pci_dev
*dev
);
1045 int __must_check
pci_reenable_device(struct pci_dev
*);
1046 int __must_check
pcim_enable_device(struct pci_dev
*pdev
);
1047 void pcim_pin_device(struct pci_dev
*pdev
);
1049 static inline bool pci_intx_mask_supported(struct pci_dev
*pdev
)
1052 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1053 * writable and no quirk has marked the feature broken.
1055 return !pdev
->broken_intx_masking
;
1058 static inline int pci_is_enabled(struct pci_dev
*pdev
)
1060 return (atomic_read(&pdev
->enable_cnt
) > 0);
1063 static inline int pci_is_managed(struct pci_dev
*pdev
)
1065 return pdev
->is_managed
;
1068 void pci_disable_device(struct pci_dev
*dev
);
1070 extern unsigned int pcibios_max_latency
;
1071 void pci_set_master(struct pci_dev
*dev
);
1072 void pci_clear_master(struct pci_dev
*dev
);
1074 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
);
1075 int pci_set_cacheline_size(struct pci_dev
*dev
);
1076 #define HAVE_PCI_SET_MWI
1077 int __must_check
pci_set_mwi(struct pci_dev
*dev
);
1078 int pci_try_set_mwi(struct pci_dev
*dev
);
1079 void pci_clear_mwi(struct pci_dev
*dev
);
1080 void pci_intx(struct pci_dev
*dev
, int enable
);
1081 bool pci_check_and_mask_intx(struct pci_dev
*dev
);
1082 bool pci_check_and_unmask_intx(struct pci_dev
*dev
);
1083 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
);
1084 int pci_wait_for_pending_transaction(struct pci_dev
*dev
);
1085 int pcix_get_max_mmrbc(struct pci_dev
*dev
);
1086 int pcix_get_mmrbc(struct pci_dev
*dev
);
1087 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
);
1088 int pcie_get_readrq(struct pci_dev
*dev
);
1089 int pcie_set_readrq(struct pci_dev
*dev
, int rq
);
1090 int pcie_get_mps(struct pci_dev
*dev
);
1091 int pcie_set_mps(struct pci_dev
*dev
, int mps
);
1092 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
1093 enum pcie_link_width
*width
);
1094 void pcie_flr(struct pci_dev
*dev
);
1095 int __pci_reset_function_locked(struct pci_dev
*dev
);
1096 int pci_reset_function(struct pci_dev
*dev
);
1097 int pci_reset_function_locked(struct pci_dev
*dev
);
1098 int pci_try_reset_function(struct pci_dev
*dev
);
1099 int pci_probe_reset_slot(struct pci_slot
*slot
);
1100 int pci_reset_slot(struct pci_slot
*slot
);
1101 int pci_try_reset_slot(struct pci_slot
*slot
);
1102 int pci_probe_reset_bus(struct pci_bus
*bus
);
1103 int pci_reset_bus(struct pci_bus
*bus
);
1104 int pci_try_reset_bus(struct pci_bus
*bus
);
1105 void pci_reset_secondary_bus(struct pci_dev
*dev
);
1106 void pcibios_reset_secondary_bus(struct pci_dev
*dev
);
1107 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
);
1108 void pci_update_resource(struct pci_dev
*dev
, int resno
);
1109 int __must_check
pci_assign_resource(struct pci_dev
*dev
, int i
);
1110 int __must_check
pci_reassign_resource(struct pci_dev
*dev
, int i
, resource_size_t add_size
, resource_size_t align
);
1111 void pci_release_resource(struct pci_dev
*dev
, int resno
);
1112 int __must_check
pci_resize_resource(struct pci_dev
*dev
, int i
, int size
);
1113 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
);
1114 bool pci_device_is_present(struct pci_dev
*pdev
);
1115 void pci_ignore_hotplug(struct pci_dev
*dev
);
1117 int __printf(6, 7) pci_request_irq(struct pci_dev
*dev
, unsigned int nr
,
1118 irq_handler_t handler
, irq_handler_t thread_fn
, void *dev_id
,
1119 const char *fmt
, ...);
1120 void pci_free_irq(struct pci_dev
*dev
, unsigned int nr
, void *dev_id
);
1122 /* ROM control related routines */
1123 int pci_enable_rom(struct pci_dev
*pdev
);
1124 void pci_disable_rom(struct pci_dev
*pdev
);
1125 void __iomem __must_check
*pci_map_rom(struct pci_dev
*pdev
, size_t *size
);
1126 void pci_unmap_rom(struct pci_dev
*pdev
, void __iomem
*rom
);
1127 size_t pci_get_rom_size(struct pci_dev
*pdev
, void __iomem
*rom
, size_t size
);
1128 void __iomem __must_check
*pci_platform_rom(struct pci_dev
*pdev
, size_t *size
);
1130 /* Power management related routines */
1131 int pci_save_state(struct pci_dev
*dev
);
1132 void pci_restore_state(struct pci_dev
*dev
);
1133 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
);
1134 int pci_load_saved_state(struct pci_dev
*dev
,
1135 struct pci_saved_state
*state
);
1136 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1137 struct pci_saved_state
**state
);
1138 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
);
1139 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
,
1141 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
);
1142 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
,
1143 u16 cap
, unsigned int size
);
1144 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
);
1145 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
);
1146 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
);
1147 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
);
1148 void pci_pme_active(struct pci_dev
*dev
, bool enable
);
1149 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
);
1150 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
);
1151 int pci_prepare_to_sleep(struct pci_dev
*dev
);
1152 int pci_back_from_sleep(struct pci_dev
*dev
);
1153 bool pci_dev_run_wake(struct pci_dev
*dev
);
1154 bool pci_check_pme_status(struct pci_dev
*dev
);
1155 void pci_pme_wakeup_bus(struct pci_bus
*bus
);
1156 void pci_d3cold_enable(struct pci_dev
*dev
);
1157 void pci_d3cold_disable(struct pci_dev
*dev
);
1158 bool pcie_relaxed_ordering_enabled(struct pci_dev
*dev
);
1160 /* PCI Virtual Channel */
1161 int pci_save_vc_state(struct pci_dev
*dev
);
1162 void pci_restore_vc_state(struct pci_dev
*dev
);
1163 void pci_allocate_vc_save_buffers(struct pci_dev
*dev
);
1165 /* For use by arch with custom probe code */
1166 void set_pcie_port_type(struct pci_dev
*pdev
);
1167 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
);
1169 /* Functions for PCI Hotplug drivers to use */
1170 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1171 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
);
1172 unsigned int pci_rescan_bus(struct pci_bus
*bus
);
1173 void pci_lock_rescan_remove(void);
1174 void pci_unlock_rescan_remove(void);
1176 /* Vital product data routines */
1177 ssize_t
pci_read_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, void *buf
);
1178 ssize_t
pci_write_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, const void *buf
);
1179 int pci_set_vpd_size(struct pci_dev
*dev
, size_t len
);
1181 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1182 resource_size_t
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
);
1183 void pci_bus_assign_resources(const struct pci_bus
*bus
);
1184 void pci_bus_claim_resources(struct pci_bus
*bus
);
1185 void pci_bus_size_bridges(struct pci_bus
*bus
);
1186 int pci_claim_resource(struct pci_dev
*, int);
1187 int pci_claim_bridge_resource(struct pci_dev
*bridge
, int i
);
1188 void pci_assign_unassigned_resources(void);
1189 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
);
1190 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
);
1191 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
);
1192 int pci_reassign_bridge_resources(struct pci_dev
*bridge
, unsigned long type
);
1193 void pdev_enable_device(struct pci_dev
*);
1194 int pci_enable_resources(struct pci_dev
*, int mask
);
1195 void pci_assign_irq(struct pci_dev
*dev
);
1196 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
);
1197 #define HAVE_PCI_REQ_REGIONS 2
1198 int __must_check
pci_request_regions(struct pci_dev
*, const char *);
1199 int __must_check
pci_request_regions_exclusive(struct pci_dev
*, const char *);
1200 void pci_release_regions(struct pci_dev
*);
1201 int __must_check
pci_request_region(struct pci_dev
*, int, const char *);
1202 int __must_check
pci_request_region_exclusive(struct pci_dev
*, int, const char *);
1203 void pci_release_region(struct pci_dev
*, int);
1204 int pci_request_selected_regions(struct pci_dev
*, int, const char *);
1205 int pci_request_selected_regions_exclusive(struct pci_dev
*, int, const char *);
1206 void pci_release_selected_regions(struct pci_dev
*, int);
1208 /* drivers/pci/bus.c */
1209 struct pci_bus
*pci_bus_get(struct pci_bus
*bus
);
1210 void pci_bus_put(struct pci_bus
*bus
);
1211 void pci_add_resource(struct list_head
*resources
, struct resource
*res
);
1212 void pci_add_resource_offset(struct list_head
*resources
, struct resource
*res
,
1213 resource_size_t offset
);
1214 void pci_free_resource_list(struct list_head
*resources
);
1215 void pci_bus_add_resource(struct pci_bus
*bus
, struct resource
*res
,
1216 unsigned int flags
);
1217 struct resource
*pci_bus_resource_n(const struct pci_bus
*bus
, int n
);
1218 void pci_bus_remove_resources(struct pci_bus
*bus
);
1219 int devm_request_pci_bus_resources(struct device
*dev
,
1220 struct list_head
*resources
);
1222 #define pci_bus_for_each_resource(bus, res, i) \
1224 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1227 int __must_check
pci_bus_alloc_resource(struct pci_bus
*bus
,
1228 struct resource
*res
, resource_size_t size
,
1229 resource_size_t align
, resource_size_t min
,
1230 unsigned long type_mask
,
1231 resource_size_t (*alignf
)(void *,
1232 const struct resource
*,
1238 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
1239 resource_size_t size
);
1240 unsigned long pci_address_to_pio(phys_addr_t addr
);
1241 phys_addr_t
pci_pio_to_address(unsigned long pio
);
1242 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
);
1243 void pci_unmap_iospace(struct resource
*res
);
1244 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
1245 resource_size_t offset
,
1246 resource_size_t size
);
1247 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
1248 struct resource
*res
);
1250 static inline pci_bus_addr_t
pci_bus_address(struct pci_dev
*pdev
, int bar
)
1252 struct pci_bus_region region
;
1254 pcibios_resource_to_bus(pdev
->bus
, ®ion
, &pdev
->resource
[bar
]);
1255 return region
.start
;
1258 /* Proper probing supporting hot-pluggable devices */
1259 int __must_check
__pci_register_driver(struct pci_driver
*, struct module
*,
1260 const char *mod_name
);
1263 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1265 #define pci_register_driver(driver) \
1266 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1268 void pci_unregister_driver(struct pci_driver
*dev
);
1271 * module_pci_driver() - Helper macro for registering a PCI driver
1272 * @__pci_driver: pci_driver struct
1274 * Helper macro for PCI drivers which do not do anything special in module
1275 * init/exit. This eliminates a lot of boilerplate. Each module may only
1276 * use this macro once, and calling it replaces module_init() and module_exit()
1278 #define module_pci_driver(__pci_driver) \
1279 module_driver(__pci_driver, pci_register_driver, \
1280 pci_unregister_driver)
1283 * builtin_pci_driver() - Helper macro for registering a PCI driver
1284 * @__pci_driver: pci_driver struct
1286 * Helper macro for PCI drivers which do not do anything special in their
1287 * init code. This eliminates a lot of boilerplate. Each driver may only
1288 * use this macro once, and calling it replaces device_initcall(...)
1290 #define builtin_pci_driver(__pci_driver) \
1291 builtin_driver(__pci_driver, pci_register_driver)
1293 struct pci_driver
*pci_dev_driver(const struct pci_dev
*dev
);
1294 int pci_add_dynid(struct pci_driver
*drv
,
1295 unsigned int vendor
, unsigned int device
,
1296 unsigned int subvendor
, unsigned int subdevice
,
1297 unsigned int class, unsigned int class_mask
,
1298 unsigned long driver_data
);
1299 const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1300 struct pci_dev
*dev
);
1301 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
,
1304 void pci_walk_bus(struct pci_bus
*top
, int (*cb
)(struct pci_dev
*, void *),
1306 int pci_cfg_space_size(struct pci_dev
*dev
);
1307 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
);
1308 void pci_setup_bridge(struct pci_bus
*bus
);
1309 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
1310 unsigned long type
);
1311 resource_size_t
pcibios_iov_resource_alignment(struct pci_dev
*dev
, int resno
);
1313 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1314 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1316 int pci_set_vga_state(struct pci_dev
*pdev
, bool decode
,
1317 unsigned int command_bits
, u32 flags
);
1319 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1320 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1321 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1322 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1323 #define PCI_IRQ_ALL_TYPES \
1324 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1326 /* kmem_cache style wrapper around pci_alloc_consistent() */
1328 #include <linux/pci-dma.h>
1329 #include <linux/dmapool.h>
1331 #define pci_pool dma_pool
1332 #define pci_pool_create(name, pdev, size, align, allocation) \
1333 dma_pool_create(name, &pdev->dev, size, align, allocation)
1334 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1335 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1336 #define pci_pool_zalloc(pool, flags, handle) \
1337 dma_pool_zalloc(pool, flags, handle)
1338 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1341 u32 vector
; /* kernel uses to write allocated vector */
1342 u16 entry
; /* driver uses to specify entry, OS writes */
1345 #ifdef CONFIG_PCI_MSI
1346 int pci_msi_vec_count(struct pci_dev
*dev
);
1347 void pci_disable_msi(struct pci_dev
*dev
);
1348 int pci_msix_vec_count(struct pci_dev
*dev
);
1349 void pci_disable_msix(struct pci_dev
*dev
);
1350 void pci_restore_msi_state(struct pci_dev
*dev
);
1351 int pci_msi_enabled(void);
1352 int pci_enable_msi(struct pci_dev
*dev
);
1353 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1354 int minvec
, int maxvec
);
1355 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1356 struct msix_entry
*entries
, int nvec
)
1358 int rc
= pci_enable_msix_range(dev
, entries
, nvec
, nvec
);
1363 int pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1364 unsigned int max_vecs
, unsigned int flags
,
1365 const struct irq_affinity
*affd
);
1367 void pci_free_irq_vectors(struct pci_dev
*dev
);
1368 int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
);
1369 const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*pdev
, int vec
);
1370 int pci_irq_get_node(struct pci_dev
*pdev
, int vec
);
1373 static inline int pci_msi_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1374 static inline void pci_disable_msi(struct pci_dev
*dev
) { }
1375 static inline int pci_msix_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1376 static inline void pci_disable_msix(struct pci_dev
*dev
) { }
1377 static inline void pci_restore_msi_state(struct pci_dev
*dev
) { }
1378 static inline int pci_msi_enabled(void) { return 0; }
1379 static inline int pci_enable_msi(struct pci_dev
*dev
)
1381 static inline int pci_enable_msix_range(struct pci_dev
*dev
,
1382 struct msix_entry
*entries
, int minvec
, int maxvec
)
1384 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1385 struct msix_entry
*entries
, int nvec
)
1389 pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1390 unsigned int max_vecs
, unsigned int flags
,
1391 const struct irq_affinity
*aff_desc
)
1393 if ((flags
& PCI_IRQ_LEGACY
) && min_vecs
== 1 && dev
->irq
)
1398 static inline void pci_free_irq_vectors(struct pci_dev
*dev
)
1402 static inline int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
)
1404 if (WARN_ON_ONCE(nr
> 0))
1408 static inline const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*pdev
,
1411 return cpu_possible_mask
;
1414 static inline int pci_irq_get_node(struct pci_dev
*pdev
, int vec
)
1416 return first_online_node
;
1421 pci_alloc_irq_vectors(struct pci_dev
*dev
, unsigned int min_vecs
,
1422 unsigned int max_vecs
, unsigned int flags
)
1424 return pci_alloc_irq_vectors_affinity(dev
, min_vecs
, max_vecs
, flags
,
1429 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1430 * @d: the INTx IRQ domain
1431 * @node: the DT node for the device whose interrupt we're translating
1432 * @intspec: the interrupt specifier data from the DT
1433 * @intsize: the number of entries in @intspec
1434 * @out_hwirq: pointer at which to write the hwirq number
1435 * @out_type: pointer at which to write the interrupt type
1437 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1438 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1439 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1440 * INTx value to obtain the hwirq number.
1442 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1444 static inline int pci_irqd_intx_xlate(struct irq_domain
*d
,
1445 struct device_node
*node
,
1447 unsigned int intsize
,
1448 unsigned long *out_hwirq
,
1449 unsigned int *out_type
)
1451 const u32 intx
= intspec
[0];
1453 if (intx
< PCI_INTERRUPT_INTA
|| intx
> PCI_INTERRUPT_INTD
)
1456 *out_hwirq
= intx
- PCI_INTERRUPT_INTA
;
1460 #ifdef CONFIG_PCIEPORTBUS
1461 extern bool pcie_ports_disabled
;
1462 extern bool pcie_ports_auto
;
1464 #define pcie_ports_disabled true
1465 #define pcie_ports_auto false
1468 #ifdef CONFIG_PCIEASPM
1469 bool pcie_aspm_support_enabled(void);
1471 static inline bool pcie_aspm_support_enabled(void) { return false; }
1474 #ifdef CONFIG_PCIEAER
1475 void pci_no_aer(void);
1476 bool pci_aer_available(void);
1477 int pci_aer_init(struct pci_dev
*dev
);
1479 static inline void pci_no_aer(void) { }
1480 static inline bool pci_aer_available(void) { return false; }
1481 static inline int pci_aer_init(struct pci_dev
*d
) { return -ENODEV
; }
1484 #ifdef CONFIG_PCIE_ECRC
1485 void pcie_set_ecrc_checking(struct pci_dev
*dev
);
1486 void pcie_ecrc_get_policy(char *str
);
1488 static inline void pcie_set_ecrc_checking(struct pci_dev
*dev
) { }
1489 static inline void pcie_ecrc_get_policy(char *str
) { }
1492 #ifdef CONFIG_PCI_ATS
1493 /* Address Translation Service */
1494 void pci_ats_init(struct pci_dev
*dev
);
1495 int pci_enable_ats(struct pci_dev
*dev
, int ps
);
1496 void pci_disable_ats(struct pci_dev
*dev
);
1497 int pci_ats_queue_depth(struct pci_dev
*dev
);
1499 static inline void pci_ats_init(struct pci_dev
*d
) { }
1500 static inline int pci_enable_ats(struct pci_dev
*d
, int ps
) { return -ENODEV
; }
1501 static inline void pci_disable_ats(struct pci_dev
*d
) { }
1502 static inline int pci_ats_queue_depth(struct pci_dev
*d
) { return -ENODEV
; }
1505 #ifdef CONFIG_PCIE_PTM
1506 int pci_enable_ptm(struct pci_dev
*dev
, u8
*granularity
);
1508 static inline int pci_enable_ptm(struct pci_dev
*dev
, u8
*granularity
)
1512 void pci_cfg_access_lock(struct pci_dev
*dev
);
1513 bool pci_cfg_access_trylock(struct pci_dev
*dev
);
1514 void pci_cfg_access_unlock(struct pci_dev
*dev
);
1517 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1518 * a PCI domain is defined to be a set of PCI buses which share
1519 * configuration space.
1521 #ifdef CONFIG_PCI_DOMAINS
1522 extern int pci_domains_supported
;
1523 int pci_get_new_domain_nr(void);
1525 enum { pci_domains_supported
= 0 };
1526 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1527 static inline int pci_proc_domain(struct pci_bus
*bus
) { return 0; }
1528 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1529 #endif /* CONFIG_PCI_DOMAINS */
1532 * Generic implementation for PCI domain support. If your
1533 * architecture does not need custom management of PCI
1534 * domains then this implementation will be used
1536 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1537 static inline int pci_domain_nr(struct pci_bus
*bus
)
1539 return bus
->domain_nr
;
1542 int acpi_pci_bus_find_domain_nr(struct pci_bus
*bus
);
1544 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus
*bus
)
1547 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
);
1550 /* some architectures require additional setup to direct VGA traffic */
1551 typedef int (*arch_set_vga_state_t
)(struct pci_dev
*pdev
, bool decode
,
1552 unsigned int command_bits
, u32 flags
);
1553 void pci_register_set_vga_state(arch_set_vga_state_t func
);
1556 pci_request_io_regions(struct pci_dev
*pdev
, const char *name
)
1558 return pci_request_selected_regions(pdev
,
1559 pci_select_bars(pdev
, IORESOURCE_IO
), name
);
1563 pci_release_io_regions(struct pci_dev
*pdev
)
1565 return pci_release_selected_regions(pdev
,
1566 pci_select_bars(pdev
, IORESOURCE_IO
));
1570 pci_request_mem_regions(struct pci_dev
*pdev
, const char *name
)
1572 return pci_request_selected_regions(pdev
,
1573 pci_select_bars(pdev
, IORESOURCE_MEM
), name
);
1577 pci_release_mem_regions(struct pci_dev
*pdev
)
1579 return pci_release_selected_regions(pdev
,
1580 pci_select_bars(pdev
, IORESOURCE_MEM
));
1583 #else /* CONFIG_PCI is not enabled */
1585 static inline void pci_set_flags(int flags
) { }
1586 static inline void pci_add_flags(int flags
) { }
1587 static inline void pci_clear_flags(int flags
) { }
1588 static inline int pci_has_flag(int flag
) { return 0; }
1591 * If the system does not have PCI, clearly these return errors. Define
1592 * these as simple inline functions to avoid hair in drivers.
1595 #define _PCI_NOP(o, s, t) \
1596 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1598 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1600 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1601 _PCI_NOP(o, word, u16 x) \
1602 _PCI_NOP(o, dword, u32 x)
1603 _PCI_NOP_ALL(read
, *)
1604 _PCI_NOP_ALL(write
,)
1606 static inline struct pci_dev
*pci_get_device(unsigned int vendor
,
1607 unsigned int device
,
1608 struct pci_dev
*from
)
1611 static inline struct pci_dev
*pci_get_subsys(unsigned int vendor
,
1612 unsigned int device
,
1613 unsigned int ss_vendor
,
1614 unsigned int ss_device
,
1615 struct pci_dev
*from
)
1618 static inline struct pci_dev
*pci_get_class(unsigned int class,
1619 struct pci_dev
*from
)
1622 #define pci_dev_present(ids) (0)
1623 #define no_pci_devices() (1)
1624 #define pci_dev_put(dev) do { } while (0)
1626 static inline void pci_set_master(struct pci_dev
*dev
) { }
1627 static inline int pci_enable_device(struct pci_dev
*dev
) { return -EIO
; }
1628 static inline void pci_disable_device(struct pci_dev
*dev
) { }
1629 static inline int pci_assign_resource(struct pci_dev
*dev
, int i
)
1631 static inline int __pci_register_driver(struct pci_driver
*drv
,
1632 struct module
*owner
)
1634 static inline int pci_register_driver(struct pci_driver
*drv
)
1636 static inline void pci_unregister_driver(struct pci_driver
*drv
) { }
1637 static inline int pci_find_capability(struct pci_dev
*dev
, int cap
)
1639 static inline int pci_find_next_capability(struct pci_dev
*dev
, u8 post
,
1642 static inline int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
1645 /* Power management related routines */
1646 static inline int pci_save_state(struct pci_dev
*dev
) { return 0; }
1647 static inline void pci_restore_state(struct pci_dev
*dev
) { }
1648 static inline int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1650 static inline int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1652 static inline pci_power_t
pci_choose_state(struct pci_dev
*dev
,
1655 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1659 static inline struct resource
*pci_find_resource(struct pci_dev
*dev
,
1660 struct resource
*res
)
1662 static inline int pci_request_regions(struct pci_dev
*dev
, const char *res_name
)
1664 static inline void pci_release_regions(struct pci_dev
*dev
) { }
1666 static inline unsigned long pci_address_to_pio(phys_addr_t addr
) { return -1; }
1668 static inline void pci_block_cfg_access(struct pci_dev
*dev
) { }
1669 static inline int pci_block_cfg_access_in_atomic(struct pci_dev
*dev
)
1671 static inline void pci_unblock_cfg_access(struct pci_dev
*dev
) { }
1673 static inline struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
)
1675 static inline struct pci_dev
*pci_get_slot(struct pci_bus
*bus
,
1678 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
1681 static inline struct pci_dev
*pci_get_domain_bus_and_slot(int domain
,
1682 unsigned int bus
, unsigned int devfn
)
1685 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1686 static inline struct pci_dev
*pci_dev_get(struct pci_dev
*dev
) { return NULL
; }
1687 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1689 #define dev_is_pci(d) (false)
1690 #define dev_is_pf(d) (false)
1691 static inline bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
1693 static inline int pci_irqd_intx_xlate(struct irq_domain
*d
,
1694 struct device_node
*node
,
1696 unsigned int intsize
,
1697 unsigned long *out_hwirq
,
1698 unsigned int *out_type
)
1700 #endif /* CONFIG_PCI */
1702 /* Include architecture-dependent settings and functions */
1704 #include <asm/pci.h>
1706 /* These two functions provide almost identical functionality. Depennding
1707 * on the architecture, one will be implemented as a wrapper around the
1708 * other (in drivers/pci/mmap.c).
1710 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1711 * is expected to be an offset within that region.
1713 * pci_mmap_page_range() is the legacy architecture-specific interface,
1714 * which accepts a "user visible" resource address converted by
1715 * pci_resource_to_user(), as used in the legacy mmap() interface in
1718 int pci_mmap_resource_range(struct pci_dev
*dev
, int bar
,
1719 struct vm_area_struct
*vma
,
1720 enum pci_mmap_state mmap_state
, int write_combine
);
1721 int pci_mmap_page_range(struct pci_dev
*pdev
, int bar
,
1722 struct vm_area_struct
*vma
,
1723 enum pci_mmap_state mmap_state
, int write_combine
);
1725 #ifndef arch_can_pci_mmap_wc
1726 #define arch_can_pci_mmap_wc() 0
1729 #ifndef arch_can_pci_mmap_io
1730 #define arch_can_pci_mmap_io() 0
1731 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1733 int pci_iobar_pfn(struct pci_dev
*pdev
, int bar
, struct vm_area_struct
*vma
);
1736 #ifndef pci_root_bus_fwnode
1737 #define pci_root_bus_fwnode(bus) NULL
1740 /* these helpers provide future and backwards compatibility
1741 * for accessing popular PCI BAR info */
1742 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1743 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1744 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1745 #define pci_resource_len(dev,bar) \
1746 ((pci_resource_start((dev), (bar)) == 0 && \
1747 pci_resource_end((dev), (bar)) == \
1748 pci_resource_start((dev), (bar))) ? 0 : \
1750 (pci_resource_end((dev), (bar)) - \
1751 pci_resource_start((dev), (bar)) + 1))
1753 /* Similar to the helpers above, these manipulate per-pci_dev
1754 * driver-specific data. They are really just a wrapper around
1755 * the generic device structure functions of these calls.
1757 static inline void *pci_get_drvdata(struct pci_dev
*pdev
)
1759 return dev_get_drvdata(&pdev
->dev
);
1762 static inline void pci_set_drvdata(struct pci_dev
*pdev
, void *data
)
1764 dev_set_drvdata(&pdev
->dev
, data
);
1767 /* If you want to know what to call your pci_dev, ask this function.
1768 * Again, it's a wrapper around the generic device.
1770 static inline const char *pci_name(const struct pci_dev
*pdev
)
1772 return dev_name(&pdev
->dev
);
1776 /* Some archs don't want to expose struct resource to userland as-is
1777 * in sysfs and /proc
1779 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1780 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1781 const struct resource
*rsrc
,
1782 resource_size_t
*start
, resource_size_t
*end
);
1784 static inline void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1785 const struct resource
*rsrc
, resource_size_t
*start
,
1786 resource_size_t
*end
)
1788 *start
= rsrc
->start
;
1791 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1795 * The world is not perfect and supplies us with broken PCI devices.
1796 * For at least a part of these bugs we need a work-around, so both
1797 * generic (drivers/pci/quirks.c) and per-architecture code can define
1798 * fixup hooks to be called for particular buggy devices.
1802 u16 vendor
; /* You can use PCI_ANY_ID here of course */
1803 u16 device
; /* You can use PCI_ANY_ID here of course */
1804 u32
class; /* You can use PCI_ANY_ID here too */
1805 unsigned int class_shift
; /* should be 0, 8, 16 */
1806 void (*hook
)(struct pci_dev
*dev
);
1809 enum pci_fixup_pass
{
1810 pci_fixup_early
, /* Before probing BARs */
1811 pci_fixup_header
, /* After reading configuration header */
1812 pci_fixup_final
, /* Final phase of device fixups */
1813 pci_fixup_enable
, /* pci_enable_device() time */
1814 pci_fixup_resume
, /* pci_device_resume() */
1815 pci_fixup_suspend
, /* pci_device_suspend() */
1816 pci_fixup_resume_early
, /* pci_device_resume_early() */
1817 pci_fixup_suspend_late
, /* pci_device_suspend_late() */
1820 /* Anonymous variables would be nice... */
1821 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1822 class_shift, hook) \
1823 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1824 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1825 = { vendor, device, class, class_shift, hook };
1827 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1828 class_shift, hook) \
1829 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1830 hook, vendor, device, class, class_shift, hook)
1831 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1832 class_shift, hook) \
1833 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1834 hook, vendor, device, class, class_shift, hook)
1835 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1836 class_shift, hook) \
1837 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1838 hook, vendor, device, class, class_shift, hook)
1839 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1840 class_shift, hook) \
1841 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1842 hook, vendor, device, class, class_shift, hook)
1843 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1844 class_shift, hook) \
1845 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1846 resume##hook, vendor, device, class, \
1848 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1849 class_shift, hook) \
1850 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1851 resume_early##hook, vendor, device, \
1852 class, class_shift, hook)
1853 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1854 class_shift, hook) \
1855 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1856 suspend##hook, vendor, device, class, \
1858 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1859 class_shift, hook) \
1860 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1861 suspend_late##hook, vendor, device, \
1862 class, class_shift, hook)
1864 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1865 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1866 hook, vendor, device, PCI_ANY_ID, 0, hook)
1867 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1868 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1869 hook, vendor, device, PCI_ANY_ID, 0, hook)
1870 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1871 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1872 hook, vendor, device, PCI_ANY_ID, 0, hook)
1873 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1874 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1875 hook, vendor, device, PCI_ANY_ID, 0, hook)
1876 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1877 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1878 resume##hook, vendor, device, \
1879 PCI_ANY_ID, 0, hook)
1880 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1881 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1882 resume_early##hook, vendor, device, \
1883 PCI_ANY_ID, 0, hook)
1884 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1885 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1886 suspend##hook, vendor, device, \
1887 PCI_ANY_ID, 0, hook)
1888 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1889 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1890 suspend_late##hook, vendor, device, \
1891 PCI_ANY_ID, 0, hook)
1893 #ifdef CONFIG_PCI_QUIRKS
1894 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
);
1895 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
);
1896 int pci_dev_specific_enable_acs(struct pci_dev
*dev
);
1898 static inline void pci_fixup_device(enum pci_fixup_pass pass
,
1899 struct pci_dev
*dev
) { }
1900 static inline int pci_dev_specific_acs_enabled(struct pci_dev
*dev
,
1905 static inline int pci_dev_specific_enable_acs(struct pci_dev
*dev
)
1911 void __iomem
*pcim_iomap(struct pci_dev
*pdev
, int bar
, unsigned long maxlen
);
1912 void pcim_iounmap(struct pci_dev
*pdev
, void __iomem
*addr
);
1913 void __iomem
* const *pcim_iomap_table(struct pci_dev
*pdev
);
1914 int pcim_iomap_regions(struct pci_dev
*pdev
, int mask
, const char *name
);
1915 int pcim_iomap_regions_request_all(struct pci_dev
*pdev
, int mask
,
1917 void pcim_iounmap_regions(struct pci_dev
*pdev
, int mask
);
1919 extern int pci_pci_problems
;
1920 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1921 #define PCIPCI_TRITON 2
1922 #define PCIPCI_NATOMA 4
1923 #define PCIPCI_VIAETBF 8
1924 #define PCIPCI_VSFX 16
1925 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1926 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1928 extern unsigned long pci_cardbus_io_size
;
1929 extern unsigned long pci_cardbus_mem_size
;
1930 extern u8 pci_dfl_cache_line_size
;
1931 extern u8 pci_cache_line_size
;
1933 extern unsigned long pci_hotplug_io_size
;
1934 extern unsigned long pci_hotplug_mem_size
;
1935 extern unsigned long pci_hotplug_bus_size
;
1937 /* Architecture-specific versions may override these (weak) */
1938 void pcibios_disable_device(struct pci_dev
*dev
);
1939 void pcibios_set_master(struct pci_dev
*dev
);
1940 int pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1941 enum pcie_reset_state state
);
1942 int pcibios_add_device(struct pci_dev
*dev
);
1943 void pcibios_release_device(struct pci_dev
*dev
);
1944 void pcibios_penalize_isa_irq(int irq
, int active
);
1945 int pcibios_alloc_irq(struct pci_dev
*dev
);
1946 void pcibios_free_irq(struct pci_dev
*dev
);
1948 #ifdef CONFIG_HIBERNATE_CALLBACKS
1949 extern struct dev_pm_ops pcibios_pm_ops
;
1952 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1953 void __init
pci_mmcfg_early_init(void);
1954 void __init
pci_mmcfg_late_init(void);
1956 static inline void pci_mmcfg_early_init(void) { }
1957 static inline void pci_mmcfg_late_init(void) { }
1960 int pci_ext_cfg_avail(void);
1962 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
);
1963 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
);
1965 #ifdef CONFIG_PCI_IOV
1966 int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
);
1967 int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
);
1969 int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
);
1970 void pci_disable_sriov(struct pci_dev
*dev
);
1971 int pci_iov_add_virtfn(struct pci_dev
*dev
, int id
);
1972 void pci_iov_remove_virtfn(struct pci_dev
*dev
, int id
);
1973 int pci_num_vf(struct pci_dev
*dev
);
1974 int pci_vfs_assigned(struct pci_dev
*dev
);
1975 int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
);
1976 int pci_sriov_get_totalvfs(struct pci_dev
*dev
);
1977 resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
);
1979 static inline int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
)
1983 static inline int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
)
1987 static inline int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
)
1989 static inline int pci_iov_add_virtfn(struct pci_dev
*dev
, int id
)
1993 static inline void pci_iov_remove_virtfn(struct pci_dev
*dev
,
1995 static inline void pci_disable_sriov(struct pci_dev
*dev
) { }
1996 static inline int pci_num_vf(struct pci_dev
*dev
) { return 0; }
1997 static inline int pci_vfs_assigned(struct pci_dev
*dev
)
1999 static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
)
2001 static inline int pci_sriov_get_totalvfs(struct pci_dev
*dev
)
2003 static inline resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
)
2007 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2008 void pci_hp_create_module_link(struct pci_slot
*pci_slot
);
2009 void pci_hp_remove_module_link(struct pci_slot
*pci_slot
);
2013 * pci_pcie_cap - get the saved PCIe capability offset
2016 * PCIe capability offset is calculated at PCI device initialization
2017 * time and saved in the data structure. This function returns saved
2018 * PCIe capability offset. Using this instead of pci_find_capability()
2019 * reduces unnecessary search in the PCI configuration space. If you
2020 * need to calculate PCIe capability offset from raw device for some
2021 * reasons, please use pci_find_capability() instead.
2023 static inline int pci_pcie_cap(struct pci_dev
*dev
)
2025 return dev
->pcie_cap
;
2029 * pci_is_pcie - check if the PCI device is PCI Express capable
2032 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2034 static inline bool pci_is_pcie(struct pci_dev
*dev
)
2036 return pci_pcie_cap(dev
);
2040 * pcie_caps_reg - get the PCIe Capabilities Register
2043 static inline u16
pcie_caps_reg(const struct pci_dev
*dev
)
2045 return dev
->pcie_flags_reg
;
2049 * pci_pcie_type - get the PCIe device/port type
2052 static inline int pci_pcie_type(const struct pci_dev
*dev
)
2054 return (pcie_caps_reg(dev
) & PCI_EXP_FLAGS_TYPE
) >> 4;
2057 static inline struct pci_dev
*pcie_find_root_port(struct pci_dev
*dev
)
2060 if (!pci_is_pcie(dev
))
2062 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2064 if (!dev
->bus
->self
)
2066 dev
= dev
->bus
->self
;
2071 void pci_request_acs(void);
2072 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
);
2073 bool pci_acs_path_enabled(struct pci_dev
*start
,
2074 struct pci_dev
*end
, u16 acs_flags
);
2076 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2077 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2079 /* Large Resource Data Type Tag Item Names */
2080 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2081 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2082 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2084 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2085 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2086 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2088 /* Small Resource Data Type Tag Item Names */
2089 #define PCI_VPD_STIN_END 0x0f /* End */
2091 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2093 #define PCI_VPD_SRDT_TIN_MASK 0x78
2094 #define PCI_VPD_SRDT_LEN_MASK 0x07
2095 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2097 #define PCI_VPD_LRDT_TAG_SIZE 3
2098 #define PCI_VPD_SRDT_TAG_SIZE 1
2100 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2102 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2103 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2104 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2105 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2108 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2109 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2111 * Returns the extracted Large Resource Data Type length.
2113 static inline u16
pci_vpd_lrdt_size(const u8
*lrdt
)
2115 return (u16
)lrdt
[1] + ((u16
)lrdt
[2] << 8);
2119 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2120 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2122 * Returns the extracted Large Resource Data Type Tag item.
2124 static inline u16
pci_vpd_lrdt_tag(const u8
*lrdt
)
2126 return (u16
)(lrdt
[0] & PCI_VPD_LRDT_TIN_MASK
);
2130 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2131 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2133 * Returns the extracted Small Resource Data Type length.
2135 static inline u8
pci_vpd_srdt_size(const u8
*srdt
)
2137 return (*srdt
) & PCI_VPD_SRDT_LEN_MASK
;
2141 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2142 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2144 * Returns the extracted Small Resource Data Type Tag Item.
2146 static inline u8
pci_vpd_srdt_tag(const u8
*srdt
)
2148 return ((*srdt
) & PCI_VPD_SRDT_TIN_MASK
) >> 3;
2152 * pci_vpd_info_field_size - Extracts the information field length
2153 * @lrdt: Pointer to the beginning of an information field header
2155 * Returns the extracted information field length.
2157 static inline u8
pci_vpd_info_field_size(const u8
*info_field
)
2159 return info_field
[2];
2163 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2164 * @buf: Pointer to buffered vpd data
2165 * @off: The offset into the buffer at which to begin the search
2166 * @len: The length of the vpd buffer
2167 * @rdt: The Resource Data Type to search for
2169 * Returns the index where the Resource Data Type was found or
2170 * -ENOENT otherwise.
2172 int pci_vpd_find_tag(const u8
*buf
, unsigned int off
, unsigned int len
, u8 rdt
);
2175 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2176 * @buf: Pointer to buffered vpd data
2177 * @off: The offset into the buffer at which to begin the search
2178 * @len: The length of the buffer area, relative to off, in which to search
2179 * @kw: The keyword to search for
2181 * Returns the index where the information field keyword was found or
2182 * -ENOENT otherwise.
2184 int pci_vpd_find_info_keyword(const u8
*buf
, unsigned int off
,
2185 unsigned int len
, const char *kw
);
2187 /* PCI <-> OF binding helpers */
2191 void pci_set_of_node(struct pci_dev
*dev
);
2192 void pci_release_of_node(struct pci_dev
*dev
);
2193 void pci_set_bus_of_node(struct pci_bus
*bus
);
2194 void pci_release_bus_of_node(struct pci_bus
*bus
);
2195 struct irq_domain
*pci_host_bridge_of_msi_domain(struct pci_bus
*bus
);
2197 /* Arch may override this (weak) */
2198 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
);
2200 static inline struct device_node
*
2201 pci_device_to_OF_node(const struct pci_dev
*pdev
)
2203 return pdev
? pdev
->dev
.of_node
: NULL
;
2206 static inline struct device_node
*pci_bus_to_OF_node(struct pci_bus
*bus
)
2208 return bus
? bus
->dev
.of_node
: NULL
;
2211 #else /* CONFIG_OF */
2212 static inline void pci_set_of_node(struct pci_dev
*dev
) { }
2213 static inline void pci_release_of_node(struct pci_dev
*dev
) { }
2214 static inline void pci_set_bus_of_node(struct pci_bus
*bus
) { }
2215 static inline void pci_release_bus_of_node(struct pci_bus
*bus
) { }
2216 static inline struct device_node
*
2217 pci_device_to_OF_node(const struct pci_dev
*pdev
) { return NULL
; }
2218 static inline struct irq_domain
*
2219 pci_host_bridge_of_msi_domain(struct pci_bus
*bus
) { return NULL
; }
2220 #endif /* CONFIG_OF */
2223 struct irq_domain
*pci_host_bridge_acpi_msi_domain(struct pci_bus
*bus
);
2226 pci_msi_register_fwnode_provider(struct fwnode_handle
*(*fn
)(struct device
*));
2228 static inline struct irq_domain
*
2229 pci_host_bridge_acpi_msi_domain(struct pci_bus
*bus
) { return NULL
; }
2233 static inline struct eeh_dev
*pci_dev_to_eeh_dev(struct pci_dev
*pdev
)
2235 return pdev
->dev
.archdata
.edev
;
2239 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn
);
2240 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
);
2241 int pci_for_each_dma_alias(struct pci_dev
*pdev
,
2242 int (*fn
)(struct pci_dev
*pdev
,
2243 u16 alias
, void *data
), void *data
);
2245 /* helper functions for operation of device flag */
2246 static inline void pci_set_dev_assigned(struct pci_dev
*pdev
)
2248 pdev
->dev_flags
|= PCI_DEV_FLAGS_ASSIGNED
;
2250 static inline void pci_clear_dev_assigned(struct pci_dev
*pdev
)
2252 pdev
->dev_flags
&= ~PCI_DEV_FLAGS_ASSIGNED
;
2254 static inline bool pci_is_dev_assigned(struct pci_dev
*pdev
)
2256 return (pdev
->dev_flags
& PCI_DEV_FLAGS_ASSIGNED
) == PCI_DEV_FLAGS_ASSIGNED
;
2260 * pci_ari_enabled - query ARI forwarding status
2263 * Returns true if ARI forwarding is enabled.
2265 static inline bool pci_ari_enabled(struct pci_bus
*bus
)
2267 return bus
->self
&& bus
->self
->ari_enabled
;
2271 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2272 * @pdev: PCI device to check
2274 * Walk upwards from @pdev and check for each encountered bridge if it's part
2275 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2276 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2278 static inline bool pci_is_thunderbolt_attached(struct pci_dev
*pdev
)
2280 struct pci_dev
*parent
= pdev
;
2282 if (pdev
->is_thunderbolt
)
2285 while ((parent
= pci_upstream_bridge(parent
)))
2286 if (parent
->is_thunderbolt
)
2292 /* provide the legacy pci_dma_* API */
2293 #include <linux/pci-dma-compat.h>
2295 #endif /* LINUX_PCI_H */