4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus
*bus
; /* The bus this slot is on */
56 struct list_head list
; /* node in list of slots on this bus */
57 struct hotplug_slot
*hotplug
; /* Hotplug info (migrate over time) */
58 unsigned char number
; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot
*slot
)
64 return kobject_name(&slot
->kobj
);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
80 * For PCI devices, the region numbers are assigned this way:
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END
= 5,
87 /* #6: expansion ROM resource */
90 /* device specific resources */
93 PCI_IOV_RESOURCE_END
= PCI_IOV_RESOURCES
+ PCI_SRIOV_NUM_BARS
- 1,
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END
= PCI_BRIDGE_RESOURCES
+
101 PCI_BRIDGE_RESOURCE_NUM
- 1,
103 /* total resources associated with a PCI device */
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE
= PCI_NUM_RESOURCES
,
110 typedef int __bitwise pci_power_t
;
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names
[];
123 static inline const char *pci_power_name(pci_power_t state
)
125 return pci_power_names
[1 + (int) state
];
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
137 typedef unsigned int __bitwise pci_channel_state_t
;
139 enum pci_channel_state
{
140 /* I/O channel is in normal state */
141 pci_channel_io_normal
= (__force pci_channel_state_t
) 1,
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen
= (__force pci_channel_state_t
) 2,
146 /* PCI card is dead */
147 pci_channel_io_perm_failure
= (__force pci_channel_state_t
) 3,
150 typedef unsigned int __bitwise pcie_reset_state_t
;
152 enum pcie_reset_state
{
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset
= (__force pcie_reset_state_t
) 1,
156 /* Use #PERST to reset PCIe device */
157 pcie_warm_reset
= (__force pcie_reset_state_t
) 2,
159 /* Use PCIe Hot Reset to reset device */
160 pcie_hot_reset
= (__force pcie_reset_state_t
) 3
163 typedef unsigned short __bitwise pci_dev_flags_t
;
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
= (__force pci_dev_flags_t
) (1 << 0),
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3
= (__force pci_dev_flags_t
) (1 << 1),
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED
= (__force pci_dev_flags_t
) (1 << 2),
173 /* Flag for quirk use to store if quirk-specific ACS is enabled */
174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
= (__force pci_dev_flags_t
) (1 << 3),
175 /* Flag to indicate the device uses dma_alias_devfn */
176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN
= (__force pci_dev_flags_t
) (1 << 4),
177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
= (__force pci_dev_flags_t
) (1 << 5),
179 /* Do not use bus resets for device */
180 PCI_DEV_FLAGS_NO_BUS_RESET
= (__force pci_dev_flags_t
) (1 << 6),
181 /* Do not use PM reset even if device advertises NoSoftRst- */
182 PCI_DEV_FLAGS_NO_PM_RESET
= (__force pci_dev_flags_t
) (1 << 7),
185 enum pci_irq_reroute_variant
{
186 INTEL_IRQ_REROUTE_VARIANT
= 1,
187 MAX_IRQ_REROUTE_VARIANTS
= 3
190 typedef unsigned short __bitwise pci_bus_flags_t
;
192 PCI_BUS_FLAGS_NO_MSI
= (__force pci_bus_flags_t
) 1,
193 PCI_BUS_FLAGS_NO_MMRBC
= (__force pci_bus_flags_t
) 2,
196 /* These values come from the PCI Express Spec */
197 enum pcie_link_width
{
198 PCIE_LNK_WIDTH_RESRV
= 0x00,
206 PCIE_LNK_WIDTH_UNKNOWN
= 0xFF,
209 /* Based on the PCI Hotplug Spec, but some values are made up by us */
211 PCI_SPEED_33MHz
= 0x00,
212 PCI_SPEED_66MHz
= 0x01,
213 PCI_SPEED_66MHz_PCIX
= 0x02,
214 PCI_SPEED_100MHz_PCIX
= 0x03,
215 PCI_SPEED_133MHz_PCIX
= 0x04,
216 PCI_SPEED_66MHz_PCIX_ECC
= 0x05,
217 PCI_SPEED_100MHz_PCIX_ECC
= 0x06,
218 PCI_SPEED_133MHz_PCIX_ECC
= 0x07,
219 PCI_SPEED_66MHz_PCIX_266
= 0x09,
220 PCI_SPEED_100MHz_PCIX_266
= 0x0a,
221 PCI_SPEED_133MHz_PCIX_266
= 0x0b,
227 PCI_SPEED_66MHz_PCIX_533
= 0x11,
228 PCI_SPEED_100MHz_PCIX_533
= 0x12,
229 PCI_SPEED_133MHz_PCIX_533
= 0x13,
230 PCIE_SPEED_2_5GT
= 0x14,
231 PCIE_SPEED_5_0GT
= 0x15,
232 PCIE_SPEED_8_0GT
= 0x16,
233 PCI_SPEED_UNKNOWN
= 0xff,
236 struct pci_cap_saved_data
{
243 struct pci_cap_saved_state
{
244 struct hlist_node next
;
245 struct pci_cap_saved_data cap
;
248 struct pcie_link_state
;
254 * The pci_dev structure is used to describe PCI devices.
257 struct list_head bus_list
; /* node in per-bus list */
258 struct pci_bus
*bus
; /* bus this device is on */
259 struct pci_bus
*subordinate
; /* bus this device bridges to */
261 void *sysdata
; /* hook for sys-specific extension */
262 struct proc_dir_entry
*procent
; /* device entry in /proc/bus/pci */
263 struct pci_slot
*slot
; /* Physical slot this device is in */
265 unsigned int devfn
; /* encoded device & function index */
266 unsigned short vendor
;
267 unsigned short device
;
268 unsigned short subsystem_vendor
;
269 unsigned short subsystem_device
;
270 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
271 u8 revision
; /* PCI revision, low byte of class word */
272 u8 hdr_type
; /* PCI header type (`multi' flag masked out) */
273 u8 pcie_cap
; /* PCIe capability offset */
274 u8 msi_cap
; /* MSI capability offset */
275 u8 msix_cap
; /* MSI-X capability offset */
276 u8 pcie_mpss
:3; /* PCIe Max Payload Size Supported */
277 u8 rom_base_reg
; /* which config register controls the ROM */
278 u8 pin
; /* which interrupt pin this device uses */
279 u16 pcie_flags_reg
; /* cached PCIe Capabilities Register */
280 u8 dma_alias_devfn
;/* devfn of DMA alias, if any */
282 struct pci_driver
*driver
; /* which driver has allocated this device */
283 u64 dma_mask
; /* Mask of the bits of bus address this
284 device implements. Normally this is
285 0xffffffff. You only need to change
286 this if your device has broken DMA
287 or supports 64-bit transfers. */
289 struct device_dma_parameters dma_parms
;
291 pci_power_t current_state
; /* Current operating state. In ACPI-speak,
292 this is D0-D3, D0 being fully functional,
294 u8 pm_cap
; /* PM capability offset */
295 unsigned int pme_support
:5; /* Bitmask of states from which PME#
297 unsigned int pme_interrupt
:1;
298 unsigned int pme_poll
:1; /* Poll device's PME status bit */
299 unsigned int d1_support
:1; /* Low power state D1 is supported */
300 unsigned int d2_support
:1; /* Low power state D2 is supported */
301 unsigned int no_d1d2
:1; /* D1 and D2 are forbidden */
302 unsigned int no_d3cold
:1; /* D3cold is forbidden */
303 unsigned int d3cold_allowed
:1; /* D3cold is allowed by user */
304 unsigned int mmio_always_on
:1; /* disallow turning off io/mem
305 decoding during bar sizing */
306 unsigned int wakeup_prepared
:1;
307 unsigned int runtime_d3cold
:1; /* whether go through runtime
308 D3cold, not set for devices
309 powered on/off by the
310 corresponding bridge */
311 unsigned int ignore_hotplug
:1; /* Ignore hotplug events */
312 unsigned int d3_delay
; /* D3->D0 transition time in ms */
313 unsigned int d3cold_delay
; /* D3cold->D0 transition time in ms */
315 #ifdef CONFIG_PCIEASPM
316 struct pcie_link_state
*link_state
; /* ASPM link state */
319 pci_channel_state_t error_state
; /* current connectivity state */
320 struct device dev
; /* Generic device interface */
322 int cfg_size
; /* Size of configuration space */
325 * Instead of touching interrupt line and base address registers
326 * directly, use the values stored here. They might be different!
329 struct resource resource
[DEVICE_COUNT_RESOURCE
]; /* I/O and memory regions + expansion ROMs */
331 bool match_driver
; /* Skip attaching driver */
332 /* These fields are used by common fixups */
333 unsigned int transparent
:1; /* Subtractive decode PCI bridge */
334 unsigned int multifunction
:1;/* Part of multi-function device */
335 /* keep track of device state */
336 unsigned int is_added
:1;
337 unsigned int is_busmaster
:1; /* device is busmaster */
338 unsigned int no_msi
:1; /* device may not use msi */
339 unsigned int no_64bit_msi
:1; /* device may only use 32-bit MSIs */
340 unsigned int block_cfg_access
:1; /* config space access is blocked */
341 unsigned int broken_parity_status
:1; /* Device generates false positive parity */
342 unsigned int irq_reroute_variant
:2; /* device needs IRQ rerouting variant */
343 unsigned int msi_enabled
:1;
344 unsigned int msix_enabled
:1;
345 unsigned int ari_enabled
:1; /* ARI forwarding */
346 unsigned int ats_enabled
:1; /* Address Translation Service */
347 unsigned int is_managed
:1;
348 unsigned int needs_freset
:1; /* Dev requires fundamental reset */
349 unsigned int state_saved
:1;
350 unsigned int is_physfn
:1;
351 unsigned int is_virtfn
:1;
352 unsigned int reset_fn
:1;
353 unsigned int is_hotplug_bridge
:1;
354 unsigned int __aer_firmware_first_valid
:1;
355 unsigned int __aer_firmware_first
:1;
356 unsigned int broken_intx_masking
:1;
357 unsigned int io_window_1k
:1; /* Intel P2P bridge 1K I/O windows */
358 unsigned int irq_managed
:1;
359 unsigned int has_secondary_link
:1;
360 pci_dev_flags_t dev_flags
;
361 atomic_t enable_cnt
; /* pci_enable_device has been called */
363 u32 saved_config_space
[16]; /* config space saved at suspend time */
364 struct hlist_head saved_cap_space
;
365 struct bin_attribute
*rom_attr
; /* attribute descriptor for sysfs ROM entry */
366 int rom_attr_enabled
; /* has display of the rom attribute been enabled? */
367 struct bin_attribute
*res_attr
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for resources */
368 struct bin_attribute
*res_attr_wc
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for WC mapping of resources */
369 #ifdef CONFIG_PCI_MSI
370 struct list_head msi_list
;
371 const struct attribute_group
**msi_irq_groups
;
374 #ifdef CONFIG_PCI_ATS
376 struct pci_sriov
*sriov
; /* SR-IOV capability related */
377 struct pci_dev
*physfn
; /* the PF this VF is associated with */
379 u16 ats_cap
; /* ATS Capability offset */
380 u8 ats_stu
; /* ATS Smallest Translation Unit */
381 atomic_t ats_ref_cnt
; /* number of VFs with ATS enabled */
383 phys_addr_t rom
; /* Physical address of ROM if it's not from the BAR */
384 size_t romlen
; /* Length of ROM if it's not from the BAR */
385 char *driver_override
; /* Driver name to force a match */
388 static inline struct pci_dev
*pci_physfn(struct pci_dev
*dev
)
390 #ifdef CONFIG_PCI_IOV
397 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
);
399 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
400 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
402 static inline int pci_channel_offline(struct pci_dev
*pdev
)
404 return (pdev
->error_state
!= pci_channel_io_normal
);
407 struct pci_host_bridge
{
409 struct pci_bus
*bus
; /* root bus */
410 struct list_head windows
; /* resource_entry */
411 void (*release_fn
)(struct pci_host_bridge
*);
413 unsigned int ignore_reset_delay
:1; /* for entire hierarchy */
416 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
417 void pci_set_host_bridge_release(struct pci_host_bridge
*bridge
,
418 void (*release_fn
)(struct pci_host_bridge
*),
421 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
);
424 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
425 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
426 * buses below host bridges or subtractive decode bridges) go in the list.
427 * Use pci_bus_for_each_resource() to iterate through all the resources.
431 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
432 * and there's no way to program the bridge with the details of the window.
433 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
434 * decode bit set, because they are explicit and can be programmed with _SRS.
436 #define PCI_SUBTRACTIVE_DECODE 0x1
438 struct pci_bus_resource
{
439 struct list_head list
;
440 struct resource
*res
;
444 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
447 struct list_head node
; /* node in list of buses */
448 struct pci_bus
*parent
; /* parent bus this bridge is on */
449 struct list_head children
; /* list of child buses */
450 struct list_head devices
; /* list of devices on this bus */
451 struct pci_dev
*self
; /* bridge device as seen by parent */
452 struct list_head slots
; /* list of slots on this bus */
453 struct resource
*resource
[PCI_BRIDGE_RESOURCE_NUM
];
454 struct list_head resources
; /* address space routed to this bus */
455 struct resource busn_res
; /* bus numbers routed to this bus */
457 struct pci_ops
*ops
; /* configuration access functions */
458 struct msi_controller
*msi
; /* MSI controller */
459 void *sysdata
; /* hook for sys-specific extension */
460 struct proc_dir_entry
*procdir
; /* directory entry in /proc/bus/pci */
462 unsigned char number
; /* bus number */
463 unsigned char primary
; /* number of primary bridge */
464 unsigned char max_bus_speed
; /* enum pci_bus_speed */
465 unsigned char cur_bus_speed
; /* enum pci_bus_speed */
466 #ifdef CONFIG_PCI_DOMAINS_GENERIC
472 unsigned short bridge_ctl
; /* manage NO_ISA/FBB/et al behaviors */
473 pci_bus_flags_t bus_flags
; /* inherited by child buses */
474 struct device
*bridge
;
476 struct bin_attribute
*legacy_io
; /* legacy I/O for this bus */
477 struct bin_attribute
*legacy_mem
; /* legacy mem */
478 unsigned int is_added
:1;
481 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
484 * Returns true if the PCI bus is root (behind host-PCI bridge),
487 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
488 * This is incorrect because "virtual" buses added for SR-IOV (via
489 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
491 static inline bool pci_is_root_bus(struct pci_bus
*pbus
)
493 return !(pbus
->parent
);
497 * pci_is_bridge - check if the PCI device is a bridge
500 * Return true if the PCI device is bridge whether it has subordinate
503 static inline bool pci_is_bridge(struct pci_dev
*dev
)
505 return dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
506 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
;
509 static inline struct pci_dev
*pci_upstream_bridge(struct pci_dev
*dev
)
511 dev
= pci_physfn(dev
);
512 if (pci_is_root_bus(dev
->bus
))
515 return dev
->bus
->self
;
518 struct device
*pci_get_host_bridge_device(struct pci_dev
*dev
);
519 void pci_put_host_bridge_device(struct device
*dev
);
521 #ifdef CONFIG_PCI_MSI
522 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
)
524 return pci_dev
->msi_enabled
|| pci_dev
->msix_enabled
;
527 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
) { return false; }
531 * Error values that may be returned by PCI functions.
533 #define PCIBIOS_SUCCESSFUL 0x00
534 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
535 #define PCIBIOS_BAD_VENDOR_ID 0x83
536 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
537 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
538 #define PCIBIOS_SET_FAILED 0x88
539 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
542 * Translate above to generic errno for passing back through non-PCI code.
544 static inline int pcibios_err_to_errno(int err
)
546 if (err
<= PCIBIOS_SUCCESSFUL
)
547 return err
; /* Assume already errno */
550 case PCIBIOS_FUNC_NOT_SUPPORTED
:
552 case PCIBIOS_BAD_VENDOR_ID
:
554 case PCIBIOS_DEVICE_NOT_FOUND
:
556 case PCIBIOS_BAD_REGISTER_NUMBER
:
558 case PCIBIOS_SET_FAILED
:
560 case PCIBIOS_BUFFER_TOO_SMALL
:
567 /* Low-level architecture-dependent routines */
570 void __iomem
*(*map_bus
)(struct pci_bus
*bus
, unsigned int devfn
, int where
);
571 int (*read
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
572 int (*write
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
576 * ACPI needs to be able to access PCI config space before we've done a
577 * PCI bus scan and created pci_bus structures.
579 int raw_pci_read(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
580 int reg
, int len
, u32
*val
);
581 int raw_pci_write(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
582 int reg
, int len
, u32 val
);
584 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
585 typedef u64 pci_bus_addr_t
;
587 typedef u32 pci_bus_addr_t
;
590 struct pci_bus_region
{
591 pci_bus_addr_t start
;
596 spinlock_t lock
; /* protects list, index */
597 struct list_head list
; /* for IDs added at runtime */
602 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
603 * a set of callbacks in struct pci_error_handlers, that device driver
604 * will be notified of PCI bus errors, and will be driven to recovery
605 * when an error occurs.
608 typedef unsigned int __bitwise pci_ers_result_t
;
610 enum pci_ers_result
{
611 /* no result/none/not supported in device driver */
612 PCI_ERS_RESULT_NONE
= (__force pci_ers_result_t
) 1,
614 /* Device driver can recover without slot reset */
615 PCI_ERS_RESULT_CAN_RECOVER
= (__force pci_ers_result_t
) 2,
617 /* Device driver wants slot to be reset. */
618 PCI_ERS_RESULT_NEED_RESET
= (__force pci_ers_result_t
) 3,
620 /* Device has completely failed, is unrecoverable */
621 PCI_ERS_RESULT_DISCONNECT
= (__force pci_ers_result_t
) 4,
623 /* Device driver is fully recovered and operational */
624 PCI_ERS_RESULT_RECOVERED
= (__force pci_ers_result_t
) 5,
626 /* No AER capabilities registered for the driver */
627 PCI_ERS_RESULT_NO_AER_DRIVER
= (__force pci_ers_result_t
) 6,
630 /* PCI bus error event callbacks */
631 struct pci_error_handlers
{
632 /* PCI bus error detected on this device */
633 pci_ers_result_t (*error_detected
)(struct pci_dev
*dev
,
634 enum pci_channel_state error
);
636 /* MMIO has been re-enabled, but not DMA */
637 pci_ers_result_t (*mmio_enabled
)(struct pci_dev
*dev
);
639 /* PCI Express link has been reset */
640 pci_ers_result_t (*link_reset
)(struct pci_dev
*dev
);
642 /* PCI slot has been reset */
643 pci_ers_result_t (*slot_reset
)(struct pci_dev
*dev
);
645 /* PCI function reset prepare or completed */
646 void (*reset_notify
)(struct pci_dev
*dev
, bool prepare
);
648 /* Device driver may resume normal operations */
649 void (*resume
)(struct pci_dev
*dev
);
655 struct list_head node
;
657 const struct pci_device_id
*id_table
; /* must be non-NULL for probe to be called */
658 int (*probe
) (struct pci_dev
*dev
, const struct pci_device_id
*id
); /* New device inserted */
659 void (*remove
) (struct pci_dev
*dev
); /* Device removed (NULL if not a hot-plug capable driver) */
660 int (*suspend
) (struct pci_dev
*dev
, pm_message_t state
); /* Device suspended */
661 int (*suspend_late
) (struct pci_dev
*dev
, pm_message_t state
);
662 int (*resume_early
) (struct pci_dev
*dev
);
663 int (*resume
) (struct pci_dev
*dev
); /* Device woken up */
664 void (*shutdown
) (struct pci_dev
*dev
);
665 int (*sriov_configure
) (struct pci_dev
*dev
, int num_vfs
); /* PF pdev */
666 const struct pci_error_handlers
*err_handler
;
667 struct device_driver driver
;
668 struct pci_dynids dynids
;
671 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
674 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
675 * @_table: device table name
677 * This macro is deprecated and should not be used in new code.
679 #define DEFINE_PCI_DEVICE_TABLE(_table) \
680 const struct pci_device_id _table[]
683 * PCI_DEVICE - macro used to describe a specific pci device
684 * @vend: the 16 bit PCI Vendor ID
685 * @dev: the 16 bit PCI Device ID
687 * This macro is used to create a struct pci_device_id that matches a
688 * specific device. The subvendor and subdevice fields will be set to
691 #define PCI_DEVICE(vend,dev) \
692 .vendor = (vend), .device = (dev), \
693 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
696 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
697 * @vend: the 16 bit PCI Vendor ID
698 * @dev: the 16 bit PCI Device ID
699 * @subvend: the 16 bit PCI Subvendor ID
700 * @subdev: the 16 bit PCI Subdevice ID
702 * This macro is used to create a struct pci_device_id that matches a
703 * specific device with subsystem information.
705 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
706 .vendor = (vend), .device = (dev), \
707 .subvendor = (subvend), .subdevice = (subdev)
710 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
711 * @dev_class: the class, subclass, prog-if triple for this device
712 * @dev_class_mask: the class mask for this device
714 * This macro is used to create a struct pci_device_id that matches a
715 * specific PCI class. The vendor, device, subvendor, and subdevice
716 * fields will be set to PCI_ANY_ID.
718 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
719 .class = (dev_class), .class_mask = (dev_class_mask), \
720 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
721 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
724 * PCI_VDEVICE - macro used to describe a specific pci device in short form
725 * @vend: the vendor name
726 * @dev: the 16 bit PCI Device ID
728 * This macro is used to create a struct pci_device_id that matches a
729 * specific PCI device. The subvendor, and subdevice fields will be set
730 * to PCI_ANY_ID. The macro allows the next field to follow as the device
734 #define PCI_VDEVICE(vend, dev) \
735 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
736 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
738 /* these external functions are only available when PCI support is enabled */
741 void pcie_bus_configure_settings(struct pci_bus
*bus
);
743 enum pcie_bus_config_types
{
746 PCIE_BUS_PERFORMANCE
,
750 extern enum pcie_bus_config_types pcie_bus_config
;
752 extern struct bus_type pci_bus_type
;
754 /* Do NOT directly access these two variables, unless you are arch-specific PCI
755 * code, or PCI core code. */
756 extern struct list_head pci_root_buses
; /* list of all known PCI buses */
757 /* Some device drivers need know if PCI is initiated */
758 int no_pci_devices(void);
760 void pcibios_resource_survey_bus(struct pci_bus
*bus
);
761 void pcibios_add_bus(struct pci_bus
*bus
);
762 void pcibios_remove_bus(struct pci_bus
*bus
);
763 void pcibios_fixup_bus(struct pci_bus
*);
764 int __must_check
pcibios_enable_device(struct pci_dev
*, int mask
);
765 /* Architecture-specific versions may override this (weak) */
766 char *pcibios_setup(char *str
);
768 /* Used only when drivers/pci/setup.c is used */
769 resource_size_t
pcibios_align_resource(void *, const struct resource
*,
772 void pcibios_update_irq(struct pci_dev
*, int irq
);
774 /* Weak but can be overriden by arch */
775 void pci_fixup_cardbus(struct pci_bus
*);
777 /* Generic PCI functions used internally */
779 void pcibios_resource_to_bus(struct pci_bus
*bus
, struct pci_bus_region
*region
,
780 struct resource
*res
);
781 void pcibios_bus_to_resource(struct pci_bus
*bus
, struct resource
*res
,
782 struct pci_bus_region
*region
);
783 void pcibios_scan_specific_bus(int busn
);
784 struct pci_bus
*pci_find_bus(int domain
, int busnr
);
785 void pci_bus_add_devices(const struct pci_bus
*bus
);
786 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
);
787 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
788 struct pci_ops
*ops
, void *sysdata
,
789 struct list_head
*resources
);
790 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int busmax
);
791 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int busmax
);
792 void pci_bus_release_busn_res(struct pci_bus
*b
);
793 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
794 struct pci_ops
*ops
, void *sysdata
,
795 struct list_head
*resources
);
796 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
798 void pcie_update_link_speed(struct pci_bus
*bus
, u16 link_status
);
799 struct pci_slot
*pci_create_slot(struct pci_bus
*parent
, int slot_nr
,
801 struct hotplug_slot
*hotplug
);
802 void pci_destroy_slot(struct pci_slot
*slot
);
803 int pci_scan_slot(struct pci_bus
*bus
, int devfn
);
804 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
);
805 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
);
806 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
807 void pci_bus_add_device(struct pci_dev
*dev
);
808 void pci_read_bridge_bases(struct pci_bus
*child
);
809 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
810 struct resource
*res
);
811 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
);
812 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
);
813 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
);
814 struct pci_dev
*pci_dev_get(struct pci_dev
*dev
);
815 void pci_dev_put(struct pci_dev
*dev
);
816 void pci_remove_bus(struct pci_bus
*b
);
817 void pci_stop_and_remove_bus_device(struct pci_dev
*dev
);
818 void pci_stop_and_remove_bus_device_locked(struct pci_dev
*dev
);
819 void pci_stop_root_bus(struct pci_bus
*bus
);
820 void pci_remove_root_bus(struct pci_bus
*bus
);
821 void pci_setup_cardbus(struct pci_bus
*bus
);
822 void pci_sort_breadthfirst(void);
823 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
824 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
825 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
827 /* Generic PCI functions exported to card drivers */
829 enum pci_lost_interrupt_reason
{
830 PCI_LOST_IRQ_NO_INFORMATION
= 0,
831 PCI_LOST_IRQ_DISABLE_MSI
,
832 PCI_LOST_IRQ_DISABLE_MSIX
,
833 PCI_LOST_IRQ_DISABLE_ACPI
,
835 enum pci_lost_interrupt_reason
pci_lost_interrupt(struct pci_dev
*dev
);
836 int pci_find_capability(struct pci_dev
*dev
, int cap
);
837 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
);
838 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
);
839 int pci_find_next_ext_capability(struct pci_dev
*dev
, int pos
, int cap
);
840 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
);
841 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
);
842 struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
);
844 struct pci_dev
*pci_get_device(unsigned int vendor
, unsigned int device
,
845 struct pci_dev
*from
);
846 struct pci_dev
*pci_get_subsys(unsigned int vendor
, unsigned int device
,
847 unsigned int ss_vendor
, unsigned int ss_device
,
848 struct pci_dev
*from
);
849 struct pci_dev
*pci_get_slot(struct pci_bus
*bus
, unsigned int devfn
);
850 struct pci_dev
*pci_get_domain_bus_and_slot(int domain
, unsigned int bus
,
852 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
855 return pci_get_domain_bus_and_slot(0, bus
, devfn
);
857 struct pci_dev
*pci_get_class(unsigned int class, struct pci_dev
*from
);
858 int pci_dev_present(const struct pci_device_id
*ids
);
860 int pci_bus_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
862 int pci_bus_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
863 int where
, u16
*val
);
864 int pci_bus_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
865 int where
, u32
*val
);
866 int pci_bus_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
868 int pci_bus_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
870 int pci_bus_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
873 int pci_generic_config_read(struct pci_bus
*bus
, unsigned int devfn
,
874 int where
, int size
, u32
*val
);
875 int pci_generic_config_write(struct pci_bus
*bus
, unsigned int devfn
,
876 int where
, int size
, u32 val
);
877 int pci_generic_config_read32(struct pci_bus
*bus
, unsigned int devfn
,
878 int where
, int size
, u32
*val
);
879 int pci_generic_config_write32(struct pci_bus
*bus
, unsigned int devfn
,
880 int where
, int size
, u32 val
);
882 struct pci_ops
*pci_bus_set_ops(struct pci_bus
*bus
, struct pci_ops
*ops
);
884 static inline int pci_read_config_byte(const struct pci_dev
*dev
, int where
, u8
*val
)
886 return pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
888 static inline int pci_read_config_word(const struct pci_dev
*dev
, int where
, u16
*val
)
890 return pci_bus_read_config_word(dev
->bus
, dev
->devfn
, where
, val
);
892 static inline int pci_read_config_dword(const struct pci_dev
*dev
, int where
,
895 return pci_bus_read_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
897 static inline int pci_write_config_byte(const struct pci_dev
*dev
, int where
, u8 val
)
899 return pci_bus_write_config_byte(dev
->bus
, dev
->devfn
, where
, val
);
901 static inline int pci_write_config_word(const struct pci_dev
*dev
, int where
, u16 val
)
903 return pci_bus_write_config_word(dev
->bus
, dev
->devfn
, where
, val
);
905 static inline int pci_write_config_dword(const struct pci_dev
*dev
, int where
,
908 return pci_bus_write_config_dword(dev
->bus
, dev
->devfn
, where
, val
);
911 int pcie_capability_read_word(struct pci_dev
*dev
, int pos
, u16
*val
);
912 int pcie_capability_read_dword(struct pci_dev
*dev
, int pos
, u32
*val
);
913 int pcie_capability_write_word(struct pci_dev
*dev
, int pos
, u16 val
);
914 int pcie_capability_write_dword(struct pci_dev
*dev
, int pos
, u32 val
);
915 int pcie_capability_clear_and_set_word(struct pci_dev
*dev
, int pos
,
917 int pcie_capability_clear_and_set_dword(struct pci_dev
*dev
, int pos
,
920 static inline int pcie_capability_set_word(struct pci_dev
*dev
, int pos
,
923 return pcie_capability_clear_and_set_word(dev
, pos
, 0, set
);
926 static inline int pcie_capability_set_dword(struct pci_dev
*dev
, int pos
,
929 return pcie_capability_clear_and_set_dword(dev
, pos
, 0, set
);
932 static inline int pcie_capability_clear_word(struct pci_dev
*dev
, int pos
,
935 return pcie_capability_clear_and_set_word(dev
, pos
, clear
, 0);
938 static inline int pcie_capability_clear_dword(struct pci_dev
*dev
, int pos
,
941 return pcie_capability_clear_and_set_dword(dev
, pos
, clear
, 0);
944 /* user-space driven config access */
945 int pci_user_read_config_byte(struct pci_dev
*dev
, int where
, u8
*val
);
946 int pci_user_read_config_word(struct pci_dev
*dev
, int where
, u16
*val
);
947 int pci_user_read_config_dword(struct pci_dev
*dev
, int where
, u32
*val
);
948 int pci_user_write_config_byte(struct pci_dev
*dev
, int where
, u8 val
);
949 int pci_user_write_config_word(struct pci_dev
*dev
, int where
, u16 val
);
950 int pci_user_write_config_dword(struct pci_dev
*dev
, int where
, u32 val
);
952 int __must_check
pci_enable_device(struct pci_dev
*dev
);
953 int __must_check
pci_enable_device_io(struct pci_dev
*dev
);
954 int __must_check
pci_enable_device_mem(struct pci_dev
*dev
);
955 int __must_check
pci_reenable_device(struct pci_dev
*);
956 int __must_check
pcim_enable_device(struct pci_dev
*pdev
);
957 void pcim_pin_device(struct pci_dev
*pdev
);
959 static inline int pci_is_enabled(struct pci_dev
*pdev
)
961 return (atomic_read(&pdev
->enable_cnt
) > 0);
964 static inline int pci_is_managed(struct pci_dev
*pdev
)
966 return pdev
->is_managed
;
969 void pci_disable_device(struct pci_dev
*dev
);
971 extern unsigned int pcibios_max_latency
;
972 void pci_set_master(struct pci_dev
*dev
);
973 void pci_clear_master(struct pci_dev
*dev
);
975 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
);
976 int pci_set_cacheline_size(struct pci_dev
*dev
);
977 #define HAVE_PCI_SET_MWI
978 int __must_check
pci_set_mwi(struct pci_dev
*dev
);
979 int pci_try_set_mwi(struct pci_dev
*dev
);
980 void pci_clear_mwi(struct pci_dev
*dev
);
981 void pci_intx(struct pci_dev
*dev
, int enable
);
982 bool pci_intx_mask_supported(struct pci_dev
*dev
);
983 bool pci_check_and_mask_intx(struct pci_dev
*dev
);
984 bool pci_check_and_unmask_intx(struct pci_dev
*dev
);
985 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
);
986 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
);
987 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
);
988 int pci_wait_for_pending_transaction(struct pci_dev
*dev
);
989 int pcix_get_max_mmrbc(struct pci_dev
*dev
);
990 int pcix_get_mmrbc(struct pci_dev
*dev
);
991 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
);
992 int pcie_get_readrq(struct pci_dev
*dev
);
993 int pcie_set_readrq(struct pci_dev
*dev
, int rq
);
994 int pcie_get_mps(struct pci_dev
*dev
);
995 int pcie_set_mps(struct pci_dev
*dev
, int mps
);
996 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
997 enum pcie_link_width
*width
);
998 int __pci_reset_function(struct pci_dev
*dev
);
999 int __pci_reset_function_locked(struct pci_dev
*dev
);
1000 int pci_reset_function(struct pci_dev
*dev
);
1001 int pci_try_reset_function(struct pci_dev
*dev
);
1002 int pci_probe_reset_slot(struct pci_slot
*slot
);
1003 int pci_reset_slot(struct pci_slot
*slot
);
1004 int pci_try_reset_slot(struct pci_slot
*slot
);
1005 int pci_probe_reset_bus(struct pci_bus
*bus
);
1006 int pci_reset_bus(struct pci_bus
*bus
);
1007 int pci_try_reset_bus(struct pci_bus
*bus
);
1008 void pci_reset_secondary_bus(struct pci_dev
*dev
);
1009 void pcibios_reset_secondary_bus(struct pci_dev
*dev
);
1010 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
);
1011 void pci_update_resource(struct pci_dev
*dev
, int resno
);
1012 int __must_check
pci_assign_resource(struct pci_dev
*dev
, int i
);
1013 int __must_check
pci_reassign_resource(struct pci_dev
*dev
, int i
, resource_size_t add_size
, resource_size_t align
);
1014 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
);
1015 bool pci_device_is_present(struct pci_dev
*pdev
);
1016 void pci_ignore_hotplug(struct pci_dev
*dev
);
1018 /* ROM control related routines */
1019 int pci_enable_rom(struct pci_dev
*pdev
);
1020 void pci_disable_rom(struct pci_dev
*pdev
);
1021 void __iomem __must_check
*pci_map_rom(struct pci_dev
*pdev
, size_t *size
);
1022 void pci_unmap_rom(struct pci_dev
*pdev
, void __iomem
*rom
);
1023 size_t pci_get_rom_size(struct pci_dev
*pdev
, void __iomem
*rom
, size_t size
);
1024 void __iomem __must_check
*pci_platform_rom(struct pci_dev
*pdev
, size_t *size
);
1026 /* Power management related routines */
1027 int pci_save_state(struct pci_dev
*dev
);
1028 void pci_restore_state(struct pci_dev
*dev
);
1029 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
);
1030 int pci_load_saved_state(struct pci_dev
*dev
,
1031 struct pci_saved_state
*state
);
1032 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1033 struct pci_saved_state
**state
);
1034 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
);
1035 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
,
1037 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
);
1038 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
,
1039 u16 cap
, unsigned int size
);
1040 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
);
1041 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
);
1042 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
);
1043 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
);
1044 void pci_pme_active(struct pci_dev
*dev
, bool enable
);
1045 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1046 bool runtime
, bool enable
);
1047 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
);
1048 int pci_prepare_to_sleep(struct pci_dev
*dev
);
1049 int pci_back_from_sleep(struct pci_dev
*dev
);
1050 bool pci_dev_run_wake(struct pci_dev
*dev
);
1051 bool pci_check_pme_status(struct pci_dev
*dev
);
1052 void pci_pme_wakeup_bus(struct pci_bus
*bus
);
1054 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1057 return __pci_enable_wake(dev
, state
, false, enable
);
1060 /* PCI Virtual Channel */
1061 int pci_save_vc_state(struct pci_dev
*dev
);
1062 void pci_restore_vc_state(struct pci_dev
*dev
);
1063 void pci_allocate_vc_save_buffers(struct pci_dev
*dev
);
1065 /* For use by arch with custom probe code */
1066 void set_pcie_port_type(struct pci_dev
*pdev
);
1067 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
);
1069 /* Functions for PCI Hotplug drivers to use */
1070 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1071 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
);
1072 unsigned int pci_rescan_bus(struct pci_bus
*bus
);
1073 void pci_lock_rescan_remove(void);
1074 void pci_unlock_rescan_remove(void);
1076 /* Vital product data routines */
1077 ssize_t
pci_read_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, void *buf
);
1078 ssize_t
pci_write_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, const void *buf
);
1080 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1081 resource_size_t
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
);
1082 void pci_bus_assign_resources(const struct pci_bus
*bus
);
1083 void pci_bus_size_bridges(struct pci_bus
*bus
);
1084 int pci_claim_resource(struct pci_dev
*, int);
1085 int pci_claim_bridge_resource(struct pci_dev
*bridge
, int i
);
1086 void pci_assign_unassigned_resources(void);
1087 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
);
1088 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
);
1089 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
);
1090 void pdev_enable_device(struct pci_dev
*);
1091 int pci_enable_resources(struct pci_dev
*, int mask
);
1092 void pci_fixup_irqs(u8 (*)(struct pci_dev
*, u8
*),
1093 int (*)(const struct pci_dev
*, u8
, u8
));
1094 #define HAVE_PCI_REQ_REGIONS 2
1095 int __must_check
pci_request_regions(struct pci_dev
*, const char *);
1096 int __must_check
pci_request_regions_exclusive(struct pci_dev
*, const char *);
1097 void pci_release_regions(struct pci_dev
*);
1098 int __must_check
pci_request_region(struct pci_dev
*, int, const char *);
1099 int __must_check
pci_request_region_exclusive(struct pci_dev
*, int, const char *);
1100 void pci_release_region(struct pci_dev
*, int);
1101 int pci_request_selected_regions(struct pci_dev
*, int, const char *);
1102 int pci_request_selected_regions_exclusive(struct pci_dev
*, int, const char *);
1103 void pci_release_selected_regions(struct pci_dev
*, int);
1105 /* drivers/pci/bus.c */
1106 struct pci_bus
*pci_bus_get(struct pci_bus
*bus
);
1107 void pci_bus_put(struct pci_bus
*bus
);
1108 void pci_add_resource(struct list_head
*resources
, struct resource
*res
);
1109 void pci_add_resource_offset(struct list_head
*resources
, struct resource
*res
,
1110 resource_size_t offset
);
1111 void pci_free_resource_list(struct list_head
*resources
);
1112 void pci_bus_add_resource(struct pci_bus
*bus
, struct resource
*res
, unsigned int flags
);
1113 struct resource
*pci_bus_resource_n(const struct pci_bus
*bus
, int n
);
1114 void pci_bus_remove_resources(struct pci_bus
*bus
);
1116 #define pci_bus_for_each_resource(bus, res, i) \
1118 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1121 int __must_check
pci_bus_alloc_resource(struct pci_bus
*bus
,
1122 struct resource
*res
, resource_size_t size
,
1123 resource_size_t align
, resource_size_t min
,
1124 unsigned long type_mask
,
1125 resource_size_t (*alignf
)(void *,
1126 const struct resource
*,
1132 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
);
1134 static inline pci_bus_addr_t
pci_bus_address(struct pci_dev
*pdev
, int bar
)
1136 struct pci_bus_region region
;
1138 pcibios_resource_to_bus(pdev
->bus
, ®ion
, &pdev
->resource
[bar
]);
1139 return region
.start
;
1142 /* Proper probing supporting hot-pluggable devices */
1143 int __must_check
__pci_register_driver(struct pci_driver
*, struct module
*,
1144 const char *mod_name
);
1147 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1149 #define pci_register_driver(driver) \
1150 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1152 void pci_unregister_driver(struct pci_driver
*dev
);
1155 * module_pci_driver() - Helper macro for registering a PCI driver
1156 * @__pci_driver: pci_driver struct
1158 * Helper macro for PCI drivers which do not do anything special in module
1159 * init/exit. This eliminates a lot of boilerplate. Each module may only
1160 * use this macro once, and calling it replaces module_init() and module_exit()
1162 #define module_pci_driver(__pci_driver) \
1163 module_driver(__pci_driver, pci_register_driver, \
1164 pci_unregister_driver)
1166 struct pci_driver
*pci_dev_driver(const struct pci_dev
*dev
);
1167 int pci_add_dynid(struct pci_driver
*drv
,
1168 unsigned int vendor
, unsigned int device
,
1169 unsigned int subvendor
, unsigned int subdevice
,
1170 unsigned int class, unsigned int class_mask
,
1171 unsigned long driver_data
);
1172 const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1173 struct pci_dev
*dev
);
1174 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
,
1177 void pci_walk_bus(struct pci_bus
*top
, int (*cb
)(struct pci_dev
*, void *),
1179 int pci_cfg_space_size(struct pci_dev
*dev
);
1180 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
);
1181 void pci_setup_bridge(struct pci_bus
*bus
);
1182 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
1183 unsigned long type
);
1184 resource_size_t
pcibios_iov_resource_alignment(struct pci_dev
*dev
, int resno
);
1186 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1187 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1189 int pci_set_vga_state(struct pci_dev
*pdev
, bool decode
,
1190 unsigned int command_bits
, u32 flags
);
1191 /* kmem_cache style wrapper around pci_alloc_consistent() */
1193 #include <linux/pci-dma.h>
1194 #include <linux/dmapool.h>
1196 #define pci_pool dma_pool
1197 #define pci_pool_create(name, pdev, size, align, allocation) \
1198 dma_pool_create(name, &pdev->dev, size, align, allocation)
1199 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1200 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1201 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1204 u32 vector
; /* kernel uses to write allocated vector */
1205 u16 entry
; /* driver uses to specify entry, OS writes */
1209 #ifdef CONFIG_PCI_MSI
1210 int pci_msi_vec_count(struct pci_dev
*dev
);
1211 void pci_msi_shutdown(struct pci_dev
*dev
);
1212 void pci_disable_msi(struct pci_dev
*dev
);
1213 int pci_msix_vec_count(struct pci_dev
*dev
);
1214 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
);
1215 void pci_msix_shutdown(struct pci_dev
*dev
);
1216 void pci_disable_msix(struct pci_dev
*dev
);
1217 void pci_restore_msi_state(struct pci_dev
*dev
);
1218 int pci_msi_enabled(void);
1219 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
);
1220 static inline int pci_enable_msi_exact(struct pci_dev
*dev
, int nvec
)
1222 int rc
= pci_enable_msi_range(dev
, nvec
, nvec
);
1227 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1228 int minvec
, int maxvec
);
1229 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1230 struct msix_entry
*entries
, int nvec
)
1232 int rc
= pci_enable_msix_range(dev
, entries
, nvec
, nvec
);
1238 static inline int pci_msi_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1239 static inline void pci_msi_shutdown(struct pci_dev
*dev
) { }
1240 static inline void pci_disable_msi(struct pci_dev
*dev
) { }
1241 static inline int pci_msix_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1242 static inline int pci_enable_msix(struct pci_dev
*dev
,
1243 struct msix_entry
*entries
, int nvec
)
1245 static inline void pci_msix_shutdown(struct pci_dev
*dev
) { }
1246 static inline void pci_disable_msix(struct pci_dev
*dev
) { }
1247 static inline void pci_restore_msi_state(struct pci_dev
*dev
) { }
1248 static inline int pci_msi_enabled(void) { return 0; }
1249 static inline int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
,
1252 static inline int pci_enable_msi_exact(struct pci_dev
*dev
, int nvec
)
1254 static inline int pci_enable_msix_range(struct pci_dev
*dev
,
1255 struct msix_entry
*entries
, int minvec
, int maxvec
)
1257 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1258 struct msix_entry
*entries
, int nvec
)
1262 #ifdef CONFIG_PCIEPORTBUS
1263 extern bool pcie_ports_disabled
;
1264 extern bool pcie_ports_auto
;
1266 #define pcie_ports_disabled true
1267 #define pcie_ports_auto false
1270 #ifdef CONFIG_PCIEASPM
1271 bool pcie_aspm_support_enabled(void);
1273 static inline bool pcie_aspm_support_enabled(void) { return false; }
1276 #ifdef CONFIG_PCIEAER
1277 void pci_no_aer(void);
1278 bool pci_aer_available(void);
1280 static inline void pci_no_aer(void) { }
1281 static inline bool pci_aer_available(void) { return false; }
1284 #ifdef CONFIG_PCIE_ECRC
1285 void pcie_set_ecrc_checking(struct pci_dev
*dev
);
1286 void pcie_ecrc_get_policy(char *str
);
1288 static inline void pcie_set_ecrc_checking(struct pci_dev
*dev
) { }
1289 static inline void pcie_ecrc_get_policy(char *str
) { }
1292 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1294 #ifdef CONFIG_HT_IRQ
1295 /* The functions a driver should call */
1296 int ht_create_irq(struct pci_dev
*dev
, int idx
);
1297 void ht_destroy_irq(unsigned int irq
);
1298 #endif /* CONFIG_HT_IRQ */
1300 #ifdef CONFIG_PCI_ATS
1301 /* Address Translation Service */
1302 void pci_ats_init(struct pci_dev
*dev
);
1303 int pci_enable_ats(struct pci_dev
*dev
, int ps
);
1304 void pci_disable_ats(struct pci_dev
*dev
);
1305 int pci_ats_queue_depth(struct pci_dev
*dev
);
1307 static inline void pci_ats_init(struct pci_dev
*d
) { }
1308 static inline int pci_enable_ats(struct pci_dev
*d
, int ps
) { return -ENODEV
; }
1309 static inline void pci_disable_ats(struct pci_dev
*d
) { }
1310 static inline int pci_ats_queue_depth(struct pci_dev
*d
) { return -ENODEV
; }
1313 void pci_cfg_access_lock(struct pci_dev
*dev
);
1314 bool pci_cfg_access_trylock(struct pci_dev
*dev
);
1315 void pci_cfg_access_unlock(struct pci_dev
*dev
);
1318 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1319 * a PCI domain is defined to be a set of PCI buses which share
1320 * configuration space.
1322 #ifdef CONFIG_PCI_DOMAINS
1323 extern int pci_domains_supported
;
1324 int pci_get_new_domain_nr(void);
1326 enum { pci_domains_supported
= 0 };
1327 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1328 static inline int pci_proc_domain(struct pci_bus
*bus
) { return 0; }
1329 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1330 #endif /* CONFIG_PCI_DOMAINS */
1333 * Generic implementation for PCI domain support. If your
1334 * architecture does not need custom management of PCI
1335 * domains then this implementation will be used
1337 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1338 static inline int pci_domain_nr(struct pci_bus
*bus
)
1340 return bus
->domain_nr
;
1342 void pci_bus_assign_domain_nr(struct pci_bus
*bus
, struct device
*parent
);
1344 static inline void pci_bus_assign_domain_nr(struct pci_bus
*bus
,
1345 struct device
*parent
)
1350 /* some architectures require additional setup to direct VGA traffic */
1351 typedef int (*arch_set_vga_state_t
)(struct pci_dev
*pdev
, bool decode
,
1352 unsigned int command_bits
, u32 flags
);
1353 void pci_register_set_vga_state(arch_set_vga_state_t func
);
1355 #else /* CONFIG_PCI is not enabled */
1358 * If the system does not have PCI, clearly these return errors. Define
1359 * these as simple inline functions to avoid hair in drivers.
1362 #define _PCI_NOP(o, s, t) \
1363 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1365 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1367 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1368 _PCI_NOP(o, word, u16 x) \
1369 _PCI_NOP(o, dword, u32 x)
1370 _PCI_NOP_ALL(read
, *)
1371 _PCI_NOP_ALL(write
,)
1373 static inline struct pci_dev
*pci_get_device(unsigned int vendor
,
1374 unsigned int device
,
1375 struct pci_dev
*from
)
1378 static inline struct pci_dev
*pci_get_subsys(unsigned int vendor
,
1379 unsigned int device
,
1380 unsigned int ss_vendor
,
1381 unsigned int ss_device
,
1382 struct pci_dev
*from
)
1385 static inline struct pci_dev
*pci_get_class(unsigned int class,
1386 struct pci_dev
*from
)
1389 #define pci_dev_present(ids) (0)
1390 #define no_pci_devices() (1)
1391 #define pci_dev_put(dev) do { } while (0)
1393 static inline void pci_set_master(struct pci_dev
*dev
) { }
1394 static inline int pci_enable_device(struct pci_dev
*dev
) { return -EIO
; }
1395 static inline void pci_disable_device(struct pci_dev
*dev
) { }
1396 static inline int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1398 static inline int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1400 static inline int pci_set_dma_max_seg_size(struct pci_dev
*dev
,
1403 static inline int pci_set_dma_seg_boundary(struct pci_dev
*dev
,
1406 static inline int pci_assign_resource(struct pci_dev
*dev
, int i
)
1408 static inline int __pci_register_driver(struct pci_driver
*drv
,
1409 struct module
*owner
)
1411 static inline int pci_register_driver(struct pci_driver
*drv
)
1413 static inline void pci_unregister_driver(struct pci_driver
*drv
) { }
1414 static inline int pci_find_capability(struct pci_dev
*dev
, int cap
)
1416 static inline int pci_find_next_capability(struct pci_dev
*dev
, u8 post
,
1419 static inline int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
1422 /* Power management related routines */
1423 static inline int pci_save_state(struct pci_dev
*dev
) { return 0; }
1424 static inline void pci_restore_state(struct pci_dev
*dev
) { }
1425 static inline int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1427 static inline int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1429 static inline pci_power_t
pci_choose_state(struct pci_dev
*dev
,
1432 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1436 static inline int pci_request_regions(struct pci_dev
*dev
, const char *res_name
)
1438 static inline void pci_release_regions(struct pci_dev
*dev
) { }
1440 static inline void pci_block_cfg_access(struct pci_dev
*dev
) { }
1441 static inline int pci_block_cfg_access_in_atomic(struct pci_dev
*dev
)
1443 static inline void pci_unblock_cfg_access(struct pci_dev
*dev
) { }
1445 static inline struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
)
1447 static inline struct pci_dev
*pci_get_slot(struct pci_bus
*bus
,
1450 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
1454 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1455 static inline struct pci_dev
*pci_dev_get(struct pci_dev
*dev
) { return NULL
; }
1456 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1458 #define dev_is_pci(d) (false)
1459 #define dev_is_pf(d) (false)
1460 #define dev_num_vf(d) (0)
1461 #endif /* CONFIG_PCI */
1463 /* Include architecture-dependent settings and functions */
1465 #include <asm/pci.h>
1467 /* these helpers provide future and backwards compatibility
1468 * for accessing popular PCI BAR info */
1469 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1470 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1471 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1472 #define pci_resource_len(dev,bar) \
1473 ((pci_resource_start((dev), (bar)) == 0 && \
1474 pci_resource_end((dev), (bar)) == \
1475 pci_resource_start((dev), (bar))) ? 0 : \
1477 (pci_resource_end((dev), (bar)) - \
1478 pci_resource_start((dev), (bar)) + 1))
1480 /* Similar to the helpers above, these manipulate per-pci_dev
1481 * driver-specific data. They are really just a wrapper around
1482 * the generic device structure functions of these calls.
1484 static inline void *pci_get_drvdata(struct pci_dev
*pdev
)
1486 return dev_get_drvdata(&pdev
->dev
);
1489 static inline void pci_set_drvdata(struct pci_dev
*pdev
, void *data
)
1491 dev_set_drvdata(&pdev
->dev
, data
);
1494 /* If you want to know what to call your pci_dev, ask this function.
1495 * Again, it's a wrapper around the generic device.
1497 static inline const char *pci_name(const struct pci_dev
*pdev
)
1499 return dev_name(&pdev
->dev
);
1503 /* Some archs don't want to expose struct resource to userland as-is
1504 * in sysfs and /proc
1506 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1507 static inline void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1508 const struct resource
*rsrc
, resource_size_t
*start
,
1509 resource_size_t
*end
)
1511 *start
= rsrc
->start
;
1514 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1518 * The world is not perfect and supplies us with broken PCI devices.
1519 * For at least a part of these bugs we need a work-around, so both
1520 * generic (drivers/pci/quirks.c) and per-architecture code can define
1521 * fixup hooks to be called for particular buggy devices.
1525 u16 vendor
; /* You can use PCI_ANY_ID here of course */
1526 u16 device
; /* You can use PCI_ANY_ID here of course */
1527 u32
class; /* You can use PCI_ANY_ID here too */
1528 unsigned int class_shift
; /* should be 0, 8, 16 */
1529 void (*hook
)(struct pci_dev
*dev
);
1532 enum pci_fixup_pass
{
1533 pci_fixup_early
, /* Before probing BARs */
1534 pci_fixup_header
, /* After reading configuration header */
1535 pci_fixup_final
, /* Final phase of device fixups */
1536 pci_fixup_enable
, /* pci_enable_device() time */
1537 pci_fixup_resume
, /* pci_device_resume() */
1538 pci_fixup_suspend
, /* pci_device_suspend() */
1539 pci_fixup_resume_early
, /* pci_device_resume_early() */
1540 pci_fixup_suspend_late
, /* pci_device_suspend_late() */
1543 /* Anonymous variables would be nice... */
1544 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1545 class_shift, hook) \
1546 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1547 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1548 = { vendor, device, class, class_shift, hook };
1550 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1551 class_shift, hook) \
1552 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1553 hook, vendor, device, class, class_shift, hook)
1554 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1555 class_shift, hook) \
1556 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1557 hook, vendor, device, class, class_shift, hook)
1558 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1559 class_shift, hook) \
1560 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1561 hook, vendor, device, class, class_shift, hook)
1562 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1563 class_shift, hook) \
1564 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1565 hook, vendor, device, class, class_shift, hook)
1566 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1567 class_shift, hook) \
1568 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1569 resume##hook, vendor, device, class, \
1571 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1572 class_shift, hook) \
1573 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1574 resume_early##hook, vendor, device, \
1575 class, class_shift, hook)
1576 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1577 class_shift, hook) \
1578 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1579 suspend##hook, vendor, device, class, \
1581 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1582 class_shift, hook) \
1583 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1584 suspend_late##hook, vendor, device, \
1585 class, class_shift, hook)
1587 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1588 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1589 hook, vendor, device, PCI_ANY_ID, 0, hook)
1590 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1591 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1592 hook, vendor, device, PCI_ANY_ID, 0, hook)
1593 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1594 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1595 hook, vendor, device, PCI_ANY_ID, 0, hook)
1596 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1597 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1598 hook, vendor, device, PCI_ANY_ID, 0, hook)
1599 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1600 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1601 resume##hook, vendor, device, \
1602 PCI_ANY_ID, 0, hook)
1603 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1604 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1605 resume_early##hook, vendor, device, \
1606 PCI_ANY_ID, 0, hook)
1607 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1608 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1609 suspend##hook, vendor, device, \
1610 PCI_ANY_ID, 0, hook)
1611 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1612 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1613 suspend_late##hook, vendor, device, \
1614 PCI_ANY_ID, 0, hook)
1616 #ifdef CONFIG_PCI_QUIRKS
1617 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
);
1618 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
);
1619 void pci_dev_specific_enable_acs(struct pci_dev
*dev
);
1621 static inline void pci_fixup_device(enum pci_fixup_pass pass
,
1622 struct pci_dev
*dev
) { }
1623 static inline int pci_dev_specific_acs_enabled(struct pci_dev
*dev
,
1628 static inline void pci_dev_specific_enable_acs(struct pci_dev
*dev
) { }
1631 void __iomem
*pcim_iomap(struct pci_dev
*pdev
, int bar
, unsigned long maxlen
);
1632 void pcim_iounmap(struct pci_dev
*pdev
, void __iomem
*addr
);
1633 void __iomem
* const *pcim_iomap_table(struct pci_dev
*pdev
);
1634 int pcim_iomap_regions(struct pci_dev
*pdev
, int mask
, const char *name
);
1635 int pcim_iomap_regions_request_all(struct pci_dev
*pdev
, int mask
,
1637 void pcim_iounmap_regions(struct pci_dev
*pdev
, int mask
);
1639 extern int pci_pci_problems
;
1640 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1641 #define PCIPCI_TRITON 2
1642 #define PCIPCI_NATOMA 4
1643 #define PCIPCI_VIAETBF 8
1644 #define PCIPCI_VSFX 16
1645 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1646 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1648 extern unsigned long pci_cardbus_io_size
;
1649 extern unsigned long pci_cardbus_mem_size
;
1650 extern u8 pci_dfl_cache_line_size
;
1651 extern u8 pci_cache_line_size
;
1653 extern unsigned long pci_hotplug_io_size
;
1654 extern unsigned long pci_hotplug_mem_size
;
1656 /* Architecture-specific versions may override these (weak) */
1657 void pcibios_disable_device(struct pci_dev
*dev
);
1658 void pcibios_set_master(struct pci_dev
*dev
);
1659 int pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1660 enum pcie_reset_state state
);
1661 int pcibios_add_device(struct pci_dev
*dev
);
1662 void pcibios_release_device(struct pci_dev
*dev
);
1663 void pcibios_penalize_isa_irq(int irq
, int active
);
1665 #ifdef CONFIG_HIBERNATE_CALLBACKS
1666 extern struct dev_pm_ops pcibios_pm_ops
;
1669 #ifdef CONFIG_PCI_MMCONFIG
1670 void __init
pci_mmcfg_early_init(void);
1671 void __init
pci_mmcfg_late_init(void);
1673 static inline void pci_mmcfg_early_init(void) { }
1674 static inline void pci_mmcfg_late_init(void) { }
1677 int pci_ext_cfg_avail(void);
1679 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
);
1681 #ifdef CONFIG_PCI_IOV
1682 int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
);
1683 int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
);
1685 int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
);
1686 void pci_disable_sriov(struct pci_dev
*dev
);
1687 int pci_num_vf(struct pci_dev
*dev
);
1688 int pci_vfs_assigned(struct pci_dev
*dev
);
1689 int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
);
1690 int pci_sriov_get_totalvfs(struct pci_dev
*dev
);
1691 resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
);
1693 static inline int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
)
1697 static inline int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
)
1701 static inline int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
)
1703 static inline void pci_disable_sriov(struct pci_dev
*dev
) { }
1704 static inline int pci_num_vf(struct pci_dev
*dev
) { return 0; }
1705 static inline int pci_vfs_assigned(struct pci_dev
*dev
)
1707 static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
)
1709 static inline int pci_sriov_get_totalvfs(struct pci_dev
*dev
)
1711 static inline resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
)
1715 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1716 void pci_hp_create_module_link(struct pci_slot
*pci_slot
);
1717 void pci_hp_remove_module_link(struct pci_slot
*pci_slot
);
1721 * pci_pcie_cap - get the saved PCIe capability offset
1724 * PCIe capability offset is calculated at PCI device initialization
1725 * time and saved in the data structure. This function returns saved
1726 * PCIe capability offset. Using this instead of pci_find_capability()
1727 * reduces unnecessary search in the PCI configuration space. If you
1728 * need to calculate PCIe capability offset from raw device for some
1729 * reasons, please use pci_find_capability() instead.
1731 static inline int pci_pcie_cap(struct pci_dev
*dev
)
1733 return dev
->pcie_cap
;
1737 * pci_is_pcie - check if the PCI device is PCI Express capable
1740 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1742 static inline bool pci_is_pcie(struct pci_dev
*dev
)
1744 return pci_pcie_cap(dev
);
1748 * pcie_caps_reg - get the PCIe Capabilities Register
1751 static inline u16
pcie_caps_reg(const struct pci_dev
*dev
)
1753 return dev
->pcie_flags_reg
;
1757 * pci_pcie_type - get the PCIe device/port type
1760 static inline int pci_pcie_type(const struct pci_dev
*dev
)
1762 return (pcie_caps_reg(dev
) & PCI_EXP_FLAGS_TYPE
) >> 4;
1765 void pci_request_acs(void);
1766 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
);
1767 bool pci_acs_path_enabled(struct pci_dev
*start
,
1768 struct pci_dev
*end
, u16 acs_flags
);
1770 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1771 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1773 /* Large Resource Data Type Tag Item Names */
1774 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1775 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1776 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1778 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1779 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1780 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1782 /* Small Resource Data Type Tag Item Names */
1783 #define PCI_VPD_STIN_END 0x78 /* End */
1785 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1787 #define PCI_VPD_SRDT_TIN_MASK 0x78
1788 #define PCI_VPD_SRDT_LEN_MASK 0x07
1790 #define PCI_VPD_LRDT_TAG_SIZE 3
1791 #define PCI_VPD_SRDT_TAG_SIZE 1
1793 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1795 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1796 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1797 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1798 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1801 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1802 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1804 * Returns the extracted Large Resource Data Type length.
1806 static inline u16
pci_vpd_lrdt_size(const u8
*lrdt
)
1808 return (u16
)lrdt
[1] + ((u16
)lrdt
[2] << 8);
1812 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1813 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1815 * Returns the extracted Small Resource Data Type length.
1817 static inline u8
pci_vpd_srdt_size(const u8
*srdt
)
1819 return (*srdt
) & PCI_VPD_SRDT_LEN_MASK
;
1823 * pci_vpd_info_field_size - Extracts the information field length
1824 * @lrdt: Pointer to the beginning of an information field header
1826 * Returns the extracted information field length.
1828 static inline u8
pci_vpd_info_field_size(const u8
*info_field
)
1830 return info_field
[2];
1834 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1835 * @buf: Pointer to buffered vpd data
1836 * @off: The offset into the buffer at which to begin the search
1837 * @len: The length of the vpd buffer
1838 * @rdt: The Resource Data Type to search for
1840 * Returns the index where the Resource Data Type was found or
1841 * -ENOENT otherwise.
1843 int pci_vpd_find_tag(const u8
*buf
, unsigned int off
, unsigned int len
, u8 rdt
);
1846 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1847 * @buf: Pointer to buffered vpd data
1848 * @off: The offset into the buffer at which to begin the search
1849 * @len: The length of the buffer area, relative to off, in which to search
1850 * @kw: The keyword to search for
1852 * Returns the index where the information field keyword was found or
1853 * -ENOENT otherwise.
1855 int pci_vpd_find_info_keyword(const u8
*buf
, unsigned int off
,
1856 unsigned int len
, const char *kw
);
1858 /* PCI <-> OF binding helpers */
1861 void pci_set_of_node(struct pci_dev
*dev
);
1862 void pci_release_of_node(struct pci_dev
*dev
);
1863 void pci_set_bus_of_node(struct pci_bus
*bus
);
1864 void pci_release_bus_of_node(struct pci_bus
*bus
);
1866 /* Arch may override this (weak) */
1867 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
);
1869 static inline struct device_node
*
1870 pci_device_to_OF_node(const struct pci_dev
*pdev
)
1872 return pdev
? pdev
->dev
.of_node
: NULL
;
1875 static inline struct device_node
*pci_bus_to_OF_node(struct pci_bus
*bus
)
1877 return bus
? bus
->dev
.of_node
: NULL
;
1880 #else /* CONFIG_OF */
1881 static inline void pci_set_of_node(struct pci_dev
*dev
) { }
1882 static inline void pci_release_of_node(struct pci_dev
*dev
) { }
1883 static inline void pci_set_bus_of_node(struct pci_bus
*bus
) { }
1884 static inline void pci_release_bus_of_node(struct pci_bus
*bus
) { }
1885 static inline struct device_node
*
1886 pci_device_to_OF_node(const struct pci_dev
*pdev
) { return NULL
; }
1887 #endif /* CONFIG_OF */
1890 static inline struct eeh_dev
*pci_dev_to_eeh_dev(struct pci_dev
*pdev
)
1892 return pdev
->dev
.archdata
.edev
;
1896 int pci_for_each_dma_alias(struct pci_dev
*pdev
,
1897 int (*fn
)(struct pci_dev
*pdev
,
1898 u16 alias
, void *data
), void *data
);
1900 /* helper functions for operation of device flag */
1901 static inline void pci_set_dev_assigned(struct pci_dev
*pdev
)
1903 pdev
->dev_flags
|= PCI_DEV_FLAGS_ASSIGNED
;
1905 static inline void pci_clear_dev_assigned(struct pci_dev
*pdev
)
1907 pdev
->dev_flags
&= ~PCI_DEV_FLAGS_ASSIGNED
;
1909 static inline bool pci_is_dev_assigned(struct pci_dev
*pdev
)
1911 return (pdev
->dev_flags
& PCI_DEV_FLAGS_ASSIGNED
) == PCI_DEV_FLAGS_ASSIGNED
;
1915 * pci_ari_enabled - query ARI forwarding status
1918 * Returns true if ARI forwarding is enabled.
1920 static inline bool pci_ari_enabled(struct pci_bus
*bus
)
1922 return bus
->self
&& bus
->self
->ari_enabled
;
1924 #endif /* LINUX_PCI_H */