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PCI: Make current and maximum bus speeds part of the PCI core
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1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
191 enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 PCI_SPEED_66MHz_PCIX_533 = 0x11,
204 PCI_SPEED_100MHz_PCIX_533 = 0x12,
205 PCI_SPEED_133MHz_PCIX_533 = 0x13,
206 PCIE_SPEED_2_5GT = 0x14,
207 PCIE_SPEED_5_0GT = 0x15,
208 PCI_SPEED_UNKNOWN = 0xff,
209 };
210
211 struct pci_cap_saved_state {
212 struct hlist_node next;
213 char cap_nr;
214 u32 data[0];
215 };
216
217 struct pcie_link_state;
218 struct pci_vpd;
219 struct pci_sriov;
220 struct pci_ats;
221
222 /*
223 * The pci_dev structure is used to describe PCI devices.
224 */
225 struct pci_dev {
226 struct list_head bus_list; /* node in per-bus list */
227 struct pci_bus *bus; /* bus this device is on */
228 struct pci_bus *subordinate; /* bus this device bridges to */
229
230 void *sysdata; /* hook for sys-specific extension */
231 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
232 struct pci_slot *slot; /* Physical slot this device is in */
233
234 unsigned int devfn; /* encoded device & function index */
235 unsigned short vendor;
236 unsigned short device;
237 unsigned short subsystem_vendor;
238 unsigned short subsystem_device;
239 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
240 u8 revision; /* PCI revision, low byte of class word */
241 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
242 u8 pcie_cap; /* PCI-E capability offset */
243 u8 pcie_type; /* PCI-E device/port type */
244 u8 rom_base_reg; /* which config register controls the ROM */
245 u8 pin; /* which interrupt pin this device uses */
246
247 struct pci_driver *driver; /* which driver has allocated this device */
248 u64 dma_mask; /* Mask of the bits of bus address this
249 device implements. Normally this is
250 0xffffffff. You only need to change
251 this if your device has broken DMA
252 or supports 64-bit transfers. */
253
254 struct device_dma_parameters dma_parms;
255
256 pci_power_t current_state; /* Current operating state. In ACPI-speak,
257 this is D0-D3, D0 being fully functional,
258 and D3 being off. */
259 int pm_cap; /* PM capability offset in the
260 configuration space */
261 unsigned int pme_support:5; /* Bitmask of states from which PME#
262 can be generated */
263 unsigned int d1_support:1; /* Low power state D1 is supported */
264 unsigned int d2_support:1; /* Low power state D2 is supported */
265 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
266 unsigned int wakeup_prepared:1;
267 unsigned int d3_delay; /* D3->D0 transition time in ms */
268
269 #ifdef CONFIG_PCIEASPM
270 struct pcie_link_state *link_state; /* ASPM link state. */
271 #endif
272
273 pci_channel_state_t error_state; /* current connectivity state */
274 struct device dev; /* Generic device interface */
275
276 int cfg_size; /* Size of configuration space */
277
278 /*
279 * Instead of touching interrupt line and base address registers
280 * directly, use the values stored here. They might be different!
281 */
282 unsigned int irq;
283 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
284
285 /* These fields are used by common fixups */
286 unsigned int transparent:1; /* Transparent PCI bridge */
287 unsigned int multifunction:1;/* Part of multi-function device */
288 /* keep track of device state */
289 unsigned int is_added:1;
290 unsigned int is_busmaster:1; /* device is busmaster */
291 unsigned int no_msi:1; /* device may not use msi */
292 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
293 unsigned int broken_parity_status:1; /* Device generates false positive parity */
294 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
295 unsigned int msi_enabled:1;
296 unsigned int msix_enabled:1;
297 unsigned int ari_enabled:1; /* ARI forwarding */
298 unsigned int is_managed:1;
299 unsigned int is_pcie:1;
300 unsigned int needs_freset:1; /* Dev requires fundamental reset */
301 unsigned int state_saved:1;
302 unsigned int is_physfn:1;
303 unsigned int is_virtfn:1;
304 unsigned int reset_fn:1;
305 unsigned int is_hotplug_bridge:1;
306 unsigned int aer_firmware_first:1;
307 pci_dev_flags_t dev_flags;
308 atomic_t enable_cnt; /* pci_enable_device has been called */
309
310 u32 saved_config_space[16]; /* config space saved at suspend time */
311 struct hlist_head saved_cap_space;
312 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
313 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
314 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
315 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
316 #ifdef CONFIG_PCI_MSI
317 struct list_head msi_list;
318 #endif
319 struct pci_vpd *vpd;
320 #ifdef CONFIG_PCI_IOV
321 union {
322 struct pci_sriov *sriov; /* SR-IOV capability related */
323 struct pci_dev *physfn; /* the PF this VF is associated with */
324 };
325 struct pci_ats *ats; /* Address Translation Service */
326 #endif
327 };
328
329 extern struct pci_dev *alloc_pci_dev(void);
330
331 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
332 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
333 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
334
335 static inline int pci_channel_offline(struct pci_dev *pdev)
336 {
337 return (pdev->error_state != pci_channel_io_normal);
338 }
339
340 static inline struct pci_cap_saved_state *pci_find_saved_cap(
341 struct pci_dev *pci_dev, char cap)
342 {
343 struct pci_cap_saved_state *tmp;
344 struct hlist_node *pos;
345
346 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
347 if (tmp->cap_nr == cap)
348 return tmp;
349 }
350 return NULL;
351 }
352
353 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
354 struct pci_cap_saved_state *new_cap)
355 {
356 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
357 }
358
359 #ifndef PCI_BUS_NUM_RESOURCES
360 #define PCI_BUS_NUM_RESOURCES 16
361 #endif
362
363 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
364
365 struct pci_bus {
366 struct list_head node; /* node in list of buses */
367 struct pci_bus *parent; /* parent bus this bridge is on */
368 struct list_head children; /* list of child buses */
369 struct list_head devices; /* list of devices on this bus */
370 struct pci_dev *self; /* bridge device as seen by parent */
371 struct list_head slots; /* list of slots on this bus */
372 struct resource *resource[PCI_BUS_NUM_RESOURCES];
373 /* address space routed to this bus */
374
375 struct pci_ops *ops; /* configuration access functions */
376 void *sysdata; /* hook for sys-specific extension */
377 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
378
379 unsigned char number; /* bus number */
380 unsigned char primary; /* number of primary bridge */
381 unsigned char secondary; /* number of secondary bridge */
382 unsigned char subordinate; /* max number of subordinate buses */
383 unsigned char max_bus_speed; /* enum pci_bus_speed */
384 unsigned char cur_bus_speed; /* enum pci_bus_speed */
385
386 char name[48];
387
388 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
389 pci_bus_flags_t bus_flags; /* Inherited by child busses */
390 struct device *bridge;
391 struct device dev;
392 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
393 struct bin_attribute *legacy_mem; /* legacy mem */
394 unsigned int is_added:1;
395 };
396
397 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
398 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
399
400 /*
401 * Returns true if the pci bus is root (behind host-pci bridge),
402 * false otherwise
403 */
404 static inline bool pci_is_root_bus(struct pci_bus *pbus)
405 {
406 return !(pbus->parent);
407 }
408
409 #ifdef CONFIG_PCI_MSI
410 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
411 {
412 return pci_dev->msi_enabled || pci_dev->msix_enabled;
413 }
414 #else
415 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
416 #endif
417
418 /*
419 * Error values that may be returned by PCI functions.
420 */
421 #define PCIBIOS_SUCCESSFUL 0x00
422 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
423 #define PCIBIOS_BAD_VENDOR_ID 0x83
424 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
425 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
426 #define PCIBIOS_SET_FAILED 0x88
427 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
428
429 /* Low-level architecture-dependent routines */
430
431 struct pci_ops {
432 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
433 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
434 };
435
436 /*
437 * ACPI needs to be able to access PCI config space before we've done a
438 * PCI bus scan and created pci_bus structures.
439 */
440 extern int raw_pci_read(unsigned int domain, unsigned int bus,
441 unsigned int devfn, int reg, int len, u32 *val);
442 extern int raw_pci_write(unsigned int domain, unsigned int bus,
443 unsigned int devfn, int reg, int len, u32 val);
444
445 struct pci_bus_region {
446 resource_size_t start;
447 resource_size_t end;
448 };
449
450 struct pci_dynids {
451 spinlock_t lock; /* protects list, index */
452 struct list_head list; /* for IDs added at runtime */
453 };
454
455 /* ---------------------------------------------------------------- */
456 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
457 * a set of callbacks in struct pci_error_handlers, then that device driver
458 * will be notified of PCI bus errors, and will be driven to recovery
459 * when an error occurs.
460 */
461
462 typedef unsigned int __bitwise pci_ers_result_t;
463
464 enum pci_ers_result {
465 /* no result/none/not supported in device driver */
466 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
467
468 /* Device driver can recover without slot reset */
469 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
470
471 /* Device driver wants slot to be reset. */
472 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
473
474 /* Device has completely failed, is unrecoverable */
475 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
476
477 /* Device driver is fully recovered and operational */
478 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
479 };
480
481 /* PCI bus error event callbacks */
482 struct pci_error_handlers {
483 /* PCI bus error detected on this device */
484 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
485 enum pci_channel_state error);
486
487 /* MMIO has been re-enabled, but not DMA */
488 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
489
490 /* PCI Express link has been reset */
491 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
492
493 /* PCI slot has been reset */
494 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
495
496 /* Device driver may resume normal operations */
497 void (*resume)(struct pci_dev *dev);
498 };
499
500 /* ---------------------------------------------------------------- */
501
502 struct module;
503 struct pci_driver {
504 struct list_head node;
505 char *name;
506 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
507 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
508 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
509 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
510 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
511 int (*resume_early) (struct pci_dev *dev);
512 int (*resume) (struct pci_dev *dev); /* Device woken up */
513 void (*shutdown) (struct pci_dev *dev);
514 struct pci_error_handlers *err_handler;
515 struct device_driver driver;
516 struct pci_dynids dynids;
517 };
518
519 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
520
521 /**
522 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
523 * @_table: device table name
524 *
525 * This macro is used to create a struct pci_device_id array (a device table)
526 * in a generic manner.
527 */
528 #define DEFINE_PCI_DEVICE_TABLE(_table) \
529 const struct pci_device_id _table[] __devinitconst
530
531 /**
532 * PCI_DEVICE - macro used to describe a specific pci device
533 * @vend: the 16 bit PCI Vendor ID
534 * @dev: the 16 bit PCI Device ID
535 *
536 * This macro is used to create a struct pci_device_id that matches a
537 * specific device. The subvendor and subdevice fields will be set to
538 * PCI_ANY_ID.
539 */
540 #define PCI_DEVICE(vend,dev) \
541 .vendor = (vend), .device = (dev), \
542 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
543
544 /**
545 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
546 * @dev_class: the class, subclass, prog-if triple for this device
547 * @dev_class_mask: the class mask for this device
548 *
549 * This macro is used to create a struct pci_device_id that matches a
550 * specific PCI class. The vendor, device, subvendor, and subdevice
551 * fields will be set to PCI_ANY_ID.
552 */
553 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
554 .class = (dev_class), .class_mask = (dev_class_mask), \
555 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
556 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
557
558 /**
559 * PCI_VDEVICE - macro used to describe a specific pci device in short form
560 * @vendor: the vendor name
561 * @device: the 16 bit PCI Device ID
562 *
563 * This macro is used to create a struct pci_device_id that matches a
564 * specific PCI device. The subvendor, and subdevice fields will be set
565 * to PCI_ANY_ID. The macro allows the next field to follow as the device
566 * private data.
567 */
568
569 #define PCI_VDEVICE(vendor, device) \
570 PCI_VENDOR_ID_##vendor, (device), \
571 PCI_ANY_ID, PCI_ANY_ID, 0, 0
572
573 /* these external functions are only available when PCI support is enabled */
574 #ifdef CONFIG_PCI
575
576 extern struct bus_type pci_bus_type;
577
578 /* Do NOT directly access these two variables, unless you are arch specific pci
579 * code, or pci core code. */
580 extern struct list_head pci_root_buses; /* list of all known PCI buses */
581 /* Some device drivers need know if pci is initiated */
582 extern int no_pci_devices(void);
583
584 void pcibios_fixup_bus(struct pci_bus *);
585 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
586 char *pcibios_setup(char *str);
587
588 /* Used only when drivers/pci/setup.c is used */
589 void pcibios_align_resource(void *, struct resource *, resource_size_t,
590 resource_size_t);
591 void pcibios_update_irq(struct pci_dev *, int irq);
592
593 /* Weak but can be overriden by arch */
594 void pci_fixup_cardbus(struct pci_bus *);
595
596 /* Generic PCI functions used internally */
597
598 extern struct pci_bus *pci_find_bus(int domain, int busnr);
599 void pci_bus_add_devices(const struct pci_bus *bus);
600 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
601 struct pci_ops *ops, void *sysdata);
602 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
603 void *sysdata)
604 {
605 struct pci_bus *root_bus;
606 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
607 if (root_bus)
608 pci_bus_add_devices(root_bus);
609 return root_bus;
610 }
611 struct pci_bus *pci_create_bus(struct device *parent, int bus,
612 struct pci_ops *ops, void *sysdata);
613 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
614 int busnr);
615 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
616 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
617 const char *name,
618 struct hotplug_slot *hotplug);
619 void pci_destroy_slot(struct pci_slot *slot);
620 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
621 int pci_scan_slot(struct pci_bus *bus, int devfn);
622 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
623 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
624 unsigned int pci_scan_child_bus(struct pci_bus *bus);
625 int __must_check pci_bus_add_device(struct pci_dev *dev);
626 void pci_read_bridge_bases(struct pci_bus *child);
627 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
628 struct resource *res);
629 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
630 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
631 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
632 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
633 extern void pci_dev_put(struct pci_dev *dev);
634 extern void pci_remove_bus(struct pci_bus *b);
635 extern void pci_remove_bus_device(struct pci_dev *dev);
636 extern void pci_stop_bus_device(struct pci_dev *dev);
637 void pci_setup_cardbus(struct pci_bus *bus);
638 extern void pci_sort_breadthfirst(void);
639
640 /* Generic PCI functions exported to card drivers */
641
642 #ifdef CONFIG_PCI_LEGACY
643 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
644 unsigned int device,
645 struct pci_dev *from);
646 #endif /* CONFIG_PCI_LEGACY */
647
648 enum pci_lost_interrupt_reason {
649 PCI_LOST_IRQ_NO_INFORMATION = 0,
650 PCI_LOST_IRQ_DISABLE_MSI,
651 PCI_LOST_IRQ_DISABLE_MSIX,
652 PCI_LOST_IRQ_DISABLE_ACPI,
653 };
654 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
655 int pci_find_capability(struct pci_dev *dev, int cap);
656 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
657 int pci_find_ext_capability(struct pci_dev *dev, int cap);
658 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
659 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
660 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
661
662 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
663 struct pci_dev *from);
664 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
665 unsigned int ss_vendor, unsigned int ss_device,
666 struct pci_dev *from);
667 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
668 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
669 unsigned int devfn);
670 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
671 unsigned int devfn)
672 {
673 return pci_get_domain_bus_and_slot(0, bus, devfn);
674 }
675 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
676 int pci_dev_present(const struct pci_device_id *ids);
677
678 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
679 int where, u8 *val);
680 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
681 int where, u16 *val);
682 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
683 int where, u32 *val);
684 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
685 int where, u8 val);
686 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
687 int where, u16 val);
688 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
689 int where, u32 val);
690 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
691
692 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
693 {
694 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
695 }
696 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
697 {
698 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
699 }
700 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
701 u32 *val)
702 {
703 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
704 }
705 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
706 {
707 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
708 }
709 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
710 {
711 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
712 }
713 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
714 u32 val)
715 {
716 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
717 }
718
719 int __must_check pci_enable_device(struct pci_dev *dev);
720 int __must_check pci_enable_device_io(struct pci_dev *dev);
721 int __must_check pci_enable_device_mem(struct pci_dev *dev);
722 int __must_check pci_reenable_device(struct pci_dev *);
723 int __must_check pcim_enable_device(struct pci_dev *pdev);
724 void pcim_pin_device(struct pci_dev *pdev);
725
726 static inline int pci_is_enabled(struct pci_dev *pdev)
727 {
728 return (atomic_read(&pdev->enable_cnt) > 0);
729 }
730
731 static inline int pci_is_managed(struct pci_dev *pdev)
732 {
733 return pdev->is_managed;
734 }
735
736 void pci_disable_device(struct pci_dev *dev);
737 void pci_set_master(struct pci_dev *dev);
738 void pci_clear_master(struct pci_dev *dev);
739 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
740 int pci_set_cacheline_size(struct pci_dev *dev);
741 #define HAVE_PCI_SET_MWI
742 int __must_check pci_set_mwi(struct pci_dev *dev);
743 int pci_try_set_mwi(struct pci_dev *dev);
744 void pci_clear_mwi(struct pci_dev *dev);
745 void pci_intx(struct pci_dev *dev, int enable);
746 void pci_msi_off(struct pci_dev *dev);
747 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
748 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
749 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
750 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
751 int pcix_get_max_mmrbc(struct pci_dev *dev);
752 int pcix_get_mmrbc(struct pci_dev *dev);
753 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
754 int pcie_get_readrq(struct pci_dev *dev);
755 int pcie_set_readrq(struct pci_dev *dev, int rq);
756 int __pci_reset_function(struct pci_dev *dev);
757 int pci_reset_function(struct pci_dev *dev);
758 void pci_update_resource(struct pci_dev *dev, int resno);
759 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
760 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
761
762 /* ROM control related routines */
763 int pci_enable_rom(struct pci_dev *pdev);
764 void pci_disable_rom(struct pci_dev *pdev);
765 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
766 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
767 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
768
769 /* Power management related routines */
770 int pci_save_state(struct pci_dev *dev);
771 int pci_restore_state(struct pci_dev *dev);
772 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
773 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
774 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
775 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
776 void pci_pme_active(struct pci_dev *dev, bool enable);
777 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
778 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
779 pci_power_t pci_target_state(struct pci_dev *dev);
780 int pci_prepare_to_sleep(struct pci_dev *dev);
781 int pci_back_from_sleep(struct pci_dev *dev);
782
783 /* For use by arch with custom probe code */
784 void set_pcie_port_type(struct pci_dev *pdev);
785 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
786
787 /* Functions for PCI Hotplug drivers to use */
788 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
789 #ifdef CONFIG_HOTPLUG
790 unsigned int pci_rescan_bus(struct pci_bus *bus);
791 #endif
792
793 /* Vital product data routines */
794 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
795 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
796 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
797
798 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
799 void pci_bus_assign_resources(const struct pci_bus *bus);
800 void pci_bus_size_bridges(struct pci_bus *bus);
801 int pci_claim_resource(struct pci_dev *, int);
802 void pci_assign_unassigned_resources(void);
803 void pdev_enable_device(struct pci_dev *);
804 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
805 int pci_enable_resources(struct pci_dev *, int mask);
806 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
807 int (*)(struct pci_dev *, u8, u8));
808 #define HAVE_PCI_REQ_REGIONS 2
809 int __must_check pci_request_regions(struct pci_dev *, const char *);
810 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
811 void pci_release_regions(struct pci_dev *);
812 int __must_check pci_request_region(struct pci_dev *, int, const char *);
813 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
814 void pci_release_region(struct pci_dev *, int);
815 int pci_request_selected_regions(struct pci_dev *, int, const char *);
816 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
817 void pci_release_selected_regions(struct pci_dev *, int);
818
819 /* drivers/pci/bus.c */
820 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
821 struct resource *res, resource_size_t size,
822 resource_size_t align, resource_size_t min,
823 unsigned int type_mask,
824 void (*alignf)(void *, struct resource *,
825 resource_size_t, resource_size_t),
826 void *alignf_data);
827 void pci_enable_bridges(struct pci_bus *bus);
828
829 /* Proper probing supporting hot-pluggable devices */
830 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
831 const char *mod_name);
832
833 /*
834 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
835 */
836 #define pci_register_driver(driver) \
837 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
838
839 void pci_unregister_driver(struct pci_driver *dev);
840 void pci_remove_behind_bridge(struct pci_dev *dev);
841 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
842 int pci_add_dynid(struct pci_driver *drv,
843 unsigned int vendor, unsigned int device,
844 unsigned int subvendor, unsigned int subdevice,
845 unsigned int class, unsigned int class_mask,
846 unsigned long driver_data);
847 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
848 struct pci_dev *dev);
849 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
850 int pass);
851
852 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
853 void *userdata);
854 int pci_cfg_space_size_ext(struct pci_dev *dev);
855 int pci_cfg_space_size(struct pci_dev *dev);
856 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
857
858 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
859 unsigned int command_bits, bool change_bridge);
860 /* kmem_cache style wrapper around pci_alloc_consistent() */
861
862 #include <linux/dmapool.h>
863
864 #define pci_pool dma_pool
865 #define pci_pool_create(name, pdev, size, align, allocation) \
866 dma_pool_create(name, &pdev->dev, size, align, allocation)
867 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
868 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
869 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
870
871 enum pci_dma_burst_strategy {
872 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
873 strategy_parameter is N/A */
874 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
875 byte boundaries */
876 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
877 strategy_parameter byte boundaries */
878 };
879
880 struct msix_entry {
881 u32 vector; /* kernel uses to write allocated vector */
882 u16 entry; /* driver uses to specify entry, OS writes */
883 };
884
885
886 #ifndef CONFIG_PCI_MSI
887 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
888 {
889 return -1;
890 }
891
892 static inline void pci_msi_shutdown(struct pci_dev *dev)
893 { }
894 static inline void pci_disable_msi(struct pci_dev *dev)
895 { }
896
897 static inline int pci_msix_table_size(struct pci_dev *dev)
898 {
899 return 0;
900 }
901 static inline int pci_enable_msix(struct pci_dev *dev,
902 struct msix_entry *entries, int nvec)
903 {
904 return -1;
905 }
906
907 static inline void pci_msix_shutdown(struct pci_dev *dev)
908 { }
909 static inline void pci_disable_msix(struct pci_dev *dev)
910 { }
911
912 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
913 { }
914
915 static inline void pci_restore_msi_state(struct pci_dev *dev)
916 { }
917 static inline int pci_msi_enabled(void)
918 {
919 return 0;
920 }
921 #else
922 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
923 extern void pci_msi_shutdown(struct pci_dev *dev);
924 extern void pci_disable_msi(struct pci_dev *dev);
925 extern int pci_msix_table_size(struct pci_dev *dev);
926 extern int pci_enable_msix(struct pci_dev *dev,
927 struct msix_entry *entries, int nvec);
928 extern void pci_msix_shutdown(struct pci_dev *dev);
929 extern void pci_disable_msix(struct pci_dev *dev);
930 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
931 extern void pci_restore_msi_state(struct pci_dev *dev);
932 extern int pci_msi_enabled(void);
933 #endif
934
935 #ifndef CONFIG_PCIEASPM
936 static inline int pcie_aspm_enabled(void)
937 {
938 return 0;
939 }
940 #else
941 extern int pcie_aspm_enabled(void);
942 #endif
943
944 #ifndef CONFIG_PCIE_ECRC
945 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
946 {
947 return;
948 }
949 static inline void pcie_ecrc_get_policy(char *str) {};
950 #else
951 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
952 extern void pcie_ecrc_get_policy(char *str);
953 #endif
954
955 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
956
957 #ifdef CONFIG_HT_IRQ
958 /* The functions a driver should call */
959 int ht_create_irq(struct pci_dev *dev, int idx);
960 void ht_destroy_irq(unsigned int irq);
961 #endif /* CONFIG_HT_IRQ */
962
963 extern void pci_block_user_cfg_access(struct pci_dev *dev);
964 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
965
966 /*
967 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
968 * a PCI domain is defined to be a set of PCI busses which share
969 * configuration space.
970 */
971 #ifdef CONFIG_PCI_DOMAINS
972 extern int pci_domains_supported;
973 #else
974 enum { pci_domains_supported = 0 };
975 static inline int pci_domain_nr(struct pci_bus *bus)
976 {
977 return 0;
978 }
979
980 static inline int pci_proc_domain(struct pci_bus *bus)
981 {
982 return 0;
983 }
984 #endif /* CONFIG_PCI_DOMAINS */
985
986 #else /* CONFIG_PCI is not enabled */
987
988 /*
989 * If the system does not have PCI, clearly these return errors. Define
990 * these as simple inline functions to avoid hair in drivers.
991 */
992
993 #define _PCI_NOP(o, s, t) \
994 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
995 int where, t val) \
996 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
997
998 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
999 _PCI_NOP(o, word, u16 x) \
1000 _PCI_NOP(o, dword, u32 x)
1001 _PCI_NOP_ALL(read, *)
1002 _PCI_NOP_ALL(write,)
1003
1004 static inline struct pci_dev *pci_find_device(unsigned int vendor,
1005 unsigned int device,
1006 struct pci_dev *from)
1007 {
1008 return NULL;
1009 }
1010
1011 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1012 unsigned int device,
1013 struct pci_dev *from)
1014 {
1015 return NULL;
1016 }
1017
1018 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1019 unsigned int device,
1020 unsigned int ss_vendor,
1021 unsigned int ss_device,
1022 struct pci_dev *from)
1023 {
1024 return NULL;
1025 }
1026
1027 static inline struct pci_dev *pci_get_class(unsigned int class,
1028 struct pci_dev *from)
1029 {
1030 return NULL;
1031 }
1032
1033 #define pci_dev_present(ids) (0)
1034 #define no_pci_devices() (1)
1035 #define pci_dev_put(dev) do { } while (0)
1036
1037 static inline void pci_set_master(struct pci_dev *dev)
1038 { }
1039
1040 static inline int pci_enable_device(struct pci_dev *dev)
1041 {
1042 return -EIO;
1043 }
1044
1045 static inline void pci_disable_device(struct pci_dev *dev)
1046 { }
1047
1048 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1049 {
1050 return -EIO;
1051 }
1052
1053 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1054 {
1055 return -EIO;
1056 }
1057
1058 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1059 unsigned int size)
1060 {
1061 return -EIO;
1062 }
1063
1064 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1065 unsigned long mask)
1066 {
1067 return -EIO;
1068 }
1069
1070 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1071 {
1072 return -EBUSY;
1073 }
1074
1075 static inline int __pci_register_driver(struct pci_driver *drv,
1076 struct module *owner)
1077 {
1078 return 0;
1079 }
1080
1081 static inline int pci_register_driver(struct pci_driver *drv)
1082 {
1083 return 0;
1084 }
1085
1086 static inline void pci_unregister_driver(struct pci_driver *drv)
1087 { }
1088
1089 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1090 {
1091 return 0;
1092 }
1093
1094 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1095 int cap)
1096 {
1097 return 0;
1098 }
1099
1100 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1101 {
1102 return 0;
1103 }
1104
1105 /* Power management related routines */
1106 static inline int pci_save_state(struct pci_dev *dev)
1107 {
1108 return 0;
1109 }
1110
1111 static inline int pci_restore_state(struct pci_dev *dev)
1112 {
1113 return 0;
1114 }
1115
1116 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1117 {
1118 return 0;
1119 }
1120
1121 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1122 pm_message_t state)
1123 {
1124 return PCI_D0;
1125 }
1126
1127 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1128 int enable)
1129 {
1130 return 0;
1131 }
1132
1133 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1134 {
1135 return -EIO;
1136 }
1137
1138 static inline void pci_release_regions(struct pci_dev *dev)
1139 { }
1140
1141 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1142
1143 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1144 { }
1145
1146 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1147 { }
1148
1149 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1150 { return NULL; }
1151
1152 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1153 unsigned int devfn)
1154 { return NULL; }
1155
1156 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1157 unsigned int devfn)
1158 { return NULL; }
1159
1160 #endif /* CONFIG_PCI */
1161
1162 /* Include architecture-dependent settings and functions */
1163
1164 #include <asm/pci.h>
1165
1166 #ifndef PCIBIOS_MAX_MEM_32
1167 #define PCIBIOS_MAX_MEM_32 (-1)
1168 #endif
1169
1170 /* these helpers provide future and backwards compatibility
1171 * for accessing popular PCI BAR info */
1172 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1173 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1174 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1175 #define pci_resource_len(dev,bar) \
1176 ((pci_resource_start((dev), (bar)) == 0 && \
1177 pci_resource_end((dev), (bar)) == \
1178 pci_resource_start((dev), (bar))) ? 0 : \
1179 \
1180 (pci_resource_end((dev), (bar)) - \
1181 pci_resource_start((dev), (bar)) + 1))
1182
1183 /* Similar to the helpers above, these manipulate per-pci_dev
1184 * driver-specific data. They are really just a wrapper around
1185 * the generic device structure functions of these calls.
1186 */
1187 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1188 {
1189 return dev_get_drvdata(&pdev->dev);
1190 }
1191
1192 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1193 {
1194 dev_set_drvdata(&pdev->dev, data);
1195 }
1196
1197 /* If you want to know what to call your pci_dev, ask this function.
1198 * Again, it's a wrapper around the generic device.
1199 */
1200 static inline const char *pci_name(const struct pci_dev *pdev)
1201 {
1202 return dev_name(&pdev->dev);
1203 }
1204
1205
1206 /* Some archs don't want to expose struct resource to userland as-is
1207 * in sysfs and /proc
1208 */
1209 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1210 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1211 const struct resource *rsrc, resource_size_t *start,
1212 resource_size_t *end)
1213 {
1214 *start = rsrc->start;
1215 *end = rsrc->end;
1216 }
1217 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1218
1219
1220 /*
1221 * The world is not perfect and supplies us with broken PCI devices.
1222 * For at least a part of these bugs we need a work-around, so both
1223 * generic (drivers/pci/quirks.c) and per-architecture code can define
1224 * fixup hooks to be called for particular buggy devices.
1225 */
1226
1227 struct pci_fixup {
1228 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1229 void (*hook)(struct pci_dev *dev);
1230 };
1231
1232 enum pci_fixup_pass {
1233 pci_fixup_early, /* Before probing BARs */
1234 pci_fixup_header, /* After reading configuration header */
1235 pci_fixup_final, /* Final phase of device fixups */
1236 pci_fixup_enable, /* pci_enable_device() time */
1237 pci_fixup_resume, /* pci_device_resume() */
1238 pci_fixup_suspend, /* pci_device_suspend */
1239 pci_fixup_resume_early, /* pci_device_resume_early() */
1240 };
1241
1242 /* Anonymous variables would be nice... */
1243 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1244 static const struct pci_fixup __pci_fixup_##name __used \
1245 __attribute__((__section__(#section))) = { vendor, device, hook };
1246 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1247 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1248 vendor##device##hook, vendor, device, hook)
1249 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1250 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1251 vendor##device##hook, vendor, device, hook)
1252 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1253 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1254 vendor##device##hook, vendor, device, hook)
1255 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1256 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1257 vendor##device##hook, vendor, device, hook)
1258 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1259 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1260 resume##vendor##device##hook, vendor, device, hook)
1261 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1262 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1263 resume_early##vendor##device##hook, vendor, device, hook)
1264 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1265 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1266 suspend##vendor##device##hook, vendor, device, hook)
1267
1268
1269 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1270
1271 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1272 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1273 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1274 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1275 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1276 const char *name);
1277 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1278
1279 extern int pci_pci_problems;
1280 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1281 #define PCIPCI_TRITON 2
1282 #define PCIPCI_NATOMA 4
1283 #define PCIPCI_VIAETBF 8
1284 #define PCIPCI_VSFX 16
1285 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1286 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1287
1288 extern unsigned long pci_cardbus_io_size;
1289 extern unsigned long pci_cardbus_mem_size;
1290 extern u8 __devinitdata pci_dfl_cache_line_size;
1291 extern u8 pci_cache_line_size;
1292
1293 extern unsigned long pci_hotplug_io_size;
1294 extern unsigned long pci_hotplug_mem_size;
1295
1296 int pcibios_add_platform_entries(struct pci_dev *dev);
1297 void pcibios_disable_device(struct pci_dev *dev);
1298 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1299 enum pcie_reset_state state);
1300
1301 #ifdef CONFIG_PCI_MMCONFIG
1302 extern void __init pci_mmcfg_early_init(void);
1303 extern void __init pci_mmcfg_late_init(void);
1304 #else
1305 static inline void pci_mmcfg_early_init(void) { }
1306 static inline void pci_mmcfg_late_init(void) { }
1307 #endif
1308
1309 int pci_ext_cfg_avail(struct pci_dev *dev);
1310
1311 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1312
1313 #ifdef CONFIG_PCI_IOV
1314 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1315 extern void pci_disable_sriov(struct pci_dev *dev);
1316 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1317 #else
1318 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1319 {
1320 return -ENODEV;
1321 }
1322 static inline void pci_disable_sriov(struct pci_dev *dev)
1323 {
1324 }
1325 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1326 {
1327 return IRQ_NONE;
1328 }
1329 #endif
1330
1331 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1332 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1333 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1334 #endif
1335
1336 /**
1337 * pci_pcie_cap - get the saved PCIe capability offset
1338 * @dev: PCI device
1339 *
1340 * PCIe capability offset is calculated at PCI device initialization
1341 * time and saved in the data structure. This function returns saved
1342 * PCIe capability offset. Using this instead of pci_find_capability()
1343 * reduces unnecessary search in the PCI configuration space. If you
1344 * need to calculate PCIe capability offset from raw device for some
1345 * reasons, please use pci_find_capability() instead.
1346 */
1347 static inline int pci_pcie_cap(struct pci_dev *dev)
1348 {
1349 return dev->pcie_cap;
1350 }
1351
1352 /**
1353 * pci_is_pcie - check if the PCI device is PCI Express capable
1354 * @dev: PCI device
1355 *
1356 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1357 */
1358 static inline bool pci_is_pcie(struct pci_dev *dev)
1359 {
1360 return !!pci_pcie_cap(dev);
1361 }
1362
1363 void pci_request_acs(void);
1364
1365 #endif /* __KERNEL__ */
1366 #endif /* LINUX_PCI_H */
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