1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus
*bus
; /* The bus this slot is on */
58 struct list_head list
; /* node in list of slots on this bus */
59 struct hotplug_slot
*hotplug
; /* Hotplug info (migrate over time) */
60 unsigned char number
; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot
*slot
)
66 return kobject_name(&slot
->kobj
);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
76 * For PCI devices, the region numbers are assigned this way:
79 /* #0-5: standard PCI resources */
81 PCI_STD_RESOURCE_END
= 5,
83 /* #6: expansion ROM resource */
86 /* device specific resources */
89 PCI_IOV_RESOURCE_END
= PCI_IOV_RESOURCES
+ PCI_SRIOV_NUM_BARS
- 1,
92 /* resources assigned to buses behind the bridge */
93 #define PCI_BRIDGE_RESOURCE_NUM 4
96 PCI_BRIDGE_RESOURCE_END
= PCI_BRIDGE_RESOURCES
+
97 PCI_BRIDGE_RESOURCE_NUM
- 1,
99 /* total resources associated with a PCI device */
102 /* preserve this for compatibility */
103 DEVICE_COUNT_RESOURCE
= PCI_NUM_RESOURCES
,
107 * enum pci_interrupt_pin - PCI INTx interrupt values
108 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
109 * @PCI_INTERRUPT_INTA: PCI INTA pin
110 * @PCI_INTERRUPT_INTB: PCI INTB pin
111 * @PCI_INTERRUPT_INTC: PCI INTC pin
112 * @PCI_INTERRUPT_INTD: PCI INTD pin
114 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
115 * PCI_INTERRUPT_PIN register.
117 enum pci_interrupt_pin
{
118 PCI_INTERRUPT_UNKNOWN
,
125 /* The number of legacy PCI INTx interrupts */
126 #define PCI_NUM_INTX 4
129 * pci_power_t values must match the bits in the Capabilities PME_Support
130 * and Control/Status PowerState fields in the Power Management capability.
132 typedef int __bitwise pci_power_t
;
134 #define PCI_D0 ((pci_power_t __force) 0)
135 #define PCI_D1 ((pci_power_t __force) 1)
136 #define PCI_D2 ((pci_power_t __force) 2)
137 #define PCI_D3hot ((pci_power_t __force) 3)
138 #define PCI_D3cold ((pci_power_t __force) 4)
139 #define PCI_UNKNOWN ((pci_power_t __force) 5)
140 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
142 /* Remember to update this when the list above changes! */
143 extern const char *pci_power_names
[];
145 static inline const char *pci_power_name(pci_power_t state
)
147 return pci_power_names
[1 + (__force
int) state
];
150 #define PCI_PM_D2_DELAY 200
151 #define PCI_PM_D3_WAIT 10
152 #define PCI_PM_D3COLD_WAIT 100
153 #define PCI_PM_BUS_WAIT 50
155 /** The pci_channel state describes connectivity between the CPU and
156 * the pci device. If some PCI bus between here and the pci device
157 * has crashed or locked up, this info is reflected here.
159 typedef unsigned int __bitwise pci_channel_state_t
;
161 enum pci_channel_state
{
162 /* I/O channel is in normal state */
163 pci_channel_io_normal
= (__force pci_channel_state_t
) 1,
165 /* I/O to channel is blocked */
166 pci_channel_io_frozen
= (__force pci_channel_state_t
) 2,
168 /* PCI card is dead */
169 pci_channel_io_perm_failure
= (__force pci_channel_state_t
) 3,
172 typedef unsigned int __bitwise pcie_reset_state_t
;
174 enum pcie_reset_state
{
175 /* Reset is NOT asserted (Use to deassert reset) */
176 pcie_deassert_reset
= (__force pcie_reset_state_t
) 1,
178 /* Use #PERST to reset PCIe device */
179 pcie_warm_reset
= (__force pcie_reset_state_t
) 2,
181 /* Use PCIe Hot Reset to reset device */
182 pcie_hot_reset
= (__force pcie_reset_state_t
) 3
185 typedef unsigned short __bitwise pci_dev_flags_t
;
187 /* INTX_DISABLE in PCI_COMMAND register disables MSI
190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
= (__force pci_dev_flags_t
) (1 << 0),
191 /* Device configuration is irrevocably lost if disabled into D3 */
192 PCI_DEV_FLAGS_NO_D3
= (__force pci_dev_flags_t
) (1 << 1),
193 /* Provide indication device is assigned by a Virtual Machine Manager */
194 PCI_DEV_FLAGS_ASSIGNED
= (__force pci_dev_flags_t
) (1 << 2),
195 /* Flag for quirk use to store if quirk-specific ACS is enabled */
196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
= (__force pci_dev_flags_t
) (1 << 3),
197 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
= (__force pci_dev_flags_t
) (1 << 5),
199 /* Do not use bus resets for device */
200 PCI_DEV_FLAGS_NO_BUS_RESET
= (__force pci_dev_flags_t
) (1 << 6),
201 /* Do not use PM reset even if device advertises NoSoftRst- */
202 PCI_DEV_FLAGS_NO_PM_RESET
= (__force pci_dev_flags_t
) (1 << 7),
203 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0
= (__force pci_dev_flags_t
) (1 << 8),
205 /* a non-root bridge where translation occurs, stop alias search here */
206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
= (__force pci_dev_flags_t
) (1 << 9),
207 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET
= (__force pci_dev_flags_t
) (1 << 10),
209 /* Don't use Relaxed Ordering for TLPs directed at this device */
210 PCI_DEV_FLAGS_NO_RELAXED_ORDERING
= (__force pci_dev_flags_t
) (1 << 11),
213 enum pci_irq_reroute_variant
{
214 INTEL_IRQ_REROUTE_VARIANT
= 1,
215 MAX_IRQ_REROUTE_VARIANTS
= 3
218 typedef unsigned short __bitwise pci_bus_flags_t
;
220 PCI_BUS_FLAGS_NO_MSI
= (__force pci_bus_flags_t
) 1,
221 PCI_BUS_FLAGS_NO_MMRBC
= (__force pci_bus_flags_t
) 2,
222 PCI_BUS_FLAGS_NO_AERSID
= (__force pci_bus_flags_t
) 4,
225 /* These values come from the PCI Express Spec */
226 enum pcie_link_width
{
227 PCIE_LNK_WIDTH_RESRV
= 0x00,
235 PCIE_LNK_WIDTH_UNKNOWN
= 0xFF,
238 /* Based on the PCI Hotplug Spec, but some values are made up by us */
240 PCI_SPEED_33MHz
= 0x00,
241 PCI_SPEED_66MHz
= 0x01,
242 PCI_SPEED_66MHz_PCIX
= 0x02,
243 PCI_SPEED_100MHz_PCIX
= 0x03,
244 PCI_SPEED_133MHz_PCIX
= 0x04,
245 PCI_SPEED_66MHz_PCIX_ECC
= 0x05,
246 PCI_SPEED_100MHz_PCIX_ECC
= 0x06,
247 PCI_SPEED_133MHz_PCIX_ECC
= 0x07,
248 PCI_SPEED_66MHz_PCIX_266
= 0x09,
249 PCI_SPEED_100MHz_PCIX_266
= 0x0a,
250 PCI_SPEED_133MHz_PCIX_266
= 0x0b,
256 PCI_SPEED_66MHz_PCIX_533
= 0x11,
257 PCI_SPEED_100MHz_PCIX_533
= 0x12,
258 PCI_SPEED_133MHz_PCIX_533
= 0x13,
259 PCIE_SPEED_2_5GT
= 0x14,
260 PCIE_SPEED_5_0GT
= 0x15,
261 PCIE_SPEED_8_0GT
= 0x16,
262 PCIE_SPEED_16_0GT
= 0x17,
263 PCI_SPEED_UNKNOWN
= 0xff,
266 struct pci_cap_saved_data
{
273 struct pci_cap_saved_state
{
274 struct hlist_node next
;
275 struct pci_cap_saved_data cap
;
279 struct pcie_link_state
;
285 * The pci_dev structure is used to describe PCI devices.
288 struct list_head bus_list
; /* node in per-bus list */
289 struct pci_bus
*bus
; /* bus this device is on */
290 struct pci_bus
*subordinate
; /* bus this device bridges to */
292 void *sysdata
; /* hook for sys-specific extension */
293 struct proc_dir_entry
*procent
; /* device entry in /proc/bus/pci */
294 struct pci_slot
*slot
; /* Physical slot this device is in */
296 unsigned int devfn
; /* encoded device & function index */
297 unsigned short vendor
;
298 unsigned short device
;
299 unsigned short subsystem_vendor
;
300 unsigned short subsystem_device
;
301 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
302 u8 revision
; /* PCI revision, low byte of class word */
303 u8 hdr_type
; /* PCI header type (`multi' flag masked out) */
304 #ifdef CONFIG_PCIEAER
305 u16 aer_cap
; /* AER capability offset */
307 u8 pcie_cap
; /* PCIe capability offset */
308 u8 msi_cap
; /* MSI capability offset */
309 u8 msix_cap
; /* MSI-X capability offset */
310 u8 pcie_mpss
:3; /* PCIe Max Payload Size Supported */
311 u8 rom_base_reg
; /* which config register controls the ROM */
312 u8 pin
; /* which interrupt pin this device uses */
313 u16 pcie_flags_reg
; /* cached PCIe Capabilities Register */
314 unsigned long *dma_alias_mask
;/* mask of enabled devfn aliases */
316 struct pci_driver
*driver
; /* which driver has allocated this device */
317 u64 dma_mask
; /* Mask of the bits of bus address this
318 device implements. Normally this is
319 0xffffffff. You only need to change
320 this if your device has broken DMA
321 or supports 64-bit transfers. */
323 struct device_dma_parameters dma_parms
;
325 pci_power_t current_state
; /* Current operating state. In ACPI-speak,
326 this is D0-D3, D0 being fully functional,
328 u8 pm_cap
; /* PM capability offset */
329 unsigned int pme_support
:5; /* Bitmask of states from which PME#
331 unsigned int pme_poll
:1; /* Poll device's PME status bit */
332 unsigned int d1_support
:1; /* Low power state D1 is supported */
333 unsigned int d2_support
:1; /* Low power state D2 is supported */
334 unsigned int no_d1d2
:1; /* D1 and D2 are forbidden */
335 unsigned int no_d3cold
:1; /* D3cold is forbidden */
336 unsigned int bridge_d3
:1; /* Allow D3 for bridge */
337 unsigned int d3cold_allowed
:1; /* D3cold is allowed by user */
338 unsigned int mmio_always_on
:1; /* disallow turning off io/mem
339 decoding during bar sizing */
340 unsigned int wakeup_prepared
:1;
341 unsigned int runtime_d3cold
:1; /* whether go through runtime
342 D3cold, not set for devices
343 powered on/off by the
344 corresponding bridge */
345 unsigned int skip_bus_pm
:1; /* Internal: Skip bus-level PM */
346 unsigned int ignore_hotplug
:1; /* Ignore hotplug events */
347 unsigned int hotplug_user_indicators
:1; /* SlotCtl indicators
348 controlled exclusively by
350 unsigned int d3_delay
; /* D3->D0 transition time in ms */
351 unsigned int d3cold_delay
; /* D3cold->D0 transition time in ms */
353 #ifdef CONFIG_PCIEASPM
354 struct pcie_link_state
*link_state
; /* ASPM link state */
355 unsigned int ltr_path
:1; /* Latency Tolerance Reporting
356 supported from root to here */
359 pci_channel_state_t error_state
; /* current connectivity state */
360 struct device dev
; /* Generic device interface */
362 int cfg_size
; /* Size of configuration space */
365 * Instead of touching interrupt line and base address registers
366 * directly, use the values stored here. They might be different!
369 struct resource resource
[DEVICE_COUNT_RESOURCE
]; /* I/O and memory regions + expansion ROMs */
371 bool match_driver
; /* Skip attaching driver */
372 /* These fields are used by common fixups */
373 unsigned int transparent
:1; /* Subtractive decode PCI bridge */
374 unsigned int multifunction
:1;/* Part of multi-function device */
375 /* keep track of device state */
376 unsigned int is_added
:1;
377 unsigned int is_busmaster
:1; /* device is busmaster */
378 unsigned int no_msi
:1; /* device may not use msi */
379 unsigned int no_64bit_msi
:1; /* device may only use 32-bit MSIs */
380 unsigned int block_cfg_access
:1; /* config space access is blocked */
381 unsigned int broken_parity_status
:1; /* Device generates false positive parity */
382 unsigned int irq_reroute_variant
:2; /* device needs IRQ rerouting variant */
383 unsigned int msi_enabled
:1;
384 unsigned int msix_enabled
:1;
385 unsigned int ari_enabled
:1; /* ARI forwarding */
386 unsigned int ats_enabled
:1; /* Address Translation Service */
387 unsigned int pasid_enabled
:1; /* Process Address Space ID */
388 unsigned int pri_enabled
:1; /* Page Request Interface */
389 unsigned int is_managed
:1;
390 unsigned int needs_freset
:1; /* Dev requires fundamental reset */
391 unsigned int state_saved
:1;
392 unsigned int is_physfn
:1;
393 unsigned int is_virtfn
:1;
394 unsigned int reset_fn
:1;
395 unsigned int is_hotplug_bridge
:1;
396 unsigned int is_thunderbolt
:1; /* Thunderbolt controller */
398 * Devices marked being untrusted are the ones that can potentially
399 * execute DMA attacks and similar. They are typically connected
400 * through external ports such as Thunderbolt but not limited to
401 * that. When an IOMMU is enabled they should be getting full
402 * mappings to make sure they cannot access arbitrary memory.
404 unsigned int untrusted
:1;
405 unsigned int __aer_firmware_first_valid
:1;
406 unsigned int __aer_firmware_first
:1;
407 unsigned int broken_intx_masking
:1; /* INTx masking can't be used */
408 unsigned int io_window_1k
:1; /* Intel P2P bridge 1K I/O windows */
409 unsigned int irq_managed
:1;
410 unsigned int has_secondary_link
:1;
411 unsigned int non_compliant_bars
:1; /* broken BARs; ignore them */
412 unsigned int is_probed
:1; /* device probing in progress */
413 pci_dev_flags_t dev_flags
;
414 atomic_t enable_cnt
; /* pci_enable_device has been called */
416 u32 saved_config_space
[16]; /* config space saved at suspend time */
417 struct hlist_head saved_cap_space
;
418 struct bin_attribute
*rom_attr
; /* attribute descriptor for sysfs ROM entry */
419 int rom_attr_enabled
; /* has display of the rom attribute been enabled? */
420 struct bin_attribute
*res_attr
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for resources */
421 struct bin_attribute
*res_attr_wc
[DEVICE_COUNT_RESOURCE
]; /* sysfs file for WC mapping of resources */
423 #ifdef CONFIG_PCIE_PTM
424 unsigned int ptm_root
:1;
425 unsigned int ptm_enabled
:1;
428 #ifdef CONFIG_PCI_MSI
429 const struct attribute_group
**msi_irq_groups
;
432 #ifdef CONFIG_PCI_ATS
434 struct pci_sriov
*sriov
; /* SR-IOV capability related */
435 struct pci_dev
*physfn
; /* the PF this VF is associated with */
437 u16 ats_cap
; /* ATS Capability offset */
438 u8 ats_stu
; /* ATS Smallest Translation Unit */
439 atomic_t ats_ref_cnt
; /* number of VFs with ATS enabled */
441 #ifdef CONFIG_PCI_PRI
442 u32 pri_reqs_alloc
; /* Number of PRI requests allocated */
444 #ifdef CONFIG_PCI_PASID
447 phys_addr_t rom
; /* Physical address of ROM if it's not from the BAR */
448 size_t romlen
; /* Length of ROM if it's not from the BAR */
449 char *driver_override
; /* Driver name to force a match */
451 unsigned long priv_flags
; /* Private flags for the pci driver */
454 static inline struct pci_dev
*pci_physfn(struct pci_dev
*dev
)
456 #ifdef CONFIG_PCI_IOV
463 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
);
465 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
466 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
468 static inline int pci_channel_offline(struct pci_dev
*pdev
)
470 return (pdev
->error_state
!= pci_channel_io_normal
);
473 struct pci_host_bridge
{
475 struct pci_bus
*bus
; /* root bus */
479 struct list_head windows
; /* resource_entry */
480 u8 (*swizzle_irq
)(struct pci_dev
*, u8
*); /* platform IRQ swizzler */
481 int (*map_irq
)(const struct pci_dev
*, u8
, u8
);
482 void (*release_fn
)(struct pci_host_bridge
*);
484 struct msi_controller
*msi
;
485 unsigned int ignore_reset_delay
:1; /* for entire hierarchy */
486 unsigned int no_ext_tags
:1; /* no Extended Tags */
487 /* Resource alignment requirements */
488 resource_size_t (*align_resource
)(struct pci_dev
*dev
,
489 const struct resource
*res
,
490 resource_size_t start
,
491 resource_size_t size
,
492 resource_size_t align
);
493 unsigned long private[0] ____cacheline_aligned
;
496 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
498 static inline void *pci_host_bridge_priv(struct pci_host_bridge
*bridge
)
500 return (void *)bridge
->private;
503 static inline struct pci_host_bridge
*pci_host_bridge_from_priv(void *priv
)
505 return container_of(priv
, struct pci_host_bridge
, private);
508 struct pci_host_bridge
*pci_alloc_host_bridge(size_t priv
);
509 struct pci_host_bridge
*devm_pci_alloc_host_bridge(struct device
*dev
,
511 void pci_free_host_bridge(struct pci_host_bridge
*bridge
);
512 struct pci_host_bridge
*pci_find_host_bridge(struct pci_bus
*bus
);
514 void pci_set_host_bridge_release(struct pci_host_bridge
*bridge
,
515 void (*release_fn
)(struct pci_host_bridge
*),
518 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
);
521 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
522 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
523 * buses below host bridges or subtractive decode bridges) go in the list.
524 * Use pci_bus_for_each_resource() to iterate through all the resources.
528 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
529 * and there's no way to program the bridge with the details of the window.
530 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
531 * decode bit set, because they are explicit and can be programmed with _SRS.
533 #define PCI_SUBTRACTIVE_DECODE 0x1
535 struct pci_bus_resource
{
536 struct list_head list
;
537 struct resource
*res
;
541 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
544 struct list_head node
; /* node in list of buses */
545 struct pci_bus
*parent
; /* parent bus this bridge is on */
546 struct list_head children
; /* list of child buses */
547 struct list_head devices
; /* list of devices on this bus */
548 struct pci_dev
*self
; /* bridge device as seen by parent */
549 struct list_head slots
; /* list of slots on this bus;
550 protected by pci_slot_mutex */
551 struct resource
*resource
[PCI_BRIDGE_RESOURCE_NUM
];
552 struct list_head resources
; /* address space routed to this bus */
553 struct resource busn_res
; /* bus numbers routed to this bus */
555 struct pci_ops
*ops
; /* configuration access functions */
556 struct msi_controller
*msi
; /* MSI controller */
557 void *sysdata
; /* hook for sys-specific extension */
558 struct proc_dir_entry
*procdir
; /* directory entry in /proc/bus/pci */
560 unsigned char number
; /* bus number */
561 unsigned char primary
; /* number of primary bridge */
562 unsigned char max_bus_speed
; /* enum pci_bus_speed */
563 unsigned char cur_bus_speed
; /* enum pci_bus_speed */
564 #ifdef CONFIG_PCI_DOMAINS_GENERIC
570 unsigned short bridge_ctl
; /* manage NO_ISA/FBB/et al behaviors */
571 pci_bus_flags_t bus_flags
; /* inherited by child buses */
572 struct device
*bridge
;
574 struct bin_attribute
*legacy_io
; /* legacy I/O for this bus */
575 struct bin_attribute
*legacy_mem
; /* legacy mem */
576 unsigned int is_added
:1;
579 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
582 * Returns true if the PCI bus is root (behind host-PCI bridge),
585 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
586 * This is incorrect because "virtual" buses added for SR-IOV (via
587 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
589 static inline bool pci_is_root_bus(struct pci_bus
*pbus
)
591 return !(pbus
->parent
);
595 * pci_is_bridge - check if the PCI device is a bridge
598 * Return true if the PCI device is bridge whether it has subordinate
601 static inline bool pci_is_bridge(struct pci_dev
*dev
)
603 return dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
604 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
;
607 #define for_each_pci_bridge(dev, bus) \
608 list_for_each_entry(dev, &bus->devices, bus_list) \
609 if (!pci_is_bridge(dev)) {} else
611 static inline struct pci_dev
*pci_upstream_bridge(struct pci_dev
*dev
)
613 dev
= pci_physfn(dev
);
614 if (pci_is_root_bus(dev
->bus
))
617 return dev
->bus
->self
;
620 struct device
*pci_get_host_bridge_device(struct pci_dev
*dev
);
621 void pci_put_host_bridge_device(struct device
*dev
);
623 #ifdef CONFIG_PCI_MSI
624 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
)
626 return pci_dev
->msi_enabled
|| pci_dev
->msix_enabled
;
629 static inline bool pci_dev_msi_enabled(struct pci_dev
*pci_dev
) { return false; }
633 * Error values that may be returned by PCI functions.
635 #define PCIBIOS_SUCCESSFUL 0x00
636 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
637 #define PCIBIOS_BAD_VENDOR_ID 0x83
638 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
639 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
640 #define PCIBIOS_SET_FAILED 0x88
641 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
644 * Translate above to generic errno for passing back through non-PCI code.
646 static inline int pcibios_err_to_errno(int err
)
648 if (err
<= PCIBIOS_SUCCESSFUL
)
649 return err
; /* Assume already errno */
652 case PCIBIOS_FUNC_NOT_SUPPORTED
:
654 case PCIBIOS_BAD_VENDOR_ID
:
656 case PCIBIOS_DEVICE_NOT_FOUND
:
658 case PCIBIOS_BAD_REGISTER_NUMBER
:
660 case PCIBIOS_SET_FAILED
:
662 case PCIBIOS_BUFFER_TOO_SMALL
:
669 /* Low-level architecture-dependent routines */
672 int (*add_bus
)(struct pci_bus
*bus
);
673 void (*remove_bus
)(struct pci_bus
*bus
);
674 void __iomem
*(*map_bus
)(struct pci_bus
*bus
, unsigned int devfn
, int where
);
675 int (*read
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
676 int (*write
)(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
680 * ACPI needs to be able to access PCI config space before we've done a
681 * PCI bus scan and created pci_bus structures.
683 int raw_pci_read(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
684 int reg
, int len
, u32
*val
);
685 int raw_pci_write(unsigned int domain
, unsigned int bus
, unsigned int devfn
,
686 int reg
, int len
, u32 val
);
688 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
689 typedef u64 pci_bus_addr_t
;
691 typedef u32 pci_bus_addr_t
;
694 struct pci_bus_region
{
695 pci_bus_addr_t start
;
700 spinlock_t lock
; /* protects list, index */
701 struct list_head list
; /* for IDs added at runtime */
706 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
707 * a set of callbacks in struct pci_error_handlers, that device driver
708 * will be notified of PCI bus errors, and will be driven to recovery
709 * when an error occurs.
712 typedef unsigned int __bitwise pci_ers_result_t
;
714 enum pci_ers_result
{
715 /* no result/none/not supported in device driver */
716 PCI_ERS_RESULT_NONE
= (__force pci_ers_result_t
) 1,
718 /* Device driver can recover without slot reset */
719 PCI_ERS_RESULT_CAN_RECOVER
= (__force pci_ers_result_t
) 2,
721 /* Device driver wants slot to be reset. */
722 PCI_ERS_RESULT_NEED_RESET
= (__force pci_ers_result_t
) 3,
724 /* Device has completely failed, is unrecoverable */
725 PCI_ERS_RESULT_DISCONNECT
= (__force pci_ers_result_t
) 4,
727 /* Device driver is fully recovered and operational */
728 PCI_ERS_RESULT_RECOVERED
= (__force pci_ers_result_t
) 5,
730 /* No AER capabilities registered for the driver */
731 PCI_ERS_RESULT_NO_AER_DRIVER
= (__force pci_ers_result_t
) 6,
734 /* PCI bus error event callbacks */
735 struct pci_error_handlers
{
736 /* PCI bus error detected on this device */
737 pci_ers_result_t (*error_detected
)(struct pci_dev
*dev
,
738 enum pci_channel_state error
);
740 /* MMIO has been re-enabled, but not DMA */
741 pci_ers_result_t (*mmio_enabled
)(struct pci_dev
*dev
);
743 /* PCI slot has been reset */
744 pci_ers_result_t (*slot_reset
)(struct pci_dev
*dev
);
746 /* PCI function reset prepare or completed */
747 void (*reset_prepare
)(struct pci_dev
*dev
);
748 void (*reset_done
)(struct pci_dev
*dev
);
750 /* Device driver may resume normal operations */
751 void (*resume
)(struct pci_dev
*dev
);
757 struct list_head node
;
759 const struct pci_device_id
*id_table
; /* must be non-NULL for probe to be called */
760 int (*probe
) (struct pci_dev
*dev
, const struct pci_device_id
*id
); /* New device inserted */
761 void (*remove
) (struct pci_dev
*dev
); /* Device removed (NULL if not a hot-plug capable driver) */
762 int (*suspend
) (struct pci_dev
*dev
, pm_message_t state
); /* Device suspended */
763 int (*suspend_late
) (struct pci_dev
*dev
, pm_message_t state
);
764 int (*resume_early
) (struct pci_dev
*dev
);
765 int (*resume
) (struct pci_dev
*dev
); /* Device woken up */
766 void (*shutdown
) (struct pci_dev
*dev
);
767 int (*sriov_configure
) (struct pci_dev
*dev
, int num_vfs
); /* PF pdev */
768 const struct pci_error_handlers
*err_handler
;
769 const struct attribute_group
**groups
;
770 struct device_driver driver
;
771 struct pci_dynids dynids
;
774 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
777 * PCI_DEVICE - macro used to describe a specific pci device
778 * @vend: the 16 bit PCI Vendor ID
779 * @dev: the 16 bit PCI Device ID
781 * This macro is used to create a struct pci_device_id that matches a
782 * specific device. The subvendor and subdevice fields will be set to
785 #define PCI_DEVICE(vend,dev) \
786 .vendor = (vend), .device = (dev), \
787 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
790 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
791 * @vend: the 16 bit PCI Vendor ID
792 * @dev: the 16 bit PCI Device ID
793 * @subvend: the 16 bit PCI Subvendor ID
794 * @subdev: the 16 bit PCI Subdevice ID
796 * This macro is used to create a struct pci_device_id that matches a
797 * specific device with subsystem information.
799 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
800 .vendor = (vend), .device = (dev), \
801 .subvendor = (subvend), .subdevice = (subdev)
804 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
805 * @dev_class: the class, subclass, prog-if triple for this device
806 * @dev_class_mask: the class mask for this device
808 * This macro is used to create a struct pci_device_id that matches a
809 * specific PCI class. The vendor, device, subvendor, and subdevice
810 * fields will be set to PCI_ANY_ID.
812 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
813 .class = (dev_class), .class_mask = (dev_class_mask), \
814 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
815 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
818 * PCI_VDEVICE - macro used to describe a specific pci device in short form
819 * @vend: the vendor name
820 * @dev: the 16 bit PCI Device ID
822 * This macro is used to create a struct pci_device_id that matches a
823 * specific PCI device. The subvendor, and subdevice fields will be set
824 * to PCI_ANY_ID. The macro allows the next field to follow as the device
828 #define PCI_VDEVICE(vend, dev) \
829 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
830 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
833 PCI_REASSIGN_ALL_RSRC
= 0x00000001, /* ignore firmware setup */
834 PCI_REASSIGN_ALL_BUS
= 0x00000002, /* reassign all bus numbers */
835 PCI_PROBE_ONLY
= 0x00000004, /* use existing setup */
836 PCI_CAN_SKIP_ISA_ALIGN
= 0x00000008, /* don't do ISA alignment */
837 PCI_ENABLE_PROC_DOMAINS
= 0x00000010, /* enable domains in /proc */
838 PCI_COMPAT_DOMAIN_0
= 0x00000020, /* ... except domain 0 */
839 PCI_SCAN_ALL_PCIE_DEVS
= 0x00000040, /* scan all, not just dev 0 */
842 /* these external functions are only available when PCI support is enabled */
845 extern unsigned int pci_flags
;
847 static inline void pci_set_flags(int flags
) { pci_flags
= flags
; }
848 static inline void pci_add_flags(int flags
) { pci_flags
|= flags
; }
849 static inline void pci_clear_flags(int flags
) { pci_flags
&= ~flags
; }
850 static inline int pci_has_flag(int flag
) { return pci_flags
& flag
; }
852 void pcie_bus_configure_settings(struct pci_bus
*bus
);
854 enum pcie_bus_config_types
{
855 PCIE_BUS_TUNE_OFF
, /* don't touch MPS at all */
856 PCIE_BUS_DEFAULT
, /* ensure MPS matches upstream bridge */
857 PCIE_BUS_SAFE
, /* use largest MPS boot-time devices support */
858 PCIE_BUS_PERFORMANCE
, /* use MPS and MRRS for best performance */
859 PCIE_BUS_PEER2PEER
, /* set MPS = 128 for all devices */
862 extern enum pcie_bus_config_types pcie_bus_config
;
864 extern struct bus_type pci_bus_type
;
866 /* Do NOT directly access these two variables, unless you are arch-specific PCI
867 * code, or PCI core code. */
868 extern struct list_head pci_root_buses
; /* list of all known PCI buses */
869 /* Some device drivers need know if PCI is initiated */
870 int no_pci_devices(void);
872 void pcibios_resource_survey_bus(struct pci_bus
*bus
);
873 void pcibios_bus_add_device(struct pci_dev
*pdev
);
874 void pcibios_add_bus(struct pci_bus
*bus
);
875 void pcibios_remove_bus(struct pci_bus
*bus
);
876 void pcibios_fixup_bus(struct pci_bus
*);
877 int __must_check
pcibios_enable_device(struct pci_dev
*, int mask
);
878 /* Architecture-specific versions may override this (weak) */
879 char *pcibios_setup(char *str
);
881 /* Used only when drivers/pci/setup.c is used */
882 resource_size_t
pcibios_align_resource(void *, const struct resource
*,
886 /* Weak but can be overriden by arch */
887 void pci_fixup_cardbus(struct pci_bus
*);
889 /* Generic PCI functions used internally */
891 void pcibios_resource_to_bus(struct pci_bus
*bus
, struct pci_bus_region
*region
,
892 struct resource
*res
);
893 void pcibios_bus_to_resource(struct pci_bus
*bus
, struct resource
*res
,
894 struct pci_bus_region
*region
);
895 void pcibios_scan_specific_bus(int busn
);
896 struct pci_bus
*pci_find_bus(int domain
, int busnr
);
897 void pci_bus_add_devices(const struct pci_bus
*bus
);
898 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
);
899 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
900 struct pci_ops
*ops
, void *sysdata
,
901 struct list_head
*resources
);
902 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int busmax
);
903 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int busmax
);
904 void pci_bus_release_busn_res(struct pci_bus
*b
);
905 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
906 struct pci_ops
*ops
, void *sysdata
,
907 struct list_head
*resources
);
908 int pci_scan_root_bus_bridge(struct pci_host_bridge
*bridge
);
909 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
911 void pcie_update_link_speed(struct pci_bus
*bus
, u16 link_status
);
912 struct pci_slot
*pci_create_slot(struct pci_bus
*parent
, int slot_nr
,
914 struct hotplug_slot
*hotplug
);
915 void pci_destroy_slot(struct pci_slot
*slot
);
917 void pci_dev_assign_slot(struct pci_dev
*dev
);
919 static inline void pci_dev_assign_slot(struct pci_dev
*dev
) { }
921 int pci_scan_slot(struct pci_bus
*bus
, int devfn
);
922 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
);
923 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
);
924 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
925 void pci_bus_add_device(struct pci_dev
*dev
);
926 void pci_read_bridge_bases(struct pci_bus
*child
);
927 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
928 struct resource
*res
);
929 struct pci_dev
*pci_find_pcie_root_port(struct pci_dev
*dev
);
930 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
);
931 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
);
932 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
);
933 struct pci_dev
*pci_dev_get(struct pci_dev
*dev
);
934 void pci_dev_put(struct pci_dev
*dev
);
935 void pci_remove_bus(struct pci_bus
*b
);
936 void pci_stop_and_remove_bus_device(struct pci_dev
*dev
);
937 void pci_stop_and_remove_bus_device_locked(struct pci_dev
*dev
);
938 void pci_stop_root_bus(struct pci_bus
*bus
);
939 void pci_remove_root_bus(struct pci_bus
*bus
);
940 void pci_setup_cardbus(struct pci_bus
*bus
);
941 void pcibios_setup_bridge(struct pci_bus
*bus
, unsigned long type
);
942 void pci_sort_breadthfirst(void);
943 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
944 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
946 /* Generic PCI functions exported to card drivers */
948 enum pci_lost_interrupt_reason
{
949 PCI_LOST_IRQ_NO_INFORMATION
= 0,
950 PCI_LOST_IRQ_DISABLE_MSI
,
951 PCI_LOST_IRQ_DISABLE_MSIX
,
952 PCI_LOST_IRQ_DISABLE_ACPI
,
954 enum pci_lost_interrupt_reason
pci_lost_interrupt(struct pci_dev
*dev
);
955 int pci_find_capability(struct pci_dev
*dev
, int cap
);
956 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
);
957 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
);
958 int pci_find_next_ext_capability(struct pci_dev
*dev
, int pos
, int cap
);
959 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
);
960 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
);
961 struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
);
963 struct pci_dev
*pci_get_device(unsigned int vendor
, unsigned int device
,
964 struct pci_dev
*from
);
965 struct pci_dev
*pci_get_subsys(unsigned int vendor
, unsigned int device
,
966 unsigned int ss_vendor
, unsigned int ss_device
,
967 struct pci_dev
*from
);
968 struct pci_dev
*pci_get_slot(struct pci_bus
*bus
, unsigned int devfn
);
969 struct pci_dev
*pci_get_domain_bus_and_slot(int domain
, unsigned int bus
,
971 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
974 return pci_get_domain_bus_and_slot(0, bus
, devfn
);
976 struct pci_dev
*pci_get_class(unsigned int class, struct pci_dev
*from
);
977 int pci_dev_present(const struct pci_device_id
*ids
);
979 int pci_bus_read_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
981 int pci_bus_read_config_word(struct pci_bus
*bus
, unsigned int devfn
,
982 int where
, u16
*val
);
983 int pci_bus_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
984 int where
, u32
*val
);
985 int pci_bus_write_config_byte(struct pci_bus
*bus
, unsigned int devfn
,
987 int pci_bus_write_config_word(struct pci_bus
*bus
, unsigned int devfn
,
989 int pci_bus_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
992 int pci_generic_config_read(struct pci_bus
*bus
, unsigned int devfn
,
993 int where
, int size
, u32
*val
);
994 int pci_generic_config_write(struct pci_bus
*bus
, unsigned int devfn
,
995 int where
, int size
, u32 val
);
996 int pci_generic_config_read32(struct pci_bus
*bus
, unsigned int devfn
,
997 int where
, int size
, u32
*val
);
998 int pci_generic_config_write32(struct pci_bus
*bus
, unsigned int devfn
,
999 int where
, int size
, u32 val
);
1001 struct pci_ops
*pci_bus_set_ops(struct pci_bus
*bus
, struct pci_ops
*ops
);
1003 int pci_read_config_byte(const struct pci_dev
*dev
, int where
, u8
*val
);
1004 int pci_read_config_word(const struct pci_dev
*dev
, int where
, u16
*val
);
1005 int pci_read_config_dword(const struct pci_dev
*dev
, int where
, u32
*val
);
1006 int pci_write_config_byte(const struct pci_dev
*dev
, int where
, u8 val
);
1007 int pci_write_config_word(const struct pci_dev
*dev
, int where
, u16 val
);
1008 int pci_write_config_dword(const struct pci_dev
*dev
, int where
, u32 val
);
1010 int pcie_capability_read_word(struct pci_dev
*dev
, int pos
, u16
*val
);
1011 int pcie_capability_read_dword(struct pci_dev
*dev
, int pos
, u32
*val
);
1012 int pcie_capability_write_word(struct pci_dev
*dev
, int pos
, u16 val
);
1013 int pcie_capability_write_dword(struct pci_dev
*dev
, int pos
, u32 val
);
1014 int pcie_capability_clear_and_set_word(struct pci_dev
*dev
, int pos
,
1015 u16 clear
, u16 set
);
1016 int pcie_capability_clear_and_set_dword(struct pci_dev
*dev
, int pos
,
1017 u32 clear
, u32 set
);
1019 static inline int pcie_capability_set_word(struct pci_dev
*dev
, int pos
,
1022 return pcie_capability_clear_and_set_word(dev
, pos
, 0, set
);
1025 static inline int pcie_capability_set_dword(struct pci_dev
*dev
, int pos
,
1028 return pcie_capability_clear_and_set_dword(dev
, pos
, 0, set
);
1031 static inline int pcie_capability_clear_word(struct pci_dev
*dev
, int pos
,
1034 return pcie_capability_clear_and_set_word(dev
, pos
, clear
, 0);
1037 static inline int pcie_capability_clear_dword(struct pci_dev
*dev
, int pos
,
1040 return pcie_capability_clear_and_set_dword(dev
, pos
, clear
, 0);
1043 /* user-space driven config access */
1044 int pci_user_read_config_byte(struct pci_dev
*dev
, int where
, u8
*val
);
1045 int pci_user_read_config_word(struct pci_dev
*dev
, int where
, u16
*val
);
1046 int pci_user_read_config_dword(struct pci_dev
*dev
, int where
, u32
*val
);
1047 int pci_user_write_config_byte(struct pci_dev
*dev
, int where
, u8 val
);
1048 int pci_user_write_config_word(struct pci_dev
*dev
, int where
, u16 val
);
1049 int pci_user_write_config_dword(struct pci_dev
*dev
, int where
, u32 val
);
1051 int __must_check
pci_enable_device(struct pci_dev
*dev
);
1052 int __must_check
pci_enable_device_io(struct pci_dev
*dev
);
1053 int __must_check
pci_enable_device_mem(struct pci_dev
*dev
);
1054 int __must_check
pci_reenable_device(struct pci_dev
*);
1055 int __must_check
pcim_enable_device(struct pci_dev
*pdev
);
1056 void pcim_pin_device(struct pci_dev
*pdev
);
1058 static inline bool pci_intx_mask_supported(struct pci_dev
*pdev
)
1061 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1062 * writable and no quirk has marked the feature broken.
1064 return !pdev
->broken_intx_masking
;
1067 static inline int pci_is_enabled(struct pci_dev
*pdev
)
1069 return (atomic_read(&pdev
->enable_cnt
) > 0);
1072 static inline int pci_is_managed(struct pci_dev
*pdev
)
1074 return pdev
->is_managed
;
1077 void pci_disable_device(struct pci_dev
*dev
);
1079 extern unsigned int pcibios_max_latency
;
1080 void pci_set_master(struct pci_dev
*dev
);
1081 void pci_clear_master(struct pci_dev
*dev
);
1083 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
);
1084 int pci_set_cacheline_size(struct pci_dev
*dev
);
1085 #define HAVE_PCI_SET_MWI
1086 int __must_check
pci_set_mwi(struct pci_dev
*dev
);
1087 int __must_check
pcim_set_mwi(struct pci_dev
*dev
);
1088 int pci_try_set_mwi(struct pci_dev
*dev
);
1089 void pci_clear_mwi(struct pci_dev
*dev
);
1090 void pci_intx(struct pci_dev
*dev
, int enable
);
1091 bool pci_check_and_mask_intx(struct pci_dev
*dev
);
1092 bool pci_check_and_unmask_intx(struct pci_dev
*dev
);
1093 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
);
1094 int pci_wait_for_pending_transaction(struct pci_dev
*dev
);
1095 int pcix_get_max_mmrbc(struct pci_dev
*dev
);
1096 int pcix_get_mmrbc(struct pci_dev
*dev
);
1097 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
);
1098 int pcie_get_readrq(struct pci_dev
*dev
);
1099 int pcie_set_readrq(struct pci_dev
*dev
, int rq
);
1100 int pcie_get_mps(struct pci_dev
*dev
);
1101 int pcie_set_mps(struct pci_dev
*dev
, int mps
);
1102 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
1103 enum pcie_link_width
*width
);
1104 void pcie_flr(struct pci_dev
*dev
);
1105 int __pci_reset_function_locked(struct pci_dev
*dev
);
1106 int pci_reset_function(struct pci_dev
*dev
);
1107 int pci_reset_function_locked(struct pci_dev
*dev
);
1108 int pci_try_reset_function(struct pci_dev
*dev
);
1109 int pci_probe_reset_slot(struct pci_slot
*slot
);
1110 int pci_reset_slot(struct pci_slot
*slot
);
1111 int pci_try_reset_slot(struct pci_slot
*slot
);
1112 int pci_probe_reset_bus(struct pci_bus
*bus
);
1113 int pci_reset_bus(struct pci_bus
*bus
);
1114 int pci_try_reset_bus(struct pci_bus
*bus
);
1115 void pci_reset_secondary_bus(struct pci_dev
*dev
);
1116 void pcibios_reset_secondary_bus(struct pci_dev
*dev
);
1117 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
);
1118 void pci_update_resource(struct pci_dev
*dev
, int resno
);
1119 int __must_check
pci_assign_resource(struct pci_dev
*dev
, int i
);
1120 int __must_check
pci_reassign_resource(struct pci_dev
*dev
, int i
, resource_size_t add_size
, resource_size_t align
);
1121 void pci_release_resource(struct pci_dev
*dev
, int resno
);
1122 int __must_check
pci_resize_resource(struct pci_dev
*dev
, int i
, int size
);
1123 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
);
1124 bool pci_device_is_present(struct pci_dev
*pdev
);
1125 void pci_ignore_hotplug(struct pci_dev
*dev
);
1127 int __printf(6, 7) pci_request_irq(struct pci_dev
*dev
, unsigned int nr
,
1128 irq_handler_t handler
, irq_handler_t thread_fn
, void *dev_id
,
1129 const char *fmt
, ...);
1130 void pci_free_irq(struct pci_dev
*dev
, unsigned int nr
, void *dev_id
);
1132 /* ROM control related routines */
1133 int pci_enable_rom(struct pci_dev
*pdev
);
1134 void pci_disable_rom(struct pci_dev
*pdev
);
1135 void __iomem __must_check
*pci_map_rom(struct pci_dev
*pdev
, size_t *size
);
1136 void pci_unmap_rom(struct pci_dev
*pdev
, void __iomem
*rom
);
1137 size_t pci_get_rom_size(struct pci_dev
*pdev
, void __iomem
*rom
, size_t size
);
1138 void __iomem __must_check
*pci_platform_rom(struct pci_dev
*pdev
, size_t *size
);
1140 /* Power management related routines */
1141 int pci_save_state(struct pci_dev
*dev
);
1142 void pci_restore_state(struct pci_dev
*dev
);
1143 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
);
1144 int pci_load_saved_state(struct pci_dev
*dev
,
1145 struct pci_saved_state
*state
);
1146 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1147 struct pci_saved_state
**state
);
1148 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
);
1149 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
,
1151 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
);
1152 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
,
1153 u16 cap
, unsigned int size
);
1154 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
);
1155 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
);
1156 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
);
1157 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
);
1158 void pci_pme_active(struct pci_dev
*dev
, bool enable
);
1159 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
);
1160 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
);
1161 int pci_prepare_to_sleep(struct pci_dev
*dev
);
1162 int pci_back_from_sleep(struct pci_dev
*dev
);
1163 bool pci_dev_run_wake(struct pci_dev
*dev
);
1164 bool pci_check_pme_status(struct pci_dev
*dev
);
1165 void pci_pme_wakeup_bus(struct pci_bus
*bus
);
1166 void pci_d3cold_enable(struct pci_dev
*dev
);
1167 void pci_d3cold_disable(struct pci_dev
*dev
);
1168 bool pcie_relaxed_ordering_enabled(struct pci_dev
*dev
);
1170 /* PCI Virtual Channel */
1171 int pci_save_vc_state(struct pci_dev
*dev
);
1172 void pci_restore_vc_state(struct pci_dev
*dev
);
1173 void pci_allocate_vc_save_buffers(struct pci_dev
*dev
);
1175 /* For use by arch with custom probe code */
1176 void set_pcie_port_type(struct pci_dev
*pdev
);
1177 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
);
1179 /* Functions for PCI Hotplug drivers to use */
1180 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1181 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
);
1182 unsigned int pci_rescan_bus(struct pci_bus
*bus
);
1183 void pci_lock_rescan_remove(void);
1184 void pci_unlock_rescan_remove(void);
1186 /* Vital product data routines */
1187 ssize_t
pci_read_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, void *buf
);
1188 ssize_t
pci_write_vpd(struct pci_dev
*dev
, loff_t pos
, size_t count
, const void *buf
);
1189 int pci_set_vpd_size(struct pci_dev
*dev
, size_t len
);
1191 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1192 resource_size_t
pcibios_retrieve_fw_addr(struct pci_dev
*dev
, int idx
);
1193 void pci_bus_assign_resources(const struct pci_bus
*bus
);
1194 void pci_bus_claim_resources(struct pci_bus
*bus
);
1195 void pci_bus_size_bridges(struct pci_bus
*bus
);
1196 int pci_claim_resource(struct pci_dev
*, int);
1197 int pci_claim_bridge_resource(struct pci_dev
*bridge
, int i
);
1198 void pci_assign_unassigned_resources(void);
1199 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
);
1200 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
);
1201 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
);
1202 int pci_reassign_bridge_resources(struct pci_dev
*bridge
, unsigned long type
);
1203 void pdev_enable_device(struct pci_dev
*);
1204 int pci_enable_resources(struct pci_dev
*, int mask
);
1205 void pci_assign_irq(struct pci_dev
*dev
);
1206 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
);
1207 #define HAVE_PCI_REQ_REGIONS 2
1208 int __must_check
pci_request_regions(struct pci_dev
*, const char *);
1209 int __must_check
pci_request_regions_exclusive(struct pci_dev
*, const char *);
1210 void pci_release_regions(struct pci_dev
*);
1211 int __must_check
pci_request_region(struct pci_dev
*, int, const char *);
1212 int __must_check
pci_request_region_exclusive(struct pci_dev
*, int, const char *);
1213 void pci_release_region(struct pci_dev
*, int);
1214 int pci_request_selected_regions(struct pci_dev
*, int, const char *);
1215 int pci_request_selected_regions_exclusive(struct pci_dev
*, int, const char *);
1216 void pci_release_selected_regions(struct pci_dev
*, int);
1218 /* drivers/pci/bus.c */
1219 struct pci_bus
*pci_bus_get(struct pci_bus
*bus
);
1220 void pci_bus_put(struct pci_bus
*bus
);
1221 void pci_add_resource(struct list_head
*resources
, struct resource
*res
);
1222 void pci_add_resource_offset(struct list_head
*resources
, struct resource
*res
,
1223 resource_size_t offset
);
1224 void pci_free_resource_list(struct list_head
*resources
);
1225 void pci_bus_add_resource(struct pci_bus
*bus
, struct resource
*res
,
1226 unsigned int flags
);
1227 struct resource
*pci_bus_resource_n(const struct pci_bus
*bus
, int n
);
1228 void pci_bus_remove_resources(struct pci_bus
*bus
);
1229 int devm_request_pci_bus_resources(struct device
*dev
,
1230 struct list_head
*resources
);
1232 #define pci_bus_for_each_resource(bus, res, i) \
1234 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1237 int __must_check
pci_bus_alloc_resource(struct pci_bus
*bus
,
1238 struct resource
*res
, resource_size_t size
,
1239 resource_size_t align
, resource_size_t min
,
1240 unsigned long type_mask
,
1241 resource_size_t (*alignf
)(void *,
1242 const struct resource
*,
1248 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
1249 resource_size_t size
);
1250 unsigned long pci_address_to_pio(phys_addr_t addr
);
1251 phys_addr_t
pci_pio_to_address(unsigned long pio
);
1252 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
);
1253 int devm_pci_remap_iospace(struct device
*dev
, const struct resource
*res
,
1254 phys_addr_t phys_addr
);
1255 void pci_unmap_iospace(struct resource
*res
);
1256 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
1257 resource_size_t offset
,
1258 resource_size_t size
);
1259 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
1260 struct resource
*res
);
1262 static inline pci_bus_addr_t
pci_bus_address(struct pci_dev
*pdev
, int bar
)
1264 struct pci_bus_region region
;
1266 pcibios_resource_to_bus(pdev
->bus
, ®ion
, &pdev
->resource
[bar
]);
1267 return region
.start
;
1270 /* Proper probing supporting hot-pluggable devices */
1271 int __must_check
__pci_register_driver(struct pci_driver
*, struct module
*,
1272 const char *mod_name
);
1275 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1277 #define pci_register_driver(driver) \
1278 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1280 void pci_unregister_driver(struct pci_driver
*dev
);
1283 * module_pci_driver() - Helper macro for registering a PCI driver
1284 * @__pci_driver: pci_driver struct
1286 * Helper macro for PCI drivers which do not do anything special in module
1287 * init/exit. This eliminates a lot of boilerplate. Each module may only
1288 * use this macro once, and calling it replaces module_init() and module_exit()
1290 #define module_pci_driver(__pci_driver) \
1291 module_driver(__pci_driver, pci_register_driver, \
1292 pci_unregister_driver)
1295 * builtin_pci_driver() - Helper macro for registering a PCI driver
1296 * @__pci_driver: pci_driver struct
1298 * Helper macro for PCI drivers which do not do anything special in their
1299 * init code. This eliminates a lot of boilerplate. Each driver may only
1300 * use this macro once, and calling it replaces device_initcall(...)
1302 #define builtin_pci_driver(__pci_driver) \
1303 builtin_driver(__pci_driver, pci_register_driver)
1305 struct pci_driver
*pci_dev_driver(const struct pci_dev
*dev
);
1306 int pci_add_dynid(struct pci_driver
*drv
,
1307 unsigned int vendor
, unsigned int device
,
1308 unsigned int subvendor
, unsigned int subdevice
,
1309 unsigned int class, unsigned int class_mask
,
1310 unsigned long driver_data
);
1311 const struct pci_device_id
*pci_match_id(const struct pci_device_id
*ids
,
1312 struct pci_dev
*dev
);
1313 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
,
1316 void pci_walk_bus(struct pci_bus
*top
, int (*cb
)(struct pci_dev
*, void *),
1318 int pci_cfg_space_size(struct pci_dev
*dev
);
1319 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
);
1320 void pci_setup_bridge(struct pci_bus
*bus
);
1321 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
1322 unsigned long type
);
1323 resource_size_t
pcibios_iov_resource_alignment(struct pci_dev
*dev
, int resno
);
1325 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1326 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1328 int pci_set_vga_state(struct pci_dev
*pdev
, bool decode
,
1329 unsigned int command_bits
, u32 flags
);
1331 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1332 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1333 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1334 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1335 #define PCI_IRQ_ALL_TYPES \
1336 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1338 /* kmem_cache style wrapper around pci_alloc_consistent() */
1340 #include <linux/pci-dma.h>
1341 #include <linux/dmapool.h>
1343 #define pci_pool dma_pool
1344 #define pci_pool_create(name, pdev, size, align, allocation) \
1345 dma_pool_create(name, &pdev->dev, size, align, allocation)
1346 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1347 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1348 #define pci_pool_zalloc(pool, flags, handle) \
1349 dma_pool_zalloc(pool, flags, handle)
1350 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1353 u32 vector
; /* kernel uses to write allocated vector */
1354 u16 entry
; /* driver uses to specify entry, OS writes */
1357 #ifdef CONFIG_PCI_MSI
1358 int pci_msi_vec_count(struct pci_dev
*dev
);
1359 void pci_disable_msi(struct pci_dev
*dev
);
1360 int pci_msix_vec_count(struct pci_dev
*dev
);
1361 void pci_disable_msix(struct pci_dev
*dev
);
1362 void pci_restore_msi_state(struct pci_dev
*dev
);
1363 int pci_msi_enabled(void);
1364 int pci_enable_msi(struct pci_dev
*dev
);
1365 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1366 int minvec
, int maxvec
);
1367 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1368 struct msix_entry
*entries
, int nvec
)
1370 int rc
= pci_enable_msix_range(dev
, entries
, nvec
, nvec
);
1375 int pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1376 unsigned int max_vecs
, unsigned int flags
,
1377 const struct irq_affinity
*affd
);
1379 void pci_free_irq_vectors(struct pci_dev
*dev
);
1380 int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
);
1381 const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*pdev
, int vec
);
1382 int pci_irq_get_node(struct pci_dev
*pdev
, int vec
);
1385 static inline int pci_msi_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1386 static inline void pci_disable_msi(struct pci_dev
*dev
) { }
1387 static inline int pci_msix_vec_count(struct pci_dev
*dev
) { return -ENOSYS
; }
1388 static inline void pci_disable_msix(struct pci_dev
*dev
) { }
1389 static inline void pci_restore_msi_state(struct pci_dev
*dev
) { }
1390 static inline int pci_msi_enabled(void) { return 0; }
1391 static inline int pci_enable_msi(struct pci_dev
*dev
)
1393 static inline int pci_enable_msix_range(struct pci_dev
*dev
,
1394 struct msix_entry
*entries
, int minvec
, int maxvec
)
1396 static inline int pci_enable_msix_exact(struct pci_dev
*dev
,
1397 struct msix_entry
*entries
, int nvec
)
1401 pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1402 unsigned int max_vecs
, unsigned int flags
,
1403 const struct irq_affinity
*aff_desc
)
1405 if ((flags
& PCI_IRQ_LEGACY
) && min_vecs
== 1 && dev
->irq
)
1410 static inline void pci_free_irq_vectors(struct pci_dev
*dev
)
1414 static inline int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
)
1416 if (WARN_ON_ONCE(nr
> 0))
1420 static inline const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*pdev
,
1423 return cpu_possible_mask
;
1426 static inline int pci_irq_get_node(struct pci_dev
*pdev
, int vec
)
1428 return first_online_node
;
1433 pci_alloc_irq_vectors(struct pci_dev
*dev
, unsigned int min_vecs
,
1434 unsigned int max_vecs
, unsigned int flags
)
1436 return pci_alloc_irq_vectors_affinity(dev
, min_vecs
, max_vecs
, flags
,
1441 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1442 * @d: the INTx IRQ domain
1443 * @node: the DT node for the device whose interrupt we're translating
1444 * @intspec: the interrupt specifier data from the DT
1445 * @intsize: the number of entries in @intspec
1446 * @out_hwirq: pointer at which to write the hwirq number
1447 * @out_type: pointer at which to write the interrupt type
1449 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1450 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1451 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1452 * INTx value to obtain the hwirq number.
1454 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1456 static inline int pci_irqd_intx_xlate(struct irq_domain
*d
,
1457 struct device_node
*node
,
1459 unsigned int intsize
,
1460 unsigned long *out_hwirq
,
1461 unsigned int *out_type
)
1463 const u32 intx
= intspec
[0];
1465 if (intx
< PCI_INTERRUPT_INTA
|| intx
> PCI_INTERRUPT_INTD
)
1468 *out_hwirq
= intx
- PCI_INTERRUPT_INTA
;
1472 #ifdef CONFIG_PCIEPORTBUS
1473 extern bool pcie_ports_disabled
;
1474 extern bool pcie_ports_auto
;
1476 #define pcie_ports_disabled true
1477 #define pcie_ports_auto false
1480 #ifdef CONFIG_PCIEASPM
1481 bool pcie_aspm_support_enabled(void);
1483 static inline bool pcie_aspm_support_enabled(void) { return false; }
1486 #ifdef CONFIG_PCIEAER
1487 void pci_no_aer(void);
1488 bool pci_aer_available(void);
1489 int pci_aer_init(struct pci_dev
*dev
);
1491 static inline void pci_no_aer(void) { }
1492 static inline bool pci_aer_available(void) { return false; }
1493 static inline int pci_aer_init(struct pci_dev
*d
) { return -ENODEV
; }
1496 #ifdef CONFIG_PCIE_ECRC
1497 void pcie_set_ecrc_checking(struct pci_dev
*dev
);
1498 void pcie_ecrc_get_policy(char *str
);
1500 static inline void pcie_set_ecrc_checking(struct pci_dev
*dev
) { }
1501 static inline void pcie_ecrc_get_policy(char *str
) { }
1504 #ifdef CONFIG_PCI_ATS
1505 /* Address Translation Service */
1506 void pci_ats_init(struct pci_dev
*dev
);
1507 int pci_enable_ats(struct pci_dev
*dev
, int ps
);
1508 void pci_disable_ats(struct pci_dev
*dev
);
1509 int pci_ats_queue_depth(struct pci_dev
*dev
);
1511 static inline void pci_ats_init(struct pci_dev
*d
) { }
1512 static inline int pci_enable_ats(struct pci_dev
*d
, int ps
) { return -ENODEV
; }
1513 static inline void pci_disable_ats(struct pci_dev
*d
) { }
1514 static inline int pci_ats_queue_depth(struct pci_dev
*d
) { return -ENODEV
; }
1517 #ifdef CONFIG_PCIE_PTM
1518 int pci_enable_ptm(struct pci_dev
*dev
, u8
*granularity
);
1520 static inline int pci_enable_ptm(struct pci_dev
*dev
, u8
*granularity
)
1524 void pci_cfg_access_lock(struct pci_dev
*dev
);
1525 bool pci_cfg_access_trylock(struct pci_dev
*dev
);
1526 void pci_cfg_access_unlock(struct pci_dev
*dev
);
1529 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1530 * a PCI domain is defined to be a set of PCI buses which share
1531 * configuration space.
1533 #ifdef CONFIG_PCI_DOMAINS
1534 extern int pci_domains_supported
;
1535 int pci_get_new_domain_nr(void);
1537 enum { pci_domains_supported
= 0 };
1538 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1539 static inline int pci_proc_domain(struct pci_bus
*bus
) { return 0; }
1540 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1541 #endif /* CONFIG_PCI_DOMAINS */
1544 * Generic implementation for PCI domain support. If your
1545 * architecture does not need custom management of PCI
1546 * domains then this implementation will be used
1548 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1549 static inline int pci_domain_nr(struct pci_bus
*bus
)
1551 return bus
->domain_nr
;
1554 int acpi_pci_bus_find_domain_nr(struct pci_bus
*bus
);
1556 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus
*bus
)
1559 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
);
1562 /* some architectures require additional setup to direct VGA traffic */
1563 typedef int (*arch_set_vga_state_t
)(struct pci_dev
*pdev
, bool decode
,
1564 unsigned int command_bits
, u32 flags
);
1565 void pci_register_set_vga_state(arch_set_vga_state_t func
);
1568 pci_request_io_regions(struct pci_dev
*pdev
, const char *name
)
1570 return pci_request_selected_regions(pdev
,
1571 pci_select_bars(pdev
, IORESOURCE_IO
), name
);
1575 pci_release_io_regions(struct pci_dev
*pdev
)
1577 return pci_release_selected_regions(pdev
,
1578 pci_select_bars(pdev
, IORESOURCE_IO
));
1582 pci_request_mem_regions(struct pci_dev
*pdev
, const char *name
)
1584 return pci_request_selected_regions(pdev
,
1585 pci_select_bars(pdev
, IORESOURCE_MEM
), name
);
1589 pci_release_mem_regions(struct pci_dev
*pdev
)
1591 return pci_release_selected_regions(pdev
,
1592 pci_select_bars(pdev
, IORESOURCE_MEM
));
1595 #else /* CONFIG_PCI is not enabled */
1597 static inline void pci_set_flags(int flags
) { }
1598 static inline void pci_add_flags(int flags
) { }
1599 static inline void pci_clear_flags(int flags
) { }
1600 static inline int pci_has_flag(int flag
) { return 0; }
1603 * If the system does not have PCI, clearly these return errors. Define
1604 * these as simple inline functions to avoid hair in drivers.
1607 #define _PCI_NOP(o, s, t) \
1608 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1610 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1612 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1613 _PCI_NOP(o, word, u16 x) \
1614 _PCI_NOP(o, dword, u32 x)
1615 _PCI_NOP_ALL(read
, *)
1616 _PCI_NOP_ALL(write
,)
1618 static inline struct pci_dev
*pci_get_device(unsigned int vendor
,
1619 unsigned int device
,
1620 struct pci_dev
*from
)
1623 static inline struct pci_dev
*pci_get_subsys(unsigned int vendor
,
1624 unsigned int device
,
1625 unsigned int ss_vendor
,
1626 unsigned int ss_device
,
1627 struct pci_dev
*from
)
1630 static inline struct pci_dev
*pci_get_class(unsigned int class,
1631 struct pci_dev
*from
)
1634 #define pci_dev_present(ids) (0)
1635 #define no_pci_devices() (1)
1636 #define pci_dev_put(dev) do { } while (0)
1638 static inline void pci_set_master(struct pci_dev
*dev
) { }
1639 static inline int pci_enable_device(struct pci_dev
*dev
) { return -EIO
; }
1640 static inline void pci_disable_device(struct pci_dev
*dev
) { }
1641 static inline int pci_assign_resource(struct pci_dev
*dev
, int i
)
1643 static inline int __pci_register_driver(struct pci_driver
*drv
,
1644 struct module
*owner
)
1646 static inline int pci_register_driver(struct pci_driver
*drv
)
1648 static inline void pci_unregister_driver(struct pci_driver
*drv
) { }
1649 static inline int pci_find_capability(struct pci_dev
*dev
, int cap
)
1651 static inline int pci_find_next_capability(struct pci_dev
*dev
, u8 post
,
1654 static inline int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
1657 /* Power management related routines */
1658 static inline int pci_save_state(struct pci_dev
*dev
) { return 0; }
1659 static inline void pci_restore_state(struct pci_dev
*dev
) { }
1660 static inline int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1662 static inline int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1664 static inline pci_power_t
pci_choose_state(struct pci_dev
*dev
,
1667 static inline int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1671 static inline struct resource
*pci_find_resource(struct pci_dev
*dev
,
1672 struct resource
*res
)
1674 static inline int pci_request_regions(struct pci_dev
*dev
, const char *res_name
)
1676 static inline void pci_release_regions(struct pci_dev
*dev
) { }
1678 static inline unsigned long pci_address_to_pio(phys_addr_t addr
) { return -1; }
1680 static inline void pci_block_cfg_access(struct pci_dev
*dev
) { }
1681 static inline int pci_block_cfg_access_in_atomic(struct pci_dev
*dev
)
1683 static inline void pci_unblock_cfg_access(struct pci_dev
*dev
) { }
1685 static inline struct pci_bus
*pci_find_next_bus(const struct pci_bus
*from
)
1687 static inline struct pci_dev
*pci_get_slot(struct pci_bus
*bus
,
1690 static inline struct pci_dev
*pci_get_bus_and_slot(unsigned int bus
,
1693 static inline struct pci_dev
*pci_get_domain_bus_and_slot(int domain
,
1694 unsigned int bus
, unsigned int devfn
)
1697 static inline int pci_domain_nr(struct pci_bus
*bus
) { return 0; }
1698 static inline struct pci_dev
*pci_dev_get(struct pci_dev
*dev
) { return NULL
; }
1699 static inline int pci_get_new_domain_nr(void) { return -ENOSYS
; }
1701 #define dev_is_pci(d) (false)
1702 #define dev_is_pf(d) (false)
1703 static inline bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
1705 static inline int pci_irqd_intx_xlate(struct irq_domain
*d
,
1706 struct device_node
*node
,
1708 unsigned int intsize
,
1709 unsigned long *out_hwirq
,
1710 unsigned int *out_type
)
1712 #endif /* CONFIG_PCI */
1714 /* Include architecture-dependent settings and functions */
1716 #include <asm/pci.h>
1718 /* These two functions provide almost identical functionality. Depennding
1719 * on the architecture, one will be implemented as a wrapper around the
1720 * other (in drivers/pci/mmap.c).
1722 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1723 * is expected to be an offset within that region.
1725 * pci_mmap_page_range() is the legacy architecture-specific interface,
1726 * which accepts a "user visible" resource address converted by
1727 * pci_resource_to_user(), as used in the legacy mmap() interface in
1730 int pci_mmap_resource_range(struct pci_dev
*dev
, int bar
,
1731 struct vm_area_struct
*vma
,
1732 enum pci_mmap_state mmap_state
, int write_combine
);
1733 int pci_mmap_page_range(struct pci_dev
*pdev
, int bar
,
1734 struct vm_area_struct
*vma
,
1735 enum pci_mmap_state mmap_state
, int write_combine
);
1737 #ifndef arch_can_pci_mmap_wc
1738 #define arch_can_pci_mmap_wc() 0
1741 #ifndef arch_can_pci_mmap_io
1742 #define arch_can_pci_mmap_io() 0
1743 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1745 int pci_iobar_pfn(struct pci_dev
*pdev
, int bar
, struct vm_area_struct
*vma
);
1748 #ifndef pci_root_bus_fwnode
1749 #define pci_root_bus_fwnode(bus) NULL
1752 /* these helpers provide future and backwards compatibility
1753 * for accessing popular PCI BAR info */
1754 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1755 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1756 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1757 #define pci_resource_len(dev,bar) \
1758 ((pci_resource_start((dev), (bar)) == 0 && \
1759 pci_resource_end((dev), (bar)) == \
1760 pci_resource_start((dev), (bar))) ? 0 : \
1762 (pci_resource_end((dev), (bar)) - \
1763 pci_resource_start((dev), (bar)) + 1))
1765 /* Similar to the helpers above, these manipulate per-pci_dev
1766 * driver-specific data. They are really just a wrapper around
1767 * the generic device structure functions of these calls.
1769 static inline void *pci_get_drvdata(struct pci_dev
*pdev
)
1771 return dev_get_drvdata(&pdev
->dev
);
1774 static inline void pci_set_drvdata(struct pci_dev
*pdev
, void *data
)
1776 dev_set_drvdata(&pdev
->dev
, data
);
1779 /* If you want to know what to call your pci_dev, ask this function.
1780 * Again, it's a wrapper around the generic device.
1782 static inline const char *pci_name(const struct pci_dev
*pdev
)
1784 return dev_name(&pdev
->dev
);
1788 /* Some archs don't want to expose struct resource to userland as-is
1789 * in sysfs and /proc
1791 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1792 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1793 const struct resource
*rsrc
,
1794 resource_size_t
*start
, resource_size_t
*end
);
1796 static inline void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1797 const struct resource
*rsrc
, resource_size_t
*start
,
1798 resource_size_t
*end
)
1800 *start
= rsrc
->start
;
1803 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1807 * The world is not perfect and supplies us with broken PCI devices.
1808 * For at least a part of these bugs we need a work-around, so both
1809 * generic (drivers/pci/quirks.c) and per-architecture code can define
1810 * fixup hooks to be called for particular buggy devices.
1814 u16 vendor
; /* You can use PCI_ANY_ID here of course */
1815 u16 device
; /* You can use PCI_ANY_ID here of course */
1816 u32
class; /* You can use PCI_ANY_ID here too */
1817 unsigned int class_shift
; /* should be 0, 8, 16 */
1818 void (*hook
)(struct pci_dev
*dev
);
1821 enum pci_fixup_pass
{
1822 pci_fixup_early
, /* Before probing BARs */
1823 pci_fixup_header
, /* After reading configuration header */
1824 pci_fixup_final
, /* Final phase of device fixups */
1825 pci_fixup_enable
, /* pci_enable_device() time */
1826 pci_fixup_resume
, /* pci_device_resume() */
1827 pci_fixup_suspend
, /* pci_device_suspend() */
1828 pci_fixup_resume_early
, /* pci_device_resume_early() */
1829 pci_fixup_suspend_late
, /* pci_device_suspend_late() */
1832 /* Anonymous variables would be nice... */
1833 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1834 class_shift, hook) \
1835 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1836 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1837 = { vendor, device, class, class_shift, hook };
1839 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1840 class_shift, hook) \
1841 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1842 hook, vendor, device, class, class_shift, hook)
1843 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1844 class_shift, hook) \
1845 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1846 hook, vendor, device, class, class_shift, hook)
1847 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1848 class_shift, hook) \
1849 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1850 hook, vendor, device, class, class_shift, hook)
1851 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1852 class_shift, hook) \
1853 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1854 hook, vendor, device, class, class_shift, hook)
1855 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1856 class_shift, hook) \
1857 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1858 resume##hook, vendor, device, class, \
1860 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1861 class_shift, hook) \
1862 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1863 resume_early##hook, vendor, device, \
1864 class, class_shift, hook)
1865 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1866 class_shift, hook) \
1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1868 suspend##hook, vendor, device, class, \
1870 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1871 class_shift, hook) \
1872 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1873 suspend_late##hook, vendor, device, \
1874 class, class_shift, hook)
1876 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1877 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1878 hook, vendor, device, PCI_ANY_ID, 0, hook)
1879 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1880 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1881 hook, vendor, device, PCI_ANY_ID, 0, hook)
1882 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1883 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1884 hook, vendor, device, PCI_ANY_ID, 0, hook)
1885 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1886 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1887 hook, vendor, device, PCI_ANY_ID, 0, hook)
1888 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1889 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1890 resume##hook, vendor, device, \
1891 PCI_ANY_ID, 0, hook)
1892 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1893 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1894 resume_early##hook, vendor, device, \
1895 PCI_ANY_ID, 0, hook)
1896 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1897 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1898 suspend##hook, vendor, device, \
1899 PCI_ANY_ID, 0, hook)
1900 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1901 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1902 suspend_late##hook, vendor, device, \
1903 PCI_ANY_ID, 0, hook)
1905 #ifdef CONFIG_PCI_QUIRKS
1906 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
);
1907 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
);
1908 int pci_dev_specific_enable_acs(struct pci_dev
*dev
);
1910 static inline void pci_fixup_device(enum pci_fixup_pass pass
,
1911 struct pci_dev
*dev
) { }
1912 static inline int pci_dev_specific_acs_enabled(struct pci_dev
*dev
,
1917 static inline int pci_dev_specific_enable_acs(struct pci_dev
*dev
)
1923 void __iomem
*pcim_iomap(struct pci_dev
*pdev
, int bar
, unsigned long maxlen
);
1924 void pcim_iounmap(struct pci_dev
*pdev
, void __iomem
*addr
);
1925 void __iomem
* const *pcim_iomap_table(struct pci_dev
*pdev
);
1926 int pcim_iomap_regions(struct pci_dev
*pdev
, int mask
, const char *name
);
1927 int pcim_iomap_regions_request_all(struct pci_dev
*pdev
, int mask
,
1929 void pcim_iounmap_regions(struct pci_dev
*pdev
, int mask
);
1931 extern int pci_pci_problems
;
1932 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1933 #define PCIPCI_TRITON 2
1934 #define PCIPCI_NATOMA 4
1935 #define PCIPCI_VIAETBF 8
1936 #define PCIPCI_VSFX 16
1937 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1938 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1940 extern unsigned long pci_cardbus_io_size
;
1941 extern unsigned long pci_cardbus_mem_size
;
1942 extern u8 pci_dfl_cache_line_size
;
1943 extern u8 pci_cache_line_size
;
1945 extern unsigned long pci_hotplug_io_size
;
1946 extern unsigned long pci_hotplug_mem_size
;
1947 extern unsigned long pci_hotplug_bus_size
;
1949 /* Architecture-specific versions may override these (weak) */
1950 void pcibios_disable_device(struct pci_dev
*dev
);
1951 void pcibios_set_master(struct pci_dev
*dev
);
1952 int pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1953 enum pcie_reset_state state
);
1954 int pcibios_add_device(struct pci_dev
*dev
);
1955 void pcibios_release_device(struct pci_dev
*dev
);
1956 void pcibios_penalize_isa_irq(int irq
, int active
);
1957 int pcibios_alloc_irq(struct pci_dev
*dev
);
1958 void pcibios_free_irq(struct pci_dev
*dev
);
1960 #ifdef CONFIG_HIBERNATE_CALLBACKS
1961 extern struct dev_pm_ops pcibios_pm_ops
;
1964 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1965 void __init
pci_mmcfg_early_init(void);
1966 void __init
pci_mmcfg_late_init(void);
1968 static inline void pci_mmcfg_early_init(void) { }
1969 static inline void pci_mmcfg_late_init(void) { }
1972 int pci_ext_cfg_avail(void);
1974 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
);
1975 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
);
1977 #ifdef CONFIG_PCI_IOV
1978 int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
);
1979 int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
);
1981 int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
);
1982 void pci_disable_sriov(struct pci_dev
*dev
);
1983 int pci_iov_add_virtfn(struct pci_dev
*dev
, int id
);
1984 void pci_iov_remove_virtfn(struct pci_dev
*dev
, int id
);
1985 int pci_num_vf(struct pci_dev
*dev
);
1986 int pci_vfs_assigned(struct pci_dev
*dev
);
1987 int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
);
1988 int pci_sriov_get_totalvfs(struct pci_dev
*dev
);
1989 resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
);
1991 static inline int pci_iov_virtfn_bus(struct pci_dev
*dev
, int id
)
1995 static inline int pci_iov_virtfn_devfn(struct pci_dev
*dev
, int id
)
1999 static inline int pci_enable_sriov(struct pci_dev
*dev
, int nr_virtfn
)
2001 static inline int pci_iov_add_virtfn(struct pci_dev
*dev
, int id
)
2005 static inline void pci_iov_remove_virtfn(struct pci_dev
*dev
,
2007 static inline void pci_disable_sriov(struct pci_dev
*dev
) { }
2008 static inline int pci_num_vf(struct pci_dev
*dev
) { return 0; }
2009 static inline int pci_vfs_assigned(struct pci_dev
*dev
)
2011 static inline int pci_sriov_set_totalvfs(struct pci_dev
*dev
, u16 numvfs
)
2013 static inline int pci_sriov_get_totalvfs(struct pci_dev
*dev
)
2015 static inline resource_size_t
pci_iov_resource_size(struct pci_dev
*dev
, int resno
)
2019 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2020 void pci_hp_create_module_link(struct pci_slot
*pci_slot
);
2021 void pci_hp_remove_module_link(struct pci_slot
*pci_slot
);
2025 * pci_pcie_cap - get the saved PCIe capability offset
2028 * PCIe capability offset is calculated at PCI device initialization
2029 * time and saved in the data structure. This function returns saved
2030 * PCIe capability offset. Using this instead of pci_find_capability()
2031 * reduces unnecessary search in the PCI configuration space. If you
2032 * need to calculate PCIe capability offset from raw device for some
2033 * reasons, please use pci_find_capability() instead.
2035 static inline int pci_pcie_cap(struct pci_dev
*dev
)
2037 return dev
->pcie_cap
;
2041 * pci_is_pcie - check if the PCI device is PCI Express capable
2044 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2046 static inline bool pci_is_pcie(struct pci_dev
*dev
)
2048 return pci_pcie_cap(dev
);
2052 * pcie_caps_reg - get the PCIe Capabilities Register
2055 static inline u16
pcie_caps_reg(const struct pci_dev
*dev
)
2057 return dev
->pcie_flags_reg
;
2061 * pci_pcie_type - get the PCIe device/port type
2064 static inline int pci_pcie_type(const struct pci_dev
*dev
)
2066 return (pcie_caps_reg(dev
) & PCI_EXP_FLAGS_TYPE
) >> 4;
2069 static inline struct pci_dev
*pcie_find_root_port(struct pci_dev
*dev
)
2072 if (!pci_is_pcie(dev
))
2074 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2076 if (!dev
->bus
->self
)
2078 dev
= dev
->bus
->self
;
2083 void pci_request_acs(void);
2084 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
);
2085 bool pci_acs_path_enabled(struct pci_dev
*start
,
2086 struct pci_dev
*end
, u16 acs_flags
);
2088 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2089 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2091 /* Large Resource Data Type Tag Item Names */
2092 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2093 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2094 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2096 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2097 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2098 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2100 /* Small Resource Data Type Tag Item Names */
2101 #define PCI_VPD_STIN_END 0x0f /* End */
2103 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2105 #define PCI_VPD_SRDT_TIN_MASK 0x78
2106 #define PCI_VPD_SRDT_LEN_MASK 0x07
2107 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2109 #define PCI_VPD_LRDT_TAG_SIZE 3
2110 #define PCI_VPD_SRDT_TAG_SIZE 1
2112 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2114 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2115 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2116 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2117 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2120 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2121 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2123 * Returns the extracted Large Resource Data Type length.
2125 static inline u16
pci_vpd_lrdt_size(const u8
*lrdt
)
2127 return (u16
)lrdt
[1] + ((u16
)lrdt
[2] << 8);
2131 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2132 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2134 * Returns the extracted Large Resource Data Type Tag item.
2136 static inline u16
pci_vpd_lrdt_tag(const u8
*lrdt
)
2138 return (u16
)(lrdt
[0] & PCI_VPD_LRDT_TIN_MASK
);
2142 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2143 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2145 * Returns the extracted Small Resource Data Type length.
2147 static inline u8
pci_vpd_srdt_size(const u8
*srdt
)
2149 return (*srdt
) & PCI_VPD_SRDT_LEN_MASK
;
2153 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2154 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2156 * Returns the extracted Small Resource Data Type Tag Item.
2158 static inline u8
pci_vpd_srdt_tag(const u8
*srdt
)
2160 return ((*srdt
) & PCI_VPD_SRDT_TIN_MASK
) >> 3;
2164 * pci_vpd_info_field_size - Extracts the information field length
2165 * @lrdt: Pointer to the beginning of an information field header
2167 * Returns the extracted information field length.
2169 static inline u8
pci_vpd_info_field_size(const u8
*info_field
)
2171 return info_field
[2];
2175 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2176 * @buf: Pointer to buffered vpd data
2177 * @off: The offset into the buffer at which to begin the search
2178 * @len: The length of the vpd buffer
2179 * @rdt: The Resource Data Type to search for
2181 * Returns the index where the Resource Data Type was found or
2182 * -ENOENT otherwise.
2184 int pci_vpd_find_tag(const u8
*buf
, unsigned int off
, unsigned int len
, u8 rdt
);
2187 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2188 * @buf: Pointer to buffered vpd data
2189 * @off: The offset into the buffer at which to begin the search
2190 * @len: The length of the buffer area, relative to off, in which to search
2191 * @kw: The keyword to search for
2193 * Returns the index where the information field keyword was found or
2194 * -ENOENT otherwise.
2196 int pci_vpd_find_info_keyword(const u8
*buf
, unsigned int off
,
2197 unsigned int len
, const char *kw
);
2199 /* PCI <-> OF binding helpers */
2203 void pci_set_of_node(struct pci_dev
*dev
);
2204 void pci_release_of_node(struct pci_dev
*dev
);
2205 void pci_set_bus_of_node(struct pci_bus
*bus
);
2206 void pci_release_bus_of_node(struct pci_bus
*bus
);
2207 struct irq_domain
*pci_host_bridge_of_msi_domain(struct pci_bus
*bus
);
2209 /* Arch may override this (weak) */
2210 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
);
2212 static inline struct device_node
*
2213 pci_device_to_OF_node(const struct pci_dev
*pdev
)
2215 return pdev
? pdev
->dev
.of_node
: NULL
;
2218 static inline struct device_node
*pci_bus_to_OF_node(struct pci_bus
*bus
)
2220 return bus
? bus
->dev
.of_node
: NULL
;
2223 #else /* CONFIG_OF */
2224 static inline void pci_set_of_node(struct pci_dev
*dev
) { }
2225 static inline void pci_release_of_node(struct pci_dev
*dev
) { }
2226 static inline void pci_set_bus_of_node(struct pci_bus
*bus
) { }
2227 static inline void pci_release_bus_of_node(struct pci_bus
*bus
) { }
2228 static inline struct device_node
*
2229 pci_device_to_OF_node(const struct pci_dev
*pdev
) { return NULL
; }
2230 static inline struct irq_domain
*
2231 pci_host_bridge_of_msi_domain(struct pci_bus
*bus
) { return NULL
; }
2232 #endif /* CONFIG_OF */
2235 struct irq_domain
*pci_host_bridge_acpi_msi_domain(struct pci_bus
*bus
);
2238 pci_msi_register_fwnode_provider(struct fwnode_handle
*(*fn
)(struct device
*));
2240 static inline struct irq_domain
*
2241 pci_host_bridge_acpi_msi_domain(struct pci_bus
*bus
) { return NULL
; }
2245 static inline struct eeh_dev
*pci_dev_to_eeh_dev(struct pci_dev
*pdev
)
2247 return pdev
->dev
.archdata
.edev
;
2251 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn
);
2252 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
);
2253 int pci_for_each_dma_alias(struct pci_dev
*pdev
,
2254 int (*fn
)(struct pci_dev
*pdev
,
2255 u16 alias
, void *data
), void *data
);
2257 /* helper functions for operation of device flag */
2258 static inline void pci_set_dev_assigned(struct pci_dev
*pdev
)
2260 pdev
->dev_flags
|= PCI_DEV_FLAGS_ASSIGNED
;
2262 static inline void pci_clear_dev_assigned(struct pci_dev
*pdev
)
2264 pdev
->dev_flags
&= ~PCI_DEV_FLAGS_ASSIGNED
;
2266 static inline bool pci_is_dev_assigned(struct pci_dev
*pdev
)
2268 return (pdev
->dev_flags
& PCI_DEV_FLAGS_ASSIGNED
) == PCI_DEV_FLAGS_ASSIGNED
;
2272 * pci_ari_enabled - query ARI forwarding status
2275 * Returns true if ARI forwarding is enabled.
2277 static inline bool pci_ari_enabled(struct pci_bus
*bus
)
2279 return bus
->self
&& bus
->self
->ari_enabled
;
2283 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2284 * @pdev: PCI device to check
2286 * Walk upwards from @pdev and check for each encountered bridge if it's part
2287 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2288 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2290 static inline bool pci_is_thunderbolt_attached(struct pci_dev
*pdev
)
2292 struct pci_dev
*parent
= pdev
;
2294 if (pdev
->is_thunderbolt
)
2297 while ((parent
= pci_upstream_bridge(parent
)))
2298 if (parent
->is_thunderbolt
)
2304 /* provide the legacy pci_dma_* API */
2305 #include <linux/pci-dma-compat.h>
2307 #endif /* LINUX_PCI_H */