include/linux/qcom-geni-se.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef _LINUX_QCOM_GENI_SE
   7 #define _LINUX_QCOM_GENI_SE
   8
   9 #include <linux/interconnect.h>
  10
  11 /* Transfer mode supported by GENI Serial Engines */
  12 enum geni_se_xfer_mode {
  13         GENI_SE_INVALID,
  14         GENI_SE_FIFO,
  15         GENI_SE_DMA,
  16 };
  17
  18 /* Protocols supported by GENI Serial Engines */
  19 enum geni_se_protocol_type {
  20         GENI_SE_NONE,
  21         GENI_SE_SPI,
  22         GENI_SE_UART,
  23         GENI_SE_I2C,
  24         GENI_SE_I3C,
  25 };
  26
  27 struct geni_wrapper;
  28 struct clk;
  29
  30 enum geni_icc_path_index {
  31         GENI_TO_CORE,
  32         CPU_TO_GENI,
  33         GENI_TO_DDR
  34 };
  35
  36 struct geni_icc_path {
  37         struct icc_path *path;
  38         unsigned int avg_bw;
  39 };
  40
  41 /**
  42  * struct geni_se - GENI Serial Engine
  43  * @base:               Base Address of the Serial Engine's register block
  44  * @dev:                Pointer to the Serial Engine device
  45  * @wrapper:            Pointer to the parent QUP Wrapper core
  46  * @clk:                Handle to the core serial engine clock
  47  * @num_clk_levels:     Number of valid clock levels in clk_perf_tbl
  48  * @clk_perf_tbl:       Table of clock frequency input to serial engine clock
  49  * @icc_paths:          Array of ICC paths for SE
  50  * @opp_table:          Pointer to the OPP table
  51  */
  52 struct geni_se {
  53         void __iomem *base;
  54         struct device *dev;
  55         struct geni_wrapper *wrapper;
  56         struct clk *clk;
  57         unsigned int num_clk_levels;
  58         unsigned long *clk_perf_tbl;
  59         struct geni_icc_path icc_paths[3];
  60         struct opp_table *opp_table;
  61 };
  62
  63 /* Common SE registers */
  64 #define GENI_FORCE_DEFAULT_REG          0x20
  65 #define SE_GENI_STATUS                  0x40
  66 #define GENI_SER_M_CLK_CFG              0x48
  67 #define GENI_SER_S_CLK_CFG              0x4c
  68 #define GENI_FW_REVISION_RO             0x68
  69 #define SE_GENI_CLK_SEL                 0x7c
  70 #define SE_GENI_DMA_MODE_EN             0x258
  71 #define SE_GENI_M_CMD0                  0x600
  72 #define SE_GENI_M_CMD_CTRL_REG          0x604
  73 #define SE_GENI_M_IRQ_STATUS            0x610
  74 #define SE_GENI_M_IRQ_EN                0x614
  75 #define SE_GENI_M_IRQ_CLEAR             0x618
  76 #define SE_GENI_S_CMD0                  0x630
  77 #define SE_GENI_S_CMD_CTRL_REG          0x634
  78 #define SE_GENI_S_IRQ_STATUS            0x640
  79 #define SE_GENI_S_IRQ_EN                0x644
  80 #define SE_GENI_S_IRQ_CLEAR             0x648
  81 #define SE_GENI_TX_FIFOn                0x700
  82 #define SE_GENI_RX_FIFOn                0x780
  83 #define SE_GENI_TX_FIFO_STATUS          0x800
  84 #define SE_GENI_RX_FIFO_STATUS          0x804
  85 #define SE_GENI_TX_WATERMARK_REG        0x80c
  86 #define SE_GENI_RX_WATERMARK_REG        0x810
  87 #define SE_GENI_RX_RFR_WATERMARK_REG    0x814
  88 #define SE_GENI_IOS                     0x908
  89 #define SE_DMA_TX_IRQ_STAT              0xc40
  90 #define SE_DMA_TX_IRQ_CLR               0xc44
  91 #define SE_DMA_TX_FSM_RST               0xc58
  92 #define SE_DMA_RX_IRQ_STAT              0xd40
  93 #define SE_DMA_RX_IRQ_CLR               0xd44
  94 #define SE_DMA_RX_FSM_RST               0xd58
  95 #define SE_HW_PARAM_0                   0xe24
  96 #define SE_HW_PARAM_1                   0xe28
  97
  98 /* GENI_FORCE_DEFAULT_REG fields */
  99 #define FORCE_DEFAULT   BIT(0)
 100
 101 /* GENI_STATUS fields */
 102 #define M_GENI_CMD_ACTIVE               BIT(0)
 103 #define S_GENI_CMD_ACTIVE               BIT(12)
 104
 105 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
 106 #define SER_CLK_EN                      BIT(0)
 107 #define CLK_DIV_MSK                     GENMASK(15, 4)
 108 #define CLK_DIV_SHFT                    4
 109
 110 /* GENI_FW_REVISION_RO fields */
 111 #define FW_REV_PROTOCOL_MSK             GENMASK(15, 8)
 112 #define FW_REV_PROTOCOL_SHFT            8
 113
 114 /* GENI_CLK_SEL fields */
 115 #define CLK_SEL_MSK                     GENMASK(2, 0)
 116
 117 /* SE_GENI_DMA_MODE_EN */
 118 #define GENI_DMA_MODE_EN                BIT(0)
 119
 120 /* GENI_M_CMD0 fields */
 121 #define M_OPCODE_MSK                    GENMASK(31, 27)
 122 #define M_OPCODE_SHFT                   27
 123 #define M_PARAMS_MSK                    GENMASK(26, 0)
 124
 125 /* GENI_M_CMD_CTRL_REG */
 126 #define M_GENI_CMD_CANCEL               BIT(2)
 127 #define M_GENI_CMD_ABORT                BIT(1)
 128 #define M_GENI_DISABLE                  BIT(0)
 129
 130 /* GENI_S_CMD0 fields */
 131 #define S_OPCODE_MSK                    GENMASK(31, 27)
 132 #define S_OPCODE_SHFT                   27
 133 #define S_PARAMS_MSK                    GENMASK(26, 0)
 134
 135 /* GENI_S_CMD_CTRL_REG */
 136 #define S_GENI_CMD_CANCEL               BIT(2)
 137 #define S_GENI_CMD_ABORT                BIT(1)
 138 #define S_GENI_DISABLE                  BIT(0)
 139
 140 /* GENI_M_IRQ_EN fields */
 141 #define M_CMD_DONE_EN                   BIT(0)
 142 #define M_CMD_OVERRUN_EN                BIT(1)
 143 #define M_ILLEGAL_CMD_EN                BIT(2)
 144 #define M_CMD_FAILURE_EN                BIT(3)
 145 #define M_CMD_CANCEL_EN                 BIT(4)
 146 #define M_CMD_ABORT_EN                  BIT(5)
 147 #define M_TIMESTAMP_EN                  BIT(6)
 148 #define M_RX_IRQ_EN                     BIT(7)
 149 #define M_GP_SYNC_IRQ_0_EN              BIT(8)
 150 #define M_GP_IRQ_0_EN                   BIT(9)
 151 #define M_GP_IRQ_1_EN                   BIT(10)
 152 #define M_GP_IRQ_2_EN                   BIT(11)
 153 #define M_GP_IRQ_3_EN                   BIT(12)
 154 #define M_GP_IRQ_4_EN                   BIT(13)
 155 #define M_GP_IRQ_5_EN                   BIT(14)
 156 #define M_IO_DATA_DEASSERT_EN           BIT(22)
 157 #define M_IO_DATA_ASSERT_EN             BIT(23)
 158 #define M_RX_FIFO_RD_ERR_EN             BIT(24)
 159 #define M_RX_FIFO_WR_ERR_EN             BIT(25)
 160 #define M_RX_FIFO_WATERMARK_EN          BIT(26)
 161 #define M_RX_FIFO_LAST_EN               BIT(27)
 162 #define M_TX_FIFO_RD_ERR_EN             BIT(28)
 163 #define M_TX_FIFO_WR_ERR_EN             BIT(29)
 164 #define M_TX_FIFO_WATERMARK_EN          BIT(30)
 165 #define M_SEC_IRQ_EN                    BIT(31)
 166 #define M_COMMON_GENI_M_IRQ_EN  (GENMASK(6, 1) | \
 167                                 M_IO_DATA_DEASSERT_EN | \
 168                                 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
 169                                 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
 170                                 M_TX_FIFO_WR_ERR_EN)
 171
 172 /* GENI_S_IRQ_EN fields */
 173 #define S_CMD_DONE_EN                   BIT(0)
 174 #define S_CMD_OVERRUN_EN                BIT(1)
 175 #define S_ILLEGAL_CMD_EN                BIT(2)
 176 #define S_CMD_FAILURE_EN                BIT(3)
 177 #define S_CMD_CANCEL_EN                 BIT(4)
 178 #define S_CMD_ABORT_EN                  BIT(5)
 179 #define S_GP_SYNC_IRQ_0_EN              BIT(8)
 180 #define S_GP_IRQ_0_EN                   BIT(9)
 181 #define S_GP_IRQ_1_EN                   BIT(10)
 182 #define S_GP_IRQ_2_EN                   BIT(11)
 183 #define S_GP_IRQ_3_EN                   BIT(12)
 184 #define S_GP_IRQ_4_EN                   BIT(13)
 185 #define S_GP_IRQ_5_EN                   BIT(14)
 186 #define S_IO_DATA_DEASSERT_EN           BIT(22)
 187 #define S_IO_DATA_ASSERT_EN             BIT(23)
 188 #define S_RX_FIFO_RD_ERR_EN             BIT(24)
 189 #define S_RX_FIFO_WR_ERR_EN             BIT(25)
 190 #define S_RX_FIFO_WATERMARK_EN          BIT(26)
 191 #define S_RX_FIFO_LAST_EN               BIT(27)
 192 #define S_COMMON_GENI_S_IRQ_EN  (GENMASK(5, 1) | GENMASK(13, 9) | \
 193                                  S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
 194
 195 /*  GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
 196 #define WATERMARK_MSK                   GENMASK(5, 0)
 197
 198 /* GENI_TX_FIFO_STATUS fields */
 199 #define TX_FIFO_WC                      GENMASK(27, 0)
 200
 201 /*  GENI_RX_FIFO_STATUS fields */
 202 #define RX_LAST                         BIT(31)
 203 #define RX_LAST_BYTE_VALID_MSK          GENMASK(30, 28)
 204 #define RX_LAST_BYTE_VALID_SHFT         28
 205 #define RX_FIFO_WC_MSK                  GENMASK(24, 0)
 206
 207 /* SE_GENI_IOS fields */
 208 #define IO2_DATA_IN                     BIT(1)
 209 #define RX_DATA_IN                      BIT(0)
 210
 211 /* SE_DMA_TX_IRQ_STAT Register fields */
 212 #define TX_DMA_DONE                     BIT(0)
 213 #define TX_EOT                          BIT(1)
 214 #define TX_SBE                          BIT(2)
 215 #define TX_RESET_DONE                   BIT(3)
 216
 217 /* SE_DMA_RX_IRQ_STAT Register fields */
 218 #define RX_DMA_DONE                     BIT(0)
 219 #define RX_EOT                          BIT(1)
 220 #define RX_SBE                          BIT(2)
 221 #define RX_RESET_DONE                   BIT(3)
 222 #define RX_FLUSH_DONE                   BIT(4)
 223 #define RX_GENI_GP_IRQ                  GENMASK(10, 5)
 224 #define RX_GENI_CANCEL_IRQ              BIT(11)
 225 #define RX_GENI_GP_IRQ_EXT              GENMASK(13, 12)
 226
 227 /* SE_HW_PARAM_0 fields */
 228 #define TX_FIFO_WIDTH_MSK               GENMASK(29, 24)
 229 #define TX_FIFO_WIDTH_SHFT              24
 230 #define TX_FIFO_DEPTH_MSK               GENMASK(21, 16)
 231 #define TX_FIFO_DEPTH_SHFT              16
 232
 233 /* SE_HW_PARAM_1 fields */
 234 #define RX_FIFO_WIDTH_MSK               GENMASK(29, 24)
 235 #define RX_FIFO_WIDTH_SHFT              24
 236 #define RX_FIFO_DEPTH_MSK               GENMASK(21, 16)
 237 #define RX_FIFO_DEPTH_SHFT              16
 238
 239 #define HW_VER_MAJOR_MASK               GENMASK(31, 28)
 240 #define HW_VER_MAJOR_SHFT               28
 241 #define HW_VER_MINOR_MASK               GENMASK(27, 16)
 242 #define HW_VER_MINOR_SHFT               16
 243 #define HW_VER_STEP_MASK                GENMASK(15, 0)
 244
 245 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
 246 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
 247 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
 248
 249 /* QUP SE VERSION value for major number 2 and minor number 5 */
 250 #define QUP_SE_VERSION_2_5                  0x20050000
 251
 252 /*
 253  * Define bandwidth thresholds that cause the underlying Core 2X interconnect
 254  * clock to run at the named frequency. These baseline values are recommended
 255  * by the hardware team, and are not dynamically scaled with GENI bandwidth
 256  * beyond basic on/off.
 257  */
 258 #define CORE_2X_19_2_MHZ                960
 259 #define CORE_2X_50_MHZ                  2500
 260 #define CORE_2X_100_MHZ                 5000
 261 #define CORE_2X_150_MHZ                 7500
 262 #define CORE_2X_200_MHZ                 10000
 263 #define CORE_2X_236_MHZ                 16383
 264
 265 #define GENI_DEFAULT_BW                 Bps_to_icc(1000)
 266
 267 #if IS_ENABLED(CONFIG_QCOM_GENI_SE)
 268
 269 u32 geni_se_get_qup_hw_version(struct geni_se *se);
 270
 271 /**
 272  * geni_se_read_proto() - Read the protocol configured for a serial engine
 273  * @se:         Pointer to the concerned serial engine.
 274  *
 275  * Return: Protocol value as configured in the serial engine.
 276  */
 277 static inline u32 geni_se_read_proto(struct geni_se *se)
 278 {
 279         u32 val;
 280
 281         val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
 282
 283         return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
 284 }
 285
 286 /**
 287  * geni_se_setup_m_cmd() - Setup the primary sequencer
 288  * @se:         Pointer to the concerned serial engine.
 289  * @cmd:        Command/Operation to setup in the primary sequencer.
 290  * @params:     Parameter for the sequencer command.
 291  *
 292  * This function is used to configure the primary sequencer with the
 293  * command and its associated parameters.
 294  */
 295 static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
 296 {
 297         u32 m_cmd;
 298
 299         m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
 300         writel(m_cmd, se->base + SE_GENI_M_CMD0);
 301 }
 302
 303 /**
 304  * geni_se_setup_s_cmd() - Setup the secondary sequencer
 305  * @se:         Pointer to the concerned serial engine.
 306  * @cmd:        Command/Operation to setup in the secondary sequencer.
 307  * @params:     Parameter for the sequencer command.
 308  *
 309  * This function is used to configure the secondary sequencer with the
 310  * command and its associated parameters.
 311  */
 312 static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
 313 {
 314         u32 s_cmd;
 315
 316         s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
 317         s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
 318         s_cmd |= (cmd << S_OPCODE_SHFT);
 319         s_cmd |= (params & S_PARAMS_MSK);
 320         writel(s_cmd, se->base + SE_GENI_S_CMD0);
 321 }
 322
 323 /**
 324  * geni_se_cancel_m_cmd() - Cancel the command configured in the primary
 325  *                          sequencer
 326  * @se: Pointer to the concerned serial engine.
 327  *
 328  * This function is used to cancel the currently configured command in the
 329  * primary sequencer.
 330  */
 331 static inline void geni_se_cancel_m_cmd(struct geni_se *se)
 332 {
 333         writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
 334 }
 335
 336 /**
 337  * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
 338  *                          sequencer
 339  * @se: Pointer to the concerned serial engine.
 340  *
 341  * This function is used to cancel the currently configured command in the
 342  * secondary sequencer.
 343  */
 344 static inline void geni_se_cancel_s_cmd(struct geni_se *se)
 345 {
 346         writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
 347 }
 348
 349 /**
 350  * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
 351  * @se: Pointer to the concerned serial engine.
 352  *
 353  * This function is used to force abort the currently configured command in the
 354  * primary sequencer.
 355  */
 356 static inline void geni_se_abort_m_cmd(struct geni_se *se)
 357 {
 358         writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
 359 }
 360
 361 /**
 362  * geni_se_abort_s_cmd() - Abort the command configured in the secondary
 363  *                         sequencer
 364  * @se: Pointer to the concerned serial engine.
 365  *
 366  * This function is used to force abort the currently configured command in the
 367  * secondary sequencer.
 368  */
 369 static inline void geni_se_abort_s_cmd(struct geni_se *se)
 370 {
 371         writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
 372 }
 373
 374 /**
 375  * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
 376  * @se: Pointer to the concerned serial engine.
 377  *
 378  * This function is used to get the depth i.e. number of elements in the
 379  * TX fifo of the serial engine.
 380  *
 381  * Return: TX fifo depth in units of FIFO words.
 382  */
 383 static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
 384 {
 385         u32 val;
 386
 387         val = readl_relaxed(se->base + SE_HW_PARAM_0);
 388
 389         return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
 390 }
 391
 392 /**
 393  * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
 394  * @se: Pointer to the concerned serial engine.
 395  *
 396  * This function is used to get the width i.e. word size per element in the
 397  * TX fifo of the serial engine.
 398  *
 399  * Return: TX fifo width in bits
 400  */
 401 static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
 402 {
 403         u32 val;
 404
 405         val = readl_relaxed(se->base + SE_HW_PARAM_0);
 406
 407         return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
 408 }
 409
 410 /**
 411  * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
 412  * @se: Pointer to the concerned serial engine.
 413  *
 414  * This function is used to get the depth i.e. number of elements in the
 415  * RX fifo of the serial engine.
 416  *
 417  * Return: RX fifo depth in units of FIFO words
 418  */
 419 static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
 420 {
 421         u32 val;
 422
 423         val = readl_relaxed(se->base + SE_HW_PARAM_1);
 424
 425         return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
 426 }
 427
 428 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
 429
 430 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
 431
 432 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
 433                             bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
 434
 435 int geni_se_resources_off(struct geni_se *se);
 436
 437 int geni_se_resources_on(struct geni_se *se);
 438
 439 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);
 440
 441 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
 442                            unsigned int *index, unsigned long *res_freq,
 443                            bool exact);
 444
 445 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
 446                         dma_addr_t *iova);
 447
 448 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
 449                         dma_addr_t *iova);
 450
 451 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
 452
 453 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
 454
 455 int geni_icc_get(struct geni_se *se, const char *icc_ddr);
 456
 457 int geni_icc_set_bw(struct geni_se *se);
 458 void geni_icc_set_tag(struct geni_se *se, u32 tag);
 459
 460 int geni_icc_enable(struct geni_se *se);
 461
 462 int geni_icc_disable(struct geni_se *se);
 463
 464 void geni_remove_earlycon_icc_vote(void);
 465 #endif
 466 #endif