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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.
9 #include <linux/types.h>
10 #include <linux/cpumask.h>
12 #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
13 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
14 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
15 #define QCOM_SCM_HDCP_MAX_REQ_CNT 5
17 struct qcom_scm_hdcp_req
{
22 struct qcom_scm_vmperm
{
27 #define QCOM_SCM_VMID_HLOS 0x3
28 #define QCOM_SCM_VMID_MSS_MSA 0xF
29 #define QCOM_SCM_VMID_WLAN 0x18
30 #define QCOM_SCM_VMID_WLAN_CE 0x19
31 #define QCOM_SCM_PERM_READ 0x4
32 #define QCOM_SCM_PERM_WRITE 0x2
33 #define QCOM_SCM_PERM_EXEC 0x1
34 #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
35 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
37 #if IS_ENABLED(CONFIG_QCOM_SCM)
38 extern int qcom_scm_set_cold_boot_addr(void *entry
, const cpumask_t
*cpus
);
39 extern int qcom_scm_set_warm_boot_addr(void *entry
, const cpumask_t
*cpus
);
40 extern bool qcom_scm_is_available(void);
41 extern bool qcom_scm_hdcp_available(void);
42 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req
*req
, u32 req_cnt
,
44 extern bool qcom_scm_pas_supported(u32 peripheral
);
45 extern int qcom_scm_pas_init_image(u32 peripheral
, const void *metadata
,
47 extern int qcom_scm_pas_mem_setup(u32 peripheral
, phys_addr_t addr
,
49 extern int qcom_scm_pas_auth_and_reset(u32 peripheral
);
50 extern int qcom_scm_pas_shutdown(u32 peripheral
);
51 extern int qcom_scm_assign_mem(phys_addr_t mem_addr
, size_t mem_sz
,
52 unsigned int *src
, struct qcom_scm_vmperm
*newvm
,
54 extern void qcom_scm_cpu_power_down(u32 flags
);
55 extern u32
qcom_scm_get_version(void);
56 extern int qcom_scm_set_remote_state(u32 state
, u32 id
);
57 extern int qcom_scm_restore_sec_cfg(u32 device_id
, u32 spare
);
58 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare
, size_t *size
);
59 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr
, u32 size
, u32 spare
);
60 extern int qcom_scm_io_readl(phys_addr_t addr
, unsigned int *val
);
61 extern int qcom_scm_io_writel(phys_addr_t addr
, unsigned int val
);
64 #include <linux/errno.h>
67 int qcom_scm_set_cold_boot_addr(void *entry
, const cpumask_t
*cpus
)
72 int qcom_scm_set_warm_boot_addr(void *entry
, const cpumask_t
*cpus
)
76 static inline bool qcom_scm_is_available(void) { return false; }
77 static inline bool qcom_scm_hdcp_available(void) { return false; }
78 static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req
*req
, u32 req_cnt
,
79 u32
*resp
) { return -ENODEV
; }
80 static inline bool qcom_scm_pas_supported(u32 peripheral
) { return false; }
81 static inline int qcom_scm_pas_init_image(u32 peripheral
, const void *metadata
,
82 size_t size
) { return -ENODEV
; }
83 static inline int qcom_scm_pas_mem_setup(u32 peripheral
, phys_addr_t addr
,
84 phys_addr_t size
) { return -ENODEV
; }
86 qcom_scm_pas_auth_and_reset(u32 peripheral
) { return -ENODEV
; }
87 static inline int qcom_scm_pas_shutdown(u32 peripheral
) { return -ENODEV
; }
88 static inline int qcom_scm_assign_mem(phys_addr_t mem_addr
, size_t mem_sz
,
90 struct qcom_scm_vmperm
*newvm
,
91 int dest_cnt
) { return -ENODEV
; }
92 static inline void qcom_scm_cpu_power_down(u32 flags
) {}
93 static inline u32
qcom_scm_get_version(void) { return 0; }
95 qcom_scm_set_remote_state(u32 state
,u32 id
) { return -ENODEV
; }
96 static inline int qcom_scm_restore_sec_cfg(u32 device_id
, u32 spare
) { return -ENODEV
; }
97 static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare
, size_t *size
) { return -ENODEV
; }
98 static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr
, u32 size
, u32 spare
) { return -ENODEV
; }
99 static inline int qcom_scm_io_readl(phys_addr_t addr
, unsigned int *val
) { return -ENODEV
; }
100 static inline int qcom_scm_io_writel(phys_addr_t addr
, unsigned int val
) { return -ENODEV
; }