include/linux/shdma-base.h

   1 /*
   2  * Dmaengine driver base library for DMA controllers, found on SH-based SoCs
   3  *
   4  * extracted from shdma.c and headers
   5  *
   6  * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   8  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   9  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef SHDMA_BASE_H
  17 #define SHDMA_BASE_H
  18
  19 #include <linux/dmaengine.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/types.h>
  23
  24 /**
  25  * shdma_pm_state - DMA channel PM state
  26  * SHDMA_PM_ESTABLISHED:        either idle or during data transfer
  27  * SHDMA_PM_BUSY:               during the transfer preparation, when we have to
  28  *                              drop the lock temporarily
  29  * SHDMA_PM_PENDING:    transfers pending
  30  */
  31 enum shdma_pm_state {
  32         SHDMA_PM_ESTABLISHED,
  33         SHDMA_PM_BUSY,
  34         SHDMA_PM_PENDING,
  35 };
  36
  37 struct device;
  38
  39 /*
  40  * Drivers, using this library are expected to embed struct shdma_dev,
  41  * struct shdma_chan, struct shdma_desc, and struct shdma_slave
  42  * in their respective device, channel, descriptor and slave objects.
  43  */
  44
  45 struct shdma_slave {
  46         int slave_id;
  47 };
  48
  49 struct shdma_desc {
  50         struct list_head node;
  51         struct dma_async_tx_descriptor async_tx;
  52         enum dma_transfer_direction direction;
  53         size_t partial;
  54         dma_cookie_t cookie;
  55         int chunks;
  56         int mark;
  57 };
  58
  59 struct shdma_chan {
  60         spinlock_t chan_lock;           /* Channel operation lock */
  61         struct list_head ld_queue;      /* Link descriptors queue */
  62         struct list_head ld_free;       /* Free link descriptors */
  63         struct dma_chan dma_chan;       /* DMA channel */
  64         struct device *dev;             /* Channel device */
  65         void *desc;                     /* buffer for descriptor array */
  66         int desc_num;                   /* desc count */
  67         size_t max_xfer_len;            /* max transfer length */
  68         int id;                         /* Raw id of this channel */
  69         int irq;                        /* Channel IRQ */
  70         int slave_id;                   /* Client ID for slave DMA */
  71         enum shdma_pm_state pm_state;
  72 };
  73
  74 /**
  75  * struct shdma_ops - simple DMA driver operations
  76  * desc_completed:      return true, if this is the descriptor, that just has
  77  *                      completed (atomic)
  78  * halt_channel:        stop DMA channel operation (atomic)
  79  * channel_busy:        return true, if the channel is busy (atomic)
  80  * slave_addr:          return slave DMA address
  81  * desc_setup:          set up the hardware specific descriptor portion (atomic)
  82  * set_slave:           bind channel to a slave
  83  * setup_xfer:          configure channel hardware for operation (atomic)
  84  * start_xfer:          start the DMA transfer (atomic)
  85  * embedded_desc:       return Nth struct shdma_desc pointer from the
  86  *                      descriptor array
  87  * chan_irq:            process channel IRQ, return true if a transfer has
  88  *                      completed (atomic)
  89  */
  90 struct shdma_ops {
  91         bool (*desc_completed)(struct shdma_chan *, struct shdma_desc *);
  92         void (*halt_channel)(struct shdma_chan *);
  93         bool (*channel_busy)(struct shdma_chan *);
  94         dma_addr_t (*slave_addr)(struct shdma_chan *);
  95         int (*desc_setup)(struct shdma_chan *, struct shdma_desc *,
  96                           dma_addr_t, dma_addr_t, size_t *);
  97         int (*set_slave)(struct shdma_chan *, int, bool);
  98         void (*setup_xfer)(struct shdma_chan *, int);
  99         void (*start_xfer)(struct shdma_chan *, struct shdma_desc *);
 100         struct shdma_desc *(*embedded_desc)(void *, int);
 101         bool (*chan_irq)(struct shdma_chan *, int);
 102         size_t (*get_partial)(struct shdma_chan *, struct shdma_desc *);
 103 };
 104
 105 struct shdma_dev {
 106         struct dma_device dma_dev;
 107         struct shdma_chan **schan;
 108         const struct shdma_ops *ops;
 109         size_t desc_size;
 110 };
 111
 112 #define shdma_for_each_chan(c, d, i) for (i = 0, c = (d)->schan[0]; \
 113                                 i < (d)->dma_dev.chancnt; c = (d)->schan[++i])
 114
 115 int shdma_request_irq(struct shdma_chan *, int,
 116                            unsigned long, const char *);
 117 void shdma_free_irq(struct shdma_chan *);
 118 bool shdma_reset(struct shdma_dev *sdev);
 119 void shdma_chan_probe(struct shdma_dev *sdev,
 120                            struct shdma_chan *schan, int id);
 121 void shdma_chan_remove(struct shdma_chan *schan);
 122 int shdma_init(struct device *dev, struct shdma_dev *sdev,
 123                     int chan_num);
 124 void shdma_cleanup(struct shdma_dev *sdev);
 125
 126 #endif