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git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - include/linux/soundwire/sdw_registers.h
1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
4 #ifndef __SDW_REGISTERS_H
5 #define __SDW_REGISTERS_H
8 * typically we define register and shifts but if one observes carefully,
9 * the shift can be generated from MASKS using few bit primitaives like ffs
10 * etc, so we use that and avoid defining shifts
12 #define SDW_REG_SHIFT(n) (ffs(n) - 1)
15 * SDW registers as defined by MIPI 1.1 Spec
17 #define SDW_REGADDR GENMASK(14, 0)
18 #define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15)
19 #define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23)
21 #define SDW_REG_NO_PAGE 0x00008000
22 #define SDW_REG_OPTIONAL_PAGE 0x00010000
23 #define SDW_REG_MAX 0x80000000
25 #define SDW_DPN_SIZE 0x100
26 #define SDW_BANK1_OFFSET 0x10
29 * DP0 Interrupt register & bits
31 * Spec treats Status (RO) and Clear (WC) as separate but they are same
32 * address, so treat as same register with WC.
35 /* both INT and STATUS register are same */
36 #define SDW_DP0_INT 0x0
37 #define SDW_DP0_INTMASK 0x1
38 #define SDW_DP0_PORTCTRL 0x2
39 #define SDW_DP0_BLOCKCTRL1 0x3
40 #define SDW_DP0_PREPARESTATUS 0x4
41 #define SDW_DP0_PREPARECTRL 0x5
43 #define SDW_DP0_INT_TEST_FAIL BIT(0)
44 #define SDW_DP0_INT_PORT_READY BIT(1)
45 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
46 #define SDW_DP0_INT_IMPDEF1 BIT(5)
47 #define SDW_DP0_INT_IMPDEF2 BIT(6)
48 #define SDW_DP0_INT_IMPDEF3 BIT(7)
50 #define SDW_DP0_PORTCTRL_DATAMODE GENMASK(3, 2)
51 #define SDW_DP0_PORTCTRL_NXTINVBANK BIT(4)
52 #define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6)
54 #define SDW_DP0_CHANNELEN 0x20
55 #define SDW_DP0_SAMPLECTRL1 0x22
56 #define SDW_DP0_SAMPLECTRL2 0x23
57 #define SDW_DP0_OFFSETCTRL1 0x24
58 #define SDW_DP0_OFFSETCTRL2 0x25
59 #define SDW_DP0_HCTRL 0x26
60 #define SDW_DP0_LANECTRL 0x28
62 /* Both INT and STATUS register are same */
63 #define SDW_SCP_INT1 0x40
64 #define SDW_SCP_INTMASK1 0x41
66 #define SDW_SCP_INT1_PARITY BIT(0)
67 #define SDW_SCP_INT1_BUS_CLASH BIT(1)
68 #define SDW_SCP_INT1_IMPL_DEF BIT(2)
69 #define SDW_SCP_INT1_SCP2_CASCADE BIT(7)
70 #define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3)
72 #define SDW_SCP_INTSTAT2 0x42
73 #define SDW_SCP_INTSTAT2_SCP3_CASCADE BIT(7)
74 #define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0)
76 #define SDW_SCP_INTSTAT3 0x43
77 #define SDW_SCP_INTSTAT3_PORT11_14 GENMASK(3, 0)
79 /* Number of interrupt status registers */
80 #define SDW_NUM_INT_STAT_REGISTERS 3
82 /* Number of interrupt clear registers */
83 #define SDW_NUM_INT_CLEAR_REGISTERS 1
85 #define SDW_SCP_CTRL 0x44
86 #define SDW_SCP_CTRL_CLK_STP_NOW BIT(1)
87 #define SDW_SCP_CTRL_FORCE_RESET BIT(7)
89 #define SDW_SCP_STAT 0x44
90 #define SDW_SCP_STAT_CLK_STP_NF BIT(0)
91 #define SDW_SCP_STAT_HPHY_NOK BIT(5)
92 #define SDW_SCP_STAT_CURR_BANK BIT(6)
94 #define SDW_SCP_SYSTEMCTRL 0x45
95 #define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP BIT(0)
96 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE BIT(2)
97 #define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN BIT(3)
98 #define SDW_SCP_SYSTEMCTRL_HIGH_PHY BIT(4)
100 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE0 0
101 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1 BIT(2)
103 #define SDW_SCP_DEVNUMBER 0x46
104 #define SDW_SCP_HIGH_PHY_CHECK 0x47
105 #define SDW_SCP_ADDRPAGE1 0x48
106 #define SDW_SCP_ADDRPAGE2 0x49
107 #define SDW_SCP_KEEPEREN 0x4A
108 #define SDW_SCP_BANKDELAY 0x4B
109 #define SDW_SCP_TESTMODE 0x4F
110 #define SDW_SCP_DEVID_0 0x50
111 #define SDW_SCP_DEVID_1 0x51
112 #define SDW_SCP_DEVID_2 0x52
113 #define SDW_SCP_DEVID_3 0x53
114 #define SDW_SCP_DEVID_4 0x54
115 #define SDW_SCP_DEVID_5 0x55
117 /* Banked Registers */
118 #define SDW_SCP_FRAMECTRL_B0 0x60
119 #define SDW_SCP_FRAMECTRL_B1 (0x60 + SDW_BANK1_OFFSET)
120 #define SDW_SCP_NEXTFRAME_B0 0x61
121 #define SDW_SCP_NEXTFRAME_B1 (0x61 + SDW_BANK1_OFFSET)
123 /* Both INT and STATUS register is same */
124 #define SDW_DPN_INT(n) (0x0 + SDW_DPN_SIZE * (n))
125 #define SDW_DPN_INTMASK(n) (0x1 + SDW_DPN_SIZE * (n))
126 #define SDW_DPN_PORTCTRL(n) (0x2 + SDW_DPN_SIZE * (n))
127 #define SDW_DPN_BLOCKCTRL1(n) (0x3 + SDW_DPN_SIZE * (n))
128 #define SDW_DPN_PREPARESTATUS(n) (0x4 + SDW_DPN_SIZE * (n))
129 #define SDW_DPN_PREPARECTRL(n) (0x5 + SDW_DPN_SIZE * (n))
131 #define SDW_DPN_INT_TEST_FAIL BIT(0)
132 #define SDW_DPN_INT_PORT_READY BIT(1)
133 #define SDW_DPN_INT_IMPDEF1 BIT(5)
134 #define SDW_DPN_INT_IMPDEF2 BIT(6)
135 #define SDW_DPN_INT_IMPDEF3 BIT(7)
137 #define SDW_DPN_PORTCTRL_FLOWMODE GENMASK(1, 0)
138 #define SDW_DPN_PORTCTRL_DATAMODE GENMASK(3, 2)
139 #define SDW_DPN_PORTCTRL_NXTINVBANK BIT(4)
141 #define SDW_DPN_BLOCKCTRL1_WDLEN GENMASK(5, 0)
143 #define SDW_DPN_PREPARECTRL_CH_PREP GENMASK(7, 0)
145 #define SDW_DPN_CHANNELEN_B0(n) (0x20 + SDW_DPN_SIZE * (n))
146 #define SDW_DPN_CHANNELEN_B1(n) (0x30 + SDW_DPN_SIZE * (n))
148 #define SDW_DPN_BLOCKCTRL2_B0(n) (0x21 + SDW_DPN_SIZE * (n))
149 #define SDW_DPN_BLOCKCTRL2_B1(n) (0x31 + SDW_DPN_SIZE * (n))
151 #define SDW_DPN_SAMPLECTRL1_B0(n) (0x22 + SDW_DPN_SIZE * (n))
152 #define SDW_DPN_SAMPLECTRL1_B1(n) (0x32 + SDW_DPN_SIZE * (n))
154 #define SDW_DPN_SAMPLECTRL2_B0(n) (0x23 + SDW_DPN_SIZE * (n))
155 #define SDW_DPN_SAMPLECTRL2_B1(n) (0x33 + SDW_DPN_SIZE * (n))
157 #define SDW_DPN_OFFSETCTRL1_B0(n) (0x24 + SDW_DPN_SIZE * (n))
158 #define SDW_DPN_OFFSETCTRL1_B1(n) (0x34 + SDW_DPN_SIZE * (n))
160 #define SDW_DPN_OFFSETCTRL2_B0(n) (0x25 + SDW_DPN_SIZE * (n))
161 #define SDW_DPN_OFFSETCTRL2_B1(n) (0x35 + SDW_DPN_SIZE * (n))
163 #define SDW_DPN_HCTRL_B0(n) (0x26 + SDW_DPN_SIZE * (n))
164 #define SDW_DPN_HCTRL_B1(n) (0x36 + SDW_DPN_SIZE * (n))
166 #define SDW_DPN_BLOCKCTRL3_B0(n) (0x27 + SDW_DPN_SIZE * (n))
167 #define SDW_DPN_BLOCKCTRL3_B1(n) (0x37 + SDW_DPN_SIZE * (n))
169 #define SDW_DPN_LANECTRL_B0(n) (0x28 + SDW_DPN_SIZE * (n))
170 #define SDW_DPN_LANECTRL_B1(n) (0x38 + SDW_DPN_SIZE * (n))
172 #define SDW_DPN_SAMPLECTRL_LOW GENMASK(7, 0)
173 #define SDW_DPN_SAMPLECTRL_HIGH GENMASK(15, 8)
175 #define SDW_DPN_HCTRL_HSTART GENMASK(7, 4)
176 #define SDW_DPN_HCTRL_HSTOP GENMASK(3, 0)
178 #define SDW_NUM_CASC_PORT_INTSTAT1 4
179 #define SDW_CASC_PORT_START_INTSTAT1 0
180 #define SDW_CASC_PORT_MASK_INTSTAT1 0x8
181 #define SDW_CASC_PORT_REG_OFFSET_INTSTAT1 0x0
183 #define SDW_NUM_CASC_PORT_INTSTAT2 7
184 #define SDW_CASC_PORT_START_INTSTAT2 4
185 #define SDW_CASC_PORT_MASK_INTSTAT2 1
186 #define SDW_CASC_PORT_REG_OFFSET_INTSTAT2 1
188 #define SDW_NUM_CASC_PORT_INTSTAT3 4
189 #define SDW_CASC_PORT_START_INTSTAT3 11
190 #define SDW_CASC_PORT_MASK_INTSTAT3 1
191 #define SDW_CASC_PORT_REG_OFFSET_INTSTAT3 2
193 #endif /* __SDW_REGISTERS_H */