include/linux/stmmac.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*******************************************************************************
   3
   4   Header file for stmmac platform data
   5
   6   Copyright (C) 2009  STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10 *******************************************************************************/
  11
  12 #ifndef __STMMAC_PLATFORM_DATA
  13 #define __STMMAC_PLATFORM_DATA
  14
  15 #include <linux/platform_device.h>
  16 #include <linux/phy.h>
  17
  18 #define MTL_MAX_RX_QUEUES       8
  19 #define MTL_MAX_TX_QUEUES       8
  20 #define STMMAC_CH_MAX           8
  21
  22 #define STMMAC_RX_COE_NONE      0
  23 #define STMMAC_RX_COE_TYPE1     1
  24 #define STMMAC_RX_COE_TYPE2     2
  25
  26 /* Define the macros for CSR clock range parameters to be passed by
  27  * platform code.
  28  * This could also be configured at run time using CPU freq framework. */
  29
  30 /* MDC Clock Selection define*/
  31 #define STMMAC_CSR_60_100M      0x0     /* MDC = clk_scr_i/42 */
  32 #define STMMAC_CSR_100_150M     0x1     /* MDC = clk_scr_i/62 */
  33 #define STMMAC_CSR_20_35M       0x2     /* MDC = clk_scr_i/16 */
  34 #define STMMAC_CSR_35_60M       0x3     /* MDC = clk_scr_i/26 */
  35 #define STMMAC_CSR_150_250M     0x4     /* MDC = clk_scr_i/102 */
  36 #define STMMAC_CSR_250_300M     0x5     /* MDC = clk_scr_i/122 */
  37
  38 /* MTL algorithms identifiers */
  39 #define MTL_TX_ALGORITHM_WRR    0x0
  40 #define MTL_TX_ALGORITHM_WFQ    0x1
  41 #define MTL_TX_ALGORITHM_DWRR   0x2
  42 #define MTL_TX_ALGORITHM_SP     0x3
  43 #define MTL_RX_ALGORITHM_SP     0x4
  44 #define MTL_RX_ALGORITHM_WSP    0x5
  45
  46 /* RX/TX Queue Mode */
  47 #define MTL_QUEUE_AVB           0x0
  48 #define MTL_QUEUE_DCB           0x1
  49
  50 /* The MDC clock could be set higher than the IEEE 802.3
  51  * specified frequency limit 0f 2.5 MHz, by programming a clock divider
  52  * of value different than the above defined values. The resultant MDIO
  53  * clock frequency of 12.5 MHz is applicable for the interfacing chips
  54  * supporting higher MDC clocks.
  55  * The MDC clock selection macros need to be defined for MDC clock rate
  56  * of 12.5 MHz, corresponding to the following selection.
  57  */
  58 #define STMMAC_CSR_I_4          0x8     /* clk_csr_i/4 */
  59 #define STMMAC_CSR_I_6          0x9     /* clk_csr_i/6 */
  60 #define STMMAC_CSR_I_8          0xA     /* clk_csr_i/8 */
  61 #define STMMAC_CSR_I_10         0xB     /* clk_csr_i/10 */
  62 #define STMMAC_CSR_I_12         0xC     /* clk_csr_i/12 */
  63 #define STMMAC_CSR_I_14         0xD     /* clk_csr_i/14 */
  64 #define STMMAC_CSR_I_16         0xE     /* clk_csr_i/16 */
  65 #define STMMAC_CSR_I_18         0xF     /* clk_csr_i/18 */
  66
  67 /* AXI DMA Burst length supported */
  68 #define DMA_AXI_BLEN_4          (1 << 1)
  69 #define DMA_AXI_BLEN_8          (1 << 2)
  70 #define DMA_AXI_BLEN_16         (1 << 3)
  71 #define DMA_AXI_BLEN_32         (1 << 4)
  72 #define DMA_AXI_BLEN_64         (1 << 5)
  73 #define DMA_AXI_BLEN_128        (1 << 6)
  74 #define DMA_AXI_BLEN_256        (1 << 7)
  75 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
  76                         | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
  77                         | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
  78
  79 /* Platfrom data for platform device structure's platform_data field */
  80
  81 struct stmmac_mdio_bus_data {
  82         unsigned int phy_mask;
  83         unsigned int has_xpcs;
  84         unsigned int xpcs_an_inband;
  85         int *irqs;
  86         int probed_phy_irq;
  87         bool needs_reset;
  88 };
  89
  90 struct stmmac_dma_cfg {
  91         int pbl;
  92         int txpbl;
  93         int rxpbl;
  94         bool pblx8;
  95         int fixed_burst;
  96         int mixed_burst;
  97         bool aal;
  98         bool eame;
  99         bool multi_msi_en;
 100         bool dche;
 101 };
 102
 103 #define AXI_BLEN        7
 104 struct stmmac_axi {
 105         bool axi_lpi_en;
 106         bool axi_xit_frm;
 107         u32 axi_wr_osr_lmt;
 108         u32 axi_rd_osr_lmt;
 109         bool axi_kbbe;
 110         u32 axi_blen[AXI_BLEN];
 111         bool axi_fb;
 112         bool axi_mb;
 113         bool axi_rb;
 114 };
 115
 116 #define EST_GCL         1024
 117 struct stmmac_est {
 118         struct mutex lock;
 119         int enable;
 120         u32 btr_reserve[2];
 121         u32 btr_offset[2];
 122         u32 btr[2];
 123         u32 ctr[2];
 124         u32 ter;
 125         u32 gcl_unaligned[EST_GCL];
 126         u32 gcl[EST_GCL];
 127         u32 gcl_size;
 128 };
 129
 130 struct stmmac_rxq_cfg {
 131         u8 mode_to_use;
 132         u32 chan;
 133         u8 pkt_route;
 134         bool use_prio;
 135         u32 prio;
 136 };
 137
 138 struct stmmac_txq_cfg {
 139         u32 weight;
 140         u8 mode_to_use;
 141         /* Credit Base Shaper parameters */
 142         u32 send_slope;
 143         u32 idle_slope;
 144         u32 high_credit;
 145         u32 low_credit;
 146         bool use_prio;
 147         u32 prio;
 148         int tbs_en;
 149 };
 150
 151 /* FPE link state */
 152 enum stmmac_fpe_state {
 153         FPE_STATE_OFF = 0,
 154         FPE_STATE_CAPABLE = 1,
 155         FPE_STATE_ENTERING_ON = 2,
 156         FPE_STATE_ON = 3,
 157 };
 158
 159 /* FPE link-partner hand-shaking mPacket type */
 160 enum stmmac_mpacket_type {
 161         MPACKET_VERIFY = 0,
 162         MPACKET_RESPONSE = 1,
 163 };
 164
 165 enum stmmac_fpe_task_state_t {
 166         __FPE_REMOVING,
 167         __FPE_TASK_SCHED,
 168 };
 169
 170 struct stmmac_fpe_cfg {
 171         bool enable;                            /* FPE enable */
 172         bool hs_enable;                         /* FPE handshake enable */
 173         enum stmmac_fpe_state lp_fpe_state;     /* Link Partner FPE state */
 174         enum stmmac_fpe_state lo_fpe_state;     /* Local station FPE state */
 175 };
 176
 177 struct stmmac_safety_feature_cfg {
 178         u32 tsoee;
 179         u32 mrxpee;
 180         u32 mestee;
 181         u32 mrxee;
 182         u32 mtxee;
 183         u32 epsi;
 184         u32 edpp;
 185         u32 prtyen;
 186         u32 tmouten;
 187 };
 188
 189 struct plat_stmmacenet_data {
 190         int bus_id;
 191         int phy_addr;
 192         int interface;
 193         phy_interface_t phy_interface;
 194         struct stmmac_mdio_bus_data *mdio_bus_data;
 195         struct device_node *phy_node;
 196         struct device_node *phylink_node;
 197         struct device_node *mdio_node;
 198         struct stmmac_dma_cfg *dma_cfg;
 199         struct stmmac_est *est;
 200         struct stmmac_fpe_cfg *fpe_cfg;
 201         struct stmmac_safety_feature_cfg *safety_feat_cfg;
 202         int clk_csr;
 203         int has_gmac;
 204         int enh_desc;
 205         int tx_coe;
 206         int rx_coe;
 207         int bugged_jumbo;
 208         int pmt;
 209         int force_sf_dma_mode;
 210         int force_thresh_dma_mode;
 211         int riwt_off;
 212         int max_speed;
 213         int maxmtu;
 214         int multicast_filter_bins;
 215         int unicast_filter_entries;
 216         int tx_fifo_size;
 217         int rx_fifo_size;
 218         u32 addr64;
 219         u32 rx_queues_to_use;
 220         u32 tx_queues_to_use;
 221         u8 rx_sched_algorithm;
 222         u8 tx_sched_algorithm;
 223         struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
 224         struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
 225         void (*fix_mac_speed)(void *priv, unsigned int speed);
 226         int (*serdes_powerup)(struct net_device *ndev, void *priv);
 227         void (*serdes_powerdown)(struct net_device *ndev, void *priv);
 228         void (*speed_mode_2500)(struct net_device *ndev, void *priv);
 229         void (*ptp_clk_freq_config)(void *priv);
 230         int (*init)(struct platform_device *pdev, void *priv);
 231         void (*exit)(struct platform_device *pdev, void *priv);
 232         struct mac_device_info *(*setup)(void *priv);
 233         int (*clks_config)(void *priv, bool enabled);
 234         int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
 235                            void *ctx);
 236         void *bsp_priv;
 237         struct clk *stmmac_clk;
 238         struct clk *pclk;
 239         struct clk *clk_ptp_ref;
 240         unsigned int clk_ptp_rate;
 241         unsigned int clk_ref_rate;
 242         unsigned int mult_fact_100ns;
 243         s32 ptp_max_adj;
 244         struct reset_control *stmmac_rst;
 245         struct reset_control *stmmac_ahb_rst;
 246         struct stmmac_axi *axi;
 247         int has_gmac4;
 248         bool has_sun8i;
 249         bool tso_en;
 250         int rss_en;
 251         int mac_port_sel_speed;
 252         bool en_tx_lpi_clockgating;
 253         int has_xgmac;
 254         bool vlan_fail_q_en;
 255         u8 vlan_fail_q;
 256         unsigned int eee_usecs_rate;
 257         struct pci_dev *pdev;
 258         bool has_crossts;
 259         int int_snapshot_num;
 260         int ext_snapshot_num;
 261         bool ext_snapshot_en;
 262         bool multi_msi_en;
 263         int msi_mac_vec;
 264         int msi_wol_vec;
 265         int msi_lpi_vec;
 266         int msi_sfty_ce_vec;
 267         int msi_sfty_ue_vec;
 268         int msi_rx_base_vec;
 269         int msi_tx_base_vec;
 270         bool use_phy_wol;
 271 };
 272 #endif