1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*******************************************************************************
4 Header file for stmmac platform data
6 Copyright (C) 2009 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10 *******************************************************************************/
12 #ifndef __STMMAC_PLATFORM_DATA
13 #define __STMMAC_PLATFORM_DATA
15 #include <linux/platform_device.h>
16 #include <linux/phy.h>
18 #define MTL_MAX_RX_QUEUES 8
19 #define MTL_MAX_TX_QUEUES 8
20 #define STMMAC_CH_MAX 8
22 #define STMMAC_RX_COE_NONE 0
23 #define STMMAC_RX_COE_TYPE1 1
24 #define STMMAC_RX_COE_TYPE2 2
26 /* Define the macros for CSR clock range parameters to be passed by
28 * This could also be configured at run time using CPU freq framework. */
30 /* MDC Clock Selection define*/
31 #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
32 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
33 #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
34 #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
35 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
36 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
38 /* MTL algorithms identifiers */
39 #define MTL_TX_ALGORITHM_WRR 0x0
40 #define MTL_TX_ALGORITHM_WFQ 0x1
41 #define MTL_TX_ALGORITHM_DWRR 0x2
42 #define MTL_TX_ALGORITHM_SP 0x3
43 #define MTL_RX_ALGORITHM_SP 0x4
44 #define MTL_RX_ALGORITHM_WSP 0x5
46 /* RX/TX Queue Mode */
47 #define MTL_QUEUE_AVB 0x0
48 #define MTL_QUEUE_DCB 0x1
50 /* The MDC clock could be set higher than the IEEE 802.3
51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
52 * of value different than the above defined values. The resultant MDIO
53 * clock frequency of 12.5 MHz is applicable for the interfacing chips
54 * supporting higher MDC clocks.
55 * The MDC clock selection macros need to be defined for MDC clock rate
56 * of 12.5 MHz, corresponding to the following selection.
58 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
59 #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
60 #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
61 #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
62 #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
63 #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
64 #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
65 #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
67 /* AXI DMA Burst length supported */
68 #define DMA_AXI_BLEN_4 (1 << 1)
69 #define DMA_AXI_BLEN_8 (1 << 2)
70 #define DMA_AXI_BLEN_16 (1 << 3)
71 #define DMA_AXI_BLEN_32 (1 << 4)
72 #define DMA_AXI_BLEN_64 (1 << 5)
73 #define DMA_AXI_BLEN_128 (1 << 6)
74 #define DMA_AXI_BLEN_256 (1 << 7)
75 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
76 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
77 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
79 /* Platfrom data for platform device structure's platform_data field */
81 struct stmmac_mdio_bus_data
{
82 unsigned int phy_mask
;
83 unsigned int has_xpcs
;
89 struct stmmac_dma_cfg
{
107 u32 axi_blen
[AXI_BLEN
];
120 u32 gcl_unaligned
[EST_GCL
];
125 struct stmmac_rxq_cfg
{
133 struct stmmac_txq_cfg
{
136 /* Credit Base Shaper parameters */
146 struct plat_stmmacenet_data
{
150 phy_interface_t phy_interface
;
151 struct stmmac_mdio_bus_data
*mdio_bus_data
;
152 struct device_node
*phy_node
;
153 struct device_node
*phylink_node
;
154 struct device_node
*mdio_node
;
155 struct stmmac_dma_cfg
*dma_cfg
;
156 struct stmmac_est
*est
;
164 int force_sf_dma_mode
;
165 int force_thresh_dma_mode
;
169 int multicast_filter_bins
;
170 int unicast_filter_entries
;
173 u32 rx_queues_to_use
;
174 u32 tx_queues_to_use
;
175 u8 rx_sched_algorithm
;
176 u8 tx_sched_algorithm
;
177 struct stmmac_rxq_cfg rx_queues_cfg
[MTL_MAX_RX_QUEUES
];
178 struct stmmac_txq_cfg tx_queues_cfg
[MTL_MAX_TX_QUEUES
];
179 void (*fix_mac_speed
)(void *priv
, unsigned int speed
);
180 int (*serdes_powerup
)(struct net_device
*ndev
, void *priv
);
181 void (*serdes_powerdown
)(struct net_device
*ndev
, void *priv
);
182 int (*init
)(struct platform_device
*pdev
, void *priv
);
183 void (*exit
)(struct platform_device
*pdev
, void *priv
);
184 struct mac_device_info
*(*setup
)(void *priv
);
186 struct clk
*stmmac_clk
;
188 struct clk
*clk_ptp_ref
;
189 unsigned int clk_ptp_rate
;
190 unsigned int clk_ref_rate
;
192 struct reset_control
*stmmac_rst
;
193 struct stmmac_axi
*axi
;
198 int mac_port_sel_speed
;
199 bool en_tx_lpi_clockgating
;