1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Microsemi Switchtec PCIe Driver
4 * Copyright (c) 2017, Microsemi Corporation
10 #include <linux/pci.h>
11 #include <linux/cdev.h>
13 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
14 #define SWITCHTEC_MAX_PFF_CSR 255
16 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
17 #define SWITCHTEC_EVENT_CLEAR BIT(0)
18 #define SWITCHTEC_EVENT_EN_LOG BIT(1)
19 #define SWITCHTEC_EVENT_EN_CLI BIT(2)
20 #define SWITCHTEC_EVENT_EN_IRQ BIT(3)
21 #define SWITCHTEC_EVENT_FATAL BIT(4)
23 #define SWITCHTEC_DMA_MRPC_EN BIT(0)
25 SWITCHTEC_GAS_MRPC_OFFSET
= 0x0000,
26 SWITCHTEC_GAS_TOP_CFG_OFFSET
= 0x1000,
27 SWITCHTEC_GAS_SW_EVENT_OFFSET
= 0x1800,
28 SWITCHTEC_GAS_SYS_INFO_OFFSET
= 0x2000,
29 SWITCHTEC_GAS_FLASH_INFO_OFFSET
= 0x2200,
30 SWITCHTEC_GAS_PART_CFG_OFFSET
= 0x4000,
31 SWITCHTEC_GAS_NTB_OFFSET
= 0x10000,
32 SWITCHTEC_GAS_PFF_CSR_OFFSET
= 0x134000,
36 u8 input_data
[SWITCHTEC_MRPC_PAYLOAD_SIZE
];
37 u8 output_data
[SWITCHTEC_MRPC_PAYLOAD_SIZE
];
48 SWITCHTEC_MRPC_STATUS_INPROGRESS
= 1,
49 SWITCHTEC_MRPC_STATUS_DONE
= 2,
50 SWITCHTEC_MRPC_STATUS_ERROR
= 0xFF,
51 SWITCHTEC_MRPC_STATUS_INTERRUPTED
= 0x100,
54 struct sw_event_regs
{
55 u64 event_report_ctrl
;
57 u64 part_event_bitmap
;
61 u32 stack_error_event_hdr
;
62 u32 stack_error_event_data
;
64 u32 ppu_error_event_hdr
;
65 u32 ppu_error_event_data
;
67 u32 isp_error_event_hdr
;
68 u32 isp_error_event_data
;
70 u32 sys_reset_event_hdr
;
80 u32 twi_mrpc_comp_hdr
;
81 u32 twi_mrpc_comp_data
;
83 u32 twi_mrpc_comp_async_hdr
;
84 u32 twi_mrpc_comp_async_data
;
86 u32 cli_mrpc_comp_hdr
;
87 u32 cli_mrpc_comp_data
;
89 u32 cli_mrpc_comp_async_hdr
;
90 u32 cli_mrpc_comp_async_data
;
92 u32 gpio_interrupt_hdr
;
93 u32 gpio_interrupt_data
;
101 SWITCHTEC_CFG0_RUNNING
= 0x04,
102 SWITCHTEC_CFG1_RUNNING
= 0x05,
103 SWITCHTEC_IMG0_RUNNING
= 0x03,
104 SWITCHTEC_IMG1_RUNNING
= 0x07,
107 struct sys_info_regs
{
110 u32 firmware_version
;
112 u32 vendor_table_revision
;
113 u32 table_format_version
;
115 u32 cfg_file_fmt_version
;
121 char product_revision
[4];
122 char component_vendor
[8];
124 u8 component_revision
;
127 struct flash_info_regs
{
128 u32 flash_part_map_upd_idx
;
130 struct active_partition_info
{
136 struct active_partition_info active_cfg
;
137 struct active_partition_info inactive_img
;
138 struct active_partition_info inactive_cfg
;
142 struct partition_info
{
147 struct partition_info cfg1
;
148 struct partition_info img0
;
149 struct partition_info img1
;
150 struct partition_info nvlog
;
151 struct partition_info vendor
[8];
155 SWITCHTEC_NTB_REG_INFO_OFFSET
= 0x0000,
156 SWITCHTEC_NTB_REG_CTRL_OFFSET
= 0x4000,
157 SWITCHTEC_NTB_REG_DBMSG_OFFSET
= 0x64000,
160 struct ntb_info_regs
{
168 struct nt_partition_info
{
171 u32 target_part_high
;
176 struct part_cfg_regs
{
183 u32 dsp_pff_inst_id
[47];
185 u16 vep_vector_number
;
186 u16 usp_vector_number
;
187 u32 port_event_bitmap
;
189 u32 part_event_summary
;
192 u32 part_reset_data
[5];
194 u32 mrpc_comp_data
[5];
195 u32 mrpc_comp_async_hdr
;
196 u32 mrpc_comp_async_data
[5];
198 u32 dyn_binding_data
[5];
203 NTB_CTRL_PART_OP_LOCK
= 0x1,
204 NTB_CTRL_PART_OP_CFG
= 0x2,
205 NTB_CTRL_PART_OP_RESET
= 0x3,
207 NTB_CTRL_PART_STATUS_NORMAL
= 0x1,
208 NTB_CTRL_PART_STATUS_LOCKED
= 0x2,
209 NTB_CTRL_PART_STATUS_LOCKING
= 0x3,
210 NTB_CTRL_PART_STATUS_CONFIGURING
= 0x4,
211 NTB_CTRL_PART_STATUS_RESETTING
= 0x5,
213 NTB_CTRL_BAR_VALID
= 1 << 0,
214 NTB_CTRL_BAR_DIR_WIN_EN
= 1 << 4,
215 NTB_CTRL_BAR_LUT_WIN_EN
= 1 << 5,
217 NTB_CTRL_REQ_ID_EN
= 1 << 0,
219 NTB_CTRL_LUT_EN
= 1 << 0,
221 NTB_PART_CTRL_ID_PROT_DIS
= 1 << 0,
224 struct ntb_ctrl_regs
{
225 u32 partition_status
;
230 u16 lut_table_entries
;
231 u16 lut_table_offset
;
233 u16 req_id_table_size
;
234 u16 req_id_table_offset
;
247 u32 req_id_table
[512];
252 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
253 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
255 struct ntb_dbmsg_regs
{
285 SWITCHTEC_PART_CFG_EVENT_RESET
= 1 << 0,
286 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP
= 1 << 1,
287 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP
= 1 << 2,
288 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP
= 1 << 3,
291 struct pff_csr_regs
{
303 u32 pci_subsystem_id
;
304 u32 pci_expansion_rom
;
308 u32 pci_cap_region
[48];
309 u32 pcie_cap_region
[448];
310 u32 indirect_gas_window
[128];
311 u32 indirect_gas_window_off
;
313 u32 pff_event_summary
;
316 u32 aer_in_p2p_data
[5];
318 u32 aer_in_vep_data
[5];
329 u32 threshold_data
[5];
331 u32 power_mgmt_data
[5];
332 u32 tlp_throttling_hdr
;
333 u32 tlp_throttling_data
[5];
335 u32 force_speed_data
[5];
336 u32 credit_timeout_hdr
;
337 u32 credit_timeout_data
[5];
339 u32 link_state_data
[5];
343 struct switchtec_ntb
;
345 struct dma_mrpc_output
{
350 u8 data
[SWITCHTEC_MRPC_PAYLOAD_SIZE
];
353 struct switchtec_dev
{
354 struct pci_dev
*pdev
;
361 char pff_local
[SWITCHTEC_MAX_PFF_CSR
];
364 struct mrpc_regs __iomem
*mmio_mrpc
;
365 struct sw_event_regs __iomem
*mmio_sw_event
;
366 struct sys_info_regs __iomem
*mmio_sys_info
;
367 struct flash_info_regs __iomem
*mmio_flash_info
;
368 struct ntb_info_regs __iomem
*mmio_ntb
;
369 struct part_cfg_regs __iomem
*mmio_part_cfg
;
370 struct part_cfg_regs __iomem
*mmio_part_cfg_all
;
371 struct pff_csr_regs __iomem
*mmio_pff_csr
;
374 * The mrpc mutex must be held when accessing the other
375 * mrpc_ fields, alive flag and stuser->state field
377 struct mutex mrpc_mutex
;
378 struct list_head mrpc_queue
;
380 struct work_struct mrpc_work
;
381 struct delayed_work mrpc_timeout
;
384 wait_queue_head_t event_wq
;
387 struct work_struct link_event_work
;
388 void (*link_notifier
)(struct switchtec_dev
*stdev
);
389 u8 link_event_count
[SWITCHTEC_MAX_PFF_CSR
];
391 struct switchtec_ntb
*sndev
;
393 struct dma_mrpc_output
*dma_mrpc
;
394 dma_addr_t dma_mrpc_dma_addr
;
397 static inline struct switchtec_dev
*to_stdev(struct device
*dev
)
399 return container_of(dev
, struct switchtec_dev
, dev
);
402 extern struct class *switchtec_class
;