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2 * SyncLink Multiprotocol Serial Adapter Driver
4 * $Id: synclink.h,v 3.11 2006/02/06 21:20:29 paulkf Exp $
6 * Copyright (C) 1998-2000 by Microgate Corporation
8 * Redistribution of this file is permitted under
9 * the terms of the GNU Public License (GPL)
14 #define SYNCLINK_H_VERSION 3.6
36 #define BIT16 0x00010000
37 #define BIT17 0x00020000
38 #define BIT18 0x00040000
39 #define BIT19 0x00080000
40 #define BIT20 0x00100000
41 #define BIT21 0x00200000
42 #define BIT22 0x00400000
43 #define BIT23 0x00800000
44 #define BIT24 0x01000000
45 #define BIT25 0x02000000
46 #define BIT26 0x04000000
47 #define BIT27 0x08000000
48 #define BIT28 0x10000000
49 #define BIT29 0x20000000
50 #define BIT30 0x40000000
51 #define BIT31 0x80000000
54 #define HDLC_MAX_FRAME_SIZE 65535
55 #define MAX_ASYNC_TRANSMIT 4096
56 #define MAX_ASYNC_BUFFER_SIZE 4096
58 #define ASYNC_PARITY_NONE 0
59 #define ASYNC_PARITY_EVEN 1
60 #define ASYNC_PARITY_ODD 2
61 #define ASYNC_PARITY_SPACE 3
63 #define HDLC_FLAG_UNDERRUN_ABORT7 0x0000
64 #define HDLC_FLAG_UNDERRUN_ABORT15 0x0001
65 #define HDLC_FLAG_UNDERRUN_FLAG 0x0002
66 #define HDLC_FLAG_UNDERRUN_CRC 0x0004
67 #define HDLC_FLAG_SHARE_ZERO 0x0010
68 #define HDLC_FLAG_AUTO_CTS 0x0020
69 #define HDLC_FLAG_AUTO_DCD 0x0040
70 #define HDLC_FLAG_AUTO_RTS 0x0080
71 #define HDLC_FLAG_RXC_DPLL 0x0100
72 #define HDLC_FLAG_RXC_BRG 0x0200
73 #define HDLC_FLAG_RXC_TXCPIN 0x8000
74 #define HDLC_FLAG_RXC_RXCPIN 0x0000
75 #define HDLC_FLAG_TXC_DPLL 0x0400
76 #define HDLC_FLAG_TXC_BRG 0x0800
77 #define HDLC_FLAG_TXC_TXCPIN 0x0000
78 #define HDLC_FLAG_TXC_RXCPIN 0x0008
79 #define HDLC_FLAG_DPLL_DIV8 0x1000
80 #define HDLC_FLAG_DPLL_DIV16 0x2000
81 #define HDLC_FLAG_DPLL_DIV32 0x0000
82 #define HDLC_FLAG_HDLC_LOOPMODE 0x4000
84 #define HDLC_CRC_NONE 0
85 #define HDLC_CRC_16_CCITT 1
86 #define HDLC_CRC_32_CCITT 2
87 #define HDLC_CRC_MASK 0x00ff
88 #define HDLC_CRC_RETURN_EX 0x8000
91 #define RX_CRC_ERROR 1
93 #define HDLC_TXIDLE_FLAGS 0
94 #define HDLC_TXIDLE_ALT_ZEROS_ONES 1
95 #define HDLC_TXIDLE_ZEROS 2
96 #define HDLC_TXIDLE_ONES 3
97 #define HDLC_TXIDLE_ALT_MARK_SPACE 4
98 #define HDLC_TXIDLE_SPACE 5
99 #define HDLC_TXIDLE_MARK 6
101 #define HDLC_ENCODING_NRZ 0
102 #define HDLC_ENCODING_NRZB 1
103 #define HDLC_ENCODING_NRZI_MARK 2
104 #define HDLC_ENCODING_NRZI_SPACE 3
105 #define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE
106 #define HDLC_ENCODING_BIPHASE_MARK 4
107 #define HDLC_ENCODING_BIPHASE_SPACE 5
108 #define HDLC_ENCODING_BIPHASE_LEVEL 6
109 #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7
111 #define HDLC_PREAMBLE_LENGTH_8BITS 0
112 #define HDLC_PREAMBLE_LENGTH_16BITS 1
113 #define HDLC_PREAMBLE_LENGTH_32BITS 2
114 #define HDLC_PREAMBLE_LENGTH_64BITS 3
116 #define HDLC_PREAMBLE_PATTERN_NONE 0
117 #define HDLC_PREAMBLE_PATTERN_ZEROS 1
118 #define HDLC_PREAMBLE_PATTERN_FLAGS 2
119 #define HDLC_PREAMBLE_PATTERN_10 3
120 #define HDLC_PREAMBLE_PATTERN_01 4
121 #define HDLC_PREAMBLE_PATTERN_ONES 5
123 #define MGSL_MODE_ASYNC 1
124 #define MGSL_MODE_HDLC 2
125 #define MGSL_MODE_RAW 6
127 #define MGSL_BUS_TYPE_ISA 1
128 #define MGSL_BUS_TYPE_EISA 2
129 #define MGSL_BUS_TYPE_PCI 5
131 #define MGSL_INTERFACE_MASK 0xf
132 #define MGSL_INTERFACE_DISABLE 0
133 #define MGSL_INTERFACE_RS232 1
134 #define MGSL_INTERFACE_V35 2
135 #define MGSL_INTERFACE_RS422 3
136 #define MGSL_INTERFACE_RTS_EN 0x10
137 #define MGSL_INTERFACE_LL 0x20
138 #define MGSL_INTERFACE_RL 0x40
140 typedef struct _MGSL_PARAMS
144 unsigned long mode
; /* Asynchronous or HDLC */
145 unsigned char loopback
; /* internal loopback mode */
149 unsigned short flags
;
150 unsigned char encoding
; /* NRZ, NRZI, etc. */
151 unsigned long clock_speed
; /* external clock speed in bits per second */
152 unsigned char addr_filter
; /* receive HDLC address filter, 0xFF = disable */
153 unsigned short crc_type
; /* None, CRC16-CCITT, or CRC32-CCITT */
154 unsigned char preamble_length
;
155 unsigned char preamble
;
159 unsigned long data_rate
; /* bits per second */
160 unsigned char data_bits
; /* 7 or 8 data bits */
161 unsigned char stop_bits
; /* 1 or 2 stop bits */
162 unsigned char parity
; /* none, even, or odd */
164 } MGSL_PARAMS
, *PMGSL_PARAMS
;
166 #define MICROGATE_VENDOR_ID 0x13c0
167 #define SYNCLINK_DEVICE_ID 0x0010
168 #define MGSCC_DEVICE_ID 0x0020
169 #define SYNCLINK_SCA_DEVICE_ID 0x0030
170 #define SYNCLINK_GT_DEVICE_ID 0x0070
171 #define SYNCLINK_GT4_DEVICE_ID 0x0080
172 #define SYNCLINK_AC_DEVICE_ID 0x0090
173 #define MGSL_MAX_SERIAL_NUMBER 30
176 ** device diagnostics status
179 #define DiagStatus_OK 0
180 #define DiagStatus_AddressFailure 1
181 #define DiagStatus_AddressConflict 2
182 #define DiagStatus_IrqFailure 3
183 #define DiagStatus_IrqConflict 4
184 #define DiagStatus_DmaFailure 5
185 #define DiagStatus_DmaConflict 6
186 #define DiagStatus_PciAdapterNotFound 7
187 #define DiagStatus_CantAssignPciResources 8
188 #define DiagStatus_CantAssignPciMemAddr 9
189 #define DiagStatus_CantAssignPciIoAddr 10
190 #define DiagStatus_CantAssignPciIrq 11
191 #define DiagStatus_MemoryError 12
193 #define SerialSignal_DCD 0x01 /* Data Carrier Detect */
194 #define SerialSignal_TXD 0x02 /* Transmit Data */
195 #define SerialSignal_RI 0x04 /* Ring Indicator */
196 #define SerialSignal_RXD 0x08 /* Receive Data */
197 #define SerialSignal_CTS 0x10 /* Clear to Send */
198 #define SerialSignal_RTS 0x20 /* Request to Send */
199 #define SerialSignal_DSR 0x40 /* Data Set Ready */
200 #define SerialSignal_DTR 0x80 /* Data Terminal Ready */
204 * Counters of the input lines (CTS, DSR, RI, CD) interrupts
207 __u32 cts
, dsr
, rng
, dcd
, tx
, rx
;
208 __u32 frame
, parity
, overrun
, brk
;
231 #define DEBUG_LEVEL_DATA 1
232 #define DEBUG_LEVEL_ERROR 2
233 #define DEBUG_LEVEL_INFO 3
234 #define DEBUG_LEVEL_BH 4
235 #define DEBUG_LEVEL_ISR 5
238 ** Event bit flags for use with MgslWaitEvent
241 #define MgslEvent_DsrActive 0x0001
242 #define MgslEvent_DsrInactive 0x0002
243 #define MgslEvent_Dsr 0x0003
244 #define MgslEvent_CtsActive 0x0004
245 #define MgslEvent_CtsInactive 0x0008
246 #define MgslEvent_Cts 0x000c
247 #define MgslEvent_DcdActive 0x0010
248 #define MgslEvent_DcdInactive 0x0020
249 #define MgslEvent_Dcd 0x0030
250 #define MgslEvent_RiActive 0x0040
251 #define MgslEvent_RiInactive 0x0080
252 #define MgslEvent_Ri 0x00c0
253 #define MgslEvent_ExitHuntMode 0x0100
254 #define MgslEvent_IdleReceived 0x0200
256 /* Private IOCTL codes:
258 * MGSL_IOCSPARAMS set MGSL_PARAMS structure values
259 * MGSL_IOCGPARAMS get current MGSL_PARAMS structure values
260 * MGSL_IOCSTXIDLE set current transmit idle mode
261 * MGSL_IOCGTXIDLE get current transmit idle mode
262 * MGSL_IOCTXENABLE enable or disable transmitter
263 * MGSL_IOCRXENABLE enable or disable receiver
264 * MGSL_IOCTXABORT abort transmitting frame (HDLC)
265 * MGSL_IOCGSTATS return current statistics
266 * MGSL_IOCWAITEVENT wait for specified event to occur
267 * MGSL_LOOPTXDONE transmit in HDLC LoopMode done
268 * MGSL_IOCSIF set the serial interface type
269 * MGSL_IOCGIF get the serial interface type
271 #define MGSL_MAGIC_IOC 'm'
272 #define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS)
273 #define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS)
274 #define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2)
275 #define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3)
276 #define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4)
277 #define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5)
278 #define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6)
279 #define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7)
280 #define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int)
281 #define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15)
282 #define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9)
283 #define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC,10)
284 #define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC,11)
285 #define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc)
286 #define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc)
287 #define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc)
289 #endif /* _SYNCLINK_H_ */