include/linux/usb/tegra_usb_phy.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2010 Google, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #ifndef __TEGRA_USB_PHY_H
  17 #define __TEGRA_USB_PHY_H
  18
  19 #include <linux/clk.h>
  20 #include <linux/usb/otg.h>
  21
  22 /*
  23  * utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers
  24  *     should be set up by clk-tegra, false if by the PHY code
  25  * has_hostpc: true if the USB controller has the HOSTPC extension, which
  26  *     changes the location of the PHCD and PTS fields
  27  * requires_usbmode_setup: true if the USBMODE register needs to be set to
  28  *      enter host mode
  29  * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level
  30  *      and hsdiscon_level should be set for adequate signal quality
  31  */
  32
  33 struct tegra_phy_soc_config {
  34         bool utmi_pll_config_in_car_module;
  35         bool has_hostpc;
  36         bool requires_usbmode_setup;
  37         bool requires_extra_tuning_parameters;
  38 };
  39
  40 struct tegra_utmip_config {
  41         u8 hssync_start_delay;
  42         u8 elastic_limit;
  43         u8 idle_wait_delay;
  44         u8 term_range_adj;
  45         bool xcvr_setup_use_fuses;
  46         u8 xcvr_setup;
  47         u8 xcvr_lsfslew;
  48         u8 xcvr_lsrslew;
  49         u8 xcvr_hsslew;
  50         u8 hssquelch_level;
  51         u8 hsdiscon_level;
  52 };
  53
  54 enum tegra_usb_phy_port_speed {
  55         TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
  56         TEGRA_USB_PHY_PORT_SPEED_LOW,
  57         TEGRA_USB_PHY_PORT_SPEED_HIGH,
  58 };
  59
  60 struct tegra_xtal_freq;
  61
  62 struct tegra_usb_phy {
  63         int instance;
  64         const struct tegra_xtal_freq *freq;
  65         void __iomem *regs;
  66         void __iomem *pad_regs;
  67         struct clk *clk;
  68         struct clk *pll_u;
  69         struct clk *pad_clk;
  70         struct regulator *vbus;
  71         enum usb_dr_mode mode;
  72         void *config;
  73         const struct tegra_phy_soc_config *soc_config;
  74         struct usb_phy *ulpi;
  75         struct usb_phy u_phy;
  76         bool is_legacy_phy;
  77         bool is_ulpi_phy;
  78         int reset_gpio;
  79 };
  80
  81 void tegra_usb_phy_preresume(struct usb_phy *phy);
  82
  83 void tegra_usb_phy_postresume(struct usb_phy *phy);
  84
  85 void tegra_ehci_phy_restore_start(struct usb_phy *phy,
  86                                  enum tegra_usb_phy_port_speed port_speed);
  87
  88 void tegra_ehci_phy_restore_end(struct usb_phy *phy);
  89
  90 #endif /* __TEGRA_USB_PHY_H */