include/qom/cpu.h

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_CPU_H
  21 #define QEMU_CPU_H
  22
  23 #include "hw/qdev-core.h"
  24 #include "disas/bfd.h"
  25 #include "exec/hwaddr.h"
  26 #include "exec/memattrs.h"
  27 #include "qemu/queue.h"
  28 #include "qemu/thread.h"
  29
  30 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
  31                                      void *opaque);
  32
  33 /**
  34  * vaddr:
  35  * Type wide enough to contain any #target_ulong virtual address.
  36  */
  37 typedef uint64_t vaddr;
  38 #define VADDR_PRId PRId64
  39 #define VADDR_PRIu PRIu64
  40 #define VADDR_PRIo PRIo64
  41 #define VADDR_PRIx PRIx64
  42 #define VADDR_PRIX PRIX64
  43 #define VADDR_MAX UINT64_MAX
  44
  45 /**
  46  * SECTION:cpu
  47  * @section_id: QEMU-cpu
  48  * @title: CPU Class
  49  * @short_description: Base class for all CPUs
  50  */
  51
  52 #define TYPE_CPU "cpu"
  53
  54 /* Since this macro is used a lot in hot code paths and in conjunction with
  55  * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
  56  * an unchecked cast.
  57  */
  58 #define CPU(obj) ((CPUState *)(obj))
  59
  60 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
  61 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
  62
  63 typedef struct CPUWatchpoint CPUWatchpoint;
  64
  65 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
  66                                     bool is_write, bool is_exec, int opaque,
  67                                     unsigned size);
  68
  69 struct TranslationBlock;
  70
  71 /**
  72  * CPUClass:
  73  * @class_by_name: Callback to map -cpu command line model name to an
  74  * instantiatable CPU type.
  75  * @parse_features: Callback to parse command line arguments.
  76  * @reset: Callback to reset the #CPUState to its initial state.
  77  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
  78  * @has_work: Callback for checking if there is work to do.
  79  * @do_interrupt: Callback for interrupt handling.
  80  * @do_unassigned_access: Callback for unassigned access handling.
  81  * @do_unaligned_access: Callback for unaligned access handling, if
  82  * the target defines #ALIGNED_ONLY.
  83  * @virtio_is_big_endian: Callback to return %true if a CPU which supports
  84  * runtime configurable endianness is currently big-endian. Non-configurable
  85  * CPUs can use the default implementation of this method. This method should
  86  * not be used by any callers other than the pre-1.0 virtio devices.
  87  * @memory_rw_debug: Callback for GDB memory access.
  88  * @dump_state: Callback for dumping state.
  89  * @dump_statistics: Callback for dumping statistics.
  90  * @get_arch_id: Callback for getting architecture-dependent CPU ID.
  91  * @get_paging_enabled: Callback for inquiring whether paging is enabled.
  92  * @get_memory_mapping: Callback for obtaining the memory mappings.
  93  * @set_pc: Callback for setting the Program Counter register.
  94  * @synchronize_from_tb: Callback for synchronizing state from a TCG
  95  * #TranslationBlock.
  96  * @handle_mmu_fault: Callback for handling an MMU fault.
  97  * @get_phys_page_debug: Callback for obtaining a physical address.
  98  * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
  99  *       associated memory transaction attributes to use for the access.
 100  *       CPUs which use memory transaction attributes should implement this
 101  *       instead of get_phys_page_debug.
 102  * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
 103  *       a memory access with the specified memory transaction attributes.
 104  * @gdb_read_register: Callback for letting GDB read a register.
 105  * @gdb_write_register: Callback for letting GDB write a register.
 106  * @debug_check_watchpoint: Callback: return true if the architectural
 107  *       watchpoint whose address has matched should really fire.
 108  * @debug_excp_handler: Callback for handling debug exceptions.
 109  * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
 110  * 64-bit VM coredump.
 111  * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
 112  * note to a 32-bit VM coredump.
 113  * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
 114  * 32-bit VM coredump.
 115  * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
 116  * note to a 32-bit VM coredump.
 117  * @vmsd: State description for migration.
 118  * @gdb_num_core_regs: Number of core registers accessible to GDB.
 119  * @gdb_core_xml_file: File name for core registers GDB XML description.
 120  * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
 121  *           before the insn which triggers a watchpoint rather than after it.
 122  * @gdb_arch_name: Optional callback that returns the architecture name known
 123  * to GDB. The caller must free the returned string with g_free.
 124  * @cpu_exec_enter: Callback for cpu_exec preparation.
 125  * @cpu_exec_exit: Callback for cpu_exec cleanup.
 126  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
 127  * @disas_set_info: Setup architecture specific components of disassembly info
 128  *
 129  * Represents a CPU family or model.
 130  */
 131 typedef struct CPUClass {
 132     /*< private >*/
 133     DeviceClass parent_class;
 134     /*< public >*/
 135
 136     ObjectClass *(*class_by_name)(const char *cpu_model);
 137     void (*parse_features)(CPUState *cpu, char *str, Error **errp);
 138
 139     void (*reset)(CPUState *cpu);
 140     int reset_dump_flags;
 141     bool (*has_work)(CPUState *cpu);
 142     void (*do_interrupt)(CPUState *cpu);
 143     CPUUnassignedAccess do_unassigned_access;
 144     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
 145                                 int is_write, int is_user, uintptr_t retaddr);
 146     bool (*virtio_is_big_endian)(CPUState *cpu);
 147     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
 148                            uint8_t *buf, int len, bool is_write);
 149     void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 150                        int flags);
 151     void (*dump_statistics)(CPUState *cpu, FILE *f,
 152                             fprintf_function cpu_fprintf, int flags);
 153     int64_t (*get_arch_id)(CPUState *cpu);
 154     bool (*get_paging_enabled)(const CPUState *cpu);
 155     void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
 156                                Error **errp);
 157     void (*set_pc)(CPUState *cpu, vaddr value);
 158     void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
 159     int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
 160                             int mmu_index);
 161     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
 162     hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
 163                                         MemTxAttrs *attrs);
 164     int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
 165     int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
 166     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
 167     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
 168     void (*debug_excp_handler)(CPUState *cpu);
 169
 170     int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
 171                             int cpuid, void *opaque);
 172     int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 173                                 void *opaque);
 174     int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
 175                             int cpuid, void *opaque);
 176     int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 177                                 void *opaque);
 178
 179     const struct VMStateDescription *vmsd;
 180     int gdb_num_core_regs;
 181     const char *gdb_core_xml_file;
 182     gchar * (*gdb_arch_name)(CPUState *cpu);
 183     bool gdb_stop_before_watchpoint;
 184
 185     void (*cpu_exec_enter)(CPUState *cpu);
 186     void (*cpu_exec_exit)(CPUState *cpu);
 187     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
 188
 189     void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
 190 } CPUClass;
 191
 192 #ifdef HOST_WORDS_BIGENDIAN
 193 typedef struct icount_decr_u16 {
 194     uint16_t high;
 195     uint16_t low;
 196 } icount_decr_u16;
 197 #else
 198 typedef struct icount_decr_u16 {
 199     uint16_t low;
 200     uint16_t high;
 201 } icount_decr_u16;
 202 #endif
 203
 204 typedef struct CPUBreakpoint {
 205     vaddr pc;
 206     int flags; /* BP_* */
 207     QTAILQ_ENTRY(CPUBreakpoint) entry;
 208 } CPUBreakpoint;
 209
 210 struct CPUWatchpoint {
 211     vaddr vaddr;
 212     vaddr len;
 213     vaddr hitaddr;
 214     MemTxAttrs hitattrs;
 215     int flags; /* BP_* */
 216     QTAILQ_ENTRY(CPUWatchpoint) entry;
 217 };
 218
 219 struct KVMState;
 220 struct kvm_run;
 221
 222 #define TB_JMP_CACHE_BITS 12
 223 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
 224
 225 /* work queue */
 226 struct qemu_work_item {
 227     struct qemu_work_item *next;
 228     void (*func)(void *data);
 229     void *data;
 230     int done;
 231     bool free;
 232 };
 233
 234 /**
 235  * CPUState:
 236  * @cpu_index: CPU index (informative).
 237  * @nr_cores: Number of cores within this CPU package.
 238  * @nr_threads: Number of threads within this CPU.
 239  * @numa_node: NUMA node this CPU is belonging to.
 240  * @host_tid: Host thread ID.
 241  * @running: #true if CPU is currently running (usermode).
 242  * @created: Indicates whether the CPU thread has been successfully created.
 243  * @interrupt_request: Indicates a pending interrupt request.
 244  * @halted: Nonzero if the CPU is in suspended state.
 245  * @stop: Indicates a pending stop request.
 246  * @stopped: Indicates the CPU has been artificially stopped.
 247  * @unplug: Indicates a pending CPU unplug request.
 248  * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
 249  * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
 250  *           CPU and return to its top level loop.
 251  * @tb_flushed: Indicates the translation buffer has been flushed.
 252  * @singlestep_enabled: Flags for single-stepping.
 253  * @icount_extra: Instructions until next timer event.
 254  * @icount_decr: Number of cycles left, with interrupt flag in high bit.
 255  * This allows a single read-compare-cbranch-write sequence to test
 256  * for both decrementer underflow and exceptions.
 257  * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
 258  * requires that IO only be performed on the last instruction of a TB
 259  * so that interrupts take effect immediately.
 260  * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
 261  *            AddressSpaces this CPU has)
 262  * @num_ases: number of CPUAddressSpaces in @cpu_ases
 263  * @as: Pointer to the first AddressSpace, for the convenience of targets which
 264  *      only have a single AddressSpace
 265  * @env_ptr: Pointer to subclass-specific CPUArchState field.
 266  * @gdb_regs: Additional GDB registers.
 267  * @gdb_num_regs: Number of total registers accessible to GDB.
 268  * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
 269  * @next_cpu: Next CPU sharing TB cache.
 270  * @opaque: User data.
 271  * @mem_io_pc: Host Program Counter at which the memory was accessed.
 272  * @mem_io_vaddr: Target virtual address at which the memory was accessed.
 273  * @kvm_fd: vCPU file descriptor for KVM.
 274  * @work_mutex: Lock to prevent multiple access to queued_work_*.
 275  * @queued_work_first: First asynchronous work pending.
 276  *
 277  * State of one CPU core or thread.
 278  */
 279 struct CPUState {
 280     /*< private >*/
 281     DeviceState parent_obj;
 282     /*< public >*/
 283
 284     int nr_cores;
 285     int nr_threads;
 286     int numa_node;
 287
 288     struct QemuThread *thread;
 289 #ifdef _WIN32
 290     HANDLE hThread;
 291 #endif
 292     int thread_id;
 293     uint32_t host_tid;
 294     bool running;
 295     struct QemuCond *halt_cond;
 296     bool thread_kicked;
 297     bool created;
 298     bool stop;
 299     bool stopped;
 300     bool unplug;
 301     bool crash_occurred;
 302     bool exit_request;
 303     bool tb_flushed;
 304     uint32_t interrupt_request;
 305     int singlestep_enabled;
 306     int64_t icount_extra;
 307     sigjmp_buf jmp_env;
 308
 309     QemuMutex work_mutex;
 310     struct qemu_work_item *queued_work_first, *queued_work_last;
 311
 312     CPUAddressSpace *cpu_ases;
 313     int num_ases;
 314     AddressSpace *as;
 315     MemoryRegion *memory;
 316
 317     void *env_ptr; /* CPUArchState */
 318     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
 319     struct GDBRegisterState *gdb_regs;
 320     int gdb_num_regs;
 321     int gdb_num_g_regs;
 322     QTAILQ_ENTRY(CPUState) node;
 323
 324     /* ice debug support */
 325     QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
 326
 327     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
 328     CPUWatchpoint *watchpoint_hit;
 329
 330     void *opaque;
 331
 332     /* In order to avoid passing too many arguments to the MMIO helpers,
 333      * we store some rarely used information in the CPU context.
 334      */
 335     uintptr_t mem_io_pc;
 336     vaddr mem_io_vaddr;
 337
 338     int kvm_fd;
 339     bool kvm_vcpu_dirty;
 340     struct KVMState *kvm_state;
 341     struct kvm_run *kvm_run;
 342
 343     /* TODO Move common fields from CPUArchState here. */
 344     int cpu_index; /* used by alpha TCG */
 345     uint32_t halted; /* used by alpha, cris, ppc TCG */
 346     union {
 347         uint32_t u32;
 348         icount_decr_u16 u16;
 349     } icount_decr;
 350     uint32_t can_do_io;
 351     int32_t exception_index; /* used by m68k TCG */
 352
 353     /* Used to keep track of an outstanding cpu throttle thread for migration
 354      * autoconverge
 355      */
 356     bool throttle_thread_scheduled;
 357
 358     /* Note that this is accessed at the start of every TB via a negative
 359        offset from AREG0.  Leave this field at the end so as to make the
 360        (absolute value) offset as small as possible.  This reduces code
 361        size, especially for hosts without large memory offsets.  */
 362     uint32_t tcg_exit_req;
 363 };
 364
 365 QTAILQ_HEAD(CPUTailQ, CPUState);
 366 extern struct CPUTailQ cpus;
 367 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
 368 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
 369 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
 370     QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
 371 #define CPU_FOREACH_REVERSE(cpu) \
 372     QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node)
 373 #define first_cpu QTAILQ_FIRST(&cpus)
 374
 375 extern __thread CPUState *current_cpu;
 376
 377 /**
 378  * cpu_paging_enabled:
 379  * @cpu: The CPU whose state is to be inspected.
 380  *
 381  * Returns: %true if paging is enabled, %false otherwise.
 382  */
 383 bool cpu_paging_enabled(const CPUState *cpu);
 384
 385 /**
 386  * cpu_get_memory_mapping:
 387  * @cpu: The CPU whose memory mappings are to be obtained.
 388  * @list: Where to write the memory mappings to.
 389  * @errp: Pointer for reporting an #Error.
 390  */
 391 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
 392                             Error **errp);
 393
 394 /**
 395  * cpu_write_elf64_note:
 396  * @f: pointer to a function that writes memory to a file
 397  * @cpu: The CPU whose memory is to be dumped
 398  * @cpuid: ID number of the CPU
 399  * @opaque: pointer to the CPUState struct
 400  */
 401 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 402                          int cpuid, void *opaque);
 403
 404 /**
 405  * cpu_write_elf64_qemunote:
 406  * @f: pointer to a function that writes memory to a file
 407  * @cpu: The CPU whose memory is to be dumped
 408  * @cpuid: ID number of the CPU
 409  * @opaque: pointer to the CPUState struct
 410  */
 411 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 412                              void *opaque);
 413
 414 /**
 415  * cpu_write_elf32_note:
 416  * @f: pointer to a function that writes memory to a file
 417  * @cpu: The CPU whose memory is to be dumped
 418  * @cpuid: ID number of the CPU
 419  * @opaque: pointer to the CPUState struct
 420  */
 421 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 422                          int cpuid, void *opaque);
 423
 424 /**
 425  * cpu_write_elf32_qemunote:
 426  * @f: pointer to a function that writes memory to a file
 427  * @cpu: The CPU whose memory is to be dumped
 428  * @cpuid: ID number of the CPU
 429  * @opaque: pointer to the CPUState struct
 430  */
 431 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 432                              void *opaque);
 433
 434 /**
 435  * CPUDumpFlags:
 436  * @CPU_DUMP_CODE:
 437  * @CPU_DUMP_FPU: dump FPU register state, not just integer
 438  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
 439  */
 440 enum CPUDumpFlags {
 441     CPU_DUMP_CODE = 0x00010000,
 442     CPU_DUMP_FPU  = 0x00020000,
 443     CPU_DUMP_CCOP = 0x00040000,
 444 };
 445
 446 /**
 447  * cpu_dump_state:
 448  * @cpu: The CPU whose state is to be dumped.
 449  * @f: File to dump to.
 450  * @cpu_fprintf: Function to dump with.
 451  * @flags: Flags what to dump.
 452  *
 453  * Dumps CPU state.
 454  */
 455 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 456                     int flags);
 457
 458 /**
 459  * cpu_dump_statistics:
 460  * @cpu: The CPU whose state is to be dumped.
 461  * @f: File to dump to.
 462  * @cpu_fprintf: Function to dump with.
 463  * @flags: Flags what to dump.
 464  *
 465  * Dumps CPU statistics.
 466  */
 467 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 468                          int flags);
 469
 470 #ifndef CONFIG_USER_ONLY
 471 /**
 472  * cpu_get_phys_page_attrs_debug:
 473  * @cpu: The CPU to obtain the physical page address for.
 474  * @addr: The virtual address.
 475  * @attrs: Updated on return with the memory transaction attributes to use
 476  *         for this access.
 477  *
 478  * Obtains the physical page corresponding to a virtual one, together
 479  * with the corresponding memory transaction attributes to use for the access.
 480  * Use it only for debugging because no protection checks are done.
 481  *
 482  * Returns: Corresponding physical page address or -1 if no page found.
 483  */
 484 static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
 485                                                    MemTxAttrs *attrs)
 486 {
 487     CPUClass *cc = CPU_GET_CLASS(cpu);
 488
 489     if (cc->get_phys_page_attrs_debug) {
 490         return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
 491     }
 492     /* Fallback for CPUs which don't implement the _attrs_ hook */
 493     *attrs = MEMTXATTRS_UNSPECIFIED;
 494     return cc->get_phys_page_debug(cpu, addr);
 495 }
 496
 497 /**
 498  * cpu_get_phys_page_debug:
 499  * @cpu: The CPU to obtain the physical page address for.
 500  * @addr: The virtual address.
 501  *
 502  * Obtains the physical page corresponding to a virtual one.
 503  * Use it only for debugging because no protection checks are done.
 504  *
 505  * Returns: Corresponding physical page address or -1 if no page found.
 506  */
 507 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
 508 {
 509     MemTxAttrs attrs = {};
 510
 511     return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
 512 }
 513
 514 /** cpu_asidx_from_attrs:
 515  * @cpu: CPU
 516  * @attrs: memory transaction attributes
 517  *
 518  * Returns the address space index specifying the CPU AddressSpace
 519  * to use for a memory access with the given transaction attributes.
 520  */
 521 static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
 522 {
 523     CPUClass *cc = CPU_GET_CLASS(cpu);
 524
 525     if (cc->asidx_from_attrs) {
 526         return cc->asidx_from_attrs(cpu, attrs);
 527     }
 528     return 0;
 529 }
 530 #endif
 531
 532 /**
 533  * cpu_reset:
 534  * @cpu: The CPU whose state is to be reset.
 535  */
 536 void cpu_reset(CPUState *cpu);
 537
 538 /**
 539  * cpu_class_by_name:
 540  * @typename: The CPU base type.
 541  * @cpu_model: The model string without any parameters.
 542  *
 543  * Looks up a CPU #ObjectClass matching name @cpu_model.
 544  *
 545  * Returns: A #CPUClass or %NULL if not matching class is found.
 546  */
 547 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
 548
 549 /**
 550  * cpu_generic_init:
 551  * @typename: The CPU base type.
 552  * @cpu_model: The model string including optional parameters.
 553  *
 554  * Instantiates a CPU, processes optional parameters and realizes the CPU.
 555  *
 556  * Returns: A #CPUState or %NULL if an error occurred.
 557  */
 558 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
 559
 560 /**
 561  * cpu_has_work:
 562  * @cpu: The vCPU to check.
 563  *
 564  * Checks whether the CPU has work to do.
 565  *
 566  * Returns: %true if the CPU has work, %false otherwise.
 567  */
 568 static inline bool cpu_has_work(CPUState *cpu)
 569 {
 570     CPUClass *cc = CPU_GET_CLASS(cpu);
 571
 572     g_assert(cc->has_work);
 573     return cc->has_work(cpu);
 574 }
 575
 576 /**
 577  * qemu_cpu_is_self:
 578  * @cpu: The vCPU to check against.
 579  *
 580  * Checks whether the caller is executing on the vCPU thread.
 581  *
 582  * Returns: %true if called from @cpu's thread, %false otherwise.
 583  */
 584 bool qemu_cpu_is_self(CPUState *cpu);
 585
 586 /**
 587  * qemu_cpu_kick:
 588  * @cpu: The vCPU to kick.
 589  *
 590  * Kicks @cpu's thread.
 591  */
 592 void qemu_cpu_kick(CPUState *cpu);
 593
 594 /**
 595  * cpu_is_stopped:
 596  * @cpu: The CPU to check.
 597  *
 598  * Checks whether the CPU is stopped.
 599  *
 600  * Returns: %true if run state is not running or if artificially stopped;
 601  * %false otherwise.
 602  */
 603 bool cpu_is_stopped(CPUState *cpu);
 604
 605 /**
 606  * run_on_cpu:
 607  * @cpu: The vCPU to run on.
 608  * @func: The function to be executed.
 609  * @data: Data to pass to the function.
 610  *
 611  * Schedules the function @func for execution on the vCPU @cpu.
 612  */
 613 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 614
 615 /**
 616  * async_run_on_cpu:
 617  * @cpu: The vCPU to run on.
 618  * @func: The function to be executed.
 619  * @data: Data to pass to the function.
 620  *
 621  * Schedules the function @func for execution on the vCPU @cpu asynchronously.
 622  */
 623 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 624
 625 /**
 626  * qemu_get_cpu:
 627  * @index: The CPUState@cpu_index value of the CPU to obtain.
 628  *
 629  * Gets a CPU matching @index.
 630  *
 631  * Returns: The CPU or %NULL if there is no matching CPU.
 632  */
 633 CPUState *qemu_get_cpu(int index);
 634
 635 /**
 636  * cpu_exists:
 637  * @id: Guest-exposed CPU ID to lookup.
 638  *
 639  * Search for CPU with specified ID.
 640  *
 641  * Returns: %true - CPU is found, %false - CPU isn't found.
 642  */
 643 bool cpu_exists(int64_t id);
 644
 645 /**
 646  * cpu_throttle_set:
 647  * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99.
 648  *
 649  * Throttles all vcpus by forcing them to sleep for the given percentage of
 650  * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly.
 651  * (example: 10ms sleep for every 30ms awake).
 652  *
 653  * cpu_throttle_set can be called as needed to adjust new_throttle_pct.
 654  * Once the throttling starts, it will remain in effect until cpu_throttle_stop
 655  * is called.
 656  */
 657 void cpu_throttle_set(int new_throttle_pct);
 658
 659 /**
 660  * cpu_throttle_stop:
 661  *
 662  * Stops the vcpu throttling started by cpu_throttle_set.
 663  */
 664 void cpu_throttle_stop(void);
 665
 666 /**
 667  * cpu_throttle_active:
 668  *
 669  * Returns: %true if the vcpus are currently being throttled, %false otherwise.
 670  */
 671 bool cpu_throttle_active(void);
 672
 673 /**
 674  * cpu_throttle_get_percentage:
 675  *
 676  * Returns the vcpu throttle percentage. See cpu_throttle_set for details.
 677  *
 678  * Returns: The throttle percentage in range 1 to 99.
 679  */
 680 int cpu_throttle_get_percentage(void);
 681
 682 #ifndef CONFIG_USER_ONLY
 683
 684 typedef void (*CPUInterruptHandler)(CPUState *, int);
 685
 686 extern CPUInterruptHandler cpu_interrupt_handler;
 687
 688 /**
 689  * cpu_interrupt:
 690  * @cpu: The CPU to set an interrupt on.
 691  * @mask: The interupts to set.
 692  *
 693  * Invokes the interrupt handler.
 694  */
 695 static inline void cpu_interrupt(CPUState *cpu, int mask)
 696 {
 697     cpu_interrupt_handler(cpu, mask);
 698 }
 699
 700 #else /* USER_ONLY */
 701
 702 void cpu_interrupt(CPUState *cpu, int mask);
 703
 704 #endif /* USER_ONLY */
 705
 706 #ifdef CONFIG_SOFTMMU
 707 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 708                                          bool is_write, bool is_exec,
 709                                          int opaque, unsigned size)
 710 {
 711     CPUClass *cc = CPU_GET_CLASS(cpu);
 712
 713     if (cc->do_unassigned_access) {
 714         cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
 715     }
 716 }
 717
 718 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
 719                                         int is_write, int is_user,
 720                                         uintptr_t retaddr)
 721 {
 722     CPUClass *cc = CPU_GET_CLASS(cpu);
 723
 724     cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
 725 }
 726 #endif
 727
 728 /**
 729  * cpu_set_pc:
 730  * @cpu: The CPU to set the program counter for.
 731  * @addr: Program counter value.
 732  *
 733  * Sets the program counter for a CPU.
 734  */
 735 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
 736 {
 737     CPUClass *cc = CPU_GET_CLASS(cpu);
 738
 739     cc->set_pc(cpu, addr);
 740 }
 741
 742 /**
 743  * cpu_reset_interrupt:
 744  * @cpu: The CPU to clear the interrupt on.
 745  * @mask: The interrupt mask to clear.
 746  *
 747  * Resets interrupts on the vCPU @cpu.
 748  */
 749 void cpu_reset_interrupt(CPUState *cpu, int mask);
 750
 751 /**
 752  * cpu_exit:
 753  * @cpu: The CPU to exit.
 754  *
 755  * Requests the CPU @cpu to exit execution.
 756  */
 757 void cpu_exit(CPUState *cpu);
 758
 759 /**
 760  * cpu_resume:
 761  * @cpu: The CPU to resume.
 762  *
 763  * Resumes CPU, i.e. puts CPU into runnable state.
 764  */
 765 void cpu_resume(CPUState *cpu);
 766
 767 /**
 768  * cpu_remove:
 769  * @cpu: The CPU to remove.
 770  *
 771  * Requests the CPU to be removed.
 772  */
 773 void cpu_remove(CPUState *cpu);
 774
 775  /**
 776  * cpu_remove_sync:
 777  * @cpu: The CPU to remove.
 778  *
 779  * Requests the CPU to be removed and waits till it is removed.
 780  */
 781 void cpu_remove_sync(CPUState *cpu);
 782
 783 /**
 784  * qemu_init_vcpu:
 785  * @cpu: The vCPU to initialize.
 786  *
 787  * Initializes a vCPU.
 788  */
 789 void qemu_init_vcpu(CPUState *cpu);
 790
 791 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 792 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 793 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 794
 795 /**
 796  * cpu_single_step:
 797  * @cpu: CPU to the flags for.
 798  * @enabled: Flags to enable.
 799  *
 800  * Enables or disables single-stepping for @cpu.
 801  */
 802 void cpu_single_step(CPUState *cpu, int enabled);
 803
 804 /* Breakpoint/watchpoint flags */
 805 #define BP_MEM_READ           0x01
 806 #define BP_MEM_WRITE          0x02
 807 #define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
 808 #define BP_STOP_BEFORE_ACCESS 0x04
 809 /* 0x08 currently unused */
 810 #define BP_GDB                0x10
 811 #define BP_CPU                0x20
 812 #define BP_ANY                (BP_GDB | BP_CPU)
 813 #define BP_WATCHPOINT_HIT_READ 0x40
 814 #define BP_WATCHPOINT_HIT_WRITE 0x80
 815 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
 816
 817 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
 818                           CPUBreakpoint **breakpoint);
 819 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
 820 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
 821 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
 822
 823 /* Return true if PC matches an installed breakpoint.  */
 824 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
 825 {
 826     CPUBreakpoint *bp;
 827
 828     if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
 829         QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
 830             if (bp->pc == pc && (bp->flags & mask)) {
 831                 return true;
 832             }
 833         }
 834     }
 835     return false;
 836 }
 837
 838 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
 839                           int flags, CPUWatchpoint **watchpoint);
 840 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
 841                           vaddr len, int flags);
 842 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
 843 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
 844
 845 /**
 846  * cpu_get_address_space:
 847  * @cpu: CPU to get address space from
 848  * @asidx: index identifying which address space to get
 849  *
 850  * Return the requested address space of this CPU. @asidx
 851  * specifies which address space to read.
 852  */
 853 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
 854
 855 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
 856     GCC_FMT_ATTR(2, 3);
 857 void cpu_exec_exit(CPUState *cpu);
 858
 859 #ifdef CONFIG_SOFTMMU
 860 extern const struct VMStateDescription vmstate_cpu_common;
 861 #else
 862 #define vmstate_cpu_common vmstate_dummy
 863 #endif
 864
 865 #define VMSTATE_CPU() {                                                     \
 866     .name = "parent_obj",                                                   \
 867     .size = sizeof(CPUState),                                               \
 868     .vmsd = &vmstate_cpu_common,                                            \
 869     .flags = VMS_STRUCT,                                                    \
 870     .offset = 0,                                                            \
 871 }
 872
 873 #endif