include/soc/fsl/qe/qe_ic.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
   4  *
   5  * Authors:     Shlomi Gridish <gridish@freescale.com>
   6  *              Li Yang <leoli@freescale.com>
   7  *
   8  * Description:
   9  * QE IC external definitions and structure.
  10  */
  11 #ifndef _ASM_POWERPC_QE_IC_H
  12 #define _ASM_POWERPC_QE_IC_H
  13
  14 #include <linux/irq.h>
  15
  16 struct device_node;
  17 struct qe_ic;
  18
  19 #define NUM_OF_QE_IC_GROUPS     6
  20
  21 /* Flags when we init the QE IC */
  22 #define QE_IC_SPREADMODE_GRP_W                  0x00000001
  23 #define QE_IC_SPREADMODE_GRP_X                  0x00000002
  24 #define QE_IC_SPREADMODE_GRP_Y                  0x00000004
  25 #define QE_IC_SPREADMODE_GRP_Z                  0x00000008
  26 #define QE_IC_SPREADMODE_GRP_RISCA              0x00000010
  27 #define QE_IC_SPREADMODE_GRP_RISCB              0x00000020
  28
  29 #define QE_IC_LOW_SIGNAL                        0x00000100
  30 #define QE_IC_HIGH_SIGNAL                       0x00000200
  31
  32 #define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH       0x00001000
  33 #define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH       0x00002000
  34 #define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH       0x00004000
  35 #define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH       0x00008000
  36 #define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH       0x00010000
  37 #define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH       0x00020000
  38 #define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH       0x00040000
  39 #define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH       0x00080000
  40 #define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH   0x00100000
  41 #define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH   0x00200000
  42 #define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH   0x00400000
  43 #define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH   0x00800000
  44 #define QE_IC_GRP_W_DEST_SIGNAL_SHIFT           (12)
  45
  46 /* QE interrupt sources groups */
  47 enum qe_ic_grp_id {
  48         QE_IC_GRP_W = 0,        /* QE interrupt controller group W */
  49         QE_IC_GRP_X,            /* QE interrupt controller group X */
  50         QE_IC_GRP_Y,            /* QE interrupt controller group Y */
  51         QE_IC_GRP_Z,            /* QE interrupt controller group Z */
  52         QE_IC_GRP_RISCA,        /* QE interrupt controller RISC group A */
  53         QE_IC_GRP_RISCB         /* QE interrupt controller RISC group B */
  54 };
  55
  56 #ifdef CONFIG_QUICC_ENGINE
  57 void qe_ic_init(struct device_node *node, unsigned int flags,
  58                 void (*low_handler)(struct irq_desc *desc),
  59                 void (*high_handler)(struct irq_desc *desc));
  60 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
  61 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
  62 #else
  63 static inline void qe_ic_init(struct device_node *node, unsigned int flags,
  64                 void (*low_handler)(struct irq_desc *desc),
  65                 void (*high_handler)(struct irq_desc *desc))
  66 {}
  67 static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
  68 { return 0; }
  69 static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
  70 { return 0; }
  71 #endif /* CONFIG_QUICC_ENGINE */
  72
  73 void qe_ic_set_highest_priority(unsigned int virq, int high);
  74 int qe_ic_set_priority(unsigned int virq, unsigned int priority);
  75 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
  76
  77 static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
  78 {
  79         struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
  80         unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
  81
  82         if (cascade_irq != NO_IRQ)
  83                 generic_handle_irq(cascade_irq);
  84 }
  85
  86 static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
  87 {
  88         struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
  89         unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
  90
  91         if (cascade_irq != NO_IRQ)
  92                 generic_handle_irq(cascade_irq);
  93 }
  94
  95 static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
  96 {
  97         struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
  98         unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
  99         struct irq_chip *chip = irq_desc_get_chip(desc);
 100
 101         if (cascade_irq != NO_IRQ)
 102                 generic_handle_irq(cascade_irq);
 103
 104         chip->irq_eoi(&desc->irq_data);
 105 }
 106
 107 static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
 108 {
 109         struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 110         unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
 111         struct irq_chip *chip = irq_desc_get_chip(desc);
 112
 113         if (cascade_irq != NO_IRQ)
 114                 generic_handle_irq(cascade_irq);
 115
 116         chip->irq_eoi(&desc->irq_data);
 117 }
 118
 119 static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
 120 {
 121         struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
 122         unsigned int cascade_irq;
 123         struct irq_chip *chip = irq_desc_get_chip(desc);
 124
 125         cascade_irq = qe_ic_get_high_irq(qe_ic);
 126         if (cascade_irq == NO_IRQ)
 127                 cascade_irq = qe_ic_get_low_irq(qe_ic);
 128
 129         if (cascade_irq != NO_IRQ)
 130                 generic_handle_irq(cascade_irq);
 131
 132         chip->irq_eoi(&desc->irq_data);
 133 }
 134
 135 #endif /* _ASM_POWERPC_QE_IC_H */