1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
14 /* Port Group IDs (PGID) are masks of destination ports.
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
53 /* Reserve some destination PGIDs at the end of the range:
54 * PGID_BLACKHOLE: used for not forwarding the frames
55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
56 * of the switch port net devices, towards the CPU port module.
57 * PGID_UC: the flooding destinations for unknown unicast traffic.
58 * PGID_MC: the flooding destinations for non-IP multicast traffic.
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
61 * PGID_BC: the flooding destinations for broadcast traffic.
63 #define PGID_BLACKHOLE 57
67 #define PGID_MCIPV4 61
68 #define PGID_MCIPV6 62
71 #define for_each_unicast_dest_pgid(ocelot, pgid) \
73 (pgid) < (ocelot)->num_phys_ports; \
76 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
77 for ((pgid) = (ocelot)->num_phys_ports + 1; \
78 (pgid) < PGID_BLACKHOLE; \
81 #define for_each_aggr_pgid(ocelot, pgid) \
82 for ((pgid) = PGID_AGGR; \
86 /* Aggregation PGIDs, one per Link Aggregation Code */
89 /* Source PGIDs, one per physical port */
92 #define IFH_TAG_TYPE_C 0
93 #define IFH_TAG_TYPE_S 1
95 #define IFH_REW_OP_NOOP 0x0
96 #define IFH_REW_OP_DSCP 0x1
97 #define IFH_REW_OP_ONE_STEP_PTP 0x2
98 #define IFH_REW_OP_TWO_STEP_PTP 0x3
99 #define IFH_REW_OP_ORIGIN_PTP 0x5
101 #define OCELOT_NUM_TC 8
103 #define OCELOT_SPEED_2500 0
104 #define OCELOT_SPEED_1000 1
105 #define OCELOT_SPEED_100 2
106 #define OCELOT_SPEED_10 3
108 #define OCELOT_PTP_PINS_NUM 4
110 #define TARGET_OFFSET 24
111 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
112 #define REG(reg, offset) [reg & REG_MASK] = offset
114 #define REG_RESERVED_ADDR 0xffffffff
115 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
117 #define OCELOT_MRP_CPUQ 7
136 ANA_ADVLEARN
= ANA
<< TARGET_OFFSET
,
141 ANA_STORMLIMIT_BURST
,
160 ANA_TABLES_STREAMDATA
,
161 ANA_TABLES_MACACCESS
,
163 ANA_TABLES_VLANACCESS
,
165 ANA_TABLES_ISDXACCESS
,
168 ANA_TABLES_PTP_ID_HIGH
,
169 ANA_TABLES_PTP_ID_LOW
,
170 ANA_TABLES_STREAMACCESS
,
171 ANA_TABLES_STREAMTIDX
,
172 ANA_TABLES_SEQ_HISTORY
,
174 ANA_TABLES_SFID_MASK
,
175 ANA_TABLES_SFIDACCESS
,
185 ANA_SG_GCL_GS_CONFIG
,
186 ANA_SG_GCL_TI_CONFIG
,
194 ANA_PORT_VCAP_S1_KEY_CFG
,
195 ANA_PORT_VCAP_S2_CFG
,
196 ANA_PORT_PCP_DEI_MAP
,
197 ANA_PORT_CPU_FWD_CFG
,
198 ANA_PORT_CPU_FWD_BPDU_CFG
,
199 ANA_PORT_CPU_FWD_GARP_CFG
,
200 ANA_PORT_CPU_FWD_CCM_CFG
,
204 ANA_PORT_PTP_DLY1_CFG
,
205 ANA_PORT_PTP_DLY2_CFG
,
219 ANA_VCAP_RNG_TYPE_CFG
,
220 ANA_VCAP_RNG_VAL_CFG
,
235 QS_XTR_GRP_CFG
= QS
<< TARGET_OFFSET
,
247 QSYS_PORT_MODE
= QSYS
<< TARGET_OFFSET
,
248 QSYS_SWITCH_PORT_MODE
,
260 QSYS_TIMED_FRAME_ENTRY
,
263 QSYS_TFRM_TIMER_CFG_1
,
264 QSYS_TFRM_TIMER_CFG_2
,
265 QSYS_TFRM_TIMER_CFG_3
,
266 QSYS_TFRM_TIMER_CFG_4
,
267 QSYS_TFRM_TIMER_CFG_5
,
268 QSYS_TFRM_TIMER_CFG_6
,
269 QSYS_TFRM_TIMER_CFG_7
,
270 QSYS_TFRM_TIMER_CFG_8
,
298 QSYS_TAS_PARAM_CFG_CTRL
,
300 QSYS_PARAM_CFG_REG_1
,
301 QSYS_PARAM_CFG_REG_2
,
302 QSYS_PARAM_CFG_REG_3
,
303 QSYS_PARAM_CFG_REG_4
,
304 QSYS_PARAM_CFG_REG_5
,
307 QSYS_PARAM_STATUS_REG_1
,
308 QSYS_PARAM_STATUS_REG_2
,
309 QSYS_PARAM_STATUS_REG_3
,
310 QSYS_PARAM_STATUS_REG_4
,
311 QSYS_PARAM_STATUS_REG_5
,
312 QSYS_PARAM_STATUS_REG_6
,
313 QSYS_PARAM_STATUS_REG_7
,
314 QSYS_PARAM_STATUS_REG_8
,
315 QSYS_PARAM_STATUS_REG_9
,
316 QSYS_GCL_STATUS_REG_1
,
317 QSYS_GCL_STATUS_REG_2
,
318 REW_PORT_VLAN_CFG
= REW
<< TARGET_OFFSET
,
322 REW_PCP_DEI_QOS_MAP_CFG
,
326 REW_DSCP_REMAP_DP1_CFG
,
331 SYS_COUNT_RX_OCTETS
= SYS
<< TARGET_OFFSET
,
332 SYS_COUNT_RX_UNICAST
,
333 SYS_COUNT_RX_MULTICAST
,
334 SYS_COUNT_RX_BROADCAST
,
336 SYS_COUNT_RX_FRAGMENTS
,
337 SYS_COUNT_RX_JABBERS
,
338 SYS_COUNT_RX_CRC_ALIGN_ERRS
,
339 SYS_COUNT_RX_SYM_ERRS
,
342 SYS_COUNT_RX_128_255
,
343 SYS_COUNT_RX_256_1023
,
344 SYS_COUNT_RX_1024_1526
,
345 SYS_COUNT_RX_1527_MAX
,
347 SYS_COUNT_RX_CONTROL
,
349 SYS_COUNT_RX_CLASSIFIED_DROPS
,
351 SYS_COUNT_TX_UNICAST
,
352 SYS_COUNT_TX_MULTICAST
,
353 SYS_COUNT_TX_BROADCAST
,
354 SYS_COUNT_TX_COLLISION
,
359 SYS_COUNT_TX_128_511
,
360 SYS_COUNT_TX_512_1023
,
361 SYS_COUNT_TX_1024_1526
,
362 SYS_COUNT_TX_1527_MAX
,
373 SYS_REW_MAC_HIGH_CFG
,
375 SYS_TIMESTAMP_OFFSET
,
397 PTP_PIN_CFG
= PTP
<< TARGET_OFFSET
,
401 PTP_PIN_WF_HIGH_PERIOD
,
402 PTP_PIN_WF_LOW_PERIOD
,
405 PTP_CLK_CFG_ADJ_FREQ
,
406 GCB_SOFT_RST
= GCB
<< TARGET_OFFSET
,
410 DEV_CLOCK_CFG
= DEV_GMII
<< TARGET_OFFSET
,
425 DEV_MAC_FC_MAC_LOW_CFG
,
426 DEV_MAC_FC_MAC_HIGH_CFG
,
437 PCS1G_ANEG_NP_STATUS
,
443 PCS1G_LPI_WAKE_ERROR_CNT
,
445 PCS1G_TSTPAT_MODE_CFG
,
448 DEV_PCS_FX100_STATUS
,
451 enum ocelot_regfield
{
452 ANA_ADVLEARN_VLAN_CHK
,
453 ANA_ADVLEARN_LEARN_MIRROR
,
454 ANA_ANEVENTS_FLOOD_DISCARD
,
455 ANA_ANEVENTS_MSTI_DROP
,
456 ANA_ANEVENTS_ACLKILL
,
457 ANA_ANEVENTS_ACLUSED
,
458 ANA_ANEVENTS_AUTOAGE
,
459 ANA_ANEVENTS_VS2TTL1
,
460 ANA_ANEVENTS_STORM_DROP
,
461 ANA_ANEVENTS_LEARN_DROP
,
462 ANA_ANEVENTS_AGED_ENTRY
,
463 ANA_ANEVENTS_CPU_LEARN_FAILED
,
464 ANA_ANEVENTS_AUTO_LEARN_FAILED
,
465 ANA_ANEVENTS_LEARN_REMOVE
,
466 ANA_ANEVENTS_AUTO_LEARNED
,
467 ANA_ANEVENTS_AUTO_MOVED
,
468 ANA_ANEVENTS_DROPPED
,
469 ANA_ANEVENTS_CLASSIFIED_DROP
,
470 ANA_ANEVENTS_CLASSIFIED_COPY
,
471 ANA_ANEVENTS_VLAN_DISCARD
,
472 ANA_ANEVENTS_FWD_DISCARD
,
473 ANA_ANEVENTS_MULTICAST_FLOOD
,
474 ANA_ANEVENTS_UNICAST_FLOOD
,
475 ANA_ANEVENTS_DEST_KNOWN
,
476 ANA_ANEVENTS_BUCKET3_MATCH
,
477 ANA_ANEVENTS_BUCKET2_MATCH
,
478 ANA_ANEVENTS_BUCKET1_MATCH
,
479 ANA_ANEVENTS_BUCKET0_MATCH
,
480 ANA_ANEVENTS_CPU_OPERATION
,
481 ANA_ANEVENTS_DMAC_LOOKUP
,
482 ANA_ANEVENTS_SMAC_LOOKUP
,
483 ANA_ANEVENTS_SEQ_GEN_ERR_0
,
484 ANA_ANEVENTS_SEQ_GEN_ERR_1
,
485 ANA_TABLES_MACACCESS_B_DOM
,
486 ANA_TABLES_MACTINDX_BUCKET
,
487 ANA_TABLES_MACTINDX_M_INDEX
,
488 QSYS_SWITCH_PORT_MODE_PORT_ENA
,
489 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG
,
490 QSYS_SWITCH_PORT_MODE_YEL_RSRVD
,
491 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE
,
492 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA
,
493 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE
,
494 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD
,
495 QSYS_TIMED_FRAME_ENTRY_TFRM_FP
,
496 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO
,
497 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL
,
498 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T
,
499 SYS_PORT_MODE_DATA_WO_TS
,
500 SYS_PORT_MODE_INCL_INJ_HDR
,
501 SYS_PORT_MODE_INCL_XTR_HDR
,
502 SYS_PORT_MODE_INCL_HDR_ERR
,
503 SYS_RESET_CFG_CORE_ENA
,
504 SYS_RESET_CFG_MEM_ENA
,
505 SYS_RESET_CFG_MEM_INIT
,
506 GCB_SOFT_RST_SWC_RST
,
507 GCB_MIIM_MII_STATUS_PENDING
,
508 GCB_MIIM_MII_STATUS_BUSY
,
509 SYS_PAUSE_CFG_PAUSE_START
,
510 SYS_PAUSE_CFG_PAUSE_STOP
,
511 SYS_PAUSE_CFG_PAUSE_ENA
,
517 VCAP_CORE_UPDATE_CTRL
,
519 /* VCAP_CORE_CACHE */
520 VCAP_CACHE_ENTRY_DAT
,
522 VCAP_CACHE_ACTION_DAT
,
527 VCAP_CONST_ENTRY_WIDTH
,
528 VCAP_CONST_ENTRY_CNT
,
529 VCAP_CONST_ENTRY_SWCNT
,
530 VCAP_CONST_ENTRY_TG_WIDTH
,
531 VCAP_CONST_ACTION_DEF_CNT
,
532 VCAP_CONST_ACTION_WIDTH
,
533 VCAP_CONST_CNT_WIDTH
,
538 enum ocelot_ptp_pins
{
546 struct ocelot_stat_layout
{
548 char name
[ETH_GSTRING_LEN
];
551 enum ocelot_tag_prefix
{
552 OCELOT_TAG_PREFIX_DISABLED
= 0,
553 OCELOT_TAG_PREFIX_NONE
,
554 OCELOT_TAG_PREFIX_SHORT
,
555 OCELOT_TAG_PREFIX_LONG
,
561 struct net_device
*(*port_to_netdev
)(struct ocelot
*ocelot
, int port
);
562 int (*netdev_to_port
)(struct net_device
*dev
);
563 int (*reset
)(struct ocelot
*ocelot
);
564 u16 (*wm_enc
)(u16 value
);
565 u16 (*wm_dec
)(u16 value
);
566 void (*wm_stat
)(u32 val
, u32
*inuse
, u32
*maxuse
);
569 struct ocelot_vcap_block
{
570 struct list_head rules
;
586 enum ocelot_sb_pool
{
592 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0)
593 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1)
596 struct ocelot
*ocelot
;
598 struct regmap
*target
;
601 /* VLAN that untagged frames are classified to, on ingress */
602 struct ocelot_vlan pvid_vlan
;
603 /* The VLAN ID that will be transmitted as untagged, on egress */
604 struct ocelot_vlan native_vlan
;
607 struct sk_buff_head tx_skbs
;
609 spinlock_t ts_id_lock
;
611 phy_interface_t phy_mode
;
614 bool is_dsa_8021q_cpu
;
617 struct net_device
*bond
;
622 struct net_device
*bridge
;
628 struct devlink
*devlink
;
629 struct devlink_port
*devlink_ports
;
631 const struct ocelot_ops
*ops
;
632 struct regmap
*targets
[TARGET_MAX
];
633 struct regmap_field
*regfields
[REGFIELD_MAX
];
634 const u32
*const *map
;
635 const struct ocelot_stat_layout
*stats_layout
;
636 unsigned int num_stats
;
638 u32 pool_size
[OCELOT_SB_NUM
][OCELOT_SB_POOL_NUM
];
639 int packet_buffer_size
;
643 struct ocelot_port
**ports
;
645 u8 base_mac
[ETH_ALEN
];
647 /* Keep track of the vlan port masks */
648 u32 vlan_mask
[VLAN_N_VID
];
650 /* Switches like VSC9959 have flooding per traffic class */
651 int num_flooding_pgids
;
653 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
654 * the CPU is located after the physical ports (at the
655 * num_phys_ports index).
661 enum ocelot_tag_prefix npi_inj_prefix
;
662 enum ocelot_tag_prefix npi_xtr_prefix
;
664 struct list_head multicast
;
665 struct list_head pgids
;
667 struct list_head dummy_rules
;
668 struct ocelot_vcap_block block
[3];
669 struct vcap_props
*vcap
;
671 /* Workqueue to check statistics for overflow with its lock */
672 struct mutex stats_lock
;
674 struct delayed_work stats_work
;
675 struct workqueue_struct
*stats_queue
;
677 struct workqueue_struct
*owq
;
680 struct ptp_clock
*ptp_clock
;
681 struct ptp_clock_info ptp_info
;
682 struct hwtstamp_config hwtstamp_config
;
683 /* Protects the PTP interface state */
684 struct mutex ptp_lock
;
685 /* Protects the PTP clock */
686 spinlock_t ptp_clock_lock
;
687 struct ptp_pin_desc ptp_pins
[OCELOT_PTP_PINS_NUM
];
690 struct ocelot_policer
{
691 u32 rate
; /* kilobit per second */
692 u32 burst
; /* bytes */
695 struct ocelot_skb_cb
{
696 struct sk_buff
*clone
;
701 #define OCELOT_SKB_CB(skb) \
702 ((struct ocelot_skb_cb *)((skb)->cb))
704 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
705 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
706 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
707 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
709 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
710 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
711 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
712 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
714 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
715 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
716 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
717 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
719 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
720 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
721 #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
722 #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
724 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
725 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
726 #define ocelot_target_read_gix(ocelot, target, reg, gi) \
727 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
728 #define ocelot_target_read_rix(ocelot, target, reg, ri) \
729 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
730 #define ocelot_target_read(ocelot, target, reg) \
731 __ocelot_target_read_ix(ocelot, target, reg, 0)
733 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
734 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
735 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
736 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
737 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
738 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
739 #define ocelot_target_write(ocelot, target, val, reg) \
740 __ocelot_target_write_ix(ocelot, target, val, reg, 0)
743 u32
ocelot_port_readl(struct ocelot_port
*port
, u32 reg
);
744 void ocelot_port_writel(struct ocelot_port
*port
, u32 val
, u32 reg
);
745 void ocelot_port_rmwl(struct ocelot_port
*port
, u32 val
, u32 mask
, u32 reg
);
746 u32
__ocelot_read_ix(struct ocelot
*ocelot
, u32 reg
, u32 offset
);
747 void __ocelot_write_ix(struct ocelot
*ocelot
, u32 val
, u32 reg
, u32 offset
);
748 void __ocelot_rmw_ix(struct ocelot
*ocelot
, u32 val
, u32 mask
, u32 reg
,
750 u32
__ocelot_target_read_ix(struct ocelot
*ocelot
, enum ocelot_target target
,
751 u32 reg
, u32 offset
);
752 void __ocelot_target_write_ix(struct ocelot
*ocelot
, enum ocelot_target target
,
753 u32 val
, u32 reg
, u32 offset
);
755 #if IS_ENABLED(CONFIG_MSCC_OCELOT_SWITCH_LIB)
758 bool ocelot_can_inject(struct ocelot
*ocelot
, int grp
);
759 void ocelot_port_inject_frame(struct ocelot
*ocelot
, int port
, int grp
,
760 u32 rew_op
, struct sk_buff
*skb
);
761 int ocelot_xtr_poll_frame(struct ocelot
*ocelot
, int grp
, struct sk_buff
**skb
);
762 void ocelot_drain_cpu_queue(struct ocelot
*ocelot
, int grp
);
764 u32
ocelot_ptp_rew_op(struct sk_buff
*skb
);
767 static inline bool ocelot_can_inject(struct ocelot
*ocelot
, int grp
)
772 static inline void ocelot_port_inject_frame(struct ocelot
*ocelot
, int port
,
778 static inline int ocelot_xtr_poll_frame(struct ocelot
*ocelot
, int grp
,
779 struct sk_buff
**skb
)
784 static inline void ocelot_drain_cpu_queue(struct ocelot
*ocelot
, int grp
)
788 static inline u32
ocelot_ptp_rew_op(struct sk_buff
*skb
)
794 /* Hardware initialization */
795 int ocelot_regfields_init(struct ocelot
*ocelot
,
796 const struct reg_field
*const regfields
);
797 struct regmap
*ocelot_regmap_init(struct ocelot
*ocelot
, struct resource
*res
);
798 int ocelot_init(struct ocelot
*ocelot
);
799 void ocelot_deinit(struct ocelot
*ocelot
);
800 void ocelot_init_port(struct ocelot
*ocelot
, int port
);
801 void ocelot_deinit_port(struct ocelot
*ocelot
, int port
);
804 void ocelot_get_strings(struct ocelot
*ocelot
, int port
, u32 sset
, u8
*data
);
805 void ocelot_get_ethtool_stats(struct ocelot
*ocelot
, int port
, u64
*data
);
806 int ocelot_get_sset_count(struct ocelot
*ocelot
, int port
, int sset
);
807 int ocelot_get_ts_info(struct ocelot
*ocelot
, int port
,
808 struct ethtool_ts_info
*info
);
809 void ocelot_set_ageing_time(struct ocelot
*ocelot
, unsigned int msecs
);
810 int ocelot_port_vlan_filtering(struct ocelot
*ocelot
, int port
, bool enabled
);
811 void ocelot_bridge_stp_state_set(struct ocelot
*ocelot
, int port
, u8 state
);
812 void ocelot_apply_bridge_fwd_mask(struct ocelot
*ocelot
);
813 int ocelot_port_pre_bridge_flags(struct ocelot
*ocelot
, int port
,
814 struct switchdev_brport_flags val
);
815 void ocelot_port_bridge_flags(struct ocelot
*ocelot
, int port
,
816 struct switchdev_brport_flags val
);
817 void ocelot_port_bridge_join(struct ocelot
*ocelot
, int port
,
818 struct net_device
*bridge
);
819 void ocelot_port_bridge_leave(struct ocelot
*ocelot
, int port
,
820 struct net_device
*bridge
);
821 int ocelot_fdb_dump(struct ocelot
*ocelot
, int port
,
822 dsa_fdb_dump_cb_t
*cb
, void *data
);
823 int ocelot_fdb_add(struct ocelot
*ocelot
, int port
,
824 const unsigned char *addr
, u16 vid
);
825 int ocelot_fdb_del(struct ocelot
*ocelot
, int port
,
826 const unsigned char *addr
, u16 vid
);
827 int ocelot_vlan_prepare(struct ocelot
*ocelot
, int port
, u16 vid
, bool pvid
,
828 bool untagged
, struct netlink_ext_ack
*extack
);
829 int ocelot_vlan_add(struct ocelot
*ocelot
, int port
, u16 vid
, bool pvid
,
831 int ocelot_vlan_del(struct ocelot
*ocelot
, int port
, u16 vid
);
832 int ocelot_hwstamp_get(struct ocelot
*ocelot
, int port
, struct ifreq
*ifr
);
833 int ocelot_hwstamp_set(struct ocelot
*ocelot
, int port
, struct ifreq
*ifr
);
834 int ocelot_port_txtstamp_request(struct ocelot
*ocelot
, int port
,
836 struct sk_buff
**clone
);
837 void ocelot_get_txtstamp(struct ocelot
*ocelot
);
838 void ocelot_port_set_maxlen(struct ocelot
*ocelot
, int port
, size_t sdu
);
839 int ocelot_get_max_mtu(struct ocelot
*ocelot
, int port
);
840 int ocelot_port_policer_add(struct ocelot
*ocelot
, int port
,
841 struct ocelot_policer
*pol
);
842 int ocelot_port_policer_del(struct ocelot
*ocelot
, int port
);
843 int ocelot_cls_flower_replace(struct ocelot
*ocelot
, int port
,
844 struct flow_cls_offload
*f
, bool ingress
);
845 int ocelot_cls_flower_destroy(struct ocelot
*ocelot
, int port
,
846 struct flow_cls_offload
*f
, bool ingress
);
847 int ocelot_cls_flower_stats(struct ocelot
*ocelot
, int port
,
848 struct flow_cls_offload
*f
, bool ingress
);
849 int ocelot_port_mdb_add(struct ocelot
*ocelot
, int port
,
850 const struct switchdev_obj_port_mdb
*mdb
);
851 int ocelot_port_mdb_del(struct ocelot
*ocelot
, int port
,
852 const struct switchdev_obj_port_mdb
*mdb
);
853 int ocelot_port_lag_join(struct ocelot
*ocelot
, int port
,
854 struct net_device
*bond
,
855 struct netdev_lag_upper_info
*info
);
856 void ocelot_port_lag_leave(struct ocelot
*ocelot
, int port
,
857 struct net_device
*bond
);
858 void ocelot_port_lag_change(struct ocelot
*ocelot
, int port
, bool lag_tx_active
);
860 int ocelot_devlink_sb_register(struct ocelot
*ocelot
);
861 void ocelot_devlink_sb_unregister(struct ocelot
*ocelot
);
862 int ocelot_sb_pool_get(struct ocelot
*ocelot
, unsigned int sb_index
,
864 struct devlink_sb_pool_info
*pool_info
);
865 int ocelot_sb_pool_set(struct ocelot
*ocelot
, unsigned int sb_index
,
866 u16 pool_index
, u32 size
,
867 enum devlink_sb_threshold_type threshold_type
,
868 struct netlink_ext_ack
*extack
);
869 int ocelot_sb_port_pool_get(struct ocelot
*ocelot
, int port
,
870 unsigned int sb_index
, u16 pool_index
,
872 int ocelot_sb_port_pool_set(struct ocelot
*ocelot
, int port
,
873 unsigned int sb_index
, u16 pool_index
,
874 u32 threshold
, struct netlink_ext_ack
*extack
);
875 int ocelot_sb_tc_pool_bind_get(struct ocelot
*ocelot
, int port
,
876 unsigned int sb_index
, u16 tc_index
,
877 enum devlink_sb_pool_type pool_type
,
878 u16
*p_pool_index
, u32
*p_threshold
);
879 int ocelot_sb_tc_pool_bind_set(struct ocelot
*ocelot
, int port
,
880 unsigned int sb_index
, u16 tc_index
,
881 enum devlink_sb_pool_type pool_type
,
882 u16 pool_index
, u32 threshold
,
883 struct netlink_ext_ack
*extack
);
884 int ocelot_sb_occ_snapshot(struct ocelot
*ocelot
, unsigned int sb_index
);
885 int ocelot_sb_occ_max_clear(struct ocelot
*ocelot
, unsigned int sb_index
);
886 int ocelot_sb_occ_port_pool_get(struct ocelot
*ocelot
, int port
,
887 unsigned int sb_index
, u16 pool_index
,
888 u32
*p_cur
, u32
*p_max
);
889 int ocelot_sb_occ_tc_port_bind_get(struct ocelot
*ocelot
, int port
,
890 unsigned int sb_index
, u16 tc_index
,
891 enum devlink_sb_pool_type pool_type
,
892 u32
*p_cur
, u32
*p_max
);
894 void ocelot_phylink_mac_link_down(struct ocelot
*ocelot
, int port
,
895 unsigned int link_an_mode
,
896 phy_interface_t interface
,
897 unsigned long quirks
);
898 void ocelot_phylink_mac_link_up(struct ocelot
*ocelot
, int port
,
899 struct phy_device
*phydev
,
900 unsigned int link_an_mode
,
901 phy_interface_t interface
,
902 int speed
, int duplex
,
903 bool tx_pause
, bool rx_pause
,
904 unsigned long quirks
);
906 #if IS_ENABLED(CONFIG_BRIDGE_MRP)
907 int ocelot_mrp_add(struct ocelot
*ocelot
, int port
,
908 const struct switchdev_obj_mrp
*mrp
);
909 int ocelot_mrp_del(struct ocelot
*ocelot
, int port
,
910 const struct switchdev_obj_mrp
*mrp
);
911 int ocelot_mrp_add_ring_role(struct ocelot
*ocelot
, int port
,
912 const struct switchdev_obj_ring_role_mrp
*mrp
);
913 int ocelot_mrp_del_ring_role(struct ocelot
*ocelot
, int port
,
914 const struct switchdev_obj_ring_role_mrp
*mrp
);
916 static inline int ocelot_mrp_add(struct ocelot
*ocelot
, int port
,
917 const struct switchdev_obj_mrp
*mrp
)
922 static inline int ocelot_mrp_del(struct ocelot
*ocelot
, int port
,
923 const struct switchdev_obj_mrp
*mrp
)
929 ocelot_mrp_add_ring_role(struct ocelot
*ocelot
, int port
,
930 const struct switchdev_obj_ring_role_mrp
*mrp
)
936 ocelot_mrp_del_ring_role(struct ocelot
*ocelot
, int port
,
937 const struct switchdev_obj_ring_role_mrp
*mrp
)