2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "exec/memop.h"
29 #include "exec/memopidx.h"
30 #include "qemu/bitops.h"
31 #include "qemu/plugin.h"
32 #include "qemu/queue.h"
33 #include "tcg/tcg-mo.h"
34 #include "tcg-target-reg-bits.h"
35 #include "tcg-target.h"
36 #include "tcg/tcg-cond.h"
37 #include "tcg/debug-assert.h"
39 /* XXX: make safe guess about sizes */
40 #define MAX_OP_PER_INSTR 266
42 #define MAX_CALL_IARGS 7
44 #define CPU_TEMP_BUF_NLONGS 128
45 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long))
47 #if TCG_TARGET_REG_BITS == 32
48 typedef int32_t tcg_target_long
;
49 typedef uint32_t tcg_target_ulong
;
50 #define TCG_PRIlx PRIx32
51 #define TCG_PRIld PRId32
52 #elif TCG_TARGET_REG_BITS == 64
53 typedef int64_t tcg_target_long
;
54 typedef uint64_t tcg_target_ulong
;
55 #define TCG_PRIlx PRIx64
56 #define TCG_PRIld PRId64
61 #if TCG_TARGET_NB_REGS <= 32
62 typedef uint32_t TCGRegSet
;
63 #elif TCG_TARGET_NB_REGS <= 64
64 typedef uint64_t TCGRegSet
;
69 #if TCG_TARGET_REG_BITS == 32
70 /* Turn some undef macros into false macros. */
71 #define TCG_TARGET_HAS_extrl_i64_i32 0
72 #define TCG_TARGET_HAS_extrh_i64_i32 0
73 #define TCG_TARGET_HAS_div_i64 0
74 #define TCG_TARGET_HAS_rem_i64 0
75 #define TCG_TARGET_HAS_div2_i64 0
76 #define TCG_TARGET_HAS_rot_i64 0
77 #define TCG_TARGET_HAS_ext8s_i64 0
78 #define TCG_TARGET_HAS_ext16s_i64 0
79 #define TCG_TARGET_HAS_ext32s_i64 0
80 #define TCG_TARGET_HAS_ext8u_i64 0
81 #define TCG_TARGET_HAS_ext16u_i64 0
82 #define TCG_TARGET_HAS_ext32u_i64 0
83 #define TCG_TARGET_HAS_bswap16_i64 0
84 #define TCG_TARGET_HAS_bswap32_i64 0
85 #define TCG_TARGET_HAS_bswap64_i64 0
86 #define TCG_TARGET_HAS_neg_i64 0
87 #define TCG_TARGET_HAS_not_i64 0
88 #define TCG_TARGET_HAS_andc_i64 0
89 #define TCG_TARGET_HAS_orc_i64 0
90 #define TCG_TARGET_HAS_eqv_i64 0
91 #define TCG_TARGET_HAS_nand_i64 0
92 #define TCG_TARGET_HAS_nor_i64 0
93 #define TCG_TARGET_HAS_clz_i64 0
94 #define TCG_TARGET_HAS_ctz_i64 0
95 #define TCG_TARGET_HAS_ctpop_i64 0
96 #define TCG_TARGET_HAS_deposit_i64 0
97 #define TCG_TARGET_HAS_extract_i64 0
98 #define TCG_TARGET_HAS_sextract_i64 0
99 #define TCG_TARGET_HAS_extract2_i64 0
100 #define TCG_TARGET_HAS_movcond_i64 0
101 #define TCG_TARGET_HAS_add2_i64 0
102 #define TCG_TARGET_HAS_sub2_i64 0
103 #define TCG_TARGET_HAS_mulu2_i64 0
104 #define TCG_TARGET_HAS_muls2_i64 0
105 #define TCG_TARGET_HAS_muluh_i64 0
106 #define TCG_TARGET_HAS_mulsh_i64 0
107 /* Turn some undef macros into true macros. */
108 #define TCG_TARGET_HAS_add2_i32 1
109 #define TCG_TARGET_HAS_sub2_i32 1
112 #ifndef TCG_TARGET_deposit_i32_valid
113 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
115 #ifndef TCG_TARGET_deposit_i64_valid
116 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
118 #ifndef TCG_TARGET_extract_i32_valid
119 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
121 #ifndef TCG_TARGET_extract_i64_valid
122 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
125 /* Only one of DIV or DIV2 should be defined. */
126 #if defined(TCG_TARGET_HAS_div_i32)
127 #define TCG_TARGET_HAS_div2_i32 0
128 #elif defined(TCG_TARGET_HAS_div2_i32)
129 #define TCG_TARGET_HAS_div_i32 0
130 #define TCG_TARGET_HAS_rem_i32 0
132 #if defined(TCG_TARGET_HAS_div_i64)
133 #define TCG_TARGET_HAS_div2_i64 0
134 #elif defined(TCG_TARGET_HAS_div2_i64)
135 #define TCG_TARGET_HAS_div_i64 0
136 #define TCG_TARGET_HAS_rem_i64 0
139 #if !defined(TCG_TARGET_HAS_v64) \
140 && !defined(TCG_TARGET_HAS_v128) \
141 && !defined(TCG_TARGET_HAS_v256)
142 #define TCG_TARGET_MAYBE_vec 0
143 #define TCG_TARGET_HAS_abs_vec 0
144 #define TCG_TARGET_HAS_neg_vec 0
145 #define TCG_TARGET_HAS_not_vec 0
146 #define TCG_TARGET_HAS_andc_vec 0
147 #define TCG_TARGET_HAS_orc_vec 0
148 #define TCG_TARGET_HAS_nand_vec 0
149 #define TCG_TARGET_HAS_nor_vec 0
150 #define TCG_TARGET_HAS_eqv_vec 0
151 #define TCG_TARGET_HAS_roti_vec 0
152 #define TCG_TARGET_HAS_rots_vec 0
153 #define TCG_TARGET_HAS_rotv_vec 0
154 #define TCG_TARGET_HAS_shi_vec 0
155 #define TCG_TARGET_HAS_shs_vec 0
156 #define TCG_TARGET_HAS_shv_vec 0
157 #define TCG_TARGET_HAS_mul_vec 0
158 #define TCG_TARGET_HAS_sat_vec 0
159 #define TCG_TARGET_HAS_minmax_vec 0
160 #define TCG_TARGET_HAS_bitsel_vec 0
161 #define TCG_TARGET_HAS_cmpsel_vec 0
163 #define TCG_TARGET_MAYBE_vec 1
165 #ifndef TCG_TARGET_HAS_v64
166 #define TCG_TARGET_HAS_v64 0
168 #ifndef TCG_TARGET_HAS_v128
169 #define TCG_TARGET_HAS_v128 0
171 #ifndef TCG_TARGET_HAS_v256
172 #define TCG_TARGET_HAS_v256 0
175 typedef enum TCGOpcode
{
176 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
177 #include "tcg/tcg-opc.h"
182 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r))
183 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
184 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
186 #ifndef TCG_TARGET_INSN_UNIT_SIZE
187 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
188 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
189 typedef uint8_t tcg_insn_unit
;
190 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
191 typedef uint16_t tcg_insn_unit
;
192 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
193 typedef uint32_t tcg_insn_unit
;
194 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
195 typedef uint64_t tcg_insn_unit
;
197 /* The port better have done this. */
200 typedef struct TCGRelocation TCGRelocation
;
201 struct TCGRelocation
{
202 QSIMPLEQ_ENTRY(TCGRelocation
) next
;
208 typedef struct TCGOp TCGOp
;
209 typedef struct TCGLabelUse TCGLabelUse
;
211 QSIMPLEQ_ENTRY(TCGLabelUse
) next
;
215 typedef struct TCGLabel TCGLabel
;
222 const tcg_insn_unit
*value_ptr
;
224 QSIMPLEQ_HEAD(, TCGLabelUse
) branches
;
225 QSIMPLEQ_HEAD(, TCGRelocation
) relocs
;
226 QSIMPLEQ_ENTRY(TCGLabel
) next
;
229 typedef struct TCGPool
{
230 struct TCGPool
*next
;
232 uint8_t data
[] __attribute__ ((aligned
));
235 #define TCG_POOL_CHUNK_SIZE 32768
237 #define TCG_MAX_TEMPS 512
238 #define TCG_MAX_INSNS 512
240 /* when the size of the arguments of a called function is smaller than
241 this value, they are statically allocated in the TB stack frame */
242 #define TCG_STATIC_CALL_ARGS_SIZE 128
244 typedef enum TCGType
{
253 /* Number of different types (integer not enum) */
254 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1)
256 /* An alias for the size of the host register. */
257 #if TCG_TARGET_REG_BITS == 32
258 TCG_TYPE_REG
= TCG_TYPE_I32
,
260 TCG_TYPE_REG
= TCG_TYPE_I64
,
263 /* An alias for the size of the native pointer. */
264 #if UINTPTR_MAX == UINT32_MAX
265 TCG_TYPE_PTR
= TCG_TYPE_I32
,
267 TCG_TYPE_PTR
= TCG_TYPE_I64
,
275 * Return the size of the type in bytes.
277 static inline int tcg_type_size(TCGType t
)
280 if (i
>= TCG_TYPE_V64
) {
281 tcg_debug_assert(i
< TCG_TYPE_COUNT
);
282 i
-= TCG_TYPE_V64
- 1;
289 * @memop: MemOp value
291 * Extract the alignment size from the memop.
293 static inline unsigned get_alignment_bits(MemOp memop
)
295 unsigned a
= memop
& MO_AMASK
;
298 /* No alignment required. */
300 } else if (a
== MO_ALIGN
) {
301 /* A natural alignment requirement. */
304 /* A specific alignment requirement. */
310 typedef tcg_target_ulong TCGArg
;
312 /* Define type and accessor macros for TCG variables.
314 TCG variables are the inputs and outputs of TCG ops, as described
315 in tcg/README. Target CPU front-end code uses these types to deal
316 with TCG variables as it emits TCG code via the tcg_gen_* functions.
317 They come in several flavours:
318 * TCGv_i32 : 32 bit integer type
319 * TCGv_i64 : 64 bit integer type
320 * TCGv_i128 : 128 bit integer type
321 * TCGv_ptr : a host pointer type
322 * TCGv_vec : a host vector type; the exact size is not exposed
323 to the CPU front-end code.
324 * TCGv : an integer type the same size as target_ulong
325 (an alias for either TCGv_i32 or TCGv_i64)
326 The compiler's type checking will complain if you mix them
327 up and pass the wrong sized TCGv to a function.
329 Users of tcg_gen_* don't need to know about any of the internal
330 details of these, and should treat them as opaque types.
331 You won't be able to look inside them in a debugger either.
333 Internal implementation details follow:
335 Note that there is no definition of the structs TCGv_i32_d etc anywhere.
336 This is deliberate, because the values we store in variables of type
337 TCGv_i32 are not really pointers-to-structures. They're just small
338 integers, but keeping them in pointer types like this means that the
339 compiler will complain if you accidentally pass a TCGv_i32 to a
340 function which takes a TCGv_i64, and so on. Only the internals of
341 TCG need to care about the actual contents of the types. */
343 typedef struct TCGv_i32_d
*TCGv_i32
;
344 typedef struct TCGv_i64_d
*TCGv_i64
;
345 typedef struct TCGv_i128_d
*TCGv_i128
;
346 typedef struct TCGv_ptr_d
*TCGv_ptr
;
347 typedef struct TCGv_vec_d
*TCGv_vec
;
348 typedef TCGv_ptr TCGv_env
;
351 /* Helper does not read globals (either directly or through an exception). It
352 implies TCG_CALL_NO_WRITE_GLOBALS. */
353 #define TCG_CALL_NO_READ_GLOBALS 0x0001
354 /* Helper does not write globals */
355 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002
356 /* Helper can be safely suppressed if the return value is not used. */
357 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004
358 /* Helper is G_NORETURN. */
359 #define TCG_CALL_NO_RETURN 0x0008
360 /* Helper is part of Plugins. */
361 #define TCG_CALL_PLUGIN 0x0010
363 /* convenience version of most used call flags */
364 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
365 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
366 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
367 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
368 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
371 * Flags for the bswap opcodes.
372 * If IZ, the input is zero-extended, otherwise unknown.
373 * If OZ or OS, the output is zero- or sign-extended respectively,
374 * otherwise the high bits are undefined.
382 typedef enum TCGTempVal
{
389 typedef enum TCGTempKind
{
391 * Temp is dead at the end of the extended basic block (EBB),
392 * the single-entry multiple-exit region that falls through
393 * conditional branches.
396 /* Temp is live across the entire translation block, but dead at end. */
398 /* Temp is live across the entire translation block, and between them. */
400 /* Temp is in a fixed register. */
402 /* Temp is a fixed constant. */
406 typedef struct TCGTemp
{
408 TCGTempVal val_type
:8;
412 unsigned int indirect_reg
:1;
413 unsigned int indirect_base
:1;
414 unsigned int mem_coherent
:1;
415 unsigned int mem_allocated
:1;
416 unsigned int temp_allocated
:1;
417 unsigned int temp_subindex
:1;
420 struct TCGTemp
*mem_base
;
424 /* Pass-specific information that can be stored for a temporary.
425 One word worth of integer data, and one pointer to data
426 allocated separately. */
431 typedef struct TCGContext TCGContext
;
433 typedef struct TCGTempSet
{
434 unsigned long l
[BITS_TO_LONGS(TCG_MAX_TEMPS
)];
438 * With 1 128-bit output, a 32-bit host requires 4 output parameters,
439 * which leaves a maximum of 28 other slots. Which is enough for 7
442 #define DEAD_ARG (1 << 4)
443 #define SYNC_ARG (1 << 0)
444 typedef uint32_t TCGLifeData
;
450 /* Parameters for this opcode. See below. */
454 /* Lifetime data of the operands. */
457 /* Next and previous opcodes. */
458 QTAILQ_ENTRY(TCGOp
) link
;
460 /* Register preferences for the output(s). */
461 TCGRegSet output_pref
[2];
463 /* Arguments for the opcode. */
467 #define TCGOP_CALLI(X) (X)->param1
468 #define TCGOP_CALLO(X) (X)->param2
470 #define TCGOP_VECL(X) (X)->param1
471 #define TCGOP_VECE(X) (X)->param2
473 /* Make sure operands fit in the bitfields above. */
474 QEMU_BUILD_BUG_ON(NB_OPS
> (1 << 8));
476 static inline TCGRegSet
output_pref(const TCGOp
*op
, unsigned i
)
478 return i
< ARRAY_SIZE(op
->output_pref
) ? op
->output_pref
[i
] : 0;
481 typedef struct TCGProfile
{
482 int64_t cpu_exec_time
;
485 int64_t op_count
; /* total insn count */
486 int op_count_max
; /* max insn per TB */
489 int64_t del_op_count
;
491 int64_t code_out_len
;
492 int64_t search_out_len
;
497 int64_t restore_count
;
498 int64_t restore_time
;
499 int64_t table_op_count
[NB_OPS
];
503 uint8_t *pool_cur
, *pool_end
;
504 TCGPool
*pool_first
, *pool_current
, *pool_first_large
;
510 TCGType addr_type
; /* TCG_TYPE_I32 or TCG_TYPE_I64 */
512 #ifdef CONFIG_SOFTMMU
516 uint8_t tlb_dyn_max_bits
;
518 uint8_t insn_start_words
;
521 TCGRegSet reserved_regs
;
522 intptr_t current_frame_offset
;
523 intptr_t frame_start
;
527 TranslationBlock
*gen_tb
; /* tb for which code is being generated */
528 tcg_insn_unit
*code_buf
; /* pointer for start of tb */
529 tcg_insn_unit
*code_ptr
; /* pointer for running end of tb */
531 #ifdef CONFIG_PROFILER
535 #ifdef CONFIG_DEBUG_TCG
536 int goto_tb_issue_mask
;
537 const TCGOpcode
*vecop_list
;
540 /* Code generation. Note that we specifically do not use tcg_insn_unit
541 here, because there's too much arithmetic throughout that relies
542 on addition and subtraction working on bytes. Rely on the GCC
543 extension that allows arithmetic on void*. */
544 void *code_gen_buffer
;
545 size_t code_gen_buffer_size
;
549 /* Threshold to flush the translated code buffer. */
550 void *code_gen_highwater
;
552 /* Track which vCPU triggers events */
553 CPUState
*cpu
; /* *_trans */
555 /* These structures are private to tcg-target.c.inc. */
556 #ifdef TCG_TARGET_NEED_LDST_LABELS
557 QSIMPLEQ_HEAD(, TCGLabelQemuLdst
) ldst_labels
;
559 #ifdef TCG_TARGET_NEED_POOL_LABELS
560 struct TCGLabelPoolData
*pool_labels
;
563 TCGLabel
*exitreq_label
;
567 * We keep one plugin_tb struct per TCGContext. Note that on every TB
568 * translation we clear but do not free its contents; this way we
569 * avoid a lot of malloc/free churn, since after a few TB's it's
570 * unlikely that we'll need to allocate either more instructions or more
571 * space for instructions (for variable-instruction-length ISAs).
573 struct qemu_plugin_tb
*plugin_tb
;
575 /* descriptor of the instruction being translated */
576 struct qemu_plugin_insn
*plugin_insn
;
579 GHashTable
*const_table
[TCG_TYPE_COUNT
];
580 TCGTempSet free_temps
[TCG_TYPE_COUNT
];
581 TCGTemp temps
[TCG_MAX_TEMPS
]; /* globals first, temps after */
583 QTAILQ_HEAD(, TCGOp
) ops
, free_ops
;
584 QSIMPLEQ_HEAD(, TCGLabel
) labels
;
586 /* Tells which temporary holds a given register.
587 It does not take into account fixed registers */
588 TCGTemp
*reg_to_temp
[TCG_TARGET_NB_REGS
];
590 uint16_t gen_insn_end_off
[TCG_MAX_INSNS
];
591 uint64_t *gen_insn_data
;
593 /* Exit to translator on overflow. */
594 sigjmp_buf jmp_trans
;
597 static inline bool temp_readonly(TCGTemp
*ts
)
599 return ts
->kind
>= TEMP_FIXED
;
602 extern __thread TCGContext
*tcg_ctx
;
603 extern const void *tcg_code_gen_epilogue
;
604 extern uintptr_t tcg_splitwx_diff
;
605 extern TCGv_env cpu_env
;
607 bool in_code_gen_buffer(const void *p
);
609 #ifdef CONFIG_DEBUG_TCG
610 const void *tcg_splitwx_to_rx(void *rw
);
611 void *tcg_splitwx_to_rw(const void *rx
);
613 static inline const void *tcg_splitwx_to_rx(void *rw
)
615 return rw
? rw
+ tcg_splitwx_diff
: NULL
;
618 static inline void *tcg_splitwx_to_rw(const void *rx
)
620 return rx
? (void *)rx
- tcg_splitwx_diff
: NULL
;
624 static inline TCGArg
temp_arg(TCGTemp
*ts
)
626 return (uintptr_t)ts
;
629 static inline TCGTemp
*arg_temp(TCGArg a
)
631 return (TCGTemp
*)(uintptr_t)a
;
634 #ifdef CONFIG_DEBUG_TCG
635 size_t temp_idx(TCGTemp
*ts
);
636 TCGTemp
*tcgv_i32_temp(TCGv_i32 v
);
638 static inline size_t temp_idx(TCGTemp
*ts
)
640 return ts
- tcg_ctx
->temps
;
644 * Using the offset of a temporary, relative to TCGContext, rather than
645 * its index means that we don't use 0. That leaves offset 0 free for
646 * a NULL representation without having to leave index 0 unused.
648 static inline TCGTemp
*tcgv_i32_temp(TCGv_i32 v
)
650 return (void *)tcg_ctx
+ (uintptr_t)v
;
654 static inline TCGTemp
*tcgv_i64_temp(TCGv_i64 v
)
656 return tcgv_i32_temp((TCGv_i32
)v
);
659 static inline TCGTemp
*tcgv_i128_temp(TCGv_i128 v
)
661 return tcgv_i32_temp((TCGv_i32
)v
);
664 static inline TCGTemp
*tcgv_ptr_temp(TCGv_ptr v
)
666 return tcgv_i32_temp((TCGv_i32
)v
);
669 static inline TCGTemp
*tcgv_vec_temp(TCGv_vec v
)
671 return tcgv_i32_temp((TCGv_i32
)v
);
674 static inline TCGArg
tcgv_i32_arg(TCGv_i32 v
)
676 return temp_arg(tcgv_i32_temp(v
));
679 static inline TCGArg
tcgv_i64_arg(TCGv_i64 v
)
681 return temp_arg(tcgv_i64_temp(v
));
684 static inline TCGArg
tcgv_i128_arg(TCGv_i128 v
)
686 return temp_arg(tcgv_i128_temp(v
));
689 static inline TCGArg
tcgv_ptr_arg(TCGv_ptr v
)
691 return temp_arg(tcgv_ptr_temp(v
));
694 static inline TCGArg
tcgv_vec_arg(TCGv_vec v
)
696 return temp_arg(tcgv_vec_temp(v
));
699 static inline TCGv_i32
temp_tcgv_i32(TCGTemp
*t
)
701 (void)temp_idx(t
); /* trigger embedded assert */
702 return (TCGv_i32
)((void *)t
- (void *)tcg_ctx
);
705 static inline TCGv_i64
temp_tcgv_i64(TCGTemp
*t
)
707 return (TCGv_i64
)temp_tcgv_i32(t
);
710 static inline TCGv_i128
temp_tcgv_i128(TCGTemp
*t
)
712 return (TCGv_i128
)temp_tcgv_i32(t
);
715 static inline TCGv_ptr
temp_tcgv_ptr(TCGTemp
*t
)
717 return (TCGv_ptr
)temp_tcgv_i32(t
);
720 static inline TCGv_vec
temp_tcgv_vec(TCGTemp
*t
)
722 return (TCGv_vec
)temp_tcgv_i32(t
);
725 static inline TCGArg
tcg_get_insn_param(TCGOp
*op
, int arg
)
727 return op
->args
[arg
];
730 static inline void tcg_set_insn_param(TCGOp
*op
, int arg
, TCGArg v
)
735 static inline uint64_t tcg_get_insn_start_param(TCGOp
*op
, int arg
)
737 if (TCG_TARGET_REG_BITS
== 64) {
738 return tcg_get_insn_param(op
, arg
);
740 return deposit64(tcg_get_insn_param(op
, arg
* 2), 32, 32,
741 tcg_get_insn_param(op
, arg
* 2 + 1));
745 static inline void tcg_set_insn_start_param(TCGOp
*op
, int arg
, uint64_t v
)
747 if (TCG_TARGET_REG_BITS
== 64) {
748 tcg_set_insn_param(op
, arg
, v
);
750 tcg_set_insn_param(op
, arg
* 2, v
);
751 tcg_set_insn_param(op
, arg
* 2 + 1, v
>> 32);
755 /* The last op that was emitted. */
756 static inline TCGOp
*tcg_last_op(void)
758 return QTAILQ_LAST(&tcg_ctx
->ops
);
761 /* Test for whether to terminate the TB for using too many opcodes. */
762 static inline bool tcg_op_buf_full(void)
764 /* This is not a hard limit, it merely stops translation when
765 * we have produced "enough" opcodes. We want to limit TB size
766 * such that a RISC host can reasonably use a 16-bit signed
767 * branch within the TB. We also need to be mindful of the
768 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
769 * and TCGContext.gen_insn_end_off[].
771 return tcg_ctx
->nb_ops
>= 4000;
774 /* pool based memory allocation */
776 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
777 void *tcg_malloc_internal(TCGContext
*s
, int size
);
778 void tcg_pool_reset(TCGContext
*s
);
779 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
);
781 void tcg_region_reset_all(void);
783 size_t tcg_code_size(void);
784 size_t tcg_code_capacity(void);
786 void tcg_tb_insert(TranslationBlock
*tb
);
787 void tcg_tb_remove(TranslationBlock
*tb
);
788 TranslationBlock
*tcg_tb_lookup(uintptr_t tc_ptr
);
789 void tcg_tb_foreach(GTraverseFunc func
, gpointer user_data
);
790 size_t tcg_nb_tbs(void);
792 /* user-mode: Called with mmap_lock held. */
793 static inline void *tcg_malloc(int size
)
795 TCGContext
*s
= tcg_ctx
;
796 uint8_t *ptr
, *ptr_end
;
798 /* ??? This is a weak placeholder for minimum malloc alignment. */
799 size
= QEMU_ALIGN_UP(size
, 8);
802 ptr_end
= ptr
+ size
;
803 if (unlikely(ptr_end
> s
->pool_end
)) {
804 return tcg_malloc_internal(tcg_ctx
, size
);
806 s
->pool_cur
= ptr_end
;
811 void tcg_init(size_t tb_size
, int splitwx
, unsigned max_cpus
);
812 void tcg_register_thread(void);
813 void tcg_prologue_init(TCGContext
*s
);
814 void tcg_func_start(TCGContext
*s
);
816 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
, uint64_t pc_start
);
818 void tb_target_set_jmp_target(const TranslationBlock
*, int,
819 uintptr_t, uintptr_t);
821 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
);
823 TCGTemp
*tcg_global_mem_new_internal(TCGType
, TCGv_ptr
,
824 intptr_t, const char *);
825 TCGTemp
*tcg_temp_new_internal(TCGType
, TCGTempKind
);
826 TCGv_vec
tcg_temp_new_vec(TCGType type
);
827 TCGv_vec
tcg_temp_new_vec_matching(TCGv_vec match
);
829 static inline TCGv_i32
tcg_global_mem_new_i32(TCGv_ptr reg
, intptr_t offset
,
832 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_I32
, reg
, offset
, name
);
833 return temp_tcgv_i32(t
);
836 static inline TCGv_i32
tcg_temp_new_i32(void)
838 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I32
, TEMP_TB
);
839 return temp_tcgv_i32(t
);
842 static inline TCGv_i64
tcg_global_mem_new_i64(TCGv_ptr reg
, intptr_t offset
,
845 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_I64
, reg
, offset
, name
);
846 return temp_tcgv_i64(t
);
849 static inline TCGv_i64
tcg_temp_new_i64(void)
851 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I64
, TEMP_TB
);
852 return temp_tcgv_i64(t
);
855 static inline TCGv_i128
tcg_temp_new_i128(void)
857 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I128
, TEMP_TB
);
858 return temp_tcgv_i128(t
);
861 static inline TCGv_ptr
tcg_global_mem_new_ptr(TCGv_ptr reg
, intptr_t offset
,
864 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_PTR
, reg
, offset
, name
);
865 return temp_tcgv_ptr(t
);
868 static inline TCGv_ptr
tcg_temp_new_ptr(void)
870 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_PTR
, TEMP_TB
);
871 return temp_tcgv_ptr(t
);
874 int64_t tcg_cpu_exec_time(void);
875 void tcg_dump_info(GString
*buf
);
876 void tcg_dump_op_count(GString
*buf
);
878 #define TCG_CT_CONST 1 /* any constant of register size */
880 typedef struct TCGArgConstraint
{
882 unsigned alias_index
: 4;
883 unsigned sort_index
: 4;
884 unsigned pair_index
: 4;
885 unsigned pair
: 2; /* 0: none, 1: first, 2: second, 3: second alias */
892 #define TCG_MAX_OP_ARGS 16
894 /* Bits for TCGOpDef->flags, 8 bits available, all used. */
896 /* Instruction exits the translation block. */
897 TCG_OPF_BB_EXIT
= 0x01,
898 /* Instruction defines the end of a basic block. */
899 TCG_OPF_BB_END
= 0x02,
900 /* Instruction clobbers call registers and potentially update globals. */
901 TCG_OPF_CALL_CLOBBER
= 0x04,
902 /* Instruction has side effects: it cannot be removed if its outputs
903 are not used, and might trigger exceptions. */
904 TCG_OPF_SIDE_EFFECTS
= 0x08,
905 /* Instruction operands are 64-bits (otherwise 32-bits). */
906 TCG_OPF_64BIT
= 0x10,
907 /* Instruction is optional and not implemented by the host, or insn
908 is generic and should not be implemened by the host. */
909 TCG_OPF_NOT_PRESENT
= 0x20,
910 /* Instruction operands are vectors. */
911 TCG_OPF_VECTOR
= 0x40,
912 /* Instruction is a conditional branch. */
913 TCG_OPF_COND_BRANCH
= 0x80
916 typedef struct TCGOpDef
{
918 uint8_t nb_oargs
, nb_iargs
, nb_cargs
, nb_args
;
920 TCGArgConstraint
*args_ct
;
923 extern TCGOpDef tcg_op_defs
[];
924 extern const size_t tcg_op_defs_max
;
926 typedef struct TCGTargetOpDef
{
928 const char *args_ct_str
[TCG_MAX_OP_ARGS
];
931 bool tcg_op_supported(TCGOpcode op
);
933 void tcg_gen_call0(TCGHelperInfo
*, TCGTemp
*ret
);
934 void tcg_gen_call1(TCGHelperInfo
*, TCGTemp
*ret
, TCGTemp
*);
935 void tcg_gen_call2(TCGHelperInfo
*, TCGTemp
*ret
, TCGTemp
*, TCGTemp
*);
936 void tcg_gen_call3(TCGHelperInfo
*, TCGTemp
*ret
, TCGTemp
*,
937 TCGTemp
*, TCGTemp
*);
938 void tcg_gen_call4(TCGHelperInfo
*, TCGTemp
*ret
, TCGTemp
*, TCGTemp
*,
939 TCGTemp
*, TCGTemp
*);
940 void tcg_gen_call5(TCGHelperInfo
*, TCGTemp
*ret
, TCGTemp
*, TCGTemp
*,
941 TCGTemp
*, TCGTemp
*, TCGTemp
*);
942 void tcg_gen_call6(TCGHelperInfo
*, TCGTemp
*ret
, TCGTemp
*, TCGTemp
*,
943 TCGTemp
*, TCGTemp
*, TCGTemp
*, TCGTemp
*);
944 void tcg_gen_call7(TCGHelperInfo
*, TCGTemp
*ret
, TCGTemp
*, TCGTemp
*,
945 TCGTemp
*, TCGTemp
*, TCGTemp
*, TCGTemp
*, TCGTemp
*);
947 TCGOp
*tcg_emit_op(TCGOpcode opc
, unsigned nargs
);
948 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
);
949 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*op
,
950 TCGOpcode opc
, unsigned nargs
);
951 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*op
,
952 TCGOpcode opc
, unsigned nargs
);
955 * tcg_remove_ops_after:
956 * @op: target operation
958 * Discard any opcodes emitted since @op. Expected usage is to save
959 * a starting point with tcg_last_op(), speculatively emit opcodes,
960 * then decide whether or not to keep those opcodes after the fact.
962 void tcg_remove_ops_after(TCGOp
*op
);
964 void tcg_optimize(TCGContext
*s
);
967 * Locate or create a read-only temporary that is a constant.
968 * This kind of temporary need not be freed, but for convenience
969 * will be silently ignored by tcg_temp_free_*.
971 TCGTemp
*tcg_constant_internal(TCGType type
, int64_t val
);
973 static inline TCGv_i32
tcg_constant_i32(int32_t val
)
975 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32
, val
));
978 static inline TCGv_i64
tcg_constant_i64(int64_t val
)
980 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64
, val
));
983 TCGv_vec
tcg_constant_vec(TCGType type
, unsigned vece
, int64_t val
);
984 TCGv_vec
tcg_constant_vec_matching(TCGv_vec match
, unsigned vece
, int64_t val
);
986 #if UINTPTR_MAX == UINT32_MAX
987 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x)))
989 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x)))
992 TCGLabel
*gen_new_label(void);
998 * Encode a label for storage in the TCG opcode stream.
1001 static inline TCGArg
label_arg(TCGLabel
*l
)
1003 return (uintptr_t)l
;
1010 * The opposite of label_arg. Retrieve a label from the
1011 * encoding of the TCG opcode stream.
1014 static inline TCGLabel
*arg_label(TCGArg i
)
1016 return (TCGLabel
*)(uintptr_t)i
;
1021 * @a, @b: addresses to be differenced
1023 * There are many places within the TCG backends where we need a byte
1024 * difference between two pointers. While this can be accomplished
1025 * with local casting, it's easy to get wrong -- especially if one is
1026 * concerned with the signedness of the result.
1028 * This version relies on GCC's void pointer arithmetic to get the
1032 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a
, const void *b
)
1039 * @s: the tcg context
1040 * @target: address of the target
1042 * Produce a pc-relative difference, from the current code_ptr
1043 * to the destination address.
1046 static inline ptrdiff_t tcg_pcrel_diff(TCGContext
*s
, const void *target
)
1048 return tcg_ptr_byte_diff(target
, tcg_splitwx_to_rx(s
->code_ptr
));
1053 * @s: the tcg context
1054 * @target: address of the target
1056 * Produce a difference, from the beginning of the current TB code
1057 * to the destination address.
1059 static inline ptrdiff_t tcg_tbrel_diff(TCGContext
*s
, const void *target
)
1061 return tcg_ptr_byte_diff(target
, tcg_splitwx_to_rx(s
->code_buf
));
1065 * tcg_current_code_size
1066 * @s: the tcg context
1068 * Compute the current code size within the translation block.
1069 * This is used to fill in qemu's data structures for goto_tb.
1072 static inline size_t tcg_current_code_size(TCGContext
*s
)
1074 return tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
);
1079 * @env: pointer to CPUArchState for the CPU
1080 * @tb_ptr: address of generated code for the TB to execute
1082 * Start executing code from a given translation block.
1083 * Where translation blocks have been linked, execution
1084 * may proceed from the given TB into successive ones.
1085 * Control eventually returns only when some action is needed
1086 * from the top-level loop: either control must pass to a TB
1087 * which has not yet been directly linked, or an asynchronous
1088 * event such as an interrupt needs handling.
1090 * Return: The return value is the value passed to the corresponding
1091 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1092 * The value is either zero or a 4-byte aligned pointer to that TB combined
1093 * with additional information in its two least significant bits. The
1094 * additional information is encoded as follows:
1095 * 0, 1: the link between this TB and the next is via the specified
1096 * TB index (0 or 1). That is, we left the TB via (the equivalent
1097 * of) "goto_tb <index>". The main loop uses this to determine
1098 * how to link the TB just executed to the next.
1099 * 2: we are using instruction counting code generation, and we
1100 * did not start executing this TB because the instruction counter
1101 * would hit zero midway through it. In this case the pointer
1102 * returned is the TB we were about to execute, and the caller must
1103 * arrange to execute the remaining count of instructions.
1104 * 3: we stopped because the CPU's exit_request flag was set
1105 * (usually meaning that there is an interrupt that needs to be
1106 * handled). The pointer returned is the TB we were about to execute
1107 * when we noticed the pending exit request.
1109 * If the bottom two bits indicate an exit-via-index then the CPU
1110 * state is correctly synchronised and ready for execution of the next
1111 * TB (and in particular the guest PC is the address to execute next).
1112 * Otherwise, we gave up on execution of this TB before it started, and
1113 * the caller must fix up the CPU state by calling the CPU's
1114 * synchronize_from_tb() method with the TB pointer we return (falling
1115 * back to calling the CPU's set_pc method with tb->pb if no
1116 * synchronize_from_tb() method exists).
1118 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1119 * to this default (which just calls the prologue.code emitted by
1120 * tcg_target_qemu_prologue()).
1122 #define TB_EXIT_MASK 3
1123 #define TB_EXIT_IDX0 0
1124 #define TB_EXIT_IDX1 1
1125 #define TB_EXIT_IDXMAX 1
1126 #define TB_EXIT_REQUESTED 3
1128 #ifdef CONFIG_TCG_INTERPRETER
1129 uintptr_t tcg_qemu_tb_exec(CPUArchState
*env
, const void *tb_ptr
);
1131 typedef uintptr_t tcg_prologue_fn(CPUArchState
*env
, const void *tb_ptr
);
1132 extern tcg_prologue_fn
*tcg_qemu_tb_exec
;
1135 void tcg_register_jit(const void *buf
, size_t buf_size
);
1137 #if TCG_TARGET_MAYBE_vec
1138 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1139 return > 0 if it is directly supportable;
1140 return < 0 if we must call tcg_expand_vec_op. */
1141 int tcg_can_emit_vec_op(TCGOpcode
, TCGType
, unsigned);
1143 static inline int tcg_can_emit_vec_op(TCGOpcode o
, TCGType t
, unsigned ve
)
1149 /* Expand the tuple (opc, type, vece) on the given arguments. */
1150 void tcg_expand_vec_op(TCGOpcode
, TCGType
, unsigned, TCGArg
, ...);
1152 /* Replicate a constant C accoring to the log2 of the element size. */
1153 uint64_t dup_const(unsigned vece
, uint64_t c
);
1155 #define dup_const(VECE, C) \
1156 (__builtin_constant_p(VECE) \
1157 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
1158 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
1159 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
1160 : (VECE) == MO_64 ? (uint64_t)(C) \
1161 : (qemu_build_not_reached_always(), 0)) \
1162 : dup_const(VECE, C))
1164 #ifdef CONFIG_DEBUG_TCG
1165 void tcg_assert_listed_vecop(TCGOpcode
);
1167 static inline void tcg_assert_listed_vecop(TCGOpcode op
) { }
1170 static inline const TCGOpcode
*tcg_swap_vecop_list(const TCGOpcode
*n
)
1172 #ifdef CONFIG_DEBUG_TCG
1173 const TCGOpcode
*o
= tcg_ctx
->vecop_list
;
1174 tcg_ctx
->vecop_list
= n
;
1181 bool tcg_can_emit_vecop_list(const TCGOpcode
*, TCGType
, unsigned);