1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #ifndef __AMDGPU_DRM_H__
33 #define __AMDGPU_DRM_H__
37 #if defined(__cplusplus)
41 #define DRM_AMDGPU_GEM_CREATE 0x00
42 #define DRM_AMDGPU_GEM_MMAP 0x01
43 #define DRM_AMDGPU_CTX 0x02
44 #define DRM_AMDGPU_BO_LIST 0x03
45 #define DRM_AMDGPU_CS 0x04
46 #define DRM_AMDGPU_INFO 0x05
47 #define DRM_AMDGPU_GEM_METADATA 0x06
48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49 #define DRM_AMDGPU_GEM_VA 0x08
50 #define DRM_AMDGPU_WAIT_CS 0x09
51 #define DRM_AMDGPU_GEM_OP 0x10
52 #define DRM_AMDGPU_GEM_USERPTR 0x11
53 #define DRM_AMDGPU_WAIT_FENCES 0x12
54 #define DRM_AMDGPU_VM 0x13
55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56 #define DRM_AMDGPU_SCHED 0x15
58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
75 #define AMDGPU_GEM_DOMAIN_CPU 0x1
76 #define AMDGPU_GEM_DOMAIN_GTT 0x2
77 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
78 #define AMDGPU_GEM_DOMAIN_GDS 0x8
79 #define AMDGPU_GEM_DOMAIN_GWS 0x10
80 #define AMDGPU_GEM_DOMAIN_OA 0x20
82 /* Flag that CPU access will be required for the case of VRAM domain */
83 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
84 /* Flag that CPU access will not work, this VRAM domain is invisible */
85 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
86 /* Flag that USWC attributes should be used for GTT */
87 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
88 /* Flag that the memory should be in VRAM and cleared */
89 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
90 /* Flag that create shadow bo(GTT) while allocating vram bo */
91 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
92 /* Flag that allocating the BO should use linear VRAM */
93 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
94 /* Flag that BO is always valid in this VM */
95 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
96 /* Flag that BO sharing will be explicitly synchronized */
97 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
99 struct drm_amdgpu_gem_create_in
{
100 /** the requested memory size */
102 /** physical start_addr alignment in bytes for some HW requirements */
104 /** the requested memory domains */
106 /** allocation flags */
110 struct drm_amdgpu_gem_create_out
{
111 /** returned GEM object handle */
116 union drm_amdgpu_gem_create
{
117 struct drm_amdgpu_gem_create_in in
;
118 struct drm_amdgpu_gem_create_out out
;
121 /** Opcode to create new residency list. */
122 #define AMDGPU_BO_LIST_OP_CREATE 0
123 /** Opcode to destroy previously created residency list */
124 #define AMDGPU_BO_LIST_OP_DESTROY 1
125 /** Opcode to update resource information in the list */
126 #define AMDGPU_BO_LIST_OP_UPDATE 2
128 struct drm_amdgpu_bo_list_in
{
129 /** Type of operation */
131 /** Handle of list or 0 if we want to create one */
133 /** Number of BOs in list */
135 /** Size of each element describing BO */
137 /** Pointer to array describing BOs */
141 struct drm_amdgpu_bo_list_entry
{
144 /** New (if specified) BO priority to be used during migration */
148 struct drm_amdgpu_bo_list_out
{
149 /** Handle of resource list */
154 union drm_amdgpu_bo_list
{
155 struct drm_amdgpu_bo_list_in in
;
156 struct drm_amdgpu_bo_list_out out
;
159 /* context related */
160 #define AMDGPU_CTX_OP_ALLOC_CTX 1
161 #define AMDGPU_CTX_OP_FREE_CTX 2
162 #define AMDGPU_CTX_OP_QUERY_STATE 3
163 #define AMDGPU_CTX_OP_QUERY_STATE2 4
165 /* GPU reset status */
166 #define AMDGPU_CTX_NO_RESET 0
167 /* this the context caused it */
168 #define AMDGPU_CTX_GUILTY_RESET 1
169 /* some other context caused it */
170 #define AMDGPU_CTX_INNOCENT_RESET 2
172 #define AMDGPU_CTX_UNKNOWN_RESET 3
174 /* indicate gpu reset occured after ctx created */
175 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
176 /* indicate vram lost occured after ctx created */
177 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
178 /* indicate some job from this context once cause gpu hang */
179 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
181 /* Context priority level */
182 #define AMDGPU_CTX_PRIORITY_UNSET -2048
183 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
184 #define AMDGPU_CTX_PRIORITY_LOW -512
185 #define AMDGPU_CTX_PRIORITY_NORMAL 0
186 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
187 #define AMDGPU_CTX_PRIORITY_HIGH 512
188 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
190 struct drm_amdgpu_ctx_in
{
191 /** AMDGPU_CTX_OP_* */
193 /** For future use, no flags defined so far */
199 union drm_amdgpu_ctx_out
{
206 /** For future use, no flags defined so far */
208 /** Number of resets caused by this context so far. */
210 /** Reset status since the last call of the ioctl. */
215 union drm_amdgpu_ctx
{
216 struct drm_amdgpu_ctx_in in
;
217 union drm_amdgpu_ctx_out out
;
221 #define AMDGPU_VM_OP_RESERVE_VMID 1
222 #define AMDGPU_VM_OP_UNRESERVE_VMID 2
224 struct drm_amdgpu_vm_in
{
225 /** AMDGPU_VM_OP_* */
230 struct drm_amdgpu_vm_out
{
231 /** For future use, no flags defined so far */
235 union drm_amdgpu_vm
{
236 struct drm_amdgpu_vm_in in
;
237 struct drm_amdgpu_vm_out out
;
241 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
243 struct drm_amdgpu_sched_in
{
244 /* AMDGPU_SCHED_OP_* */
251 union drm_amdgpu_sched
{
252 struct drm_amdgpu_sched_in in
;
256 * This is not a reliable API and you should expect it to fail for any
257 * number of reasons and have fallback path that do not use userptr to
258 * perform any operation.
260 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
261 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
262 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
263 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
265 struct drm_amdgpu_gem_userptr
{
268 /* AMDGPU_GEM_USERPTR_* */
270 /* Resulting GEM handle */
275 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
276 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
277 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
278 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
279 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
280 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
281 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
282 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
283 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
284 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
285 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
286 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
287 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
288 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
289 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
290 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
291 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
293 /* GFX9 and later: */
294 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
295 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
297 /* Set/Get helpers for tiling flags. */
298 #define AMDGPU_TILING_SET(field, value) \
299 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
300 #define AMDGPU_TILING_GET(value, field) \
301 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
303 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
304 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
306 /** The same structure is shared for input/output */
307 struct drm_amdgpu_gem_metadata
{
308 /** GEM Object handle */
310 /** Do we want get or set metadata */
313 /** For future use, no flags defined so far */
315 /** family specific tiling info */
317 __u32 data_size_bytes
;
322 struct drm_amdgpu_gem_mmap_in
{
323 /** the GEM object handle */
328 struct drm_amdgpu_gem_mmap_out
{
329 /** mmap offset from the vma offset manager */
333 union drm_amdgpu_gem_mmap
{
334 struct drm_amdgpu_gem_mmap_in in
;
335 struct drm_amdgpu_gem_mmap_out out
;
338 struct drm_amdgpu_gem_wait_idle_in
{
339 /** GEM object handle */
341 /** For future use, no flags defined so far */
343 /** Absolute timeout to wait */
347 struct drm_amdgpu_gem_wait_idle_out
{
348 /** BO status: 0 - BO is idle, 1 - BO is busy */
350 /** Returned current memory domain */
354 union drm_amdgpu_gem_wait_idle
{
355 struct drm_amdgpu_gem_wait_idle_in in
;
356 struct drm_amdgpu_gem_wait_idle_out out
;
359 struct drm_amdgpu_wait_cs_in
{
360 /* Command submission handle
361 * handle equals 0 means none to wait for
362 * handle equals ~0ull means wait for the latest sequence number
365 /** Absolute timeout to wait */
373 struct drm_amdgpu_wait_cs_out
{
374 /** CS status: 0 - CS completed, 1 - CS still busy */
378 union drm_amdgpu_wait_cs
{
379 struct drm_amdgpu_wait_cs_in in
;
380 struct drm_amdgpu_wait_cs_out out
;
383 struct drm_amdgpu_fence
{
391 struct drm_amdgpu_wait_fences_in
{
392 /** This points to uint64_t * which points to fences */
399 struct drm_amdgpu_wait_fences_out
{
401 __u32 first_signaled
;
404 union drm_amdgpu_wait_fences
{
405 struct drm_amdgpu_wait_fences_in in
;
406 struct drm_amdgpu_wait_fences_out out
;
409 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
410 #define AMDGPU_GEM_OP_SET_PLACEMENT 1
412 /* Sets or returns a value associated with a buffer. */
413 struct drm_amdgpu_gem_op
{
414 /** GEM object handle */
416 /** AMDGPU_GEM_OP_* */
418 /** Input or return value */
422 #define AMDGPU_VA_OP_MAP 1
423 #define AMDGPU_VA_OP_UNMAP 2
424 #define AMDGPU_VA_OP_CLEAR 3
425 #define AMDGPU_VA_OP_REPLACE 4
427 /* Delay the page table update till the next CS */
428 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
431 /* readable mapping */
432 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
433 /* writable mapping */
434 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
435 /* executable mapping, new for VI */
436 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
437 /* partially resident texture */
438 #define AMDGPU_VM_PAGE_PRT (1 << 4)
439 /* MTYPE flags use bit 5 to 8 */
440 #define AMDGPU_VM_MTYPE_MASK (0xf << 5)
441 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
442 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
443 /* Use NC MTYPE instead of default MTYPE */
444 #define AMDGPU_VM_MTYPE_NC (1 << 5)
445 /* Use WC MTYPE instead of default MTYPE */
446 #define AMDGPU_VM_MTYPE_WC (2 << 5)
447 /* Use CC MTYPE instead of default MTYPE */
448 #define AMDGPU_VM_MTYPE_CC (3 << 5)
449 /* Use UC MTYPE instead of default MTYPE */
450 #define AMDGPU_VM_MTYPE_UC (4 << 5)
452 struct drm_amdgpu_gem_va
{
453 /** GEM object handle */
456 /** AMDGPU_VA_OP_* */
458 /** AMDGPU_VM_PAGE_* */
460 /** va address to assign . Must be correctly aligned.*/
462 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
464 /** Specify mapping size. Must be correctly aligned. */
468 #define AMDGPU_HW_IP_GFX 0
469 #define AMDGPU_HW_IP_COMPUTE 1
470 #define AMDGPU_HW_IP_DMA 2
471 #define AMDGPU_HW_IP_UVD 3
472 #define AMDGPU_HW_IP_VCE 4
473 #define AMDGPU_HW_IP_UVD_ENC 5
474 #define AMDGPU_HW_IP_VCN_DEC 6
475 #define AMDGPU_HW_IP_VCN_ENC 7
476 #define AMDGPU_HW_IP_NUM 8
478 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
480 #define AMDGPU_CHUNK_ID_IB 0x01
481 #define AMDGPU_CHUNK_ID_FENCE 0x02
482 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
483 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
484 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
486 struct drm_amdgpu_cs_chunk
{
492 struct drm_amdgpu_cs_in
{
493 /** Rendering context id */
495 /** Handle of resource list associated with CS */
496 __u32 bo_list_handle
;
499 /** this points to __u64 * which point to cs chunks */
503 struct drm_amdgpu_cs_out
{
507 union drm_amdgpu_cs
{
508 struct drm_amdgpu_cs_in in
;
509 struct drm_amdgpu_cs_out out
;
512 /* Specify flags to be used for IB */
514 /* This IB should be submitted to CE */
515 #define AMDGPU_IB_FLAG_CE (1<<0)
517 /* Preamble flag, which means the IB could be dropped if no context switch */
518 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
520 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
521 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
523 struct drm_amdgpu_cs_chunk_ib
{
525 /** AMDGPU_IB_FLAG_* */
527 /** Virtual address to begin IB execution */
529 /** Size of submission */
531 /** HW IP to submit to */
533 /** HW IP index of the same type to submit to */
535 /** Ring index to submit to */
539 struct drm_amdgpu_cs_chunk_dep
{
547 struct drm_amdgpu_cs_chunk_fence
{
552 struct drm_amdgpu_cs_chunk_sem
{
556 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
557 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
558 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
560 union drm_amdgpu_fence_to_handle
{
562 struct drm_amdgpu_fence fence
;
571 struct drm_amdgpu_cs_chunk_data
{
573 struct drm_amdgpu_cs_chunk_ib ib_data
;
574 struct drm_amdgpu_cs_chunk_fence fence_data
;
579 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
582 #define AMDGPU_IDS_FLAGS_FUSION 0x1
583 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
585 /* indicate if acceleration can be working */
586 #define AMDGPU_INFO_ACCEL_WORKING 0x00
587 /* get the crtc_id from the mode object id? */
588 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
589 /* query hw IP info */
590 #define AMDGPU_INFO_HW_IP_INFO 0x02
591 /* query hw IP instance count for the specified type */
592 #define AMDGPU_INFO_HW_IP_COUNT 0x03
593 /* timestamp for GL_ARB_timer_query */
594 #define AMDGPU_INFO_TIMESTAMP 0x05
595 /* Query the firmware version */
596 #define AMDGPU_INFO_FW_VERSION 0x0e
597 /* Subquery id: Query VCE firmware version */
598 #define AMDGPU_INFO_FW_VCE 0x1
599 /* Subquery id: Query UVD firmware version */
600 #define AMDGPU_INFO_FW_UVD 0x2
601 /* Subquery id: Query GMC firmware version */
602 #define AMDGPU_INFO_FW_GMC 0x03
603 /* Subquery id: Query GFX ME firmware version */
604 #define AMDGPU_INFO_FW_GFX_ME 0x04
605 /* Subquery id: Query GFX PFP firmware version */
606 #define AMDGPU_INFO_FW_GFX_PFP 0x05
607 /* Subquery id: Query GFX CE firmware version */
608 #define AMDGPU_INFO_FW_GFX_CE 0x06
609 /* Subquery id: Query GFX RLC firmware version */
610 #define AMDGPU_INFO_FW_GFX_RLC 0x07
611 /* Subquery id: Query GFX MEC firmware version */
612 #define AMDGPU_INFO_FW_GFX_MEC 0x08
613 /* Subquery id: Query SMC firmware version */
614 #define AMDGPU_INFO_FW_SMC 0x0a
615 /* Subquery id: Query SDMA firmware version */
616 #define AMDGPU_INFO_FW_SDMA 0x0b
617 /* Subquery id: Query PSP SOS firmware version */
618 #define AMDGPU_INFO_FW_SOS 0x0c
619 /* Subquery id: Query PSP ASD firmware version */
620 #define AMDGPU_INFO_FW_ASD 0x0d
621 /* number of bytes moved for TTM migration */
622 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
623 /* the used VRAM size */
624 #define AMDGPU_INFO_VRAM_USAGE 0x10
625 /* the used GTT size */
626 #define AMDGPU_INFO_GTT_USAGE 0x11
627 /* Information about GDS, etc. resource configuration */
628 #define AMDGPU_INFO_GDS_CONFIG 0x13
629 /* Query information about VRAM and GTT domains */
630 #define AMDGPU_INFO_VRAM_GTT 0x14
631 /* Query information about register in MMR address space*/
632 #define AMDGPU_INFO_READ_MMR_REG 0x15
633 /* Query information about device: rev id, family, etc. */
634 #define AMDGPU_INFO_DEV_INFO 0x16
635 /* visible vram usage */
636 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
637 /* number of TTM buffer evictions */
638 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
639 /* Query memory about VRAM and GTT domains */
640 #define AMDGPU_INFO_MEMORY 0x19
641 /* Query vce clock table */
642 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
643 /* Query vbios related information */
644 #define AMDGPU_INFO_VBIOS 0x1B
645 /* Subquery id: Query vbios size */
646 #define AMDGPU_INFO_VBIOS_SIZE 0x1
647 /* Subquery id: Query vbios image */
648 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
649 /* Query UVD handles */
650 #define AMDGPU_INFO_NUM_HANDLES 0x1C
651 /* Query sensor related information */
652 #define AMDGPU_INFO_SENSOR 0x1D
653 /* Subquery id: Query GPU shader clock */
654 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
655 /* Subquery id: Query GPU memory clock */
656 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
657 /* Subquery id: Query GPU temperature */
658 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
659 /* Subquery id: Query GPU load */
660 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
661 /* Subquery id: Query average GPU power */
662 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
663 /* Subquery id: Query northbridge voltage */
664 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
665 /* Subquery id: Query graphics voltage */
666 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
667 /* Subquery id: Query GPU stable pstate shader clock */
668 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
669 /* Subquery id: Query GPU stable pstate memory clock */
670 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
671 /* Number of VRAM page faults on CPU access. */
672 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
673 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
675 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
676 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
677 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
678 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
680 struct drm_amdgpu_query_fw
{
681 /** AMDGPU_INFO_FW_* */
684 * Index of the IP if there are more IPs of
689 * Index of the engine. Whether this is used depends
690 * on the firmware type. (e.g. MEC, SDMA)
696 /* Input structure for the INFO ioctl */
697 struct drm_amdgpu_info
{
698 /* Where the return value will be stored */
699 __u64 return_pointer
;
700 /* The size of the return value. Just like "size" in "snprintf",
701 * it limits how many bytes the kernel can write. */
703 /* The query request id. */
713 /** AMDGPU_HW_IP_* */
716 * Index of the IP if there are more IPs of the same
717 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
724 /** number of registers to read */
727 /** For future use, no flags defined so far */
731 struct drm_amdgpu_query_fw query_fw
;
744 struct drm_amdgpu_info_gds
{
745 /** GDS GFX partition size */
746 __u32 gds_gfx_partition_size
;
747 /** GDS compute partition size */
748 __u32 compute_partition_size
;
749 /** total GDS memory size */
750 __u32 gds_total_size
;
751 /** GWS size per GFX partition */
752 __u32 gws_per_gfx_partition
;
753 /** GSW size per compute partition */
754 __u32 gws_per_compute_partition
;
755 /** OA size per GFX partition */
756 __u32 oa_per_gfx_partition
;
757 /** OA size per compute partition */
758 __u32 oa_per_compute_partition
;
762 struct drm_amdgpu_info_vram_gtt
{
764 __u64 vram_cpu_accessible_size
;
768 struct drm_amdgpu_heap_info
{
769 /** max. physical memory */
770 __u64 total_heap_size
;
772 /** Theoretical max. available memory in the given heap */
773 __u64 usable_heap_size
;
776 * Number of bytes allocated in the heap. This includes all processes
777 * and private allocations in the kernel. It changes when new buffers
778 * are allocated, freed, and moved. It cannot be larger than
784 * Theoretical possible max. size of buffer which
785 * could be allocated in the given heap
787 __u64 max_allocation
;
790 struct drm_amdgpu_memory_info
{
791 struct drm_amdgpu_heap_info vram
;
792 struct drm_amdgpu_heap_info cpu_accessible_vram
;
793 struct drm_amdgpu_heap_info gtt
;
796 struct drm_amdgpu_info_firmware
{
801 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
802 #define AMDGPU_VRAM_TYPE_GDDR1 1
803 #define AMDGPU_VRAM_TYPE_DDR2 2
804 #define AMDGPU_VRAM_TYPE_GDDR3 3
805 #define AMDGPU_VRAM_TYPE_GDDR4 4
806 #define AMDGPU_VRAM_TYPE_GDDR5 5
807 #define AMDGPU_VRAM_TYPE_HBM 6
808 #define AMDGPU_VRAM_TYPE_DDR3 7
809 #define AMDGPU_VRAM_TYPE_DDR4 8
811 struct drm_amdgpu_info_device
{
814 /** Internal chip revision: A0, A1, etc.) */
817 /** Revision id in PCI Config space */
820 __u32 num_shader_engines
;
821 __u32 num_shader_arrays_per_engine
;
823 __u32 gpu_counter_freq
;
824 __u64 max_engine_clock
;
825 __u64 max_memory_clock
;
827 __u32 cu_active_number
;
828 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
830 __u32 cu_bitmap
[4][4];
831 /** Render backend pipe mask. One render backend is CB+DB. */
832 __u32 enabled_rb_pipes_mask
;
834 __u32 num_hw_gfx_contexts
;
837 /** Starting virtual address for UMDs. */
838 __u64 virtual_address_offset
;
839 /** The maximum virtual address */
840 __u64 virtual_address_max
;
841 /** Required alignment of virtual addresses. */
842 __u32 virtual_address_alignment
;
843 /** Page table entry - fragment size */
844 __u32 pte_fragment_size
;
845 __u32 gart_page_size
;
846 /** constant engine ram size*/
848 /** video memory type info*/
850 /** video memory bit width*/
851 __u32 vram_bit_width
;
852 /* vce harvesting instance */
853 __u32 vce_harvest_config
;
854 /* gfx double offchip LDS buffers */
855 __u32 gc_double_offchip_lds_buf
;
856 /* NGG Primitive Buffer */
857 __u64 prim_buf_gpu_addr
;
858 /* NGG Position Buffer */
859 __u64 pos_buf_gpu_addr
;
860 /* NGG Control Sideband */
861 __u64 cntl_sb_buf_gpu_addr
;
862 /* NGG Parameter Cache */
863 __u64 param_buf_gpu_addr
;
866 __u32 cntl_sb_buf_size
;
867 __u32 param_buf_size
;
869 __u32 wave_front_size
;
870 /* shader visible vgprs*/
871 __u32 num_shader_visible_vgprs
;
872 /* CU per shader array*/
874 /* number of tcc blocks*/
875 __u32 num_tcc_blocks
;
876 /* gs vgt table depth*/
877 __u32 gs_vgt_table_depth
;
878 /* gs primitive buffer depth*/
879 __u32 gs_prim_buffer_depth
;
880 /* max gs wavefront per vgt*/
881 __u32 max_gs_waves_per_vgt
;
883 /* always on cu bitmap */
884 __u32 cu_ao_bitmap
[4][4];
885 /** Starting high virtual address for UMDs. */
886 __u64 high_va_offset
;
887 /** The maximum high virtual address */
891 struct drm_amdgpu_info_hw_ip
{
892 /** Version of h/w IP */
893 __u32 hw_ip_version_major
;
894 __u32 hw_ip_version_minor
;
896 __u64 capabilities_flags
;
897 /** command buffer address start alignment*/
898 __u32 ib_start_alignment
;
899 /** command buffer size alignment*/
900 __u32 ib_size_alignment
;
901 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
902 __u32 available_rings
;
906 struct drm_amdgpu_info_num_handles
{
907 /** Max handles as supported by firmware for UVD */
908 __u32 uvd_max_handles
;
909 /** Handles currently in use for UVD */
910 __u32 uvd_used_handles
;
913 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
915 struct drm_amdgpu_info_vce_clock_table_entry
{
925 struct drm_amdgpu_info_vce_clock_table
{
926 struct drm_amdgpu_info_vce_clock_table_entry entries
[AMDGPU_VCE_CLOCK_TABLE_ENTRIES
];
927 __u32 num_valid_entries
;
932 * Supported GPU families
934 #define AMDGPU_FAMILY_UNKNOWN 0
935 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
936 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
937 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
938 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
939 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
940 #define AMDGPU_FAMILY_AI 141 /* Vega10 */
941 #define AMDGPU_FAMILY_RV 142 /* Raven */
943 #if defined(__cplusplus)